From 54356c473e96a476844d3f823c5e3e77a0d996a4 Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Sat, 3 Jan 2026 00:12:10 -0700 Subject: [PATCH 01/12] [PyMTL output] Adding generated RTL and tb files. --- ...hMultiCgraRTL__975ce70dc1a0740a__pickled.v | 23492 ++++++++++++++++ ...t_multi_CGRA_fir_vector_global_reduce_tb.v | 138 + ...i_CGRA_fir_vector_global_reduce_tb.v.cases | 201 + 3 files changed, 23831 insertions(+) create mode 100644 multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a__pickled.v create mode 100644 multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v create mode 100644 multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v.cases diff --git a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a__pickled.v b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a__pickled.v new file mode 100644 index 00000000..aea6ccbe --- /dev/null +++ b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a__pickled.v @@ -0,0 +1,23492 @@ +//------------------------------------------------------------------------- +// MeshMultiCgraRTL__975ce70dc1a0740a.v +//------------------------------------------------------------------------- +// This file is generated by PyMTL SystemVerilog translation pass. + +// PyMTL BitStruct CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Definition +typedef struct packed { + logic [63:0] payload; + logic [0:0] predicate; + logic [0:0] bypass; + logic [0:0] delay; +} CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1; + +// PyMTL BitStruct CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Definition +typedef struct packed { + logic [6:0] operation; + logic [3:0][2:0] fu_in; + logic [7:0][2:0] routing_xbar_outport; + logic [7:0][1:0] fu_xbar_outport; + logic [2:0] vector_factor_power; + logic [0:0] is_last_ctrl; + logic [3:0][1:0] write_reg_from; + logic [3:0][3:0] write_reg_idx; + logic [3:0][0:0] read_reg_from; + logic [3:0][3:0] read_reg_idx; +} CGRAConfig_7_4_2_4_4_3__49d22cda396bec88; + +// PyMTL BitStruct MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Definition +typedef struct packed { + logic [4:0] cmd; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; + logic [6:0] data_addr; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 ctrl; + logic [3:0] ctrl_addr; +} MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a; + +// PyMTL BitStruct InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d Definition +typedef struct packed { + logic [1:0] src; + logic [1:0] dst; + logic [0:0] src_x; + logic [0:0] src_y; + logic [0:0] dst_x; + logic [0:0] dst_y; + logic [4:0] src_tile_id; + logic [4:0] dst_tile_id; + logic [2:0] remote_src_port; + logic [7:0] opaque; + logic [1:0] vc_id; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a payload; +} InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d; + +// PyMTL BitStruct IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 Definition +typedef struct packed { + logic [4:0] src; + logic [4:0] dst; + logic [1:0] src_cgra_id; + logic [1:0] dst_cgra_id; + logic [0:0] src_cgra_x; + logic [0:0] src_cgra_y; + logic [0:0] dst_cgra_x; + logic [0:0] dst_cgra_y; + logic [7:0] opaque; + logic [0:0] vc_id; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a payload; +} IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69; + +// PyMTL BitStruct ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad Definition +typedef struct packed { + logic [0:0] dst; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d inter_cgra_pkt; +} ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad; + +// PyMTL BitStruct MemAccessPacket_8_3_128__43c148781d2f2a57 Definition +typedef struct packed { + logic [2:0] src; + logic [1:0] dst; + logic [6:0] addr; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; + logic [1:0] src_cgra; + logic [4:0] src_tile; + logic [2:0] remote_src_port; + logic [0:0] streaming_rd; + logic [6:0] streaming_rd_stride; + logic [6:0] streaming_rd_end_addr; +} MemAccessPacket_8_3_128__43c148781d2f2a57; + +// PyMTL BitStruct MemAccessPacket_3_8_128__9f21b0bcdad2c061 Definition +typedef struct packed { + logic [1:0] src; + logic [2:0] dst; + logic [6:0] addr; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; + logic [1:0] src_cgra; + logic [4:0] src_tile; + logic [2:0] remote_src_port; + logic [0:0] streaming_rd; + logic [6:0] streaming_rd_stride; + logic [6:0] streaming_rd_end_addr; +} MemAccessPacket_3_8_128__9f21b0bcdad2c061; + +// PyMTL BitStruct MeshPosition_2x2__pos_x_1__pos_y_1 Definition +typedef struct packed { + logic [0:0] pos_x; + logic [0:0] pos_y; +} MeshPosition_2x2__pos_x_1__pos_y_1; + +// PyMTL Component NormalQueueCtrlRTL Definition +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueCtrlRTL__num_entries_2 +( + input logic [0:0] clk , + output logic [1:0] count , + output logic [0:0] raddr , + output logic [0:0] recv_rdy , + input logic [0:0] recv_val , + input logic [0:0] reset , + input logic [0:0] send_rdy , + output logic [0:0] send_val , + output logic [0:0] waddr , + output logic [0:0] wen +); + localparam logic [1:0] __const__num_entries_at__lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy = 2'd2; + localparam logic [1:0] __const__num_entries_at_up_reg = 2'd2; + logic [0:0] head; + logic [0:0] recv_xfer; + logic [0:0] send_xfer; + logic [0:0] tail; + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:121 + // s.recv_rdy //= lambda: s.count < num_entries + + always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy + recv_rdy = count < 2'( __const__num_entries_at__lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy ); + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:124 + // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy + + always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_xfer + recv_xfer = recv_val & recv_rdy; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:122 + // s.send_val //= lambda: s.count > 0 + + always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_send_val + send_val = count > 2'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:125 + // s.send_xfer //= lambda: s.send_val & s.send_rdy + + always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_send_xfer + send_xfer = send_val & send_rdy; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:127 + // @update_ff + // def up_reg(): + // + // if s.reset: + // s.head <<= 0 + // s.tail <<= 0 + // s.count <<= 0 + // + // else: + // if s.recv_xfer: + // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 + // + // if s.send_xfer: + // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 + // + // if s.recv_xfer & ~s.send_xfer: + // s.count <<= s.count + 1 + // elif ~s.recv_xfer & s.send_xfer: + // s.count <<= s.count - 1 + + always_ff @(posedge clk) begin : up_reg + if ( reset ) begin + head <= 1'd0; + tail <= 1'd0; + count <= 2'd0; + end + else begin + if ( recv_xfer ) begin + tail <= ( tail < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? tail + 1'd1 : 1'd0; + end + if ( send_xfer ) begin + head <= ( head < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? head + 1'd1 : 1'd0; + end + if ( recv_xfer & ( ~send_xfer ) ) begin + count <= count + 2'd1; + end + else if ( ( ~recv_xfer ) & send_xfer ) begin + count <= count - 2'd1; + end + end + end + + assign wen = recv_xfer; + assign waddr = tail; + assign raddr = head; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__a60a466e6e87778c +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__b5f6715511792c61 +( + input logic [0:0] clk , + input logic [0:0] raddr , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv_msg , + input logic [0:0] reset , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__a60a466e6e87778c rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__b5f6715511792c61 +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__raddr; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad dpath__recv_msg; + logic [0:0] dpath__reset; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__b5f6715511792c61 dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component InputUnitRTL Definition +// Full name: InputUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__QueueType_NormalQueueRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py + +module InputUnitRTL__d71c3d07db1f649e +( + input logic [0:0] clk , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queue + //------------------------------------------------------------- + + logic [0:0] queue__clk; + logic [1:0] queue__count; + logic [0:0] queue__reset; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad queue__recv__msg; + logic [0:0] queue__recv__rdy; + logic [0:0] queue__recv__val; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad queue__send__msg; + logic [0:0] queue__send__rdy; + logic [0:0] queue__send__val; + + NormalQueueRTL__b5f6715511792c61 queue + ( + .clk( queue__clk ), + .count( queue__count ), + .reset( queue__reset ), + .recv__msg( queue__recv__msg ), + .recv__rdy( queue__recv__rdy ), + .recv__val( queue__recv__val ), + .send__msg( queue__send__msg ), + .send__rdy( queue__send__rdy ), + .send__val( queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component queue + //------------------------------------------------------------- + + assign queue__clk = clk; + assign queue__reset = reset; + assign queue__recv__msg = recv__msg; + assign recv__rdy = queue__recv__rdy; + assign queue__recv__val = recv__val; + assign send__msg = queue__send__msg; + assign queue__send__rdy = send__rdy; + assign send__val = queue__send__val; + +endmodule + + +// PyMTL Component OutputUnitRTL Definition +// Full name: OutputUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__QueueType_None +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py + +module OutputUnitRTL__c199f9a52ff41678 +( + input logic [0:0] clk , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + assign send__msg = recv__msg; + assign recv__rdy = send__rdy; + assign send__val = recv__val; + +endmodule + + +// PyMTL Component XbarRouteUnitRTL Definition +// Full name: XbarRouteUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_outports_1 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py + +module XbarRouteUnitRTL__2110ed3935ab4c25 +( + input logic [0:0] clk , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg [0:0] , + input logic [0:0] send__rdy [0:0] , + output logic [0:0] send__val [0:0] +); + localparam logic [0:0] __const__num_outports_at_up_ru_routing = 1'd1; + logic [0:0] out_dir; + logic [0:0] send_val; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 + // @update + // def up_ru_recv_rdy(): + // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 + + always_comb begin : up_ru_recv_rdy + recv__rdy = send__rdy[out_dir] > 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 + // @update + // def up_ru_routing(): + // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) + // + // for i in range( num_outports ): + // s.send[i].val @= b1(0) + // + // if s.recv.val: + // s.send[ s.out_dir ].val @= b1(1) + + always_comb begin : up_ru_routing + out_dir = recv__msg.dst; + for ( int unsigned i = 1'd0; i < 1'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) + send__val[1'(i)] = 1'd0; + if ( recv__val ) begin + send__val[out_dir] = 1'd1; + end + end + + assign send__msg[0] = recv__msg; + assign send_val[0:0] = send__val[0]; + +endmodule + + +// PyMTL Component RegEnRst Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py + +module RegEnRst__Type_Bits6__reset_value_1 +( + input logic [0:0] clk , + input logic [0:0] en , + input logic [5:0] in_ , + output logic [5:0] out , + input logic [0:0] reset +); + localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 + // @update_ff + // def up_regenrst(): + // if s.reset: s.out <<= reset_value + // elif s.en: s.out <<= s.in_ + + always_ff @(posedge clk) begin : up_regenrst + if ( reset ) begin + out <= 6'( __const__reset_value_at_up_regenrst ); + end + else if ( en ) begin + out <= in_; + end + end + +endmodule + + +// PyMTL Component RoundRobinArbiterEn Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py + +module RoundRobinArbiterEn__nreqs_6 +( + input logic [0:0] clk , + input logic [0:0] en , + output logic [5:0] grants , + input logic [5:0] reqs , + input logic [0:0] reset +); + localparam logic [2:0] __const__nreqs_at_comb_reqs_int = 3'd6; + localparam logic [3:0] __const__nreqsX2_at_comb_reqs_int = 4'd12; + localparam logic [2:0] __const__nreqs_at_comb_grants = 3'd6; + localparam logic [2:0] __const__nreqs_at_comb_priority_int = 3'd6; + localparam logic [3:0] __const__nreqsX2_at_comb_priority_int = 4'd12; + localparam logic [3:0] __const__nreqsX2_at_comb_kills = 4'd12; + localparam logic [3:0] __const__nreqsX2_at_comb_grants_int = 4'd12; + logic [11:0] grants_int; + logic [12:0] kills; + logic [0:0] priority_en; + logic [11:0] priority_int; + logic [11:0] reqs_int; + //------------------------------------------------------------- + // Component priority_reg + //------------------------------------------------------------- + + logic [0:0] priority_reg__clk; + logic [0:0] priority_reg__en; + logic [5:0] priority_reg__in_; + logic [5:0] priority_reg__out; + logic [0:0] priority_reg__reset; + + RegEnRst__Type_Bits6__reset_value_1 priority_reg + ( + .clk( priority_reg__clk ), + .en( priority_reg__en ), + .in_( priority_reg__in_ ), + .out( priority_reg__out ), + .reset( priority_reg__reset ) + ); + + //------------------------------------------------------------- + // End of component priority_reg + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 + // @update + // def comb_grants(): + // for i in range( nreqs ): + // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] + + always_comb begin : comb_grants + for ( int unsigned i = 1'd0; i < 3'( __const__nreqs_at_comb_grants ); i += 1'd1 ) + grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 + // @update + // def comb_grants_int(): + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.grants_int[i] @= s.reqs_int[i] + // else: + // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] + + always_comb begin : comb_grants_int + for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + grants_int[4'(i)] = reqs_int[4'(i)]; + end + else + grants_int[4'(i)] = ( ~kills[4'(i)] ) & reqs_int[4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 + // @update + // def comb_kills(): + // s.kills[0] @= 1 + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.kills[i+1] @= s.reqs_int[i] + // else: + // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) + + always_comb begin : comb_kills + kills[4'd0] = 1'd1; + for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + kills[4'(i) + 4'd1] = reqs_int[4'(i)]; + end + else + kills[4'(i) + 4'd1] = kills[4'(i)] | ( ( ~kills[4'(i)] ) & reqs_int[4'(i)] ); + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 + // @update + // def comb_priority_en(): + // s.priority_en @= ( s.grants != 0 ) & s.en + + always_comb begin : comb_priority_en + priority_en = ( grants != 6'd0 ) & en; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 + // @update + // def comb_priority_int(): + // s.priority_int[ 0:nreqs ] @= s.priority_reg.out + // s.priority_int[nreqs:nreqsX2] @= 0 + + always_comb begin : comb_priority_int + priority_int[4'd5:4'd0] = priority_reg__out; + priority_int[4'd11:4'( __const__nreqs_at_comb_priority_int )] = 6'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 + // @update + // def comb_reqs_int(): + // s.reqs_int [ 0:nreqs ] @= s.reqs + // s.reqs_int [nreqs:nreqsX2] @= s.reqs + + always_comb begin : comb_reqs_int + reqs_int[4'd5:4'd0] = reqs; + reqs_int[4'd11:4'( __const__nreqs_at_comb_reqs_int )] = reqs; + end + + assign priority_reg__clk = clk; + assign priority_reg__reset = reset; + assign priority_reg__en = priority_en; + assign priority_reg__in_[5:1] = grants[4:0]; + assign priority_reg__in_[0:0] = grants[5:5]; + +endmodule + + +// PyMTL Component Encoder Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py + +module Encoder__in_nbits_6__out_nbits_3 +( + input logic [0:0] clk , + input logic [5:0] in_ , + output logic [2:0] out , + input logic [0:0] reset +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 + // @update + // def encode(): + // s.out @= 0 + // for i in range( s.in_nbits ): + // if s.in_[i]: + // s.out @= i + + always_comb begin : encode + out = 3'd0; + for ( int unsigned i = 1'd0; i < 3'd6; i += 1'd1 ) + if ( in_[3'(i)] ) begin + out = 3'(i); + end + end + +endmodule + + +// PyMTL Component Mux Definition +// Full name: Mux__Type_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__ninputs_6 +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__899292f481a8b227 +( + input logic [0:0] clk , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad in_ [0:5], + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad out , + input logic [0:0] reset , + input logic [2:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component SwitchUnitRTL Definition +// Full name: SwitchUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_inports_6 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py + +module SwitchUnitRTL__2dc7ee83ee1f485f +( + input logic [0:0] clk , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg [0:5] , + output logic [0:0] recv__rdy [0:5] , + input logic [0:0] recv__val [0:5] , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd6; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [5:0] arbiter__grants; + logic [5:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_6 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [5:0] encoder__in_; + logic [2:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_6__out_nbits_3 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad mux__in_ [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad mux__out; + logic [0:0] mux__reset; + logic [2:0] mux__sel; + + Mux__899292f481a8b227 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 + // @update + // def up_get_en(): + // for i in range( num_inports ): + // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) + + always_comb begin : up_get_en + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) + recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 + // @update + // def up_send_val(): + // s.send.val @= s.arbiter.grants > 0 + + always_comb begin : up_send_val + send__val = arbiter__grants > 6'd0; + end + + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign arbiter__en = 1'd1; + assign mux__clk = clk; + assign mux__reset = reset; + assign send__msg = mux__out; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign encoder__in_ = arbiter__grants; + assign mux__sel = encoder__out; + assign arbiter__reqs[0:0] = recv__val[0]; + assign mux__in_[0] = recv__msg[0]; + assign arbiter__reqs[1:1] = recv__val[1]; + assign mux__in_[1] = recv__msg[1]; + assign arbiter__reqs[2:2] = recv__val[2]; + assign mux__in_[2] = recv__msg[2]; + assign arbiter__reqs[3:3] = recv__val[3]; + assign mux__in_[3] = recv__msg[3]; + assign arbiter__reqs[4:4] = recv__val[4]; + assign mux__in_[4] = recv__msg[4]; + assign arbiter__reqs[5:5] = recv__val[5]; + assign mux__in_[5] = recv__msg[5]; + +endmodule + + +// PyMTL Component XbarRTL Definition +// Full name: XbarRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_inports_6__num_outports_1__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRTL.py + +module XbarRTL__51e7846dd37f4a41 +( + input logic [0:0] clk , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg [0:5] , + output logic [0:0] recv__rdy [0:5] , + input logic [0:0] recv__val [0:5] , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg [0:0] , + input logic [0:0] send__rdy [0:0] , + output logic [0:0] send__val [0:0] +); + //------------------------------------------------------------- + // Component input_units[0:5] + //------------------------------------------------------------- + + logic [0:0] input_units__clk [0:5]; + logic [0:0] input_units__reset [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad input_units__recv__msg [0:5]; + logic [0:0] input_units__recv__rdy [0:5]; + logic [0:0] input_units__recv__val [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad input_units__send__msg [0:5]; + logic [0:0] input_units__send__rdy [0:5]; + logic [0:0] input_units__send__val [0:5]; + + InputUnitRTL__d71c3d07db1f649e input_units__0 + ( + .clk( input_units__clk[0] ), + .reset( input_units__reset[0] ), + .recv__msg( input_units__recv__msg[0] ), + .recv__rdy( input_units__recv__rdy[0] ), + .recv__val( input_units__recv__val[0] ), + .send__msg( input_units__send__msg[0] ), + .send__rdy( input_units__send__rdy[0] ), + .send__val( input_units__send__val[0] ) + ); + + InputUnitRTL__d71c3d07db1f649e input_units__1 + ( + .clk( input_units__clk[1] ), + .reset( input_units__reset[1] ), + .recv__msg( input_units__recv__msg[1] ), + .recv__rdy( input_units__recv__rdy[1] ), + .recv__val( input_units__recv__val[1] ), + .send__msg( input_units__send__msg[1] ), + .send__rdy( input_units__send__rdy[1] ), + .send__val( input_units__send__val[1] ) + ); + + InputUnitRTL__d71c3d07db1f649e input_units__2 + ( + .clk( input_units__clk[2] ), + .reset( input_units__reset[2] ), + .recv__msg( input_units__recv__msg[2] ), + .recv__rdy( input_units__recv__rdy[2] ), + .recv__val( input_units__recv__val[2] ), + .send__msg( input_units__send__msg[2] ), + .send__rdy( input_units__send__rdy[2] ), + .send__val( input_units__send__val[2] ) + ); + + InputUnitRTL__d71c3d07db1f649e input_units__3 + ( + .clk( input_units__clk[3] ), + .reset( input_units__reset[3] ), + .recv__msg( input_units__recv__msg[3] ), + .recv__rdy( input_units__recv__rdy[3] ), + .recv__val( input_units__recv__val[3] ), + .send__msg( input_units__send__msg[3] ), + .send__rdy( input_units__send__rdy[3] ), + .send__val( input_units__send__val[3] ) + ); + + InputUnitRTL__d71c3d07db1f649e input_units__4 + ( + .clk( input_units__clk[4] ), + .reset( input_units__reset[4] ), + .recv__msg( input_units__recv__msg[4] ), + .recv__rdy( input_units__recv__rdy[4] ), + .recv__val( input_units__recv__val[4] ), + .send__msg( input_units__send__msg[4] ), + .send__rdy( input_units__send__rdy[4] ), + .send__val( input_units__send__val[4] ) + ); + + InputUnitRTL__d71c3d07db1f649e input_units__5 + ( + .clk( input_units__clk[5] ), + .reset( input_units__reset[5] ), + .recv__msg( input_units__recv__msg[5] ), + .recv__rdy( input_units__recv__rdy[5] ), + .recv__val( input_units__recv__val[5] ), + .send__msg( input_units__send__msg[5] ), + .send__rdy( input_units__send__rdy[5] ), + .send__val( input_units__send__val[5] ) + ); + + //------------------------------------------------------------- + // End of component input_units[0:5] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component output_units[0:0] + //------------------------------------------------------------- + + logic [0:0] output_units__clk [0:0]; + logic [0:0] output_units__reset [0:0]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad output_units__recv__msg [0:0]; + logic [0:0] output_units__recv__rdy [0:0]; + logic [0:0] output_units__recv__val [0:0]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad output_units__send__msg [0:0]; + logic [0:0] output_units__send__rdy [0:0]; + logic [0:0] output_units__send__val [0:0]; + + OutputUnitRTL__c199f9a52ff41678 output_units__0 + ( + .clk( output_units__clk[0] ), + .reset( output_units__reset[0] ), + .recv__msg( output_units__recv__msg[0] ), + .recv__rdy( output_units__recv__rdy[0] ), + .recv__val( output_units__recv__val[0] ), + .send__msg( output_units__send__msg[0] ), + .send__rdy( output_units__send__rdy[0] ), + .send__val( output_units__send__val[0] ) + ); + + //------------------------------------------------------------- + // End of component output_units[0:0] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component route_units[0:5] + //------------------------------------------------------------- + + logic [0:0] route_units__clk [0:5]; + logic [0:0] route_units__reset [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad route_units__recv__msg [0:5]; + logic [0:0] route_units__recv__rdy [0:5]; + logic [0:0] route_units__recv__val [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad route_units__send__msg [0:5][0:0]; + logic [0:0] route_units__send__rdy [0:5][0:0]; + logic [0:0] route_units__send__val [0:5][0:0]; + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__0 + ( + .clk( route_units__clk[0] ), + .reset( route_units__reset[0] ), + .recv__msg( route_units__recv__msg[0] ), + .recv__rdy( route_units__recv__rdy[0] ), + .recv__val( route_units__recv__val[0] ), + .send__msg( route_units__send__msg[0] ), + .send__rdy( route_units__send__rdy[0] ), + .send__val( route_units__send__val[0] ) + ); + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__1 + ( + .clk( route_units__clk[1] ), + .reset( route_units__reset[1] ), + .recv__msg( route_units__recv__msg[1] ), + .recv__rdy( route_units__recv__rdy[1] ), + .recv__val( route_units__recv__val[1] ), + .send__msg( route_units__send__msg[1] ), + .send__rdy( route_units__send__rdy[1] ), + .send__val( route_units__send__val[1] ) + ); + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__2 + ( + .clk( route_units__clk[2] ), + .reset( route_units__reset[2] ), + .recv__msg( route_units__recv__msg[2] ), + .recv__rdy( route_units__recv__rdy[2] ), + .recv__val( route_units__recv__val[2] ), + .send__msg( route_units__send__msg[2] ), + .send__rdy( route_units__send__rdy[2] ), + .send__val( route_units__send__val[2] ) + ); + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__3 + ( + .clk( route_units__clk[3] ), + .reset( route_units__reset[3] ), + .recv__msg( route_units__recv__msg[3] ), + .recv__rdy( route_units__recv__rdy[3] ), + .recv__val( route_units__recv__val[3] ), + .send__msg( route_units__send__msg[3] ), + .send__rdy( route_units__send__rdy[3] ), + .send__val( route_units__send__val[3] ) + ); + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__4 + ( + .clk( route_units__clk[4] ), + .reset( route_units__reset[4] ), + .recv__msg( route_units__recv__msg[4] ), + .recv__rdy( route_units__recv__rdy[4] ), + .recv__val( route_units__recv__val[4] ), + .send__msg( route_units__send__msg[4] ), + .send__rdy( route_units__send__rdy[4] ), + .send__val( route_units__send__val[4] ) + ); + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__5 + ( + .clk( route_units__clk[5] ), + .reset( route_units__reset[5] ), + .recv__msg( route_units__recv__msg[5] ), + .recv__rdy( route_units__recv__rdy[5] ), + .recv__val( route_units__recv__val[5] ), + .send__msg( route_units__send__msg[5] ), + .send__rdy( route_units__send__rdy[5] ), + .send__val( route_units__send__val[5] ) + ); + + //------------------------------------------------------------- + // End of component route_units[0:5] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component switch_units[0:0] + //------------------------------------------------------------- + + logic [0:0] switch_units__clk [0:0]; + logic [0:0] switch_units__reset [0:0]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad switch_units__recv__msg [0:0][0:5]; + logic [0:0] switch_units__recv__rdy [0:0][0:5]; + logic [0:0] switch_units__recv__val [0:0][0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad switch_units__send__msg [0:0]; + logic [0:0] switch_units__send__rdy [0:0]; + logic [0:0] switch_units__send__val [0:0]; + + SwitchUnitRTL__2dc7ee83ee1f485f switch_units__0 + ( + .clk( switch_units__clk[0] ), + .reset( switch_units__reset[0] ), + .recv__msg( switch_units__recv__msg[0] ), + .recv__rdy( switch_units__recv__rdy[0] ), + .recv__val( switch_units__recv__val[0] ), + .send__msg( switch_units__send__msg[0] ), + .send__rdy( switch_units__send__rdy[0] ), + .send__val( switch_units__send__val[0] ) + ); + + //------------------------------------------------------------- + // End of component switch_units[0:0] + //------------------------------------------------------------- + + assign input_units__clk[0] = clk; + assign input_units__reset[0] = reset; + assign input_units__clk[1] = clk; + assign input_units__reset[1] = reset; + assign input_units__clk[2] = clk; + assign input_units__reset[2] = reset; + assign input_units__clk[3] = clk; + assign input_units__reset[3] = reset; + assign input_units__clk[4] = clk; + assign input_units__reset[4] = reset; + assign input_units__clk[5] = clk; + assign input_units__reset[5] = reset; + assign route_units__clk[0] = clk; + assign route_units__reset[0] = reset; + assign route_units__clk[1] = clk; + assign route_units__reset[1] = reset; + assign route_units__clk[2] = clk; + assign route_units__reset[2] = reset; + assign route_units__clk[3] = clk; + assign route_units__reset[3] = reset; + assign route_units__clk[4] = clk; + assign route_units__reset[4] = reset; + assign route_units__clk[5] = clk; + assign route_units__reset[5] = reset; + assign switch_units__clk[0] = clk; + assign switch_units__reset[0] = reset; + assign output_units__clk[0] = clk; + assign output_units__reset[0] = reset; + assign input_units__recv__msg[0] = recv__msg[0]; + assign recv__rdy[0] = input_units__recv__rdy[0]; + assign input_units__recv__val[0] = recv__val[0]; + assign route_units__recv__msg[0] = input_units__send__msg[0]; + assign input_units__send__rdy[0] = route_units__recv__rdy[0]; + assign route_units__recv__val[0] = input_units__send__val[0]; + assign input_units__recv__msg[1] = recv__msg[1]; + assign recv__rdy[1] = input_units__recv__rdy[1]; + assign input_units__recv__val[1] = recv__val[1]; + assign route_units__recv__msg[1] = input_units__send__msg[1]; + assign input_units__send__rdy[1] = route_units__recv__rdy[1]; + assign route_units__recv__val[1] = input_units__send__val[1]; + assign input_units__recv__msg[2] = recv__msg[2]; + assign recv__rdy[2] = input_units__recv__rdy[2]; + assign input_units__recv__val[2] = recv__val[2]; + assign route_units__recv__msg[2] = input_units__send__msg[2]; + assign input_units__send__rdy[2] = route_units__recv__rdy[2]; + assign route_units__recv__val[2] = input_units__send__val[2]; + assign input_units__recv__msg[3] = recv__msg[3]; + assign recv__rdy[3] = input_units__recv__rdy[3]; + assign input_units__recv__val[3] = recv__val[3]; + assign route_units__recv__msg[3] = input_units__send__msg[3]; + assign input_units__send__rdy[3] = route_units__recv__rdy[3]; + assign route_units__recv__val[3] = input_units__send__val[3]; + assign input_units__recv__msg[4] = recv__msg[4]; + assign recv__rdy[4] = input_units__recv__rdy[4]; + assign input_units__recv__val[4] = recv__val[4]; + assign route_units__recv__msg[4] = input_units__send__msg[4]; + assign input_units__send__rdy[4] = route_units__recv__rdy[4]; + assign route_units__recv__val[4] = input_units__send__val[4]; + assign input_units__recv__msg[5] = recv__msg[5]; + assign recv__rdy[5] = input_units__recv__rdy[5]; + assign input_units__recv__val[5] = recv__val[5]; + assign route_units__recv__msg[5] = input_units__send__msg[5]; + assign input_units__send__rdy[5] = route_units__recv__rdy[5]; + assign route_units__recv__val[5] = input_units__send__val[5]; + assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; + assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; + assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; + assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; + assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; + assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; + assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; + assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; + assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; + assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; + assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; + assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; + assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; + assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; + assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; + assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; + assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; + assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; + assign output_units__recv__msg[0] = switch_units__send__msg[0]; + assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; + assign output_units__recv__val[0] = switch_units__send__val[0]; + assign send__msg[0] = output_units__send__msg[0]; + assign output_units__send__rdy[0] = send__rdy[0]; + assign send__val[0] = output_units__send__val[0]; + +endmodule + + +// PyMTL Component NormalQueueCtrlRTL Definition +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueCtrlRTL__num_entries_16 +( + input logic [0:0] clk , + output logic [4:0] count , + output logic [3:0] raddr , + output logic [0:0] recv_rdy , + input logic [0:0] recv_val , + input logic [0:0] reset , + input logic [0:0] send_rdy , + output logic [0:0] send_val , + output logic [3:0] waddr , + output logic [0:0] wen +); + localparam logic [4:0] __const__num_entries_at__lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy = 5'd16; + localparam logic [4:0] __const__num_entries_at_up_reg = 5'd16; + logic [3:0] head; + logic [0:0] recv_xfer; + logic [0:0] send_xfer; + logic [3:0] tail; + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:121 + // s.recv_rdy //= lambda: s.count < num_entries + + always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy + recv_rdy = count < 5'( __const__num_entries_at__lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy ); + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:124 + // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy + + always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_xfer + recv_xfer = recv_val & recv_rdy; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:122 + // s.send_val //= lambda: s.count > 0 + + always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_send_val + send_val = count > 5'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:125 + // s.send_xfer //= lambda: s.send_val & s.send_rdy + + always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_send_xfer + send_xfer = send_val & send_rdy; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:127 + // @update_ff + // def up_reg(): + // + // if s.reset: + // s.head <<= 0 + // s.tail <<= 0 + // s.count <<= 0 + // + // else: + // if s.recv_xfer: + // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 + // + // if s.send_xfer: + // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 + // + // if s.recv_xfer & ~s.send_xfer: + // s.count <<= s.count + 1 + // elif ~s.recv_xfer & s.send_xfer: + // s.count <<= s.count - 1 + + always_ff @(posedge clk) begin : up_reg + if ( reset ) begin + head <= 4'd0; + tail <= 4'd0; + count <= 5'd0; + end + else begin + if ( recv_xfer ) begin + tail <= ( tail < ( 4'( __const__num_entries_at_up_reg ) - 4'd1 ) ) ? tail + 4'd1 : 4'd0; + end + if ( send_xfer ) begin + head <= ( head < ( 4'( __const__num_entries_at_up_reg ) - 4'd1 ) ) ? head + 4'd1 : 4'd0; + end + if ( recv_xfer & ( ~send_xfer ) ) begin + count <= count + 5'd1; + end + else if ( ( ~recv_xfer ) & send_xfer ) begin + count <= count - 5'd1; + end + end + end + + assign wen = recv_xfer; + assign waddr = tail; + assign raddr = head; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__nregs_16__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__769ad531033521b3 +( + input logic [0:0] clk , + input logic [3:0] raddr [0:0], + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rdata [0:0], + input logic [0:0] reset , + input logic [3:0] waddr [0:0], + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d regs [0:15]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_16 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__a1611e9294891a09 +( + input logic [0:0] clk , + input logic [3:0] raddr , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_msg , + input logic [0:0] reset , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_msg , + input logic [3:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [3:0] rf__raddr [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [3:0] rf__waddr [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__769ad531033521b3 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_16 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__a1611e9294891a09 +( + input logic [0:0] clk , + output logic [4:0] count , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [4:0] ctrl__count; + logic [3:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [3:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_16 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [3:0] dpath__raddr; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__recv_msg; + logic [0:0] dpath__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__send_msg; + logic [3:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__a1611e9294891a09 dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component GlobalReduceUnitRTL Definition +// Full name: GlobalReduceUnitRTL__InterCgraPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d +// At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py + +module GlobalReduceUnitRTL__7c4d8effbf794a25 +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_count__msg , + output logic [0:0] recv_count__rdy , + input logic [0:0] recv_count__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_data__msg , + output logic [0:0] recv_data__rdy , + input logic [0:0] recv_data__val , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL = 5'd19; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 receiving_count; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reduce_add_value; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reduce_mul_value; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 sending_count; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 target_count; + //------------------------------------------------------------- + // Component queue + //------------------------------------------------------------- + + logic [0:0] queue__clk; + logic [4:0] queue__count; + logic [0:0] queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__recv__msg; + logic [0:0] queue__recv__rdy; + logic [0:0] queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__send__msg; + logic [0:0] queue__send__rdy; + logic [0:0] queue__send__val; + + NormalQueueRTL__a1611e9294891a09 queue + ( + .clk( queue__clk ), + .count( queue__count ), + .reset( queue__reset ), + .recv__msg( queue__recv__msg ), + .recv__rdy( queue__recv__rdy ), + .recv__val( queue__recv__val ), + .send__msg( queue__send__msg ), + .send__rdy( queue__send__rdy ), + .send__val( queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component queue + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:45 + // @update + // def set_recv_rdy(): + // s.recv_data.rdy @= 0 + // s.queue.recv.val @= 0 + // s.queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // if s.target_count.payload > s.receiving_count.payload: + // s.recv_data.rdy @= s.queue.recv.rdy + // s.queue.recv.msg @= s.recv_data.msg + // s.queue.recv.val @= s.recv_data.val + + always_comb begin : set_recv_rdy + recv_data__rdy = 1'd0; + queue__recv__val = 1'd0; + queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + if ( target_count.payload > receiving_count.payload ) begin + recv_data__rdy = queue__recv__rdy; + queue__recv__msg = recv_data__msg; + queue__recv__val = recv_data__val; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:74 + // @update + // def update_send(): + // s.send.msg @= ControllerXbarPktType(0, 0) + // s.send.val @= 0 + // s.queue.send.rdy @= 0 + // if (s.target_count.payload > 0) & (s.receiving_count.payload == s.target_count.payload): + // # Updates the cmd type, result value, and src/dst. + // if s.queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: + // s.send.msg.inter_cgra_pkt.payload.cmd @= CMD_GLOBAL_REDUCE_ADD_RESPONSE + // s.send.msg.inter_cgra_pkt.payload.data @= s.reduce_add_value + // elif s.queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL: + // s.send.msg.inter_cgra_pkt.payload.cmd @= CMD_GLOBAL_REDUCE_MUL_RESPONSE + // s.send.msg.inter_cgra_pkt.payload.data @= s.reduce_mul_value + // s.send.msg.inter_cgra_pkt.src @= s.queue.send.msg.dst + // s.send.msg.inter_cgra_pkt.dst @= s.queue.send.msg.src + // s.send.msg.inter_cgra_pkt.src_x @= s.queue.send.msg.dst_x + // s.send.msg.inter_cgra_pkt.src_y @= s.queue.send.msg.dst_y + // s.send.msg.inter_cgra_pkt.dst_x @= s.queue.send.msg.src_x + // s.send.msg.inter_cgra_pkt.dst_y @= s.queue.send.msg.src_y + // s.send.msg.inter_cgra_pkt.src_tile_id @= s.queue.send.msg.dst_tile_id + // s.send.msg.inter_cgra_pkt.dst_tile_id @= s.queue.send.msg.src_tile_id + // s.queue.send.rdy @= s.send.rdy + // s.send.val @= s.queue.send.val + + always_comb begin : update_send + send__msg = { 1'd0, 221'd0 }; + send__val = 1'd0; + queue__send__rdy = 1'd0; + if ( ( target_count.payload > 64'd0 ) & ( receiving_count.payload == target_count.payload ) ) begin + if ( queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin + send__msg.inter_cgra_pkt.payload.cmd = 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ); + send__msg.inter_cgra_pkt.payload.data = reduce_add_value; + end + else if ( queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL ) ) begin + send__msg.inter_cgra_pkt.payload.cmd = 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ); + send__msg.inter_cgra_pkt.payload.data = reduce_mul_value; + end + send__msg.inter_cgra_pkt.src = queue__send__msg.dst; + send__msg.inter_cgra_pkt.dst = queue__send__msg.src; + send__msg.inter_cgra_pkt.src_x = queue__send__msg.dst_x; + send__msg.inter_cgra_pkt.src_y = queue__send__msg.dst_y; + send__msg.inter_cgra_pkt.dst_x = queue__send__msg.src_x; + send__msg.inter_cgra_pkt.dst_y = queue__send__msg.src_y; + send__msg.inter_cgra_pkt.src_tile_id = queue__send__msg.dst_tile_id; + send__msg.inter_cgra_pkt.dst_tile_id = queue__send__msg.src_tile_id; + queue__send__rdy = send__rdy; + send__val = queue__send__val; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:98 + // @update_ff + // def accumulate_value(): + // if s.reset | (s.sending_count == s.target_count): + // s.reduce_add_value <<= DataType(0, 0, 0, 0) + // s.reduce_mul_value <<= DataType(1, 0, 0, 0) + // else: + // if s.recv_data.val & \ + // s.recv_data.rdy: + // if s.recv_data.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: + // s.reduce_add_value <<= DataType(s.reduce_add_value.payload + s.recv_data.msg.payload.data.payload, + // s.recv_data.msg.payload.data.predicate, + // 0, + // 0) + // elif s.recv_data.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL: + // s.reduce_mul_value <<= DataType(s.reduce_mul_value.payload * s.recv_data.msg.payload.data.payload, + // s.recv_data.msg.payload.data.predicate, + // 0, + // 0) + + always_ff @(posedge clk) begin : accumulate_value + if ( reset | ( sending_count == target_count ) ) begin + reduce_add_value <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + reduce_mul_value <= { 64'd1, 1'd0, 1'd0, 1'd0 }; + end + else if ( recv_data__val & recv_data__rdy ) begin + if ( recv_data__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin + reduce_add_value <= { reduce_add_value.payload + recv_data__msg.payload.data.payload, recv_data__msg.payload.data.predicate, 1'd0, 1'd0 }; + end + else if ( recv_data__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL ) ) begin + reduce_mul_value <= { reduce_mul_value.payload * recv_data__msg.payload.data.payload, recv_data__msg.payload.data.predicate, 1'd0, 1'd0 }; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:55 + // @update_ff + // def update_count(): + // if s.reset: + // s.target_count <<= DataType(0, 0, 0, 0) + // s.receiving_count <<= DataType(0, 0, 0, 0) + // s.sending_count <<= DataType(0, 0, 0, 0) + // else: + // if s.recv_count.val & s.recv_count.rdy: + // s.target_count <<= DataType(s.recv_count.msg.payload.data.payload, 0, 0, 0) + // if s.recv_data.val & s.recv_data.rdy: + // s.receiving_count <<= DataType(s.receiving_count.payload + 1, 0, 0, 0) + // if s.send.rdy & s.send.val: + // s.sending_count <<= DataType(s.sending_count.payload + 1, 0, 0, 0) + // elif (s.sending_count == s.receiving_count) & \ + // (s.sending_count == s.target_count) & \ + // (s.target_count.payload > 0): + // s.sending_count <<= DataType(0, 0, 0, 0) + // s.receiving_count <<= DataType(0, 0, 0, 0) + + always_ff @(posedge clk) begin : update_count + if ( reset ) begin + target_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + receiving_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + sending_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + else begin + if ( recv_count__val & recv_count__rdy ) begin + target_count <= { recv_count__msg.payload.data.payload, 1'd0, 1'd0, 1'd0 }; + end + if ( recv_data__val & recv_data__rdy ) begin + receiving_count <= { receiving_count.payload + 64'd1, 1'd0, 1'd0, 1'd0 }; + end + if ( send__rdy & send__val ) begin + sending_count <= { sending_count.payload + 64'd1, 1'd0, 1'd0, 1'd0 }; + end + else if ( ( ( sending_count == receiving_count ) & ( sending_count == target_count ) ) & ( target_count.payload > 64'd0 ) ) begin + sending_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + receiving_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + end + end + + assign queue__clk = clk; + assign queue__reset = reset; + assign recv_count__rdy = 1'd1; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__80167091524f71e4 +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__a1c7a5a18a302c36 +( + input logic [0:0] clk , + input logic [0:0] raddr , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_msg , + input logic [0:0] reset , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__80167091524f71e4 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__a1c7a5a18a302c36 +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__raddr; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__recv_msg; + logic [0:0] dpath__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__a1c7a5a18a302c36 dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__96d83eaf701da4cb +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__c7280ffb0786127e +( + input logic [0:0] clk , + input logic [0:0] raddr , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_msg , + input logic [0:0] reset , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__96d83eaf701da4cb rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__c7280ffb0786127e +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__raddr; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__recv_msg; + logic [0:0] dpath__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__c7280ffb0786127e dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component ChannelRTL Definition +// Full name: ChannelRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_NormalQueueRTL__latency_1 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py + +module ChannelRTL__551ecec02ed96ac9 +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queues[0:0] + //------------------------------------------------------------- + + logic [0:0] queues__clk [0:0]; + logic [1:0] queues__count [0:0]; + logic [0:0] queues__reset [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queues__recv__msg [0:0]; + logic [0:0] queues__recv__rdy [0:0]; + logic [0:0] queues__recv__val [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queues__send__msg [0:0]; + logic [0:0] queues__send__rdy [0:0]; + logic [0:0] queues__send__val [0:0]; + + NormalQueueRTL__c7280ffb0786127e queues__0 + ( + .clk( queues__clk[0] ), + .count( queues__count[0] ), + .reset( queues__reset[0] ), + .recv__msg( queues__recv__msg[0] ), + .recv__rdy( queues__recv__rdy[0] ), + .recv__val( queues__recv__val[0] ), + .send__msg( queues__send__msg[0] ), + .send__rdy( queues__send__rdy[0] ), + .send__val( queues__send__val[0] ) + ); + + //------------------------------------------------------------- + // End of component queues[0:0] + //------------------------------------------------------------- + + assign queues__clk[0] = clk; + assign queues__reset[0] = reset; + assign queues__recv__msg[0] = recv__msg; + assign recv__rdy = queues__recv__rdy[0]; + assign queues__recv__val[0] = recv__val; + assign send__msg = queues__send__msg[0]; + assign queues__send__rdy[0] = send__rdy; + assign send__val = queues__send__val[0]; + +endmodule + + +// PyMTL Component ControllerRTL Definition +// Full name: ControllerRTL__InterCgraPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__multi_cgra_rows_2__multi_cgra_columns_2__num_tiles_16__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)} +// At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py + +module ControllerRTL__e06602ce343fdc8d +( + input logic [1:0] cgra_id , + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , + output logic [0:0] recv_from_cpu_pkt__rdy , + input logic [0:0] recv_from_cpu_pkt__val , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_ctrl_ring_pkt__msg , + output logic [0:0] recv_from_ctrl_ring_pkt__rdy , + input logic [0:0] recv_from_ctrl_ring_pkt__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_inter_cgra_noc__msg , + output logic [0:0] recv_from_inter_cgra_noc__rdy , + input logic [0:0] recv_from_inter_cgra_noc__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt__msg , + output logic [0:0] recv_from_tile_load_request_pkt__rdy , + input logic [0:0] recv_from_tile_load_request_pkt__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt__msg , + output logic [0:0] recv_from_tile_load_response_pkt__rdy , + input logic [0:0] recv_from_tile_load_response_pkt__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt__msg , + output logic [0:0] recv_from_tile_store_request_pkt__rdy , + input logic [0:0] recv_from_tile_store_request_pkt__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , + input logic [0:0] send_to_cpu_pkt__rdy , + output logic [0:0] send_to_cpu_pkt__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_ctrl_ring_pkt__msg , + input logic [0:0] send_to_ctrl_ring_pkt__rdy , + output logic [0:0] send_to_ctrl_ring_pkt__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_inter_cgra_noc__msg , + input logic [0:0] send_to_inter_cgra_noc__rdy , + output logic [0:0] send_to_inter_cgra_noc__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request__msg , + input logic [0:0] send_to_mem_load_request__rdy , + output logic [0:0] send_to_mem_load_request__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request__msg , + input logic [0:0] send_to_mem_store_request__rdy , + output logic [0:0] send_to_mem_store_request__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response__msg , + input logic [0:0] send_to_tile_load_response__rdy , + output logic [0:0] send_to_tile_load_response__val +); + localparam logic [2:0] __const__CONTROLLER_CROSSBAR_INPORTS = 3'd6; + localparam logic [4:0] __const__num_tiles_at_update_received_msg = 5'd16; + localparam logic [3:0] __const__CMD_LOAD_REQUEST = 4'd10; + localparam logic [3:0] __const__CMD_STORE_REQUEST = 4'd12; + localparam logic [3:0] __const__CMD_LOAD_RESPONSE = 4'd11; + localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_COUNT = 5'd17; + localparam logic [1:0] __const__CMD_CONFIG = 2'd3; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; + localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; + localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; + localparam logic [3:0] __const__CMD_CONFIG_CTRL_LOWER_BOUND = 4'd9; + localparam logic [3:0] __const__CMD_CONST = 4'd13; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; + localparam logic [0:0] __const__CMD_PAUSE = 1'd1; + localparam logic [4:0] __const__CMD_PRESERVE = 5'd22; + localparam logic [3:0] __const__CMD_RESUME = 4'd15; + localparam logic [4:0] __const__CMD_RECORD_PHI_ADDR = 5'd16; + localparam logic [1:0] __const__CMD_TERMINATE = 2'd2; + localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; + localparam logic [2:0] __const__addr_offset_nbits_at_capture_addr_dst_id = 3'd5; + logic [1:0] addr2controller_lut [0:3]; + logic [1:0] addr_dst_id; + logic [0:0] idTo2d_x_lut [0:3]; + logic [0:0] idTo2d_y_lut [0:3]; + //------------------------------------------------------------- + // Component crossbar + //------------------------------------------------------------- + + logic [0:0] crossbar__clk; + logic [0:0] crossbar__reset; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad crossbar__recv__msg [0:5]; + logic [0:0] crossbar__recv__rdy [0:5]; + logic [0:0] crossbar__recv__val [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad crossbar__send__msg [0:0]; + logic [0:0] crossbar__send__rdy [0:0]; + logic [0:0] crossbar__send__val [0:0]; + + XbarRTL__51e7846dd37f4a41 crossbar + ( + .clk( crossbar__clk ), + .reset( crossbar__reset ), + .recv__msg( crossbar__recv__msg ), + .recv__rdy( crossbar__recv__rdy ), + .recv__val( crossbar__recv__val ), + .send__msg( crossbar__send__msg ), + .send__rdy( crossbar__send__rdy ), + .send__val( crossbar__send__val ) + ); + + //------------------------------------------------------------- + // End of component crossbar + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component global_reduce_unit + //------------------------------------------------------------- + + logic [0:0] global_reduce_unit__clk; + logic [0:0] global_reduce_unit__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d global_reduce_unit__recv_count__msg; + logic [0:0] global_reduce_unit__recv_count__rdy; + logic [0:0] global_reduce_unit__recv_count__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d global_reduce_unit__recv_data__msg; + logic [0:0] global_reduce_unit__recv_data__rdy; + logic [0:0] global_reduce_unit__recv_data__val; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad global_reduce_unit__send__msg; + logic [0:0] global_reduce_unit__send__rdy; + logic [0:0] global_reduce_unit__send__val; + + GlobalReduceUnitRTL__7c4d8effbf794a25 global_reduce_unit + ( + .clk( global_reduce_unit__clk ), + .reset( global_reduce_unit__reset ), + .recv_count__msg( global_reduce_unit__recv_count__msg ), + .recv_count__rdy( global_reduce_unit__recv_count__rdy ), + .recv_count__val( global_reduce_unit__recv_count__val ), + .recv_data__msg( global_reduce_unit__recv_data__msg ), + .recv_data__rdy( global_reduce_unit__recv_data__rdy ), + .recv_data__val( global_reduce_unit__recv_data__val ), + .send__msg( global_reduce_unit__send__msg ), + .send__rdy( global_reduce_unit__send__rdy ), + .send__val( global_reduce_unit__send__val ) + ); + + //------------------------------------------------------------- + // End of component global_reduce_unit + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component recv_from_cpu_pkt_queue + //------------------------------------------------------------- + + logic [0:0] recv_from_cpu_pkt_queue__clk; + logic [1:0] recv_from_cpu_pkt_queue__count; + logic [0:0] recv_from_cpu_pkt_queue__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt_queue__recv__msg; + logic [0:0] recv_from_cpu_pkt_queue__recv__rdy; + logic [0:0] recv_from_cpu_pkt_queue__recv__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt_queue__send__msg; + logic [0:0] recv_from_cpu_pkt_queue__send__rdy; + logic [0:0] recv_from_cpu_pkt_queue__send__val; + + NormalQueueRTL__a1c7a5a18a302c36 recv_from_cpu_pkt_queue + ( + .clk( recv_from_cpu_pkt_queue__clk ), + .count( recv_from_cpu_pkt_queue__count ), + .reset( recv_from_cpu_pkt_queue__reset ), + .recv__msg( recv_from_cpu_pkt_queue__recv__msg ), + .recv__rdy( recv_from_cpu_pkt_queue__recv__rdy ), + .recv__val( recv_from_cpu_pkt_queue__recv__val ), + .send__msg( recv_from_cpu_pkt_queue__send__msg ), + .send__rdy( recv_from_cpu_pkt_queue__send__rdy ), + .send__val( recv_from_cpu_pkt_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_from_cpu_pkt_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component recv_from_tile_load_request_pkt_queue + //------------------------------------------------------------- + + logic [0:0] recv_from_tile_load_request_pkt_queue__clk; + logic [0:0] recv_from_tile_load_request_pkt_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt_queue__recv__msg; + logic [0:0] recv_from_tile_load_request_pkt_queue__recv__rdy; + logic [0:0] recv_from_tile_load_request_pkt_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt_queue__send__msg; + logic [0:0] recv_from_tile_load_request_pkt_queue__send__rdy; + logic [0:0] recv_from_tile_load_request_pkt_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 recv_from_tile_load_request_pkt_queue + ( + .clk( recv_from_tile_load_request_pkt_queue__clk ), + .reset( recv_from_tile_load_request_pkt_queue__reset ), + .recv__msg( recv_from_tile_load_request_pkt_queue__recv__msg ), + .recv__rdy( recv_from_tile_load_request_pkt_queue__recv__rdy ), + .recv__val( recv_from_tile_load_request_pkt_queue__recv__val ), + .send__msg( recv_from_tile_load_request_pkt_queue__send__msg ), + .send__rdy( recv_from_tile_load_request_pkt_queue__send__rdy ), + .send__val( recv_from_tile_load_request_pkt_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_from_tile_load_request_pkt_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component recv_from_tile_load_response_pkt_queue + //------------------------------------------------------------- + + logic [0:0] recv_from_tile_load_response_pkt_queue__clk; + logic [0:0] recv_from_tile_load_response_pkt_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt_queue__recv__msg; + logic [0:0] recv_from_tile_load_response_pkt_queue__recv__rdy; + logic [0:0] recv_from_tile_load_response_pkt_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt_queue__send__msg; + logic [0:0] recv_from_tile_load_response_pkt_queue__send__rdy; + logic [0:0] recv_from_tile_load_response_pkt_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 recv_from_tile_load_response_pkt_queue + ( + .clk( recv_from_tile_load_response_pkt_queue__clk ), + .reset( recv_from_tile_load_response_pkt_queue__reset ), + .recv__msg( recv_from_tile_load_response_pkt_queue__recv__msg ), + .recv__rdy( recv_from_tile_load_response_pkt_queue__recv__rdy ), + .recv__val( recv_from_tile_load_response_pkt_queue__recv__val ), + .send__msg( recv_from_tile_load_response_pkt_queue__send__msg ), + .send__rdy( recv_from_tile_load_response_pkt_queue__send__rdy ), + .send__val( recv_from_tile_load_response_pkt_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_from_tile_load_response_pkt_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component recv_from_tile_store_request_pkt_queue + //------------------------------------------------------------- + + logic [0:0] recv_from_tile_store_request_pkt_queue__clk; + logic [0:0] recv_from_tile_store_request_pkt_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt_queue__recv__msg; + logic [0:0] recv_from_tile_store_request_pkt_queue__recv__rdy; + logic [0:0] recv_from_tile_store_request_pkt_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt_queue__send__msg; + logic [0:0] recv_from_tile_store_request_pkt_queue__send__rdy; + logic [0:0] recv_from_tile_store_request_pkt_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 recv_from_tile_store_request_pkt_queue + ( + .clk( recv_from_tile_store_request_pkt_queue__clk ), + .reset( recv_from_tile_store_request_pkt_queue__reset ), + .recv__msg( recv_from_tile_store_request_pkt_queue__recv__msg ), + .recv__rdy( recv_from_tile_store_request_pkt_queue__recv__rdy ), + .recv__val( recv_from_tile_store_request_pkt_queue__recv__val ), + .send__msg( recv_from_tile_store_request_pkt_queue__send__msg ), + .send__rdy( recv_from_tile_store_request_pkt_queue__send__rdy ), + .send__val( recv_from_tile_store_request_pkt_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_from_tile_store_request_pkt_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component send_to_cpu_pkt_queue + //------------------------------------------------------------- + + logic [0:0] send_to_cpu_pkt_queue__clk; + logic [1:0] send_to_cpu_pkt_queue__count; + logic [0:0] send_to_cpu_pkt_queue__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt_queue__recv__msg; + logic [0:0] send_to_cpu_pkt_queue__recv__rdy; + logic [0:0] send_to_cpu_pkt_queue__recv__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt_queue__send__msg; + logic [0:0] send_to_cpu_pkt_queue__send__rdy; + logic [0:0] send_to_cpu_pkt_queue__send__val; + + NormalQueueRTL__a1c7a5a18a302c36 send_to_cpu_pkt_queue + ( + .clk( send_to_cpu_pkt_queue__clk ), + .count( send_to_cpu_pkt_queue__count ), + .reset( send_to_cpu_pkt_queue__reset ), + .recv__msg( send_to_cpu_pkt_queue__recv__msg ), + .recv__rdy( send_to_cpu_pkt_queue__recv__rdy ), + .recv__val( send_to_cpu_pkt_queue__recv__val ), + .send__msg( send_to_cpu_pkt_queue__send__msg ), + .send__rdy( send_to_cpu_pkt_queue__send__rdy ), + .send__val( send_to_cpu_pkt_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component send_to_cpu_pkt_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component send_to_mem_load_request_queue + //------------------------------------------------------------- + + logic [0:0] send_to_mem_load_request_queue__clk; + logic [0:0] send_to_mem_load_request_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request_queue__recv__msg; + logic [0:0] send_to_mem_load_request_queue__recv__rdy; + logic [0:0] send_to_mem_load_request_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request_queue__send__msg; + logic [0:0] send_to_mem_load_request_queue__send__rdy; + logic [0:0] send_to_mem_load_request_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 send_to_mem_load_request_queue + ( + .clk( send_to_mem_load_request_queue__clk ), + .reset( send_to_mem_load_request_queue__reset ), + .recv__msg( send_to_mem_load_request_queue__recv__msg ), + .recv__rdy( send_to_mem_load_request_queue__recv__rdy ), + .recv__val( send_to_mem_load_request_queue__recv__val ), + .send__msg( send_to_mem_load_request_queue__send__msg ), + .send__rdy( send_to_mem_load_request_queue__send__rdy ), + .send__val( send_to_mem_load_request_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component send_to_mem_load_request_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component send_to_mem_store_request_queue + //------------------------------------------------------------- + + logic [0:0] send_to_mem_store_request_queue__clk; + logic [0:0] send_to_mem_store_request_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request_queue__recv__msg; + logic [0:0] send_to_mem_store_request_queue__recv__rdy; + logic [0:0] send_to_mem_store_request_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request_queue__send__msg; + logic [0:0] send_to_mem_store_request_queue__send__rdy; + logic [0:0] send_to_mem_store_request_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 send_to_mem_store_request_queue + ( + .clk( send_to_mem_store_request_queue__clk ), + .reset( send_to_mem_store_request_queue__reset ), + .recv__msg( send_to_mem_store_request_queue__recv__msg ), + .recv__rdy( send_to_mem_store_request_queue__recv__rdy ), + .recv__val( send_to_mem_store_request_queue__recv__val ), + .send__msg( send_to_mem_store_request_queue__send__msg ), + .send__rdy( send_to_mem_store_request_queue__send__rdy ), + .send__val( send_to_mem_store_request_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component send_to_mem_store_request_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component send_to_tile_load_response_queue + //------------------------------------------------------------- + + logic [0:0] send_to_tile_load_response_queue__clk; + logic [0:0] send_to_tile_load_response_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response_queue__recv__msg; + logic [0:0] send_to_tile_load_response_queue__recv__rdy; + logic [0:0] send_to_tile_load_response_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response_queue__send__msg; + logic [0:0] send_to_tile_load_response_queue__send__rdy; + logic [0:0] send_to_tile_load_response_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 send_to_tile_load_response_queue + ( + .clk( send_to_tile_load_response_queue__clk ), + .reset( send_to_tile_load_response_queue__reset ), + .recv__msg( send_to_tile_load_response_queue__recv__msg ), + .recv__rdy( send_to_tile_load_response_queue__recv__rdy ), + .recv__val( send_to_tile_load_response_queue__recv__val ), + .send__msg( send_to_tile_load_response_queue__send__msg ), + .send__rdy( send_to_tile_load_response_queue__send__rdy ), + .send__val( send_to_tile_load_response_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component send_to_tile_load_response_queue + //------------------------------------------------------------- + logic [0:0] __tmpvar__update_received_msg_kLoadRequestInportIdx; + logic [0:0] __tmpvar__update_received_msg_kLoadResponseInportIdx; + logic [1:0] __tmpvar__update_received_msg_kStoreRequestInportIdx; + logic [1:0] __tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx; + logic [2:0] __tmpvar__update_received_msg_kFromInterTileRingIdx; + logic [2:0] __tmpvar__update_received_msg_kFromReduceUnitIdx; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d __tmpvar__update_received_msg_received_pkt; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:362 + // @update + // def capture_addr_dst_id(): + // s.addr_dst_id @= s.addr2controller_lut[trunc(s.crossbar.send[0].msg.inter_cgra_pkt.payload.data_addr >> addr_offset_nbits, CgraIdType)] + + always_comb begin : capture_addr_dst_id + addr_dst_id = addr2controller_lut[2'(crossbar__send__msg[1'd0].inter_cgra_pkt.payload.data_addr >> 3'( __const__addr_offset_nbits_at_capture_addr_dst_id ))]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:141 + // @update + // def update_received_msg(): + // kLoadRequestInportIdx = 0 + // kLoadResponseInportIdx = 1 + // kStoreRequestInportIdx = 2 + // kFromCpuCtrlAndDataIdx = 3 + // kFromInterTileRingIdx = 4 + // kFromReduceUnitIdx = 5 + // + // s.send_to_cpu_pkt_queue.recv.val @= 0 + // s.send_to_cpu_pkt_queue.recv.msg @= IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.recv_from_ctrl_ring_pkt.rdy @= 0 + // + // for i in range(CONTROLLER_CROSSBAR_INPORTS): + // s.crossbar.recv[i].val @= 0 + // s.crossbar.recv[i].msg @= ControllerXbarPktType(0, 0) + // + // # For the command signal from inter-tile/intra-cgra control ring. + // s.crossbar.recv[kFromInterTileRingIdx].val @= s.recv_from_ctrl_ring_pkt.val + // s.recv_from_ctrl_ring_pkt.rdy @= s.crossbar.recv[kFromInterTileRingIdx].rdy + // s.crossbar.recv[kFromInterTileRingIdx].msg @= \ + // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) + // InterCgraPktType(s.cgra_id, + // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_id, + // s.idTo2d_x_lut[s.cgra_id], # src_x + // s.idTo2d_y_lut[s.cgra_id], # src_y + // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_x, # dst_x + // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_y, # dst_y + // s.recv_from_ctrl_ring_pkt.msg.src, # src_tile_id + // s.recv_from_ctrl_ring_pkt.msg.dst, # dst_tile_id + // 0, # remote_src_port, only used for inter-cgra remote load request/response. + // 0, # opaque + // 0, # vc_id. No need to specify vc_id for self produce-consume pkt thanks to the additional VC buffer. + // s.recv_from_ctrl_ring_pkt.msg.payload)) + // + // # For the load request from local tiles. + // s.crossbar.recv[kLoadRequestInportIdx].val @= s.recv_from_tile_load_request_pkt_queue.send.val + // s.recv_from_tile_load_request_pkt_queue.send.rdy @= s.crossbar.recv[kLoadRequestInportIdx].rdy + // s.crossbar.recv[kLoadRequestInportIdx].msg @= \ + // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) + // s.recv_from_tile_load_request_pkt_queue.send.msg) + // + // # For the store request from local tiles. + // s.crossbar.recv[kStoreRequestInportIdx].val @= s.recv_from_tile_store_request_pkt_queue.send.val + // s.recv_from_tile_store_request_pkt_queue.send.rdy @= s.crossbar.recv[kStoreRequestInportIdx].rdy + // s.crossbar.recv[kStoreRequestInportIdx].msg @= \ + // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) + // s.recv_from_tile_store_request_pkt_queue.send.msg) + // + // # For the load response (i.e., the data towards other) from local memory. + // s.crossbar.recv[kLoadResponseInportIdx].val @= \ + // s.recv_from_tile_load_response_pkt_queue.send.val + // s.recv_from_tile_load_response_pkt_queue.send.rdy @= s.crossbar.recv[kLoadResponseInportIdx].rdy + // s.crossbar.recv[kLoadResponseInportIdx].msg @= \ + // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) + // s.recv_from_tile_load_response_pkt_queue.send.msg) + // + // # For the load response (i.e., the data towards other) from local memory. + // s.crossbar.recv[kFromReduceUnitIdx].val @= \ + // s.global_reduce_unit.send.val + // s.global_reduce_unit.send.rdy @= s.crossbar.recv[kFromReduceUnitIdx].rdy + // s.crossbar.recv[kFromReduceUnitIdx].msg @= s.global_reduce_unit.send.msg + // + // # For the ctrl and data preloading. + // s.crossbar.recv[kFromCpuCtrlAndDataIdx].val @= \ + // s.recv_from_cpu_pkt_queue.send.val + // s.recv_from_cpu_pkt_queue.send.rdy @= s.crossbar.recv[kFromCpuCtrlAndDataIdx].rdy + // s.crossbar.recv[kFromCpuCtrlAndDataIdx].msg @= \ + // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) + // InterCgraPktType(s.cgra_id, # src + // s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id, # dst + // 0, # src_x + // 0, # src_y + // s.idTo2d_x_lut[s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id], # dst_x + // s.idTo2d_y_lut[s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id], # dst_y + // num_tiles, # src_tile_id, num_tiles is used to indicate the request is from CPU, so the LOAD response can come back. + // s.recv_from_cpu_pkt_queue.send.msg.dst, # dst_tile_id + // 0, # remote_src_port, only used for inter-cgra remote load request/response. + // 0, # opaque + // 0, # vc_id + // s.recv_from_cpu_pkt_queue.send.msg.payload)) + // + // # TODO: For the other cmd types. + // + // + // # @update + // # def update_received_msg_from_noc(): + // + // # Initiates the signals. + // s.send_to_mem_load_request_queue.recv.val @= 0 + // s.send_to_mem_store_request_queue.recv.val @= 0 + // s.send_to_tile_load_response_queue.recv.val @= 0 + // + // s.send_to_mem_load_request_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.send_to_mem_store_request_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.send_to_tile_load_response_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // + // s.recv_from_inter_cgra_noc.rdy @= 0 + // s.send_to_ctrl_ring_pkt.val @= 0 + // s.send_to_ctrl_ring_pkt.msg @= IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.global_reduce_unit.recv_count.val @= 0 + // s.global_reduce_unit.recv_count.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.global_reduce_unit.recv_data.val @= 0 + // s.global_reduce_unit.recv_data.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // + // # For the load request from NoC. + // received_pkt = s.recv_from_inter_cgra_noc.msg + // if s.recv_from_inter_cgra_noc.val: + // if s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LOAD_REQUEST: + // s.send_to_mem_load_request_queue.recv.val @= 1 + // + // if s.send_to_mem_load_request_queue.recv.rdy: + // s.recv_from_inter_cgra_noc.rdy @= 1 + // s.send_to_mem_load_request_queue.recv.msg @= received_pkt + // + // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_STORE_REQUEST: + // s.send_to_mem_store_request_queue.recv.msg @= received_pkt + // s.send_to_mem_store_request_queue.recv.val @= 1 + // + // if s.send_to_mem_store_request_queue.recv.rdy: + // s.recv_from_inter_cgra_noc.rdy @= 1 + // + // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LOAD_RESPONSE: + // # FIXME: This condition needs to check whether this controller is the + // # one connecting to CPU, and with the help from additional field indicating + // # whether the packet is originally from CPU. + // # https://github.com/tancheng/VectorCGRA/issues/116. + // if s.recv_from_inter_cgra_noc.msg.dst_tile_id == num_tiles: + // s.recv_from_inter_cgra_noc.rdy @= s.send_to_cpu_pkt_queue.recv.rdy + // s.send_to_cpu_pkt_queue.recv.val @= 1 + // s.send_to_cpu_pkt_queue.recv.msg @= \ + // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src + // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst + // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x + // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y + // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x + // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y + // 0, # opaque + // 0, # vc_id + // s.recv_from_inter_cgra_noc.msg.payload) + // + // else: + // s.recv_from_inter_cgra_noc.rdy @= s.send_to_tile_load_response_queue.recv.rdy + // s.send_to_tile_load_response_queue.recv.msg @= received_pkt + // s.send_to_tile_load_response_queue.recv.val @= 1 + // + // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_COMPLETE: + // s.recv_from_inter_cgra_noc.rdy @= s.send_to_cpu_pkt_queue.recv.rdy + // s.send_to_cpu_pkt_queue.recv.val @= 1 + // s.send_to_cpu_pkt_queue.recv.msg @= \ + // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src + // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst + // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x + // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y + // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x + // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y + // 0, # opaque + // 0, # vc_id + // s.recv_from_inter_cgra_noc.msg.payload) + // + // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: + // s.recv_from_inter_cgra_noc.rdy @= s.global_reduce_unit.recv_data.rdy + // s.global_reduce_unit.recv_data.val @= 1 + // s.global_reduce_unit.recv_data.msg @= s.recv_from_inter_cgra_noc.msg + // + // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_COUNT: + // s.recv_from_inter_cgra_noc.rdy @= s.global_reduce_unit.recv_count.rdy + // s.global_reduce_unit.recv_count.val @= 1 + // s.global_reduce_unit.recv_count.msg @= s.recv_from_inter_cgra_noc.msg + // + // elif (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONST) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_PAUSE) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_PRESERVE) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_RESUME) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_RECORD_PHI_ADDR) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_TERMINATE) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LAUNCH): + // s.recv_from_inter_cgra_noc.rdy @= s.send_to_ctrl_ring_pkt.rdy + // s.send_to_ctrl_ring_pkt.val @= s.recv_from_inter_cgra_noc.val + // s.send_to_ctrl_ring_pkt.msg @= \ + // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src + // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst + // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x + // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y + // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x + // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y + // 0, # opaque + // 0, # vc_id + // s.recv_from_inter_cgra_noc.msg.payload) + // + // # else: + // # # TODO: Handle other cmd types. + // # assert(False) + + always_comb begin : update_received_msg + __tmpvar__update_received_msg_kLoadRequestInportIdx = 1'd0; + __tmpvar__update_received_msg_kLoadResponseInportIdx = 1'd1; + __tmpvar__update_received_msg_kStoreRequestInportIdx = 2'd2; + __tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx = 2'd3; + __tmpvar__update_received_msg_kFromInterTileRingIdx = 3'd4; + __tmpvar__update_received_msg_kFromReduceUnitIdx = 3'd5; + send_to_cpu_pkt_queue__recv__val = 1'd0; + send_to_cpu_pkt_queue__recv__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; + recv_from_ctrl_ring_pkt__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__CONTROLLER_CROSSBAR_INPORTS ); i += 1'd1 ) begin + crossbar__recv__val[3'(i)] = 1'd0; + crossbar__recv__msg[3'(i)] = { 1'd0, 221'd0 }; + end + crossbar__recv__val[__tmpvar__update_received_msg_kFromInterTileRingIdx] = recv_from_ctrl_ring_pkt__val; + recv_from_ctrl_ring_pkt__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromInterTileRingIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kFromInterTileRingIdx] = { 1'd0, { cgra_id, recv_from_ctrl_ring_pkt__msg.dst_cgra_id, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], recv_from_ctrl_ring_pkt__msg.dst_cgra_x, recv_from_ctrl_ring_pkt__msg.dst_cgra_y, recv_from_ctrl_ring_pkt__msg.src, recv_from_ctrl_ring_pkt__msg.dst, 3'd0, 8'd0, 2'd0, recv_from_ctrl_ring_pkt__msg.payload } }; + crossbar__recv__val[__tmpvar__update_received_msg_kLoadRequestInportIdx] = recv_from_tile_load_request_pkt_queue__send__val; + recv_from_tile_load_request_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kLoadRequestInportIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kLoadRequestInportIdx] = { 1'd0, recv_from_tile_load_request_pkt_queue__send__msg }; + crossbar__recv__val[__tmpvar__update_received_msg_kStoreRequestInportIdx] = recv_from_tile_store_request_pkt_queue__send__val; + recv_from_tile_store_request_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kStoreRequestInportIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kStoreRequestInportIdx] = { 1'd0, recv_from_tile_store_request_pkt_queue__send__msg }; + crossbar__recv__val[__tmpvar__update_received_msg_kLoadResponseInportIdx] = recv_from_tile_load_response_pkt_queue__send__val; + recv_from_tile_load_response_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kLoadResponseInportIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kLoadResponseInportIdx] = { 1'd0, recv_from_tile_load_response_pkt_queue__send__msg }; + crossbar__recv__val[__tmpvar__update_received_msg_kFromReduceUnitIdx] = global_reduce_unit__send__val; + global_reduce_unit__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromReduceUnitIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kFromReduceUnitIdx] = global_reduce_unit__send__msg; + crossbar__recv__val[__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx] = recv_from_cpu_pkt_queue__send__val; + recv_from_cpu_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx] = { 1'd0, { cgra_id, recv_from_cpu_pkt_queue__send__msg.dst_cgra_id, 1'd0, 1'd0, idTo2d_x_lut[recv_from_cpu_pkt_queue__send__msg.dst_cgra_id], idTo2d_y_lut[recv_from_cpu_pkt_queue__send__msg.dst_cgra_id], 5'( __const__num_tiles_at_update_received_msg ), recv_from_cpu_pkt_queue__send__msg.dst, 3'd0, 8'd0, 2'd0, recv_from_cpu_pkt_queue__send__msg.payload } }; + send_to_mem_load_request_queue__recv__val = 1'd0; + send_to_mem_store_request_queue__recv__val = 1'd0; + send_to_tile_load_response_queue__recv__val = 1'd0; + send_to_mem_load_request_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + send_to_mem_store_request_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + send_to_tile_load_response_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + recv_from_inter_cgra_noc__rdy = 1'd0; + send_to_ctrl_ring_pkt__val = 1'd0; + send_to_ctrl_ring_pkt__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; + global_reduce_unit__recv_count__val = 1'd0; + global_reduce_unit__recv_count__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + global_reduce_unit__recv_data__val = 1'd0; + global_reduce_unit__recv_data__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + __tmpvar__update_received_msg_received_pkt = recv_from_inter_cgra_noc__msg; + if ( recv_from_inter_cgra_noc__val ) begin + if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LOAD_REQUEST ) ) begin + send_to_mem_load_request_queue__recv__val = 1'd1; + if ( send_to_mem_load_request_queue__recv__rdy ) begin + recv_from_inter_cgra_noc__rdy = 1'd1; + send_to_mem_load_request_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; + end + end + else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_STORE_REQUEST ) ) begin + send_to_mem_store_request_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; + send_to_mem_store_request_queue__recv__val = 1'd1; + if ( send_to_mem_store_request_queue__recv__rdy ) begin + recv_from_inter_cgra_noc__rdy = 1'd1; + end + end + else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LOAD_RESPONSE ) ) begin + if ( recv_from_inter_cgra_noc__msg.dst_tile_id == 5'( __const__num_tiles_at_update_received_msg ) ) begin + recv_from_inter_cgra_noc__rdy = send_to_cpu_pkt_queue__recv__rdy; + send_to_cpu_pkt_queue__recv__val = 1'd1; + send_to_cpu_pkt_queue__recv__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; + end + else begin + recv_from_inter_cgra_noc__rdy = send_to_tile_load_response_queue__recv__rdy; + send_to_tile_load_response_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; + send_to_tile_load_response_queue__recv__val = 1'd1; + end + end + else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_COMPLETE ) ) begin + recv_from_inter_cgra_noc__rdy = send_to_cpu_pkt_queue__recv__rdy; + send_to_cpu_pkt_queue__recv__val = 1'd1; + send_to_cpu_pkt_queue__recv__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; + end + else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin + recv_from_inter_cgra_noc__rdy = global_reduce_unit__recv_data__rdy; + global_reduce_unit__recv_data__val = 1'd1; + global_reduce_unit__recv_data__msg = recv_from_inter_cgra_noc__msg; + end + else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_COUNT ) ) begin + recv_from_inter_cgra_noc__rdy = global_reduce_unit__recv_count__rdy; + global_reduce_unit__recv_count__val = 1'd1; + global_reduce_unit__recv_count__msg = recv_from_inter_cgra_noc__msg; + end + else if ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONST ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_PAUSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_PRESERVE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_RECORD_PHI_ADDR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) begin + recv_from_inter_cgra_noc__rdy = send_to_ctrl_ring_pkt__rdy; + send_to_ctrl_ring_pkt__val = recv_from_inter_cgra_noc__val; + send_to_ctrl_ring_pkt__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:350 + // @update + // def update_sending_to_noc_msg(): + // s.send_to_inter_cgra_noc.val @= s.crossbar.send[0].val + // s.crossbar.send[0].rdy @= s.send_to_inter_cgra_noc.rdy + // s.send_to_inter_cgra_noc.msg @= s.crossbar.send[0].msg.inter_cgra_pkt + // # addr_dst_id = 0 + // if (s.crossbar.send[0].msg.inter_cgra_pkt.payload.cmd == CMD_LOAD_REQUEST) | \ + // (s.crossbar.send[0].msg.inter_cgra_pkt.payload.cmd == CMD_STORE_REQUEST): + // s.send_to_inter_cgra_noc.msg.dst @= s.addr_dst_id + // s.send_to_inter_cgra_noc.msg.dst_x @= s.idTo2d_x_lut[s.addr_dst_id] + // s.send_to_inter_cgra_noc.msg.dst_y @= s.idTo2d_y_lut[s.addr_dst_id] + + always_comb begin : update_sending_to_noc_msg + send_to_inter_cgra_noc__val = crossbar__send__val[1'd0]; + crossbar__send__rdy[1'd0] = send_to_inter_cgra_noc__rdy; + send_to_inter_cgra_noc__msg = crossbar__send__msg[1'd0].inter_cgra_pkt; + if ( ( crossbar__send__msg[1'd0].inter_cgra_pkt.payload.cmd == 5'( __const__CMD_LOAD_REQUEST ) ) | ( crossbar__send__msg[1'd0].inter_cgra_pkt.payload.cmd == 5'( __const__CMD_STORE_REQUEST ) ) ) begin + send_to_inter_cgra_noc__msg.dst = addr_dst_id; + send_to_inter_cgra_noc__msg.dst_x = idTo2d_x_lut[addr_dst_id]; + send_to_inter_cgra_noc__msg.dst_y = idTo2d_y_lut[addr_dst_id]; + end + end + + assign recv_from_tile_load_request_pkt_queue__clk = clk; + assign recv_from_tile_load_request_pkt_queue__reset = reset; + assign recv_from_tile_load_response_pkt_queue__clk = clk; + assign recv_from_tile_load_response_pkt_queue__reset = reset; + assign recv_from_tile_store_request_pkt_queue__clk = clk; + assign recv_from_tile_store_request_pkt_queue__reset = reset; + assign send_to_mem_load_request_queue__clk = clk; + assign send_to_mem_load_request_queue__reset = reset; + assign send_to_tile_load_response_queue__clk = clk; + assign send_to_tile_load_response_queue__reset = reset; + assign send_to_mem_store_request_queue__clk = clk; + assign send_to_mem_store_request_queue__reset = reset; + assign crossbar__clk = clk; + assign crossbar__reset = reset; + assign recv_from_cpu_pkt_queue__clk = clk; + assign recv_from_cpu_pkt_queue__reset = reset; + assign send_to_cpu_pkt_queue__clk = clk; + assign send_to_cpu_pkt_queue__reset = reset; + assign global_reduce_unit__clk = clk; + assign global_reduce_unit__reset = reset; + assign addr2controller_lut[0] = 2'd0; + assign addr2controller_lut[1] = 2'd1; + assign addr2controller_lut[2] = 2'd2; + assign addr2controller_lut[3] = 2'd3; + assign idTo2d_x_lut[0] = 1'd0; + assign idTo2d_y_lut[0] = 1'd0; + assign idTo2d_x_lut[1] = 1'd1; + assign idTo2d_y_lut[1] = 1'd0; + assign idTo2d_x_lut[2] = 1'd0; + assign idTo2d_y_lut[2] = 1'd1; + assign idTo2d_x_lut[3] = 1'd1; + assign idTo2d_y_lut[3] = 1'd1; + assign recv_from_tile_load_request_pkt_queue__recv__msg = recv_from_tile_load_request_pkt__msg; + assign recv_from_tile_load_request_pkt__rdy = recv_from_tile_load_request_pkt_queue__recv__rdy; + assign recv_from_tile_load_request_pkt_queue__recv__val = recv_from_tile_load_request_pkt__val; + assign recv_from_tile_load_response_pkt_queue__recv__msg = recv_from_tile_load_response_pkt__msg; + assign recv_from_tile_load_response_pkt__rdy = recv_from_tile_load_response_pkt_queue__recv__rdy; + assign recv_from_tile_load_response_pkt_queue__recv__val = recv_from_tile_load_response_pkt__val; + assign recv_from_tile_store_request_pkt_queue__recv__msg = recv_from_tile_store_request_pkt__msg; + assign recv_from_tile_store_request_pkt__rdy = recv_from_tile_store_request_pkt_queue__recv__rdy; + assign recv_from_tile_store_request_pkt_queue__recv__val = recv_from_tile_store_request_pkt__val; + assign send_to_mem_load_request__msg = send_to_mem_load_request_queue__send__msg; + assign send_to_mem_load_request_queue__send__rdy = send_to_mem_load_request__rdy; + assign send_to_mem_load_request__val = send_to_mem_load_request_queue__send__val; + assign send_to_tile_load_response__msg = send_to_tile_load_response_queue__send__msg; + assign send_to_tile_load_response_queue__send__rdy = send_to_tile_load_response__rdy; + assign send_to_tile_load_response__val = send_to_tile_load_response_queue__send__val; + assign send_to_mem_store_request__msg = send_to_mem_store_request_queue__send__msg; + assign send_to_mem_store_request_queue__send__rdy = send_to_mem_store_request__rdy; + assign send_to_mem_store_request__val = send_to_mem_store_request_queue__send__val; + assign recv_from_cpu_pkt_queue__recv__msg = recv_from_cpu_pkt__msg; + assign recv_from_cpu_pkt__rdy = recv_from_cpu_pkt_queue__recv__rdy; + assign recv_from_cpu_pkt_queue__recv__val = recv_from_cpu_pkt__val; + assign send_to_cpu_pkt__msg = send_to_cpu_pkt_queue__send__msg; + assign send_to_cpu_pkt_queue__send__rdy = send_to_cpu_pkt__rdy; + assign send_to_cpu_pkt__val = send_to_cpu_pkt_queue__send__val; + +endmodule + + +// PyMTL Component Counter Definition +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/rtl/Counter.py + +module Counter__Type_Bits2__reset_value_2 +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] decr , + input logic [0:0] incr , + input logic [0:0] load , + input logic [1:0] load_value , + input logic [0:0] reset +); + localparam logic [1:0] __const__reset_value_at_up_count = 2'd2; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/rtl/Counter.py:28 + // @update_ff + // def up_count(): + // + // if s.reset: + // s.count <<= reset_value + // + // elif s.load: + // s.count <<= s.load_value + // + // elif s.incr & ~s.decr: + // s.count <<= s.count + 1 + // + // elif ~s.incr & s.decr: + // s.count <<= s.count - 1 + + always_ff @(posedge clk) begin : up_count + if ( reset ) begin + count <= 2'( __const__reset_value_at_up_count ); + end + else if ( load ) begin + count <= load_value; + end + else if ( incr & ( ~decr ) ) begin + count <= count + 2'd1; + end + else if ( ( ~incr ) & decr ) begin + count <= count - 2'd1; + end + end + +endmodule + + +// PyMTL Component RecvRTL2CreditSendRTL Definition +// Full name: RecvRTL2CreditSendRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py + +module RecvRTL2CreditSendRTL__6d49e584a986d10c +( + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output logic [0:0] send__en , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__yum [0:1] +); + localparam logic [1:0] __const__vc_at_up_credit_send = 2'd2; + localparam logic [1:0] __const__vc_at_up_counter_decr = 2'd2; + //------------------------------------------------------------- + // Component credit[0:1] + //------------------------------------------------------------- + + logic [0:0] credit__clk [0:1]; + logic [1:0] credit__count [0:1]; + logic [0:0] credit__decr [0:1]; + logic [0:0] credit__incr [0:1]; + logic [0:0] credit__load [0:1]; + logic [1:0] credit__load_value [0:1]; + logic [0:0] credit__reset [0:1]; + + Counter__Type_Bits2__reset_value_2 credit__0 + ( + .clk( credit__clk[0] ), + .count( credit__count[0] ), + .decr( credit__decr[0] ), + .incr( credit__incr[0] ), + .load( credit__load[0] ), + .load_value( credit__load_value[0] ), + .reset( credit__reset[0] ) + ); + + Counter__Type_Bits2__reset_value_2 credit__1 + ( + .clk( credit__clk[1] ), + .count( credit__count[1] ), + .decr( credit__decr[1] ), + .incr( credit__incr[1] ), + .load( credit__load[1] ), + .load_value( credit__load_value[1] ), + .reset( credit__reset[1] ) + ); + + //------------------------------------------------------------- + // End of component credit[0:1] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:149 + // @update + // def up_counter_decr(): + // for i in range( vc ): + // s.credit[i].decr @= s.send.en & ( i == s.send.msg.vc_id ) + + always_comb begin : up_counter_decr + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_counter_decr ); i += 1'd1 ) + credit__decr[1'(i)] = send__en & ( 1'(i) == send__msg.vc_id ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:137 + // @update + // def up_credit_send(): + // s.send.en @= 0 + // s.recv.rdy @= 0 + // # NOTE: recv.rdy depends on recv.val. + // # Be careful about combinationl loop. + // if s.recv.val: + // for i in range( vc ): + // if ( i == s.recv.msg.vc_id ) & ( s.credit[i].count > 0 ): + // s.send.en @= 1 + // s.recv.rdy @= 1 + + always_comb begin : up_credit_send + send__en = 1'd0; + recv__rdy = 1'd0; + if ( recv__val ) begin + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_credit_send ); i += 1'd1 ) + if ( ( 1'(i) == recv__msg.vc_id ) & ( credit__count[1'(i)] > 2'd0 ) ) begin + send__en = 1'd1; + recv__rdy = 1'd1; + end + end + end + + assign credit__clk[0] = clk; + assign credit__reset[0] = reset; + assign credit__clk[1] = clk; + assign credit__reset[1] = reset; + assign send__msg = recv__msg; + assign credit__incr[0] = send__yum[0]; + assign credit__load[0] = 1'd0; + assign credit__load_value[0] = 2'd0; + assign credit__incr[1] = send__yum[1]; + assign credit__load[1] = 1'd0; + assign credit__load_value[1] = 2'd0; + +endmodule + + +// PyMTL Component InputUnitCreditRTL Definition +// Full name: InputUnitCreditRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__QueueType_NormalQueueRTL__vc_2__credit_line_2 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py + +module InputUnitCreditRTL__797fe657f4e9d44e +( + input logic [0:0] clk , + input logic [0:0] reset , + input logic [0:0] recv__en , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__yum [0:1] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:1] , + input logic [0:0] send__rdy [0:1] , + output logic [0:0] send__val [0:1] +); + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ = 1'd0; + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ = 1'd1; + localparam logic [1:0] __const__vc_at_up_enq = 2'd2; + //------------------------------------------------------------- + // Component buffers[0:1] + //------------------------------------------------------------- + + logic [0:0] buffers__clk [0:1]; + logic [1:0] buffers__count [0:1]; + logic [0:0] buffers__reset [0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__recv__msg [0:1]; + logic [0:0] buffers__recv__rdy [0:1]; + logic [0:0] buffers__recv__val [0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__send__msg [0:1]; + logic [0:0] buffers__send__rdy [0:1]; + logic [0:0] buffers__send__val [0:1]; + + NormalQueueRTL__a1c7a5a18a302c36 buffers__0 + ( + .clk( buffers__clk[0] ), + .count( buffers__count[0] ), + .reset( buffers__reset[0] ), + .recv__msg( buffers__recv__msg[0] ), + .recv__rdy( buffers__recv__rdy[0] ), + .recv__val( buffers__recv__val[0] ), + .send__msg( buffers__send__msg[0] ), + .send__rdy( buffers__send__rdy[0] ), + .send__val( buffers__send__val[0] ) + ); + + NormalQueueRTL__a1c7a5a18a302c36 buffers__1 + ( + .clk( buffers__clk[1] ), + .count( buffers__count[1] ), + .reset( buffers__reset[1] ), + .recv__msg( buffers__recv__msg[1] ), + .recv__rdy( buffers__recv__rdy[1] ), + .recv__val( buffers__recv__val[1] ), + .send__msg( buffers__send__msg[1] ), + .send__rdy( buffers__send__rdy[1] ), + .send__val( buffers__send__val[1] ) + ); + + //------------------------------------------------------------- + // End of component buffers[0:1] + //------------------------------------------------------------- + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:39 + // s.recv.yum[i] //= lambda: s.send[i].val & s.send[i].rdy + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ + recv__yum[1'd0] = send__val[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ )] & send__rdy[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ )]; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:39 + // s.recv.yum[i] //= lambda: s.send[i].val & s.send[i].rdy + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ + recv__yum[1'd1] = send__val[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ )] & send__rdy[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ )]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:41 + // @update + // def up_enq(): + // if s.recv.en: + // for i in range( vc ): + // s.buffers[i].recv.val @= ( s.recv.msg.vc_id == i ) + // else: + // for i in range( vc ): + // s.buffers[i].recv.val @= 0 + + always_comb begin : up_enq + if ( recv__en ) begin + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) + buffers__recv__val[1'(i)] = recv__msg.vc_id == 1'(i); + end + else + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) + buffers__recv__val[1'(i)] = 1'd0; + end + + assign buffers__clk[0] = clk; + assign buffers__reset[0] = reset; + assign buffers__clk[1] = clk; + assign buffers__reset[1] = reset; + assign buffers__recv__msg[0] = recv__msg; + assign send__msg[0] = buffers__send__msg[0]; + assign buffers__send__rdy[0] = send__rdy[0]; + assign send__val[0] = buffers__send__val[0]; + assign buffers__recv__msg[1] = recv__msg; + assign send__msg[1] = buffers__send__msg[1]; + assign buffers__send__rdy[1] = send__rdy[1]; + assign send__val[1] = buffers__send__val[1]; + +endmodule + + +// PyMTL Component OutputUnitCreditRTL Definition +// Full name: OutputUnitCreditRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py + +module OutputUnitCreditRTL__6d49e584a986d10c +( + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output logic [0:0] send__en , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__yum [0:1] +); + localparam logic [1:0] __const__vc_at_up_credit_send = 2'd2; + localparam logic [1:0] __const__vc_at_up_counter_decr = 2'd2; + //------------------------------------------------------------- + // Component credit[0:1] + //------------------------------------------------------------- + + logic [0:0] credit__clk [0:1]; + logic [1:0] credit__count [0:1]; + logic [0:0] credit__decr [0:1]; + logic [0:0] credit__incr [0:1]; + logic [0:0] credit__load [0:1]; + logic [1:0] credit__load_value [0:1]; + logic [0:0] credit__reset [0:1]; + + Counter__Type_Bits2__reset_value_2 credit__0 + ( + .clk( credit__clk[0] ), + .count( credit__count[0] ), + .decr( credit__decr[0] ), + .incr( credit__incr[0] ), + .load( credit__load[0] ), + .load_value( credit__load_value[0] ), + .reset( credit__reset[0] ) + ); + + Counter__Type_Bits2__reset_value_2 credit__1 + ( + .clk( credit__clk[1] ), + .count( credit__count[1] ), + .decr( credit__decr[1] ), + .incr( credit__incr[1] ), + .load( credit__load[1] ), + .load_value( credit__load_value[1] ), + .reset( credit__reset[1] ) + ); + + //------------------------------------------------------------- + // End of component credit[0:1] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py:47 + // @update + // def up_counter_decr(): + // for i in range( vc ): + // s.credit[i].decr @= s.send.en & ( i == s.send.msg.vc_id ) + + always_comb begin : up_counter_decr + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_counter_decr ); i += 1'd1 ) + credit__decr[1'(i)] = send__en & ( 1'(i) == send__msg.vc_id ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py:35 + // @update + // def up_credit_send(): + // s.send.en @= 0 + // s.recv.rdy @= 0 + // # NOTE: Here the recv.rdy depends on recv.val. + // # Be careful about combinational loop. + // if s.recv.val: + // for i in range( vc ): + // if (i == s.recv.msg.vc_id) & (s.credit[i].count > 0): + // s.send.en @= 1 + // s.recv.rdy @= 1 + + always_comb begin : up_credit_send + send__en = 1'd0; + recv__rdy = 1'd0; + if ( recv__val ) begin + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_credit_send ); i += 1'd1 ) + if ( ( 1'(i) == recv__msg.vc_id ) & ( credit__count[1'(i)] > 2'd0 ) ) begin + send__en = 1'd1; + recv__rdy = 1'd1; + end + end + end + + assign credit__clk[0] = clk; + assign credit__reset[0] = reset; + assign credit__clk[1] = clk; + assign credit__reset[1] = reset; + assign send__msg = recv__msg; + assign credit__incr[0] = send__yum[0]; + assign credit__load[0] = 1'd0; + assign credit__load_value[0] = 2'd0; + assign credit__incr[1] = send__yum[1]; + assign credit__load[1] = 1'd0; + assign credit__load_value[1] = 2'd0; + +endmodule + + +// PyMTL Component RingRouteUnitRTL Definition +// Full name: RingRouteUnitRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py + +module RingRouteUnitRTL__6d1cae73cf31e9a0 +( + input logic [0:0] clk , + input logic [4:0] pos , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:2] , + input logic [0:0] send__rdy [0:2] , + output logic [0:0] send__val [0:2] +); + localparam logic [1:0] __const__SELF = 2'd2; + localparam logic [0:0] __const__LEFT = 1'd0; + localparam logic [0:0] __const__RIGHT = 1'd1; + logic [4:0] left_dist; + logic [1:0] out_dir; + logic [4:0] right_dist; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg_wire; + logic [2:0] send_rdy; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:51 + // @update + // def up_left_right_dist(): + // if s.recv.msg.dst < s.pos: + // s.left_dist @= zext(s.pos, DistType) - zext(s.recv.msg.dst, DistType) + // s.right_dist @= zext(s.last_idx, DistType) - zext(s.pos, DistType) + zext(s.recv.msg.dst, DistType) + 1 + // else: + // s.left_dist @= 1 + zext(s.last_idx, DistType) + zext(s.pos, DistType) - zext(s.recv.msg.dst, DistType) + // s.right_dist @= zext(s.recv.msg.dst, DistType) - zext(s.pos, DistType) + + always_comb begin : up_left_right_dist + if ( recv__msg.dst < pos ) begin + left_dist = pos - recv__msg.dst; + right_dist = ( ( 5'd16 - pos ) + recv__msg.dst ) + 5'd1; + end + else begin + left_dist = ( ( 5'd1 + 5'd16 ) + pos ) - recv__msg.dst; + right_dist = recv__msg.dst - pos; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:85 + // @update + // def up_ru_recv_rdy(): + // s.recv.rdy @= s.send_rdy[ s.out_dir ] + + always_comb begin : up_ru_recv_rdy + recv__rdy = send_rdy[out_dir]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:60 + // @update + // def up_ru_routing(): + // + // s.out_dir @= 0 + // s.send_msg_wire @= s.recv.msg + // for i in range( s.num_outports ): + // s.send[i].val @= 0 + // s.send[i].msg @= s.recv.msg + // + // if s.recv.val: + // if s.pos == s.recv.msg.dst: + // s.out_dir @= SELF + // elif s.left_dist < s.right_dist: + // s.out_dir @= LEFT + // else: + // s.out_dir @= RIGHT + // + // if ( s.pos == s.last_idx ) & ( s.out_dir == RIGHT ): + // s.send_msg_wire.vc_id @= 1 + // elif ( s.pos == 0 ) & ( s.out_dir == LEFT ): + // s.send_msg_wire.vc_id @= 1 + // + // s.send[ s.out_dir ].val @= 1 + // s.send[ s.out_dir ].msg @= s.send_msg_wire + + always_comb begin : up_ru_routing + out_dir = 2'd0; + send_msg_wire = recv__msg; + for ( int unsigned i = 1'd0; i < 2'd3; i += 1'd1 ) begin + send__val[2'(i)] = 1'd0; + send__msg[2'(i)] = recv__msg; + end + if ( recv__val ) begin + if ( pos == recv__msg.dst ) begin + out_dir = 2'( __const__SELF ); + end + else if ( left_dist < right_dist ) begin + out_dir = 2'( __const__LEFT ); + end + else + out_dir = 2'( __const__RIGHT ); + if ( ( pos == 5'd16 ) & ( out_dir == 2'( __const__RIGHT ) ) ) begin + send_msg_wire.vc_id = 1'd1; + end + else if ( ( pos == 5'd0 ) & ( out_dir == 2'( __const__LEFT ) ) ) begin + send_msg_wire.vc_id = 1'd1; + end + send__val[out_dir] = 1'd1; + send__msg[out_dir] = send_msg_wire; + end + end + + assign send_rdy[0:0] = send__rdy[0]; + assign send_rdy[1:1] = send__rdy[1]; + assign send_rdy[2:2] = send__rdy[2]; + +endmodule + + +// PyMTL Component Mux Definition +// Full name: Mux__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ninputs_6 +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__1cc75bdfd067f505 +( + input logic [0:0] clk , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 in_ [0:5], + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 out , + input logic [0:0] reset , + input logic [2:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component SwitchUnitRTL Definition +// Full name: SwitchUnitRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_inports_6 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py + +module SwitchUnitRTL__ae7d6e1a8f952f91 +( + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:5] , + output logic [0:0] recv__rdy [0:5] , + input logic [0:0] recv__val [0:5] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd6; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [5:0] arbiter__grants; + logic [5:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_6 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [5:0] encoder__in_; + logic [2:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_6__out_nbits_3 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__in_ [0:5]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__out; + logic [0:0] mux__reset; + logic [2:0] mux__sel; + + Mux__1cc75bdfd067f505 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 + // @update + // def up_get_en(): + // for i in range( num_inports ): + // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) + + always_comb begin : up_get_en + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) + recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 + // @update + // def up_send_val(): + // s.send.val @= s.arbiter.grants > 0 + + always_comb begin : up_send_val + send__val = arbiter__grants > 6'd0; + end + + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign arbiter__en = 1'd1; + assign mux__clk = clk; + assign mux__reset = reset; + assign send__msg = mux__out; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign encoder__in_ = arbiter__grants; + assign mux__sel = encoder__out; + assign arbiter__reqs[0:0] = recv__val[0]; + assign mux__in_[0] = recv__msg[0]; + assign arbiter__reqs[1:1] = recv__val[1]; + assign mux__in_[1] = recv__msg[1]; + assign arbiter__reqs[2:2] = recv__val[2]; + assign mux__in_[2] = recv__msg[2]; + assign arbiter__reqs[3:3] = recv__val[3]; + assign mux__in_[3] = recv__msg[3]; + assign arbiter__reqs[4:4] = recv__val[4]; + assign mux__in_[4] = recv__msg[4]; + assign arbiter__reqs[5:5] = recv__val[5]; + assign mux__in_[5] = recv__msg[5]; + +endmodule + + +// PyMTL Component RingRouterRTL Definition +// Full name: RingRouterRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17__InputUnitType_InputUnitCreditRTL__RouteUnitType_RingRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitCreditRTL__vc_2__credit_line_2 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouterRTL.py + +module RingRouterRTL__6e670e447e1766e0 +( + input logic [0:0] clk , + input logic [4:0] pos , + input logic [0:0] reset , + input logic [0:0] recv__en [0:2] , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:2] , + output logic [0:0] recv__yum [0:2][0:1] , + output logic [0:0] send__en [0:2] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:2] , + input logic [0:0] send__yum [0:2][0:1] +); + //------------------------------------------------------------- + // Component input_units[0:2] + //------------------------------------------------------------- + + logic [0:0] input_units__clk [0:2]; + logic [0:0] input_units__reset [0:2]; + logic [0:0] input_units__recv__en [0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 input_units__recv__msg [0:2]; + logic [0:0] input_units__recv__yum [0:2][0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 input_units__send__msg [0:2][0:1]; + logic [0:0] input_units__send__rdy [0:2][0:1]; + logic [0:0] input_units__send__val [0:2][0:1]; + + InputUnitCreditRTL__797fe657f4e9d44e input_units__0 + ( + .clk( input_units__clk[0] ), + .reset( input_units__reset[0] ), + .recv__en( input_units__recv__en[0] ), + .recv__msg( input_units__recv__msg[0] ), + .recv__yum( input_units__recv__yum[0] ), + .send__msg( input_units__send__msg[0] ), + .send__rdy( input_units__send__rdy[0] ), + .send__val( input_units__send__val[0] ) + ); + + InputUnitCreditRTL__797fe657f4e9d44e input_units__1 + ( + .clk( input_units__clk[1] ), + .reset( input_units__reset[1] ), + .recv__en( input_units__recv__en[1] ), + .recv__msg( input_units__recv__msg[1] ), + .recv__yum( input_units__recv__yum[1] ), + .send__msg( input_units__send__msg[1] ), + .send__rdy( input_units__send__rdy[1] ), + .send__val( input_units__send__val[1] ) + ); + + InputUnitCreditRTL__797fe657f4e9d44e input_units__2 + ( + .clk( input_units__clk[2] ), + .reset( input_units__reset[2] ), + .recv__en( input_units__recv__en[2] ), + .recv__msg( input_units__recv__msg[2] ), + .recv__yum( input_units__recv__yum[2] ), + .send__msg( input_units__send__msg[2] ), + .send__rdy( input_units__send__rdy[2] ), + .send__val( input_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component input_units[0:2] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component output_units[0:2] + //------------------------------------------------------------- + + logic [0:0] output_units__clk [0:2]; + logic [0:0] output_units__reset [0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 output_units__recv__msg [0:2]; + logic [0:0] output_units__recv__rdy [0:2]; + logic [0:0] output_units__recv__val [0:2]; + logic [0:0] output_units__send__en [0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 output_units__send__msg [0:2]; + logic [0:0] output_units__send__yum [0:2][0:1]; + + OutputUnitCreditRTL__6d49e584a986d10c output_units__0 + ( + .clk( output_units__clk[0] ), + .reset( output_units__reset[0] ), + .recv__msg( output_units__recv__msg[0] ), + .recv__rdy( output_units__recv__rdy[0] ), + .recv__val( output_units__recv__val[0] ), + .send__en( output_units__send__en[0] ), + .send__msg( output_units__send__msg[0] ), + .send__yum( output_units__send__yum[0] ) + ); + + OutputUnitCreditRTL__6d49e584a986d10c output_units__1 + ( + .clk( output_units__clk[1] ), + .reset( output_units__reset[1] ), + .recv__msg( output_units__recv__msg[1] ), + .recv__rdy( output_units__recv__rdy[1] ), + .recv__val( output_units__recv__val[1] ), + .send__en( output_units__send__en[1] ), + .send__msg( output_units__send__msg[1] ), + .send__yum( output_units__send__yum[1] ) + ); + + OutputUnitCreditRTL__6d49e584a986d10c output_units__2 + ( + .clk( output_units__clk[2] ), + .reset( output_units__reset[2] ), + .recv__msg( output_units__recv__msg[2] ), + .recv__rdy( output_units__recv__rdy[2] ), + .recv__val( output_units__recv__val[2] ), + .send__en( output_units__send__en[2] ), + .send__msg( output_units__send__msg[2] ), + .send__yum( output_units__send__yum[2] ) + ); + + //------------------------------------------------------------- + // End of component output_units[0:2] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component route_units[0:5] + //------------------------------------------------------------- + + logic [0:0] route_units__clk [0:5]; + logic [4:0] route_units__pos [0:5]; + logic [0:0] route_units__reset [0:5]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 route_units__recv__msg [0:5]; + logic [0:0] route_units__recv__rdy [0:5]; + logic [0:0] route_units__recv__val [0:5]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 route_units__send__msg [0:5][0:2]; + logic [0:0] route_units__send__rdy [0:5][0:2]; + logic [0:0] route_units__send__val [0:5][0:2]; + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__0 + ( + .clk( route_units__clk[0] ), + .pos( route_units__pos[0] ), + .reset( route_units__reset[0] ), + .recv__msg( route_units__recv__msg[0] ), + .recv__rdy( route_units__recv__rdy[0] ), + .recv__val( route_units__recv__val[0] ), + .send__msg( route_units__send__msg[0] ), + .send__rdy( route_units__send__rdy[0] ), + .send__val( route_units__send__val[0] ) + ); + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__1 + ( + .clk( route_units__clk[1] ), + .pos( route_units__pos[1] ), + .reset( route_units__reset[1] ), + .recv__msg( route_units__recv__msg[1] ), + .recv__rdy( route_units__recv__rdy[1] ), + .recv__val( route_units__recv__val[1] ), + .send__msg( route_units__send__msg[1] ), + .send__rdy( route_units__send__rdy[1] ), + .send__val( route_units__send__val[1] ) + ); + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__2 + ( + .clk( route_units__clk[2] ), + .pos( route_units__pos[2] ), + .reset( route_units__reset[2] ), + .recv__msg( route_units__recv__msg[2] ), + .recv__rdy( route_units__recv__rdy[2] ), + .recv__val( route_units__recv__val[2] ), + .send__msg( route_units__send__msg[2] ), + .send__rdy( route_units__send__rdy[2] ), + .send__val( route_units__send__val[2] ) + ); + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__3 + ( + .clk( route_units__clk[3] ), + .pos( route_units__pos[3] ), + .reset( route_units__reset[3] ), + .recv__msg( route_units__recv__msg[3] ), + .recv__rdy( route_units__recv__rdy[3] ), + .recv__val( route_units__recv__val[3] ), + .send__msg( route_units__send__msg[3] ), + .send__rdy( route_units__send__rdy[3] ), + .send__val( route_units__send__val[3] ) + ); + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__4 + ( + .clk( route_units__clk[4] ), + .pos( route_units__pos[4] ), + .reset( route_units__reset[4] ), + .recv__msg( route_units__recv__msg[4] ), + .recv__rdy( route_units__recv__rdy[4] ), + .recv__val( route_units__recv__val[4] ), + .send__msg( route_units__send__msg[4] ), + .send__rdy( route_units__send__rdy[4] ), + .send__val( route_units__send__val[4] ) + ); + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__5 + ( + .clk( route_units__clk[5] ), + .pos( route_units__pos[5] ), + .reset( route_units__reset[5] ), + .recv__msg( route_units__recv__msg[5] ), + .recv__rdy( route_units__recv__rdy[5] ), + .recv__val( route_units__recv__val[5] ), + .send__msg( route_units__send__msg[5] ), + .send__rdy( route_units__send__rdy[5] ), + .send__val( route_units__send__val[5] ) + ); + + //------------------------------------------------------------- + // End of component route_units[0:5] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component switch_units[0:2] + //------------------------------------------------------------- + + logic [0:0] switch_units__clk [0:2]; + logic [0:0] switch_units__reset [0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 switch_units__recv__msg [0:2][0:5]; + logic [0:0] switch_units__recv__rdy [0:2][0:5]; + logic [0:0] switch_units__recv__val [0:2][0:5]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 switch_units__send__msg [0:2]; + logic [0:0] switch_units__send__rdy [0:2]; + logic [0:0] switch_units__send__val [0:2]; + + SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__0 + ( + .clk( switch_units__clk[0] ), + .reset( switch_units__reset[0] ), + .recv__msg( switch_units__recv__msg[0] ), + .recv__rdy( switch_units__recv__rdy[0] ), + .recv__val( switch_units__recv__val[0] ), + .send__msg( switch_units__send__msg[0] ), + .send__rdy( switch_units__send__rdy[0] ), + .send__val( switch_units__send__val[0] ) + ); + + SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__1 + ( + .clk( switch_units__clk[1] ), + .reset( switch_units__reset[1] ), + .recv__msg( switch_units__recv__msg[1] ), + .recv__rdy( switch_units__recv__rdy[1] ), + .recv__val( switch_units__recv__val[1] ), + .send__msg( switch_units__send__msg[1] ), + .send__rdy( switch_units__send__rdy[1] ), + .send__val( switch_units__send__val[1] ) + ); + + SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__2 + ( + .clk( switch_units__clk[2] ), + .reset( switch_units__reset[2] ), + .recv__msg( switch_units__recv__msg[2] ), + .recv__rdy( switch_units__recv__rdy[2] ), + .recv__val( switch_units__recv__val[2] ), + .send__msg( switch_units__send__msg[2] ), + .send__rdy( switch_units__send__rdy[2] ), + .send__val( switch_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component switch_units[0:2] + //------------------------------------------------------------- + + assign input_units__clk[0] = clk; + assign input_units__reset[0] = reset; + assign input_units__clk[1] = clk; + assign input_units__reset[1] = reset; + assign input_units__clk[2] = clk; + assign input_units__reset[2] = reset; + assign route_units__clk[0] = clk; + assign route_units__reset[0] = reset; + assign route_units__clk[1] = clk; + assign route_units__reset[1] = reset; + assign route_units__clk[2] = clk; + assign route_units__reset[2] = reset; + assign route_units__clk[3] = clk; + assign route_units__reset[3] = reset; + assign route_units__clk[4] = clk; + assign route_units__reset[4] = reset; + assign route_units__clk[5] = clk; + assign route_units__reset[5] = reset; + assign switch_units__clk[0] = clk; + assign switch_units__reset[0] = reset; + assign switch_units__clk[1] = clk; + assign switch_units__reset[1] = reset; + assign switch_units__clk[2] = clk; + assign switch_units__reset[2] = reset; + assign output_units__clk[0] = clk; + assign output_units__reset[0] = reset; + assign output_units__clk[1] = clk; + assign output_units__reset[1] = reset; + assign output_units__clk[2] = clk; + assign output_units__reset[2] = reset; + assign input_units__recv__en[0] = recv__en[0]; + assign input_units__recv__msg[0] = recv__msg[0]; + assign recv__yum[0][0] = input_units__recv__yum[0][0]; + assign recv__yum[0][1] = input_units__recv__yum[0][1]; + assign route_units__recv__msg[0] = input_units__send__msg[0][0]; + assign input_units__send__rdy[0][0] = route_units__recv__rdy[0]; + assign route_units__recv__val[0] = input_units__send__val[0][0]; + assign route_units__pos[0] = pos; + assign route_units__recv__msg[1] = input_units__send__msg[0][1]; + assign input_units__send__rdy[0][1] = route_units__recv__rdy[1]; + assign route_units__recv__val[1] = input_units__send__val[0][1]; + assign route_units__pos[1] = pos; + assign input_units__recv__en[1] = recv__en[1]; + assign input_units__recv__msg[1] = recv__msg[1]; + assign recv__yum[1][0] = input_units__recv__yum[1][0]; + assign recv__yum[1][1] = input_units__recv__yum[1][1]; + assign route_units__recv__msg[2] = input_units__send__msg[1][0]; + assign input_units__send__rdy[1][0] = route_units__recv__rdy[2]; + assign route_units__recv__val[2] = input_units__send__val[1][0]; + assign route_units__pos[2] = pos; + assign route_units__recv__msg[3] = input_units__send__msg[1][1]; + assign input_units__send__rdy[1][1] = route_units__recv__rdy[3]; + assign route_units__recv__val[3] = input_units__send__val[1][1]; + assign route_units__pos[3] = pos; + assign input_units__recv__en[2] = recv__en[2]; + assign input_units__recv__msg[2] = recv__msg[2]; + assign recv__yum[2][0] = input_units__recv__yum[2][0]; + assign recv__yum[2][1] = input_units__recv__yum[2][1]; + assign route_units__recv__msg[4] = input_units__send__msg[2][0]; + assign input_units__send__rdy[2][0] = route_units__recv__rdy[4]; + assign route_units__recv__val[4] = input_units__send__val[2][0]; + assign route_units__pos[4] = pos; + assign route_units__recv__msg[5] = input_units__send__msg[2][1]; + assign input_units__send__rdy[2][1] = route_units__recv__rdy[5]; + assign route_units__recv__val[5] = input_units__send__val[2][1]; + assign route_units__pos[5] = pos; + assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; + assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; + assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; + assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; + assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; + assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; + assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; + assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; + assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; + assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; + assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; + assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; + assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; + assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; + assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; + assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; + assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; + assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; + assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; + assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; + assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; + assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; + assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; + assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; + assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; + assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; + assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; + assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; + assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; + assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; + assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; + assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; + assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; + assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; + assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; + assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; + assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; + assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; + assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; + assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; + assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; + assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; + assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; + assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; + assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; + assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; + assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; + assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; + assign switch_units__recv__msg[1][5] = route_units__send__msg[5][1]; + assign route_units__send__rdy[5][1] = switch_units__recv__rdy[1][5]; + assign switch_units__recv__val[1][5] = route_units__send__val[5][1]; + assign switch_units__recv__msg[2][5] = route_units__send__msg[5][2]; + assign route_units__send__rdy[5][2] = switch_units__recv__rdy[2][5]; + assign switch_units__recv__val[2][5] = route_units__send__val[5][2]; + assign output_units__recv__msg[0] = switch_units__send__msg[0]; + assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; + assign output_units__recv__val[0] = switch_units__send__val[0]; + assign send__en[0] = output_units__send__en[0]; + assign send__msg[0] = output_units__send__msg[0]; + assign output_units__send__yum[0][0] = send__yum[0][0]; + assign output_units__send__yum[0][1] = send__yum[0][1]; + assign output_units__recv__msg[1] = switch_units__send__msg[1]; + assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; + assign output_units__recv__val[1] = switch_units__send__val[1]; + assign send__en[1] = output_units__send__en[1]; + assign send__msg[1] = output_units__send__msg[1]; + assign output_units__send__yum[1][0] = send__yum[1][0]; + assign output_units__send__yum[1][1] = send__yum[1][1]; + assign output_units__recv__msg[2] = switch_units__send__msg[2]; + assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; + assign output_units__recv__val[2] = switch_units__send__val[2]; + assign send__en[2] = output_units__send__en[2]; + assign send__msg[2] = output_units__send__msg[2]; + assign output_units__send__yum[2][0] = send__yum[2][0]; + assign output_units__send__yum[2][1] = send__yum[2][1]; + +endmodule + + +// PyMTL Component RegEnRst Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py + +module RegEnRst__Type_Bits2__reset_value_1 +( + input logic [0:0] clk , + input logic [0:0] en , + input logic [1:0] in_ , + output logic [1:0] out , + input logic [0:0] reset +); + localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 + // @update_ff + // def up_regenrst(): + // if s.reset: s.out <<= reset_value + // elif s.en: s.out <<= s.in_ + + always_ff @(posedge clk) begin : up_regenrst + if ( reset ) begin + out <= 2'( __const__reset_value_at_up_regenrst ); + end + else if ( en ) begin + out <= in_; + end + end + +endmodule + + +// PyMTL Component RoundRobinArbiterEn Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py + +module RoundRobinArbiterEn__nreqs_2 +( + input logic [0:0] clk , + input logic [0:0] en , + output logic [1:0] grants , + input logic [1:0] reqs , + input logic [0:0] reset +); + localparam logic [1:0] __const__nreqs_at_comb_reqs_int = 2'd2; + localparam logic [2:0] __const__nreqsX2_at_comb_reqs_int = 3'd4; + localparam logic [1:0] __const__nreqs_at_comb_grants = 2'd2; + localparam logic [1:0] __const__nreqs_at_comb_priority_int = 2'd2; + localparam logic [2:0] __const__nreqsX2_at_comb_priority_int = 3'd4; + localparam logic [2:0] __const__nreqsX2_at_comb_kills = 3'd4; + localparam logic [2:0] __const__nreqsX2_at_comb_grants_int = 3'd4; + logic [3:0] grants_int; + logic [4:0] kills; + logic [0:0] priority_en; + logic [3:0] priority_int; + logic [3:0] reqs_int; + //------------------------------------------------------------- + // Component priority_reg + //------------------------------------------------------------- + + logic [0:0] priority_reg__clk; + logic [0:0] priority_reg__en; + logic [1:0] priority_reg__in_; + logic [1:0] priority_reg__out; + logic [0:0] priority_reg__reset; + + RegEnRst__Type_Bits2__reset_value_1 priority_reg + ( + .clk( priority_reg__clk ), + .en( priority_reg__en ), + .in_( priority_reg__in_ ), + .out( priority_reg__out ), + .reset( priority_reg__reset ) + ); + + //------------------------------------------------------------- + // End of component priority_reg + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 + // @update + // def comb_grants(): + // for i in range( nreqs ): + // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] + + always_comb begin : comb_grants + for ( int unsigned i = 1'd0; i < 2'( __const__nreqs_at_comb_grants ); i += 1'd1 ) + grants[1'(i)] = grants_int[2'(i)] | grants_int[2'( __const__nreqs_at_comb_grants ) + 2'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 + // @update + // def comb_grants_int(): + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.grants_int[i] @= s.reqs_int[i] + // else: + // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] + + always_comb begin : comb_grants_int + for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) + if ( priority_int[2'(i)] ) begin + grants_int[2'(i)] = reqs_int[2'(i)]; + end + else + grants_int[2'(i)] = ( ~kills[3'(i)] ) & reqs_int[2'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 + // @update + // def comb_kills(): + // s.kills[0] @= 1 + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.kills[i+1] @= s.reqs_int[i] + // else: + // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) + + always_comb begin : comb_kills + kills[3'd0] = 1'd1; + for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) + if ( priority_int[2'(i)] ) begin + kills[3'(i) + 3'd1] = reqs_int[2'(i)]; + end + else + kills[3'(i) + 3'd1] = kills[3'(i)] | ( ( ~kills[3'(i)] ) & reqs_int[2'(i)] ); + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 + // @update + // def comb_priority_en(): + // s.priority_en @= ( s.grants != 0 ) & s.en + + always_comb begin : comb_priority_en + priority_en = ( grants != 2'd0 ) & en; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 + // @update + // def comb_priority_int(): + // s.priority_int[ 0:nreqs ] @= s.priority_reg.out + // s.priority_int[nreqs:nreqsX2] @= 0 + + always_comb begin : comb_priority_int + priority_int[2'd1:2'd0] = priority_reg__out; + priority_int[2'd3:2'( __const__nreqs_at_comb_priority_int )] = 2'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 + // @update + // def comb_reqs_int(): + // s.reqs_int [ 0:nreqs ] @= s.reqs + // s.reqs_int [nreqs:nreqsX2] @= s.reqs + + always_comb begin : comb_reqs_int + reqs_int[2'd1:2'd0] = reqs; + reqs_int[2'd3:2'( __const__nreqs_at_comb_reqs_int )] = reqs; + end + + assign priority_reg__clk = clk; + assign priority_reg__reset = reset; + assign priority_reg__en = priority_en; + assign priority_reg__in_[1:1] = grants[0:0]; + assign priority_reg__in_[0:0] = grants[1:1]; + +endmodule + + +// PyMTL Component BypassQueueCtrlRTL Definition +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueCtrlRTL__num_entries_2 +( + input logic [0:0] clk , + output logic [1:0] count , + output logic [0:0] mux_sel , + output logic [0:0] raddr , + output logic [0:0] recv_rdy , + input logic [0:0] recv_val , + input logic [0:0] reset , + input logic [0:0] send_rdy , + output logic [0:0] send_val , + output logic [0:0] waddr , + output logic [0:0] wen +); + localparam logic [1:0] __const__num_entries_at__lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy = 2'd2; + localparam logic [1:0] __const__num_entries_at_up_reg = 2'd2; + logic [0:0] head; + logic [0:0] recv_xfer; + logic [0:0] send_xfer; + logic [0:0] tail; + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:645 + // s.mux_sel //= lambda: s.count == 0 + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_mux_sel + mux_sel = count == 2'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:642 + // s.recv_rdy //= lambda: s.count < num_entries + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy + recv_rdy = count < 2'( __const__num_entries_at__lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy ); + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:647 + // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_xfer + recv_xfer = recv_val & recv_rdy; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:643 + // s.send_val //= lambda: (s.count > 0) | s.recv_val + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_send_val + send_val = ( count > 2'd0 ) | recv_val; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:648 + // s.send_xfer //= lambda: s.send_val & s.send_rdy + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_send_xfer + send_xfer = send_val & send_rdy; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:650 + // @update_ff + // def up_reg(): + // + // if s.reset: + // s.head <<= 0 + // s.tail <<= 0 + // s.count <<= 0 + // + // else: + // if s.recv_xfer: + // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 + // + // if s.send_xfer: + // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 + // + // if s.recv_xfer & ~s.send_xfer: + // s.count <<= s.count + 1 + // if ~s.recv_xfer & s.send_xfer: + // s.count <<= s.count - 1 + + always_ff @(posedge clk) begin : up_reg + if ( reset ) begin + head <= 1'd0; + tail <= 1'd0; + count <= 2'd0; + end + else begin + if ( recv_xfer ) begin + tail <= ( tail < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? tail + 1'd1 : 1'd0; + end + if ( send_xfer ) begin + head <= ( head < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? head + 1'd1 : 1'd0; + end + if ( recv_xfer & ( ~send_xfer ) ) begin + count <= count + 2'd1; + end + if ( ( ~recv_xfer ) & send_xfer ) begin + count <= count - 2'd1; + end + end + end + + assign wen = recv_xfer; + assign waddr = tail; + assign raddr = head; + +endmodule + + +// PyMTL Component Mux Definition +// Full name: Mux__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ninputs_2 +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__4754a371c6cda085 +( + input logic [0:0] clk , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 in_ [0:1], + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 out , + input logic [0:0] reset , + input logic [0:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component BypassQueueDpathRTL Definition +// Full name: BypassQueueDpathRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueDpathRTL__a1c7a5a18a302c36 +( + input logic [0:0] clk , + input logic [0:0] mux_sel , + input logic [0:0] raddr , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_msg , + input logic [0:0] reset , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__in_ [0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__out; + logic [0:0] mux__reset; + logic [0:0] mux__sel; + + Mux__4754a371c6cda085 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__80167091524f71e4 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + assign mux__clk = clk; + assign mux__reset = reset; + assign mux__sel = mux_sel; + assign mux__in_[0] = rf__rdata[0]; + assign mux__in_[1] = recv_msg; + assign send_msg = mux__out; + +endmodule + + +// PyMTL Component BypassQueueRTL Definition +// Full name: BypassQueueRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueRTL__a1c7a5a18a302c36 +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__mux_sel; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + BypassQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .mux_sel( ctrl__mux_sel ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__mux_sel; + logic [0:0] dpath__raddr; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__recv_msg; + logic [0:0] dpath__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + BypassQueueDpathRTL__a1c7a5a18a302c36 dpath + ( + .clk( dpath__clk ), + .mux_sel( dpath__mux_sel ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign dpath__mux_sel = ctrl__mux_sel; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign count = ctrl__count; + assign dpath__recv_msg = recv__msg; + assign send__msg = dpath__send_msg; + +endmodule + + +// PyMTL Component Encoder Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py + +module Encoder__in_nbits_2__out_nbits_1 +( + input logic [0:0] clk , + input logic [1:0] in_ , + output logic [0:0] out , + input logic [0:0] reset +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 + // @update + // def encode(): + // s.out @= 0 + // for i in range( s.in_nbits ): + // if s.in_[i]: + // s.out @= i + + always_comb begin : encode + out = 1'd0; + for ( int unsigned i = 1'd0; i < 2'd2; i += 1'd1 ) + if ( in_[1'(i)] ) begin + out = 1'(i); + end + end + +endmodule + + +// PyMTL Component CreditRecvRTL2SendRTL Definition +// Full name: CreditRecvRTL2SendRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2__QType_BypassQueueRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py + +module CreditRecvRTL2SendRTL__0d4276a185d5c616 +( + input logic [0:0] clk , + input logic [0:0] reset , + input logic [0:0] recv__en , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__yum [0:1] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [1:0] __const__vc_at_up_enq = 2'd2; + localparam logic [1:0] __const__vc_at_up_deq_and_send = 2'd2; + localparam logic [1:0] __const__vc_at_up_yummy = 2'd2; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [1:0] arbiter__grants; + logic [1:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_2 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component buffers[0:1] + //------------------------------------------------------------- + + logic [0:0] buffers__clk [0:1]; + logic [1:0] buffers__count [0:1]; + logic [0:0] buffers__reset [0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__recv__msg [0:1]; + logic [0:0] buffers__recv__rdy [0:1]; + logic [0:0] buffers__recv__val [0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__send__msg [0:1]; + logic [0:0] buffers__send__rdy [0:1]; + logic [0:0] buffers__send__val [0:1]; + + BypassQueueRTL__a1c7a5a18a302c36 buffers__0 + ( + .clk( buffers__clk[0] ), + .count( buffers__count[0] ), + .reset( buffers__reset[0] ), + .recv__msg( buffers__recv__msg[0] ), + .recv__rdy( buffers__recv__rdy[0] ), + .recv__val( buffers__recv__val[0] ), + .send__msg( buffers__send__msg[0] ), + .send__rdy( buffers__send__rdy[0] ), + .send__val( buffers__send__val[0] ) + ); + + BypassQueueRTL__a1c7a5a18a302c36 buffers__1 + ( + .clk( buffers__clk[1] ), + .count( buffers__count[1] ), + .reset( buffers__reset[1] ), + .recv__msg( buffers__recv__msg[1] ), + .recv__rdy( buffers__recv__rdy[1] ), + .recv__val( buffers__recv__val[1] ), + .send__msg( buffers__send__msg[1] ), + .send__rdy( buffers__send__rdy[1] ), + .send__val( buffers__send__val[1] ) + ); + + //------------------------------------------------------------- + // End of component buffers[0:1] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [1:0] encoder__in_; + logic [0:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_2__out_nbits_1 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:205 + // @update + // def up_deq_and_send(): + // for i in range( vc ): + // s.buffers[i].send.rdy @= 0 + // + // s.send.msg @= s.buffers[ s.encoder.out ].send.msg + // + // if s.arbiter.grants > 0: + // s.send.val @= 1 + // s.buffers[ s.encoder.out ].send.rdy @= s.send.rdy + // else: + // s.send.val @= 0 + + always_comb begin : up_deq_and_send + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_deq_and_send ); i += 1'd1 ) + buffers__send__rdy[1'(i)] = 1'd0; + send__msg = buffers__send__msg[encoder__out]; + if ( arbiter__grants > 2'd0 ) begin + send__val = 1'd1; + buffers__send__rdy[encoder__out] = send__rdy; + end + else + send__val = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:194 + // @update + // def up_enq(): + // if s.recv.en: + // for i in range( vc ): + // s.buffers[i].recv.val @= ( s.recv.msg.vc_id == i ) + // else: + // for i in range( vc ): + // s.buffers[i].recv.val @= 0 + + always_comb begin : up_enq + if ( recv__en ) begin + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) + buffers__recv__val[1'(i)] = recv__msg.vc_id == 1'(i); + end + else + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) + buffers__recv__val[1'(i)] = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:218 + // @update + // def up_yummy(): + // for i in range( vc ): + // s.recv.yum[i] @= s.buffers[i].send.val & s.buffers[i].send.rdy + + always_comb begin : up_yummy + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_yummy ); i += 1'd1 ) + recv__yum[1'(i)] = buffers__send__val[1'(i)] & buffers__send__rdy[1'(i)]; + end + + assign buffers__clk[0] = clk; + assign buffers__reset[0] = reset; + assign buffers__clk[1] = clk; + assign buffers__reset[1] = reset; + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign buffers__recv__msg[0] = recv__msg; + assign arbiter__reqs[0:0] = buffers__send__val[0]; + assign buffers__recv__msg[1] = recv__msg; + assign arbiter__reqs[1:1] = buffers__send__val[1]; + assign encoder__in_ = arbiter__grants; + assign arbiter__en = send__val; + +endmodule + + +// PyMTL Component RingNetworkRTL Definition +// Full name: RingNetworkRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17__chl_lat_1__vc_2__credit_line_2 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingNetworkRTL.py + +module RingNetworkRTL__8866f4e00dbc912a +( + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:16] , + output logic [0:0] recv__rdy [0:16] , + input logic [0:0] recv__val [0:16] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:16] , + input logic [0:0] send__rdy [0:16] , + output logic [0:0] send__val [0:16] +); + //------------------------------------------------------------- + // Component recv_adp[0:16] + //------------------------------------------------------------- + + logic [0:0] recv_adp__clk [0:16]; + logic [0:0] recv_adp__reset [0:16]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_adp__recv__msg [0:16]; + logic [0:0] recv_adp__recv__rdy [0:16]; + logic [0:0] recv_adp__recv__val [0:16]; + logic [0:0] recv_adp__send__en [0:16]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_adp__send__msg [0:16]; + logic [0:0] recv_adp__send__yum [0:16][0:1]; + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__0 + ( + .clk( recv_adp__clk[0] ), + .reset( recv_adp__reset[0] ), + .recv__msg( recv_adp__recv__msg[0] ), + .recv__rdy( recv_adp__recv__rdy[0] ), + .recv__val( recv_adp__recv__val[0] ), + .send__en( recv_adp__send__en[0] ), + .send__msg( recv_adp__send__msg[0] ), + .send__yum( recv_adp__send__yum[0] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__1 + ( + .clk( recv_adp__clk[1] ), + .reset( recv_adp__reset[1] ), + .recv__msg( recv_adp__recv__msg[1] ), + .recv__rdy( recv_adp__recv__rdy[1] ), + .recv__val( recv_adp__recv__val[1] ), + .send__en( recv_adp__send__en[1] ), + .send__msg( recv_adp__send__msg[1] ), + .send__yum( recv_adp__send__yum[1] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__2 + ( + .clk( recv_adp__clk[2] ), + .reset( recv_adp__reset[2] ), + .recv__msg( recv_adp__recv__msg[2] ), + .recv__rdy( recv_adp__recv__rdy[2] ), + .recv__val( recv_adp__recv__val[2] ), + .send__en( recv_adp__send__en[2] ), + .send__msg( recv_adp__send__msg[2] ), + .send__yum( recv_adp__send__yum[2] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__3 + ( + .clk( recv_adp__clk[3] ), + .reset( recv_adp__reset[3] ), + .recv__msg( recv_adp__recv__msg[3] ), + .recv__rdy( recv_adp__recv__rdy[3] ), + .recv__val( recv_adp__recv__val[3] ), + .send__en( recv_adp__send__en[3] ), + .send__msg( recv_adp__send__msg[3] ), + .send__yum( recv_adp__send__yum[3] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__4 + ( + .clk( recv_adp__clk[4] ), + .reset( recv_adp__reset[4] ), + .recv__msg( recv_adp__recv__msg[4] ), + .recv__rdy( recv_adp__recv__rdy[4] ), + .recv__val( recv_adp__recv__val[4] ), + .send__en( recv_adp__send__en[4] ), + .send__msg( recv_adp__send__msg[4] ), + .send__yum( recv_adp__send__yum[4] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__5 + ( + .clk( recv_adp__clk[5] ), + .reset( recv_adp__reset[5] ), + .recv__msg( recv_adp__recv__msg[5] ), + .recv__rdy( recv_adp__recv__rdy[5] ), + .recv__val( recv_adp__recv__val[5] ), + .send__en( recv_adp__send__en[5] ), + .send__msg( recv_adp__send__msg[5] ), + .send__yum( recv_adp__send__yum[5] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__6 + ( + .clk( recv_adp__clk[6] ), + .reset( recv_adp__reset[6] ), + .recv__msg( recv_adp__recv__msg[6] ), + .recv__rdy( recv_adp__recv__rdy[6] ), + .recv__val( recv_adp__recv__val[6] ), + .send__en( recv_adp__send__en[6] ), + .send__msg( recv_adp__send__msg[6] ), + .send__yum( recv_adp__send__yum[6] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__7 + ( + .clk( recv_adp__clk[7] ), + .reset( recv_adp__reset[7] ), + .recv__msg( recv_adp__recv__msg[7] ), + .recv__rdy( recv_adp__recv__rdy[7] ), + .recv__val( recv_adp__recv__val[7] ), + .send__en( recv_adp__send__en[7] ), + .send__msg( recv_adp__send__msg[7] ), + .send__yum( recv_adp__send__yum[7] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__8 + ( + .clk( recv_adp__clk[8] ), + .reset( recv_adp__reset[8] ), + .recv__msg( recv_adp__recv__msg[8] ), + .recv__rdy( recv_adp__recv__rdy[8] ), + .recv__val( recv_adp__recv__val[8] ), + .send__en( recv_adp__send__en[8] ), + .send__msg( recv_adp__send__msg[8] ), + .send__yum( recv_adp__send__yum[8] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__9 + ( + .clk( recv_adp__clk[9] ), + .reset( recv_adp__reset[9] ), + .recv__msg( recv_adp__recv__msg[9] ), + .recv__rdy( recv_adp__recv__rdy[9] ), + .recv__val( recv_adp__recv__val[9] ), + .send__en( recv_adp__send__en[9] ), + .send__msg( recv_adp__send__msg[9] ), + .send__yum( recv_adp__send__yum[9] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__10 + ( + .clk( recv_adp__clk[10] ), + .reset( recv_adp__reset[10] ), + .recv__msg( recv_adp__recv__msg[10] ), + .recv__rdy( recv_adp__recv__rdy[10] ), + .recv__val( recv_adp__recv__val[10] ), + .send__en( recv_adp__send__en[10] ), + .send__msg( recv_adp__send__msg[10] ), + .send__yum( recv_adp__send__yum[10] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__11 + ( + .clk( recv_adp__clk[11] ), + .reset( recv_adp__reset[11] ), + .recv__msg( recv_adp__recv__msg[11] ), + .recv__rdy( recv_adp__recv__rdy[11] ), + .recv__val( recv_adp__recv__val[11] ), + .send__en( recv_adp__send__en[11] ), + .send__msg( recv_adp__send__msg[11] ), + .send__yum( recv_adp__send__yum[11] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__12 + ( + .clk( recv_adp__clk[12] ), + .reset( recv_adp__reset[12] ), + .recv__msg( recv_adp__recv__msg[12] ), + .recv__rdy( recv_adp__recv__rdy[12] ), + .recv__val( recv_adp__recv__val[12] ), + .send__en( recv_adp__send__en[12] ), + .send__msg( recv_adp__send__msg[12] ), + .send__yum( recv_adp__send__yum[12] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__13 + ( + .clk( recv_adp__clk[13] ), + .reset( recv_adp__reset[13] ), + .recv__msg( recv_adp__recv__msg[13] ), + .recv__rdy( recv_adp__recv__rdy[13] ), + .recv__val( recv_adp__recv__val[13] ), + .send__en( recv_adp__send__en[13] ), + .send__msg( recv_adp__send__msg[13] ), + .send__yum( recv_adp__send__yum[13] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__14 + ( + .clk( recv_adp__clk[14] ), + .reset( recv_adp__reset[14] ), + .recv__msg( recv_adp__recv__msg[14] ), + .recv__rdy( recv_adp__recv__rdy[14] ), + .recv__val( recv_adp__recv__val[14] ), + .send__en( recv_adp__send__en[14] ), + .send__msg( recv_adp__send__msg[14] ), + .send__yum( recv_adp__send__yum[14] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__15 + ( + .clk( recv_adp__clk[15] ), + .reset( recv_adp__reset[15] ), + .recv__msg( recv_adp__recv__msg[15] ), + .recv__rdy( recv_adp__recv__rdy[15] ), + .recv__val( recv_adp__recv__val[15] ), + .send__en( recv_adp__send__en[15] ), + .send__msg( recv_adp__send__msg[15] ), + .send__yum( recv_adp__send__yum[15] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__16 + ( + .clk( recv_adp__clk[16] ), + .reset( recv_adp__reset[16] ), + .recv__msg( recv_adp__recv__msg[16] ), + .recv__rdy( recv_adp__recv__rdy[16] ), + .recv__val( recv_adp__recv__val[16] ), + .send__en( recv_adp__send__en[16] ), + .send__msg( recv_adp__send__msg[16] ), + .send__yum( recv_adp__send__yum[16] ) + ); + + //------------------------------------------------------------- + // End of component recv_adp[0:16] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component routers[0:16] + //------------------------------------------------------------- + + logic [0:0] routers__clk [0:16]; + logic [4:0] routers__pos [0:16]; + logic [0:0] routers__reset [0:16]; + logic [0:0] routers__recv__en [0:16][0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 routers__recv__msg [0:16][0:2]; + logic [0:0] routers__recv__yum [0:16][0:2][0:1]; + logic [0:0] routers__send__en [0:16][0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 routers__send__msg [0:16][0:2]; + logic [0:0] routers__send__yum [0:16][0:2][0:1]; + + RingRouterRTL__6e670e447e1766e0 routers__0 + ( + .clk( routers__clk[0] ), + .pos( routers__pos[0] ), + .reset( routers__reset[0] ), + .recv__en( routers__recv__en[0] ), + .recv__msg( routers__recv__msg[0] ), + .recv__yum( routers__recv__yum[0] ), + .send__en( routers__send__en[0] ), + .send__msg( routers__send__msg[0] ), + .send__yum( routers__send__yum[0] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__1 + ( + .clk( routers__clk[1] ), + .pos( routers__pos[1] ), + .reset( routers__reset[1] ), + .recv__en( routers__recv__en[1] ), + .recv__msg( routers__recv__msg[1] ), + .recv__yum( routers__recv__yum[1] ), + .send__en( routers__send__en[1] ), + .send__msg( routers__send__msg[1] ), + .send__yum( routers__send__yum[1] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__2 + ( + .clk( routers__clk[2] ), + .pos( routers__pos[2] ), + .reset( routers__reset[2] ), + .recv__en( routers__recv__en[2] ), + .recv__msg( routers__recv__msg[2] ), + .recv__yum( routers__recv__yum[2] ), + .send__en( routers__send__en[2] ), + .send__msg( routers__send__msg[2] ), + .send__yum( routers__send__yum[2] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__3 + ( + .clk( routers__clk[3] ), + .pos( routers__pos[3] ), + .reset( routers__reset[3] ), + .recv__en( routers__recv__en[3] ), + .recv__msg( routers__recv__msg[3] ), + .recv__yum( routers__recv__yum[3] ), + .send__en( routers__send__en[3] ), + .send__msg( routers__send__msg[3] ), + .send__yum( routers__send__yum[3] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__4 + ( + .clk( routers__clk[4] ), + .pos( routers__pos[4] ), + .reset( routers__reset[4] ), + .recv__en( routers__recv__en[4] ), + .recv__msg( routers__recv__msg[4] ), + .recv__yum( routers__recv__yum[4] ), + .send__en( routers__send__en[4] ), + .send__msg( routers__send__msg[4] ), + .send__yum( routers__send__yum[4] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__5 + ( + .clk( routers__clk[5] ), + .pos( routers__pos[5] ), + .reset( routers__reset[5] ), + .recv__en( routers__recv__en[5] ), + .recv__msg( routers__recv__msg[5] ), + .recv__yum( routers__recv__yum[5] ), + .send__en( routers__send__en[5] ), + .send__msg( routers__send__msg[5] ), + .send__yum( routers__send__yum[5] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__6 + ( + .clk( routers__clk[6] ), + .pos( routers__pos[6] ), + .reset( routers__reset[6] ), + .recv__en( routers__recv__en[6] ), + .recv__msg( routers__recv__msg[6] ), + .recv__yum( routers__recv__yum[6] ), + .send__en( routers__send__en[6] ), + .send__msg( routers__send__msg[6] ), + .send__yum( routers__send__yum[6] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__7 + ( + .clk( routers__clk[7] ), + .pos( routers__pos[7] ), + .reset( routers__reset[7] ), + .recv__en( routers__recv__en[7] ), + .recv__msg( routers__recv__msg[7] ), + .recv__yum( routers__recv__yum[7] ), + .send__en( routers__send__en[7] ), + .send__msg( routers__send__msg[7] ), + .send__yum( routers__send__yum[7] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__8 + ( + .clk( routers__clk[8] ), + .pos( routers__pos[8] ), + .reset( routers__reset[8] ), + .recv__en( routers__recv__en[8] ), + .recv__msg( routers__recv__msg[8] ), + .recv__yum( routers__recv__yum[8] ), + .send__en( routers__send__en[8] ), + .send__msg( routers__send__msg[8] ), + .send__yum( routers__send__yum[8] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__9 + ( + .clk( routers__clk[9] ), + .pos( routers__pos[9] ), + .reset( routers__reset[9] ), + .recv__en( routers__recv__en[9] ), + .recv__msg( routers__recv__msg[9] ), + .recv__yum( routers__recv__yum[9] ), + .send__en( routers__send__en[9] ), + .send__msg( routers__send__msg[9] ), + .send__yum( routers__send__yum[9] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__10 + ( + .clk( routers__clk[10] ), + .pos( routers__pos[10] ), + .reset( routers__reset[10] ), + .recv__en( routers__recv__en[10] ), + .recv__msg( routers__recv__msg[10] ), + .recv__yum( routers__recv__yum[10] ), + .send__en( routers__send__en[10] ), + .send__msg( routers__send__msg[10] ), + .send__yum( routers__send__yum[10] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__11 + ( + .clk( routers__clk[11] ), + .pos( routers__pos[11] ), + .reset( routers__reset[11] ), + .recv__en( routers__recv__en[11] ), + .recv__msg( routers__recv__msg[11] ), + .recv__yum( routers__recv__yum[11] ), + .send__en( routers__send__en[11] ), + .send__msg( routers__send__msg[11] ), + .send__yum( routers__send__yum[11] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__12 + ( + .clk( routers__clk[12] ), + .pos( routers__pos[12] ), + .reset( routers__reset[12] ), + .recv__en( routers__recv__en[12] ), + .recv__msg( routers__recv__msg[12] ), + .recv__yum( routers__recv__yum[12] ), + .send__en( routers__send__en[12] ), + .send__msg( routers__send__msg[12] ), + .send__yum( routers__send__yum[12] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__13 + ( + .clk( routers__clk[13] ), + .pos( routers__pos[13] ), + .reset( routers__reset[13] ), + .recv__en( routers__recv__en[13] ), + .recv__msg( routers__recv__msg[13] ), + .recv__yum( routers__recv__yum[13] ), + .send__en( routers__send__en[13] ), + .send__msg( routers__send__msg[13] ), + .send__yum( routers__send__yum[13] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__14 + ( + .clk( routers__clk[14] ), + .pos( routers__pos[14] ), + .reset( routers__reset[14] ), + .recv__en( routers__recv__en[14] ), + .recv__msg( routers__recv__msg[14] ), + .recv__yum( routers__recv__yum[14] ), + .send__en( routers__send__en[14] ), + .send__msg( routers__send__msg[14] ), + .send__yum( routers__send__yum[14] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__15 + ( + .clk( routers__clk[15] ), + .pos( routers__pos[15] ), + .reset( routers__reset[15] ), + .recv__en( routers__recv__en[15] ), + .recv__msg( routers__recv__msg[15] ), + .recv__yum( routers__recv__yum[15] ), + .send__en( routers__send__en[15] ), + .send__msg( routers__send__msg[15] ), + .send__yum( routers__send__yum[15] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__16 + ( + .clk( routers__clk[16] ), + .pos( routers__pos[16] ), + .reset( routers__reset[16] ), + .recv__en( routers__recv__en[16] ), + .recv__msg( routers__recv__msg[16] ), + .recv__yum( routers__recv__yum[16] ), + .send__en( routers__send__en[16] ), + .send__msg( routers__send__msg[16] ), + .send__yum( routers__send__yum[16] ) + ); + + //------------------------------------------------------------- + // End of component routers[0:16] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component send_adp[0:16] + //------------------------------------------------------------- + + logic [0:0] send_adp__clk [0:16]; + logic [0:0] send_adp__reset [0:16]; + logic [0:0] send_adp__recv__en [0:16]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_adp__recv__msg [0:16]; + logic [0:0] send_adp__recv__yum [0:16][0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_adp__send__msg [0:16]; + logic [0:0] send_adp__send__rdy [0:16]; + logic [0:0] send_adp__send__val [0:16]; + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__0 + ( + .clk( send_adp__clk[0] ), + .reset( send_adp__reset[0] ), + .recv__en( send_adp__recv__en[0] ), + .recv__msg( send_adp__recv__msg[0] ), + .recv__yum( send_adp__recv__yum[0] ), + .send__msg( send_adp__send__msg[0] ), + .send__rdy( send_adp__send__rdy[0] ), + .send__val( send_adp__send__val[0] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__1 + ( + .clk( send_adp__clk[1] ), + .reset( send_adp__reset[1] ), + .recv__en( send_adp__recv__en[1] ), + .recv__msg( send_adp__recv__msg[1] ), + .recv__yum( send_adp__recv__yum[1] ), + .send__msg( send_adp__send__msg[1] ), + .send__rdy( send_adp__send__rdy[1] ), + .send__val( send_adp__send__val[1] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__2 + ( + .clk( send_adp__clk[2] ), + .reset( send_adp__reset[2] ), + .recv__en( send_adp__recv__en[2] ), + .recv__msg( send_adp__recv__msg[2] ), + .recv__yum( send_adp__recv__yum[2] ), + .send__msg( send_adp__send__msg[2] ), + .send__rdy( send_adp__send__rdy[2] ), + .send__val( send_adp__send__val[2] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__3 + ( + .clk( send_adp__clk[3] ), + .reset( send_adp__reset[3] ), + .recv__en( send_adp__recv__en[3] ), + .recv__msg( send_adp__recv__msg[3] ), + .recv__yum( send_adp__recv__yum[3] ), + .send__msg( send_adp__send__msg[3] ), + .send__rdy( send_adp__send__rdy[3] ), + .send__val( send_adp__send__val[3] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__4 + ( + .clk( send_adp__clk[4] ), + .reset( send_adp__reset[4] ), + .recv__en( send_adp__recv__en[4] ), + .recv__msg( send_adp__recv__msg[4] ), + .recv__yum( send_adp__recv__yum[4] ), + .send__msg( send_adp__send__msg[4] ), + .send__rdy( send_adp__send__rdy[4] ), + .send__val( send_adp__send__val[4] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__5 + ( + .clk( send_adp__clk[5] ), + .reset( send_adp__reset[5] ), + .recv__en( send_adp__recv__en[5] ), + .recv__msg( send_adp__recv__msg[5] ), + .recv__yum( send_adp__recv__yum[5] ), + .send__msg( send_adp__send__msg[5] ), + .send__rdy( send_adp__send__rdy[5] ), + .send__val( send_adp__send__val[5] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__6 + ( + .clk( send_adp__clk[6] ), + .reset( send_adp__reset[6] ), + .recv__en( send_adp__recv__en[6] ), + .recv__msg( send_adp__recv__msg[6] ), + .recv__yum( send_adp__recv__yum[6] ), + .send__msg( send_adp__send__msg[6] ), + .send__rdy( send_adp__send__rdy[6] ), + .send__val( send_adp__send__val[6] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__7 + ( + .clk( send_adp__clk[7] ), + .reset( send_adp__reset[7] ), + .recv__en( send_adp__recv__en[7] ), + .recv__msg( send_adp__recv__msg[7] ), + .recv__yum( send_adp__recv__yum[7] ), + .send__msg( send_adp__send__msg[7] ), + .send__rdy( send_adp__send__rdy[7] ), + .send__val( send_adp__send__val[7] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__8 + ( + .clk( send_adp__clk[8] ), + .reset( send_adp__reset[8] ), + .recv__en( send_adp__recv__en[8] ), + .recv__msg( send_adp__recv__msg[8] ), + .recv__yum( send_adp__recv__yum[8] ), + .send__msg( send_adp__send__msg[8] ), + .send__rdy( send_adp__send__rdy[8] ), + .send__val( send_adp__send__val[8] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__9 + ( + .clk( send_adp__clk[9] ), + .reset( send_adp__reset[9] ), + .recv__en( send_adp__recv__en[9] ), + .recv__msg( send_adp__recv__msg[9] ), + .recv__yum( send_adp__recv__yum[9] ), + .send__msg( send_adp__send__msg[9] ), + .send__rdy( send_adp__send__rdy[9] ), + .send__val( send_adp__send__val[9] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__10 + ( + .clk( send_adp__clk[10] ), + .reset( send_adp__reset[10] ), + .recv__en( send_adp__recv__en[10] ), + .recv__msg( send_adp__recv__msg[10] ), + .recv__yum( send_adp__recv__yum[10] ), + .send__msg( send_adp__send__msg[10] ), + .send__rdy( send_adp__send__rdy[10] ), + .send__val( send_adp__send__val[10] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__11 + ( + .clk( send_adp__clk[11] ), + .reset( send_adp__reset[11] ), + .recv__en( send_adp__recv__en[11] ), + .recv__msg( send_adp__recv__msg[11] ), + .recv__yum( send_adp__recv__yum[11] ), + .send__msg( send_adp__send__msg[11] ), + .send__rdy( send_adp__send__rdy[11] ), + .send__val( send_adp__send__val[11] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__12 + ( + .clk( send_adp__clk[12] ), + .reset( send_adp__reset[12] ), + .recv__en( send_adp__recv__en[12] ), + .recv__msg( send_adp__recv__msg[12] ), + .recv__yum( send_adp__recv__yum[12] ), + .send__msg( send_adp__send__msg[12] ), + .send__rdy( send_adp__send__rdy[12] ), + .send__val( send_adp__send__val[12] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__13 + ( + .clk( send_adp__clk[13] ), + .reset( send_adp__reset[13] ), + .recv__en( send_adp__recv__en[13] ), + .recv__msg( send_adp__recv__msg[13] ), + .recv__yum( send_adp__recv__yum[13] ), + .send__msg( send_adp__send__msg[13] ), + .send__rdy( send_adp__send__rdy[13] ), + .send__val( send_adp__send__val[13] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__14 + ( + .clk( send_adp__clk[14] ), + .reset( send_adp__reset[14] ), + .recv__en( send_adp__recv__en[14] ), + .recv__msg( send_adp__recv__msg[14] ), + .recv__yum( send_adp__recv__yum[14] ), + .send__msg( send_adp__send__msg[14] ), + .send__rdy( send_adp__send__rdy[14] ), + .send__val( send_adp__send__val[14] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__15 + ( + .clk( send_adp__clk[15] ), + .reset( send_adp__reset[15] ), + .recv__en( send_adp__recv__en[15] ), + .recv__msg( send_adp__recv__msg[15] ), + .recv__yum( send_adp__recv__yum[15] ), + .send__msg( send_adp__send__msg[15] ), + .send__rdy( send_adp__send__rdy[15] ), + .send__val( send_adp__send__val[15] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__16 + ( + .clk( send_adp__clk[16] ), + .reset( send_adp__reset[16] ), + .recv__en( send_adp__recv__en[16] ), + .recv__msg( send_adp__recv__msg[16] ), + .recv__yum( send_adp__recv__yum[16] ), + .send__msg( send_adp__send__msg[16] ), + .send__rdy( send_adp__send__rdy[16] ), + .send__val( send_adp__send__val[16] ) + ); + + //------------------------------------------------------------- + // End of component send_adp[0:16] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingNetworkRTL.py:58 + // @update + // def up_pos(): + // for r in range( s.num_routers ): + // s.routers[r].pos @= r + + always_comb begin : up_pos + for ( int unsigned r = 1'd0; r < 5'd17; r += 1'd1 ) + routers__pos[5'(r)] = 5'(r); + end + + assign routers__clk[0] = clk; + assign routers__reset[0] = reset; + assign routers__clk[1] = clk; + assign routers__reset[1] = reset; + assign routers__clk[2] = clk; + assign routers__reset[2] = reset; + assign routers__clk[3] = clk; + assign routers__reset[3] = reset; + assign routers__clk[4] = clk; + assign routers__reset[4] = reset; + assign routers__clk[5] = clk; + assign routers__reset[5] = reset; + assign routers__clk[6] = clk; + assign routers__reset[6] = reset; + assign routers__clk[7] = clk; + assign routers__reset[7] = reset; + assign routers__clk[8] = clk; + assign routers__reset[8] = reset; + assign routers__clk[9] = clk; + assign routers__reset[9] = reset; + assign routers__clk[10] = clk; + assign routers__reset[10] = reset; + assign routers__clk[11] = clk; + assign routers__reset[11] = reset; + assign routers__clk[12] = clk; + assign routers__reset[12] = reset; + assign routers__clk[13] = clk; + assign routers__reset[13] = reset; + assign routers__clk[14] = clk; + assign routers__reset[14] = reset; + assign routers__clk[15] = clk; + assign routers__reset[15] = reset; + assign routers__clk[16] = clk; + assign routers__reset[16] = reset; + assign recv_adp__clk[0] = clk; + assign recv_adp__reset[0] = reset; + assign recv_adp__clk[1] = clk; + assign recv_adp__reset[1] = reset; + assign recv_adp__clk[2] = clk; + assign recv_adp__reset[2] = reset; + assign recv_adp__clk[3] = clk; + assign recv_adp__reset[3] = reset; + assign recv_adp__clk[4] = clk; + assign recv_adp__reset[4] = reset; + assign recv_adp__clk[5] = clk; + assign recv_adp__reset[5] = reset; + assign recv_adp__clk[6] = clk; + assign recv_adp__reset[6] = reset; + assign recv_adp__clk[7] = clk; + assign recv_adp__reset[7] = reset; + assign recv_adp__clk[8] = clk; + assign recv_adp__reset[8] = reset; + assign recv_adp__clk[9] = clk; + assign recv_adp__reset[9] = reset; + assign recv_adp__clk[10] = clk; + assign recv_adp__reset[10] = reset; + assign recv_adp__clk[11] = clk; + assign recv_adp__reset[11] = reset; + assign recv_adp__clk[12] = clk; + assign recv_adp__reset[12] = reset; + assign recv_adp__clk[13] = clk; + assign recv_adp__reset[13] = reset; + assign recv_adp__clk[14] = clk; + assign recv_adp__reset[14] = reset; + assign recv_adp__clk[15] = clk; + assign recv_adp__reset[15] = reset; + assign recv_adp__clk[16] = clk; + assign recv_adp__reset[16] = reset; + assign send_adp__clk[0] = clk; + assign send_adp__reset[0] = reset; + assign send_adp__clk[1] = clk; + assign send_adp__reset[1] = reset; + assign send_adp__clk[2] = clk; + assign send_adp__reset[2] = reset; + assign send_adp__clk[3] = clk; + assign send_adp__reset[3] = reset; + assign send_adp__clk[4] = clk; + assign send_adp__reset[4] = reset; + assign send_adp__clk[5] = clk; + assign send_adp__reset[5] = reset; + assign send_adp__clk[6] = clk; + assign send_adp__reset[6] = reset; + assign send_adp__clk[7] = clk; + assign send_adp__reset[7] = reset; + assign send_adp__clk[8] = clk; + assign send_adp__reset[8] = reset; + assign send_adp__clk[9] = clk; + assign send_adp__reset[9] = reset; + assign send_adp__clk[10] = clk; + assign send_adp__reset[10] = reset; + assign send_adp__clk[11] = clk; + assign send_adp__reset[11] = reset; + assign send_adp__clk[12] = clk; + assign send_adp__reset[12] = reset; + assign send_adp__clk[13] = clk; + assign send_adp__reset[13] = reset; + assign send_adp__clk[14] = clk; + assign send_adp__reset[14] = reset; + assign send_adp__clk[15] = clk; + assign send_adp__reset[15] = reset; + assign send_adp__clk[16] = clk; + assign send_adp__reset[16] = reset; + assign routers__recv__en[1][0] = routers__send__en[0][1]; + assign routers__recv__msg[1][0] = routers__send__msg[0][1]; + assign routers__send__yum[0][1][0] = routers__recv__yum[1][0][0]; + assign routers__send__yum[0][1][1] = routers__recv__yum[1][0][1]; + assign routers__recv__en[0][1] = routers__send__en[1][0]; + assign routers__recv__msg[0][1] = routers__send__msg[1][0]; + assign routers__send__yum[1][0][0] = routers__recv__yum[0][1][0]; + assign routers__send__yum[1][0][1] = routers__recv__yum[0][1][1]; + assign recv_adp__recv__msg[0] = recv__msg[0]; + assign recv__rdy[0] = recv_adp__recv__rdy[0]; + assign recv_adp__recv__val[0] = recv__val[0]; + assign routers__recv__en[0][2] = recv_adp__send__en[0]; + assign routers__recv__msg[0][2] = recv_adp__send__msg[0]; + assign recv_adp__send__yum[0][0] = routers__recv__yum[0][2][0]; + assign recv_adp__send__yum[0][1] = routers__recv__yum[0][2][1]; + assign send_adp__recv__en[0] = routers__send__en[0][2]; + assign send_adp__recv__msg[0] = routers__send__msg[0][2]; + assign routers__send__yum[0][2][0] = send_adp__recv__yum[0][0]; + assign routers__send__yum[0][2][1] = send_adp__recv__yum[0][1]; + assign send__msg[0] = send_adp__send__msg[0]; + assign send_adp__send__rdy[0] = send__rdy[0]; + assign send__val[0] = send_adp__send__val[0]; + assign routers__recv__en[2][0] = routers__send__en[1][1]; + assign routers__recv__msg[2][0] = routers__send__msg[1][1]; + assign routers__send__yum[1][1][0] = routers__recv__yum[2][0][0]; + assign routers__send__yum[1][1][1] = routers__recv__yum[2][0][1]; + assign routers__recv__en[1][1] = routers__send__en[2][0]; + assign routers__recv__msg[1][1] = routers__send__msg[2][0]; + assign routers__send__yum[2][0][0] = routers__recv__yum[1][1][0]; + assign routers__send__yum[2][0][1] = routers__recv__yum[1][1][1]; + assign recv_adp__recv__msg[1] = recv__msg[1]; + assign recv__rdy[1] = recv_adp__recv__rdy[1]; + assign recv_adp__recv__val[1] = recv__val[1]; + assign routers__recv__en[1][2] = recv_adp__send__en[1]; + assign routers__recv__msg[1][2] = recv_adp__send__msg[1]; + assign recv_adp__send__yum[1][0] = routers__recv__yum[1][2][0]; + assign recv_adp__send__yum[1][1] = routers__recv__yum[1][2][1]; + assign send_adp__recv__en[1] = routers__send__en[1][2]; + assign send_adp__recv__msg[1] = routers__send__msg[1][2]; + assign routers__send__yum[1][2][0] = send_adp__recv__yum[1][0]; + assign routers__send__yum[1][2][1] = send_adp__recv__yum[1][1]; + assign send__msg[1] = send_adp__send__msg[1]; + assign send_adp__send__rdy[1] = send__rdy[1]; + assign send__val[1] = send_adp__send__val[1]; + assign routers__recv__en[3][0] = routers__send__en[2][1]; + assign routers__recv__msg[3][0] = routers__send__msg[2][1]; + assign routers__send__yum[2][1][0] = routers__recv__yum[3][0][0]; + assign routers__send__yum[2][1][1] = routers__recv__yum[3][0][1]; + assign routers__recv__en[2][1] = routers__send__en[3][0]; + assign routers__recv__msg[2][1] = routers__send__msg[3][0]; + assign routers__send__yum[3][0][0] = routers__recv__yum[2][1][0]; + assign routers__send__yum[3][0][1] = routers__recv__yum[2][1][1]; + assign recv_adp__recv__msg[2] = recv__msg[2]; + assign recv__rdy[2] = recv_adp__recv__rdy[2]; + assign recv_adp__recv__val[2] = recv__val[2]; + assign routers__recv__en[2][2] = recv_adp__send__en[2]; + assign routers__recv__msg[2][2] = recv_adp__send__msg[2]; + assign recv_adp__send__yum[2][0] = routers__recv__yum[2][2][0]; + assign recv_adp__send__yum[2][1] = routers__recv__yum[2][2][1]; + assign send_adp__recv__en[2] = routers__send__en[2][2]; + assign send_adp__recv__msg[2] = routers__send__msg[2][2]; + assign routers__send__yum[2][2][0] = send_adp__recv__yum[2][0]; + assign routers__send__yum[2][2][1] = send_adp__recv__yum[2][1]; + assign send__msg[2] = send_adp__send__msg[2]; + assign send_adp__send__rdy[2] = send__rdy[2]; + assign send__val[2] = send_adp__send__val[2]; + assign routers__recv__en[4][0] = routers__send__en[3][1]; + assign routers__recv__msg[4][0] = routers__send__msg[3][1]; + assign routers__send__yum[3][1][0] = routers__recv__yum[4][0][0]; + assign routers__send__yum[3][1][1] = routers__recv__yum[4][0][1]; + assign routers__recv__en[3][1] = routers__send__en[4][0]; + assign routers__recv__msg[3][1] = routers__send__msg[4][0]; + assign routers__send__yum[4][0][0] = routers__recv__yum[3][1][0]; + assign routers__send__yum[4][0][1] = routers__recv__yum[3][1][1]; + assign recv_adp__recv__msg[3] = recv__msg[3]; + assign recv__rdy[3] = recv_adp__recv__rdy[3]; + assign recv_adp__recv__val[3] = recv__val[3]; + assign routers__recv__en[3][2] = recv_adp__send__en[3]; + assign routers__recv__msg[3][2] = recv_adp__send__msg[3]; + assign recv_adp__send__yum[3][0] = routers__recv__yum[3][2][0]; + assign recv_adp__send__yum[3][1] = routers__recv__yum[3][2][1]; + assign send_adp__recv__en[3] = routers__send__en[3][2]; + assign send_adp__recv__msg[3] = routers__send__msg[3][2]; + assign routers__send__yum[3][2][0] = send_adp__recv__yum[3][0]; + assign routers__send__yum[3][2][1] = send_adp__recv__yum[3][1]; + assign send__msg[3] = send_adp__send__msg[3]; + assign send_adp__send__rdy[3] = send__rdy[3]; + assign send__val[3] = send_adp__send__val[3]; + assign routers__recv__en[5][0] = routers__send__en[4][1]; + assign routers__recv__msg[5][0] = routers__send__msg[4][1]; + assign routers__send__yum[4][1][0] = routers__recv__yum[5][0][0]; + assign routers__send__yum[4][1][1] = routers__recv__yum[5][0][1]; + assign routers__recv__en[4][1] = routers__send__en[5][0]; + assign routers__recv__msg[4][1] = routers__send__msg[5][0]; + assign routers__send__yum[5][0][0] = routers__recv__yum[4][1][0]; + assign routers__send__yum[5][0][1] = routers__recv__yum[4][1][1]; + assign recv_adp__recv__msg[4] = recv__msg[4]; + assign recv__rdy[4] = recv_adp__recv__rdy[4]; + assign recv_adp__recv__val[4] = recv__val[4]; + assign routers__recv__en[4][2] = recv_adp__send__en[4]; + assign routers__recv__msg[4][2] = recv_adp__send__msg[4]; + assign recv_adp__send__yum[4][0] = routers__recv__yum[4][2][0]; + assign recv_adp__send__yum[4][1] = routers__recv__yum[4][2][1]; + assign send_adp__recv__en[4] = routers__send__en[4][2]; + assign send_adp__recv__msg[4] = routers__send__msg[4][2]; + assign routers__send__yum[4][2][0] = send_adp__recv__yum[4][0]; + assign routers__send__yum[4][2][1] = send_adp__recv__yum[4][1]; + assign send__msg[4] = send_adp__send__msg[4]; + assign send_adp__send__rdy[4] = send__rdy[4]; + assign send__val[4] = send_adp__send__val[4]; + assign routers__recv__en[6][0] = routers__send__en[5][1]; + assign routers__recv__msg[6][0] = routers__send__msg[5][1]; + assign routers__send__yum[5][1][0] = routers__recv__yum[6][0][0]; + assign routers__send__yum[5][1][1] = routers__recv__yum[6][0][1]; + assign routers__recv__en[5][1] = routers__send__en[6][0]; + assign routers__recv__msg[5][1] = routers__send__msg[6][0]; + assign routers__send__yum[6][0][0] = routers__recv__yum[5][1][0]; + assign routers__send__yum[6][0][1] = routers__recv__yum[5][1][1]; + assign recv_adp__recv__msg[5] = recv__msg[5]; + assign recv__rdy[5] = recv_adp__recv__rdy[5]; + assign recv_adp__recv__val[5] = recv__val[5]; + assign routers__recv__en[5][2] = recv_adp__send__en[5]; + assign routers__recv__msg[5][2] = recv_adp__send__msg[5]; + assign recv_adp__send__yum[5][0] = routers__recv__yum[5][2][0]; + assign recv_adp__send__yum[5][1] = routers__recv__yum[5][2][1]; + assign send_adp__recv__en[5] = routers__send__en[5][2]; + assign send_adp__recv__msg[5] = routers__send__msg[5][2]; + assign routers__send__yum[5][2][0] = send_adp__recv__yum[5][0]; + assign routers__send__yum[5][2][1] = send_adp__recv__yum[5][1]; + assign send__msg[5] = send_adp__send__msg[5]; + assign send_adp__send__rdy[5] = send__rdy[5]; + assign send__val[5] = send_adp__send__val[5]; + assign routers__recv__en[7][0] = routers__send__en[6][1]; + assign routers__recv__msg[7][0] = routers__send__msg[6][1]; + assign routers__send__yum[6][1][0] = routers__recv__yum[7][0][0]; + assign routers__send__yum[6][1][1] = routers__recv__yum[7][0][1]; + assign routers__recv__en[6][1] = routers__send__en[7][0]; + assign routers__recv__msg[6][1] = routers__send__msg[7][0]; + assign routers__send__yum[7][0][0] = routers__recv__yum[6][1][0]; + assign routers__send__yum[7][0][1] = routers__recv__yum[6][1][1]; + assign recv_adp__recv__msg[6] = recv__msg[6]; + assign recv__rdy[6] = recv_adp__recv__rdy[6]; + assign recv_adp__recv__val[6] = recv__val[6]; + assign routers__recv__en[6][2] = recv_adp__send__en[6]; + assign routers__recv__msg[6][2] = recv_adp__send__msg[6]; + assign recv_adp__send__yum[6][0] = routers__recv__yum[6][2][0]; + assign recv_adp__send__yum[6][1] = routers__recv__yum[6][2][1]; + assign send_adp__recv__en[6] = routers__send__en[6][2]; + assign send_adp__recv__msg[6] = routers__send__msg[6][2]; + assign routers__send__yum[6][2][0] = send_adp__recv__yum[6][0]; + assign routers__send__yum[6][2][1] = send_adp__recv__yum[6][1]; + assign send__msg[6] = send_adp__send__msg[6]; + assign send_adp__send__rdy[6] = send__rdy[6]; + assign send__val[6] = send_adp__send__val[6]; + assign routers__recv__en[8][0] = routers__send__en[7][1]; + assign routers__recv__msg[8][0] = routers__send__msg[7][1]; + assign routers__send__yum[7][1][0] = routers__recv__yum[8][0][0]; + assign routers__send__yum[7][1][1] = routers__recv__yum[8][0][1]; + assign routers__recv__en[7][1] = routers__send__en[8][0]; + assign routers__recv__msg[7][1] = routers__send__msg[8][0]; + assign routers__send__yum[8][0][0] = routers__recv__yum[7][1][0]; + assign routers__send__yum[8][0][1] = routers__recv__yum[7][1][1]; + assign recv_adp__recv__msg[7] = recv__msg[7]; + assign recv__rdy[7] = recv_adp__recv__rdy[7]; + assign recv_adp__recv__val[7] = recv__val[7]; + assign routers__recv__en[7][2] = recv_adp__send__en[7]; + assign routers__recv__msg[7][2] = recv_adp__send__msg[7]; + assign recv_adp__send__yum[7][0] = routers__recv__yum[7][2][0]; + assign recv_adp__send__yum[7][1] = routers__recv__yum[7][2][1]; + assign send_adp__recv__en[7] = routers__send__en[7][2]; + assign send_adp__recv__msg[7] = routers__send__msg[7][2]; + assign routers__send__yum[7][2][0] = send_adp__recv__yum[7][0]; + assign routers__send__yum[7][2][1] = send_adp__recv__yum[7][1]; + assign send__msg[7] = send_adp__send__msg[7]; + assign send_adp__send__rdy[7] = send__rdy[7]; + assign send__val[7] = send_adp__send__val[7]; + assign routers__recv__en[9][0] = routers__send__en[8][1]; + assign routers__recv__msg[9][0] = routers__send__msg[8][1]; + assign routers__send__yum[8][1][0] = routers__recv__yum[9][0][0]; + assign routers__send__yum[8][1][1] = routers__recv__yum[9][0][1]; + assign routers__recv__en[8][1] = routers__send__en[9][0]; + assign routers__recv__msg[8][1] = routers__send__msg[9][0]; + assign routers__send__yum[9][0][0] = routers__recv__yum[8][1][0]; + assign routers__send__yum[9][0][1] = routers__recv__yum[8][1][1]; + assign recv_adp__recv__msg[8] = recv__msg[8]; + assign recv__rdy[8] = recv_adp__recv__rdy[8]; + assign recv_adp__recv__val[8] = recv__val[8]; + assign routers__recv__en[8][2] = recv_adp__send__en[8]; + assign routers__recv__msg[8][2] = recv_adp__send__msg[8]; + assign recv_adp__send__yum[8][0] = routers__recv__yum[8][2][0]; + assign recv_adp__send__yum[8][1] = routers__recv__yum[8][2][1]; + assign send_adp__recv__en[8] = routers__send__en[8][2]; + assign send_adp__recv__msg[8] = routers__send__msg[8][2]; + assign routers__send__yum[8][2][0] = send_adp__recv__yum[8][0]; + assign routers__send__yum[8][2][1] = send_adp__recv__yum[8][1]; + assign send__msg[8] = send_adp__send__msg[8]; + assign send_adp__send__rdy[8] = send__rdy[8]; + assign send__val[8] = send_adp__send__val[8]; + assign routers__recv__en[10][0] = routers__send__en[9][1]; + assign routers__recv__msg[10][0] = routers__send__msg[9][1]; + assign routers__send__yum[9][1][0] = routers__recv__yum[10][0][0]; + assign routers__send__yum[9][1][1] = routers__recv__yum[10][0][1]; + assign routers__recv__en[9][1] = routers__send__en[10][0]; + assign routers__recv__msg[9][1] = routers__send__msg[10][0]; + assign routers__send__yum[10][0][0] = routers__recv__yum[9][1][0]; + assign routers__send__yum[10][0][1] = routers__recv__yum[9][1][1]; + assign recv_adp__recv__msg[9] = recv__msg[9]; + assign recv__rdy[9] = recv_adp__recv__rdy[9]; + assign recv_adp__recv__val[9] = recv__val[9]; + assign routers__recv__en[9][2] = recv_adp__send__en[9]; + assign routers__recv__msg[9][2] = recv_adp__send__msg[9]; + assign recv_adp__send__yum[9][0] = routers__recv__yum[9][2][0]; + assign recv_adp__send__yum[9][1] = routers__recv__yum[9][2][1]; + assign send_adp__recv__en[9] = routers__send__en[9][2]; + assign send_adp__recv__msg[9] = routers__send__msg[9][2]; + assign routers__send__yum[9][2][0] = send_adp__recv__yum[9][0]; + assign routers__send__yum[9][2][1] = send_adp__recv__yum[9][1]; + assign send__msg[9] = send_adp__send__msg[9]; + assign send_adp__send__rdy[9] = send__rdy[9]; + assign send__val[9] = send_adp__send__val[9]; + assign routers__recv__en[11][0] = routers__send__en[10][1]; + assign routers__recv__msg[11][0] = routers__send__msg[10][1]; + assign routers__send__yum[10][1][0] = routers__recv__yum[11][0][0]; + assign routers__send__yum[10][1][1] = routers__recv__yum[11][0][1]; + assign routers__recv__en[10][1] = routers__send__en[11][0]; + assign routers__recv__msg[10][1] = routers__send__msg[11][0]; + assign routers__send__yum[11][0][0] = routers__recv__yum[10][1][0]; + assign routers__send__yum[11][0][1] = routers__recv__yum[10][1][1]; + assign recv_adp__recv__msg[10] = recv__msg[10]; + assign recv__rdy[10] = recv_adp__recv__rdy[10]; + assign recv_adp__recv__val[10] = recv__val[10]; + assign routers__recv__en[10][2] = recv_adp__send__en[10]; + assign routers__recv__msg[10][2] = recv_adp__send__msg[10]; + assign recv_adp__send__yum[10][0] = routers__recv__yum[10][2][0]; + assign recv_adp__send__yum[10][1] = routers__recv__yum[10][2][1]; + assign send_adp__recv__en[10] = routers__send__en[10][2]; + assign send_adp__recv__msg[10] = routers__send__msg[10][2]; + assign routers__send__yum[10][2][0] = send_adp__recv__yum[10][0]; + assign routers__send__yum[10][2][1] = send_adp__recv__yum[10][1]; + assign send__msg[10] = send_adp__send__msg[10]; + assign send_adp__send__rdy[10] = send__rdy[10]; + assign send__val[10] = send_adp__send__val[10]; + assign routers__recv__en[12][0] = routers__send__en[11][1]; + assign routers__recv__msg[12][0] = routers__send__msg[11][1]; + assign routers__send__yum[11][1][0] = routers__recv__yum[12][0][0]; + assign routers__send__yum[11][1][1] = routers__recv__yum[12][0][1]; + assign routers__recv__en[11][1] = routers__send__en[12][0]; + assign routers__recv__msg[11][1] = routers__send__msg[12][0]; + assign routers__send__yum[12][0][0] = routers__recv__yum[11][1][0]; + assign routers__send__yum[12][0][1] = routers__recv__yum[11][1][1]; + assign recv_adp__recv__msg[11] = recv__msg[11]; + assign recv__rdy[11] = recv_adp__recv__rdy[11]; + assign recv_adp__recv__val[11] = recv__val[11]; + assign routers__recv__en[11][2] = recv_adp__send__en[11]; + assign routers__recv__msg[11][2] = recv_adp__send__msg[11]; + assign recv_adp__send__yum[11][0] = routers__recv__yum[11][2][0]; + assign recv_adp__send__yum[11][1] = routers__recv__yum[11][2][1]; + assign send_adp__recv__en[11] = routers__send__en[11][2]; + assign send_adp__recv__msg[11] = routers__send__msg[11][2]; + assign routers__send__yum[11][2][0] = send_adp__recv__yum[11][0]; + assign routers__send__yum[11][2][1] = send_adp__recv__yum[11][1]; + assign send__msg[11] = send_adp__send__msg[11]; + assign send_adp__send__rdy[11] = send__rdy[11]; + assign send__val[11] = send_adp__send__val[11]; + assign routers__recv__en[13][0] = routers__send__en[12][1]; + assign routers__recv__msg[13][0] = routers__send__msg[12][1]; + assign routers__send__yum[12][1][0] = routers__recv__yum[13][0][0]; + assign routers__send__yum[12][1][1] = routers__recv__yum[13][0][1]; + assign routers__recv__en[12][1] = routers__send__en[13][0]; + assign routers__recv__msg[12][1] = routers__send__msg[13][0]; + assign routers__send__yum[13][0][0] = routers__recv__yum[12][1][0]; + assign routers__send__yum[13][0][1] = routers__recv__yum[12][1][1]; + assign recv_adp__recv__msg[12] = recv__msg[12]; + assign recv__rdy[12] = recv_adp__recv__rdy[12]; + assign recv_adp__recv__val[12] = recv__val[12]; + assign routers__recv__en[12][2] = recv_adp__send__en[12]; + assign routers__recv__msg[12][2] = recv_adp__send__msg[12]; + assign recv_adp__send__yum[12][0] = routers__recv__yum[12][2][0]; + assign recv_adp__send__yum[12][1] = routers__recv__yum[12][2][1]; + assign send_adp__recv__en[12] = routers__send__en[12][2]; + assign send_adp__recv__msg[12] = routers__send__msg[12][2]; + assign routers__send__yum[12][2][0] = send_adp__recv__yum[12][0]; + assign routers__send__yum[12][2][1] = send_adp__recv__yum[12][1]; + assign send__msg[12] = send_adp__send__msg[12]; + assign send_adp__send__rdy[12] = send__rdy[12]; + assign send__val[12] = send_adp__send__val[12]; + assign routers__recv__en[14][0] = routers__send__en[13][1]; + assign routers__recv__msg[14][0] = routers__send__msg[13][1]; + assign routers__send__yum[13][1][0] = routers__recv__yum[14][0][0]; + assign routers__send__yum[13][1][1] = routers__recv__yum[14][0][1]; + assign routers__recv__en[13][1] = routers__send__en[14][0]; + assign routers__recv__msg[13][1] = routers__send__msg[14][0]; + assign routers__send__yum[14][0][0] = routers__recv__yum[13][1][0]; + assign routers__send__yum[14][0][1] = routers__recv__yum[13][1][1]; + assign recv_adp__recv__msg[13] = recv__msg[13]; + assign recv__rdy[13] = recv_adp__recv__rdy[13]; + assign recv_adp__recv__val[13] = recv__val[13]; + assign routers__recv__en[13][2] = recv_adp__send__en[13]; + assign routers__recv__msg[13][2] = recv_adp__send__msg[13]; + assign recv_adp__send__yum[13][0] = routers__recv__yum[13][2][0]; + assign recv_adp__send__yum[13][1] = routers__recv__yum[13][2][1]; + assign send_adp__recv__en[13] = routers__send__en[13][2]; + assign send_adp__recv__msg[13] = routers__send__msg[13][2]; + assign routers__send__yum[13][2][0] = send_adp__recv__yum[13][0]; + assign routers__send__yum[13][2][1] = send_adp__recv__yum[13][1]; + assign send__msg[13] = send_adp__send__msg[13]; + assign send_adp__send__rdy[13] = send__rdy[13]; + assign send__val[13] = send_adp__send__val[13]; + assign routers__recv__en[15][0] = routers__send__en[14][1]; + assign routers__recv__msg[15][0] = routers__send__msg[14][1]; + assign routers__send__yum[14][1][0] = routers__recv__yum[15][0][0]; + assign routers__send__yum[14][1][1] = routers__recv__yum[15][0][1]; + assign routers__recv__en[14][1] = routers__send__en[15][0]; + assign routers__recv__msg[14][1] = routers__send__msg[15][0]; + assign routers__send__yum[15][0][0] = routers__recv__yum[14][1][0]; + assign routers__send__yum[15][0][1] = routers__recv__yum[14][1][1]; + assign recv_adp__recv__msg[14] = recv__msg[14]; + assign recv__rdy[14] = recv_adp__recv__rdy[14]; + assign recv_adp__recv__val[14] = recv__val[14]; + assign routers__recv__en[14][2] = recv_adp__send__en[14]; + assign routers__recv__msg[14][2] = recv_adp__send__msg[14]; + assign recv_adp__send__yum[14][0] = routers__recv__yum[14][2][0]; + assign recv_adp__send__yum[14][1] = routers__recv__yum[14][2][1]; + assign send_adp__recv__en[14] = routers__send__en[14][2]; + assign send_adp__recv__msg[14] = routers__send__msg[14][2]; + assign routers__send__yum[14][2][0] = send_adp__recv__yum[14][0]; + assign routers__send__yum[14][2][1] = send_adp__recv__yum[14][1]; + assign send__msg[14] = send_adp__send__msg[14]; + assign send_adp__send__rdy[14] = send__rdy[14]; + assign send__val[14] = send_adp__send__val[14]; + assign routers__recv__en[16][0] = routers__send__en[15][1]; + assign routers__recv__msg[16][0] = routers__send__msg[15][1]; + assign routers__send__yum[15][1][0] = routers__recv__yum[16][0][0]; + assign routers__send__yum[15][1][1] = routers__recv__yum[16][0][1]; + assign routers__recv__en[15][1] = routers__send__en[16][0]; + assign routers__recv__msg[15][1] = routers__send__msg[16][0]; + assign routers__send__yum[16][0][0] = routers__recv__yum[15][1][0]; + assign routers__send__yum[16][0][1] = routers__recv__yum[15][1][1]; + assign recv_adp__recv__msg[15] = recv__msg[15]; + assign recv__rdy[15] = recv_adp__recv__rdy[15]; + assign recv_adp__recv__val[15] = recv__val[15]; + assign routers__recv__en[15][2] = recv_adp__send__en[15]; + assign routers__recv__msg[15][2] = recv_adp__send__msg[15]; + assign recv_adp__send__yum[15][0] = routers__recv__yum[15][2][0]; + assign recv_adp__send__yum[15][1] = routers__recv__yum[15][2][1]; + assign send_adp__recv__en[15] = routers__send__en[15][2]; + assign send_adp__recv__msg[15] = routers__send__msg[15][2]; + assign routers__send__yum[15][2][0] = send_adp__recv__yum[15][0]; + assign routers__send__yum[15][2][1] = send_adp__recv__yum[15][1]; + assign send__msg[15] = send_adp__send__msg[15]; + assign send_adp__send__rdy[15] = send__rdy[15]; + assign send__val[15] = send_adp__send__val[15]; + assign routers__recv__en[0][0] = routers__send__en[16][1]; + assign routers__recv__msg[0][0] = routers__send__msg[16][1]; + assign routers__send__yum[16][1][0] = routers__recv__yum[0][0][0]; + assign routers__send__yum[16][1][1] = routers__recv__yum[0][0][1]; + assign routers__recv__en[16][1] = routers__send__en[0][0]; + assign routers__recv__msg[16][1] = routers__send__msg[0][0]; + assign routers__send__yum[0][0][0] = routers__recv__yum[16][1][0]; + assign routers__send__yum[0][0][1] = routers__recv__yum[16][1][1]; + assign recv_adp__recv__msg[16] = recv__msg[16]; + assign recv__rdy[16] = recv_adp__recv__rdy[16]; + assign recv_adp__recv__val[16] = recv__val[16]; + assign routers__recv__en[16][2] = recv_adp__send__en[16]; + assign routers__recv__msg[16][2] = recv_adp__send__msg[16]; + assign recv_adp__send__yum[16][0] = routers__recv__yum[16][2][0]; + assign recv_adp__send__yum[16][1] = routers__recv__yum[16][2][1]; + assign send_adp__recv__en[16] = routers__send__en[16][2]; + assign send_adp__recv__msg[16] = routers__send__msg[16][2]; + assign routers__send__yum[16][2][0] = send_adp__recv__yum[16][0]; + assign routers__send__yum[16][2][1] = send_adp__recv__yum[16][1]; + assign send__msg[16] = send_adp__send__msg[16]; + assign send_adp__send__rdy[16] = send__rdy[16]; + assign send__val[16] = send_adp__send__val[16]; + +endmodule + + +// PyMTL Component ChannelRTL Definition +// Full name: ChannelRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_NormalQueueRTL__latency_0 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py + +module ChannelRTL__c31a2b1c86c6a129 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + assign send__msg = recv__msg; + assign recv__rdy = send__rdy; + assign send__val = recv__val; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__nregs_16__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__bd22936ec5812d0d +( + input logic [0:0] clk , + input logic [3:0] raddr [0:0], + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rdata [0:0], + input logic [0:0] reset , + input logic [3:0] waddr [0:0], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 regs [0:15]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component DataMemWrapperRTL Definition +// Full name: DataMemWrapperRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__MemReadType_MemAccessPacket_8_3_128__43c148781d2f2a57__MemWriteType_MemAccessPacket_8_3_128__43c148781d2f2a57__MemResponseType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__global_data_mem_size_128__per_bank_data_mem_size_16__is_combinational_True +// At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py + +module DataMemWrapperRTL__33e0a5b37976e571 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_rd__msg , + output logic [0:0] recv_rd__rdy , + input logic [0:0] recv_rd__val , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_wr__msg , + output logic [0:0] recv_wr__rdy , + input logic [0:0] recv_wr__val , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [4:0] __const__per_bank_data_mem_size_at_request_memory = 5'd16; + logic [6:0] streaming_rd_addr; + MemAccessPacket_8_3_128__43c148781d2f2a57 streaming_rd_read_reqeust; + logic [0:0] streaming_rd_status; + //------------------------------------------------------------- + // Component channel_rd + //------------------------------------------------------------- + + logic [0:0] channel_rd__clk; + logic [0:0] channel_rd__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 channel_rd__recv__msg; + logic [0:0] channel_rd__recv__rdy; + logic [0:0] channel_rd__recv__val; + MemAccessPacket_8_3_128__43c148781d2f2a57 channel_rd__send__msg; + logic [0:0] channel_rd__send__rdy; + logic [0:0] channel_rd__send__val; + + ChannelRTL__c31a2b1c86c6a129 channel_rd + ( + .clk( channel_rd__clk ), + .reset( channel_rd__reset ), + .recv__msg( channel_rd__recv__msg ), + .recv__rdy( channel_rd__recv__rdy ), + .recv__val( channel_rd__recv__val ), + .send__msg( channel_rd__send__msg ), + .send__rdy( channel_rd__send__rdy ), + .send__val( channel_rd__send__val ) + ); + + //------------------------------------------------------------- + // End of component channel_rd + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component channel_wr + //------------------------------------------------------------- + + logic [0:0] channel_wr__clk; + logic [0:0] channel_wr__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 channel_wr__recv__msg; + logic [0:0] channel_wr__recv__rdy; + logic [0:0] channel_wr__recv__val; + MemAccessPacket_8_3_128__43c148781d2f2a57 channel_wr__send__msg; + logic [0:0] channel_wr__send__rdy; + logic [0:0] channel_wr__send__val; + + ChannelRTL__c31a2b1c86c6a129 channel_wr + ( + .clk( channel_wr__clk ), + .reset( channel_wr__reset ), + .recv__msg( channel_wr__recv__msg ), + .recv__rdy( channel_wr__recv__rdy ), + .recv__val( channel_wr__recv__val ), + .send__msg( channel_wr__send__msg ), + .send__rdy( channel_wr__send__rdy ), + .send__val( channel_wr__send__val ) + ); + + //------------------------------------------------------------- + // End of component channel_wr + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component memory + //------------------------------------------------------------- + + logic [0:0] memory__clk; + logic [3:0] memory__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 memory__rdata [0:0]; + logic [0:0] memory__reset; + logic [3:0] memory__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 memory__wdata [0:0]; + logic [0:0] memory__wen [0:0]; + + RegisterFile__bd22936ec5812d0d memory + ( + .clk( memory__clk ), + .raddr( memory__raddr ), + .rdata( memory__rdata ), + .reset( memory__reset ), + .waddr( memory__waddr ), + .wdata( memory__wdata ), + .wen( memory__wen ) + ); + + //------------------------------------------------------------- + // End of component memory + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:76 + // @update + // def compose_send_msg(): + // s.send.msg @= MemResponseType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) + // # TODO: change to pipe's out's wen. + // # Streaming read example: + // # At cycle 0, s.channel_rd issues one single streaming read request (indicated by + // # s.channel_rd.send.msg.streaming_rd = 1) with s.channel_rd.send.msg.addr = 2, + // # s.channel_rd.send.msg.streaming_rd_stride = 2, and s.channel_rd.send.msg.streaming_rd_end_addr = 6. + // # Then s.send will return the multiple response data from addr=2, addr=4, and addr=6 + // # at cycle 0, cycle 1, and cycle 2, respectively. + // if s.streaming_rd_status: + // s.send.msg.src @= s.streaming_rd_read_reqeust.dst + // s.send.msg.dst @= s.streaming_rd_read_reqeust.src + // s.send.msg.addr @= s.streaming_rd_addr + // s.send.msg.data @= s.memory.rdata[0] + // s.send.msg.src_cgra @= s.streaming_rd_read_reqeust.src_cgra + // s.send.msg.src_tile @= s.streaming_rd_read_reqeust.src_tile + // s.send.msg.remote_src_port @= s.streaming_rd_read_reqeust.remote_src_port + // elif s.channel_rd.send.val: + // s.send.msg.src @= s.channel_rd.send.msg.dst + // s.send.msg.dst @= s.channel_rd.send.msg.src + // s.send.msg.addr @= s.channel_rd.send.msg.addr + // s.send.msg.data @= s.memory.rdata[0] + // s.send.msg.src_cgra @= s.channel_rd.send.msg.src_cgra + // s.send.msg.src_tile @= s.channel_rd.send.msg.src_tile + // s.send.msg.remote_src_port @= s.channel_rd.send.msg.remote_src_port + + always_comb begin : compose_send_msg + send__msg = { 2'd0, 3'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; + if ( streaming_rd_status ) begin + send__msg.src = streaming_rd_read_reqeust.dst; + send__msg.dst = streaming_rd_read_reqeust.src; + send__msg.addr = streaming_rd_addr; + send__msg.data = memory__rdata[1'd0]; + send__msg.src_cgra = streaming_rd_read_reqeust.src_cgra; + send__msg.src_tile = streaming_rd_read_reqeust.src_tile; + send__msg.remote_src_port = streaming_rd_read_reqeust.remote_src_port; + end + else if ( channel_rd__send__val ) begin + send__msg.src = channel_rd__send__msg.dst; + send__msg.dst = channel_rd__send__msg.src; + send__msg.addr = channel_rd__send__msg.addr; + send__msg.data = memory__rdata[1'd0]; + send__msg.src_cgra = channel_rd__send__msg.src_cgra; + send__msg.src_tile = channel_rd__send__msg.src_tile; + send__msg.remote_src_port = channel_rd__send__msg.remote_src_port; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:123 + // @update + // def notify_channel_rdy(): + // # TODO: change to SRAM's rdy when replacing register file + // # with SRAM. + // if s.streaming_rd_status: + // # Issue one streaming request at one time. + // s.channel_rd.send.rdy @= 0 + // else: + // s.channel_rd.send.rdy @= s.send.rdy + // s.channel_wr.send.rdy @= 1 + + always_comb begin : notify_channel_rdy + if ( streaming_rd_status ) begin + channel_rd__send__rdy = 1'd0; + end + else + channel_rd__send__rdy = send__rdy; + channel_wr__send__rdy = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:134 + // @update + // def notify_send_val(): + // # TODO: change to SRAM's valid when replacing register file + // # with SRAM. + // if s.streaming_rd_status: + // # Keep sending read data during streaming status. + // s.send.val @= 1 + // else: + // s.send.val @= s.channel_rd.send.val + + always_comb begin : notify_send_val + if ( streaming_rd_status ) begin + send__val = 1'd1; + end + else + send__val = channel_rd__send__val; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:103 + // @update + // def request_memory(): + // # Default values. + // s.memory.wen[0] @= 0 + // s.memory.raddr[0] @= PerBankAddrType(0) + // s.memory.waddr[0] @= PerBankAddrType(0) + // s.memory.wdata[0] @= DataType(0, 0, 0, 0) + // + // if s.streaming_rd_status: + // s.memory.raddr[0] @= \ + // trunc(s.streaming_rd_addr % per_bank_data_mem_size, PerBankAddrType) + // if s.channel_rd.send.val: + // s.memory.raddr[0] @= \ + // trunc(s.channel_rd.send.msg.addr % per_bank_data_mem_size, PerBankAddrType) + // if s.channel_wr.send.val: + // s.memory.waddr[0] @= \ + // trunc(s.channel_wr.send.msg.addr % per_bank_data_mem_size, PerBankAddrType) + // s.memory.wdata[0] @= s.channel_wr.send.msg.data + // s.memory.wen[0] @= 1 + + always_comb begin : request_memory + memory__wen[1'd0] = 1'd0; + memory__raddr[1'd0] = 4'd0; + memory__waddr[1'd0] = 4'd0; + memory__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + if ( streaming_rd_status ) begin + memory__raddr[1'd0] = 4'(streaming_rd_addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); + end + if ( channel_rd__send__val ) begin + memory__raddr[1'd0] = 4'(channel_rd__send__msg.addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); + end + if ( channel_wr__send__val ) begin + memory__waddr[1'd0] = 4'(channel_wr__send__msg.addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); + memory__wdata[1'd0] = channel_wr__send__msg.data; + memory__wen[1'd0] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:63 + // @update_ff + // def update_streaming_rd_regs(): + // if s.channel_rd.send.val & s.channel_rd.send.msg.streaming_rd: + // s.streaming_rd_status <<= 1 + // s.streaming_rd_addr <<= s.channel_rd.send.msg.addr + s.channel_rd.send.msg.streaming_rd_stride + // s.streaming_rd_read_reqeust <<= s.channel_rd.send.msg + // elif s.streaming_rd_addr == s.streaming_rd_read_reqeust.streaming_rd_end_addr: + // s.streaming_rd_status <<= 0 + // s.streaming_rd_addr <<= GlobalAddrType(0) + // s.streaming_rd_read_reqeust <<= MemReadType() + // else: + // s.streaming_rd_addr <<= s.streaming_rd_addr + s.streaming_rd_read_reqeust.streaming_rd_stride + + always_ff @(posedge clk) begin : update_streaming_rd_regs + if ( channel_rd__send__val & channel_rd__send__msg.streaming_rd ) begin + streaming_rd_status <= 1'd1; + streaming_rd_addr <= channel_rd__send__msg.addr + channel_rd__send__msg.streaming_rd_stride; + streaming_rd_read_reqeust <= channel_rd__send__msg; + end + else if ( streaming_rd_addr == streaming_rd_read_reqeust.streaming_rd_end_addr ) begin + streaming_rd_status <= 1'd0; + streaming_rd_addr <= 7'd0; + streaming_rd_read_reqeust <= { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; + end + else + streaming_rd_addr <= streaming_rd_addr + streaming_rd_read_reqeust.streaming_rd_stride; + end + + assign memory__clk = clk; + assign memory__reset = reset; + assign channel_rd__clk = clk; + assign channel_rd__reset = reset; + assign channel_wr__clk = clk; + assign channel_wr__reset = reset; + assign channel_rd__recv__msg = recv_rd__msg; + assign recv_rd__rdy = channel_rd__recv__rdy; + assign channel_rd__recv__val = recv_rd__val; + assign channel_wr__recv__msg = recv_wr__msg; + assign recv_wr__rdy = channel_wr__recv__rdy; + assign channel_wr__recv__val = recv_wr__val; + +endmodule + + +// PyMTL Component Mux Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_2 +( + input logic [0:0] clk , + input MemAccessPacket_8_3_128__43c148781d2f2a57 in_ [0:1], + output MemAccessPacket_8_3_128__43c148781d2f2a57 out , + input logic [0:0] reset , + input logic [0:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__7305dd76cfb05fd9 +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output MemAccessPacket_8_3_128__43c148781d2f2a57 rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input MemAccessPacket_8_3_128__43c148781d2f2a57 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + MemAccessPacket_8_3_128__43c148781d2f2a57 regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component BypassQueueDpathRTL Definition +// Full name: BypassQueueDpathRTL__EntryType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueDpathRTL__4eac613e5285098c +( + input logic [0:0] clk , + input logic [0:0] mux_sel , + input logic [0:0] raddr , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_msg , + input logic [0:0] reset , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + MemAccessPacket_8_3_128__43c148781d2f2a57 mux__in_ [0:1]; + MemAccessPacket_8_3_128__43c148781d2f2a57 mux__out; + logic [0:0] mux__reset; + logic [0:0] mux__sel; + + Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_2 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + MemAccessPacket_8_3_128__43c148781d2f2a57 rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + MemAccessPacket_8_3_128__43c148781d2f2a57 rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__7305dd76cfb05fd9 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + assign mux__clk = clk; + assign mux__reset = reset; + assign mux__sel = mux_sel; + assign mux__in_[0] = rf__rdata[0]; + assign mux__in_[1] = recv_msg; + assign send_msg = mux__out; + +endmodule + + +// PyMTL Component BypassQueueRTL Definition +// Full name: BypassQueueRTL__EntryType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueRTL__4eac613e5285098c +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__mux_sel; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + BypassQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .mux_sel( ctrl__mux_sel ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__mux_sel; + logic [0:0] dpath__raddr; + MemAccessPacket_8_3_128__43c148781d2f2a57 dpath__recv_msg; + logic [0:0] dpath__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + BypassQueueDpathRTL__4eac613e5285098c dpath + ( + .clk( dpath__clk ), + .mux_sel( dpath__mux_sel ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign dpath__mux_sel = ctrl__mux_sel; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign count = ctrl__count; + assign dpath__recv_msg = recv__msg; + assign send__msg = dpath__send_msg; + +endmodule + + +// PyMTL Component InputUnitRTL Definition +// Full name: InputUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_BypassQueueRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py + +module InputUnitRTL__1864e8652261553b +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queue + //------------------------------------------------------------- + + logic [0:0] queue__clk; + logic [1:0] queue__count; + logic [0:0] queue__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 queue__recv__msg; + logic [0:0] queue__recv__rdy; + logic [0:0] queue__recv__val; + MemAccessPacket_8_3_128__43c148781d2f2a57 queue__send__msg; + logic [0:0] queue__send__rdy; + logic [0:0] queue__send__val; + + BypassQueueRTL__4eac613e5285098c queue + ( + .clk( queue__clk ), + .count( queue__count ), + .reset( queue__reset ), + .recv__msg( queue__recv__msg ), + .recv__rdy( queue__recv__rdy ), + .recv__val( queue__recv__val ), + .send__msg( queue__send__msg ), + .send__rdy( queue__send__rdy ), + .send__val( queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component queue + //------------------------------------------------------------- + + assign queue__clk = clk; + assign queue__reset = reset; + assign queue__recv__msg = recv__msg; + assign recv__rdy = queue__recv__rdy; + assign queue__recv__val = recv__val; + assign send__msg = queue__send__msg; + assign queue__send__rdy = send__rdy; + assign send__val = queue__send__val; + +endmodule + + +// PyMTL Component OutputUnitRTL Definition +// Full name: OutputUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_None +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py + +module OutputUnitRTL__a3f8631b75bafad0 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + assign send__msg = recv__msg; + assign recv__rdy = send__rdy; + assign send__val = recv__val; + +endmodule + + +// PyMTL Component XbarRouteUnitRTL Definition +// Full name: XbarRouteUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_outports_3 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py + +module XbarRouteUnitRTL__32c7752a7c15587d +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg [0:2] , + input logic [0:0] send__rdy [0:2] , + output logic [0:0] send__val [0:2] +); + localparam logic [1:0] __const__num_outports_at_up_ru_routing = 2'd3; + logic [1:0] out_dir; + logic [2:0] send_val; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 + // @update + // def up_ru_recv_rdy(): + // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 + + always_comb begin : up_ru_recv_rdy + recv__rdy = send__rdy[out_dir] > 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 + // @update + // def up_ru_routing(): + // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) + // + // for i in range( num_outports ): + // s.send[i].val @= b1(0) + // + // if s.recv.val: + // s.send[ s.out_dir ].val @= b1(1) + + always_comb begin : up_ru_routing + out_dir = recv__msg.dst; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) + send__val[2'(i)] = 1'd0; + if ( recv__val ) begin + send__val[out_dir] = 1'd1; + end + end + + assign send__msg[0] = recv__msg; + assign send_val[0:0] = send__val[0]; + assign send__msg[1] = recv__msg; + assign send_val[1:1] = send__val[1]; + assign send__msg[2] = recv__msg; + assign send_val[2:2] = send__val[2]; + +endmodule + + +// PyMTL Component RegEnRst Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py + +module RegEnRst__Type_Bits8__reset_value_1 +( + input logic [0:0] clk , + input logic [0:0] en , + input logic [7:0] in_ , + output logic [7:0] out , + input logic [0:0] reset +); + localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 + // @update_ff + // def up_regenrst(): + // if s.reset: s.out <<= reset_value + // elif s.en: s.out <<= s.in_ + + always_ff @(posedge clk) begin : up_regenrst + if ( reset ) begin + out <= 8'( __const__reset_value_at_up_regenrst ); + end + else if ( en ) begin + out <= in_; + end + end + +endmodule + + +// PyMTL Component RoundRobinArbiterEn Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py + +module RoundRobinArbiterEn__nreqs_8 +( + input logic [0:0] clk , + input logic [0:0] en , + output logic [7:0] grants , + input logic [7:0] reqs , + input logic [0:0] reset +); + localparam logic [3:0] __const__nreqs_at_comb_reqs_int = 4'd8; + localparam logic [4:0] __const__nreqsX2_at_comb_reqs_int = 5'd16; + localparam logic [3:0] __const__nreqs_at_comb_grants = 4'd8; + localparam logic [3:0] __const__nreqs_at_comb_priority_int = 4'd8; + localparam logic [4:0] __const__nreqsX2_at_comb_priority_int = 5'd16; + localparam logic [4:0] __const__nreqsX2_at_comb_kills = 5'd16; + localparam logic [4:0] __const__nreqsX2_at_comb_grants_int = 5'd16; + logic [15:0] grants_int; + logic [16:0] kills; + logic [0:0] priority_en; + logic [15:0] priority_int; + logic [15:0] reqs_int; + //------------------------------------------------------------- + // Component priority_reg + //------------------------------------------------------------- + + logic [0:0] priority_reg__clk; + logic [0:0] priority_reg__en; + logic [7:0] priority_reg__in_; + logic [7:0] priority_reg__out; + logic [0:0] priority_reg__reset; + + RegEnRst__Type_Bits8__reset_value_1 priority_reg + ( + .clk( priority_reg__clk ), + .en( priority_reg__en ), + .in_( priority_reg__in_ ), + .out( priority_reg__out ), + .reset( priority_reg__reset ) + ); + + //------------------------------------------------------------- + // End of component priority_reg + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 + // @update + // def comb_grants(): + // for i in range( nreqs ): + // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] + + always_comb begin : comb_grants + for ( int unsigned i = 1'd0; i < 4'( __const__nreqs_at_comb_grants ); i += 1'd1 ) + grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 + // @update + // def comb_grants_int(): + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.grants_int[i] @= s.reqs_int[i] + // else: + // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] + + always_comb begin : comb_grants_int + for ( int unsigned i = 1'd0; i < 5'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + grants_int[4'(i)] = reqs_int[4'(i)]; + end + else + grants_int[4'(i)] = ( ~kills[5'(i)] ) & reqs_int[4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 + // @update + // def comb_kills(): + // s.kills[0] @= 1 + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.kills[i+1] @= s.reqs_int[i] + // else: + // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) + + always_comb begin : comb_kills + kills[5'd0] = 1'd1; + for ( int unsigned i = 1'd0; i < 5'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + kills[5'(i) + 5'd1] = reqs_int[4'(i)]; + end + else + kills[5'(i) + 5'd1] = kills[5'(i)] | ( ( ~kills[5'(i)] ) & reqs_int[4'(i)] ); + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 + // @update + // def comb_priority_en(): + // s.priority_en @= ( s.grants != 0 ) & s.en + + always_comb begin : comb_priority_en + priority_en = ( grants != 8'd0 ) & en; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 + // @update + // def comb_priority_int(): + // s.priority_int[ 0:nreqs ] @= s.priority_reg.out + // s.priority_int[nreqs:nreqsX2] @= 0 + + always_comb begin : comb_priority_int + priority_int[4'd7:4'd0] = priority_reg__out; + priority_int[4'd15:4'( __const__nreqs_at_comb_priority_int )] = 8'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 + // @update + // def comb_reqs_int(): + // s.reqs_int [ 0:nreqs ] @= s.reqs + // s.reqs_int [nreqs:nreqsX2] @= s.reqs + + always_comb begin : comb_reqs_int + reqs_int[4'd7:4'd0] = reqs; + reqs_int[4'd15:4'( __const__nreqs_at_comb_reqs_int )] = reqs; + end + + assign priority_reg__clk = clk; + assign priority_reg__reset = reset; + assign priority_reg__en = priority_en; + assign priority_reg__in_[7:1] = grants[6:0]; + assign priority_reg__in_[0:0] = grants[7:7]; + +endmodule + + +// PyMTL Component Encoder Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py + +module Encoder__in_nbits_8__out_nbits_3 +( + input logic [0:0] clk , + input logic [7:0] in_ , + output logic [2:0] out , + input logic [0:0] reset +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 + // @update + // def encode(): + // s.out @= 0 + // for i in range( s.in_nbits ): + // if s.in_[i]: + // s.out @= i + + always_comb begin : encode + out = 3'd0; + for ( int unsigned i = 1'd0; i < 4'd8; i += 1'd1 ) + if ( in_[3'(i)] ) begin + out = 3'(i); + end + end + +endmodule + + +// PyMTL Component Mux Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_8 +( + input logic [0:0] clk , + input MemAccessPacket_8_3_128__43c148781d2f2a57 in_ [0:7], + output MemAccessPacket_8_3_128__43c148781d2f2a57 out , + input logic [0:0] reset , + input logic [2:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component SwitchUnitRTL Definition +// Full name: SwitchUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_inports_8 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py + +module SwitchUnitRTL__10097976fa423359 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg [0:7] , + output logic [0:0] recv__rdy [0:7] , + input logic [0:0] recv__val [0:7] , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [3:0] __const__num_inports_at_up_get_en = 4'd8; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [7:0] arbiter__grants; + logic [7:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_8 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [7:0] encoder__in_; + logic [2:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_8__out_nbits_3 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + MemAccessPacket_8_3_128__43c148781d2f2a57 mux__in_ [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 mux__out; + logic [0:0] mux__reset; + logic [2:0] mux__sel; + + Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_8 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 + // @update + // def up_get_en(): + // for i in range( num_inports ): + // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) + + always_comb begin : up_get_en + for ( int unsigned i = 1'd0; i < 4'( __const__num_inports_at_up_get_en ); i += 1'd1 ) + recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 + // @update + // def up_send_val(): + // s.send.val @= s.arbiter.grants > 0 + + always_comb begin : up_send_val + send__val = arbiter__grants > 8'd0; + end + + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign arbiter__en = 1'd1; + assign mux__clk = clk; + assign mux__reset = reset; + assign send__msg = mux__out; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign encoder__in_ = arbiter__grants; + assign mux__sel = encoder__out; + assign arbiter__reqs[0:0] = recv__val[0]; + assign mux__in_[0] = recv__msg[0]; + assign arbiter__reqs[1:1] = recv__val[1]; + assign mux__in_[1] = recv__msg[1]; + assign arbiter__reqs[2:2] = recv__val[2]; + assign mux__in_[2] = recv__msg[2]; + assign arbiter__reqs[3:3] = recv__val[3]; + assign mux__in_[3] = recv__msg[3]; + assign arbiter__reqs[4:4] = recv__val[4]; + assign mux__in_[4] = recv__msg[4]; + assign arbiter__reqs[5:5] = recv__val[5]; + assign mux__in_[5] = recv__msg[5]; + assign arbiter__reqs[6:6] = recv__val[6]; + assign mux__in_[6] = recv__msg[6]; + assign arbiter__reqs[7:7] = recv__val[7]; + assign mux__in_[7] = recv__msg[7]; + +endmodule + + +// PyMTL Component XbarBypassQueueRTL Definition +// Full name: XbarBypassQueueRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_inports_8__num_outports_3__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarBypassQueueRTL.py + +module XbarBypassQueueRTL__045133ee283ca701 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg [0:7] , + output logic [0:0] recv__rdy [0:7] , + input logic [0:0] recv__val [0:7] , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg [0:2] , + input logic [0:0] send__rdy [0:2] , + output logic [0:0] send__val [0:2] +); + //------------------------------------------------------------- + // Component input_units[0:7] + //------------------------------------------------------------- + + logic [0:0] input_units__clk [0:7]; + logic [0:0] input_units__reset [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 input_units__recv__msg [0:7]; + logic [0:0] input_units__recv__rdy [0:7]; + logic [0:0] input_units__recv__val [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 input_units__send__msg [0:7]; + logic [0:0] input_units__send__rdy [0:7]; + logic [0:0] input_units__send__val [0:7]; + + InputUnitRTL__1864e8652261553b input_units__0 + ( + .clk( input_units__clk[0] ), + .reset( input_units__reset[0] ), + .recv__msg( input_units__recv__msg[0] ), + .recv__rdy( input_units__recv__rdy[0] ), + .recv__val( input_units__recv__val[0] ), + .send__msg( input_units__send__msg[0] ), + .send__rdy( input_units__send__rdy[0] ), + .send__val( input_units__send__val[0] ) + ); + + InputUnitRTL__1864e8652261553b input_units__1 + ( + .clk( input_units__clk[1] ), + .reset( input_units__reset[1] ), + .recv__msg( input_units__recv__msg[1] ), + .recv__rdy( input_units__recv__rdy[1] ), + .recv__val( input_units__recv__val[1] ), + .send__msg( input_units__send__msg[1] ), + .send__rdy( input_units__send__rdy[1] ), + .send__val( input_units__send__val[1] ) + ); + + InputUnitRTL__1864e8652261553b input_units__2 + ( + .clk( input_units__clk[2] ), + .reset( input_units__reset[2] ), + .recv__msg( input_units__recv__msg[2] ), + .recv__rdy( input_units__recv__rdy[2] ), + .recv__val( input_units__recv__val[2] ), + .send__msg( input_units__send__msg[2] ), + .send__rdy( input_units__send__rdy[2] ), + .send__val( input_units__send__val[2] ) + ); + + InputUnitRTL__1864e8652261553b input_units__3 + ( + .clk( input_units__clk[3] ), + .reset( input_units__reset[3] ), + .recv__msg( input_units__recv__msg[3] ), + .recv__rdy( input_units__recv__rdy[3] ), + .recv__val( input_units__recv__val[3] ), + .send__msg( input_units__send__msg[3] ), + .send__rdy( input_units__send__rdy[3] ), + .send__val( input_units__send__val[3] ) + ); + + InputUnitRTL__1864e8652261553b input_units__4 + ( + .clk( input_units__clk[4] ), + .reset( input_units__reset[4] ), + .recv__msg( input_units__recv__msg[4] ), + .recv__rdy( input_units__recv__rdy[4] ), + .recv__val( input_units__recv__val[4] ), + .send__msg( input_units__send__msg[4] ), + .send__rdy( input_units__send__rdy[4] ), + .send__val( input_units__send__val[4] ) + ); + + InputUnitRTL__1864e8652261553b input_units__5 + ( + .clk( input_units__clk[5] ), + .reset( input_units__reset[5] ), + .recv__msg( input_units__recv__msg[5] ), + .recv__rdy( input_units__recv__rdy[5] ), + .recv__val( input_units__recv__val[5] ), + .send__msg( input_units__send__msg[5] ), + .send__rdy( input_units__send__rdy[5] ), + .send__val( input_units__send__val[5] ) + ); + + InputUnitRTL__1864e8652261553b input_units__6 + ( + .clk( input_units__clk[6] ), + .reset( input_units__reset[6] ), + .recv__msg( input_units__recv__msg[6] ), + .recv__rdy( input_units__recv__rdy[6] ), + .recv__val( input_units__recv__val[6] ), + .send__msg( input_units__send__msg[6] ), + .send__rdy( input_units__send__rdy[6] ), + .send__val( input_units__send__val[6] ) + ); + + InputUnitRTL__1864e8652261553b input_units__7 + ( + .clk( input_units__clk[7] ), + .reset( input_units__reset[7] ), + .recv__msg( input_units__recv__msg[7] ), + .recv__rdy( input_units__recv__rdy[7] ), + .recv__val( input_units__recv__val[7] ), + .send__msg( input_units__send__msg[7] ), + .send__rdy( input_units__send__rdy[7] ), + .send__val( input_units__send__val[7] ) + ); + + //------------------------------------------------------------- + // End of component input_units[0:7] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component output_units[0:2] + //------------------------------------------------------------- + + logic [0:0] output_units__clk [0:2]; + logic [0:0] output_units__reset [0:2]; + MemAccessPacket_8_3_128__43c148781d2f2a57 output_units__recv__msg [0:2]; + logic [0:0] output_units__recv__rdy [0:2]; + logic [0:0] output_units__recv__val [0:2]; + MemAccessPacket_8_3_128__43c148781d2f2a57 output_units__send__msg [0:2]; + logic [0:0] output_units__send__rdy [0:2]; + logic [0:0] output_units__send__val [0:2]; + + OutputUnitRTL__a3f8631b75bafad0 output_units__0 + ( + .clk( output_units__clk[0] ), + .reset( output_units__reset[0] ), + .recv__msg( output_units__recv__msg[0] ), + .recv__rdy( output_units__recv__rdy[0] ), + .recv__val( output_units__recv__val[0] ), + .send__msg( output_units__send__msg[0] ), + .send__rdy( output_units__send__rdy[0] ), + .send__val( output_units__send__val[0] ) + ); + + OutputUnitRTL__a3f8631b75bafad0 output_units__1 + ( + .clk( output_units__clk[1] ), + .reset( output_units__reset[1] ), + .recv__msg( output_units__recv__msg[1] ), + .recv__rdy( output_units__recv__rdy[1] ), + .recv__val( output_units__recv__val[1] ), + .send__msg( output_units__send__msg[1] ), + .send__rdy( output_units__send__rdy[1] ), + .send__val( output_units__send__val[1] ) + ); + + OutputUnitRTL__a3f8631b75bafad0 output_units__2 + ( + .clk( output_units__clk[2] ), + .reset( output_units__reset[2] ), + .recv__msg( output_units__recv__msg[2] ), + .recv__rdy( output_units__recv__rdy[2] ), + .recv__val( output_units__recv__val[2] ), + .send__msg( output_units__send__msg[2] ), + .send__rdy( output_units__send__rdy[2] ), + .send__val( output_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component output_units[0:2] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component route_units[0:7] + //------------------------------------------------------------- + + logic [0:0] route_units__clk [0:7]; + logic [0:0] route_units__reset [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 route_units__recv__msg [0:7]; + logic [0:0] route_units__recv__rdy [0:7]; + logic [0:0] route_units__recv__val [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 route_units__send__msg [0:7][0:2]; + logic [0:0] route_units__send__rdy [0:7][0:2]; + logic [0:0] route_units__send__val [0:7][0:2]; + + XbarRouteUnitRTL__32c7752a7c15587d route_units__0 + ( + .clk( route_units__clk[0] ), + .reset( route_units__reset[0] ), + .recv__msg( route_units__recv__msg[0] ), + .recv__rdy( route_units__recv__rdy[0] ), + .recv__val( route_units__recv__val[0] ), + .send__msg( route_units__send__msg[0] ), + .send__rdy( route_units__send__rdy[0] ), + .send__val( route_units__send__val[0] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__1 + ( + .clk( route_units__clk[1] ), + .reset( route_units__reset[1] ), + .recv__msg( route_units__recv__msg[1] ), + .recv__rdy( route_units__recv__rdy[1] ), + .recv__val( route_units__recv__val[1] ), + .send__msg( route_units__send__msg[1] ), + .send__rdy( route_units__send__rdy[1] ), + .send__val( route_units__send__val[1] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__2 + ( + .clk( route_units__clk[2] ), + .reset( route_units__reset[2] ), + .recv__msg( route_units__recv__msg[2] ), + .recv__rdy( route_units__recv__rdy[2] ), + .recv__val( route_units__recv__val[2] ), + .send__msg( route_units__send__msg[2] ), + .send__rdy( route_units__send__rdy[2] ), + .send__val( route_units__send__val[2] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__3 + ( + .clk( route_units__clk[3] ), + .reset( route_units__reset[3] ), + .recv__msg( route_units__recv__msg[3] ), + .recv__rdy( route_units__recv__rdy[3] ), + .recv__val( route_units__recv__val[3] ), + .send__msg( route_units__send__msg[3] ), + .send__rdy( route_units__send__rdy[3] ), + .send__val( route_units__send__val[3] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__4 + ( + .clk( route_units__clk[4] ), + .reset( route_units__reset[4] ), + .recv__msg( route_units__recv__msg[4] ), + .recv__rdy( route_units__recv__rdy[4] ), + .recv__val( route_units__recv__val[4] ), + .send__msg( route_units__send__msg[4] ), + .send__rdy( route_units__send__rdy[4] ), + .send__val( route_units__send__val[4] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__5 + ( + .clk( route_units__clk[5] ), + .reset( route_units__reset[5] ), + .recv__msg( route_units__recv__msg[5] ), + .recv__rdy( route_units__recv__rdy[5] ), + .recv__val( route_units__recv__val[5] ), + .send__msg( route_units__send__msg[5] ), + .send__rdy( route_units__send__rdy[5] ), + .send__val( route_units__send__val[5] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__6 + ( + .clk( route_units__clk[6] ), + .reset( route_units__reset[6] ), + .recv__msg( route_units__recv__msg[6] ), + .recv__rdy( route_units__recv__rdy[6] ), + .recv__val( route_units__recv__val[6] ), + .send__msg( route_units__send__msg[6] ), + .send__rdy( route_units__send__rdy[6] ), + .send__val( route_units__send__val[6] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__7 + ( + .clk( route_units__clk[7] ), + .reset( route_units__reset[7] ), + .recv__msg( route_units__recv__msg[7] ), + .recv__rdy( route_units__recv__rdy[7] ), + .recv__val( route_units__recv__val[7] ), + .send__msg( route_units__send__msg[7] ), + .send__rdy( route_units__send__rdy[7] ), + .send__val( route_units__send__val[7] ) + ); + + //------------------------------------------------------------- + // End of component route_units[0:7] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component switch_units[0:2] + //------------------------------------------------------------- + + logic [0:0] switch_units__clk [0:2]; + logic [0:0] switch_units__reset [0:2]; + MemAccessPacket_8_3_128__43c148781d2f2a57 switch_units__recv__msg [0:2][0:7]; + logic [0:0] switch_units__recv__rdy [0:2][0:7]; + logic [0:0] switch_units__recv__val [0:2][0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 switch_units__send__msg [0:2]; + logic [0:0] switch_units__send__rdy [0:2]; + logic [0:0] switch_units__send__val [0:2]; + + SwitchUnitRTL__10097976fa423359 switch_units__0 + ( + .clk( switch_units__clk[0] ), + .reset( switch_units__reset[0] ), + .recv__msg( switch_units__recv__msg[0] ), + .recv__rdy( switch_units__recv__rdy[0] ), + .recv__val( switch_units__recv__val[0] ), + .send__msg( switch_units__send__msg[0] ), + .send__rdy( switch_units__send__rdy[0] ), + .send__val( switch_units__send__val[0] ) + ); + + SwitchUnitRTL__10097976fa423359 switch_units__1 + ( + .clk( switch_units__clk[1] ), + .reset( switch_units__reset[1] ), + .recv__msg( switch_units__recv__msg[1] ), + .recv__rdy( switch_units__recv__rdy[1] ), + .recv__val( switch_units__recv__val[1] ), + .send__msg( switch_units__send__msg[1] ), + .send__rdy( switch_units__send__rdy[1] ), + .send__val( switch_units__send__val[1] ) + ); + + SwitchUnitRTL__10097976fa423359 switch_units__2 + ( + .clk( switch_units__clk[2] ), + .reset( switch_units__reset[2] ), + .recv__msg( switch_units__recv__msg[2] ), + .recv__rdy( switch_units__recv__rdy[2] ), + .recv__val( switch_units__recv__val[2] ), + .send__msg( switch_units__send__msg[2] ), + .send__rdy( switch_units__send__rdy[2] ), + .send__val( switch_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component switch_units[0:2] + //------------------------------------------------------------- + + assign input_units__clk[0] = clk; + assign input_units__reset[0] = reset; + assign input_units__clk[1] = clk; + assign input_units__reset[1] = reset; + assign input_units__clk[2] = clk; + assign input_units__reset[2] = reset; + assign input_units__clk[3] = clk; + assign input_units__reset[3] = reset; + assign input_units__clk[4] = clk; + assign input_units__reset[4] = reset; + assign input_units__clk[5] = clk; + assign input_units__reset[5] = reset; + assign input_units__clk[6] = clk; + assign input_units__reset[6] = reset; + assign input_units__clk[7] = clk; + assign input_units__reset[7] = reset; + assign route_units__clk[0] = clk; + assign route_units__reset[0] = reset; + assign route_units__clk[1] = clk; + assign route_units__reset[1] = reset; + assign route_units__clk[2] = clk; + assign route_units__reset[2] = reset; + assign route_units__clk[3] = clk; + assign route_units__reset[3] = reset; + assign route_units__clk[4] = clk; + assign route_units__reset[4] = reset; + assign route_units__clk[5] = clk; + assign route_units__reset[5] = reset; + assign route_units__clk[6] = clk; + assign route_units__reset[6] = reset; + assign route_units__clk[7] = clk; + assign route_units__reset[7] = reset; + assign switch_units__clk[0] = clk; + assign switch_units__reset[0] = reset; + assign switch_units__clk[1] = clk; + assign switch_units__reset[1] = reset; + assign switch_units__clk[2] = clk; + assign switch_units__reset[2] = reset; + assign output_units__clk[0] = clk; + assign output_units__reset[0] = reset; + assign output_units__clk[1] = clk; + assign output_units__reset[1] = reset; + assign output_units__clk[2] = clk; + assign output_units__reset[2] = reset; + assign input_units__recv__msg[0] = recv__msg[0]; + assign recv__rdy[0] = input_units__recv__rdy[0]; + assign input_units__recv__val[0] = recv__val[0]; + assign route_units__recv__msg[0] = input_units__send__msg[0]; + assign input_units__send__rdy[0] = route_units__recv__rdy[0]; + assign route_units__recv__val[0] = input_units__send__val[0]; + assign input_units__recv__msg[1] = recv__msg[1]; + assign recv__rdy[1] = input_units__recv__rdy[1]; + assign input_units__recv__val[1] = recv__val[1]; + assign route_units__recv__msg[1] = input_units__send__msg[1]; + assign input_units__send__rdy[1] = route_units__recv__rdy[1]; + assign route_units__recv__val[1] = input_units__send__val[1]; + assign input_units__recv__msg[2] = recv__msg[2]; + assign recv__rdy[2] = input_units__recv__rdy[2]; + assign input_units__recv__val[2] = recv__val[2]; + assign route_units__recv__msg[2] = input_units__send__msg[2]; + assign input_units__send__rdy[2] = route_units__recv__rdy[2]; + assign route_units__recv__val[2] = input_units__send__val[2]; + assign input_units__recv__msg[3] = recv__msg[3]; + assign recv__rdy[3] = input_units__recv__rdy[3]; + assign input_units__recv__val[3] = recv__val[3]; + assign route_units__recv__msg[3] = input_units__send__msg[3]; + assign input_units__send__rdy[3] = route_units__recv__rdy[3]; + assign route_units__recv__val[3] = input_units__send__val[3]; + assign input_units__recv__msg[4] = recv__msg[4]; + assign recv__rdy[4] = input_units__recv__rdy[4]; + assign input_units__recv__val[4] = recv__val[4]; + assign route_units__recv__msg[4] = input_units__send__msg[4]; + assign input_units__send__rdy[4] = route_units__recv__rdy[4]; + assign route_units__recv__val[4] = input_units__send__val[4]; + assign input_units__recv__msg[5] = recv__msg[5]; + assign recv__rdy[5] = input_units__recv__rdy[5]; + assign input_units__recv__val[5] = recv__val[5]; + assign route_units__recv__msg[5] = input_units__send__msg[5]; + assign input_units__send__rdy[5] = route_units__recv__rdy[5]; + assign route_units__recv__val[5] = input_units__send__val[5]; + assign input_units__recv__msg[6] = recv__msg[6]; + assign recv__rdy[6] = input_units__recv__rdy[6]; + assign input_units__recv__val[6] = recv__val[6]; + assign route_units__recv__msg[6] = input_units__send__msg[6]; + assign input_units__send__rdy[6] = route_units__recv__rdy[6]; + assign route_units__recv__val[6] = input_units__send__val[6]; + assign input_units__recv__msg[7] = recv__msg[7]; + assign recv__rdy[7] = input_units__recv__rdy[7]; + assign input_units__recv__val[7] = recv__val[7]; + assign route_units__recv__msg[7] = input_units__send__msg[7]; + assign input_units__send__rdy[7] = route_units__recv__rdy[7]; + assign route_units__recv__val[7] = input_units__send__val[7]; + assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; + assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; + assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; + assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; + assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; + assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; + assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; + assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; + assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; + assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; + assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; + assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; + assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; + assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; + assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; + assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; + assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; + assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; + assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; + assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; + assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; + assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; + assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; + assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; + assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; + assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; + assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; + assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; + assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; + assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; + assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; + assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; + assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; + assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; + assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; + assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; + assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; + assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; + assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; + assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; + assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; + assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; + assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; + assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; + assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; + assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; + assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; + assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; + assign switch_units__recv__msg[1][5] = route_units__send__msg[5][1]; + assign route_units__send__rdy[5][1] = switch_units__recv__rdy[1][5]; + assign switch_units__recv__val[1][5] = route_units__send__val[5][1]; + assign switch_units__recv__msg[2][5] = route_units__send__msg[5][2]; + assign route_units__send__rdy[5][2] = switch_units__recv__rdy[2][5]; + assign switch_units__recv__val[2][5] = route_units__send__val[5][2]; + assign switch_units__recv__msg[0][6] = route_units__send__msg[6][0]; + assign route_units__send__rdy[6][0] = switch_units__recv__rdy[0][6]; + assign switch_units__recv__val[0][6] = route_units__send__val[6][0]; + assign switch_units__recv__msg[1][6] = route_units__send__msg[6][1]; + assign route_units__send__rdy[6][1] = switch_units__recv__rdy[1][6]; + assign switch_units__recv__val[1][6] = route_units__send__val[6][1]; + assign switch_units__recv__msg[2][6] = route_units__send__msg[6][2]; + assign route_units__send__rdy[6][2] = switch_units__recv__rdy[2][6]; + assign switch_units__recv__val[2][6] = route_units__send__val[6][2]; + assign switch_units__recv__msg[0][7] = route_units__send__msg[7][0]; + assign route_units__send__rdy[7][0] = switch_units__recv__rdy[0][7]; + assign switch_units__recv__val[0][7] = route_units__send__val[7][0]; + assign switch_units__recv__msg[1][7] = route_units__send__msg[7][1]; + assign route_units__send__rdy[7][1] = switch_units__recv__rdy[1][7]; + assign switch_units__recv__val[1][7] = route_units__send__val[7][1]; + assign switch_units__recv__msg[2][7] = route_units__send__msg[7][2]; + assign route_units__send__rdy[7][2] = switch_units__recv__rdy[2][7]; + assign switch_units__recv__val[2][7] = route_units__send__val[7][2]; + assign output_units__recv__msg[0] = switch_units__send__msg[0]; + assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; + assign output_units__recv__val[0] = switch_units__send__val[0]; + assign send__msg[0] = output_units__send__msg[0]; + assign output_units__send__rdy[0] = send__rdy[0]; + assign send__val[0] = output_units__send__val[0]; + assign output_units__recv__msg[1] = switch_units__send__msg[1]; + assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; + assign output_units__recv__val[1] = switch_units__send__val[1]; + assign send__msg[1] = output_units__send__msg[1]; + assign output_units__send__rdy[1] = send__rdy[1]; + assign send__val[1] = output_units__send__val[1]; + assign output_units__recv__msg[2] = switch_units__send__msg[2]; + assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; + assign output_units__recv__val[2] = switch_units__send__val[2]; + assign send__msg[2] = output_units__send__msg[2]; + assign output_units__send__rdy[2] = send__rdy[2]; + assign send__val[2] = output_units__send__val[2]; + +endmodule + + +// PyMTL Component Mux Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_2 +( + input logic [0:0] clk , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 in_ [0:1], + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 out , + input logic [0:0] reset , + input logic [0:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__3969b2773d1d2f8e +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component BypassQueueDpathRTL Definition +// Full name: BypassQueueDpathRTL__EntryType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueDpathRTL__60d0395b9f70f062 +( + input logic [0:0] clk , + input logic [0:0] mux_sel , + input logic [0:0] raddr , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv_msg , + input logic [0:0] reset , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__in_ [0:1]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__out; + logic [0:0] mux__reset; + logic [0:0] mux__sel; + + Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_2 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__3969b2773d1d2f8e rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + assign mux__clk = clk; + assign mux__reset = reset; + assign mux__sel = mux_sel; + assign mux__in_[0] = rf__rdata[0]; + assign mux__in_[1] = recv_msg; + assign send_msg = mux__out; + +endmodule + + +// PyMTL Component BypassQueueRTL Definition +// Full name: BypassQueueRTL__EntryType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueRTL__60d0395b9f70f062 +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__mux_sel; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + BypassQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .mux_sel( ctrl__mux_sel ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__mux_sel; + logic [0:0] dpath__raddr; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 dpath__recv_msg; + logic [0:0] dpath__reset; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + BypassQueueDpathRTL__60d0395b9f70f062 dpath + ( + .clk( dpath__clk ), + .mux_sel( dpath__mux_sel ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign dpath__mux_sel = ctrl__mux_sel; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign count = ctrl__count; + assign dpath__recv_msg = recv__msg; + assign send__msg = dpath__send_msg; + +endmodule + + +// PyMTL Component InputUnitRTL Definition +// Full name: InputUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__QueueType_BypassQueueRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py + +module InputUnitRTL__cff279ef5009e7c6 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queue + //------------------------------------------------------------- + + logic [0:0] queue__clk; + logic [1:0] queue__count; + logic [0:0] queue__reset; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 queue__recv__msg; + logic [0:0] queue__recv__rdy; + logic [0:0] queue__recv__val; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 queue__send__msg; + logic [0:0] queue__send__rdy; + logic [0:0] queue__send__val; + + BypassQueueRTL__60d0395b9f70f062 queue + ( + .clk( queue__clk ), + .count( queue__count ), + .reset( queue__reset ), + .recv__msg( queue__recv__msg ), + .recv__rdy( queue__recv__rdy ), + .recv__val( queue__recv__val ), + .send__msg( queue__send__msg ), + .send__rdy( queue__send__rdy ), + .send__val( queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component queue + //------------------------------------------------------------- + + assign queue__clk = clk; + assign queue__reset = reset; + assign queue__recv__msg = recv__msg; + assign recv__rdy = queue__recv__rdy; + assign queue__recv__val = recv__val; + assign send__msg = queue__send__msg; + assign queue__send__rdy = send__rdy; + assign send__val = queue__send__val; + +endmodule + + +// PyMTL Component OutputUnitRTL Definition +// Full name: OutputUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__QueueType_None +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py + +module OutputUnitRTL__e96d78a3d0126314 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + assign send__msg = recv__msg; + assign recv__rdy = send__rdy; + assign send__val = recv__val; + +endmodule + + +// PyMTL Component XbarRouteUnitRTL Definition +// Full name: XbarRouteUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_outports_8 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py + +module XbarRouteUnitRTL__c063f4910bbc0b50 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg [0:7] , + input logic [0:0] send__rdy [0:7] , + output logic [0:0] send__val [0:7] +); + localparam logic [3:0] __const__num_outports_at_up_ru_routing = 4'd8; + logic [2:0] out_dir; + logic [7:0] send_val; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 + // @update + // def up_ru_recv_rdy(): + // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 + + always_comb begin : up_ru_recv_rdy + recv__rdy = send__rdy[out_dir] > 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 + // @update + // def up_ru_routing(): + // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) + // + // for i in range( num_outports ): + // s.send[i].val @= b1(0) + // + // if s.recv.val: + // s.send[ s.out_dir ].val @= b1(1) + + always_comb begin : up_ru_routing + out_dir = recv__msg.dst; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) + send__val[3'(i)] = 1'd0; + if ( recv__val ) begin + send__val[out_dir] = 1'd1; + end + end + + assign send__msg[0] = recv__msg; + assign send_val[0:0] = send__val[0]; + assign send__msg[1] = recv__msg; + assign send_val[1:1] = send__val[1]; + assign send__msg[2] = recv__msg; + assign send_val[2:2] = send__val[2]; + assign send__msg[3] = recv__msg; + assign send_val[3:3] = send__val[3]; + assign send__msg[4] = recv__msg; + assign send_val[4:4] = send__val[4]; + assign send__msg[5] = recv__msg; + assign send_val[5:5] = send__val[5]; + assign send__msg[6] = recv__msg; + assign send_val[6:6] = send__val[6]; + assign send__msg[7] = recv__msg; + assign send_val[7:7] = send__val[7]; + +endmodule + + +// PyMTL Component RegEnRst Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py + +module RegEnRst__Type_Bits3__reset_value_1 +( + input logic [0:0] clk , + input logic [0:0] en , + input logic [2:0] in_ , + output logic [2:0] out , + input logic [0:0] reset +); + localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 + // @update_ff + // def up_regenrst(): + // if s.reset: s.out <<= reset_value + // elif s.en: s.out <<= s.in_ + + always_ff @(posedge clk) begin : up_regenrst + if ( reset ) begin + out <= 3'( __const__reset_value_at_up_regenrst ); + end + else if ( en ) begin + out <= in_; + end + end + +endmodule + + +// PyMTL Component RoundRobinArbiterEn Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py + +module RoundRobinArbiterEn__nreqs_3 +( + input logic [0:0] clk , + input logic [0:0] en , + output logic [2:0] grants , + input logic [2:0] reqs , + input logic [0:0] reset +); + localparam logic [1:0] __const__nreqs_at_comb_reqs_int = 2'd3; + localparam logic [2:0] __const__nreqsX2_at_comb_reqs_int = 3'd6; + localparam logic [1:0] __const__nreqs_at_comb_grants = 2'd3; + localparam logic [1:0] __const__nreqs_at_comb_priority_int = 2'd3; + localparam logic [2:0] __const__nreqsX2_at_comb_priority_int = 3'd6; + localparam logic [2:0] __const__nreqsX2_at_comb_kills = 3'd6; + localparam logic [2:0] __const__nreqsX2_at_comb_grants_int = 3'd6; + logic [5:0] grants_int; + logic [6:0] kills; + logic [0:0] priority_en; + logic [5:0] priority_int; + logic [5:0] reqs_int; + //------------------------------------------------------------- + // Component priority_reg + //------------------------------------------------------------- + + logic [0:0] priority_reg__clk; + logic [0:0] priority_reg__en; + logic [2:0] priority_reg__in_; + logic [2:0] priority_reg__out; + logic [0:0] priority_reg__reset; + + RegEnRst__Type_Bits3__reset_value_1 priority_reg + ( + .clk( priority_reg__clk ), + .en( priority_reg__en ), + .in_( priority_reg__in_ ), + .out( priority_reg__out ), + .reset( priority_reg__reset ) + ); + + //------------------------------------------------------------- + // End of component priority_reg + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 + // @update + // def comb_grants(): + // for i in range( nreqs ): + // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] + + always_comb begin : comb_grants + for ( int unsigned i = 1'd0; i < 2'( __const__nreqs_at_comb_grants ); i += 1'd1 ) + grants[2'(i)] = grants_int[3'(i)] | grants_int[3'( __const__nreqs_at_comb_grants ) + 3'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 + // @update + // def comb_grants_int(): + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.grants_int[i] @= s.reqs_int[i] + // else: + // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] + + always_comb begin : comb_grants_int + for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) + if ( priority_int[3'(i)] ) begin + grants_int[3'(i)] = reqs_int[3'(i)]; + end + else + grants_int[3'(i)] = ( ~kills[3'(i)] ) & reqs_int[3'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 + // @update + // def comb_kills(): + // s.kills[0] @= 1 + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.kills[i+1] @= s.reqs_int[i] + // else: + // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) + + always_comb begin : comb_kills + kills[3'd0] = 1'd1; + for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) + if ( priority_int[3'(i)] ) begin + kills[3'(i) + 3'd1] = reqs_int[3'(i)]; + end + else + kills[3'(i) + 3'd1] = kills[3'(i)] | ( ( ~kills[3'(i)] ) & reqs_int[3'(i)] ); + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 + // @update + // def comb_priority_en(): + // s.priority_en @= ( s.grants != 0 ) & s.en + + always_comb begin : comb_priority_en + priority_en = ( grants != 3'd0 ) & en; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 + // @update + // def comb_priority_int(): + // s.priority_int[ 0:nreqs ] @= s.priority_reg.out + // s.priority_int[nreqs:nreqsX2] @= 0 + + always_comb begin : comb_priority_int + priority_int[3'd2:3'd0] = priority_reg__out; + priority_int[3'd5:3'( __const__nreqs_at_comb_priority_int )] = 3'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 + // @update + // def comb_reqs_int(): + // s.reqs_int [ 0:nreqs ] @= s.reqs + // s.reqs_int [nreqs:nreqsX2] @= s.reqs + + always_comb begin : comb_reqs_int + reqs_int[3'd2:3'd0] = reqs; + reqs_int[3'd5:3'( __const__nreqs_at_comb_reqs_int )] = reqs; + end + + assign priority_reg__clk = clk; + assign priority_reg__reset = reset; + assign priority_reg__en = priority_en; + assign priority_reg__in_[2:1] = grants[1:0]; + assign priority_reg__in_[0:0] = grants[2:2]; + +endmodule + + +// PyMTL Component Encoder Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py + +module Encoder__in_nbits_3__out_nbits_2 +( + input logic [0:0] clk , + input logic [2:0] in_ , + output logic [1:0] out , + input logic [0:0] reset +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 + // @update + // def encode(): + // s.out @= 0 + // for i in range( s.in_nbits ): + // if s.in_[i]: + // s.out @= i + + always_comb begin : encode + out = 2'd0; + for ( int unsigned i = 1'd0; i < 2'd3; i += 1'd1 ) + if ( in_[2'(i)] ) begin + out = 2'(i); + end + end + +endmodule + + +// PyMTL Component Mux Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_3 +( + input logic [0:0] clk , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 in_ [0:2], + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 out , + input logic [0:0] reset , + input logic [1:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component SwitchUnitRTL Definition +// Full name: SwitchUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_inports_3 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py + +module SwitchUnitRTL__4cc70db240bb572a +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg [0:2] , + output logic [0:0] recv__rdy [0:2] , + input logic [0:0] recv__val [0:2] , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [1:0] __const__num_inports_at_up_get_en = 2'd3; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [2:0] arbiter__grants; + logic [2:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_3 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [2:0] encoder__in_; + logic [1:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_3__out_nbits_2 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__in_ [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__out; + logic [0:0] mux__reset; + logic [1:0] mux__sel; + + Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_3 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 + // @update + // def up_get_en(): + // for i in range( num_inports ): + // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) + + always_comb begin : up_get_en + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_up_get_en ); i += 1'd1 ) + recv__rdy[2'(i)] = send__rdy & ( mux__sel == 2'(i) ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 + // @update + // def up_send_val(): + // s.send.val @= s.arbiter.grants > 0 + + always_comb begin : up_send_val + send__val = arbiter__grants > 3'd0; + end + + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign arbiter__en = 1'd1; + assign mux__clk = clk; + assign mux__reset = reset; + assign send__msg = mux__out; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign encoder__in_ = arbiter__grants; + assign mux__sel = encoder__out; + assign arbiter__reqs[0:0] = recv__val[0]; + assign mux__in_[0] = recv__msg[0]; + assign arbiter__reqs[1:1] = recv__val[1]; + assign mux__in_[1] = recv__msg[1]; + assign arbiter__reqs[2:2] = recv__val[2]; + assign mux__in_[2] = recv__msg[2]; + +endmodule + + +// PyMTL Component XbarBypassQueueRTL Definition +// Full name: XbarBypassQueueRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_inports_3__num_outports_8__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarBypassQueueRTL.py + +module XbarBypassQueueRTL__510da12df6787984 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg [0:2] , + output logic [0:0] recv__rdy [0:2] , + input logic [0:0] recv__val [0:2] , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg [0:7] , + input logic [0:0] send__rdy [0:7] , + output logic [0:0] send__val [0:7] +); + //------------------------------------------------------------- + // Component input_units[0:2] + //------------------------------------------------------------- + + logic [0:0] input_units__clk [0:2]; + logic [0:0] input_units__reset [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 input_units__recv__msg [0:2]; + logic [0:0] input_units__recv__rdy [0:2]; + logic [0:0] input_units__recv__val [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 input_units__send__msg [0:2]; + logic [0:0] input_units__send__rdy [0:2]; + logic [0:0] input_units__send__val [0:2]; + + InputUnitRTL__cff279ef5009e7c6 input_units__0 + ( + .clk( input_units__clk[0] ), + .reset( input_units__reset[0] ), + .recv__msg( input_units__recv__msg[0] ), + .recv__rdy( input_units__recv__rdy[0] ), + .recv__val( input_units__recv__val[0] ), + .send__msg( input_units__send__msg[0] ), + .send__rdy( input_units__send__rdy[0] ), + .send__val( input_units__send__val[0] ) + ); + + InputUnitRTL__cff279ef5009e7c6 input_units__1 + ( + .clk( input_units__clk[1] ), + .reset( input_units__reset[1] ), + .recv__msg( input_units__recv__msg[1] ), + .recv__rdy( input_units__recv__rdy[1] ), + .recv__val( input_units__recv__val[1] ), + .send__msg( input_units__send__msg[1] ), + .send__rdy( input_units__send__rdy[1] ), + .send__val( input_units__send__val[1] ) + ); + + InputUnitRTL__cff279ef5009e7c6 input_units__2 + ( + .clk( input_units__clk[2] ), + .reset( input_units__reset[2] ), + .recv__msg( input_units__recv__msg[2] ), + .recv__rdy( input_units__recv__rdy[2] ), + .recv__val( input_units__recv__val[2] ), + .send__msg( input_units__send__msg[2] ), + .send__rdy( input_units__send__rdy[2] ), + .send__val( input_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component input_units[0:2] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component output_units[0:7] + //------------------------------------------------------------- + + logic [0:0] output_units__clk [0:7]; + logic [0:0] output_units__reset [0:7]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 output_units__recv__msg [0:7]; + logic [0:0] output_units__recv__rdy [0:7]; + logic [0:0] output_units__recv__val [0:7]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 output_units__send__msg [0:7]; + logic [0:0] output_units__send__rdy [0:7]; + logic [0:0] output_units__send__val [0:7]; + + OutputUnitRTL__e96d78a3d0126314 output_units__0 + ( + .clk( output_units__clk[0] ), + .reset( output_units__reset[0] ), + .recv__msg( output_units__recv__msg[0] ), + .recv__rdy( output_units__recv__rdy[0] ), + .recv__val( output_units__recv__val[0] ), + .send__msg( output_units__send__msg[0] ), + .send__rdy( output_units__send__rdy[0] ), + .send__val( output_units__send__val[0] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__1 + ( + .clk( output_units__clk[1] ), + .reset( output_units__reset[1] ), + .recv__msg( output_units__recv__msg[1] ), + .recv__rdy( output_units__recv__rdy[1] ), + .recv__val( output_units__recv__val[1] ), + .send__msg( output_units__send__msg[1] ), + .send__rdy( output_units__send__rdy[1] ), + .send__val( output_units__send__val[1] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__2 + ( + .clk( output_units__clk[2] ), + .reset( output_units__reset[2] ), + .recv__msg( output_units__recv__msg[2] ), + .recv__rdy( output_units__recv__rdy[2] ), + .recv__val( output_units__recv__val[2] ), + .send__msg( output_units__send__msg[2] ), + .send__rdy( output_units__send__rdy[2] ), + .send__val( output_units__send__val[2] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__3 + ( + .clk( output_units__clk[3] ), + .reset( output_units__reset[3] ), + .recv__msg( output_units__recv__msg[3] ), + .recv__rdy( output_units__recv__rdy[3] ), + .recv__val( output_units__recv__val[3] ), + .send__msg( output_units__send__msg[3] ), + .send__rdy( output_units__send__rdy[3] ), + .send__val( output_units__send__val[3] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__4 + ( + .clk( output_units__clk[4] ), + .reset( output_units__reset[4] ), + .recv__msg( output_units__recv__msg[4] ), + .recv__rdy( output_units__recv__rdy[4] ), + .recv__val( output_units__recv__val[4] ), + .send__msg( output_units__send__msg[4] ), + .send__rdy( output_units__send__rdy[4] ), + .send__val( output_units__send__val[4] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__5 + ( + .clk( output_units__clk[5] ), + .reset( output_units__reset[5] ), + .recv__msg( output_units__recv__msg[5] ), + .recv__rdy( output_units__recv__rdy[5] ), + .recv__val( output_units__recv__val[5] ), + .send__msg( output_units__send__msg[5] ), + .send__rdy( output_units__send__rdy[5] ), + .send__val( output_units__send__val[5] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__6 + ( + .clk( output_units__clk[6] ), + .reset( output_units__reset[6] ), + .recv__msg( output_units__recv__msg[6] ), + .recv__rdy( output_units__recv__rdy[6] ), + .recv__val( output_units__recv__val[6] ), + .send__msg( output_units__send__msg[6] ), + .send__rdy( output_units__send__rdy[6] ), + .send__val( output_units__send__val[6] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__7 + ( + .clk( output_units__clk[7] ), + .reset( output_units__reset[7] ), + .recv__msg( output_units__recv__msg[7] ), + .recv__rdy( output_units__recv__rdy[7] ), + .recv__val( output_units__recv__val[7] ), + .send__msg( output_units__send__msg[7] ), + .send__rdy( output_units__send__rdy[7] ), + .send__val( output_units__send__val[7] ) + ); + + //------------------------------------------------------------- + // End of component output_units[0:7] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component route_units[0:2] + //------------------------------------------------------------- + + logic [0:0] route_units__clk [0:2]; + logic [0:0] route_units__reset [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 route_units__recv__msg [0:2]; + logic [0:0] route_units__recv__rdy [0:2]; + logic [0:0] route_units__recv__val [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 route_units__send__msg [0:2][0:7]; + logic [0:0] route_units__send__rdy [0:2][0:7]; + logic [0:0] route_units__send__val [0:2][0:7]; + + XbarRouteUnitRTL__c063f4910bbc0b50 route_units__0 + ( + .clk( route_units__clk[0] ), + .reset( route_units__reset[0] ), + .recv__msg( route_units__recv__msg[0] ), + .recv__rdy( route_units__recv__rdy[0] ), + .recv__val( route_units__recv__val[0] ), + .send__msg( route_units__send__msg[0] ), + .send__rdy( route_units__send__rdy[0] ), + .send__val( route_units__send__val[0] ) + ); + + XbarRouteUnitRTL__c063f4910bbc0b50 route_units__1 + ( + .clk( route_units__clk[1] ), + .reset( route_units__reset[1] ), + .recv__msg( route_units__recv__msg[1] ), + .recv__rdy( route_units__recv__rdy[1] ), + .recv__val( route_units__recv__val[1] ), + .send__msg( route_units__send__msg[1] ), + .send__rdy( route_units__send__rdy[1] ), + .send__val( route_units__send__val[1] ) + ); + + XbarRouteUnitRTL__c063f4910bbc0b50 route_units__2 + ( + .clk( route_units__clk[2] ), + .reset( route_units__reset[2] ), + .recv__msg( route_units__recv__msg[2] ), + .recv__rdy( route_units__recv__rdy[2] ), + .recv__val( route_units__recv__val[2] ), + .send__msg( route_units__send__msg[2] ), + .send__rdy( route_units__send__rdy[2] ), + .send__val( route_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component route_units[0:2] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component switch_units[0:7] + //------------------------------------------------------------- + + logic [0:0] switch_units__clk [0:7]; + logic [0:0] switch_units__reset [0:7]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 switch_units__recv__msg [0:7][0:2]; + logic [0:0] switch_units__recv__rdy [0:7][0:2]; + logic [0:0] switch_units__recv__val [0:7][0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 switch_units__send__msg [0:7]; + logic [0:0] switch_units__send__rdy [0:7]; + logic [0:0] switch_units__send__val [0:7]; + + SwitchUnitRTL__4cc70db240bb572a switch_units__0 + ( + .clk( switch_units__clk[0] ), + .reset( switch_units__reset[0] ), + .recv__msg( switch_units__recv__msg[0] ), + .recv__rdy( switch_units__recv__rdy[0] ), + .recv__val( switch_units__recv__val[0] ), + .send__msg( switch_units__send__msg[0] ), + .send__rdy( switch_units__send__rdy[0] ), + .send__val( switch_units__send__val[0] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__1 + ( + .clk( switch_units__clk[1] ), + .reset( switch_units__reset[1] ), + .recv__msg( switch_units__recv__msg[1] ), + .recv__rdy( switch_units__recv__rdy[1] ), + .recv__val( switch_units__recv__val[1] ), + .send__msg( switch_units__send__msg[1] ), + .send__rdy( switch_units__send__rdy[1] ), + .send__val( switch_units__send__val[1] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__2 + ( + .clk( switch_units__clk[2] ), + .reset( switch_units__reset[2] ), + .recv__msg( switch_units__recv__msg[2] ), + .recv__rdy( switch_units__recv__rdy[2] ), + .recv__val( switch_units__recv__val[2] ), + .send__msg( switch_units__send__msg[2] ), + .send__rdy( switch_units__send__rdy[2] ), + .send__val( switch_units__send__val[2] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__3 + ( + .clk( switch_units__clk[3] ), + .reset( switch_units__reset[3] ), + .recv__msg( switch_units__recv__msg[3] ), + .recv__rdy( switch_units__recv__rdy[3] ), + .recv__val( switch_units__recv__val[3] ), + .send__msg( switch_units__send__msg[3] ), + .send__rdy( switch_units__send__rdy[3] ), + .send__val( switch_units__send__val[3] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__4 + ( + .clk( switch_units__clk[4] ), + .reset( switch_units__reset[4] ), + .recv__msg( switch_units__recv__msg[4] ), + .recv__rdy( switch_units__recv__rdy[4] ), + .recv__val( switch_units__recv__val[4] ), + .send__msg( switch_units__send__msg[4] ), + .send__rdy( switch_units__send__rdy[4] ), + .send__val( switch_units__send__val[4] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__5 + ( + .clk( switch_units__clk[5] ), + .reset( switch_units__reset[5] ), + .recv__msg( switch_units__recv__msg[5] ), + .recv__rdy( switch_units__recv__rdy[5] ), + .recv__val( switch_units__recv__val[5] ), + .send__msg( switch_units__send__msg[5] ), + .send__rdy( switch_units__send__rdy[5] ), + .send__val( switch_units__send__val[5] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__6 + ( + .clk( switch_units__clk[6] ), + .reset( switch_units__reset[6] ), + .recv__msg( switch_units__recv__msg[6] ), + .recv__rdy( switch_units__recv__rdy[6] ), + .recv__val( switch_units__recv__val[6] ), + .send__msg( switch_units__send__msg[6] ), + .send__rdy( switch_units__send__rdy[6] ), + .send__val( switch_units__send__val[6] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__7 + ( + .clk( switch_units__clk[7] ), + .reset( switch_units__reset[7] ), + .recv__msg( switch_units__recv__msg[7] ), + .recv__rdy( switch_units__recv__rdy[7] ), + .recv__val( switch_units__recv__val[7] ), + .send__msg( switch_units__send__msg[7] ), + .send__rdy( switch_units__send__rdy[7] ), + .send__val( switch_units__send__val[7] ) + ); + + //------------------------------------------------------------- + // End of component switch_units[0:7] + //------------------------------------------------------------- + + assign input_units__clk[0] = clk; + assign input_units__reset[0] = reset; + assign input_units__clk[1] = clk; + assign input_units__reset[1] = reset; + assign input_units__clk[2] = clk; + assign input_units__reset[2] = reset; + assign route_units__clk[0] = clk; + assign route_units__reset[0] = reset; + assign route_units__clk[1] = clk; + assign route_units__reset[1] = reset; + assign route_units__clk[2] = clk; + assign route_units__reset[2] = reset; + assign switch_units__clk[0] = clk; + assign switch_units__reset[0] = reset; + assign switch_units__clk[1] = clk; + assign switch_units__reset[1] = reset; + assign switch_units__clk[2] = clk; + assign switch_units__reset[2] = reset; + assign switch_units__clk[3] = clk; + assign switch_units__reset[3] = reset; + assign switch_units__clk[4] = clk; + assign switch_units__reset[4] = reset; + assign switch_units__clk[5] = clk; + assign switch_units__reset[5] = reset; + assign switch_units__clk[6] = clk; + assign switch_units__reset[6] = reset; + assign switch_units__clk[7] = clk; + assign switch_units__reset[7] = reset; + assign output_units__clk[0] = clk; + assign output_units__reset[0] = reset; + assign output_units__clk[1] = clk; + assign output_units__reset[1] = reset; + assign output_units__clk[2] = clk; + assign output_units__reset[2] = reset; + assign output_units__clk[3] = clk; + assign output_units__reset[3] = reset; + assign output_units__clk[4] = clk; + assign output_units__reset[4] = reset; + assign output_units__clk[5] = clk; + assign output_units__reset[5] = reset; + assign output_units__clk[6] = clk; + assign output_units__reset[6] = reset; + assign output_units__clk[7] = clk; + assign output_units__reset[7] = reset; + assign input_units__recv__msg[0] = recv__msg[0]; + assign recv__rdy[0] = input_units__recv__rdy[0]; + assign input_units__recv__val[0] = recv__val[0]; + assign route_units__recv__msg[0] = input_units__send__msg[0]; + assign input_units__send__rdy[0] = route_units__recv__rdy[0]; + assign route_units__recv__val[0] = input_units__send__val[0]; + assign input_units__recv__msg[1] = recv__msg[1]; + assign recv__rdy[1] = input_units__recv__rdy[1]; + assign input_units__recv__val[1] = recv__val[1]; + assign route_units__recv__msg[1] = input_units__send__msg[1]; + assign input_units__send__rdy[1] = route_units__recv__rdy[1]; + assign route_units__recv__val[1] = input_units__send__val[1]; + assign input_units__recv__msg[2] = recv__msg[2]; + assign recv__rdy[2] = input_units__recv__rdy[2]; + assign input_units__recv__val[2] = recv__val[2]; + assign route_units__recv__msg[2] = input_units__send__msg[2]; + assign input_units__send__rdy[2] = route_units__recv__rdy[2]; + assign route_units__recv__val[2] = input_units__send__val[2]; + assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; + assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; + assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; + assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; + assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; + assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; + assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; + assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; + assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; + assign switch_units__recv__msg[3][0] = route_units__send__msg[0][3]; + assign route_units__send__rdy[0][3] = switch_units__recv__rdy[3][0]; + assign switch_units__recv__val[3][0] = route_units__send__val[0][3]; + assign switch_units__recv__msg[4][0] = route_units__send__msg[0][4]; + assign route_units__send__rdy[0][4] = switch_units__recv__rdy[4][0]; + assign switch_units__recv__val[4][0] = route_units__send__val[0][4]; + assign switch_units__recv__msg[5][0] = route_units__send__msg[0][5]; + assign route_units__send__rdy[0][5] = switch_units__recv__rdy[5][0]; + assign switch_units__recv__val[5][0] = route_units__send__val[0][5]; + assign switch_units__recv__msg[6][0] = route_units__send__msg[0][6]; + assign route_units__send__rdy[0][6] = switch_units__recv__rdy[6][0]; + assign switch_units__recv__val[6][0] = route_units__send__val[0][6]; + assign switch_units__recv__msg[7][0] = route_units__send__msg[0][7]; + assign route_units__send__rdy[0][7] = switch_units__recv__rdy[7][0]; + assign switch_units__recv__val[7][0] = route_units__send__val[0][7]; + assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; + assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; + assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; + assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; + assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; + assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; + assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; + assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; + assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; + assign switch_units__recv__msg[3][1] = route_units__send__msg[1][3]; + assign route_units__send__rdy[1][3] = switch_units__recv__rdy[3][1]; + assign switch_units__recv__val[3][1] = route_units__send__val[1][3]; + assign switch_units__recv__msg[4][1] = route_units__send__msg[1][4]; + assign route_units__send__rdy[1][4] = switch_units__recv__rdy[4][1]; + assign switch_units__recv__val[4][1] = route_units__send__val[1][4]; + assign switch_units__recv__msg[5][1] = route_units__send__msg[1][5]; + assign route_units__send__rdy[1][5] = switch_units__recv__rdy[5][1]; + assign switch_units__recv__val[5][1] = route_units__send__val[1][5]; + assign switch_units__recv__msg[6][1] = route_units__send__msg[1][6]; + assign route_units__send__rdy[1][6] = switch_units__recv__rdy[6][1]; + assign switch_units__recv__val[6][1] = route_units__send__val[1][6]; + assign switch_units__recv__msg[7][1] = route_units__send__msg[1][7]; + assign route_units__send__rdy[1][7] = switch_units__recv__rdy[7][1]; + assign switch_units__recv__val[7][1] = route_units__send__val[1][7]; + assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; + assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; + assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; + assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; + assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; + assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; + assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; + assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; + assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; + assign switch_units__recv__msg[3][2] = route_units__send__msg[2][3]; + assign route_units__send__rdy[2][3] = switch_units__recv__rdy[3][2]; + assign switch_units__recv__val[3][2] = route_units__send__val[2][3]; + assign switch_units__recv__msg[4][2] = route_units__send__msg[2][4]; + assign route_units__send__rdy[2][4] = switch_units__recv__rdy[4][2]; + assign switch_units__recv__val[4][2] = route_units__send__val[2][4]; + assign switch_units__recv__msg[5][2] = route_units__send__msg[2][5]; + assign route_units__send__rdy[2][5] = switch_units__recv__rdy[5][2]; + assign switch_units__recv__val[5][2] = route_units__send__val[2][5]; + assign switch_units__recv__msg[6][2] = route_units__send__msg[2][6]; + assign route_units__send__rdy[2][6] = switch_units__recv__rdy[6][2]; + assign switch_units__recv__val[6][2] = route_units__send__val[2][6]; + assign switch_units__recv__msg[7][2] = route_units__send__msg[2][7]; + assign route_units__send__rdy[2][7] = switch_units__recv__rdy[7][2]; + assign switch_units__recv__val[7][2] = route_units__send__val[2][7]; + assign output_units__recv__msg[0] = switch_units__send__msg[0]; + assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; + assign output_units__recv__val[0] = switch_units__send__val[0]; + assign send__msg[0] = output_units__send__msg[0]; + assign output_units__send__rdy[0] = send__rdy[0]; + assign send__val[0] = output_units__send__val[0]; + assign output_units__recv__msg[1] = switch_units__send__msg[1]; + assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; + assign output_units__recv__val[1] = switch_units__send__val[1]; + assign send__msg[1] = output_units__send__msg[1]; + assign output_units__send__rdy[1] = send__rdy[1]; + assign send__val[1] = output_units__send__val[1]; + assign output_units__recv__msg[2] = switch_units__send__msg[2]; + assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; + assign output_units__recv__val[2] = switch_units__send__val[2]; + assign send__msg[2] = output_units__send__msg[2]; + assign output_units__send__rdy[2] = send__rdy[2]; + assign send__val[2] = output_units__send__val[2]; + assign output_units__recv__msg[3] = switch_units__send__msg[3]; + assign switch_units__send__rdy[3] = output_units__recv__rdy[3]; + assign output_units__recv__val[3] = switch_units__send__val[3]; + assign send__msg[3] = output_units__send__msg[3]; + assign output_units__send__rdy[3] = send__rdy[3]; + assign send__val[3] = output_units__send__val[3]; + assign output_units__recv__msg[4] = switch_units__send__msg[4]; + assign switch_units__send__rdy[4] = output_units__recv__rdy[4]; + assign output_units__recv__val[4] = switch_units__send__val[4]; + assign send__msg[4] = output_units__send__msg[4]; + assign output_units__send__rdy[4] = send__rdy[4]; + assign send__val[4] = output_units__send__val[4]; + assign output_units__recv__msg[5] = switch_units__send__msg[5]; + assign switch_units__send__rdy[5] = output_units__recv__rdy[5]; + assign output_units__recv__val[5] = switch_units__send__val[5]; + assign send__msg[5] = output_units__send__msg[5]; + assign output_units__send__rdy[5] = send__rdy[5]; + assign send__val[5] = output_units__send__val[5]; + assign output_units__recv__msg[6] = switch_units__send__msg[6]; + assign switch_units__send__rdy[6] = output_units__recv__rdy[6]; + assign output_units__recv__val[6] = switch_units__send__val[6]; + assign send__msg[6] = output_units__send__msg[6]; + assign output_units__send__rdy[6] = send__rdy[6]; + assign send__val[6] = output_units__send__val[6]; + assign output_units__recv__msg[7] = switch_units__send__msg[7]; + assign switch_units__send__rdy[7] = output_units__recv__rdy[7]; + assign output_units__recv__val[7] = switch_units__send__val[7]; + assign send__msg[7] = output_units__send__msg[7]; + assign output_units__send__rdy[7] = send__rdy[7]; + assign send__val[7] = output_units__send__val[7]; + +endmodule + + +// PyMTL Component DataMemControllerRTL Definition +// Full name: DataMemControllerRTL__NocPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_rd_tiles_7__num_wr_tiles_7__multi_cgra_rows_2__multi_cgra_columns_2__num_tiles_16__mem_access_is_combinational_True__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)} +// At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py + +module DataMemControllerRTL__20df9b544ed809f0 +( + input logic [6:0] address_lower , + input logic [6:0] address_upper , + input logic [1:0] cgra_id , + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_load_request__msg , + output logic [0:0] recv_from_noc_load_request__rdy , + input logic [0:0] recv_from_noc_load_request__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_load_response_pkt__msg , + output logic [0:0] recv_from_noc_load_response_pkt__rdy , + input logic [0:0] recv_from_noc_load_response_pkt__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_store_request__msg , + output logic [0:0] recv_from_noc_store_request__rdy , + input logic [0:0] recv_from_noc_store_request__val , + input logic [6:0] recv_raddr__msg [0:6] , + output logic [0:0] recv_raddr__rdy [0:6] , + input logic [0:0] recv_raddr__val [0:6] , + input logic [6:0] recv_waddr__msg [0:6] , + output logic [0:0] recv_waddr__rdy [0:6] , + input logic [0:0] recv_waddr__val [0:6] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_wdata__msg [0:6] , + output logic [0:0] recv_wdata__rdy [0:6] , + input logic [0:0] recv_wdata__val [0:6] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_rdata__msg [0:6] , + input logic [0:0] send_rdata__rdy [0:6] , + output logic [0:0] send_rdata__val [0:6] , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_load_request_pkt__msg , + input logic [0:0] send_to_noc_load_request_pkt__rdy , + output logic [0:0] send_to_noc_load_request_pkt__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_load_response_pkt__msg , + input logic [0:0] send_to_noc_load_response_pkt__rdy , + output logic [0:0] send_to_noc_load_response_pkt__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_store_pkt__msg , + input logic [0:0] send_to_noc_store_pkt__rdy , + output logic [0:0] send_to_noc_store_pkt__val +); + localparam logic [3:0] __const__num_xbar_in_rd_ports_at_assemble_xbar_pkt = 4'd8; + localparam logic [3:0] __const__num_xbar_in_wr_ports_at_assemble_xbar_pkt = 4'd8; + localparam logic [2:0] __const__num_rd_tiles_at_assemble_xbar_pkt = 3'd7; + localparam logic [2:0] __const__per_bank_addr_nbits_at_assemble_xbar_pkt = 3'd4; + localparam logic [1:0] __const__num_banks_per_cgra_at_assemble_xbar_pkt = 2'd2; + localparam logic [2:0] __const__num_wr_tiles_at_assemble_xbar_pkt = 3'd7; + localparam logic [2:0] __const__num_rd_tiles_at_update_all = 3'd7; + localparam logic [2:0] __const__num_wr_tiles_at_update_all = 3'd7; + localparam logic [3:0] __const__num_xbar_in_rd_ports_at_update_all = 4'd8; + localparam logic [3:0] __const__num_xbar_in_wr_ports_at_update_all = 4'd8; + localparam logic [3:0] __const__CMD_LOAD_RESPONSE = 4'd11; + localparam logic [1:0] __const__num_banks_per_cgra_at_update_all = 2'd2; + localparam logic [3:0] __const__CMD_LOAD_REQUEST = 4'd10; + localparam logic [3:0] __const__CMD_STORE_REQUEST = 4'd12; + logic [0:0] idTo2d_x_lut [0:3]; + logic [0:0] idTo2d_y_lut [0:3]; + MemAccessPacket_8_3_128__43c148781d2f2a57 rd_pkt [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 wr_pkt [0:7]; + //------------------------------------------------------------- + // Component memory_wrapper[0:1] + //------------------------------------------------------------- + + logic [0:0] memory_wrapper__clk [0:1]; + logic [0:0] memory_wrapper__reset [0:1]; + MemAccessPacket_8_3_128__43c148781d2f2a57 memory_wrapper__recv_rd__msg [0:1]; + logic [0:0] memory_wrapper__recv_rd__rdy [0:1]; + logic [0:0] memory_wrapper__recv_rd__val [0:1]; + MemAccessPacket_8_3_128__43c148781d2f2a57 memory_wrapper__recv_wr__msg [0:1]; + logic [0:0] memory_wrapper__recv_wr__rdy [0:1]; + logic [0:0] memory_wrapper__recv_wr__val [0:1]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 memory_wrapper__send__msg [0:1]; + logic [0:0] memory_wrapper__send__rdy [0:1]; + logic [0:0] memory_wrapper__send__val [0:1]; + + DataMemWrapperRTL__33e0a5b37976e571 memory_wrapper__0 + ( + .clk( memory_wrapper__clk[0] ), + .reset( memory_wrapper__reset[0] ), + .recv_rd__msg( memory_wrapper__recv_rd__msg[0] ), + .recv_rd__rdy( memory_wrapper__recv_rd__rdy[0] ), + .recv_rd__val( memory_wrapper__recv_rd__val[0] ), + .recv_wr__msg( memory_wrapper__recv_wr__msg[0] ), + .recv_wr__rdy( memory_wrapper__recv_wr__rdy[0] ), + .recv_wr__val( memory_wrapper__recv_wr__val[0] ), + .send__msg( memory_wrapper__send__msg[0] ), + .send__rdy( memory_wrapper__send__rdy[0] ), + .send__val( memory_wrapper__send__val[0] ) + ); + + DataMemWrapperRTL__33e0a5b37976e571 memory_wrapper__1 + ( + .clk( memory_wrapper__clk[1] ), + .reset( memory_wrapper__reset[1] ), + .recv_rd__msg( memory_wrapper__recv_rd__msg[1] ), + .recv_rd__rdy( memory_wrapper__recv_rd__rdy[1] ), + .recv_rd__val( memory_wrapper__recv_rd__val[1] ), + .recv_wr__msg( memory_wrapper__recv_wr__msg[1] ), + .recv_wr__rdy( memory_wrapper__recv_wr__rdy[1] ), + .recv_wr__val( memory_wrapper__recv_wr__val[1] ), + .send__msg( memory_wrapper__send__msg[1] ), + .send__rdy( memory_wrapper__send__rdy[1] ), + .send__val( memory_wrapper__send__val[1] ) + ); + + //------------------------------------------------------------- + // End of component memory_wrapper[0:1] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component read_crossbar + //------------------------------------------------------------- + + logic [0:0] read_crossbar__clk; + logic [0:0] read_crossbar__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 read_crossbar__recv__msg [0:7]; + logic [0:0] read_crossbar__recv__rdy [0:7]; + logic [0:0] read_crossbar__recv__val [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 read_crossbar__send__msg [0:2]; + logic [0:0] read_crossbar__send__rdy [0:2]; + logic [0:0] read_crossbar__send__val [0:2]; + + XbarBypassQueueRTL__045133ee283ca701 read_crossbar + ( + .clk( read_crossbar__clk ), + .reset( read_crossbar__reset ), + .recv__msg( read_crossbar__recv__msg ), + .recv__rdy( read_crossbar__recv__rdy ), + .recv__val( read_crossbar__recv__val ), + .send__msg( read_crossbar__send__msg ), + .send__rdy( read_crossbar__send__rdy ), + .send__val( read_crossbar__send__val ) + ); + + //------------------------------------------------------------- + // End of component read_crossbar + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component response_crossbar + //------------------------------------------------------------- + + logic [0:0] response_crossbar__clk; + logic [0:0] response_crossbar__reset; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 response_crossbar__recv__msg [0:2]; + logic [0:0] response_crossbar__recv__rdy [0:2]; + logic [0:0] response_crossbar__recv__val [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 response_crossbar__send__msg [0:7]; + logic [0:0] response_crossbar__send__rdy [0:7]; + logic [0:0] response_crossbar__send__val [0:7]; + + XbarBypassQueueRTL__510da12df6787984 response_crossbar + ( + .clk( response_crossbar__clk ), + .reset( response_crossbar__reset ), + .recv__msg( response_crossbar__recv__msg ), + .recv__rdy( response_crossbar__recv__rdy ), + .recv__val( response_crossbar__recv__val ), + .send__msg( response_crossbar__send__msg ), + .send__rdy( response_crossbar__send__rdy ), + .send__val( response_crossbar__send__val ) + ); + + //------------------------------------------------------------- + // End of component response_crossbar + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component write_crossbar + //------------------------------------------------------------- + + logic [0:0] write_crossbar__clk; + logic [0:0] write_crossbar__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 write_crossbar__recv__msg [0:7]; + logic [0:0] write_crossbar__recv__rdy [0:7]; + logic [0:0] write_crossbar__recv__val [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 write_crossbar__send__msg [0:2]; + logic [0:0] write_crossbar__send__rdy [0:2]; + logic [0:0] write_crossbar__send__val [0:2]; + + XbarBypassQueueRTL__045133ee283ca701 write_crossbar + ( + .clk( write_crossbar__clk ), + .reset( write_crossbar__reset ), + .recv__msg( write_crossbar__recv__msg ), + .recv__rdy( write_crossbar__recv__rdy ), + .recv__val( write_crossbar__recv__val ), + .send__msg( write_crossbar__send__msg ), + .send__rdy( write_crossbar__send__rdy ), + .send__val( write_crossbar__send__val ) + ); + + //------------------------------------------------------------- + // End of component write_crossbar + //------------------------------------------------------------- + logic [6:0] __tmpvar__assemble_xbar_pkt_recv_raddr; + logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_load_local; + logic [6:0] __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc; + logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc; + logic [6:0] __tmpvar__assemble_xbar_pkt_recv_waddr; + logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_store_local; + logic [6:0] __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc; + logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc; + logic [1:0] __tmpvar__update_all_from_cgra_id; + logic [4:0] __tmpvar__update_all_from_tile_id; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py:159 + // @update + // def assemble_xbar_pkt(): + // for i in range(num_xbar_in_rd_ports): + // s.rd_pkt[i] @= MemReadPktType(i, 0, 0, DataType(0, 0, 0, 0), 0, 0, i, 0, 0, 0) + // + // for i in range(num_xbar_in_wr_ports): + // s.wr_pkt[i] @= MemWritePktType(i, 0, 0, DataType(0, 0, 0, 0), 0, 0, i, 0, 0, 0) + // + // for i in range(num_rd_tiles): + // recv_raddr = s.recv_raddr[i].msg + // # Calculates the target bank index for load. + // if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper): + // bank_index_load_local = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType) + // else: + // bank_index_load_local = XbarOutRdType(num_banks_per_cgra) + // # FIXME: change to exact tile id. + // s.rd_pkt[i] @= MemReadPktType(i, # src + // bank_index_load_local, # dst + // recv_raddr, # addr + // DataType(0, 0, 0, 0), # data + // s.cgra_id, # src_cgra + // 0, # src_tile + // i, # remote_src_port + // 0, # streaming_rd + // 0, # streaming_rd_stride + // 0) # streaming_rd_end_addr + // + // recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr + // # Calculates the target bank index. + // if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper): + // bank_index_load_from_noc = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType) + // else: + // bank_index_load_from_noc = XbarOutRdType(num_banks_per_cgra) + // s.rd_pkt[num_rd_tiles] @= MemReadPktType(num_rd_tiles, # src + // bank_index_load_from_noc, # dst + // recv_raddr_from_noc, # addr + // DataType(0, 0, 0, 0), # data + // s.recv_from_noc_load_request.msg.src, # src_cgra + // s.recv_from_noc_load_request.msg.src_tile_id, # src_tile + // s.recv_from_noc_load_request.msg.remote_src_port, # remote_src_port + // 0, # streaming_rd + // 0, # streaming_rd_stride + // 0) # streaming_rd_end_addr + // + // + // for i in range(num_wr_tiles): + // recv_waddr = s.recv_waddr[i].msg + // # Calculates the target bank index for store. + // if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper): + // bank_index_store_local = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType) + // else: + // bank_index_store_local = XbarOutWrType(num_banks_per_cgra) + // s.wr_pkt[i] @= MemWritePktType(i, # src + // bank_index_store_local, # dst + // recv_waddr, # addr + // s.recv_wdata[i].msg, # data + // 0, # src_cgra + // 0, # src_tile + // i, # remote_src_port + // 0, # streaming_rd + // 0, # streaming_rd_stride + // 0) # streaming_rd_end_addr + // + // + // recv_waddr_from_noc = s.recv_from_noc_store_request.msg.payload.data_addr + // recv_wdata_from_noc = s.recv_from_noc_store_request.msg.payload.data + // if (recv_waddr_from_noc >= s.address_lower) & (recv_waddr_from_noc <= s.address_upper): + // bank_index_store_from_noc = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType) + // else: + // bank_index_store_from_noc = XbarOutWrType(num_banks_per_cgra) + // s.wr_pkt[num_wr_tiles] @= MemWritePktType(num_wr_tiles, # src + // bank_index_store_from_noc, # dst + // recv_waddr_from_noc, # addr + // recv_wdata_from_noc, # data + // 0, # src_cgra + // 0, # src_tile + // num_wr_tiles, # remote_src_port + // 0, # streaming_rd + // 0, # streaming_rd_stride + // 0) # streaming_rd_end_addr + + always_comb begin : assemble_xbar_pkt + for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_assemble_xbar_pkt ); i += 1'd1 ) + rd_pkt[3'(i)] = { 3'(i), 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; + for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_wr_ports_at_assemble_xbar_pkt ); i += 1'd1 ) + wr_pkt[3'(i)] = { 3'(i), 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; + for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_assemble_xbar_pkt ); i += 1'd1 ) begin + __tmpvar__assemble_xbar_pkt_recv_raddr = recv_raddr__msg[3'(i)]; + if ( ( __tmpvar__assemble_xbar_pkt_recv_raddr >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_raddr <= address_upper ) ) begin + __tmpvar__assemble_xbar_pkt_bank_index_load_local = 2'(( __tmpvar__assemble_xbar_pkt_recv_raddr - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); + end + else + __tmpvar__assemble_xbar_pkt_bank_index_load_local = 2'd2; + rd_pkt[3'(i)] = { 3'(i), __tmpvar__assemble_xbar_pkt_bank_index_load_local, __tmpvar__assemble_xbar_pkt_recv_raddr, { 64'd0, 1'd0, 1'd0, 1'd0 }, cgra_id, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; + end + __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc = recv_from_noc_load_request__msg.payload.data_addr; + if ( ( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc <= address_upper ) ) begin + __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc = 2'(( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); + end + else + __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc = 2'd2; + rd_pkt[3'( __const__num_rd_tiles_at_assemble_xbar_pkt )] = { 3'( __const__num_rd_tiles_at_assemble_xbar_pkt ), __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc, __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc, { 64'd0, 1'd0, 1'd0, 1'd0 }, recv_from_noc_load_request__msg.src, recv_from_noc_load_request__msg.src_tile_id, recv_from_noc_load_request__msg.remote_src_port, 1'd0, 7'd0, 7'd0 }; + for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ); i += 1'd1 ) begin + __tmpvar__assemble_xbar_pkt_recv_waddr = recv_waddr__msg[3'(i)]; + if ( ( __tmpvar__assemble_xbar_pkt_recv_waddr >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_waddr <= address_upper ) ) begin + __tmpvar__assemble_xbar_pkt_bank_index_store_local = 2'(( __tmpvar__assemble_xbar_pkt_recv_waddr - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); + end + else + __tmpvar__assemble_xbar_pkt_bank_index_store_local = 2'd2; + wr_pkt[3'(i)] = { 3'(i), __tmpvar__assemble_xbar_pkt_bank_index_store_local, __tmpvar__assemble_xbar_pkt_recv_waddr, recv_wdata__msg[3'(i)], 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; + end + __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc = recv_from_noc_store_request__msg.payload.data_addr; + __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc = recv_from_noc_store_request__msg.payload.data; + if ( ( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc <= address_upper ) ) begin + __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc = 2'(( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); + end + else + __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc = 2'd2; + wr_pkt[3'( __const__num_wr_tiles_at_assemble_xbar_pkt )] = { 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ), __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc, __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc, __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc, 2'd0, 5'd0, 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ), 1'd0, 7'd0, 7'd0 }; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py:242 + // @update + // def update_all(): + // # Initializes the signals. + // for i in range(num_rd_tiles): + // s.recv_raddr[i].rdy @= 0 + // s.recv_from_noc_load_request.rdy @= 0 + // + // for i in range(num_wr_tiles): + // s.recv_waddr[i].rdy @= 0 + // # s.recv_wdata_bypass_q[i].send.rdy @= 0 + // s.recv_from_noc_store_request.rdy @= 0 + // # s.recv_wdata_bypass_q[num_wr_tiles].send.rdy @= 0 + // + // for i in range(num_rd_tiles): + // s.send_rdata[i].val @= 0 + // s.send_rdata[i].msg @= DataType() + // s.send_to_noc_load_response_pkt.val @= 0 + // + // s.send_to_noc_load_response_pkt.msg @= \ + // NocPktType(0, # src + // 0, # dst + // 0, # src_x + // 0, # src_y + // 0, # dst_x + // 0, # dst_y + // 0, # src_tile_id + // 0, # dst_tile_id + // 0, # remote_src_port + // 0, # opaque + // 0, # vc_id + // CgraPayloadType(0, 0, 0, 0, 0)) + // + // + // for i in range(num_wr_tiles): + // s.recv_wdata[i].rdy @= 0 + // + // s.send_to_noc_store_pkt.msg @= \ + // NocPktType(0, # src + // 0, # dst + // 0, # src_x + // 0, # src_y + // 0, # dst_x + // 0, # dst_y + // 0, # src_tile_id + // 0, # dst_tile_id + // 0, # remote_src_port + // 0, # opaque + // 0, # vc_id + // CgraPayloadType(0, 0, 0, 0, 0)) + // + // s.send_to_noc_store_pkt.val @= 0 + // + // for i in range(num_xbar_in_rd_ports): + // s.read_crossbar.recv[i].val @= 0 + // s.read_crossbar.recv[i].msg @= MemReadPktType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) + // + // s.recv_from_noc_load_response_pkt.rdy @= 0 + // + // for i in range(num_xbar_in_wr_ports): + // s.write_crossbar.recv[i].val @= 0 + // s.write_crossbar.recv[i].msg @= MemWritePktType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) + // + // s.send_to_noc_load_request_pkt.msg @= \ + // NocPktType(0, # src + // 0, # dst + // 0, # src_x + // 0, # src_y + // 0, # dst_x + // 0, # dst_y + // 0, # src_tile_id + // 0, # dst_tile_id + // 0, # remote_src_port + // 0, # opaque + // 0, # vc_id + // CgraPayloadType(0, 0, 0, 0, 0)) + // + // s.send_to_noc_load_request_pkt.val @= 0 + // + // # Connects the load request ports (from tiles and NoC) to the xbar targetting memory and NoC. + // for i in range(num_rd_tiles): + // s.read_crossbar.recv[i].val @= s.recv_raddr[i].val + // s.read_crossbar.recv[i].msg @= s.rd_pkt[i] + // s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy + // s.read_crossbar.recv[num_rd_tiles].val @= s.recv_from_noc_load_request.val + // s.read_crossbar.recv[num_rd_tiles].msg @= s.rd_pkt[num_rd_tiles] + // s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[num_rd_tiles].rdy + // + // # Connects the store request ports (from tiles and NoC) to the xbar targetting memory and NoC. + // for i in range(num_wr_tiles): + // s.write_crossbar.recv[i].val @= s.recv_waddr[i].val + // s.write_crossbar.recv[i].msg @= s.wr_pkt[i] + // s.recv_waddr[i].rdy @= s.write_crossbar.recv[i].rdy + // s.recv_wdata[i].rdy @= s.write_crossbar.recv[i].rdy + // s.write_crossbar.recv[num_wr_tiles].val @= s.recv_from_noc_store_request.val + // s.write_crossbar.recv[num_wr_tiles].msg @= s.wr_pkt[num_wr_tiles] + // s.recv_from_noc_store_request.rdy @= s.write_crossbar.recv[num_wr_tiles].rdy + // + // # Connects the response ports to tiles and NoC from the xbar. + // # Number of load responses is expected to be the same as the number of load requests. + // for i in range(num_xbar_in_rd_ports): + // if i < num_rd_tiles: + // s.send_rdata[RdTileIdType(i)].msg @= s.response_crossbar.send[i].msg.data + // s.send_rdata[RdTileIdType(i)].val @= s.response_crossbar.send[i].val + // s.response_crossbar.send[i].rdy @= s.send_rdata[RdTileIdType(i)].rdy + // else: + // from_cgra_id = s.response_crossbar.send[i].msg.src_cgra + // from_tile_id = s.response_crossbar.send[i].msg.src_tile + // s.send_to_noc_load_response_pkt.msg @= \ + // NocPktType( + // s.cgra_id, # src_cgra_id + // from_cgra_id, # dst_cgra_id + // s.idTo2d_x_lut[s.cgra_id], # src_cgra_x + // s.idTo2d_y_lut[s.cgra_id], # src_cgra_y + // s.idTo2d_x_lut[from_cgra_id], # dst_cgra_x + // s.idTo2d_y_lut[from_cgra_id], # dst_cgra_y + // 0, # src_tile_id set as 0 as it is from memory rather than a specific tile. + // from_tile_id, # dst_tile_id + // s.response_crossbar.send[i].msg.remote_src_port, # remote_src_port, carries the original source port id towards the src. + // 0, # opaque + // 0, # vc_id + // CgraPayloadType( + // CMD_LOAD_RESPONSE, + // s.response_crossbar.send[i].msg.data, + // s.response_crossbar.send[i].msg.addr, 0, 0)) + // + // s.send_to_noc_load_response_pkt.val @= s.response_crossbar.send[i].val + // s.response_crossbar.send[i].rdy @= s.send_to_noc_load_response_pkt.rdy + // + // # Handles the request (not response) towards the others via the NoC. The dst would be + // # updated in the controller. + // s.send_to_noc_load_request_pkt.msg @= \ + // NocPktType(s.cgra_id, # src + // 0, # dst + // s.idTo2d_x_lut[s.cgra_id], # src_x + // s.idTo2d_y_lut[s.cgra_id], # src_y + // 0, # dst_x + // 0, # dst_y + // 0, # src_tile_id + // 0, # dst_tile_id + // s.read_crossbar.send[num_banks_per_cgra].msg.src, # remote_src_port + // 0, # opaque + // 0, # vc_id + // CgraPayloadType( + // CMD_LOAD_REQUEST, + // 0, + // s.read_crossbar.send[num_banks_per_cgra].msg.addr, 0, 0)) + // + // s.send_to_noc_load_request_pkt.val @= s.read_crossbar.send[num_banks_per_cgra].val + // # TODO: https://github.com/tancheng/VectorCGRA/issues/26 -- Modify this part for non-blocking access. + // # 'val` indicates the data is arbitrated successfully. + // s.recv_from_noc_load_response_pkt.rdy @= s.response_crossbar.recv[num_banks_per_cgra].rdy + // s.response_crossbar.recv[num_banks_per_cgra].val @= s.recv_from_noc_load_response_pkt.val + // s.response_crossbar.recv[num_banks_per_cgra].msg @= \ + // MemResponsePktType(num_banks_per_cgra, + // s.recv_from_noc_load_response_pkt.msg.remote_src_port, + // s.recv_from_noc_load_response_pkt.msg.payload.data_addr, + // s.recv_from_noc_load_response_pkt.msg.payload.data, + // s.recv_from_noc_load_response_pkt.msg.src, + // s.recv_from_noc_load_response_pkt.msg.src_tile_id, + // 0, + // 0, # streaming_rd + // 0, # streaming_rd_stride + // 0) # streaming_rd_end_addr + // + // # Allows other load request towards NoC when the previous one is not responded. There + // # could be out-of-order load response, i.e., potential consistency issue. + // s.read_crossbar.send[num_banks_per_cgra].rdy @= s.send_to_noc_load_request_pkt.rdy + // + // # Handles the write port towards the NoC. + // s.send_to_noc_store_pkt.msg @= \ + // NocPktType(s.cgra_id, # src + // 0, # dst + // s.idTo2d_x_lut[s.cgra_id], # src_x + // s.idTo2d_y_lut[s.cgra_id], # src_y + // 0, # dst_x + // 0, # dst_y + // 0, # src_tile_id + // 0, # dst_tile_id + // s.write_crossbar.send[num_banks_per_cgra].msg.src, # remote_src_port + // 0, # opaque + // 0, # vc_id + // CgraPayloadType( + // CMD_STORE_REQUEST, + // s.write_crossbar.send[num_banks_per_cgra].msg.data, + // s.write_crossbar.send[num_banks_per_cgra].msg.addr, 0, 0)) + // + // s.send_to_noc_store_pkt.val @= s.write_crossbar.send[num_banks_per_cgra].val + // s.write_crossbar.send[num_banks_per_cgra].rdy @= s.send_to_noc_store_pkt.rdy + + always_comb begin : update_all + for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) + recv_raddr__rdy[3'(i)] = 1'd0; + recv_from_noc_load_request__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) + recv_waddr__rdy[3'(i)] = 1'd0; + recv_from_noc_store_request__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) begin + send_rdata__val[3'(i)] = 1'd0; + send_rdata__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + send_to_noc_load_response_pkt__val = 1'd0; + send_to_noc_load_response_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; + for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) + recv_wdata__rdy[3'(i)] = 1'd0; + send_to_noc_store_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; + send_to_noc_store_pkt__val = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_update_all ); i += 1'd1 ) begin + read_crossbar__recv__val[3'(i)] = 1'd0; + read_crossbar__recv__msg[3'(i)] = { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; + end + recv_from_noc_load_response_pkt__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_wr_ports_at_update_all ); i += 1'd1 ) begin + write_crossbar__recv__val[3'(i)] = 1'd0; + write_crossbar__recv__msg[3'(i)] = { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; + end + send_to_noc_load_request_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; + send_to_noc_load_request_pkt__val = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) begin + read_crossbar__recv__val[3'(i)] = recv_raddr__val[3'(i)]; + read_crossbar__recv__msg[3'(i)] = rd_pkt[3'(i)]; + recv_raddr__rdy[3'(i)] = read_crossbar__recv__rdy[3'(i)]; + end + read_crossbar__recv__val[3'( __const__num_rd_tiles_at_update_all )] = recv_from_noc_load_request__val; + read_crossbar__recv__msg[3'( __const__num_rd_tiles_at_update_all )] = rd_pkt[3'( __const__num_rd_tiles_at_update_all )]; + recv_from_noc_load_request__rdy = read_crossbar__recv__rdy[3'( __const__num_rd_tiles_at_update_all )]; + for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) begin + write_crossbar__recv__val[3'(i)] = recv_waddr__val[3'(i)]; + write_crossbar__recv__msg[3'(i)] = wr_pkt[3'(i)]; + recv_waddr__rdy[3'(i)] = write_crossbar__recv__rdy[3'(i)]; + recv_wdata__rdy[3'(i)] = write_crossbar__recv__rdy[3'(i)]; + end + write_crossbar__recv__val[3'( __const__num_wr_tiles_at_update_all )] = recv_from_noc_store_request__val; + write_crossbar__recv__msg[3'( __const__num_wr_tiles_at_update_all )] = wr_pkt[3'( __const__num_wr_tiles_at_update_all )]; + recv_from_noc_store_request__rdy = write_crossbar__recv__rdy[3'( __const__num_wr_tiles_at_update_all )]; + for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_update_all ); i += 1'd1 ) + if ( 3'(i) < 3'( __const__num_rd_tiles_at_update_all ) ) begin + send_rdata__msg[3'( 3'(i) )] = response_crossbar__send__msg[3'(i)].data; + send_rdata__val[3'( 3'(i) )] = response_crossbar__send__val[3'(i)]; + response_crossbar__send__rdy[3'(i)] = send_rdata__rdy[3'( 3'(i) )]; + end + else begin + __tmpvar__update_all_from_cgra_id = response_crossbar__send__msg[3'(i)].src_cgra; + __tmpvar__update_all_from_tile_id = response_crossbar__send__msg[3'(i)].src_tile; + send_to_noc_load_response_pkt__msg = { cgra_id, __tmpvar__update_all_from_cgra_id, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], idTo2d_x_lut[__tmpvar__update_all_from_cgra_id], idTo2d_y_lut[__tmpvar__update_all_from_cgra_id], 5'd0, __tmpvar__update_all_from_tile_id, response_crossbar__send__msg[3'(i)].remote_src_port, 8'd0, 2'd0, { 5'( __const__CMD_LOAD_RESPONSE ), response_crossbar__send__msg[3'(i)].data, response_crossbar__send__msg[3'(i)].addr, 107'd0, 4'd0 } }; + send_to_noc_load_response_pkt__val = response_crossbar__send__val[3'(i)]; + response_crossbar__send__rdy[3'(i)] = send_to_noc_load_response_pkt__rdy; + end + send_to_noc_load_request_pkt__msg = { cgra_id, 2'd0, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], 1'd0, 1'd0, 5'd0, 5'd0, read_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].src, 8'd0, 2'd0, { 5'( __const__CMD_LOAD_REQUEST ), 67'd0, read_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].addr, 107'd0, 4'd0 } }; + send_to_noc_load_request_pkt__val = read_crossbar__send__val[2'( __const__num_banks_per_cgra_at_update_all )]; + recv_from_noc_load_response_pkt__rdy = response_crossbar__recv__rdy[2'( __const__num_banks_per_cgra_at_update_all )]; + response_crossbar__recv__val[2'( __const__num_banks_per_cgra_at_update_all )] = recv_from_noc_load_response_pkt__val; + response_crossbar__recv__msg[2'( __const__num_banks_per_cgra_at_update_all )] = { 2'( __const__num_banks_per_cgra_at_update_all ), recv_from_noc_load_response_pkt__msg.remote_src_port, recv_from_noc_load_response_pkt__msg.payload.data_addr, recv_from_noc_load_response_pkt__msg.payload.data, recv_from_noc_load_response_pkt__msg.src, recv_from_noc_load_response_pkt__msg.src_tile_id, 3'd0, 1'd0, 7'd0, 7'd0 }; + read_crossbar__send__rdy[2'( __const__num_banks_per_cgra_at_update_all )] = send_to_noc_load_request_pkt__rdy; + send_to_noc_store_pkt__msg = { cgra_id, 2'd0, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], 1'd0, 1'd0, 5'd0, 5'd0, write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].src, 8'd0, 2'd0, { 5'( __const__CMD_STORE_REQUEST ), write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].data, write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].addr, 107'd0, 4'd0 } }; + send_to_noc_store_pkt__val = write_crossbar__send__val[2'( __const__num_banks_per_cgra_at_update_all )]; + write_crossbar__send__rdy[2'( __const__num_banks_per_cgra_at_update_all )] = send_to_noc_store_pkt__rdy; + end + + assign memory_wrapper__clk[0] = clk; + assign memory_wrapper__reset[0] = reset; + assign memory_wrapper__clk[1] = clk; + assign memory_wrapper__reset[1] = reset; + assign read_crossbar__clk = clk; + assign read_crossbar__reset = reset; + assign write_crossbar__clk = clk; + assign write_crossbar__reset = reset; + assign response_crossbar__clk = clk; + assign response_crossbar__reset = reset; + assign idTo2d_x_lut[0] = 1'd0; + assign idTo2d_y_lut[0] = 1'd0; + assign idTo2d_x_lut[1] = 1'd1; + assign idTo2d_y_lut[1] = 1'd0; + assign idTo2d_x_lut[2] = 1'd0; + assign idTo2d_y_lut[2] = 1'd1; + assign idTo2d_x_lut[3] = 1'd1; + assign idTo2d_y_lut[3] = 1'd1; + assign memory_wrapper__recv_rd__msg[0] = read_crossbar__send__msg[0]; + assign read_crossbar__send__rdy[0] = memory_wrapper__recv_rd__rdy[0]; + assign memory_wrapper__recv_rd__val[0] = read_crossbar__send__val[0]; + assign memory_wrapper__recv_wr__msg[0] = write_crossbar__send__msg[0]; + assign write_crossbar__send__rdy[0] = memory_wrapper__recv_wr__rdy[0]; + assign memory_wrapper__recv_wr__val[0] = write_crossbar__send__val[0]; + assign response_crossbar__recv__msg[0] = memory_wrapper__send__msg[0]; + assign memory_wrapper__send__rdy[0] = response_crossbar__recv__rdy[0]; + assign response_crossbar__recv__val[0] = memory_wrapper__send__val[0]; + assign memory_wrapper__recv_rd__msg[1] = read_crossbar__send__msg[1]; + assign read_crossbar__send__rdy[1] = memory_wrapper__recv_rd__rdy[1]; + assign memory_wrapper__recv_rd__val[1] = read_crossbar__send__val[1]; + assign memory_wrapper__recv_wr__msg[1] = write_crossbar__send__msg[1]; + assign write_crossbar__send__rdy[1] = memory_wrapper__recv_wr__rdy[1]; + assign memory_wrapper__recv_wr__val[1] = write_crossbar__send__val[1]; + assign response_crossbar__recv__msg[1] = memory_wrapper__send__msg[1]; + assign memory_wrapper__send__rdy[1] = response_crossbar__recv__rdy[1]; + assign response_crossbar__recv__val[1] = memory_wrapper__send__val[1]; + +endmodule + + +// PyMTL Component ConstQueueDynamicRTL Definition +// Full name: ConstQueueDynamicRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__const_mem_size_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py + +module ConstQueueDynamicRTL__9d3397f72f19af52 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] ctrl_proceed , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_const__msg , + input logic [0:0] send_const__rdy , + output logic [0:0] send_const__val +); + localparam logic [4:0] __const__const_mem_size_at_load_const = 5'd16; + localparam logic [4:0] __const__const_mem_size_at_update_wr_cur = 5'd16; + logic [3:0] rd_cur; + logic [4:0] wr_cur; + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__bd22936ec5812d0d reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [0:0] __tmpvar__load_const_not_full; + logic [0:0] __tmpvar__update_wr_cur_not_full; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:56 + // @update + // def load_const(): + // # Initializes signals. + // s.reg_file.waddr[0] @= AddrType() + // s.reg_file.wdata[0] @= DataType() + // s.reg_file.wen[0] @= 0 + // + // not_full = s.wr_cur < const_mem_size + // s.recv_const.rdy @= not_full + // + // if s.recv_const.val & not_full: + // s.reg_file.waddr[0] @= trunc(s.wr_cur, AddrType) + // s.reg_file.wdata[0] @= s.recv_const.msg + // s.reg_file.wen[0] @= 1 + + always_comb begin : load_const + reg_file__waddr[1'd0] = 4'd0; + reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__wen[1'd0] = 1'd0; + __tmpvar__load_const_not_full = wr_cur < 5'( __const__const_mem_size_at_load_const ); + recv_const__rdy = __tmpvar__load_const_not_full; + if ( recv_const__val & __tmpvar__load_const_not_full ) begin + reg_file__waddr[1'd0] = 4'(wr_cur); + reg_file__wdata[1'd0] = recv_const__msg; + reg_file__wen[1'd0] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:83 + // @update + // def update_send_val(): + // # Checks if read cursor is in front of write cursor. + // if (zext(s.rd_cur, WrCurType) < s.wr_cur): + // s.send_const.val @= 1 + // else: + // s.send_const.val @= 0 + + always_comb begin : update_send_val + if ( { { 1 { 1'b0 } }, rd_cur } < wr_cur ) begin + send_const__val = 1'd1; + end + else + send_const__val = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:92 + // @update_ff + // def update_rd_cur(): + // if s.reset | s.clear: + // s.rd_cur <<= 0 + // else: + // # Checks whether the "reader" successfully read the data at rd_cur, + // # and proceed rd_cur accordingly. + // if s.send_const.rdy & s.ctrl_proceed: + // if zext((s.rd_cur), WrCurType) < (s.wr_cur - 1): + // s.rd_cur <<= s.rd_cur + 1 + // else: + // s.rd_cur <<= 0 + + always_ff @(posedge clk) begin : update_rd_cur + if ( reset | clear ) begin + rd_cur <= 4'd0; + end + else if ( send_const__rdy & ctrl_proceed ) begin + if ( { { 1 { 1'b0 } }, rd_cur } < ( wr_cur - 5'd1 ) ) begin + rd_cur <= rd_cur + 4'd1; + end + else + rd_cur <= 4'd0; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:72 + // @update_ff + // def update_wr_cur(): + // not_full = (s.wr_cur < const_mem_size) + // if s.reset | s.clear: + // s.wr_cur <<= 0 + // # Checks if there's a valid const (from producer) to be written. + // else: + // if s.recv_const.val & not_full: + // s.wr_cur <<= s.wr_cur + 1 + + always_ff @(posedge clk) begin : update_wr_cur + __tmpvar__update_wr_cur_not_full = wr_cur < 5'( __const__const_mem_size_at_update_wr_cur ); + if ( reset | clear ) begin + wr_cur <= 5'd0; + end + else if ( recv_const__val & __tmpvar__update_wr_cur_not_full ) begin + wr_cur <= wr_cur + 5'd1; + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + assign send_const__msg = reg_file__rdata[0]; + assign reg_file__raddr[0] = rd_cur; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__736a0143e1873b49 +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__66f570731410737c +( + input logic [0:0] clk , + input logic [0:0] raddr , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_msg , + input logic [0:0] reset , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__736a0143e1873b49 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__66f570731410737c +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__raddr; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a dpath__recv_msg; + logic [0:0] dpath__reset; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__66f570731410737c dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__nregs_16__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__46d8b36a7a21259f +( + input logic [0:0] clk , + input logic [3:0] raddr [0:0], + output CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 rdata [0:0], + input logic [0:0] reset , + input logic [3:0] waddr [0:0], + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 regs [0:15]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component CtrlMemDynamicRTL Definition +// Full name: CtrlMemDynamicRTL__IntraCgraPktType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ctrl_mem_size_16__num_fu_inports_4__num_fu_outports_2__num_tile_inports_4__num_tile_outports_4__num_cgras_4__num_tiles_16__ctrl_count_per_iter_4__total_ctrl_steps_38 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py + +module CtrlMemDynamicRTL__427d547b7d58aa8e +( + input logic [1:0] cgra_id , + input logic [0:0] clk , + output logic [3:0] ctrl_addr_outport , + output logic [2:0] prologue_count_outport_fu , + output logic [2:0] prologue_count_outport_fu_crossbar [0:15][0:1], + output logic [2:0] prologue_count_outport_routing_crossbar [0:15][0:3], + input logic [0:0] reset , + input logic [4:0] tile_id , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element__msg , + output logic [0:0] recv_from_element__rdy , + input logic [0:0] recv_from_element__val , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller__msg , + output logic [0:0] recv_pkt_from_controller__rdy , + input logic [0:0] recv_pkt_from_controller__val , + output CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 send_ctrl__msg , + input logic [0:0] send_ctrl__rdy , + output logic [0:0] send_ctrl__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_pkt_to_controller__msg , + input logic [0:0] send_pkt_to_controller__rdy , + output logic [0:0] send_pkt_to_controller__val , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_element__msg , + input logic [0:0] send_to_element__rdy , + output logic [0:0] send_to_element__val +); + localparam logic [2:0] __const__num_fu_inports_at_update_msg = 3'd4; + localparam logic [3:0] __const__num_routing_outports_at_update_msg = 4'd8; + localparam logic [1:0] __const__CMD_CONFIG = 2'd3; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; + localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; + localparam logic [1:0] __const__CMD_TERMINATE = 2'd2; + localparam logic [0:0] __const__CMD_PAUSE = 1'd1; + localparam logic [4:0] __const__CMD_PRESERVE = 5'd22; + localparam logic [3:0] __const__CMD_RESUME = 4'd15; + localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; + localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; + localparam logic [3:0] __const__CMD_CONFIG_CTRL_LOWER_BOUND = 4'd9; + localparam logic [4:0] __const__CMD_RECORD_PHI_ADDR = 5'd16; + localparam logic [4:0] __const__num_tiles_at_update_send_pkt_to_controller = 5'd16; + localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [4:0] __const__ctrl_mem_size_at_update_raddr_and_fu_prologue = 5'd16; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_outport = 5'd16; + localparam logic [2:0] __const__num_tile_inports_at_update_prologue_outport = 3'd4; + localparam logic [1:0] __const__num_fu_outports_at_update_prologue_outport = 2'd2; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_reg = 5'd16; + localparam logic [2:0] __const__num_tile_inports_at_update_prologue_reg = 3'd4; + localparam logic [1:0] __const__num_fu_outports_at_update_prologue_reg = 2'd2; + localparam logic [2:0] __const__ctrl_count_per_iter_at_update_ctrl_count_per_iter = 3'd4; + localparam logic [5:0] __const__total_ctrl_steps_at_update_total_ctrl_steps = 6'd38; + logic [3:0] ctrl_count_lower_bound; + logic [2:0] ctrl_count_per_iter_val; + logic [4:0] ctrl_count_upper_bound; + logic [2:0] prologue_count_reg_fu [0:15]; + logic [2:0] prologue_count_reg_fu_crossbar [0:15][0:1]; + logic [2:0] prologue_count_reg_routing_crossbar [0:15][0:3]; + logic [0:0] sent_complete; + logic [0:0] start_iterate_ctrl; + logic [10:0] times; + logic [10:0] total_ctrl_steps_val; + //------------------------------------------------------------- + // Component recv_from_element_queue + //------------------------------------------------------------- + + logic [0:0] recv_from_element_queue__clk; + logic [1:0] recv_from_element_queue__count; + logic [0:0] recv_from_element_queue__reset; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element_queue__recv__msg; + logic [0:0] recv_from_element_queue__recv__rdy; + logic [0:0] recv_from_element_queue__recv__val; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element_queue__send__msg; + logic [0:0] recv_from_element_queue__send__rdy; + logic [0:0] recv_from_element_queue__send__val; + + NormalQueueRTL__66f570731410737c recv_from_element_queue + ( + .clk( recv_from_element_queue__clk ), + .count( recv_from_element_queue__count ), + .reset( recv_from_element_queue__reset ), + .recv__msg( recv_from_element_queue__recv__msg ), + .recv__rdy( recv_from_element_queue__recv__rdy ), + .recv__val( recv_from_element_queue__recv__val ), + .send__msg( recv_from_element_queue__send__msg ), + .send__rdy( recv_from_element_queue__send__rdy ), + .send__val( recv_from_element_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_from_element_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component recv_pkt_from_controller_queue + //------------------------------------------------------------- + + logic [0:0] recv_pkt_from_controller_queue__clk; + logic [1:0] recv_pkt_from_controller_queue__count; + logic [0:0] recv_pkt_from_controller_queue__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller_queue__recv__msg; + logic [0:0] recv_pkt_from_controller_queue__recv__rdy; + logic [0:0] recv_pkt_from_controller_queue__recv__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller_queue__send__msg; + logic [0:0] recv_pkt_from_controller_queue__send__rdy; + logic [0:0] recv_pkt_from_controller_queue__send__val; + + NormalQueueRTL__a1c7a5a18a302c36 recv_pkt_from_controller_queue + ( + .clk( recv_pkt_from_controller_queue__clk ), + .count( recv_pkt_from_controller_queue__count ), + .reset( recv_pkt_from_controller_queue__reset ), + .recv__msg( recv_pkt_from_controller_queue__recv__msg ), + .recv__rdy( recv_pkt_from_controller_queue__recv__rdy ), + .recv__val( recv_pkt_from_controller_queue__recv__val ), + .send__msg( recv_pkt_from_controller_queue__send__msg ), + .send__rdy( recv_pkt_from_controller_queue__send__rdy ), + .send__val( recv_pkt_from_controller_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_pkt_from_controller_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__46d8b36a7a21259f reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [2:0] __tmpvar__update_prologue_reg_temp_routing_crossbar_in; + logic [1:0] __tmpvar__update_prologue_reg_temp_fu_crossbar_in; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:157 + // @update + // def update_ctrl_addr_outport(): + // s.ctrl_addr_outport @= s.reg_file.raddr[0] + + always_comb begin : update_ctrl_addr_outport + ctrl_addr_outport = reg_file__raddr[1'd0]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:94 + // @update + // def update_msg(): + // s.recv_pkt_from_controller_queue.send.rdy @= 0 + // s.send_to_element.msg @= CgraPayloadType(0, 0, 0, 0, 0) + // s.send_to_element.val @= 0 + // s.reg_file.wen[0] @= 0 + // s.reg_file.waddr[0] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr + // # Initializes the fields of the control signal. + // s.reg_file.wdata[0].operation @= 0 + // for i in range(num_fu_inports): + // s.reg_file.wdata[0].fu_in[i] @= 0 + // s.reg_file.wdata[0].write_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_from[i] + // s.reg_file.wdata[0].write_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_idx[i] + // s.reg_file.wdata[0].read_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_from[i] + // s.reg_file.wdata[0].read_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_idx[i] + // for i in range(num_routing_outports): + // s.reg_file.wdata[0].routing_xbar_outport[i] @= 0 + // s.reg_file.wdata[0].fu_xbar_outport[i] @= 0 + // s.reg_file.wdata[0].vector_factor_power @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.vector_factor_power + // s.reg_file.wdata[0].is_last_ctrl @= 0 + // + // if s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG): + // s.reg_file.wen[0] @= 1 + // s.reg_file.waddr[0] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr + // # Fills the fields of the control signal. + // s.reg_file.wdata[0].operation @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.operation + // for i in range(num_fu_inports): + // s.reg_file.wdata[0].fu_in[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_in[i] + // s.reg_file.wdata[0].write_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_from[i] + // s.reg_file.wdata[0].write_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_idx[i] + // s.reg_file.wdata[0].read_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_from[i] + // s.reg_file.wdata[0].read_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_idx[i] + // for i in range(num_routing_outports): + // s.reg_file.wdata[0].routing_xbar_outport[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.routing_xbar_outport[i] + // s.reg_file.wdata[0].fu_xbar_outport[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_xbar_outport[i] + // s.reg_file.wdata[0].vector_factor_power @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.vector_factor_power + // s.reg_file.wdata[0].is_last_ctrl @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.is_last_ctrl + // elif s.recv_pkt_from_controller_queue.send.val & \ + // ((s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE)): + // s.send_to_element.msg @= s.recv_pkt_from_controller_queue.send.msg.payload + // s.send_to_element.val @= 1 + // + // if (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_PAUSE) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_PRESERVE) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RECORD_PHI_ADDR) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE): + // s.recv_pkt_from_controller_queue.send.rdy @= 1 + // # TODO: Extend for the other commands. Maybe another queue to + // # handle complicated actions. + // # else: + + always_comb begin : update_msg + recv_pkt_from_controller_queue__send__rdy = 1'd0; + send_to_element__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + send_to_element__val = 1'd0; + reg_file__wen[1'd0] = 1'd0; + reg_file__waddr[1'd0] = recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr; + reg_file__wdata[1'd0].operation = 7'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_fu_inports_at_update_msg ); i += 1'd1 ) begin + reg_file__wdata[1'd0].fu_in[2'(i)] = 3'd0; + reg_file__wdata[1'd0].write_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_from[2'(i)]; + reg_file__wdata[1'd0].write_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_idx[2'(i)]; + reg_file__wdata[1'd0].read_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_from[2'(i)]; + reg_file__wdata[1'd0].read_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_idx[2'(i)]; + end + for ( int unsigned i = 1'd0; i < 4'( __const__num_routing_outports_at_update_msg ); i += 1'd1 ) begin + reg_file__wdata[1'd0].routing_xbar_outport[3'(i)] = 3'd0; + reg_file__wdata[1'd0].fu_xbar_outport[3'(i)] = 2'd0; + end + reg_file__wdata[1'd0].vector_factor_power = recv_pkt_from_controller_queue__send__msg.payload.ctrl.vector_factor_power; + reg_file__wdata[1'd0].is_last_ctrl = 1'd0; + if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) ) begin + reg_file__wen[1'd0] = 1'd1; + reg_file__waddr[1'd0] = recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr; + reg_file__wdata[1'd0].operation = recv_pkt_from_controller_queue__send__msg.payload.ctrl.operation; + for ( int unsigned i = 1'd0; i < 3'( __const__num_fu_inports_at_update_msg ); i += 1'd1 ) begin + reg_file__wdata[1'd0].fu_in[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_in[2'(i)]; + reg_file__wdata[1'd0].write_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_from[2'(i)]; + reg_file__wdata[1'd0].write_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_idx[2'(i)]; + reg_file__wdata[1'd0].read_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_from[2'(i)]; + reg_file__wdata[1'd0].read_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_idx[2'(i)]; + end + for ( int unsigned i = 1'd0; i < 4'( __const__num_routing_outports_at_update_msg ); i += 1'd1 ) begin + reg_file__wdata[1'd0].routing_xbar_outport[3'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.routing_xbar_outport[3'(i)]; + reg_file__wdata[1'd0].fu_xbar_outport[3'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_xbar_outport[3'(i)]; + end + reg_file__wdata[1'd0].vector_factor_power = recv_pkt_from_controller_queue__send__msg.payload.ctrl.vector_factor_power; + reg_file__wdata[1'd0].is_last_ctrl = recv_pkt_from_controller_queue__send__msg.payload.ctrl.is_last_ctrl; + end + else if ( recv_pkt_from_controller_queue__send__val & ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) ) begin + send_to_element__msg = recv_pkt_from_controller_queue__send__msg.payload; + send_to_element__val = 1'd1; + end + if ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_PAUSE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_PRESERVE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RECORD_PHI_ADDR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) begin + recv_pkt_from_controller_queue__send__rdy = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:255 + // @update + // def update_prologue_outport(): + // s.prologue_count_outport_fu @= s.prologue_count_reg_fu[s.reg_file.raddr[0]] + // for addr in range(ctrl_mem_size): + // for i in range(num_tile_inports): + // s.prologue_count_outport_routing_crossbar[addr][i] @= \ + // s.prologue_count_reg_routing_crossbar[addr][i] + // for i in range(num_fu_outports): + // s.prologue_count_outport_fu_crossbar[addr][i] @= \ + // s.prologue_count_reg_fu_crossbar[addr][i] + + always_comb begin : update_prologue_outport + prologue_count_outport_fu = prologue_count_reg_fu[reg_file__raddr[1'd0]]; + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_outport ); addr += 1'd1 ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_tile_inports_at_update_prologue_outport ); i += 1'd1 ) + prologue_count_outport_routing_crossbar[4'(addr)][2'(i)] = prologue_count_reg_routing_crossbar[4'(addr)][2'(i)]; + for ( int unsigned i = 1'd0; i < 2'( __const__num_fu_outports_at_update_prologue_outport ); i += 1'd1 ) + prologue_count_outport_fu_crossbar[4'(addr)][1'(i)] = prologue_count_reg_fu_crossbar[4'(addr)][1'(i)]; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:181 + // @update + // def update_send_ctrl(): + // s.send_ctrl.val @= 0 + // if s.start_iterate_ctrl == b1(1): + // if s.sent_complete: + // s.send_ctrl.val @= 0 + // elif ((s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val)) | \ + // (s.reg_file.rdata[0].operation == OPT_START): + // s.send_ctrl.val @= b1(0) + // else: + // s.send_ctrl.val @= 1 + // if s.recv_pkt_from_controller_queue.send.val & \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE): + // s.send_ctrl.val @= b1(0) + + always_comb begin : update_send_ctrl + send_ctrl__val = 1'd0; + if ( start_iterate_ctrl == 1'd1 ) begin + if ( sent_complete ) begin + send_ctrl__val = 1'd0; + end + else if ( ( ( total_ctrl_steps_val > 11'd0 ) & ( times == total_ctrl_steps_val ) ) | ( reg_file__rdata[1'd0].operation == 7'( __const__OPT_START ) ) ) begin + send_ctrl__val = 1'd0; + end + else + send_ctrl__val = 1'd1; + end + if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) begin + send_ctrl__val = 1'd0; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:161 + // @update + // def update_send_pkt_to_controller(): + // s.send_pkt_to_controller.val @= 0 + // s.send_pkt_to_controller.msg @= IntraCgraPktType(0, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, CgraPayloadType(CMD_COMPLETE, 0, 0, 0, 0)) + // s.recv_from_element_queue.send.rdy @= 0 + // if s.start_iterate_ctrl == b1(1): + // if s.recv_from_element_queue.send.val & (~s.sent_complete): + // s.send_pkt_to_controller.msg @= \ + // IntraCgraPktType(s.tile_id, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, + // s.recv_from_element_queue.send.msg) + // s.send_pkt_to_controller.val @= 1 + // s.recv_from_element_queue.send.rdy @= s.send_pkt_to_controller.rdy + // elif ((s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val)) | \ + // (s.reg_file.rdata[0].operation == OPT_START): + // # Sends COMPLETE signal to Controller when the last ctrl signal is done. + // if ~s.sent_complete & (s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val) & s.start_iterate_ctrl: + // s.send_pkt_to_controller.msg @= \ + // IntraCgraPktType(s.tile_id, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, CgraPayloadType(CMD_COMPLETE, 0, 0, 0, 0)) + // s.send_pkt_to_controller.val @= 1 + + always_comb begin : update_send_pkt_to_controller + send_pkt_to_controller__val = 1'd0; + send_pkt_to_controller__msg = { 5'd0, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'( __const__CMD_COMPLETE ), 67'd0, 7'd0, 107'd0, 4'd0 } }; + recv_from_element_queue__send__rdy = 1'd0; + if ( start_iterate_ctrl == 1'd1 ) begin + if ( recv_from_element_queue__send__val & ( ~sent_complete ) ) begin + send_pkt_to_controller__msg = { tile_id, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, recv_from_element_queue__send__msg }; + send_pkt_to_controller__val = 1'd1; + recv_from_element_queue__send__rdy = send_pkt_to_controller__rdy; + end + else if ( ( ( total_ctrl_steps_val > 11'd0 ) & ( times == total_ctrl_steps_val ) ) | ( reg_file__rdata[1'd0].operation == 7'( __const__OPT_START ) ) ) begin + if ( ( ( ( ~sent_complete ) & ( total_ctrl_steps_val > 11'd0 ) ) & ( times == total_ctrl_steps_val ) ) & start_iterate_ctrl ) begin + send_pkt_to_controller__msg = { tile_id, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'( __const__CMD_COMPLETE ), 67'd0, 7'd0, 107'd0, 4'd0 } }; + send_pkt_to_controller__val = 1'd1; + end + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:298 + // @update + // def update_upper_bound(): + // s.ctrl_count_upper_bound @= zext(s.ctrl_count_lower_bound, UpperBoundType) + zext(s.ctrl_count_per_iter_val, UpperBoundType) + + always_comb begin : update_upper_bound + ctrl_count_upper_bound = { { 1 { 1'b0 } }, ctrl_count_lower_bound } + { { 2 { 1'b0 } }, ctrl_count_per_iter_val }; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:210 + // @update_ff + // def issue_complete(): + // if s.reset: + // s.sent_complete <<= 0 + // else: + // if s.send_pkt_to_controller.val & \ + // s.send_pkt_to_controller.rdy & \ + // (s.send_pkt_to_controller.msg.payload.cmd == CMD_COMPLETE): + // s.sent_complete <<= 1 + // elif s.recv_pkt_from_controller_queue.send.val & ( (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME) ): + // s.sent_complete <<= 0 + + always_ff @(posedge clk) begin : issue_complete + if ( reset ) begin + sent_complete <= 1'd0; + end + else if ( ( send_pkt_to_controller__val & send_pkt_to_controller__rdy ) & ( send_pkt_to_controller__msg.payload.cmd == 5'( __const__CMD_COMPLETE ) ) ) begin + sent_complete <= 1'd1; + end + else if ( recv_pkt_from_controller_queue__send__val & ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) ) begin + sent_complete <= 1'd0; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:284 + // @update_ff + // def update_ctrl_count_per_iter(): + // if s.reset: + // s.ctrl_count_per_iter_val <<= PCType(ctrl_count_per_iter) + // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER): + // s.ctrl_count_per_iter_val <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PCType) + + always_ff @(posedge clk) begin : update_ctrl_count_per_iter + if ( reset ) begin + ctrl_count_per_iter_val <= 3'd4; + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) begin + ctrl_count_per_iter_val <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:291 + // @update_ff + // def update_lower_bound(): + // if s.reset: + // s.ctrl_count_lower_bound <<= CtrlAddrType(0) + // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND): + // s.ctrl_count_lower_bound <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, CtrlAddrType) + + always_ff @(posedge clk) begin : update_lower_bound + if ( reset ) begin + ctrl_count_lower_bound <= 4'd0; + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) begin + ctrl_count_lower_bound <= 4'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:266 + // @update_ff + // def update_prologue_reg(): + // if s.reset: + // for addr in range(ctrl_mem_size): + // for i in range(num_tile_inports): + // s.prologue_count_reg_routing_crossbar[addr][i] <<= 0 + // for i in range(num_fu_outports): + // s.prologue_count_reg_fu_crossbar[addr][i] <<= 0 + // else: + // if s.recv_pkt_from_controller_queue.send.val & \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR): + // temp_routing_crossbar_in = s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.routing_xbar_outport[0] + // s.prologue_count_reg_routing_crossbar[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr][trunc(temp_routing_crossbar_in, TileInPortType)] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) + // elif s.recv_pkt_from_controller_queue.send.val & \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR): + // temp_fu_crossbar_in = s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_xbar_outport[0] + // s.prologue_count_reg_fu_crossbar[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr][trunc(temp_fu_crossbar_in, FuOutPortType)] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) + + always_ff @(posedge clk) begin : update_prologue_reg + if ( reset ) begin + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_reg ); addr += 1'd1 ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_tile_inports_at_update_prologue_reg ); i += 1'd1 ) + prologue_count_reg_routing_crossbar[4'(addr)][2'(i)] <= 3'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_fu_outports_at_update_prologue_reg ); i += 1'd1 ) + prologue_count_reg_fu_crossbar[4'(addr)][1'(i)] <= 3'd0; + end + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) begin + __tmpvar__update_prologue_reg_temp_routing_crossbar_in = recv_pkt_from_controller_queue__send__msg.payload.ctrl.routing_xbar_outport[3'd0]; + prologue_count_reg_routing_crossbar[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr][2'(__tmpvar__update_prologue_reg_temp_routing_crossbar_in)] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) begin + __tmpvar__update_prologue_reg_temp_fu_crossbar_in = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_xbar_outport[3'd0]; + prologue_count_reg_fu_crossbar[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr][1'(__tmpvar__update_prologue_reg_temp_fu_crossbar_in)] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:223 + // @update_ff + // def update_raddr_and_fu_prologue(): + // if s.reset: + // s.times <<= 0 + // s.reg_file.raddr[0] <<= 0 + // for i in range(ctrl_mem_size): + // s.prologue_count_reg_fu[i] <<= 0 + // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND): + // s.reg_file.raddr[0] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, CtrlAddrType) + // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE): + // s.times <<= TimeType(0) + // else: + // if s.recv_pkt_from_controller_queue.send.val & \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU): + // s.prologue_count_reg_fu[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr] <<= \ + // trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) + // + // if s.start_iterate_ctrl == b1(1): + // if ((s.total_ctrl_steps_val == 0) | \ + // (s.times < s.total_ctrl_steps_val)) & \ + // s.send_ctrl.rdy & s.send_ctrl.val: + // s.times <<= s.times + TimeType(1) + // + // # Reads the next ctrl signal only when the current one is done. + // if s.send_ctrl.rdy & s.send_ctrl.val: + // if zext(s.reg_file.raddr[0], UpperBoundType) == s.ctrl_count_upper_bound - UpperBoundType(1): + // s.reg_file.raddr[0] <<= s.ctrl_count_lower_bound + // else: + // s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + CtrlAddrType(1) + // if s.prologue_count_reg_fu[s.reg_file.raddr[0]] > 0: + // s.prologue_count_reg_fu[s.reg_file.raddr[0]] <<= s.prologue_count_reg_fu[s.reg_file.raddr[0]] - 1 + + always_ff @(posedge clk) begin : update_raddr_and_fu_prologue + if ( reset ) begin + times <= 11'd0; + reg_file__raddr[1'd0] <= 4'd0; + for ( int unsigned i = 1'd0; i < 5'( __const__ctrl_mem_size_at_update_raddr_and_fu_prologue ); i += 1'd1 ) + prologue_count_reg_fu[4'(i)] <= 3'd0; + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) begin + reg_file__raddr[1'd0] <= 4'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) begin + times <= 11'd0; + end + else begin + if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) begin + prologue_count_reg_fu[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + if ( start_iterate_ctrl == 1'd1 ) begin + if ( ( ( ( total_ctrl_steps_val == 11'd0 ) | ( times < total_ctrl_steps_val ) ) & send_ctrl__rdy ) & send_ctrl__val ) begin + times <= times + 11'd1; + end + if ( send_ctrl__rdy & send_ctrl__val ) begin + if ( { { 1 { 1'b0 } }, reg_file__raddr[1'd0] } == ( ctrl_count_upper_bound - 5'd1 ) ) begin + reg_file__raddr[1'd0] <= ctrl_count_lower_bound; + end + else + reg_file__raddr[1'd0] <= reg_file__raddr[1'd0] + 4'd1; + if ( prologue_count_reg_fu[reg_file__raddr[1'd0]] > 3'd0 ) begin + prologue_count_reg_fu[reg_file__raddr[1'd0]] <= prologue_count_reg_fu[reg_file__raddr[1'd0]] - 3'd1; + end + end + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:302 + // @update_ff + // def update_total_ctrl_steps(): + // if s.reset: + // s.total_ctrl_steps_val <<= TimeType(total_ctrl_steps) + // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT): + // s.total_ctrl_steps_val <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, TimeType) + + always_ff @(posedge clk) begin : update_total_ctrl_steps + if ( reset ) begin + total_ctrl_steps_val <= 11'd38; + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) begin + total_ctrl_steps_val <= 11'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:196 + // @update_ff + // def update_whether_we_can_iterate_ctrl(): + // if s.reset: + // s.start_iterate_ctrl <<= 0 + // else: + // if s.recv_pkt_from_controller_queue.send.val: + // if (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME): + // s.start_iterate_ctrl <<= 1 + // # TODO: issue #191, stop iterate ctrl after 10 cycels during pausing status, + // # so as to clear channels safely. + // elif s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE: + // s.start_iterate_ctrl <<= 0 + + always_ff @(posedge clk) begin : update_whether_we_can_iterate_ctrl + if ( reset ) begin + start_iterate_ctrl <= 1'd0; + end + else if ( recv_pkt_from_controller_queue__send__val ) begin + if ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) begin + start_iterate_ctrl <= 1'd1; + end + else if ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) begin + start_iterate_ctrl <= 1'd0; + end + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + assign recv_pkt_from_controller_queue__clk = clk; + assign recv_pkt_from_controller_queue__reset = reset; + assign recv_from_element_queue__clk = clk; + assign recv_from_element_queue__reset = reset; + assign send_ctrl__msg = reg_file__rdata[0]; + assign recv_pkt_from_controller_queue__recv__msg = recv_pkt_from_controller__msg; + assign recv_pkt_from_controller__rdy = recv_pkt_from_controller_queue__recv__rdy; + assign recv_pkt_from_controller_queue__recv__val = recv_pkt_from_controller__val; + assign recv_from_element_queue__recv__msg = recv_from_element__msg; + assign recv_from_element__rdy = recv_from_element_queue__recv__rdy; + assign recv_from_element_queue__recv__val = recv_from_element__val; + +endmodule + + +// PyMTL Component AdderRTL Definition +// Full name: AdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py + +module AdderRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_ADD = 7'd2; + localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; + localparam logic [6:0] __const__OPT_INC = 7'd3; + localparam logic [6:0] __const__OPT_SUB = 7'd4; + localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; + localparam logic [6:0] __const__OPT_PAS = 7'd31; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py:45 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // s.in0 @= 0 + // s.in1 @= 0 + // # For pick input register + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // # Though different operations might not need to consume + // # all the operands, as long as the opcode indicating it + // # is an operand, the data would disappear from the register. + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != 0: + // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) + // if s.recv_opt.msg.fu_in[1] != 0: + // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_ADD: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_ADD_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // s.recv_const.rdy @= s.send_out[0].rdy + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_INC: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.const_one.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_PAS: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_const__msg.payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; + recv_const__rdy = send_out__rdy[1'd0]; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + 64'd1; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_const__msg.payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component MulRTL Definition +// Full name: MulRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_32 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py + +module MulRTL__903abe7e5de73fa1 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_MUL = 7'd7; + localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py:44 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != 0: + // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) + // if s.recv_opt.msg.fu_in[1] != 0: + // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_MUL: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_MUL_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_const__msg.payload; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component AdderRTL Definition +// Full name: AdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_32 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py + +module AdderRTL__903abe7e5de73fa1 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_ADD = 7'd2; + localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; + localparam logic [6:0] __const__OPT_INC = 7'd3; + localparam logic [6:0] __const__OPT_SUB = 7'd4; + localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; + localparam logic [6:0] __const__OPT_PAS = 7'd31; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py:45 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // s.in0 @= 0 + // s.in1 @= 0 + // # For pick input register + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // # Though different operations might not need to consume + // # all the operands, as long as the opcode indicating it + // # is an operand, the data would disappear from the register. + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != 0: + // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) + // if s.recv_opt.msg.fu_in[1] != 0: + // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_ADD: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_ADD_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // s.recv_const.rdy @= s.send_out[0].rdy + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_INC: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.const_one.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_PAS: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_const__msg.payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; + recv_const__rdy = send_out__rdy[1'd0]; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + 64'd1; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_const__msg.payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component SeqMulAdderRTL Definition +// Full name: SeqMulAdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/double/SeqMulAdderRTL.py + +module SeqMulAdderRTL__b741248a3a1dca5f +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_MUL_ADD = 7'd18; + localparam logic [6:0] __const__OPT_MUL = 7'd7; + localparam logic [6:0] __const__OPT_ADD = 7'd2; + localparam logic [6:0] __const__OPT_MUL_CONST_ADD = 7'd30; + localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; + localparam logic [6:0] __const__OPT_PAS = 7'd31; + localparam logic [6:0] __const__OPT_MUL_SUB = 7'd19; + localparam logic [6:0] __const__OPT_SUB = 7'd4; + localparam logic [6:0] __const__OPT_START = 7'd0; + //------------------------------------------------------------- + // Component Fu0 + //------------------------------------------------------------- + + logic [0:0] Fu0__clear; + logic [0:0] Fu0__clk; + logic [0:0] Fu0__reset; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__from_mem_rdata__msg; + logic [0:0] Fu0__from_mem_rdata__rdy; + logic [0:0] Fu0__from_mem_rdata__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__recv_const__msg; + logic [0:0] Fu0__recv_const__rdy; + logic [0:0] Fu0__recv_const__val; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu0__recv_from_ctrl_mem__msg; + logic [0:0] Fu0__recv_from_ctrl_mem__rdy; + logic [0:0] Fu0__recv_from_ctrl_mem__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__recv_in__msg [0:3]; + logic [0:0] Fu0__recv_in__rdy [0:3]; + logic [0:0] Fu0__recv_in__val [0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu0__recv_opt__msg; + logic [0:0] Fu0__recv_opt__rdy; + logic [0:0] Fu0__recv_opt__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__send_out__msg [0:1]; + logic [0:0] Fu0__send_out__rdy [0:1]; + logic [0:0] Fu0__send_out__val [0:1]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu0__send_to_ctrl_mem__msg; + logic [0:0] Fu0__send_to_ctrl_mem__rdy; + logic [0:0] Fu0__send_to_ctrl_mem__val; + logic [6:0] Fu0__to_mem_raddr__msg; + logic [0:0] Fu0__to_mem_raddr__rdy; + logic [0:0] Fu0__to_mem_raddr__val; + logic [6:0] Fu0__to_mem_waddr__msg; + logic [0:0] Fu0__to_mem_waddr__rdy; + logic [0:0] Fu0__to_mem_waddr__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__to_mem_wdata__msg; + logic [0:0] Fu0__to_mem_wdata__rdy; + logic [0:0] Fu0__to_mem_wdata__val; + + MulRTL__903abe7e5de73fa1 Fu0 + ( + .clear( Fu0__clear ), + .clk( Fu0__clk ), + .reset( Fu0__reset ), + .from_mem_rdata__msg( Fu0__from_mem_rdata__msg ), + .from_mem_rdata__rdy( Fu0__from_mem_rdata__rdy ), + .from_mem_rdata__val( Fu0__from_mem_rdata__val ), + .recv_const__msg( Fu0__recv_const__msg ), + .recv_const__rdy( Fu0__recv_const__rdy ), + .recv_const__val( Fu0__recv_const__val ), + .recv_from_ctrl_mem__msg( Fu0__recv_from_ctrl_mem__msg ), + .recv_from_ctrl_mem__rdy( Fu0__recv_from_ctrl_mem__rdy ), + .recv_from_ctrl_mem__val( Fu0__recv_from_ctrl_mem__val ), + .recv_in__msg( Fu0__recv_in__msg ), + .recv_in__rdy( Fu0__recv_in__rdy ), + .recv_in__val( Fu0__recv_in__val ), + .recv_opt__msg( Fu0__recv_opt__msg ), + .recv_opt__rdy( Fu0__recv_opt__rdy ), + .recv_opt__val( Fu0__recv_opt__val ), + .send_out__msg( Fu0__send_out__msg ), + .send_out__rdy( Fu0__send_out__rdy ), + .send_out__val( Fu0__send_out__val ), + .send_to_ctrl_mem__msg( Fu0__send_to_ctrl_mem__msg ), + .send_to_ctrl_mem__rdy( Fu0__send_to_ctrl_mem__rdy ), + .send_to_ctrl_mem__val( Fu0__send_to_ctrl_mem__val ), + .to_mem_raddr__msg( Fu0__to_mem_raddr__msg ), + .to_mem_raddr__rdy( Fu0__to_mem_raddr__rdy ), + .to_mem_raddr__val( Fu0__to_mem_raddr__val ), + .to_mem_waddr__msg( Fu0__to_mem_waddr__msg ), + .to_mem_waddr__rdy( Fu0__to_mem_waddr__rdy ), + .to_mem_waddr__val( Fu0__to_mem_waddr__val ), + .to_mem_wdata__msg( Fu0__to_mem_wdata__msg ), + .to_mem_wdata__rdy( Fu0__to_mem_wdata__rdy ), + .to_mem_wdata__val( Fu0__to_mem_wdata__val ) + ); + + //------------------------------------------------------------- + // End of component Fu0 + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component Fu1 + //------------------------------------------------------------- + + logic [0:0] Fu1__clear; + logic [0:0] Fu1__clk; + logic [0:0] Fu1__reset; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__from_mem_rdata__msg; + logic [0:0] Fu1__from_mem_rdata__rdy; + logic [0:0] Fu1__from_mem_rdata__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__recv_const__msg; + logic [0:0] Fu1__recv_const__rdy; + logic [0:0] Fu1__recv_const__val; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu1__recv_from_ctrl_mem__msg; + logic [0:0] Fu1__recv_from_ctrl_mem__rdy; + logic [0:0] Fu1__recv_from_ctrl_mem__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__recv_in__msg [0:3]; + logic [0:0] Fu1__recv_in__rdy [0:3]; + logic [0:0] Fu1__recv_in__val [0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu1__recv_opt__msg; + logic [0:0] Fu1__recv_opt__rdy; + logic [0:0] Fu1__recv_opt__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__send_out__msg [0:1]; + logic [0:0] Fu1__send_out__rdy [0:1]; + logic [0:0] Fu1__send_out__val [0:1]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu1__send_to_ctrl_mem__msg; + logic [0:0] Fu1__send_to_ctrl_mem__rdy; + logic [0:0] Fu1__send_to_ctrl_mem__val; + logic [6:0] Fu1__to_mem_raddr__msg; + logic [0:0] Fu1__to_mem_raddr__rdy; + logic [0:0] Fu1__to_mem_raddr__val; + logic [6:0] Fu1__to_mem_waddr__msg; + logic [0:0] Fu1__to_mem_waddr__rdy; + logic [0:0] Fu1__to_mem_waddr__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__to_mem_wdata__msg; + logic [0:0] Fu1__to_mem_wdata__rdy; + logic [0:0] Fu1__to_mem_wdata__val; + + AdderRTL__903abe7e5de73fa1 Fu1 + ( + .clear( Fu1__clear ), + .clk( Fu1__clk ), + .reset( Fu1__reset ), + .from_mem_rdata__msg( Fu1__from_mem_rdata__msg ), + .from_mem_rdata__rdy( Fu1__from_mem_rdata__rdy ), + .from_mem_rdata__val( Fu1__from_mem_rdata__val ), + .recv_const__msg( Fu1__recv_const__msg ), + .recv_const__rdy( Fu1__recv_const__rdy ), + .recv_const__val( Fu1__recv_const__val ), + .recv_from_ctrl_mem__msg( Fu1__recv_from_ctrl_mem__msg ), + .recv_from_ctrl_mem__rdy( Fu1__recv_from_ctrl_mem__rdy ), + .recv_from_ctrl_mem__val( Fu1__recv_from_ctrl_mem__val ), + .recv_in__msg( Fu1__recv_in__msg ), + .recv_in__rdy( Fu1__recv_in__rdy ), + .recv_in__val( Fu1__recv_in__val ), + .recv_opt__msg( Fu1__recv_opt__msg ), + .recv_opt__rdy( Fu1__recv_opt__rdy ), + .recv_opt__val( Fu1__recv_opt__val ), + .send_out__msg( Fu1__send_out__msg ), + .send_out__rdy( Fu1__send_out__rdy ), + .send_out__val( Fu1__send_out__val ), + .send_to_ctrl_mem__msg( Fu1__send_to_ctrl_mem__msg ), + .send_to_ctrl_mem__rdy( Fu1__send_to_ctrl_mem__rdy ), + .send_to_ctrl_mem__val( Fu1__send_to_ctrl_mem__val ), + .to_mem_raddr__msg( Fu1__to_mem_raddr__msg ), + .to_mem_raddr__rdy( Fu1__to_mem_raddr__rdy ), + .to_mem_raddr__val( Fu1__to_mem_raddr__val ), + .to_mem_waddr__msg( Fu1__to_mem_waddr__msg ), + .to_mem_waddr__rdy( Fu1__to_mem_waddr__rdy ), + .to_mem_waddr__val( Fu1__to_mem_waddr__val ), + .to_mem_wdata__msg( Fu1__to_mem_wdata__msg ), + .to_mem_wdata__rdy( Fu1__to_mem_wdata__rdy ), + .to_mem_wdata__val( Fu1__to_mem_wdata__val ) + ); + + //------------------------------------------------------------- + // End of component Fu1 + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:90 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= AddrType(0) + // s.to_mem_raddr.msg @= AddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/double/SeqMulAdderRTL.py:32 + // @update + // def update_opt(): + // + // s.Fu0.recv_opt.msg @= s.recv_opt.msg + // s.Fu1.recv_opt.msg @= s.recv_opt.msg + // + // s.Fu0.recv_opt.msg.fu_in[0] @= 1 + // s.Fu0.recv_opt.msg.fu_in[1] @= 2 + // s.Fu1.recv_opt.msg.fu_in[0] @= 1 + // s.Fu1.recv_opt.msg.fu_in[1] @= 2 + // + // if s.recv_opt.msg.operation == OPT_MUL_ADD: + // s.Fu0.recv_opt.msg.operation @= OPT_MUL + // s.Fu1.recv_opt.msg.operation @= OPT_ADD + // elif s.recv_opt.msg.operation == OPT_MUL_CONST_ADD: + // s.Fu0.recv_opt.msg.operation @= OPT_MUL_CONST + // s.Fu1.recv_opt.msg.operation @= OPT_ADD + // elif s.recv_opt.msg.operation == OPT_MUL_CONST: + // s.Fu0.recv_opt.msg.operation @= OPT_MUL_CONST + // s.Fu1.recv_opt.msg.operation @= OPT_PAS + // elif s.recv_opt.msg.operation == OPT_MUL_SUB: + // s.Fu0.recv_opt.msg.operation @= OPT_MUL + // s.Fu1.recv_opt.msg.operation @= OPT_SUB + // else: + // # Indicates no computation should happen no this fused FU. + // # This is necessary to avoid the OPT_MUL_CONST be executed + // # by both Mul and MulAdder. + // s.Fu0.recv_opt.msg.operation @= OPT_START + // s.Fu1.recv_opt.msg.operation @= OPT_START + // + // # TODO: need to handle the other cases + + always_comb begin : update_opt + Fu0__recv_opt__msg = recv_opt__msg; + Fu1__recv_opt__msg = recv_opt__msg; + Fu0__recv_opt__msg.fu_in[2'd0] = 3'd1; + Fu0__recv_opt__msg.fu_in[2'd1] = 3'd2; + Fu1__recv_opt__msg.fu_in[2'd0] = 3'd1; + Fu1__recv_opt__msg.fu_in[2'd1] = 3'd2; + if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_ADD ) ) begin + Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL ); + Fu1__recv_opt__msg.operation = 7'( __const__OPT_ADD ); + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST_ADD ) ) begin + Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL_CONST ); + Fu1__recv_opt__msg.operation = 7'( __const__OPT_ADD ); + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin + Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL_CONST ); + Fu1__recv_opt__msg.operation = 7'( __const__OPT_PAS ); + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_SUB ) ) begin + Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL ); + Fu1__recv_opt__msg.operation = 7'( __const__OPT_SUB ); + end + else begin + Fu0__recv_opt__msg.operation = 7'( __const__OPT_START ); + Fu1__recv_opt__msg.operation = 7'( __const__OPT_START ); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:100 + // @update + // def update_send_to_controller(): + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + + always_comb begin : update_send_to_controller + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:68 + // @update + // def update_signal(): + // + // s.recv_in[0].rdy @= s.Fu0.recv_in[0].rdy + // s.recv_in[1].rdy @= s.Fu0.recv_in[1].rdy + // s.recv_in[2].rdy @= s.Fu1.recv_in[1].rdy + // + // s.Fu0.recv_in[0].val @= s.recv_in[0].val + // s.Fu0.recv_in[1].val @= s.recv_in[1].val + // s.Fu1.recv_in[0].val @= s.Fu0.send_out[0].val + // s.Fu1.recv_in[1].val @= s.recv_in[2].val + // + // s.Fu0.recv_opt.val @= s.recv_opt.val + // s.Fu1.recv_opt.val @= s.recv_opt.val + // + // s.recv_opt.rdy @= s.Fu0.recv_opt.rdy & s.Fu1.recv_opt.rdy + // + // s.send_out[0].val @= s.Fu1.send_out[0].val + // + // s.Fu0.send_out[0].rdy @= s.Fu1.recv_in[0].rdy + // s.Fu1.send_out[0].rdy @= s.send_out[0].rdy + + always_comb begin : update_signal + recv_in__rdy[2'd0] = Fu0__recv_in__rdy[2'd0]; + recv_in__rdy[2'd1] = Fu0__recv_in__rdy[2'd1]; + recv_in__rdy[2'd2] = Fu1__recv_in__rdy[2'd1]; + Fu0__recv_in__val[2'd0] = recv_in__val[2'd0]; + Fu0__recv_in__val[2'd1] = recv_in__val[2'd1]; + Fu1__recv_in__val[2'd0] = Fu0__send_out__val[1'd0]; + Fu1__recv_in__val[2'd1] = recv_in__val[2'd2]; + Fu0__recv_opt__val = recv_opt__val; + Fu1__recv_opt__val = recv_opt__val; + recv_opt__rdy = Fu0__recv_opt__rdy & Fu1__recv_opt__rdy; + send_out__val[1'd0] = Fu1__send_out__val[1'd0]; + Fu0__send_out__rdy[1'd0] = Fu1__recv_in__rdy[2'd0]; + Fu1__send_out__rdy[1'd0] = send_out__rdy[1'd0]; + end + + assign Fu0__clk = clk; + assign Fu0__reset = reset; + assign Fu1__clk = clk; + assign Fu1__reset = reset; + assign Fu0__recv_in__msg[0] = recv_in__msg[0]; + assign Fu0__recv_in__msg[1] = recv_in__msg[1]; + assign Fu1__recv_in__msg[1] = recv_in__msg[2]; + assign Fu1__recv_in__msg[0] = Fu0__send_out__msg[0]; + assign send_out__msg[0] = Fu1__send_out__msg[0]; + assign Fu0__recv_const__msg = recv_const__msg; + assign recv_const__rdy = Fu0__recv_const__rdy; + assign Fu0__recv_const__val = recv_const__val; + +endmodule + + +// PyMTL Component VectorMulRTL Definition +// Full name: VectorMulRTL__bw_16__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulRTL.py + +module VectorMulRTL__848c3e0c53bb478c +( + input logic [0:0] clk , + input logic [0:0] reset , + input logic [31:0] recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input logic [31:0] recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output logic [31:0] send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] +); + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_MUL = 7'd7; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] recv_all_val; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulRTL.py:55 + // @update + // def comb_logic(): + // s.recv_all_val @= 0 + // # Picks input register. + // s.in0 @= FuInType(0) + // s.in1 @= FuInType(0) + // + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range( num_outports ): + // s.send_out[i].val @= b1(0) + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_MUL: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg * s.recv_in[s.in1_idx].msg + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = 32'd0; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin + send_out__msg[1'd0] = recv_in__msg[in0_idx] * recv_in__msg[in1_idx]; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component VectorMulComboRTL Definition +// Full name: VectorMulComboRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py + +module VectorMulComboRTL__e2d25a29972e2033 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [1:0] __const__num_outports_at_update_input_output = 2'd2; + localparam logic [2:0] __const__num_lanes_at_update_input_output = 3'd4; + localparam logic [4:0] __const__sub_bw_at_update_input_output = 5'd16; + localparam logic [6:0] __const__OPT_VEC_MUL = 7'd55; + localparam logic [5:0] __const__sub_bw_2_at_update_input_output = 6'd32; + localparam logic [5:0] __const__sub_bw_3_at_update_input_output = 6'd48; + localparam logic [6:0] __const__sub_bw_4_at_update_input_output = 7'd64; + localparam logic [6:0] __const__data_bitwidth_at_update_input_output = 7'd64; + localparam logic [6:0] __const__OPT_VEC_MUL_COMBINED = 7'd75; + localparam logic [2:0] __const__num_lanes_at_update_signal = 3'd4; + localparam logic [1:0] __const__num_outports_at_update_signal = 2'd2; + localparam logic [2:0] __const__num_lanes_at_update_opt = 3'd4; + localparam logic [6:0] __const__OPT_NAH = 7'd1; + localparam logic [6:0] __const__OPT_MUL = 7'd7; + logic [63:0] temp_result [0:3]; + //------------------------------------------------------------- + // Component Fu[0:3] + //------------------------------------------------------------- + + logic [0:0] Fu__clk [0:3]; + logic [0:0] Fu__reset [0:3]; + logic [31:0] Fu__recv_const__msg [0:3]; + logic [0:0] Fu__recv_const__rdy [0:3]; + logic [0:0] Fu__recv_const__val [0:3]; + logic [31:0] Fu__recv_in__msg [0:3][0:3]; + logic [0:0] Fu__recv_in__rdy [0:3][0:3]; + logic [0:0] Fu__recv_in__val [0:3][0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu__recv_opt__msg [0:3]; + logic [0:0] Fu__recv_opt__rdy [0:3]; + logic [0:0] Fu__recv_opt__val [0:3]; + logic [31:0] Fu__send_out__msg [0:3][0:1]; + logic [0:0] Fu__send_out__rdy [0:3][0:1]; + logic [0:0] Fu__send_out__val [0:3][0:1]; + + VectorMulRTL__848c3e0c53bb478c Fu__0 + ( + .clk( Fu__clk[0] ), + .reset( Fu__reset[0] ), + .recv_const__msg( Fu__recv_const__msg[0] ), + .recv_const__rdy( Fu__recv_const__rdy[0] ), + .recv_const__val( Fu__recv_const__val[0] ), + .recv_in__msg( Fu__recv_in__msg[0] ), + .recv_in__rdy( Fu__recv_in__rdy[0] ), + .recv_in__val( Fu__recv_in__val[0] ), + .recv_opt__msg( Fu__recv_opt__msg[0] ), + .recv_opt__rdy( Fu__recv_opt__rdy[0] ), + .recv_opt__val( Fu__recv_opt__val[0] ), + .send_out__msg( Fu__send_out__msg[0] ), + .send_out__rdy( Fu__send_out__rdy[0] ), + .send_out__val( Fu__send_out__val[0] ) + ); + + VectorMulRTL__848c3e0c53bb478c Fu__1 + ( + .clk( Fu__clk[1] ), + .reset( Fu__reset[1] ), + .recv_const__msg( Fu__recv_const__msg[1] ), + .recv_const__rdy( Fu__recv_const__rdy[1] ), + .recv_const__val( Fu__recv_const__val[1] ), + .recv_in__msg( Fu__recv_in__msg[1] ), + .recv_in__rdy( Fu__recv_in__rdy[1] ), + .recv_in__val( Fu__recv_in__val[1] ), + .recv_opt__msg( Fu__recv_opt__msg[1] ), + .recv_opt__rdy( Fu__recv_opt__rdy[1] ), + .recv_opt__val( Fu__recv_opt__val[1] ), + .send_out__msg( Fu__send_out__msg[1] ), + .send_out__rdy( Fu__send_out__rdy[1] ), + .send_out__val( Fu__send_out__val[1] ) + ); + + VectorMulRTL__848c3e0c53bb478c Fu__2 + ( + .clk( Fu__clk[2] ), + .reset( Fu__reset[2] ), + .recv_const__msg( Fu__recv_const__msg[2] ), + .recv_const__rdy( Fu__recv_const__rdy[2] ), + .recv_const__val( Fu__recv_const__val[2] ), + .recv_in__msg( Fu__recv_in__msg[2] ), + .recv_in__rdy( Fu__recv_in__rdy[2] ), + .recv_in__val( Fu__recv_in__val[2] ), + .recv_opt__msg( Fu__recv_opt__msg[2] ), + .recv_opt__rdy( Fu__recv_opt__rdy[2] ), + .recv_opt__val( Fu__recv_opt__val[2] ), + .send_out__msg( Fu__send_out__msg[2] ), + .send_out__rdy( Fu__send_out__rdy[2] ), + .send_out__val( Fu__send_out__val[2] ) + ); + + VectorMulRTL__848c3e0c53bb478c Fu__3 + ( + .clk( Fu__clk[3] ), + .reset( Fu__reset[3] ), + .recv_const__msg( Fu__recv_const__msg[3] ), + .recv_const__rdy( Fu__recv_const__rdy[3] ), + .recv_const__val( Fu__recv_const__val[3] ), + .recv_in__msg( Fu__recv_in__msg[3] ), + .recv_in__rdy( Fu__recv_in__rdy[3] ), + .recv_in__val( Fu__recv_in__val[3] ), + .recv_opt__msg( Fu__recv_opt__msg[3] ), + .recv_opt__rdy( Fu__recv_opt__rdy[3] ), + .recv_opt__val( Fu__recv_opt__val[3] ), + .send_out__msg( Fu__send_out__msg[3] ), + .send_out__rdy( Fu__send_out__rdy[3] ), + .send_out__val( Fu__send_out__val[3] ) + ); + + //------------------------------------------------------------- + // End of component Fu[0:3] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:80 + // @update + // def update_input_output(): + // + // # Initialization to avoid latches + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // + // s.send_out[0].val @= s.Fu[0].send_out[0].val & \ + // s.recv_opt.val + // s.send_out[0].msg.payload @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // + // s.recv_from_ctrl_mem.rdy @= 0 + // + // for i in range(num_lanes): + // s.temp_result[i] @= TempDataType(0) + // s.Fu[i].recv_in[0].msg[0:sub_bw] @= FuDataType() + // s.Fu[i].recv_in[1].msg[0:sub_bw] @= FuDataType() + // + // if s.recv_opt.msg.operation == OPT_VEC_MUL: + // # Connection: split into vectorized FUs + // s.Fu[0].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] + // s.Fu[0].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] + // s.Fu[1].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] + // s.Fu[1].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] + // s.Fu[2].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw_2:sub_bw_3] + // s.Fu[2].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw_2:sub_bw_3] + // s.Fu[3].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw_3:sub_bw_4] + // s.Fu[3].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw_3:sub_bw_4] + // + // for i in range(num_lanes): + // s.temp_result[i] @= TempDataType(0) + // s.temp_result[i][0:sub_bw_2] @= s.Fu[i].send_out[0].msg[0:sub_bw_2] + // + // s.send_out[0].msg.payload[0:data_bitwidth] @= \ + // (s.temp_result[3] << (sub_bw * 3)) + \ + // (s.temp_result[2] << (sub_bw * 2)) + \ + // (s.temp_result[1] << sub_bw) + \ + // s.temp_result[0] + // + // elif s.recv_opt.msg.operation == OPT_VEC_MUL_COMBINED: # with highest precision + // s.Fu[0].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] + // s.Fu[0].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] + // s.Fu[1].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] + // s.Fu[1].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] + // s.Fu[2].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] + // s.Fu[2].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] + // s.Fu[3].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] + // s.Fu[3].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] + // + // for i in range(num_lanes): + // s.temp_result[i] @= TempDataType(0) + // s.temp_result[i][0:sub_bw_2] @= s.Fu[i].send_out[0].msg[0:sub_bw_2] + // + // s.send_out[0].msg.payload[0:data_bitwidth] @= \ + // s.temp_result[0] + \ + // (s.temp_result[1] << sub_bw) + \ + // (s.temp_result[2] << sub_bw) + \ + // (s.temp_result[3] << (sub_bw * 2)) + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + + always_comb begin : update_input_output + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_input_output ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + send_out__val[1'd0] = Fu__send_out__val[2'd0][1'd0] & recv_opt__val; + send_out__msg[1'd0].payload = 64'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin + temp_result[2'(i)] = 64'd0; + Fu__recv_in__msg[2'(i)][2'd0][5'd15:5'd0] = 16'd0; + Fu__recv_in__msg[2'(i)][2'd1][5'd15:5'd0] = 16'd0; + end + if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL ) ) begin + Fu__recv_in__msg[2'd0][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd0][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd1][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + Fu__recv_in__msg[2'd1][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + Fu__recv_in__msg[2'd2][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd47:6'( __const__sub_bw_2_at_update_input_output )]; + Fu__recv_in__msg[2'd2][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd47:6'( __const__sub_bw_2_at_update_input_output )]; + Fu__recv_in__msg[2'd3][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd63:6'( __const__sub_bw_3_at_update_input_output )]; + Fu__recv_in__msg[2'd3][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd63:6'( __const__sub_bw_3_at_update_input_output )]; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin + temp_result[2'(i)] = 64'd0; + temp_result[2'(i)][6'd31:6'd0] = Fu__send_out__msg[2'(i)][1'd0][5'd31:5'd0]; + end + send_out__msg[1'd0].payload[6'd63:6'd0] = ( ( ( temp_result[2'd3] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd3 ) ) + ( temp_result[2'd2] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd2 ) ) ) + ( temp_result[2'd1] << 5'( __const__sub_bw_at_update_input_output ) ) ) + temp_result[2'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL_COMBINED ) ) begin + Fu__recv_in__msg[2'd0][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd0][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd1][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd1][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + Fu__recv_in__msg[2'd2][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + Fu__recv_in__msg[2'd2][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd3][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + Fu__recv_in__msg[2'd3][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin + temp_result[2'(i)] = 64'd0; + temp_result[2'(i)][6'd31:6'd0] = Fu__send_out__msg[2'(i)][1'd0][5'd31:5'd0]; + end + send_out__msg[1'd0].payload[6'd63:6'd0] = ( ( temp_result[2'd0] + ( temp_result[2'd1] << 5'( __const__sub_bw_at_update_input_output ) ) ) + ( temp_result[2'd2] << 5'( __const__sub_bw_at_update_input_output ) ) ) + ( temp_result[2'd3] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd2 ) ); + end + else + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_input_output ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:183 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= AddrType(0) + // s.to_mem_raddr.msg @= AddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:168 + // @update + // def update_opt(): + // s.send_out[0].msg.predicate @= b1(0) + // + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.fu_in[0] @= 1 + // s.Fu[i].recv_opt.msg.fu_in[1] @= 2 + // s.Fu[i].recv_opt.msg.operation @= OPT_NAH + // + // if (s.recv_opt.msg.operation == OPT_VEC_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_MUL_COMBINED): + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.operation @= OPT_MUL + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate + + always_comb begin : update_opt + send_out__msg[1'd0].predicate = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].fu_in[2'd0] = 3'd1; + Fu__recv_opt__msg[2'(i)].fu_in[2'd1] = 3'd2; + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_NAH ); + end + if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL_COMBINED ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_MUL ); + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:146 + // @update + // def update_signal(): + // s.recv_in[0].rdy @= s.Fu[0].recv_in[0].rdy + // s.recv_in[1].rdy @= s.Fu[0].recv_in[1].rdy + // + // for i in range(num_lanes): + // s.Fu[i].recv_opt.val @= s.recv_opt.val + // + // # Note that the predication for a combined FU should be identical/shareable, + // # which means the computation in different basic block cannot be combined. + // # s.Fu[i].recv_opt.msg.predicate = s.recv_opt.msg.predicate + // + // s.Fu[i].recv_in[0].val @= s.recv_in[0].val + // s.Fu[i].recv_in[1].val @= s.recv_in[1].val + // s.Fu[i].recv_const.val @= s.recv_const.val + // + // for j in range(num_outports): + // s.Fu[i].send_out[j].rdy @= s.send_out[j].rdy + // + // s.recv_const.rdy @= s.Fu[0].recv_const.rdy + // s.recv_opt.rdy @= s.send_out[0].rdy + + always_comb begin : update_signal + recv_in__rdy[2'd0] = Fu__recv_in__rdy[2'd0][2'd0]; + recv_in__rdy[2'd1] = Fu__recv_in__rdy[2'd0][2'd1]; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_signal ); i += 1'd1 ) begin + Fu__recv_opt__val[2'(i)] = recv_opt__val; + Fu__recv_in__val[2'(i)][2'd0] = recv_in__val[2'd0]; + Fu__recv_in__val[2'(i)][2'd1] = recv_in__val[2'd1]; + Fu__recv_const__val[2'(i)] = recv_const__val; + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_signal ); j += 1'd1 ) + Fu__send_out__rdy[2'(i)][1'(j)] = send_out__rdy[1'(j)]; + end + recv_const__rdy = Fu__recv_const__rdy[2'd0]; + recv_opt__rdy = send_out__rdy[1'd0]; + end + + assign Fu__clk[0] = clk; + assign Fu__reset[0] = reset; + assign Fu__clk[1] = clk; + assign Fu__reset[1] = reset; + assign Fu__clk[2] = clk; + assign Fu__reset[2] = reset; + assign Fu__clk[3] = clk; + assign Fu__reset[3] = reset; + +endmodule + + +// PyMTL Component VectorAdderRTL Definition +// Full name: VectorAdderRTL__bw_16__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderRTL.py + +module VectorAdderRTL__848c3e0c53bb478c +( + input logic [0:0] carry_in , + output logic [0:0] carry_out , + input logic [0:0] clk , + input logic [0:0] combine_adder , + input logic [0:0] reset , + input logic [16:0] recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input logic [16:0] recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output logic [16:0] send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] +); + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_ADD = 7'd2; + localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; + localparam logic [6:0] __const__OPT_INC = 7'd3; + localparam logic [6:0] __const__OPT_SUB = 7'd4; + localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; + localparam logic [6:0] __const__OPT_PAS = 7'd31; + localparam logic [4:0] __const__bw_at_comb_logic = 5'd16; + logic [16:0] carry_in_temp; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] recv_all_val; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderRTL.py:58 + // @update + // def comb_logic(): + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= b1(0) + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.carry_in_temp[0] @= s.carry_in & s.combine_adder + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_ADD: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.recv_in[s.in1_idx].msg + s.carry_in_temp + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_ADD_CONST: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.recv_const.msg + s.carry_in_temp + // s.recv_const.rdy @= s.send_out[0].rdy + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_INC: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.const_one + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - s.recv_in[s.in1_idx].msg - s.carry_in_temp + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB_CONST: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - s.recv_const.msg - s.carry_in_temp + // s.recv_const.rdy @= s.send_out[0].rdy + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_PAS: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + // + // s.carry_out @= s.send_out[0].msg[bw:bw+1] + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = 17'd0; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + carry_in_temp[5'd0] = carry_in & combine_adder; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin + send_out__msg[1'd0] = ( recv_in__msg[in0_idx] + recv_in__msg[in1_idx] ) + carry_in_temp; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin + send_out__msg[1'd0] = ( recv_in__msg[in0_idx] + recv_const__msg ) + carry_in_temp; + recv_const__rdy = send_out__rdy[1'd0]; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin + send_out__msg[1'd0] = recv_in__msg[in0_idx] + 17'd1; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin + send_out__msg[1'd0] = ( recv_in__msg[in0_idx] - recv_in__msg[in1_idx] ) - carry_in_temp; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin + send_out__msg[1'd0] = ( recv_in__msg[in0_idx] - recv_const__msg ) - carry_in_temp; + recv_const__rdy = send_out__rdy[1'd0]; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin + send_out__msg[1'd0] = recv_in__msg[in0_idx]; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + carry_out = send_out__msg[1'd0][5'd16:5'( __const__bw_at_comb_logic )]; + end + + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component VectorAdderComboRTL Definition +// Full name: VectorAdderComboRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py + +module VectorAdderComboRTL__e2d25a29972e2033 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [2:0] __const__num_lanes_at_update_signal = 3'd4; + localparam logic [1:0] __const__num_outports_at_update_signal = 2'd2; + localparam logic [1:0] __const__num_outports_at_update_opt = 2'd2; + localparam logic [2:0] __const__num_lanes_at_update_opt = 3'd4; + localparam logic [6:0] __const__OPT_NAH = 7'd1; + localparam logic [6:0] __const__OPT_VEC_ADD = 7'd51; + localparam logic [6:0] __const__OPT_VEC_ADD_COMBINED = 7'd71; + localparam logic [6:0] __const__OPT_ADD = 7'd2; + localparam logic [6:0] __const__OPT_VEC_SUB = 7'd53; + localparam logic [6:0] __const__OPT_VEC_SUB_COMBINED = 7'd73; + localparam logic [6:0] __const__OPT_SUB = 7'd4; + localparam logic [6:0] __const__OPT_VEC_ADD_CONST = 7'd52; + localparam logic [6:0] __const__OPT_VEC_ADD_CONST_COMBINED = 7'd72; + localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; + localparam logic [6:0] __const__OPT_VEC_SUB_CONST = 7'd54; + localparam logic [6:0] __const__OPT_VEC_SUB_CONST_COMBINED = 7'd74; + localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; + //------------------------------------------------------------- + // Component Fu[0:3] + //------------------------------------------------------------- + + logic [0:0] Fu__carry_in [0:3]; + logic [0:0] Fu__carry_out [0:3]; + logic [0:0] Fu__clk [0:3]; + logic [0:0] Fu__combine_adder [0:3]; + logic [0:0] Fu__reset [0:3]; + logic [16:0] Fu__recv_const__msg [0:3]; + logic [0:0] Fu__recv_const__rdy [0:3]; + logic [0:0] Fu__recv_const__val [0:3]; + logic [16:0] Fu__recv_in__msg [0:3][0:3]; + logic [0:0] Fu__recv_in__rdy [0:3][0:3]; + logic [0:0] Fu__recv_in__val [0:3][0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu__recv_opt__msg [0:3]; + logic [0:0] Fu__recv_opt__rdy [0:3]; + logic [0:0] Fu__recv_opt__val [0:3]; + logic [16:0] Fu__send_out__msg [0:3][0:1]; + logic [0:0] Fu__send_out__rdy [0:3][0:1]; + logic [0:0] Fu__send_out__val [0:3][0:1]; + + VectorAdderRTL__848c3e0c53bb478c Fu__0 + ( + .carry_in( Fu__carry_in[0] ), + .carry_out( Fu__carry_out[0] ), + .clk( Fu__clk[0] ), + .combine_adder( Fu__combine_adder[0] ), + .reset( Fu__reset[0] ), + .recv_const__msg( Fu__recv_const__msg[0] ), + .recv_const__rdy( Fu__recv_const__rdy[0] ), + .recv_const__val( Fu__recv_const__val[0] ), + .recv_in__msg( Fu__recv_in__msg[0] ), + .recv_in__rdy( Fu__recv_in__rdy[0] ), + .recv_in__val( Fu__recv_in__val[0] ), + .recv_opt__msg( Fu__recv_opt__msg[0] ), + .recv_opt__rdy( Fu__recv_opt__rdy[0] ), + .recv_opt__val( Fu__recv_opt__val[0] ), + .send_out__msg( Fu__send_out__msg[0] ), + .send_out__rdy( Fu__send_out__rdy[0] ), + .send_out__val( Fu__send_out__val[0] ) + ); + + VectorAdderRTL__848c3e0c53bb478c Fu__1 + ( + .carry_in( Fu__carry_in[1] ), + .carry_out( Fu__carry_out[1] ), + .clk( Fu__clk[1] ), + .combine_adder( Fu__combine_adder[1] ), + .reset( Fu__reset[1] ), + .recv_const__msg( Fu__recv_const__msg[1] ), + .recv_const__rdy( Fu__recv_const__rdy[1] ), + .recv_const__val( Fu__recv_const__val[1] ), + .recv_in__msg( Fu__recv_in__msg[1] ), + .recv_in__rdy( Fu__recv_in__rdy[1] ), + .recv_in__val( Fu__recv_in__val[1] ), + .recv_opt__msg( Fu__recv_opt__msg[1] ), + .recv_opt__rdy( Fu__recv_opt__rdy[1] ), + .recv_opt__val( Fu__recv_opt__val[1] ), + .send_out__msg( Fu__send_out__msg[1] ), + .send_out__rdy( Fu__send_out__rdy[1] ), + .send_out__val( Fu__send_out__val[1] ) + ); + + VectorAdderRTL__848c3e0c53bb478c Fu__2 + ( + .carry_in( Fu__carry_in[2] ), + .carry_out( Fu__carry_out[2] ), + .clk( Fu__clk[2] ), + .combine_adder( Fu__combine_adder[2] ), + .reset( Fu__reset[2] ), + .recv_const__msg( Fu__recv_const__msg[2] ), + .recv_const__rdy( Fu__recv_const__rdy[2] ), + .recv_const__val( Fu__recv_const__val[2] ), + .recv_in__msg( Fu__recv_in__msg[2] ), + .recv_in__rdy( Fu__recv_in__rdy[2] ), + .recv_in__val( Fu__recv_in__val[2] ), + .recv_opt__msg( Fu__recv_opt__msg[2] ), + .recv_opt__rdy( Fu__recv_opt__rdy[2] ), + .recv_opt__val( Fu__recv_opt__val[2] ), + .send_out__msg( Fu__send_out__msg[2] ), + .send_out__rdy( Fu__send_out__rdy[2] ), + .send_out__val( Fu__send_out__val[2] ) + ); + + VectorAdderRTL__848c3e0c53bb478c Fu__3 + ( + .carry_in( Fu__carry_in[3] ), + .carry_out( Fu__carry_out[3] ), + .clk( Fu__clk[3] ), + .combine_adder( Fu__combine_adder[3] ), + .reset( Fu__reset[3] ), + .recv_const__msg( Fu__recv_const__msg[3] ), + .recv_const__rdy( Fu__recv_const__rdy[3] ), + .recv_const__val( Fu__recv_const__val[3] ), + .recv_in__msg( Fu__recv_in__msg[3] ), + .recv_in__rdy( Fu__recv_in__rdy[3] ), + .recv_in__val( Fu__recv_in__val[3] ), + .recv_opt__msg( Fu__recv_opt__msg[3] ), + .recv_opt__rdy( Fu__recv_opt__rdy[3] ), + .recv_opt__val( Fu__recv_opt__val[3] ), + .send_out__msg( Fu__send_out__msg[3] ), + .send_out__rdy( Fu__send_out__rdy[3] ), + .send_out__val( Fu__send_out__val[3] ) + ); + + //------------------------------------------------------------- + // End of component Fu[0:3] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:158 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= AddrType(0) + // s.to_mem_raddr.msg @= AddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:108 + // @update + // def update_opt(): + // + // for j in range( num_outports ): + // s.send_out[j].val @= b1(0) + // s.send_out[j].msg.predicate @= b1(0) + // + // s.send_out[0].val @= s.Fu[0].send_out[0].val & \ + // s.recv_opt.val + // + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.fu_in[0] @= 1 + // s.Fu[i].recv_opt.msg.fu_in[1] @= 2 + // s.Fu[i].recv_opt.msg.operation @= OPT_NAH + // s.Fu[i].combine_adder @= 0 + // + // if ( s.recv_opt.msg.operation == OPT_VEC_ADD ) | \ + // ( s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED ): + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.operation @= OPT_ADD + // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED) + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate + // + // elif ( s.recv_opt.msg.operation == OPT_VEC_SUB ) | \ + // ( s.recv_opt.msg.operation == OPT_VEC_SUB_COMBINED ): + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.operation @= OPT_SUB + // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_SUB_COMBINED) + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate + // + // # elif ( s.recv_opt.msg.operation == OPT_VEC_ADD_CONST ) | \ + // # ( s.recv_opt.msg.operation == OPT_ADD_CONST ): + // elif (s.recv_opt.msg.operation == OPT_VEC_ADD_CONST) | \ + // (s.recv_opt.msg.operation == OPT_VEC_ADD_CONST_COMBINED): + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.operation @= OPT_ADD_CONST + // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED) + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate + // + // elif (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST ) | \ + // (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST_COMBINED ): + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.operation @= OPT_SUB_CONST + // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST_COMBINED) + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + + always_comb begin : update_opt + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_opt ); j += 1'd1 ) begin + send_out__val[1'(j)] = 1'd0; + send_out__msg[1'(j)].predicate = 1'd0; + end + send_out__val[1'd0] = Fu__send_out__val[2'd0][1'd0] & recv_opt__val; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].fu_in[2'd0] = 3'd1; + Fu__recv_opt__msg[2'(i)].fu_in[2'd1] = 3'd2; + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_NAH ); + Fu__combine_adder[2'(i)] = 1'd0; + end + if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_ADD ); + Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ); + end + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_COMBINED ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_SUB ); + Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_COMBINED ); + end + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_CONST_COMBINED ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_ADD_CONST ); + Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ); + end + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST_COMBINED ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_SUB_CONST ); + Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST_COMBINED ); + end + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; + end + else + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_opt ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:82 + // @update + // def update_signal(): + // s.recv_in[0].rdy @= s.Fu[0].recv_in[0].rdy + // s.recv_in[1].rdy @= s.Fu[0].recv_in[1].rdy + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // + // s.recv_from_ctrl_mem.rdy @= 0 + // + // for i in range(num_lanes): + // s.Fu[i].recv_opt.val @= s.recv_opt.val + // + // for j in range(num_outports): + // s.Fu[i].send_out[j].rdy @= s.send_out[j].rdy + // + // s.Fu[i].recv_in[0].val @= s.recv_in[0].val + // s.Fu[i].recv_in[1].val @= s.recv_in[1].val + // s.Fu[i].recv_const.val @= s.recv_const.val + // + // # Note that the predication for a combined FU should be identical/shareable, + // # which means the computation in different basic block cannot be combined. + // # s.Fu[i].recv_opt.msg.predicate = s.recv_opt.msg.predicate + // s.recv_const.rdy @= s.Fu[0].recv_const.rdy + // s.recv_opt.rdy @= s.Fu[0].recv_opt.rdy + + always_comb begin : update_signal + recv_in__rdy[2'd0] = Fu__recv_in__rdy[2'd0][2'd0]; + recv_in__rdy[2'd1] = Fu__recv_in__rdy[2'd0][2'd1]; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_signal ); i += 1'd1 ) begin + Fu__recv_opt__val[2'(i)] = recv_opt__val; + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_signal ); j += 1'd1 ) + Fu__send_out__rdy[2'(i)][1'(j)] = send_out__rdy[1'(j)]; + Fu__recv_in__val[2'(i)][2'd0] = recv_in__val[2'd0]; + Fu__recv_in__val[2'(i)][2'd1] = recv_in__val[2'd1]; + Fu__recv_const__val[2'(i)] = recv_const__val; + end + recv_const__rdy = Fu__recv_const__rdy[2'd0]; + recv_opt__rdy = Fu__recv_opt__rdy[2'd0]; + end + + assign Fu__clk[0] = clk; + assign Fu__reset[0] = reset; + assign Fu__clk[1] = clk; + assign Fu__reset[1] = reset; + assign Fu__clk[2] = clk; + assign Fu__reset[2] = reset; + assign Fu__clk[3] = clk; + assign Fu__reset[3] = reset; + assign Fu__carry_in[0] = 1'd0; + assign Fu__carry_in[1] = Fu__carry_out[0]; + assign Fu__carry_in[2] = Fu__carry_out[1]; + assign Fu__carry_in[3] = Fu__carry_out[2]; + assign Fu__recv_in__msg[0][0][15:0] = recv_in__msg[0].payload[15:0]; + assign Fu__recv_in__msg[0][1][15:0] = recv_in__msg[1].payload[15:0]; + assign Fu__recv_const__msg[0][15:0] = recv_const__msg.payload[15:0]; + assign send_out__msg[0].payload[15:0] = Fu__send_out__msg[0][0][15:0]; + assign Fu__recv_in__msg[1][0][15:0] = recv_in__msg[0].payload[31:16]; + assign Fu__recv_in__msg[1][1][15:0] = recv_in__msg[1].payload[31:16]; + assign Fu__recv_const__msg[1][15:0] = recv_const__msg.payload[31:16]; + assign send_out__msg[0].payload[31:16] = Fu__send_out__msg[1][0][15:0]; + assign Fu__recv_in__msg[2][0][15:0] = recv_in__msg[0].payload[47:32]; + assign Fu__recv_in__msg[2][1][15:0] = recv_in__msg[1].payload[47:32]; + assign Fu__recv_const__msg[2][15:0] = recv_const__msg.payload[47:32]; + assign send_out__msg[0].payload[47:32] = Fu__send_out__msg[2][0][15:0]; + assign Fu__recv_in__msg[3][0][15:0] = recv_in__msg[0].payload[63:48]; + assign Fu__recv_in__msg[3][1][15:0] = recv_in__msg[1].payload[63:48]; + assign Fu__recv_const__msg[3][15:0] = recv_const__msg.payload[63:48]; + assign send_out__msg[0].payload[63:48] = Fu__send_out__msg[3][0][15:0]; + +endmodule + + +// PyMTL Component SumUnit Definition +// At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py + +module SumUnit__DataType_Bits64__num_inputs_4 +( + input logic [0:0] clk , + input logic [63:0] in_ [0:3], + output logic [63:0] out , + input logic [0:0] reset +); + logic [63:0] partial_sum [0:3]; + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py:37 + // s.out //= lambda: s.partial_sum[s.num_inputs-1] + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_out + out = partial_sum[3'd4 - 3'd1]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py:31 + // @update + // def up_sum(): + // s.partial_sum[0] @= s.in_[0] + // for i in range( 1, s.num_inputs ): + // s.partial_sum[i] @= s.partial_sum[i-1] + s.in_[i] + + always_comb begin : up_sum + partial_sum[2'd0] = in_[2'd0]; + for ( int unsigned i = 1'd1; i < 3'd4; i += 1'd1 ) + partial_sum[2'(i)] = partial_sum[2'(i) - 2'd1] + in_[2'(i)]; + end + +endmodule + + +// PyMTL Component ReduceMulUnit Definition +// At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/ReduceMulUnit.py + +module ReduceMulUnit__DataType_Bits64__num_inputs_4 +( + input logic [0:0] clk , + input logic [63:0] in_ [0:3], + output logic [63:0] out , + input logic [0:0] reset +); + logic [63:0] partial_sum [0:3]; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/ReduceMulUnit.py:32 + // @update + // def up_sum(): + // s.partial_sum[0] @= s.in_[0] + // for i in range( 1, s.num_inputs ): + // s.partial_sum[i] @= s.partial_sum[i-1] * s.in_[i] + + always_comb begin : up_sum + partial_sum[2'd0] = in_[2'd0]; + for ( int unsigned i = 1'd1; i < 3'd4; i += 1'd1 ) + partial_sum[2'(i)] = partial_sum[2'(i) - 2'd1] * in_[2'(i)]; + end + + assign out = partial_sum[3]; + +endmodule + + +// PyMTL Component VectorAllReduceRTL Definition +// Full name: VectorAllReduceRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py + +module VectorAllReduceRTL__e2d25a29972e2033 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD = 7'd56; + localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_BASE = 7'd68; + localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_GLOBAL = 7'd76; + localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL = 7'd78; + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ = 1'd0; + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ = 1'd1; + localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ = 2'd2; + localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ = 2'd3; + localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL = 7'd57; + localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_BASE = 7'd69; + localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_GLOBAL = 7'd77; + localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL = 7'd79; + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ = 1'd0; + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ = 1'd1; + localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ = 2'd2; + localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ = 2'd3; + localparam logic [6:0] __const__data_bitwidth_at_update_result = 7'd64; + localparam logic [2:0] __const__num_inports_at_update_signal = 3'd4; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL = 5'd19; + logic [0:0] already_sent_to_controller; + logic [63:0] temp_result [0:3]; + //------------------------------------------------------------- + // Component reduce_add + //------------------------------------------------------------- + + logic [0:0] reduce_add__clk; + logic [63:0] reduce_add__in_ [0:3]; + logic [63:0] reduce_add__out; + logic [0:0] reduce_add__reset; + + SumUnit__DataType_Bits64__num_inputs_4 reduce_add + ( + .clk( reduce_add__clk ), + .in_( reduce_add__in_ ), + .out( reduce_add__out ), + .reset( reduce_add__reset ) + ); + + //------------------------------------------------------------- + // End of component reduce_add + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component reduce_mul + //------------------------------------------------------------- + + logic [0:0] reduce_mul__clk; + logic [63:0] reduce_mul__in_ [0:3]; + logic [63:0] reduce_mul__out; + logic [0:0] reduce_mul__reset; + + ReduceMulUnit__DataType_Bits64__num_inputs_4 reduce_mul + ( + .clk( reduce_mul__clk ), + .in_( reduce_mul__in_ ), + .out( reduce_mul__out ), + .reset( reduce_mul__reset ) + ); + + //------------------------------------------------------------- + // End of component reduce_mul + //------------------------------------------------------------- + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 + // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ + reduce_add__in_[2'd0] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 + // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ + reduce_add__in_[2'd1] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 + // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ + reduce_add__in_[2'd2] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 + // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ + reduce_add__in_[2'd3] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 + // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ + reduce_mul__in_[2'd0] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 + // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ + reduce_mul__in_[2'd1] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 + // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ + reduce_mul__in_[2'd2] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 + // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ + reduce_mul__in_[2'd3] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ )] : 64'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:233 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:194 + // @update + // def update_predicate(): + // s.send_out[0].msg.predicate @= 0 + // if ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL)): + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate + // elif ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)): + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & \ + // s.recv_in[1].msg.predicate + // elif ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)): + // s.send_out[0].msg.predicate @= s.recv_from_ctrl_mem.msg.data.predicate & \ + // s.recv_in[1].msg.predicate + + always_comb begin : update_predicate + send_out__msg[1'd0].predicate = 1'd0; + if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) begin + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) begin + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) begin + send_out__msg[1'd0].predicate = recv_from_ctrl_mem__msg.data.predicate & recv_in__msg[2'd1].predicate; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:94 + // @update + // def update_result(): + // # Connection: splits data into vectorized wires. + // s.send_out[0].msg.payload @= 0 + // + // if s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_add.out + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_add.out + s.recv_in[1].msg.payload + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_mul.out + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_mul.out * s.recv_in[1].msg.payload + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] + s.recv_in[1].msg.payload + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] * s.recv_in[1].msg.payload + + always_comb begin : update_result + send_out__msg[1'd0].payload = 64'd0; + if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_add__out; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_add__out + recv_in__msg[2'd1].payload; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_mul__out; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_mul__out * recv_in__msg[2'd1].payload; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0] + recv_in__msg[2'd1].payload; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0] * recv_in__msg[2'd1].payload; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:116 + // @update + // def update_signal(): + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // + // s.recv_from_ctrl_mem.rdy @= 0 + // + // s.recv_in[0].rdy @= (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)) & \ + // s.send_out[0].rdy) | \ + // (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ + // s.send_to_ctrl_mem.rdy) + // s.recv_opt.rdy @= s.send_out[0].rdy + // s.recv_in[1].rdy @= (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)) & \ + // s.send_out[0].rdy) | \ + // (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ + // s.send_to_ctrl_mem.rdy) + // s.send_out[0].val @= (s.recv_in[0].val & \ + // s.recv_opt.val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL))) | \ + // (s.recv_in[0].val & \ + // s.recv_in[1].val & \ + // s.recv_opt.val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE))) | \ + // (s.recv_opt.val & \ + // s.recv_from_ctrl_mem.val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL))) | \ + // (s.recv_opt.val & \ + // s.recv_from_ctrl_mem.val & \ + // s.recv_in[1].val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL))) + // + // if s.recv_opt.val & \ + // ~s.already_sent_to_controller & \ + // (s.recv_in[0].val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL))) | \ + // (s.recv_in[0].val & \ + // s.recv_in[1].val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL))): + // s.send_to_ctrl_mem.val @= 1 + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL): + // s.send_to_ctrl_mem.msg @= \ + // s.CgraPayloadType(CMD_GLOBAL_REDUCE_ADD, + // DataType(s.reduce_add.out, + // s.recv_in[0].msg.predicate, 0, 0), + // 0, + // s.recv_opt.msg, + // 0) + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL): + // s.send_to_ctrl_mem.msg @= \ + // s.CgraPayloadType(CMD_GLOBAL_REDUCE_MUL, + // DataType(s.reduce_add.out, + // s.recv_in[0].msg.predicate, 0, 0), + // 0, + // s.recv_opt.msg, + // 0) + // + // if s.recv_opt.val & s.already_sent_to_controller: + // s.recv_from_ctrl_mem.rdy @= 1 + + always_comb begin : update_signal + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + recv_in__rdy[2'd0] = ( ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) & send_out__rdy[1'd0] ) | ( ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) & send_to_ctrl_mem__rdy ); + recv_opt__rdy = send_out__rdy[1'd0]; + recv_in__rdy[2'd1] = ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) & send_out__rdy[1'd0] ) | ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) & send_to_ctrl_mem__rdy ); + send_out__val[1'd0] = ( ( ( ( recv_in__val[2'd0] & recv_opt__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) ) | ( ( ( recv_in__val[2'd0] & recv_in__val[2'd1] ) & recv_opt__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) ) ) | ( ( recv_opt__val & recv_from_ctrl_mem__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) ) ) | ( ( ( recv_opt__val & recv_from_ctrl_mem__val ) & recv_in__val[2'd1] ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ); + if ( ( ( recv_opt__val & ( ~already_sent_to_controller ) ) & ( recv_in__val[2'd0] & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) ) ) | ( ( recv_in__val[2'd0] & recv_in__val[2'd1] ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) ) begin + send_to_ctrl_mem__val = 1'd1; + if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) begin + send_to_ctrl_mem__msg = { 5'( __const__CMD_GLOBAL_REDUCE_ADD ), { reduce_add__out, recv_in__msg[2'd0].predicate, 1'd0, 1'd0 }, 7'd0, recv_opt__msg, 4'd0 }; + end + if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) begin + send_to_ctrl_mem__msg = { 5'( __const__CMD_GLOBAL_REDUCE_MUL ), { reduce_add__out, recv_in__msg[2'd0].predicate, 1'd0, 1'd0 }, 7'd0, recv_opt__msg, 4'd0 }; + end + end + if ( recv_opt__val & already_sent_to_controller ) begin + recv_from_ctrl_mem__rdy = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:209 + // @update_ff + // def update_already_sent_to_controller(): + // if s.reset: + // s.already_sent_to_controller <<= 0 + // else: + // if s.recv_opt.val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ + // ~s.already_sent_to_controller & \ + // s.send_to_ctrl_mem.val & \ + // s.send_to_ctrl_mem.rdy: + // s.already_sent_to_controller <<= 1 + // # Recovers already_sent_to_controller once the ctrl proceeds to the next one. + // elif s.recv_opt.val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ + // s.already_sent_to_controller & \ + // s.recv_opt.rdy: + // s.already_sent_to_controller <<= 0 + + always_ff @(posedge clk) begin : update_already_sent_to_controller + if ( reset ) begin + already_sent_to_controller <= 1'd0; + end + else if ( ( ( ( recv_opt__val & ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) & ( ~already_sent_to_controller ) ) & send_to_ctrl_mem__val ) & send_to_ctrl_mem__rdy ) begin + already_sent_to_controller <= 1'd1; + end + else if ( ( ( recv_opt__val & ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) & already_sent_to_controller ) & recv_opt__rdy ) begin + already_sent_to_controller <= 1'd0; + end + end + + assign reduce_add__clk = clk; + assign reduce_add__reset = reset; + assign reduce_mul__clk = clk; + assign reduce_mul__reset = reset; + assign temp_result[0][15:0] = recv_in__msg[0].payload[15:0]; + assign temp_result[1][15:0] = recv_in__msg[0].payload[31:16]; + assign temp_result[2][15:0] = recv_in__msg[0].payload[47:32]; + assign temp_result[3][15:0] = recv_in__msg[0].payload[63:48]; + +endmodule + + +// PyMTL Component NahRTL Definition +// Full name: NahRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/NahRTL.py + +module NahRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_NAH = 7'd1; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/NahRTL.py:28 + // @update + // def comb_logic(): + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // # For pick input register + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // + // for i in range( num_outports ): + // # s.send_out[i].val @= s.recv_opt.val + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val & (s.recv_opt.msg.operation == OPT_NAH): + // s.recv_opt.rdy @= 1 + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + + always_comb begin : comb_logic + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val & ( recv_opt__msg.operation == 7'( __const__OPT_NAH ) ) ) begin + recv_opt__rdy = 1'd1; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + +endmodule + + +// PyMTL Component MulRTL Definition +// Full name: MulRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py + +module MulRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_MUL = 7'd7; + localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py:44 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != 0: + // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) + // if s.recv_opt.msg.fu_in[1] != 0: + // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_MUL: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_MUL_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_const__msg.payload; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component LogicRTL Definition +// Full name: LogicRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/LogicRTL.py + +module LogicRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_OR = 7'd8; + localparam logic [6:0] __const__OPT_AND = 7'd10; + localparam logic [6:0] __const__OPT_BIT_NOT = 7'd43; + localparam logic [6:0] __const__OPT_NOT = 7'd11; + localparam logic [6:0] __const__OPT_XOR = 7'd9; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/LogicRTL.py:44 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range( num_outports ): + // s.send_out[i].val @= b1(0) + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_OR: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload | s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_AND: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload & s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_BIT_NOT: + // s.send_out[0].msg.payload @= ~ s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_NOT: + // if s.recv_in[s.in0_idx].msg.payload == 0: + // s.send_out[0].msg.payload @= 1 + // else: + // s.send_out[0].msg.payload @= 0 + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_XOR: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload ^ s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_OR ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload | recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_AND ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload & recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_BIT_NOT ) ) begin + send_out__msg[1'd0].payload = ~recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_NOT ) ) begin + if ( recv_in__msg[in0_idx].payload == 64'd0 ) begin + send_out__msg[1'd0].payload = 64'd1; + end + else + send_out__msg[1'd0].payload = 64'd0; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_XOR ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload ^ recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component ShifterRTL Definition +// Full name: ShifterRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/ShifterRTL.py + +module ShifterRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_LLS = 7'd5; + localparam logic [6:0] __const__OPT_LRS = 7'd6; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/ShifterRTL.py:44 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= FuInType(0) + // s.in1 @= FuInType(0) + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_LLS: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload << s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_LRS: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload >> s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_LLS ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload << recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_LRS ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload >> recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component PhiRTL Definition +// Full name: PhiRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py + +module PhiRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_PHI = 7'd17; + localparam logic [6:0] __const__OPT_PHI_START = 7'd84; + localparam logic [6:0] __const__OPT_PHI_CONST = 7'd32; + logic [0:0] first; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py:48 + // @update + // def comb_logic(): + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // # TODO: decision needs to be made. Adder could be in FU vector width. Or only effective once on the boundary. + // # if s.recv_opt.val: + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_PHI: + // if s.recv_in[s.in0_idx].msg.predicate == Bits1(1): + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // elif s.recv_in[s.in1_idx].msg.predicate == Bits1(1): + // s.send_out[0].msg.payload @= s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // else: # No predecessor is active. + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= 0 + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_PHI_START: + // if s.first: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // elif s.recv_in[s.in0_idx].msg.predicate == Bits1(1): + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // elif s.recv_in[s.in1_idx].msg.predicate == Bits1(1): + // s.send_out[0].msg.payload @= s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // else: # No predecessor is active. + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= 0 + // s.recv_all_val @= ((s.first & s.recv_in[s.in0_idx].val) | \ + // (~s.first & s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val)) + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= ~s.first & s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_PHI_CONST: + // if s.first: + // s.send_out[0].msg.payload @= s.recv_const.msg.payload + // else: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // + // s.recv_all_val @= ((s.first & s.recv_const.val) | \ + // (~s.first & s.recv_in[s.in0_idx].val)) + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // if s.first: + // s.send_out[0].msg.predicate @= s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // else: + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_PHI ) ) begin + if ( recv_in__msg[in0_idx].predicate == 1'd1 ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = reached_vector_factor; + end + else if ( recv_in__msg[in1_idx].predicate == 1'd1 ) begin + send_out__msg[1'd0].payload = recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = reached_vector_factor; + end + else begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = 1'd0; + end + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_PHI_START ) ) begin + if ( first ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = reached_vector_factor; + end + else if ( recv_in__msg[in0_idx].predicate == 1'd1 ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = reached_vector_factor; + end + else if ( recv_in__msg[in1_idx].predicate == 1'd1 ) begin + send_out__msg[1'd0].payload = recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = reached_vector_factor; + end + else begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = 1'd0; + end + recv_all_val = ( first & recv_in__val[in0_idx] ) | ( ( ( ~first ) & recv_in__val[in0_idx] ) & recv_in__val[in1_idx] ); + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = ( ( ~first ) & recv_all_val ) & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_PHI_CONST ) ) begin + if ( first ) begin + send_out__msg[1'd0].payload = recv_const__msg.payload; + end + else + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + recv_all_val = ( first & recv_const__val ) | ( ( ~first ) & recv_in__val[in0_idx] ); + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + if ( first ) begin + send_out__msg[1'd0].predicate = recv_const__msg.predicate & reached_vector_factor; + end + else + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py:141 + // @update_ff + // def br_start_once(): + // if s.reset | s.clear: + // s.first <<= b1(1) + // if ((s.recv_opt.msg.operation == OPT_PHI_CONST) | (s.recv_opt.msg.operation == OPT_PHI_START)) & s.reached_vector_factor: + // s.first <<= b1(0) + + always_ff @(posedge clk) begin : br_start_once + if ( reset | clear ) begin + first <= 1'd1; + end + if ( ( ( recv_opt__msg.operation == 7'( __const__OPT_PHI_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_PHI_START ) ) ) & reached_vector_factor ) begin + first <= 1'd0; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component CompRTL Definition +// Full name: CompRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/CompRTL.py + +module CompRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_one = { 64'd1, 1'd0, 1'd0, 1'd0 }; + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_read_reg = 3'd4; + localparam logic [1:0] __const__num_outports_at_read_reg = 2'd2; + localparam logic [6:0] __const__OPT_EQ = 7'd14; + localparam logic [6:0] __const__OPT_NE = 7'd45; + localparam logic [6:0] __const__OPT_EQ_CONST = 7'd33; + localparam logic [6:0] __const__OPT_NE_CONST = 7'd46; + localparam logic [6:0] __const__OPT_LT = 7'd60; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/CompRTL.py:48 + // @update + // def read_reg(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= FuInType(0) + // s.in1 @= FuInType(0) + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType( 0 ): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if (s.recv_opt.msg.operation == OPT_EQ) | (s.recv_opt.msg.operation == OPT_NE): + // if (s.recv_opt.msg.operation == OPT_EQ) & \ + // (s.recv_in[s.in0_idx].msg.payload == s.recv_in[s.in1_idx].msg.payload): + // s.send_out[0].msg @= s.const_one + // elif (s.recv_opt.msg.operation == OPT_NE) & \ + // (s.recv_in[s.in0_idx].msg.payload != s.recv_in[s.in1_idx].msg.payload): + // s.send_out[0].msg @= s.const_one + // else: + // s.send_out[0].msg @= s.const_zero + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif (s.recv_opt.msg.operation == OPT_EQ_CONST) | (s.recv_opt.msg.operation == OPT_NE_CONST): + // if (s.recv_opt.msg.operation == OPT_EQ_CONST) & \ + // (s.recv_in[s.in0_idx].msg.payload == s.recv_const.msg.payload): + // s.send_out[0].msg @= s.const_one + // elif (s.recv_opt.msg.operation == OPT_NE_CONST) & \ + // (s.recv_in[s.in0_idx].msg.payload != s.recv_const.msg.payload): + // s.send_out[0].msg @= s.const_one + // else: + // s.send_out[0].msg @= s.const_zero + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_LT: + // if s.recv_in[s.in0_idx].msg.payload < s.recv_in[s.in1_idx].msg.payload: + // s.send_out[0].msg @= s.const_one + // else: + // s.send_out[0].msg @= s.const_zero + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : read_reg + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_read_reg ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_read_reg ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_NE ) ) ) begin + if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ ) ) & ( recv_in__msg[in0_idx].payload == recv_in__msg[in1_idx].payload ) ) begin + send_out__msg[1'd0] = const_one; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_NE ) ) & ( recv_in__msg[in0_idx].payload != recv_in__msg[in1_idx].payload ) ) begin + send_out__msg[1'd0] = const_one; + end + else + send_out__msg[1'd0] = const_zero; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_NE_CONST ) ) ) begin + if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ_CONST ) ) & ( recv_in__msg[in0_idx].payload == recv_const__msg.payload ) ) begin + send_out__msg[1'd0] = const_one; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_NE_CONST ) ) & ( recv_in__msg[in0_idx].payload != recv_const__msg.payload ) ) begin + send_out__msg[1'd0] = const_one; + end + else + send_out__msg[1'd0] = const_zero; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_LT ) ) begin + if ( recv_in__msg[in0_idx].payload < recv_in__msg[in1_idx].payload ) begin + send_out__msg[1'd0] = const_one; + end + else + send_out__msg[1'd0] = const_zero; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_read_reg ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component GrantRTL Definition +// Full name: GrantRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py + +module GrantRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_GRT_PRED = 7'd16; + localparam logic [6:0] __const__OPT_GRT_ALWAYS = 7'd34; + localparam logic [6:0] __const__OPT_GRT_ONCE = 7'd47; + logic [0:0] already_grt_once; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py:46 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= b1(0) + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_GRT_PRED: + // # GRANT_PREDICATE is used to apply (`and` operation) predicate onto a value. + // # The second operand would be used/treated as the predicate condition that + // # is usually coming from a `cmp` operation. + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // # Only updates predicate if the condition is true. Note that we respect + // # condition's (operand_1's) both value and predicate. + // if s.recv_in[s.in1_idx].msg.payload != s.const_zero.payload: + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // elif s.recv_opt.msg.operation == OPT_GRT_ALWAYS: + // # GRANT_ALWAYS is used to apply `true` predicate onto a value regardless + // # its original predicate value. This is usually used for the constant declared + // # in the entry block of a function, and then being used as a bound variable + // # in some streaming loop. Note that if we fuse the constant and the grant_always, + // # we may not need this operation, as the constant is usually preloaded into the + // # ConstQueue with `true` predicate. + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + // # Always updates predicate as true. + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // elif s.recv_opt.msg.operation == OPT_GRT_ONCE: + // # GRANT_ONCE is used to apply `true` predicate onto a value only once. This + // # is usually used for the constant declared in the entry block of a function. + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + // # Only updates predicate as true for the first time. + // s.send_out[0].msg.predicate @= s.reached_vector_factor & ~s.already_grt_once + // + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range( num_outports ): + // s.send_out[j].val @= b1( 0 ) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_PRED ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + if ( recv_in__msg[in1_idx].payload != 64'd0 ) begin + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + end + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ALWAYS ) ) begin + send_out__msg[1'd0] = recv_in__msg[in0_idx]; + send_out__msg[1'd0].predicate = reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ONCE ) ) begin + send_out__msg[1'd0] = recv_in__msg[in0_idx]; + send_out__msg[1'd0].predicate = reached_vector_factor & ( ~already_grt_once ); + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py:123 + // @update_ff + // def record_grt_once(): + // if s.reset | s.clear: + // s.already_grt_once <<= 0 + // else: + // if ~s.already_grt_once & s.send_out[0].val & s.send_out[0].rdy & (s.recv_opt.msg.operation == OPT_GRT_ONCE): + // s.already_grt_once <<= 1 + // else: + // s.already_grt_once <<= s.already_grt_once + + always_ff @(posedge clk) begin : record_grt_once + if ( reset | clear ) begin + already_grt_once <= 1'd0; + end + else if ( ( ( ( ~already_grt_once ) & send_out__val[1'd0] ) & send_out__rdy[1'd0] ) & ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ONCE ) ) ) begin + already_grt_once <= 1'd1; + end + else + already_grt_once <= already_grt_once; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component MemUnitRTL Definition +// Full name: MemUnitRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py + +module MemUnitRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_LD = 7'd12; + localparam logic [6:0] __const__OPT_ADD_CONST_LD = 7'd81; + localparam logic [6:0] __const__OPT_LD_CONST = 7'd28; + localparam logic [6:0] __const__OPT_STR = 7'd13; + localparam logic [6:0] __const__OPT_STR_CONST = 7'd58; + logic [0:0] already_sent_raddr; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [3:0] recv_in_val_vector; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:81 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= FuInType(0) + // s.in1 @= FuInType(0) + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != 0: + // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) + // if s.recv_opt.msg.fu_in[1] != 0: + // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) + // + // s.to_mem_waddr.val @= 0 + // s.to_mem_waddr.msg @= AddrType() + // s.to_mem_wdata.val @= 0 + // s.to_mem_wdata.msg @= DataType() + // s.to_mem_raddr.val @= 0 + // s.to_mem_raddr.msg @= AddrType() + // s.from_mem_rdata.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_LD: + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_raddr.rdy + // s.to_mem_raddr.msg @= AddrType(s.recv_in[s.in0_idx].msg.payload[0:AddrType.nbits]) + // # Do not access memory by setting raddr.val=0 if the raddr has predicate=0. + // # Note that this only happends "once" when all the required inputs are arrived. + // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): + // s.to_mem_raddr.val @= 0 + // else: + // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr + // s.from_mem_rdata.rdy @= s.send_out[0].rdy + // # Although we do not access memory when raddr has predicate=0, + // # we still need to simulate that memory returns a fake data with predicate=0, + // # so that the consumer will not block due to the lack of data. + // # Then all initiated iterations can be normally drained. + // # Note that this only happends "after" all the required inputs are arrived. + // # Otherwise, the recv_opt's opcode would be consumed at the wrong timing. + // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): + // s.send_out[0].val @= s.recv_all_val + // s.send_out[0].msg.predicate @= 0 + // s.recv_opt.rdy @= s.send_out[0].rdy + // else: + // s.send_out[0].val @= s.from_mem_rdata.val + // s.send_out[0].msg @= s.from_mem_rdata.msg + // # Predicate of 0 is already handled and returned with fake data. So just + // # use the from_mem_rdata's predicate here. + // s.send_out[0].msg.predicate @= s.from_mem_rdata.msg.predicate & \ + // s.reached_vector_factor + // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val + // + // # ADD_CONST_LD indicates the address is added on a const, then perform load. + // elif s.recv_opt.msg.operation == OPT_ADD_CONST_LD: + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_raddr.rdy + // # It is okay to always set recv_const.rdy=1 here, because the const queue + // # would only proceed once the operation is done executing. + // s.recv_const.rdy @= 1 + // s.to_mem_raddr.msg @= AddrType(s.recv_in[s.in0_idx].msg.payload[0:AddrType.nbits] + + // s.recv_const.msg.payload[0:AddrType.nbits]) + // # Do not access memory by setting raddr.val=0 if the raddr has predicate=0. + // # Note that this only happends "once" when all the required inputs are arrived. + // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): + // s.to_mem_raddr.val @= 0 + // else: + // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr + // s.from_mem_rdata.rdy @= s.send_out[0].rdy + // # Although we do not access memory when raddr has predicate=0, + // # we still need to simulate that memory returns a fake data with predicate=0, + // # so that the consumer will not block due to the lack of data. + // # Then all initiated iterations can be normally drained. + // # Note that this only happends "after" all the required inputs are arrived. + // # Otherwise, the recv_opt's opcode would be consumed at the wrong timing. + // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): + // s.send_out[0].val @= s.recv_all_val + // s.send_out[0].msg.predicate @= 0 + // s.recv_opt.rdy @= s.send_out[0].rdy + // else: + // s.send_out[0].val @= s.from_mem_rdata.val + // s.send_out[0].msg @= s.from_mem_rdata.msg + // # Predicate of 0 is already handled and returned with fake data. So just + // # use the from_mem_rdata's predicate here. + // s.send_out[0].msg.predicate @= s.from_mem_rdata.msg.predicate & \ + // s.reached_vector_factor + // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val + // + // # LD_CONST indicates the address is a const. + // elif s.recv_opt.msg.operation == OPT_LD_CONST: + // s.recv_all_val @= s.recv_const.val + // # It is okay to always set recv_const.rdy=1 here, because the const queue + // # would only proceed once the operation is done executing. + // s.recv_const.rdy @= 1 + // s.to_mem_raddr.msg @= AddrType(s.recv_const.msg.payload[0:AddrType.nbits]) + // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr + // s.from_mem_rdata.rdy @= s.send_out[0].rdy + // s.send_out[0].val @= s.from_mem_rdata.val + // s.send_out[0].msg @= s.from_mem_rdata.msg + // s.send_out[0].msg.predicate @= s.recv_const.msg.predicate & \ + // s.from_mem_rdata.msg.predicate & \ + // s.reached_vector_factor + // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val + // + // elif s.recv_opt.msg.operation == OPT_STR: + // s.recv_all_val @= s.recv_in[s.in0_idx].val & \ + // s.recv_in[s.in1_idx].val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // s.to_mem_waddr.msg @= AddrType(s.recv_in[0].msg.payload[0:AddrType.nbits]) + // s.to_mem_waddr.val @= s.recv_all_val + // s.to_mem_wdata.msg @= s.recv_in[s.in1_idx].msg + // s.to_mem_wdata.msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.to_mem_wdata.val @= s.recv_all_val + // + // # `send_out` is meaningless for store operation. + // s.send_out[0].val @= b1(0) + // + // s.recv_opt.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // + // # STR_CONST indicates the address is a const. + // elif s.recv_opt.msg.operation == OPT_STR_CONST: + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.recv_const.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // # Only needs one input register to indicate the storing data. + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // s.to_mem_waddr.msg @= AddrType(s.recv_const.msg.payload[0:AddrType.nbits]) + // s.to_mem_waddr.val @= s.recv_all_val & \ + // s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate + // s.to_mem_wdata.msg @= s.recv_in[s.in0_idx].msg + // s.to_mem_wdata.msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // s.to_mem_wdata.val @= s.recv_all_val & \ + // s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate + // + // # `send_out` is meaningless for store operation. + // s.send_out[0].val @= b1(0) + // + // s.recv_opt.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + to_mem_waddr__val = 1'd0; + to_mem_waddr__msg = 7'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + to_mem_raddr__val = 1'd0; + to_mem_raddr__msg = 7'd0; + from_mem_rdata__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_LD ) ) begin + recv_all_val = recv_in__val[in0_idx]; + recv_in__rdy[in0_idx] = recv_all_val & to_mem_raddr__rdy; + to_mem_raddr__msg = 7'( recv_in__msg[in0_idx].payload[6'd6:6'd0] ); + if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin + to_mem_raddr__val = 1'd0; + end + else + to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); + from_mem_rdata__rdy = send_out__rdy[1'd0]; + if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin + send_out__val[1'd0] = recv_all_val; + send_out__msg[1'd0].predicate = 1'd0; + recv_opt__rdy = send_out__rdy[1'd0]; + end + else begin + send_out__val[1'd0] = from_mem_rdata__val; + send_out__msg[1'd0] = from_mem_rdata__msg; + send_out__msg[1'd0].predicate = from_mem_rdata__msg.predicate & reached_vector_factor; + recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; + end + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST_LD ) ) begin + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + recv_in__rdy[in0_idx] = recv_all_val & to_mem_raddr__rdy; + recv_const__rdy = 1'd1; + to_mem_raddr__msg = 7'( recv_in__msg[in0_idx].payload[6'd6:6'd0] + recv_const__msg.payload[6'd6:6'd0] ); + if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin + to_mem_raddr__val = 1'd0; + end + else + to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); + from_mem_rdata__rdy = send_out__rdy[1'd0]; + if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin + send_out__val[1'd0] = recv_all_val; + send_out__msg[1'd0].predicate = 1'd0; + recv_opt__rdy = send_out__rdy[1'd0]; + end + else begin + send_out__val[1'd0] = from_mem_rdata__val; + send_out__msg[1'd0] = from_mem_rdata__msg; + send_out__msg[1'd0].predicate = from_mem_rdata__msg.predicate & reached_vector_factor; + recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; + end + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_LD_CONST ) ) begin + recv_all_val = recv_const__val; + recv_const__rdy = 1'd1; + to_mem_raddr__msg = 7'( recv_const__msg.payload[6'd6:6'd0] ); + to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); + from_mem_rdata__rdy = send_out__rdy[1'd0]; + send_out__val[1'd0] = from_mem_rdata__val; + send_out__msg[1'd0] = from_mem_rdata__msg; + send_out__msg[1'd0].predicate = ( recv_const__msg.predicate & from_mem_rdata__msg.predicate ) & reached_vector_factor; + recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_STR ) ) begin + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + recv_in__rdy[in0_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + recv_in__rdy[in1_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + to_mem_waddr__msg = 7'( recv_in__msg[2'd0].payload[6'd6:6'd0] ); + to_mem_waddr__val = recv_all_val; + to_mem_wdata__msg = recv_in__msg[in1_idx]; + to_mem_wdata__msg.predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + to_mem_wdata__val = recv_all_val; + send_out__val[1'd0] = 1'd0; + recv_opt__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_STR_CONST ) ) begin + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + recv_const__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + recv_in__rdy[in0_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + to_mem_waddr__msg = 7'( recv_const__msg.payload[6'd6:6'd0] ); + to_mem_waddr__val = ( recv_all_val & recv_in__msg[in0_idx].predicate ) & recv_const__msg.predicate; + to_mem_wdata__msg = recv_in__msg[in0_idx]; + to_mem_wdata__msg.predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; + to_mem_wdata__val = ( recv_all_val & recv_in__msg[in0_idx].predicate ) & recv_const__msg.predicate; + send_out__val[1'd0] = 1'd0; + recv_opt__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:245 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:269 + // @update_ff + // def update_already_sent_raddr(): + // if s.reset: + // s.already_sent_raddr <<= 0 + // else: + // if ~s.recv_opt.val: + // s.already_sent_raddr <<= 0 + // elif s.from_mem_rdata.val & s.from_mem_rdata.rdy: + // # Clears the flag when the data has returned (s.from_mem_rdata.val) + // # and successfully delivered to the destination (s.from_mem_rdata.rdy). + // s.already_sent_raddr <<= 0 + // elif s.to_mem_raddr.val & \ + // s.to_mem_raddr.rdy & \ + // ~s.already_sent_raddr: + // s.already_sent_raddr <<= 1 + // else: + // s.already_sent_raddr <<= s.already_sent_raddr + + always_ff @(posedge clk) begin : update_already_sent_raddr + if ( reset ) begin + already_sent_raddr <= 1'd0; + end + else if ( ~recv_opt__val ) begin + already_sent_raddr <= 1'd0; + end + else if ( from_mem_rdata__val & from_mem_rdata__rdy ) begin + already_sent_raddr <= 1'd0; + end + else if ( ( to_mem_raddr__val & to_mem_raddr__rdy ) & ( ~already_sent_raddr ) ) begin + already_sent_raddr <= 1'd1; + end + else + already_sent_raddr <= already_sent_raddr; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:253 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + assign vector_factor_power = 3'd0; + +endmodule + + +// PyMTL Component SelRTL Definition +// Full name: SelRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py + +module SelRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_SEL = 7'd27; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [2:0] in2; + logic [1:0] in2_idx; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:88 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register, Selector needs at least 3 inputs + // s.in0 @= FuInType(0) + // s.in1 @= FuInType(0) + // s.in2 @= FuInType(0) + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= s.send_out[0].rdy + // + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // if s.recv_opt.msg.fu_in[2] != FuInType(0): + // s.in2 @= s.recv_opt.msg.fu_in[2] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_SEL: + // if s.recv_in[s.in0_idx].msg.payload == s.true.payload: + // s.send_out[0].msg @= s.recv_in[s.in1_idx].msg + // else: + // s.send_out[0].msg @= s.recv_in[s.in2_idx].msg + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.recv_in[s.in2_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & \ + // s.recv_in[s.in1_idx].val & \ + // s.recv_in[s.in2_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in2_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + // s.recv_in[s.in2_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + in2 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + recv_const__rdy = 1'd0; + recv_opt__rdy = send_out__rdy[1'd0]; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd2] != 3'd0 ) begin + in2 = recv_opt__msg.fu_in[2'd2] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_SEL ) ) begin + if ( recv_in__msg[in0_idx].payload == 64'd1 ) begin + send_out__msg[1'd0] = recv_in__msg[in1_idx]; + end + else + send_out__msg[1'd0] = recv_in__msg[in2_idx]; + send_out__msg[1'd0].predicate = ( ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & recv_in__msg[in2_idx].predicate ) & reached_vector_factor; + recv_all_val = ( recv_in__val[in0_idx] & recv_in__val[in1_idx] ) & recv_in__val[in2_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in2_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + recv_in__rdy[in2_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:78 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= AddrType(0) + // s.to_mem_raddr.msg @= AddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:144 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:152 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + assign in2_idx = in2[1:0]; + assign vector_factor_power = 3'd0; + +endmodule + + +// PyMTL Component RetRTL Definition +// Full name: RetRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py + +module RetRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_RET = 7'd35; + localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; + logic [0:0] already_done; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py:48 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register. + // s.in0 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // + // for j in range(num_outports): + // s.send_out[j].val @= 0 + // s.send_out[j].msg @= DataType() + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_RET: + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // # Value to be returned is usually granted with a predicate: + // # https://github.com/coredac/dataflow/blob/b9ffc097d67429017323e3d50d3984655f756b91/test/neura/ctrl/branch_for.mlir#L150. + // if s.already_done: + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val + // s.recv_opt.rdy @= s.recv_all_val + // elif s.recv_in[s.in0_idx].msg.predicate: + // # Only when the predicate is true, the value will be sent back to CPU. + // s.send_to_ctrl_mem.val @= s.recv_all_val & s.reached_vector_factor + // # s.send_to_ctrl_mem.msg @= s.recv_in[s.in0_idx].msg + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(CMD_COMPLETE, s.recv_in[s.in0_idx].msg, 0, s.recv_opt.msg, 0) + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.reached_vector_factor & s.send_to_ctrl_mem.rdy + // s.recv_opt.rdy @= s.recv_all_val & s.reached_vector_factor & s.send_to_ctrl_mem.rdy + // else: + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.reached_vector_factor + // s.recv_opt.rdy @= s.recv_all_val & s.reached_vector_factor + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin + send_out__val[1'(j)] = 1'd0; + send_out__msg[1'(j)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_RET ) ) begin + recv_all_val = recv_in__val[in0_idx]; + if ( already_done ) begin + recv_in__rdy[in0_idx] = recv_all_val; + recv_opt__rdy = recv_all_val; + end + else if ( recv_in__msg[in0_idx].predicate ) begin + send_to_ctrl_mem__val = recv_all_val & reached_vector_factor; + send_to_ctrl_mem__msg = { 5'( __const__CMD_COMPLETE ), recv_in__msg[in0_idx], 7'd0, recv_opt__msg, 4'd0 }; + recv_in__rdy[in0_idx] = ( recv_all_val & reached_vector_factor ) & send_to_ctrl_mem__rdy; + recv_opt__rdy = ( recv_all_val & reached_vector_factor ) & send_to_ctrl_mem__rdy; + end + else begin + recv_in__rdy[in0_idx] = recv_all_val & reached_vector_factor; + recv_opt__rdy = recv_all_val & reached_vector_factor; + end + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py:91 + // @update_ff + // def update_already_done(): + // if s.reset | s.clear: + // s.already_done <<= 0 + // else: + // if s.recv_opt.val & \ + // (s.recv_opt.msg.operation == OPT_RET) & \ + // ~s.already_done & \ + // s.recv_all_val & \ + // s.send_to_ctrl_mem.val & \ + // s.send_to_ctrl_mem.rdy: + // s.already_done <<= 1 + // else: + // s.already_done <<= s.already_done + + always_ff @(posedge clk) begin : update_already_done + if ( reset | clear ) begin + already_done <= 1'd0; + end + else if ( ( ( ( ( recv_opt__val & ( recv_opt__msg.operation == 7'( __const__OPT_RET ) ) ) & ( ~already_done ) ) & recv_all_val ) & send_to_ctrl_mem__val ) & send_to_ctrl_mem__rdy ) begin + already_done <= 1'd1; + end + else + already_done <= already_done; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + +endmodule + + +// PyMTL Component FlexibleFuRTL Definition +// Full name: FlexibleFuRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__num_tiles_16__FuList_[, , , , , , , , , , , , , , ]__exec_lantency_{} +// At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py + +module FlexibleFuRTL__07217382918d0fc2 +( + input logic [0:0] clear [0:14], + input logic [0:0] clk , + input logic [2:0] prologue_count_inport , + input logic [0:0] reset , + input logic [4:0] tile_id , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg [0:14] , + output logic [0:0] from_mem_rdata__rdy [0:14] , + input logic [0:0] from_mem_rdata__val [0:14] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg [0:14] , + input logic [0:0] to_mem_raddr__rdy [0:14] , + output logic [0:0] to_mem_raddr__val [0:14] , + output logic [6:0] to_mem_waddr__msg [0:14] , + input logic [0:0] to_mem_waddr__rdy [0:14] , + output logic [0:0] to_mem_waddr__val [0:14] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg [0:14] , + input logic [0:0] to_mem_wdata__rdy [0:14] , + output logic [0:0] to_mem_wdata__val [0:14] +); + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_NAH = 7'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + logic [14:0] fu_recv_const_rdy_vector; + logic [14:0] fu_recv_in_rdy_vector [0:3]; + logic [14:0] fu_recv_opt_rdy_vector; + logic [14:0] recv_from_controller_rdy_vector; + //------------------------------------------------------------- + // Component fu[0:14] + //------------------------------------------------------------- + + logic [0:0] fu__clear [0:14]; + logic [0:0] fu__clk [0:14]; + logic [0:0] fu__reset [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__from_mem_rdata__msg [0:14]; + logic [0:0] fu__from_mem_rdata__rdy [0:14]; + logic [0:0] fu__from_mem_rdata__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__recv_const__msg [0:14]; + logic [0:0] fu__recv_const__rdy [0:14]; + logic [0:0] fu__recv_const__val [0:14]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a fu__recv_from_ctrl_mem__msg [0:14]; + logic [0:0] fu__recv_from_ctrl_mem__rdy [0:14]; + logic [0:0] fu__recv_from_ctrl_mem__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__recv_in__msg [0:14][0:3]; + logic [0:0] fu__recv_in__rdy [0:14][0:3]; + logic [0:0] fu__recv_in__val [0:14][0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 fu__recv_opt__msg [0:14]; + logic [0:0] fu__recv_opt__rdy [0:14]; + logic [0:0] fu__recv_opt__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__send_out__msg [0:14][0:1]; + logic [0:0] fu__send_out__rdy [0:14][0:1]; + logic [0:0] fu__send_out__val [0:14][0:1]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a fu__send_to_ctrl_mem__msg [0:14]; + logic [0:0] fu__send_to_ctrl_mem__rdy [0:14]; + logic [0:0] fu__send_to_ctrl_mem__val [0:14]; + logic [6:0] fu__to_mem_raddr__msg [0:14]; + logic [0:0] fu__to_mem_raddr__rdy [0:14]; + logic [0:0] fu__to_mem_raddr__val [0:14]; + logic [6:0] fu__to_mem_waddr__msg [0:14]; + logic [0:0] fu__to_mem_waddr__rdy [0:14]; + logic [0:0] fu__to_mem_waddr__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__to_mem_wdata__msg [0:14]; + logic [0:0] fu__to_mem_wdata__rdy [0:14]; + logic [0:0] fu__to_mem_wdata__val [0:14]; + + AdderRTL__45df3c5556ff02e3 fu__0 + ( + .clear( fu__clear[0] ), + .clk( fu__clk[0] ), + .reset( fu__reset[0] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[0] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[0] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[0] ), + .recv_const__msg( fu__recv_const__msg[0] ), + .recv_const__rdy( fu__recv_const__rdy[0] ), + .recv_const__val( fu__recv_const__val[0] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[0] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[0] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[0] ), + .recv_in__msg( fu__recv_in__msg[0] ), + .recv_in__rdy( fu__recv_in__rdy[0] ), + .recv_in__val( fu__recv_in__val[0] ), + .recv_opt__msg( fu__recv_opt__msg[0] ), + .recv_opt__rdy( fu__recv_opt__rdy[0] ), + .recv_opt__val( fu__recv_opt__val[0] ), + .send_out__msg( fu__send_out__msg[0] ), + .send_out__rdy( fu__send_out__rdy[0] ), + .send_out__val( fu__send_out__val[0] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[0] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[0] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[0] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[0] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[0] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[0] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[0] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[0] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[0] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[0] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[0] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[0] ) + ); + + MulRTL__45df3c5556ff02e3 fu__1 + ( + .clear( fu__clear[1] ), + .clk( fu__clk[1] ), + .reset( fu__reset[1] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[1] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[1] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[1] ), + .recv_const__msg( fu__recv_const__msg[1] ), + .recv_const__rdy( fu__recv_const__rdy[1] ), + .recv_const__val( fu__recv_const__val[1] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[1] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[1] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[1] ), + .recv_in__msg( fu__recv_in__msg[1] ), + .recv_in__rdy( fu__recv_in__rdy[1] ), + .recv_in__val( fu__recv_in__val[1] ), + .recv_opt__msg( fu__recv_opt__msg[1] ), + .recv_opt__rdy( fu__recv_opt__rdy[1] ), + .recv_opt__val( fu__recv_opt__val[1] ), + .send_out__msg( fu__send_out__msg[1] ), + .send_out__rdy( fu__send_out__rdy[1] ), + .send_out__val( fu__send_out__val[1] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[1] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[1] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[1] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[1] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[1] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[1] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[1] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[1] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[1] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[1] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[1] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[1] ) + ); + + LogicRTL__45df3c5556ff02e3 fu__2 + ( + .clear( fu__clear[2] ), + .clk( fu__clk[2] ), + .reset( fu__reset[2] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[2] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[2] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[2] ), + .recv_const__msg( fu__recv_const__msg[2] ), + .recv_const__rdy( fu__recv_const__rdy[2] ), + .recv_const__val( fu__recv_const__val[2] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[2] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[2] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[2] ), + .recv_in__msg( fu__recv_in__msg[2] ), + .recv_in__rdy( fu__recv_in__rdy[2] ), + .recv_in__val( fu__recv_in__val[2] ), + .recv_opt__msg( fu__recv_opt__msg[2] ), + .recv_opt__rdy( fu__recv_opt__rdy[2] ), + .recv_opt__val( fu__recv_opt__val[2] ), + .send_out__msg( fu__send_out__msg[2] ), + .send_out__rdy( fu__send_out__rdy[2] ), + .send_out__val( fu__send_out__val[2] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[2] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[2] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[2] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[2] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[2] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[2] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[2] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[2] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[2] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[2] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[2] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[2] ) + ); + + ShifterRTL__45df3c5556ff02e3 fu__3 + ( + .clear( fu__clear[3] ), + .clk( fu__clk[3] ), + .reset( fu__reset[3] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[3] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[3] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[3] ), + .recv_const__msg( fu__recv_const__msg[3] ), + .recv_const__rdy( fu__recv_const__rdy[3] ), + .recv_const__val( fu__recv_const__val[3] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[3] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[3] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[3] ), + .recv_in__msg( fu__recv_in__msg[3] ), + .recv_in__rdy( fu__recv_in__rdy[3] ), + .recv_in__val( fu__recv_in__val[3] ), + .recv_opt__msg( fu__recv_opt__msg[3] ), + .recv_opt__rdy( fu__recv_opt__rdy[3] ), + .recv_opt__val( fu__recv_opt__val[3] ), + .send_out__msg( fu__send_out__msg[3] ), + .send_out__rdy( fu__send_out__rdy[3] ), + .send_out__val( fu__send_out__val[3] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[3] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[3] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[3] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[3] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[3] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[3] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[3] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[3] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[3] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[3] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[3] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[3] ) + ); + + PhiRTL__45df3c5556ff02e3 fu__4 + ( + .clear( fu__clear[4] ), + .clk( fu__clk[4] ), + .reset( fu__reset[4] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[4] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[4] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[4] ), + .recv_const__msg( fu__recv_const__msg[4] ), + .recv_const__rdy( fu__recv_const__rdy[4] ), + .recv_const__val( fu__recv_const__val[4] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[4] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[4] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[4] ), + .recv_in__msg( fu__recv_in__msg[4] ), + .recv_in__rdy( fu__recv_in__rdy[4] ), + .recv_in__val( fu__recv_in__val[4] ), + .recv_opt__msg( fu__recv_opt__msg[4] ), + .recv_opt__rdy( fu__recv_opt__rdy[4] ), + .recv_opt__val( fu__recv_opt__val[4] ), + .send_out__msg( fu__send_out__msg[4] ), + .send_out__rdy( fu__send_out__rdy[4] ), + .send_out__val( fu__send_out__val[4] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[4] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[4] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[4] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[4] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[4] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[4] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[4] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[4] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[4] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[4] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[4] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[4] ) + ); + + CompRTL__45df3c5556ff02e3 fu__5 + ( + .clear( fu__clear[5] ), + .clk( fu__clk[5] ), + .reset( fu__reset[5] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[5] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[5] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[5] ), + .recv_const__msg( fu__recv_const__msg[5] ), + .recv_const__rdy( fu__recv_const__rdy[5] ), + .recv_const__val( fu__recv_const__val[5] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[5] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[5] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[5] ), + .recv_in__msg( fu__recv_in__msg[5] ), + .recv_in__rdy( fu__recv_in__rdy[5] ), + .recv_in__val( fu__recv_in__val[5] ), + .recv_opt__msg( fu__recv_opt__msg[5] ), + .recv_opt__rdy( fu__recv_opt__rdy[5] ), + .recv_opt__val( fu__recv_opt__val[5] ), + .send_out__msg( fu__send_out__msg[5] ), + .send_out__rdy( fu__send_out__rdy[5] ), + .send_out__val( fu__send_out__val[5] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[5] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[5] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[5] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[5] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[5] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[5] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[5] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[5] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[5] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[5] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[5] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[5] ) + ); + + GrantRTL__45df3c5556ff02e3 fu__6 + ( + .clear( fu__clear[6] ), + .clk( fu__clk[6] ), + .reset( fu__reset[6] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[6] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[6] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[6] ), + .recv_const__msg( fu__recv_const__msg[6] ), + .recv_const__rdy( fu__recv_const__rdy[6] ), + .recv_const__val( fu__recv_const__val[6] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[6] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[6] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[6] ), + .recv_in__msg( fu__recv_in__msg[6] ), + .recv_in__rdy( fu__recv_in__rdy[6] ), + .recv_in__val( fu__recv_in__val[6] ), + .recv_opt__msg( fu__recv_opt__msg[6] ), + .recv_opt__rdy( fu__recv_opt__rdy[6] ), + .recv_opt__val( fu__recv_opt__val[6] ), + .send_out__msg( fu__send_out__msg[6] ), + .send_out__rdy( fu__send_out__rdy[6] ), + .send_out__val( fu__send_out__val[6] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[6] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[6] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[6] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[6] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[6] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[6] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[6] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[6] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[6] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[6] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[6] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[6] ) + ); + + MemUnitRTL__45df3c5556ff02e3 fu__7 + ( + .clear( fu__clear[7] ), + .clk( fu__clk[7] ), + .reset( fu__reset[7] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[7] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[7] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[7] ), + .recv_const__msg( fu__recv_const__msg[7] ), + .recv_const__rdy( fu__recv_const__rdy[7] ), + .recv_const__val( fu__recv_const__val[7] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[7] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[7] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[7] ), + .recv_in__msg( fu__recv_in__msg[7] ), + .recv_in__rdy( fu__recv_in__rdy[7] ), + .recv_in__val( fu__recv_in__val[7] ), + .recv_opt__msg( fu__recv_opt__msg[7] ), + .recv_opt__rdy( fu__recv_opt__rdy[7] ), + .recv_opt__val( fu__recv_opt__val[7] ), + .send_out__msg( fu__send_out__msg[7] ), + .send_out__rdy( fu__send_out__rdy[7] ), + .send_out__val( fu__send_out__val[7] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[7] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[7] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[7] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[7] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[7] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[7] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[7] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[7] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[7] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[7] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[7] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[7] ) + ); + + SelRTL__45df3c5556ff02e3 fu__8 + ( + .clear( fu__clear[8] ), + .clk( fu__clk[8] ), + .reset( fu__reset[8] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[8] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[8] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[8] ), + .recv_const__msg( fu__recv_const__msg[8] ), + .recv_const__rdy( fu__recv_const__rdy[8] ), + .recv_const__val( fu__recv_const__val[8] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[8] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[8] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[8] ), + .recv_in__msg( fu__recv_in__msg[8] ), + .recv_in__rdy( fu__recv_in__rdy[8] ), + .recv_in__val( fu__recv_in__val[8] ), + .recv_opt__msg( fu__recv_opt__msg[8] ), + .recv_opt__rdy( fu__recv_opt__rdy[8] ), + .recv_opt__val( fu__recv_opt__val[8] ), + .send_out__msg( fu__send_out__msg[8] ), + .send_out__rdy( fu__send_out__rdy[8] ), + .send_out__val( fu__send_out__val[8] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[8] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[8] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[8] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[8] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[8] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[8] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[8] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[8] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[8] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[8] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[8] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[8] ) + ); + + RetRTL__45df3c5556ff02e3 fu__9 + ( + .clear( fu__clear[9] ), + .clk( fu__clk[9] ), + .reset( fu__reset[9] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[9] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[9] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[9] ), + .recv_const__msg( fu__recv_const__msg[9] ), + .recv_const__rdy( fu__recv_const__rdy[9] ), + .recv_const__val( fu__recv_const__val[9] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[9] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[9] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[9] ), + .recv_in__msg( fu__recv_in__msg[9] ), + .recv_in__rdy( fu__recv_in__rdy[9] ), + .recv_in__val( fu__recv_in__val[9] ), + .recv_opt__msg( fu__recv_opt__msg[9] ), + .recv_opt__rdy( fu__recv_opt__rdy[9] ), + .recv_opt__val( fu__recv_opt__val[9] ), + .send_out__msg( fu__send_out__msg[9] ), + .send_out__rdy( fu__send_out__rdy[9] ), + .send_out__val( fu__send_out__val[9] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[9] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[9] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[9] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[9] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[9] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[9] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[9] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[9] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[9] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[9] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[9] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[9] ) + ); + + SeqMulAdderRTL__b741248a3a1dca5f fu__10 + ( + .clear( fu__clear[10] ), + .clk( fu__clk[10] ), + .reset( fu__reset[10] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[10] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[10] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[10] ), + .recv_const__msg( fu__recv_const__msg[10] ), + .recv_const__rdy( fu__recv_const__rdy[10] ), + .recv_const__val( fu__recv_const__val[10] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[10] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[10] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[10] ), + .recv_in__msg( fu__recv_in__msg[10] ), + .recv_in__rdy( fu__recv_in__rdy[10] ), + .recv_in__val( fu__recv_in__val[10] ), + .recv_opt__msg( fu__recv_opt__msg[10] ), + .recv_opt__rdy( fu__recv_opt__rdy[10] ), + .recv_opt__val( fu__recv_opt__val[10] ), + .send_out__msg( fu__send_out__msg[10] ), + .send_out__rdy( fu__send_out__rdy[10] ), + .send_out__val( fu__send_out__val[10] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[10] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[10] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[10] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[10] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[10] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[10] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[10] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[10] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[10] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[10] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[10] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[10] ) + ); + + VectorMulComboRTL__e2d25a29972e2033 fu__11 + ( + .clear( fu__clear[11] ), + .clk( fu__clk[11] ), + .reset( fu__reset[11] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[11] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[11] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[11] ), + .recv_const__msg( fu__recv_const__msg[11] ), + .recv_const__rdy( fu__recv_const__rdy[11] ), + .recv_const__val( fu__recv_const__val[11] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[11] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[11] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[11] ), + .recv_in__msg( fu__recv_in__msg[11] ), + .recv_in__rdy( fu__recv_in__rdy[11] ), + .recv_in__val( fu__recv_in__val[11] ), + .recv_opt__msg( fu__recv_opt__msg[11] ), + .recv_opt__rdy( fu__recv_opt__rdy[11] ), + .recv_opt__val( fu__recv_opt__val[11] ), + .send_out__msg( fu__send_out__msg[11] ), + .send_out__rdy( fu__send_out__rdy[11] ), + .send_out__val( fu__send_out__val[11] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[11] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[11] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[11] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[11] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[11] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[11] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[11] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[11] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[11] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[11] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[11] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[11] ) + ); + + VectorAdderComboRTL__e2d25a29972e2033 fu__12 + ( + .clear( fu__clear[12] ), + .clk( fu__clk[12] ), + .reset( fu__reset[12] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[12] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[12] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[12] ), + .recv_const__msg( fu__recv_const__msg[12] ), + .recv_const__rdy( fu__recv_const__rdy[12] ), + .recv_const__val( fu__recv_const__val[12] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[12] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[12] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[12] ), + .recv_in__msg( fu__recv_in__msg[12] ), + .recv_in__rdy( fu__recv_in__rdy[12] ), + .recv_in__val( fu__recv_in__val[12] ), + .recv_opt__msg( fu__recv_opt__msg[12] ), + .recv_opt__rdy( fu__recv_opt__rdy[12] ), + .recv_opt__val( fu__recv_opt__val[12] ), + .send_out__msg( fu__send_out__msg[12] ), + .send_out__rdy( fu__send_out__rdy[12] ), + .send_out__val( fu__send_out__val[12] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[12] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[12] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[12] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[12] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[12] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[12] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[12] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[12] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[12] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[12] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[12] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[12] ) + ); + + VectorAllReduceRTL__e2d25a29972e2033 fu__13 + ( + .clear( fu__clear[13] ), + .clk( fu__clk[13] ), + .reset( fu__reset[13] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[13] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[13] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[13] ), + .recv_const__msg( fu__recv_const__msg[13] ), + .recv_const__rdy( fu__recv_const__rdy[13] ), + .recv_const__val( fu__recv_const__val[13] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[13] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[13] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[13] ), + .recv_in__msg( fu__recv_in__msg[13] ), + .recv_in__rdy( fu__recv_in__rdy[13] ), + .recv_in__val( fu__recv_in__val[13] ), + .recv_opt__msg( fu__recv_opt__msg[13] ), + .recv_opt__rdy( fu__recv_opt__rdy[13] ), + .recv_opt__val( fu__recv_opt__val[13] ), + .send_out__msg( fu__send_out__msg[13] ), + .send_out__rdy( fu__send_out__rdy[13] ), + .send_out__val( fu__send_out__val[13] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[13] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[13] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[13] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[13] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[13] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[13] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[13] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[13] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[13] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[13] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[13] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[13] ) + ); + + NahRTL__45df3c5556ff02e3 fu__14 + ( + .clear( fu__clear[14] ), + .clk( fu__clk[14] ), + .reset( fu__reset[14] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[14] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[14] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[14] ), + .recv_const__msg( fu__recv_const__msg[14] ), + .recv_const__rdy( fu__recv_const__rdy[14] ), + .recv_const__val( fu__recv_const__val[14] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[14] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[14] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[14] ), + .recv_in__msg( fu__recv_in__msg[14] ), + .recv_in__rdy( fu__recv_in__rdy[14] ), + .recv_in__val( fu__recv_in__val[14] ), + .recv_opt__msg( fu__recv_opt__msg[14] ), + .recv_opt__rdy( fu__recv_opt__rdy[14] ), + .recv_opt__val( fu__recv_opt__val[14] ), + .send_out__msg( fu__send_out__msg[14] ), + .send_out__rdy( fu__send_out__rdy[14] ), + .send_out__val( fu__send_out__val[14] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[14] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[14] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[14] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[14] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[14] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[14] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[14] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[14] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[14] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[14] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[14] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[14] ) + ); + + //------------------------------------------------------------- + // End of component fu[0:14] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py:107 + // @update + // def comb_logic(): + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.send_out[j].msg @= DataType() + // + // for i in range(s.fu_list_size): + // # const connection. + // s.fu[i].recv_const.msg @= s.recv_const.msg + // s.fu[i].recv_const.val @= s.recv_const.val + // s.fu_recv_const_rdy_vector[i] @= s.fu[i].recv_const.rdy + // + // # opt connection. + // s.fu[i].recv_opt.msg @= s.recv_opt.msg + // # Sets each FU's op code as NAH when prologue execution is not completed. + // # As they are supposed to do nothing during that prologue cycles. + // if s.prologue_count_inport != 0: + // s.fu[i].recv_opt.msg.operation @= OPT_NAH + // s.fu[i].recv_opt.val @= s.recv_opt.val + // s.fu_recv_opt_rdy_vector[i] @= s.fu[i].recv_opt.rdy + // + // # send_out connection. + // for j in range(num_outports): + // # FIXME: need reduce_or here: https://github.com/tancheng/VectorCGRA/issues/51. + // if s.fu[i].send_out[j].val: + // s.send_out[j].msg @= s.fu[i].send_out[j].msg + // s.send_out[j].val @= s.fu[i].send_out[j].val + // s.fu[i].send_out[j].rdy @= s.send_out[j].rdy + // + // s.recv_const.rdy @= reduce_or(s.fu_recv_const_rdy_vector) + // # Operation (especially mem access) won't perform more than once, because once the + // # operation is performance (i.e., the recv_opt.rdy would be set), the `element_done` + // # register would be set and be respected. + // s.recv_opt.rdy @= reduce_or(s.fu_recv_opt_rdy_vector) | (s.prologue_count_inport != 0) + // + // for j in range(num_inports): + // s.recv_in[j].rdy @= b1(0) + // + // # recv_in connection. + // for port in range(num_inports): + // for i in range(s.fu_list_size): + // s.fu[i].recv_in[port].msg @= s.recv_in[port].msg + // s.fu[i].recv_in[port].val @= s.recv_in[port].val + // # s.recv_in[j].rdy @= s.fu[i].recv_in[j].rdy | s.recv_in[j].rdy + // s.fu_recv_in_rdy_vector[port][i] @= s.fu[i].recv_in[port].rdy + // s.recv_in[port].rdy @= reduce_or(s.fu_recv_in_rdy_vector[port]) + + always_comb begin : comb_logic + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin + send_out__val[1'(j)] = 1'd0; + send_out__msg[1'(j)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin + fu__recv_const__msg[4'(i)] = recv_const__msg; + fu__recv_const__val[4'(i)] = recv_const__val; + fu_recv_const_rdy_vector[4'(i)] = fu__recv_const__rdy[4'(i)]; + fu__recv_opt__msg[4'(i)] = recv_opt__msg; + if ( prologue_count_inport != 3'd0 ) begin + fu__recv_opt__msg[4'(i)].operation = 7'( __const__OPT_NAH ); + end + fu__recv_opt__val[4'(i)] = recv_opt__val; + fu_recv_opt_rdy_vector[4'(i)] = fu__recv_opt__rdy[4'(i)]; + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin + if ( fu__send_out__val[4'(i)][1'(j)] ) begin + send_out__msg[1'(j)] = fu__send_out__msg[4'(i)][1'(j)]; + send_out__val[1'(j)] = fu__send_out__val[4'(i)][1'(j)]; + end + fu__send_out__rdy[4'(i)][1'(j)] = send_out__rdy[1'(j)]; + end + end + recv_const__rdy = ( | fu_recv_const_rdy_vector ); + recv_opt__rdy = ( | fu_recv_opt_rdy_vector ) | ( prologue_count_inport != 3'd0 ); + for ( int unsigned j = 1'd0; j < 3'( __const__num_inports_at_comb_logic ); j += 1'd1 ) + recv_in__rdy[2'(j)] = 1'd0; + for ( int unsigned port = 1'd0; port < 3'( __const__num_inports_at_comb_logic ); port += 1'd1 ) begin + for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin + fu__recv_in__msg[4'(i)][2'(port)] = recv_in__msg[2'(port)]; + fu__recv_in__val[4'(i)][2'(port)] = recv_in__val[2'(port)]; + fu_recv_in_rdy_vector[2'(port)][4'(i)] = fu__recv_in__rdy[4'(i)][2'(port)]; + end + recv_in__rdy[2'(port)] = ( | fu_recv_in_rdy_vector[2'(port)] ); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py:90 + // @update + // def connect_to_controller(): + // for i in range(s.fu_list_size): + // # const connection. + // s.fu[i].recv_from_ctrl_mem.msg @= s.recv_from_ctrl_mem.msg + // s.fu[i].recv_from_ctrl_mem.val @= s.recv_from_ctrl_mem.val + // s.recv_from_controller_rdy_vector[i] @= s.fu[i].recv_from_ctrl_mem.rdy + // s.recv_from_ctrl_mem.rdy @= reduce_or(s.recv_from_controller_rdy_vector) + // + // s.send_to_ctrl_mem.msg @= CgraPayloadType(0, 0, 0, 0, 0) + // s.send_to_ctrl_mem.val @= 0 + // for i in range(s.fu_list_size): + // if s.fu[i].send_to_ctrl_mem.val: + // s.send_to_ctrl_mem.msg @= s.fu[i].send_to_ctrl_mem.msg + // s.send_to_ctrl_mem.val @= s.fu[i].send_to_ctrl_mem.val + // s.fu[i].send_to_ctrl_mem.rdy @= s.send_to_ctrl_mem.rdy + + always_comb begin : connect_to_controller + for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin + fu__recv_from_ctrl_mem__msg[4'(i)] = recv_from_ctrl_mem__msg; + fu__recv_from_ctrl_mem__val[4'(i)] = recv_from_ctrl_mem__val; + recv_from_controller_rdy_vector[4'(i)] = fu__recv_from_ctrl_mem__rdy[4'(i)]; + end + recv_from_ctrl_mem__rdy = ( | recv_from_controller_rdy_vector ); + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + send_to_ctrl_mem__val = 1'd0; + for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin + if ( fu__send_to_ctrl_mem__val[4'(i)] ) begin + send_to_ctrl_mem__msg = fu__send_to_ctrl_mem__msg[4'(i)]; + send_to_ctrl_mem__val = fu__send_to_ctrl_mem__val[4'(i)]; + end + fu__send_to_ctrl_mem__rdy[4'(i)] = send_to_ctrl_mem__rdy; + end + end + + assign fu__clk[0] = clk; + assign fu__reset[0] = reset; + assign fu__clk[1] = clk; + assign fu__reset[1] = reset; + assign fu__clk[2] = clk; + assign fu__reset[2] = reset; + assign fu__clk[3] = clk; + assign fu__reset[3] = reset; + assign fu__clk[4] = clk; + assign fu__reset[4] = reset; + assign fu__clk[5] = clk; + assign fu__reset[5] = reset; + assign fu__clk[6] = clk; + assign fu__reset[6] = reset; + assign fu__clk[7] = clk; + assign fu__reset[7] = reset; + assign fu__clk[8] = clk; + assign fu__reset[8] = reset; + assign fu__clk[9] = clk; + assign fu__reset[9] = reset; + assign fu__clk[10] = clk; + assign fu__reset[10] = reset; + assign fu__clk[11] = clk; + assign fu__reset[11] = reset; + assign fu__clk[12] = clk; + assign fu__reset[12] = reset; + assign fu__clk[13] = clk; + assign fu__reset[13] = reset; + assign fu__clk[14] = clk; + assign fu__reset[14] = reset; + assign to_mem_raddr__msg[0] = fu__to_mem_raddr__msg[0]; + assign fu__to_mem_raddr__rdy[0] = to_mem_raddr__rdy[0]; + assign to_mem_raddr__val[0] = fu__to_mem_raddr__val[0]; + assign fu__from_mem_rdata__msg[0] = from_mem_rdata__msg[0]; + assign from_mem_rdata__rdy[0] = fu__from_mem_rdata__rdy[0]; + assign fu__from_mem_rdata__val[0] = from_mem_rdata__val[0]; + assign to_mem_waddr__msg[0] = fu__to_mem_waddr__msg[0]; + assign fu__to_mem_waddr__rdy[0] = to_mem_waddr__rdy[0]; + assign to_mem_waddr__val[0] = fu__to_mem_waddr__val[0]; + assign to_mem_wdata__msg[0] = fu__to_mem_wdata__msg[0]; + assign fu__to_mem_wdata__rdy[0] = to_mem_wdata__rdy[0]; + assign to_mem_wdata__val[0] = fu__to_mem_wdata__val[0]; + assign fu__clear[0] = clear[0]; + assign to_mem_raddr__msg[1] = fu__to_mem_raddr__msg[1]; + assign fu__to_mem_raddr__rdy[1] = to_mem_raddr__rdy[1]; + assign to_mem_raddr__val[1] = fu__to_mem_raddr__val[1]; + assign fu__from_mem_rdata__msg[1] = from_mem_rdata__msg[1]; + assign from_mem_rdata__rdy[1] = fu__from_mem_rdata__rdy[1]; + assign fu__from_mem_rdata__val[1] = from_mem_rdata__val[1]; + assign to_mem_waddr__msg[1] = fu__to_mem_waddr__msg[1]; + assign fu__to_mem_waddr__rdy[1] = to_mem_waddr__rdy[1]; + assign to_mem_waddr__val[1] = fu__to_mem_waddr__val[1]; + assign to_mem_wdata__msg[1] = fu__to_mem_wdata__msg[1]; + assign fu__to_mem_wdata__rdy[1] = to_mem_wdata__rdy[1]; + assign to_mem_wdata__val[1] = fu__to_mem_wdata__val[1]; + assign fu__clear[1] = clear[1]; + assign to_mem_raddr__msg[2] = fu__to_mem_raddr__msg[2]; + assign fu__to_mem_raddr__rdy[2] = to_mem_raddr__rdy[2]; + assign to_mem_raddr__val[2] = fu__to_mem_raddr__val[2]; + assign fu__from_mem_rdata__msg[2] = from_mem_rdata__msg[2]; + assign from_mem_rdata__rdy[2] = fu__from_mem_rdata__rdy[2]; + assign fu__from_mem_rdata__val[2] = from_mem_rdata__val[2]; + assign to_mem_waddr__msg[2] = fu__to_mem_waddr__msg[2]; + assign fu__to_mem_waddr__rdy[2] = to_mem_waddr__rdy[2]; + assign to_mem_waddr__val[2] = fu__to_mem_waddr__val[2]; + assign to_mem_wdata__msg[2] = fu__to_mem_wdata__msg[2]; + assign fu__to_mem_wdata__rdy[2] = to_mem_wdata__rdy[2]; + assign to_mem_wdata__val[2] = fu__to_mem_wdata__val[2]; + assign fu__clear[2] = clear[2]; + assign to_mem_raddr__msg[3] = fu__to_mem_raddr__msg[3]; + assign fu__to_mem_raddr__rdy[3] = to_mem_raddr__rdy[3]; + assign to_mem_raddr__val[3] = fu__to_mem_raddr__val[3]; + assign fu__from_mem_rdata__msg[3] = from_mem_rdata__msg[3]; + assign from_mem_rdata__rdy[3] = fu__from_mem_rdata__rdy[3]; + assign fu__from_mem_rdata__val[3] = from_mem_rdata__val[3]; + assign to_mem_waddr__msg[3] = fu__to_mem_waddr__msg[3]; + assign fu__to_mem_waddr__rdy[3] = to_mem_waddr__rdy[3]; + assign to_mem_waddr__val[3] = fu__to_mem_waddr__val[3]; + assign to_mem_wdata__msg[3] = fu__to_mem_wdata__msg[3]; + assign fu__to_mem_wdata__rdy[3] = to_mem_wdata__rdy[3]; + assign to_mem_wdata__val[3] = fu__to_mem_wdata__val[3]; + assign fu__clear[3] = clear[3]; + assign to_mem_raddr__msg[4] = fu__to_mem_raddr__msg[4]; + assign fu__to_mem_raddr__rdy[4] = to_mem_raddr__rdy[4]; + assign to_mem_raddr__val[4] = fu__to_mem_raddr__val[4]; + assign fu__from_mem_rdata__msg[4] = from_mem_rdata__msg[4]; + assign from_mem_rdata__rdy[4] = fu__from_mem_rdata__rdy[4]; + assign fu__from_mem_rdata__val[4] = from_mem_rdata__val[4]; + assign to_mem_waddr__msg[4] = fu__to_mem_waddr__msg[4]; + assign fu__to_mem_waddr__rdy[4] = to_mem_waddr__rdy[4]; + assign to_mem_waddr__val[4] = fu__to_mem_waddr__val[4]; + assign to_mem_wdata__msg[4] = fu__to_mem_wdata__msg[4]; + assign fu__to_mem_wdata__rdy[4] = to_mem_wdata__rdy[4]; + assign to_mem_wdata__val[4] = fu__to_mem_wdata__val[4]; + assign fu__clear[4] = clear[4]; + assign to_mem_raddr__msg[5] = fu__to_mem_raddr__msg[5]; + assign fu__to_mem_raddr__rdy[5] = to_mem_raddr__rdy[5]; + assign to_mem_raddr__val[5] = fu__to_mem_raddr__val[5]; + assign fu__from_mem_rdata__msg[5] = from_mem_rdata__msg[5]; + assign from_mem_rdata__rdy[5] = fu__from_mem_rdata__rdy[5]; + assign fu__from_mem_rdata__val[5] = from_mem_rdata__val[5]; + assign to_mem_waddr__msg[5] = fu__to_mem_waddr__msg[5]; + assign fu__to_mem_waddr__rdy[5] = to_mem_waddr__rdy[5]; + assign to_mem_waddr__val[5] = fu__to_mem_waddr__val[5]; + assign to_mem_wdata__msg[5] = fu__to_mem_wdata__msg[5]; + assign fu__to_mem_wdata__rdy[5] = to_mem_wdata__rdy[5]; + assign to_mem_wdata__val[5] = fu__to_mem_wdata__val[5]; + assign fu__clear[5] = clear[5]; + assign to_mem_raddr__msg[6] = fu__to_mem_raddr__msg[6]; + assign fu__to_mem_raddr__rdy[6] = to_mem_raddr__rdy[6]; + assign to_mem_raddr__val[6] = fu__to_mem_raddr__val[6]; + assign fu__from_mem_rdata__msg[6] = from_mem_rdata__msg[6]; + assign from_mem_rdata__rdy[6] = fu__from_mem_rdata__rdy[6]; + assign fu__from_mem_rdata__val[6] = from_mem_rdata__val[6]; + assign to_mem_waddr__msg[6] = fu__to_mem_waddr__msg[6]; + assign fu__to_mem_waddr__rdy[6] = to_mem_waddr__rdy[6]; + assign to_mem_waddr__val[6] = fu__to_mem_waddr__val[6]; + assign to_mem_wdata__msg[6] = fu__to_mem_wdata__msg[6]; + assign fu__to_mem_wdata__rdy[6] = to_mem_wdata__rdy[6]; + assign to_mem_wdata__val[6] = fu__to_mem_wdata__val[6]; + assign fu__clear[6] = clear[6]; + assign to_mem_raddr__msg[7] = fu__to_mem_raddr__msg[7]; + assign fu__to_mem_raddr__rdy[7] = to_mem_raddr__rdy[7]; + assign to_mem_raddr__val[7] = fu__to_mem_raddr__val[7]; + assign fu__from_mem_rdata__msg[7] = from_mem_rdata__msg[7]; + assign from_mem_rdata__rdy[7] = fu__from_mem_rdata__rdy[7]; + assign fu__from_mem_rdata__val[7] = from_mem_rdata__val[7]; + assign to_mem_waddr__msg[7] = fu__to_mem_waddr__msg[7]; + assign fu__to_mem_waddr__rdy[7] = to_mem_waddr__rdy[7]; + assign to_mem_waddr__val[7] = fu__to_mem_waddr__val[7]; + assign to_mem_wdata__msg[7] = fu__to_mem_wdata__msg[7]; + assign fu__to_mem_wdata__rdy[7] = to_mem_wdata__rdy[7]; + assign to_mem_wdata__val[7] = fu__to_mem_wdata__val[7]; + assign fu__clear[7] = clear[7]; + assign to_mem_raddr__msg[8] = fu__to_mem_raddr__msg[8]; + assign fu__to_mem_raddr__rdy[8] = to_mem_raddr__rdy[8]; + assign to_mem_raddr__val[8] = fu__to_mem_raddr__val[8]; + assign fu__from_mem_rdata__msg[8] = from_mem_rdata__msg[8]; + assign from_mem_rdata__rdy[8] = fu__from_mem_rdata__rdy[8]; + assign fu__from_mem_rdata__val[8] = from_mem_rdata__val[8]; + assign to_mem_waddr__msg[8] = fu__to_mem_waddr__msg[8]; + assign fu__to_mem_waddr__rdy[8] = to_mem_waddr__rdy[8]; + assign to_mem_waddr__val[8] = fu__to_mem_waddr__val[8]; + assign to_mem_wdata__msg[8] = fu__to_mem_wdata__msg[8]; + assign fu__to_mem_wdata__rdy[8] = to_mem_wdata__rdy[8]; + assign to_mem_wdata__val[8] = fu__to_mem_wdata__val[8]; + assign fu__clear[8] = clear[8]; + assign to_mem_raddr__msg[9] = fu__to_mem_raddr__msg[9]; + assign fu__to_mem_raddr__rdy[9] = to_mem_raddr__rdy[9]; + assign to_mem_raddr__val[9] = fu__to_mem_raddr__val[9]; + assign fu__from_mem_rdata__msg[9] = from_mem_rdata__msg[9]; + assign from_mem_rdata__rdy[9] = fu__from_mem_rdata__rdy[9]; + assign fu__from_mem_rdata__val[9] = from_mem_rdata__val[9]; + assign to_mem_waddr__msg[9] = fu__to_mem_waddr__msg[9]; + assign fu__to_mem_waddr__rdy[9] = to_mem_waddr__rdy[9]; + assign to_mem_waddr__val[9] = fu__to_mem_waddr__val[9]; + assign to_mem_wdata__msg[9] = fu__to_mem_wdata__msg[9]; + assign fu__to_mem_wdata__rdy[9] = to_mem_wdata__rdy[9]; + assign to_mem_wdata__val[9] = fu__to_mem_wdata__val[9]; + assign fu__clear[9] = clear[9]; + assign to_mem_raddr__msg[10] = fu__to_mem_raddr__msg[10]; + assign fu__to_mem_raddr__rdy[10] = to_mem_raddr__rdy[10]; + assign to_mem_raddr__val[10] = fu__to_mem_raddr__val[10]; + assign fu__from_mem_rdata__msg[10] = from_mem_rdata__msg[10]; + assign from_mem_rdata__rdy[10] = fu__from_mem_rdata__rdy[10]; + assign fu__from_mem_rdata__val[10] = from_mem_rdata__val[10]; + assign to_mem_waddr__msg[10] = fu__to_mem_waddr__msg[10]; + assign fu__to_mem_waddr__rdy[10] = to_mem_waddr__rdy[10]; + assign to_mem_waddr__val[10] = fu__to_mem_waddr__val[10]; + assign to_mem_wdata__msg[10] = fu__to_mem_wdata__msg[10]; + assign fu__to_mem_wdata__rdy[10] = to_mem_wdata__rdy[10]; + assign to_mem_wdata__val[10] = fu__to_mem_wdata__val[10]; + assign fu__clear[10] = clear[10]; + assign to_mem_raddr__msg[11] = fu__to_mem_raddr__msg[11]; + assign fu__to_mem_raddr__rdy[11] = to_mem_raddr__rdy[11]; + assign to_mem_raddr__val[11] = fu__to_mem_raddr__val[11]; + assign fu__from_mem_rdata__msg[11] = from_mem_rdata__msg[11]; + assign from_mem_rdata__rdy[11] = fu__from_mem_rdata__rdy[11]; + assign fu__from_mem_rdata__val[11] = from_mem_rdata__val[11]; + assign to_mem_waddr__msg[11] = fu__to_mem_waddr__msg[11]; + assign fu__to_mem_waddr__rdy[11] = to_mem_waddr__rdy[11]; + assign to_mem_waddr__val[11] = fu__to_mem_waddr__val[11]; + assign to_mem_wdata__msg[11] = fu__to_mem_wdata__msg[11]; + assign fu__to_mem_wdata__rdy[11] = to_mem_wdata__rdy[11]; + assign to_mem_wdata__val[11] = fu__to_mem_wdata__val[11]; + assign fu__clear[11] = clear[11]; + assign to_mem_raddr__msg[12] = fu__to_mem_raddr__msg[12]; + assign fu__to_mem_raddr__rdy[12] = to_mem_raddr__rdy[12]; + assign to_mem_raddr__val[12] = fu__to_mem_raddr__val[12]; + assign fu__from_mem_rdata__msg[12] = from_mem_rdata__msg[12]; + assign from_mem_rdata__rdy[12] = fu__from_mem_rdata__rdy[12]; + assign fu__from_mem_rdata__val[12] = from_mem_rdata__val[12]; + assign to_mem_waddr__msg[12] = fu__to_mem_waddr__msg[12]; + assign fu__to_mem_waddr__rdy[12] = to_mem_waddr__rdy[12]; + assign to_mem_waddr__val[12] = fu__to_mem_waddr__val[12]; + assign to_mem_wdata__msg[12] = fu__to_mem_wdata__msg[12]; + assign fu__to_mem_wdata__rdy[12] = to_mem_wdata__rdy[12]; + assign to_mem_wdata__val[12] = fu__to_mem_wdata__val[12]; + assign fu__clear[12] = clear[12]; + assign to_mem_raddr__msg[13] = fu__to_mem_raddr__msg[13]; + assign fu__to_mem_raddr__rdy[13] = to_mem_raddr__rdy[13]; + assign to_mem_raddr__val[13] = fu__to_mem_raddr__val[13]; + assign fu__from_mem_rdata__msg[13] = from_mem_rdata__msg[13]; + assign from_mem_rdata__rdy[13] = fu__from_mem_rdata__rdy[13]; + assign fu__from_mem_rdata__val[13] = from_mem_rdata__val[13]; + assign to_mem_waddr__msg[13] = fu__to_mem_waddr__msg[13]; + assign fu__to_mem_waddr__rdy[13] = to_mem_waddr__rdy[13]; + assign to_mem_waddr__val[13] = fu__to_mem_waddr__val[13]; + assign to_mem_wdata__msg[13] = fu__to_mem_wdata__msg[13]; + assign fu__to_mem_wdata__rdy[13] = to_mem_wdata__rdy[13]; + assign to_mem_wdata__val[13] = fu__to_mem_wdata__val[13]; + assign fu__clear[13] = clear[13]; + assign to_mem_raddr__msg[14] = fu__to_mem_raddr__msg[14]; + assign fu__to_mem_raddr__rdy[14] = to_mem_raddr__rdy[14]; + assign to_mem_raddr__val[14] = fu__to_mem_raddr__val[14]; + assign fu__from_mem_rdata__msg[14] = from_mem_rdata__msg[14]; + assign from_mem_rdata__rdy[14] = fu__from_mem_rdata__rdy[14]; + assign fu__from_mem_rdata__val[14] = from_mem_rdata__val[14]; + assign to_mem_waddr__msg[14] = fu__to_mem_waddr__msg[14]; + assign fu__to_mem_waddr__rdy[14] = to_mem_waddr__rdy[14]; + assign to_mem_waddr__val[14] = fu__to_mem_waddr__val[14]; + assign to_mem_wdata__msg[14] = fu__to_mem_wdata__msg[14]; + assign fu__to_mem_wdata__rdy[14] = to_mem_wdata__rdy[14]; + assign to_mem_wdata__val[14] = fu__to_mem_wdata__val[14]; + assign fu__clear[14] = clear[14]; + +endmodule + + +// PyMTL Component CrossbarRTL Definition +// Full name: CrossbarRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_2__num_outports_8__num_cgras_4__num_tiles_16__ctrl_mem_size_16__outport_towards_local_base_id_4 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py + +module CrossbarRTL__45ee026205c61975 +( + input logic [1:0] cgra_id , + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] compute_done , + input logic [0:0] crossbar_id , + input logic [1:0] crossbar_outport [0:7], + input logic [3:0] ctrl_addr_inport , + input logic [2:0] prologue_count_inport [0:15][0:1], + input logic [0:0] reset , + input logic [4:0] tile_id , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:1] , + output logic [0:0] recv_data__rdy [0:1] , + input logic [0:0] recv_data__val [0:1] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:7] , + input logic [0:0] send_data__rdy [0:7] , + output logic [0:0] send_data__val [0:7] +); + localparam logic [1:0] __const__num_inports_at_update_signal = 2'd2; + localparam logic [3:0] __const__num_outports_at_update_signal = 4'd8; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter = 5'd16; + localparam logic [1:0] __const__num_inports_at_update_prologue_counter = 2'd2; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter_next = 5'd16; + localparam logic [1:0] __const__num_inports_at_update_prologue_counter_next = 2'd2; + localparam logic [3:0] __const__num_outports_at_update_prologue_counter_next = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_prologue_allowing_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_prologue_or_valid_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_in_dir_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_rdy_vector = 4'd8; + localparam logic [2:0] __const__outport_towards_local_base_id_at_update_rdy_vector = 3'd4; + localparam logic [3:0] __const__num_outports_at_update_valid_vector = 4'd8; + localparam logic [1:0] __const__num_inports_at_update_recv_required_vector = 2'd2; + localparam logic [3:0] __const__num_outports_at_update_recv_required_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_send_required_vector = 4'd8; + logic [1:0] in_dir [0:7]; + logic [0:0] in_dir_local [0:7]; + logic [7:0] prologue_allowing_vector; + logic [2:0] prologue_count_wire [0:15][0:1]; + logic [2:0] prologue_counter [0:15][0:1]; + logic [2:0] prologue_counter_next [0:15][0:1]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_msg [0:1]; + logic [0:0] recv_data_val [0:1]; + logic [1:0] recv_required_vector; + logic [7:0] recv_valid_or_prologue_allowing_vector; + logic [7:0] recv_valid_vector; + logic [7:0] send_rdy_vector; + logic [7:0] send_required_vector; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:153 + // @update + // def update_in_dir_vector(): + // + // for i in range(num_outports): + // s.in_dir[i] @= 0 + // s.in_dir_local[i] @= 0 + // + // for i in range(num_outports): + // s.in_dir[i] @= s.crossbar_outport[i] + // if s.in_dir[i] > 0: + // s.in_dir_local[i] @= trunc(s.in_dir[i] - 1, NumInportType) + + always_comb begin : update_in_dir_vector + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin + in_dir[3'(i)] = 2'd0; + in_dir_local[3'(i)] = 1'd0; + end + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin + in_dir[3'(i)] = crossbar_outport[3'(i)]; + if ( in_dir[3'(i)] > 2'd0 ) begin + in_dir_local[3'(i)] = 1'(in_dir[3'(i)] - 2'd1); + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:134 + // @update + // def update_prologue_allowing_vector(): + // s.prologue_allowing_vector @= 0 + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // # Records whether the prologue steps have already been satisfied. + // s.prologue_allowing_vector[i] @= \ + // (s.prologue_counter[s.ctrl_addr_inport][s.in_dir_local[i]] < \ + // s.prologue_count_wire[s.ctrl_addr_inport][s.in_dir_local[i]]) + // else: + // s.prologue_allowing_vector[i] @= 1 + + always_comb begin : update_prologue_allowing_vector + prologue_allowing_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_allowing_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 2'd0 ) begin + prologue_allowing_vector[3'(i)] = prologue_counter[ctrl_addr_inport][in_dir_local[3'(i)]] < prologue_count_wire[ctrl_addr_inport][in_dir_local[3'(i)]]; + end + else + prologue_allowing_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:119 + // @update + // def update_prologue_counter_next(): + // # Nested-loop to update the prologue counter, to avoid dynamic indexing to + // # work-around Yosys issue: https://github.com/tancheng/VectorCGRA/issues/148 + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + // for j in range(num_outports): + // if s.recv_opt.rdy & \ + // (s.in_dir[j] > 0) & \ + // (s.in_dir_local[j] == i) & \ + // (addr == s.ctrl_addr_inport) & \ + // (s.prologue_counter[addr][i] < s.prologue_count_wire[addr][i]): + // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + 1 + + always_comb begin : update_prologue_counter_next + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter_next ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter_next ); i += 1'd1 ) begin + prologue_counter_next[4'(addr)][1'(i)] = prologue_counter[4'(addr)][1'(i)]; + for ( int unsigned j = 1'd0; j < 4'( __const__num_outports_at_update_prologue_counter_next ); j += 1'd1 ) + if ( ( ( ( recv_opt__rdy & ( in_dir[3'(j)] > 2'd0 ) ) & ( in_dir_local[3'(j)] == 1'(i) ) ) & ( 4'(addr) == ctrl_addr_inport ) ) & ( prologue_counter[4'(addr)][1'(i)] < prologue_count_wire[4'(addr)][1'(i)] ) ) begin + prologue_counter_next[4'(addr)][1'(i)] = prologue_counter[4'(addr)][1'(i)] + 3'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:146 + // @update + // def update_prologue_or_valid_vector(): + // s.recv_valid_or_prologue_allowing_vector @= 0 + // for i in range(num_outports): + // s.recv_valid_or_prologue_allowing_vector[i] @= \ + // s.recv_valid_vector[i] | s.prologue_allowing_vector[i] + + always_comb begin : update_prologue_or_valid_vector + recv_valid_or_prologue_allowing_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_or_valid_vector ); i += 1'd1 ) + recv_valid_or_prologue_allowing_vector[3'(i)] = recv_valid_vector[3'(i)] | prologue_allowing_vector[3'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:165 + // @update + // def update_rdy_vector(): + // s.send_rdy_vector @= 0 + // for i in range(num_outports): + // # The `num_inports` indicates the number of outports that go to other tiles. + // # Specifically, if the compute already done, we shouldn't care the ones + // # (i.e., i >= num_inports) go to the FU's inports. In other words, we skip + // # the rdy checking on the FU's inports (connecting from crossbar_outport) if + // # the compute is already completed. + // if (s.in_dir[i] > 0) & \ + // (~s.compute_done | (i < outport_towards_local_base_id)): + // s.send_rdy_vector[i] @= s.send_data[i].rdy + // else: + // s.send_rdy_vector[i] @= 1 + + always_comb begin : update_rdy_vector + send_rdy_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_rdy_vector ); i += 1'd1 ) + if ( ( in_dir[3'(i)] > 2'd0 ) & ( ( ~compute_done ) | ( 3'(i) < 3'( __const__outport_towards_local_base_id_at_update_rdy_vector ) ) ) ) begin + send_rdy_vector[3'(i)] = send_data__rdy[3'(i)]; + end + else + send_rdy_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:189 + // @update + // def update_recv_required_vector(): + // for i in range(num_inports): + // s.recv_required_vector[i] @= 0 + // + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.recv_required_vector[s.in_dir_local[i]] @= 1 + + always_comb begin : update_recv_required_vector + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_recv_required_vector ); i += 1'd1 ) + recv_required_vector[1'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_recv_required_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 2'd0 ) begin + recv_required_vector[in_dir_local[3'(i)]] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:198 + // @update + // def update_send_required_vector(): + // + // for i in range(num_outports): + // s.send_required_vector[i] @= 0 + // + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.send_required_vector[i] @= 1 + + always_comb begin : update_send_required_vector + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) + send_required_vector[3'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 2'd0 ) begin + send_required_vector[3'(i)] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:82 + // @update + // def update_signal(): + // for i in range(num_inports): + // s.recv_data[i].rdy @= 0 + // for i in range(num_outports): + // s.send_data[i].val @= 0 + // s.send_data[i].msg @= DataType() + // s.recv_opt.rdy @= 0 + // + // if s.recv_opt.val & (s.recv_opt.msg.operation != OPT_START): + // for i in range(num_inports): + // s.recv_data[i].rdy @= reduce_and(s.recv_valid_vector) & \ + // reduce_and(s.send_rdy_vector) & \ + // s.recv_required_vector[i] + // + // for i in range(num_outports): + // s.send_data[i].val @= reduce_and(s.recv_valid_vector) & \ + // s.send_required_vector[i] + // if reduce_and(s.recv_valid_vector) & \ + // s.send_required_vector[i]: + // s.send_data[i].msg.payload @= s.recv_data_msg[s.in_dir_local[i]].payload + // s.send_data[i].msg.predicate @= s.recv_data_msg[s.in_dir_local[i]].predicate + // + // s.recv_opt.rdy @= reduce_and(s.send_rdy_vector) & \ + // reduce_and(s.recv_valid_or_prologue_allowing_vector) + + always_comb begin : update_signal + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_signal ); i += 1'd1 ) + recv_data__rdy[1'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin + send_data__val[3'(i)] = 1'd0; + send_data__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_opt__rdy = 1'd0; + if ( recv_opt__val & ( recv_opt__msg.operation != 7'( __const__OPT_START ) ) ) begin + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_signal ); i += 1'd1 ) + recv_data__rdy[1'(i)] = ( ( & recv_valid_vector ) & ( & send_rdy_vector ) ) & recv_required_vector[1'(i)]; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin + send_data__val[3'(i)] = ( & recv_valid_vector ) & send_required_vector[3'(i)]; + if ( ( & recv_valid_vector ) & send_required_vector[3'(i)] ) begin + send_data__msg[3'(i)].payload = recv_data_msg[in_dir_local[3'(i)]].payload; + send_data__msg[3'(i)].predicate = recv_data_msg[in_dir_local[3'(i)]].predicate; + end + end + recv_opt__rdy = ( & send_rdy_vector ) & ( & recv_valid_or_prologue_allowing_vector ); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:180 + // @update + // def update_valid_vector(): + // s.recv_valid_vector @= 0 + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.recv_valid_vector[i] @= s.recv_data_val[s.in_dir_local[i]] + // else: + // s.recv_valid_vector[i] @= 1 + + always_comb begin : update_valid_vector + recv_valid_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_valid_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 2'd0 ) begin + recv_valid_vector[3'(i)] = recv_data_val[in_dir_local[3'(i)]]; + end + else + recv_valid_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:108 + // @update_ff + // def update_prologue_counter(): + // if s.reset | s.clear: + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter[addr][i] <<= 0 + // else: + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter[addr][i] <<= s.prologue_counter_next[addr][i] + + always_ff @(posedge clk) begin : update_prologue_counter + if ( reset | clear ) begin + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) + prologue_counter[4'(addr)][1'(i)] <= 3'd0; + end + else + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) + prologue_counter[4'(addr)][1'(i)] <= prologue_counter_next[4'(addr)][1'(i)]; + end + + assign recv_data_msg[0] = recv_data__msg[0]; + assign recv_data_val[0] = recv_data__val[0]; + assign recv_data_msg[1] = recv_data__msg[1]; + assign recv_data_val[1] = recv_data__val[1]; + assign prologue_count_wire[0][0] = prologue_count_inport[0][0]; + assign prologue_count_wire[0][1] = prologue_count_inport[0][1]; + assign prologue_count_wire[1][0] = prologue_count_inport[1][0]; + assign prologue_count_wire[1][1] = prologue_count_inport[1][1]; + assign prologue_count_wire[2][0] = prologue_count_inport[2][0]; + assign prologue_count_wire[2][1] = prologue_count_inport[2][1]; + assign prologue_count_wire[3][0] = prologue_count_inport[3][0]; + assign prologue_count_wire[3][1] = prologue_count_inport[3][1]; + assign prologue_count_wire[4][0] = prologue_count_inport[4][0]; + assign prologue_count_wire[4][1] = prologue_count_inport[4][1]; + assign prologue_count_wire[5][0] = prologue_count_inport[5][0]; + assign prologue_count_wire[5][1] = prologue_count_inport[5][1]; + assign prologue_count_wire[6][0] = prologue_count_inport[6][0]; + assign prologue_count_wire[6][1] = prologue_count_inport[6][1]; + assign prologue_count_wire[7][0] = prologue_count_inport[7][0]; + assign prologue_count_wire[7][1] = prologue_count_inport[7][1]; + assign prologue_count_wire[8][0] = prologue_count_inport[8][0]; + assign prologue_count_wire[8][1] = prologue_count_inport[8][1]; + assign prologue_count_wire[9][0] = prologue_count_inport[9][0]; + assign prologue_count_wire[9][1] = prologue_count_inport[9][1]; + assign prologue_count_wire[10][0] = prologue_count_inport[10][0]; + assign prologue_count_wire[10][1] = prologue_count_inport[10][1]; + assign prologue_count_wire[11][0] = prologue_count_inport[11][0]; + assign prologue_count_wire[11][1] = prologue_count_inport[11][1]; + assign prologue_count_wire[12][0] = prologue_count_inport[12][0]; + assign prologue_count_wire[12][1] = prologue_count_inport[12][1]; + assign prologue_count_wire[13][0] = prologue_count_inport[13][0]; + assign prologue_count_wire[13][1] = prologue_count_inport[13][1]; + assign prologue_count_wire[14][0] = prologue_count_inport[14][0]; + assign prologue_count_wire[14][1] = prologue_count_inport[14][1]; + assign prologue_count_wire[15][0] = prologue_count_inport[15][0]; + assign prologue_count_wire[15][1] = prologue_count_inport[15][1]; + +endmodule + + +// PyMTL Component RegisterBankRTL Definition +// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_0__num_registers_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py + +module RegisterBankRTL__649561e613f42979 +( + input logic [0:0] clk , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , + input logic [0:0] inport_valid [0:2], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], + input logic [0:0] reset , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , + input logic [0:0] send_data_to_fu__rdy , + output logic [0:0] send_data_to_fu__val +); + localparam logic [0:0] __const__reg_bank_id_at_access_registers = 1'd0; + localparam logic [0:0] __const__reg_bank_id_at_update_send_val = 1'd0; + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__bd22936ec5812d0d reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [1:0] __tmpvar__access_registers_write_reg_from; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 + // @update + // def access_registers(): + // # Initializes signals. + // s.reg_file.raddr[0] @= AddrType() + // s.send_data_to_fu.msg @= DataType() + // s.reg_file.waddr[0] @= AddrType() + // s.reg_file.wdata[0] @= DataType() + // s.reg_file.wen[0] @= 0 + // + // if s.inport_opt.read_reg_from[reg_bank_id]: + // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] + // s.send_data_to_fu.msg @= s.reg_file.rdata[0] + // + // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] + // if ~s.reset & (write_reg_from > 0): + // if s.inport_valid[write_reg_from - 1]: + // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] + // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] + // s.reg_file.wen[0] @= 1 + + always_comb begin : access_registers + reg_file__raddr[1'd0] = 4'd0; + send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__waddr[1'd0] = 4'd0; + reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__wen[1'd0] = 1'd0; + if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin + reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + send_data_to_fu__msg = reg_file__rdata[1'd0]; + end + __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; + if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin + if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin + reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; + reg_file__wen[1'd0] = 1'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 + // @update + // def update_send_val(): + // s.send_data_to_fu.val @= 0 + // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: + // s.send_data_to_fu.val @= 1 + + always_comb begin : update_send_val + send_data_to_fu__val = 1'd0; + if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin + send_data_to_fu__val = 1'd1; + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + +endmodule + + +// PyMTL Component RegisterBankRTL Definition +// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_1__num_registers_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py + +module RegisterBankRTL__0a5bdf408d921386 +( + input logic [0:0] clk , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , + input logic [0:0] inport_valid [0:2], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], + input logic [0:0] reset , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , + input logic [0:0] send_data_to_fu__rdy , + output logic [0:0] send_data_to_fu__val +); + localparam logic [0:0] __const__reg_bank_id_at_access_registers = 1'd1; + localparam logic [0:0] __const__reg_bank_id_at_update_send_val = 1'd1; + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__bd22936ec5812d0d reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [1:0] __tmpvar__access_registers_write_reg_from; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 + // @update + // def access_registers(): + // # Initializes signals. + // s.reg_file.raddr[0] @= AddrType() + // s.send_data_to_fu.msg @= DataType() + // s.reg_file.waddr[0] @= AddrType() + // s.reg_file.wdata[0] @= DataType() + // s.reg_file.wen[0] @= 0 + // + // if s.inport_opt.read_reg_from[reg_bank_id]: + // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] + // s.send_data_to_fu.msg @= s.reg_file.rdata[0] + // + // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] + // if ~s.reset & (write_reg_from > 0): + // if s.inport_valid[write_reg_from - 1]: + // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] + // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] + // s.reg_file.wen[0] @= 1 + + always_comb begin : access_registers + reg_file__raddr[1'd0] = 4'd0; + send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__waddr[1'd0] = 4'd0; + reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__wen[1'd0] = 1'd0; + if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin + reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + send_data_to_fu__msg = reg_file__rdata[1'd0]; + end + __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; + if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin + if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin + reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; + reg_file__wen[1'd0] = 1'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 + // @update + // def update_send_val(): + // s.send_data_to_fu.val @= 0 + // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: + // s.send_data_to_fu.val @= 1 + + always_comb begin : update_send_val + send_data_to_fu__val = 1'd0; + if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin + send_data_to_fu__val = 1'd1; + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + +endmodule + + +// PyMTL Component RegisterBankRTL Definition +// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_2__num_registers_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py + +module RegisterBankRTL__ddae41891d80e575 +( + input logic [0:0] clk , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , + input logic [0:0] inport_valid [0:2], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], + input logic [0:0] reset , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , + input logic [0:0] send_data_to_fu__rdy , + output logic [0:0] send_data_to_fu__val +); + localparam logic [1:0] __const__reg_bank_id_at_access_registers = 2'd2; + localparam logic [1:0] __const__reg_bank_id_at_update_send_val = 2'd2; + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__bd22936ec5812d0d reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [1:0] __tmpvar__access_registers_write_reg_from; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 + // @update + // def access_registers(): + // # Initializes signals. + // s.reg_file.raddr[0] @= AddrType() + // s.send_data_to_fu.msg @= DataType() + // s.reg_file.waddr[0] @= AddrType() + // s.reg_file.wdata[0] @= DataType() + // s.reg_file.wen[0] @= 0 + // + // if s.inport_opt.read_reg_from[reg_bank_id]: + // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] + // s.send_data_to_fu.msg @= s.reg_file.rdata[0] + // + // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] + // if ~s.reset & (write_reg_from > 0): + // if s.inport_valid[write_reg_from - 1]: + // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] + // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] + // s.reg_file.wen[0] @= 1 + + always_comb begin : access_registers + reg_file__raddr[1'd0] = 4'd0; + send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__waddr[1'd0] = 4'd0; + reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__wen[1'd0] = 1'd0; + if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin + reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + send_data_to_fu__msg = reg_file__rdata[1'd0]; + end + __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; + if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin + if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin + reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; + reg_file__wen[1'd0] = 1'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 + // @update + // def update_send_val(): + // s.send_data_to_fu.val @= 0 + // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: + // s.send_data_to_fu.val @= 1 + + always_comb begin : update_send_val + send_data_to_fu__val = 1'd0; + if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin + send_data_to_fu__val = 1'd1; + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + +endmodule + + +// PyMTL Component RegisterBankRTL Definition +// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_3__num_registers_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py + +module RegisterBankRTL__ff0588d25abf2ed3 +( + input logic [0:0] clk , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , + input logic [0:0] inport_valid [0:2], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], + input logic [0:0] reset , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , + input logic [0:0] send_data_to_fu__rdy , + output logic [0:0] send_data_to_fu__val +); + localparam logic [1:0] __const__reg_bank_id_at_access_registers = 2'd3; + localparam logic [1:0] __const__reg_bank_id_at_update_send_val = 2'd3; + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__bd22936ec5812d0d reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [1:0] __tmpvar__access_registers_write_reg_from; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 + // @update + // def access_registers(): + // # Initializes signals. + // s.reg_file.raddr[0] @= AddrType() + // s.send_data_to_fu.msg @= DataType() + // s.reg_file.waddr[0] @= AddrType() + // s.reg_file.wdata[0] @= DataType() + // s.reg_file.wen[0] @= 0 + // + // if s.inport_opt.read_reg_from[reg_bank_id]: + // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] + // s.send_data_to_fu.msg @= s.reg_file.rdata[0] + // + // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] + // if ~s.reset & (write_reg_from > 0): + // if s.inport_valid[write_reg_from - 1]: + // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] + // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] + // s.reg_file.wen[0] @= 1 + + always_comb begin : access_registers + reg_file__raddr[1'd0] = 4'd0; + send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__waddr[1'd0] = 4'd0; + reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__wen[1'd0] = 1'd0; + if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin + reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + send_data_to_fu__msg = reg_file__rdata[1'd0]; + end + __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; + if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin + if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin + reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; + reg_file__wen[1'd0] = 1'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 + // @update + // def update_send_val(): + // s.send_data_to_fu.val @= 0 + // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: + // s.send_data_to_fu.val @= 1 + + always_comb begin : update_send_val + send_data_to_fu__val = 1'd0; + if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin + send_data_to_fu__val = 1'd1; + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + +endmodule + + +// PyMTL Component RegisterClusterRTL Definition +// Full name: RegisterClusterRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_reg_banks_4__num_registers_per_reg_bank_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterClusterRTL.py + +module RegisterClusterRTL__7f2febb613462546 +( + input logic [0:0] clk , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_const__msg [0:3] , + output logic [0:0] recv_data_from_const__rdy [0:3] , + input logic [0:0] recv_data_from_const__val [0:3] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_fu_crossbar__msg [0:3] , + output logic [0:0] recv_data_from_fu_crossbar__rdy [0:3] , + input logic [0:0] recv_data_from_fu_crossbar__val [0:3] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_routing_crossbar__msg [0:3] , + output logic [0:0] recv_data_from_routing_crossbar__rdy [0:3] , + input logic [0:0] recv_data_from_routing_crossbar__val [0:3] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg [0:3] , + input logic [0:0] send_data_to_fu__rdy [0:3] , + output logic [0:0] send_data_to_fu__val [0:3] +); + localparam logic [2:0] __const__num_reg_banks_at_update_msgs_signals = 3'd4; + //------------------------------------------------------------- + // Component reg_bank[0:3] + //------------------------------------------------------------- + + logic [0:0] reg_bank__clk [0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_bank__inport_opt [0:3]; + logic [0:0] reg_bank__inport_valid [0:3][0:2]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_bank__inport_wdata [0:3][0:2]; + logic [0:0] reg_bank__reset [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_bank__send_data_to_fu__msg [0:3]; + logic [0:0] reg_bank__send_data_to_fu__rdy [0:3]; + logic [0:0] reg_bank__send_data_to_fu__val [0:3]; + + RegisterBankRTL__649561e613f42979 reg_bank__0 + ( + .clk( reg_bank__clk[0] ), + .inport_opt( reg_bank__inport_opt[0] ), + .inport_valid( reg_bank__inport_valid[0] ), + .inport_wdata( reg_bank__inport_wdata[0] ), + .reset( reg_bank__reset[0] ), + .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[0] ), + .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[0] ), + .send_data_to_fu__val( reg_bank__send_data_to_fu__val[0] ) + ); + + RegisterBankRTL__0a5bdf408d921386 reg_bank__1 + ( + .clk( reg_bank__clk[1] ), + .inport_opt( reg_bank__inport_opt[1] ), + .inport_valid( reg_bank__inport_valid[1] ), + .inport_wdata( reg_bank__inport_wdata[1] ), + .reset( reg_bank__reset[1] ), + .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[1] ), + .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[1] ), + .send_data_to_fu__val( reg_bank__send_data_to_fu__val[1] ) + ); + + RegisterBankRTL__ddae41891d80e575 reg_bank__2 + ( + .clk( reg_bank__clk[2] ), + .inport_opt( reg_bank__inport_opt[2] ), + .inport_valid( reg_bank__inport_valid[2] ), + .inport_wdata( reg_bank__inport_wdata[2] ), + .reset( reg_bank__reset[2] ), + .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[2] ), + .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[2] ), + .send_data_to_fu__val( reg_bank__send_data_to_fu__val[2] ) + ); + + RegisterBankRTL__ff0588d25abf2ed3 reg_bank__3 + ( + .clk( reg_bank__clk[3] ), + .inport_opt( reg_bank__inport_opt[3] ), + .inport_valid( reg_bank__inport_valid[3] ), + .inport_wdata( reg_bank__inport_wdata[3] ), + .reset( reg_bank__reset[3] ), + .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[3] ), + .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[3] ), + .send_data_to_fu__val( reg_bank__send_data_to_fu__val[3] ) + ); + + //------------------------------------------------------------- + // End of component reg_bank[0:3] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterClusterRTL.py:45 + // @update + // def update_msgs_signals(): + // # Initializes signals. + // for i in range(num_reg_banks): + // s.send_data_to_fu[i].msg @= DataType() + // s.recv_data_from_routing_crossbar[i].rdy @= 0 + // s.recv_data_from_fu_crossbar[i].rdy @= 0 + // s.recv_data_from_const[i].rdy @= 0 + // s.send_data_to_fu[i].val @= 0 + // + // for i in range(num_reg_banks): + // if s.recv_data_from_routing_crossbar[i].val: + // s.send_data_to_fu[i].msg @= \ + // s.recv_data_from_routing_crossbar[i].msg + // else: + // s.send_data_to_fu[i].msg @= \ + // s.reg_bank[i].send_data_to_fu.msg + // + // s.send_data_to_fu[i].val @= \ + // s.recv_data_from_routing_crossbar[i].val | \ + // s.reg_bank[i].send_data_to_fu.val + // s.reg_bank[i].send_data_to_fu.rdy @= s.send_data_to_fu[i].rdy + // + // s.recv_data_from_routing_crossbar[i].rdy @= s.send_data_to_fu[i].rdy + // s.recv_data_from_fu_crossbar[i].rdy @= 1 + // s.recv_data_from_const[i].rdy @= 1 + + always_comb begin : update_msgs_signals + for ( int unsigned i = 1'd0; i < 3'( __const__num_reg_banks_at_update_msgs_signals ); i += 1'd1 ) begin + send_data_to_fu__msg[2'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + recv_data_from_routing_crossbar__rdy[2'(i)] = 1'd0; + recv_data_from_fu_crossbar__rdy[2'(i)] = 1'd0; + recv_data_from_const__rdy[2'(i)] = 1'd0; + send_data_to_fu__val[2'(i)] = 1'd0; + end + for ( int unsigned i = 1'd0; i < 3'( __const__num_reg_banks_at_update_msgs_signals ); i += 1'd1 ) begin + if ( recv_data_from_routing_crossbar__val[2'(i)] ) begin + send_data_to_fu__msg[2'(i)] = recv_data_from_routing_crossbar__msg[2'(i)]; + end + else + send_data_to_fu__msg[2'(i)] = reg_bank__send_data_to_fu__msg[2'(i)]; + send_data_to_fu__val[2'(i)] = recv_data_from_routing_crossbar__val[2'(i)] | reg_bank__send_data_to_fu__val[2'(i)]; + reg_bank__send_data_to_fu__rdy[2'(i)] = send_data_to_fu__rdy[2'(i)]; + recv_data_from_routing_crossbar__rdy[2'(i)] = send_data_to_fu__rdy[2'(i)]; + recv_data_from_fu_crossbar__rdy[2'(i)] = 1'd1; + recv_data_from_const__rdy[2'(i)] = 1'd1; + end + end + + assign reg_bank__clk[0] = clk; + assign reg_bank__reset[0] = reset; + assign reg_bank__clk[1] = clk; + assign reg_bank__reset[1] = reset; + assign reg_bank__clk[2] = clk; + assign reg_bank__reset[2] = reset; + assign reg_bank__clk[3] = clk; + assign reg_bank__reset[3] = reset; + assign reg_bank__inport_opt[0] = inport_opt; + assign reg_bank__inport_wdata[0][0] = recv_data_from_routing_crossbar__msg[0]; + assign reg_bank__inport_wdata[0][1] = recv_data_from_fu_crossbar__msg[0]; + assign reg_bank__inport_wdata[0][2] = recv_data_from_const__msg[0]; + assign reg_bank__inport_valid[0][0] = recv_data_from_routing_crossbar__val[0]; + assign reg_bank__inport_valid[0][1] = recv_data_from_fu_crossbar__val[0]; + assign reg_bank__inport_valid[0][2] = recv_data_from_const__val[0]; + assign reg_bank__inport_opt[1] = inport_opt; + assign reg_bank__inport_wdata[1][0] = recv_data_from_routing_crossbar__msg[1]; + assign reg_bank__inport_wdata[1][1] = recv_data_from_fu_crossbar__msg[1]; + assign reg_bank__inport_wdata[1][2] = recv_data_from_const__msg[1]; + assign reg_bank__inport_valid[1][0] = recv_data_from_routing_crossbar__val[1]; + assign reg_bank__inport_valid[1][1] = recv_data_from_fu_crossbar__val[1]; + assign reg_bank__inport_valid[1][2] = recv_data_from_const__val[1]; + assign reg_bank__inport_opt[2] = inport_opt; + assign reg_bank__inport_wdata[2][0] = recv_data_from_routing_crossbar__msg[2]; + assign reg_bank__inport_wdata[2][1] = recv_data_from_fu_crossbar__msg[2]; + assign reg_bank__inport_wdata[2][2] = recv_data_from_const__msg[2]; + assign reg_bank__inport_valid[2][0] = recv_data_from_routing_crossbar__val[2]; + assign reg_bank__inport_valid[2][1] = recv_data_from_fu_crossbar__val[2]; + assign reg_bank__inport_valid[2][2] = recv_data_from_const__val[2]; + assign reg_bank__inport_opt[3] = inport_opt; + assign reg_bank__inport_wdata[3][0] = recv_data_from_routing_crossbar__msg[3]; + assign reg_bank__inport_wdata[3][1] = recv_data_from_fu_crossbar__msg[3]; + assign reg_bank__inport_wdata[3][2] = recv_data_from_const__msg[3]; + assign reg_bank__inport_valid[3][0] = recv_data_from_routing_crossbar__val[3]; + assign reg_bank__inport_valid[3][1] = recv_data_from_fu_crossbar__val[3]; + assign reg_bank__inport_valid[3][2] = recv_data_from_const__val[3]; + +endmodule + + +// PyMTL Component CrossbarRTL Definition +// Full name: CrossbarRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_8__num_cgras_4__num_tiles_16__ctrl_mem_size_16__outport_towards_local_base_id_4 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py + +module CrossbarRTL__cad4150dfdc32fbd +( + input logic [1:0] cgra_id , + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] compute_done , + input logic [0:0] crossbar_id , + input logic [2:0] crossbar_outport [0:7], + input logic [3:0] ctrl_addr_inport , + input logic [2:0] prologue_count_inport [0:15][0:3], + input logic [0:0] reset , + input logic [4:0] tile_id , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:3] , + output logic [0:0] recv_data__rdy [0:3] , + input logic [0:0] recv_data__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:7] , + input logic [0:0] send_data__rdy [0:7] , + output logic [0:0] send_data__val [0:7] +); + localparam logic [2:0] __const__num_inports_at_update_signal = 3'd4; + localparam logic [3:0] __const__num_outports_at_update_signal = 4'd8; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter = 5'd16; + localparam logic [2:0] __const__num_inports_at_update_prologue_counter = 3'd4; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter_next = 5'd16; + localparam logic [2:0] __const__num_inports_at_update_prologue_counter_next = 3'd4; + localparam logic [3:0] __const__num_outports_at_update_prologue_counter_next = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_prologue_allowing_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_prologue_or_valid_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_in_dir_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_rdy_vector = 4'd8; + localparam logic [2:0] __const__outport_towards_local_base_id_at_update_rdy_vector = 3'd4; + localparam logic [3:0] __const__num_outports_at_update_valid_vector = 4'd8; + localparam logic [2:0] __const__num_inports_at_update_recv_required_vector = 3'd4; + localparam logic [3:0] __const__num_outports_at_update_recv_required_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_send_required_vector = 4'd8; + logic [2:0] in_dir [0:7]; + logic [1:0] in_dir_local [0:7]; + logic [7:0] prologue_allowing_vector; + logic [2:0] prologue_count_wire [0:15][0:3]; + logic [2:0] prologue_counter [0:15][0:3]; + logic [2:0] prologue_counter_next [0:15][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_msg [0:3]; + logic [0:0] recv_data_val [0:3]; + logic [3:0] recv_required_vector; + logic [7:0] recv_valid_or_prologue_allowing_vector; + logic [7:0] recv_valid_vector; + logic [7:0] send_rdy_vector; + logic [7:0] send_required_vector; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:153 + // @update + // def update_in_dir_vector(): + // + // for i in range(num_outports): + // s.in_dir[i] @= 0 + // s.in_dir_local[i] @= 0 + // + // for i in range(num_outports): + // s.in_dir[i] @= s.crossbar_outport[i] + // if s.in_dir[i] > 0: + // s.in_dir_local[i] @= trunc(s.in_dir[i] - 1, NumInportType) + + always_comb begin : update_in_dir_vector + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin + in_dir[3'(i)] = 3'd0; + in_dir_local[3'(i)] = 2'd0; + end + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin + in_dir[3'(i)] = crossbar_outport[3'(i)]; + if ( in_dir[3'(i)] > 3'd0 ) begin + in_dir_local[3'(i)] = 2'(in_dir[3'(i)] - 3'd1); + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:134 + // @update + // def update_prologue_allowing_vector(): + // s.prologue_allowing_vector @= 0 + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // # Records whether the prologue steps have already been satisfied. + // s.prologue_allowing_vector[i] @= \ + // (s.prologue_counter[s.ctrl_addr_inport][s.in_dir_local[i]] < \ + // s.prologue_count_wire[s.ctrl_addr_inport][s.in_dir_local[i]]) + // else: + // s.prologue_allowing_vector[i] @= 1 + + always_comb begin : update_prologue_allowing_vector + prologue_allowing_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_allowing_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 3'd0 ) begin + prologue_allowing_vector[3'(i)] = prologue_counter[ctrl_addr_inport][in_dir_local[3'(i)]] < prologue_count_wire[ctrl_addr_inport][in_dir_local[3'(i)]]; + end + else + prologue_allowing_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:119 + // @update + // def update_prologue_counter_next(): + // # Nested-loop to update the prologue counter, to avoid dynamic indexing to + // # work-around Yosys issue: https://github.com/tancheng/VectorCGRA/issues/148 + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + // for j in range(num_outports): + // if s.recv_opt.rdy & \ + // (s.in_dir[j] > 0) & \ + // (s.in_dir_local[j] == i) & \ + // (addr == s.ctrl_addr_inport) & \ + // (s.prologue_counter[addr][i] < s.prologue_count_wire[addr][i]): + // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + 1 + + always_comb begin : update_prologue_counter_next + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter_next ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter_next ); i += 1'd1 ) begin + prologue_counter_next[4'(addr)][2'(i)] = prologue_counter[4'(addr)][2'(i)]; + for ( int unsigned j = 1'd0; j < 4'( __const__num_outports_at_update_prologue_counter_next ); j += 1'd1 ) + if ( ( ( ( recv_opt__rdy & ( in_dir[3'(j)] > 3'd0 ) ) & ( in_dir_local[3'(j)] == 2'(i) ) ) & ( 4'(addr) == ctrl_addr_inport ) ) & ( prologue_counter[4'(addr)][2'(i)] < prologue_count_wire[4'(addr)][2'(i)] ) ) begin + prologue_counter_next[4'(addr)][2'(i)] = prologue_counter[4'(addr)][2'(i)] + 3'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:146 + // @update + // def update_prologue_or_valid_vector(): + // s.recv_valid_or_prologue_allowing_vector @= 0 + // for i in range(num_outports): + // s.recv_valid_or_prologue_allowing_vector[i] @= \ + // s.recv_valid_vector[i] | s.prologue_allowing_vector[i] + + always_comb begin : update_prologue_or_valid_vector + recv_valid_or_prologue_allowing_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_or_valid_vector ); i += 1'd1 ) + recv_valid_or_prologue_allowing_vector[3'(i)] = recv_valid_vector[3'(i)] | prologue_allowing_vector[3'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:165 + // @update + // def update_rdy_vector(): + // s.send_rdy_vector @= 0 + // for i in range(num_outports): + // # The `num_inports` indicates the number of outports that go to other tiles. + // # Specifically, if the compute already done, we shouldn't care the ones + // # (i.e., i >= num_inports) go to the FU's inports. In other words, we skip + // # the rdy checking on the FU's inports (connecting from crossbar_outport) if + // # the compute is already completed. + // if (s.in_dir[i] > 0) & \ + // (~s.compute_done | (i < outport_towards_local_base_id)): + // s.send_rdy_vector[i] @= s.send_data[i].rdy + // else: + // s.send_rdy_vector[i] @= 1 + + always_comb begin : update_rdy_vector + send_rdy_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_rdy_vector ); i += 1'd1 ) + if ( ( in_dir[3'(i)] > 3'd0 ) & ( ( ~compute_done ) | ( 3'(i) < 3'( __const__outport_towards_local_base_id_at_update_rdy_vector ) ) ) ) begin + send_rdy_vector[3'(i)] = send_data__rdy[3'(i)]; + end + else + send_rdy_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:189 + // @update + // def update_recv_required_vector(): + // for i in range(num_inports): + // s.recv_required_vector[i] @= 0 + // + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.recv_required_vector[s.in_dir_local[i]] @= 1 + + always_comb begin : update_recv_required_vector + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_recv_required_vector ); i += 1'd1 ) + recv_required_vector[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_recv_required_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 3'd0 ) begin + recv_required_vector[in_dir_local[3'(i)]] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:198 + // @update + // def update_send_required_vector(): + // + // for i in range(num_outports): + // s.send_required_vector[i] @= 0 + // + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.send_required_vector[i] @= 1 + + always_comb begin : update_send_required_vector + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) + send_required_vector[3'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 3'd0 ) begin + send_required_vector[3'(i)] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:82 + // @update + // def update_signal(): + // for i in range(num_inports): + // s.recv_data[i].rdy @= 0 + // for i in range(num_outports): + // s.send_data[i].val @= 0 + // s.send_data[i].msg @= DataType() + // s.recv_opt.rdy @= 0 + // + // if s.recv_opt.val & (s.recv_opt.msg.operation != OPT_START): + // for i in range(num_inports): + // s.recv_data[i].rdy @= reduce_and(s.recv_valid_vector) & \ + // reduce_and(s.send_rdy_vector) & \ + // s.recv_required_vector[i] + // + // for i in range(num_outports): + // s.send_data[i].val @= reduce_and(s.recv_valid_vector) & \ + // s.send_required_vector[i] + // if reduce_and(s.recv_valid_vector) & \ + // s.send_required_vector[i]: + // s.send_data[i].msg.payload @= s.recv_data_msg[s.in_dir_local[i]].payload + // s.send_data[i].msg.predicate @= s.recv_data_msg[s.in_dir_local[i]].predicate + // + // s.recv_opt.rdy @= reduce_and(s.send_rdy_vector) & \ + // reduce_and(s.recv_valid_or_prologue_allowing_vector) + + always_comb begin : update_signal + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) + recv_data__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin + send_data__val[3'(i)] = 1'd0; + send_data__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_opt__rdy = 1'd0; + if ( recv_opt__val & ( recv_opt__msg.operation != 7'( __const__OPT_START ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) + recv_data__rdy[2'(i)] = ( ( & recv_valid_vector ) & ( & send_rdy_vector ) ) & recv_required_vector[2'(i)]; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin + send_data__val[3'(i)] = ( & recv_valid_vector ) & send_required_vector[3'(i)]; + if ( ( & recv_valid_vector ) & send_required_vector[3'(i)] ) begin + send_data__msg[3'(i)].payload = recv_data_msg[in_dir_local[3'(i)]].payload; + send_data__msg[3'(i)].predicate = recv_data_msg[in_dir_local[3'(i)]].predicate; + end + end + recv_opt__rdy = ( & send_rdy_vector ) & ( & recv_valid_or_prologue_allowing_vector ); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:180 + // @update + // def update_valid_vector(): + // s.recv_valid_vector @= 0 + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.recv_valid_vector[i] @= s.recv_data_val[s.in_dir_local[i]] + // else: + // s.recv_valid_vector[i] @= 1 + + always_comb begin : update_valid_vector + recv_valid_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_valid_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 3'd0 ) begin + recv_valid_vector[3'(i)] = recv_data_val[in_dir_local[3'(i)]]; + end + else + recv_valid_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:108 + // @update_ff + // def update_prologue_counter(): + // if s.reset | s.clear: + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter[addr][i] <<= 0 + // else: + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter[addr][i] <<= s.prologue_counter_next[addr][i] + + always_ff @(posedge clk) begin : update_prologue_counter + if ( reset | clear ) begin + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) + prologue_counter[4'(addr)][2'(i)] <= 3'd0; + end + else + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) + prologue_counter[4'(addr)][2'(i)] <= prologue_counter_next[4'(addr)][2'(i)]; + end + + assign recv_data_msg[0] = recv_data__msg[0]; + assign recv_data_val[0] = recv_data__val[0]; + assign recv_data_msg[1] = recv_data__msg[1]; + assign recv_data_val[1] = recv_data__val[1]; + assign recv_data_msg[2] = recv_data__msg[2]; + assign recv_data_val[2] = recv_data__val[2]; + assign recv_data_msg[3] = recv_data__msg[3]; + assign recv_data_val[3] = recv_data__val[3]; + assign prologue_count_wire[0][0] = prologue_count_inport[0][0]; + assign prologue_count_wire[0][1] = prologue_count_inport[0][1]; + assign prologue_count_wire[0][2] = prologue_count_inport[0][2]; + assign prologue_count_wire[0][3] = prologue_count_inport[0][3]; + assign prologue_count_wire[1][0] = prologue_count_inport[1][0]; + assign prologue_count_wire[1][1] = prologue_count_inport[1][1]; + assign prologue_count_wire[1][2] = prologue_count_inport[1][2]; + assign prologue_count_wire[1][3] = prologue_count_inport[1][3]; + assign prologue_count_wire[2][0] = prologue_count_inport[2][0]; + assign prologue_count_wire[2][1] = prologue_count_inport[2][1]; + assign prologue_count_wire[2][2] = prologue_count_inport[2][2]; + assign prologue_count_wire[2][3] = prologue_count_inport[2][3]; + assign prologue_count_wire[3][0] = prologue_count_inport[3][0]; + assign prologue_count_wire[3][1] = prologue_count_inport[3][1]; + assign prologue_count_wire[3][2] = prologue_count_inport[3][2]; + assign prologue_count_wire[3][3] = prologue_count_inport[3][3]; + assign prologue_count_wire[4][0] = prologue_count_inport[4][0]; + assign prologue_count_wire[4][1] = prologue_count_inport[4][1]; + assign prologue_count_wire[4][2] = prologue_count_inport[4][2]; + assign prologue_count_wire[4][3] = prologue_count_inport[4][3]; + assign prologue_count_wire[5][0] = prologue_count_inport[5][0]; + assign prologue_count_wire[5][1] = prologue_count_inport[5][1]; + assign prologue_count_wire[5][2] = prologue_count_inport[5][2]; + assign prologue_count_wire[5][3] = prologue_count_inport[5][3]; + assign prologue_count_wire[6][0] = prologue_count_inport[6][0]; + assign prologue_count_wire[6][1] = prologue_count_inport[6][1]; + assign prologue_count_wire[6][2] = prologue_count_inport[6][2]; + assign prologue_count_wire[6][3] = prologue_count_inport[6][3]; + assign prologue_count_wire[7][0] = prologue_count_inport[7][0]; + assign prologue_count_wire[7][1] = prologue_count_inport[7][1]; + assign prologue_count_wire[7][2] = prologue_count_inport[7][2]; + assign prologue_count_wire[7][3] = prologue_count_inport[7][3]; + assign prologue_count_wire[8][0] = prologue_count_inport[8][0]; + assign prologue_count_wire[8][1] = prologue_count_inport[8][1]; + assign prologue_count_wire[8][2] = prologue_count_inport[8][2]; + assign prologue_count_wire[8][3] = prologue_count_inport[8][3]; + assign prologue_count_wire[9][0] = prologue_count_inport[9][0]; + assign prologue_count_wire[9][1] = prologue_count_inport[9][1]; + assign prologue_count_wire[9][2] = prologue_count_inport[9][2]; + assign prologue_count_wire[9][3] = prologue_count_inport[9][3]; + assign prologue_count_wire[10][0] = prologue_count_inport[10][0]; + assign prologue_count_wire[10][1] = prologue_count_inport[10][1]; + assign prologue_count_wire[10][2] = prologue_count_inport[10][2]; + assign prologue_count_wire[10][3] = prologue_count_inport[10][3]; + assign prologue_count_wire[11][0] = prologue_count_inport[11][0]; + assign prologue_count_wire[11][1] = prologue_count_inport[11][1]; + assign prologue_count_wire[11][2] = prologue_count_inport[11][2]; + assign prologue_count_wire[11][3] = prologue_count_inport[11][3]; + assign prologue_count_wire[12][0] = prologue_count_inport[12][0]; + assign prologue_count_wire[12][1] = prologue_count_inport[12][1]; + assign prologue_count_wire[12][2] = prologue_count_inport[12][2]; + assign prologue_count_wire[12][3] = prologue_count_inport[12][3]; + assign prologue_count_wire[13][0] = prologue_count_inport[13][0]; + assign prologue_count_wire[13][1] = prologue_count_inport[13][1]; + assign prologue_count_wire[13][2] = prologue_count_inport[13][2]; + assign prologue_count_wire[13][3] = prologue_count_inport[13][3]; + assign prologue_count_wire[14][0] = prologue_count_inport[14][0]; + assign prologue_count_wire[14][1] = prologue_count_inport[14][1]; + assign prologue_count_wire[14][2] = prologue_count_inport[14][2]; + assign prologue_count_wire[14][3] = prologue_count_inport[14][3]; + assign prologue_count_wire[15][0] = prologue_count_inport[15][0]; + assign prologue_count_wire[15][1] = prologue_count_inport[15][1]; + assign prologue_count_wire[15][2] = prologue_count_inport[15][2]; + assign prologue_count_wire[15][3] = prologue_count_inport[15][3]; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__684a25db9dbebdb9 +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__43c9394e24dc368f +( + input logic [0:0] clk , + input logic [0:0] raddr , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_msg , + input logic [0:0] reset , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__684a25db9dbebdb9 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__43c9394e24dc368f +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__raddr; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 dpath__recv_msg; + logic [0:0] dpath__reset; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__43c9394e24dc368f dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component ChannelRTL Definition +// Full name: ChannelRTL__PacketType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__QueueType_NormalQueueRTL__latency_1 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py + +module ChannelRTL__694d252f21ac798b +( + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queues[0:0] + //------------------------------------------------------------- + + logic [0:0] queues__clk [0:0]; + logic [1:0] queues__count [0:0]; + logic [0:0] queues__reset [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 queues__recv__msg [0:0]; + logic [0:0] queues__recv__rdy [0:0]; + logic [0:0] queues__recv__val [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 queues__send__msg [0:0]; + logic [0:0] queues__send__rdy [0:0]; + logic [0:0] queues__send__val [0:0]; + + NormalQueueRTL__43c9394e24dc368f queues__0 + ( + .clk( queues__clk[0] ), + .count( queues__count[0] ), + .reset( queues__reset[0] ), + .recv__msg( queues__recv__msg[0] ), + .recv__rdy( queues__recv__rdy[0] ), + .recv__val( queues__recv__val[0] ), + .send__msg( queues__send__msg[0] ), + .send__rdy( queues__send__rdy[0] ), + .send__val( queues__send__val[0] ) + ); + + //------------------------------------------------------------- + // End of component queues[0:0] + //------------------------------------------------------------- + + assign queues__clk[0] = clk; + assign queues__reset[0] = reset; + assign queues__recv__msg[0] = recv__msg; + assign recv__rdy = queues__recv__rdy[0]; + assign queues__recv__val[0] = recv__val; + assign send__msg = queues__send__msg[0]; + assign queues__send__rdy[0] = send__rdy; + assign send__val = queues__send__val[0]; + +endmodule + + +// PyMTL Component LinkOrRTL Definition +// Full name: LinkOrRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/LinkOrRTL.py + +module LinkOrRTL__0fce34ff986f61fe +( + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_fu__msg , + output logic [0:0] recv_fu__rdy , + input logic [0:0] recv_fu__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_xbar__msg , + output logic [0:0] recv_xbar__rdy , + input logic [0:0] recv_xbar__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/LinkOrRTL.py:28 + // @update + // def process(): + // # Initializes the delivered message. + // s.send.msg @= DataType() + // + // # The messages from two sources (i.e., xbar and FU) won't be valid + // # simultaneously (confliction would be caused if they both are valid), + // # which is guaranteed by the compiler/software. + // s.send.msg.predicate @= s.recv_fu.msg.predicate | s.recv_xbar.msg.predicate + // s.send.msg.payload @= s.recv_xbar.msg.payload | s.recv_fu.msg.payload + // + // # FIXME: bypass won't be necessary any more with separate xbar design. + // # s.send.msg.bypass @= 0 + // # s.send.msg.delay @= s.recv_fu.msg.delay | s.recv_xbar.msg.delay + // + // # s.send.val @= s.send.rdy & (s.recv_fu.val | s.recv_xbar.val) + // s.send.val @= s.recv_fu.val | s.recv_xbar.val + // s.recv_fu.rdy @= s.send.rdy + // s.recv_xbar.rdy @= s.send.rdy + + always_comb begin : process + send__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + send__msg.predicate = recv_fu__msg.predicate | recv_xbar__msg.predicate; + send__msg.payload = recv_xbar__msg.payload | recv_fu__msg.payload; + send__val = recv_fu__val | recv_xbar__val; + recv_fu__rdy = send__rdy; + recv_xbar__rdy = send__rdy; + end + +endmodule + + +// PyMTL Component TileRTL Definition +// Full name: TileRTL__IntraCgraPktType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ctrl_mem_size_16__data_mem_size_128__num_ctrl_4__total_steps_38__num_fu_inports_4__num_fu_outports_2__num_tile_inports_4__num_tile_outports_4__num_cgras_4__num_tiles_16__num_registers_per_reg_bank_16__Fu_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ] +// At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py + +module TileRTL__78da5e3970e1cd1d +( + input logic [1:0] cgra_id , + input logic [0:0] clk , + input logic [0:0] reset , + input logic [4:0] tile_id , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:3] , + output logic [0:0] recv_data__rdy [0:3] , + input logic [0:0] recv_data__val [0:3] , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_controller_pkt__msg , + output logic [0:0] recv_from_controller_pkt__rdy , + input logic [0:0] recv_from_controller_pkt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:3] , + input logic [0:0] send_data__rdy [0:3] , + output logic [0:0] send_data__val [0:3] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_controller_pkt__msg , + input logic [0:0] send_to_controller_pkt__rdy , + output logic [0:0] send_to_controller_pkt__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam logic [1:0] __const__CMD_CONFIG = 2'd3; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; + localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; + localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; + localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; + localparam logic [3:0] __const__CMD_CONST = 4'd13; + logic [0:0] element_done; + logic [0:0] fu_crossbar_done; + logic [0:0] routing_crossbar_done; + //------------------------------------------------------------- + // Component const_mem + //------------------------------------------------------------- + + logic [0:0] const_mem__clear; + logic [0:0] const_mem__clk; + logic [0:0] const_mem__ctrl_proceed; + logic [0:0] const_mem__reset; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_mem__recv_const__msg; + logic [0:0] const_mem__recv_const__rdy; + logic [0:0] const_mem__recv_const__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_mem__send_const__msg; + logic [0:0] const_mem__send_const__rdy; + logic [0:0] const_mem__send_const__val; + + ConstQueueDynamicRTL__9d3397f72f19af52 const_mem + ( + .clear( const_mem__clear ), + .clk( const_mem__clk ), + .ctrl_proceed( const_mem__ctrl_proceed ), + .reset( const_mem__reset ), + .recv_const__msg( const_mem__recv_const__msg ), + .recv_const__rdy( const_mem__recv_const__rdy ), + .recv_const__val( const_mem__recv_const__val ), + .send_const__msg( const_mem__send_const__msg ), + .send_const__rdy( const_mem__send_const__rdy ), + .send_const__val( const_mem__send_const__val ) + ); + + //------------------------------------------------------------- + // End of component const_mem + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component ctrl_mem + //------------------------------------------------------------- + + logic [1:0] ctrl_mem__cgra_id; + logic [0:0] ctrl_mem__clk; + logic [3:0] ctrl_mem__ctrl_addr_outport; + logic [2:0] ctrl_mem__prologue_count_outport_fu; + logic [2:0] ctrl_mem__prologue_count_outport_fu_crossbar [0:15][0:1]; + logic [2:0] ctrl_mem__prologue_count_outport_routing_crossbar [0:15][0:3]; + logic [0:0] ctrl_mem__reset; + logic [4:0] ctrl_mem__tile_id; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a ctrl_mem__recv_from_element__msg; + logic [0:0] ctrl_mem__recv_from_element__rdy; + logic [0:0] ctrl_mem__recv_from_element__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_mem__recv_pkt_from_controller__msg; + logic [0:0] ctrl_mem__recv_pkt_from_controller__rdy; + logic [0:0] ctrl_mem__recv_pkt_from_controller__val; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 ctrl_mem__send_ctrl__msg; + logic [0:0] ctrl_mem__send_ctrl__rdy; + logic [0:0] ctrl_mem__send_ctrl__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_mem__send_pkt_to_controller__msg; + logic [0:0] ctrl_mem__send_pkt_to_controller__rdy; + logic [0:0] ctrl_mem__send_pkt_to_controller__val; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a ctrl_mem__send_to_element__msg; + logic [0:0] ctrl_mem__send_to_element__rdy; + logic [0:0] ctrl_mem__send_to_element__val; + + CtrlMemDynamicRTL__427d547b7d58aa8e ctrl_mem + ( + .cgra_id( ctrl_mem__cgra_id ), + .clk( ctrl_mem__clk ), + .ctrl_addr_outport( ctrl_mem__ctrl_addr_outport ), + .prologue_count_outport_fu( ctrl_mem__prologue_count_outport_fu ), + .prologue_count_outport_fu_crossbar( ctrl_mem__prologue_count_outport_fu_crossbar ), + .prologue_count_outport_routing_crossbar( ctrl_mem__prologue_count_outport_routing_crossbar ), + .reset( ctrl_mem__reset ), + .tile_id( ctrl_mem__tile_id ), + .recv_from_element__msg( ctrl_mem__recv_from_element__msg ), + .recv_from_element__rdy( ctrl_mem__recv_from_element__rdy ), + .recv_from_element__val( ctrl_mem__recv_from_element__val ), + .recv_pkt_from_controller__msg( ctrl_mem__recv_pkt_from_controller__msg ), + .recv_pkt_from_controller__rdy( ctrl_mem__recv_pkt_from_controller__rdy ), + .recv_pkt_from_controller__val( ctrl_mem__recv_pkt_from_controller__val ), + .send_ctrl__msg( ctrl_mem__send_ctrl__msg ), + .send_ctrl__rdy( ctrl_mem__send_ctrl__rdy ), + .send_ctrl__val( ctrl_mem__send_ctrl__val ), + .send_pkt_to_controller__msg( ctrl_mem__send_pkt_to_controller__msg ), + .send_pkt_to_controller__rdy( ctrl_mem__send_pkt_to_controller__rdy ), + .send_pkt_to_controller__val( ctrl_mem__send_pkt_to_controller__val ), + .send_to_element__msg( ctrl_mem__send_to_element__msg ), + .send_to_element__rdy( ctrl_mem__send_to_element__rdy ), + .send_to_element__val( ctrl_mem__send_to_element__val ) + ); + + //------------------------------------------------------------- + // End of component ctrl_mem + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component element + //------------------------------------------------------------- + + logic [0:0] element__clear [0:14]; + logic [0:0] element__clk; + logic [2:0] element__prologue_count_inport; + logic [0:0] element__reset; + logic [4:0] element__tile_id; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__from_mem_rdata__msg [0:14]; + logic [0:0] element__from_mem_rdata__rdy [0:14]; + logic [0:0] element__from_mem_rdata__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__recv_const__msg; + logic [0:0] element__recv_const__rdy; + logic [0:0] element__recv_const__val; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a element__recv_from_ctrl_mem__msg; + logic [0:0] element__recv_from_ctrl_mem__rdy; + logic [0:0] element__recv_from_ctrl_mem__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__recv_in__msg [0:3]; + logic [0:0] element__recv_in__rdy [0:3]; + logic [0:0] element__recv_in__val [0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 element__recv_opt__msg; + logic [0:0] element__recv_opt__rdy; + logic [0:0] element__recv_opt__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__send_out__msg [0:1]; + logic [0:0] element__send_out__rdy [0:1]; + logic [0:0] element__send_out__val [0:1]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a element__send_to_ctrl_mem__msg; + logic [0:0] element__send_to_ctrl_mem__rdy; + logic [0:0] element__send_to_ctrl_mem__val; + logic [6:0] element__to_mem_raddr__msg [0:14]; + logic [0:0] element__to_mem_raddr__rdy [0:14]; + logic [0:0] element__to_mem_raddr__val [0:14]; + logic [6:0] element__to_mem_waddr__msg [0:14]; + logic [0:0] element__to_mem_waddr__rdy [0:14]; + logic [0:0] element__to_mem_waddr__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__to_mem_wdata__msg [0:14]; + logic [0:0] element__to_mem_wdata__rdy [0:14]; + logic [0:0] element__to_mem_wdata__val [0:14]; + + FlexibleFuRTL__07217382918d0fc2 element + ( + .clear( element__clear ), + .clk( element__clk ), + .prologue_count_inport( element__prologue_count_inport ), + .reset( element__reset ), + .tile_id( element__tile_id ), + .from_mem_rdata__msg( element__from_mem_rdata__msg ), + .from_mem_rdata__rdy( element__from_mem_rdata__rdy ), + .from_mem_rdata__val( element__from_mem_rdata__val ), + .recv_const__msg( element__recv_const__msg ), + .recv_const__rdy( element__recv_const__rdy ), + .recv_const__val( element__recv_const__val ), + .recv_from_ctrl_mem__msg( element__recv_from_ctrl_mem__msg ), + .recv_from_ctrl_mem__rdy( element__recv_from_ctrl_mem__rdy ), + .recv_from_ctrl_mem__val( element__recv_from_ctrl_mem__val ), + .recv_in__msg( element__recv_in__msg ), + .recv_in__rdy( element__recv_in__rdy ), + .recv_in__val( element__recv_in__val ), + .recv_opt__msg( element__recv_opt__msg ), + .recv_opt__rdy( element__recv_opt__rdy ), + .recv_opt__val( element__recv_opt__val ), + .send_out__msg( element__send_out__msg ), + .send_out__rdy( element__send_out__rdy ), + .send_out__val( element__send_out__val ), + .send_to_ctrl_mem__msg( element__send_to_ctrl_mem__msg ), + .send_to_ctrl_mem__rdy( element__send_to_ctrl_mem__rdy ), + .send_to_ctrl_mem__val( element__send_to_ctrl_mem__val ), + .to_mem_raddr__msg( element__to_mem_raddr__msg ), + .to_mem_raddr__rdy( element__to_mem_raddr__rdy ), + .to_mem_raddr__val( element__to_mem_raddr__val ), + .to_mem_waddr__msg( element__to_mem_waddr__msg ), + .to_mem_waddr__rdy( element__to_mem_waddr__rdy ), + .to_mem_waddr__val( element__to_mem_waddr__val ), + .to_mem_wdata__msg( element__to_mem_wdata__msg ), + .to_mem_wdata__rdy( element__to_mem_wdata__rdy ), + .to_mem_wdata__val( element__to_mem_wdata__val ) + ); + + //------------------------------------------------------------- + // End of component element + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component fu_crossbar + //------------------------------------------------------------- + + logic [1:0] fu_crossbar__cgra_id; + logic [0:0] fu_crossbar__clear; + logic [0:0] fu_crossbar__clk; + logic [0:0] fu_crossbar__compute_done; + logic [0:0] fu_crossbar__crossbar_id; + logic [1:0] fu_crossbar__crossbar_outport [0:7]; + logic [3:0] fu_crossbar__ctrl_addr_inport; + logic [2:0] fu_crossbar__prologue_count_inport [0:15][0:1]; + logic [0:0] fu_crossbar__reset; + logic [4:0] fu_crossbar__tile_id; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu_crossbar__recv_data__msg [0:1]; + logic [0:0] fu_crossbar__recv_data__rdy [0:1]; + logic [0:0] fu_crossbar__recv_data__val [0:1]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 fu_crossbar__recv_opt__msg; + logic [0:0] fu_crossbar__recv_opt__rdy; + logic [0:0] fu_crossbar__recv_opt__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu_crossbar__send_data__msg [0:7]; + logic [0:0] fu_crossbar__send_data__rdy [0:7]; + logic [0:0] fu_crossbar__send_data__val [0:7]; + + CrossbarRTL__45ee026205c61975 fu_crossbar + ( + .cgra_id( fu_crossbar__cgra_id ), + .clear( fu_crossbar__clear ), + .clk( fu_crossbar__clk ), + .compute_done( fu_crossbar__compute_done ), + .crossbar_id( fu_crossbar__crossbar_id ), + .crossbar_outport( fu_crossbar__crossbar_outport ), + .ctrl_addr_inport( fu_crossbar__ctrl_addr_inport ), + .prologue_count_inport( fu_crossbar__prologue_count_inport ), + .reset( fu_crossbar__reset ), + .tile_id( fu_crossbar__tile_id ), + .recv_data__msg( fu_crossbar__recv_data__msg ), + .recv_data__rdy( fu_crossbar__recv_data__rdy ), + .recv_data__val( fu_crossbar__recv_data__val ), + .recv_opt__msg( fu_crossbar__recv_opt__msg ), + .recv_opt__rdy( fu_crossbar__recv_opt__rdy ), + .recv_opt__val( fu_crossbar__recv_opt__val ), + .send_data__msg( fu_crossbar__send_data__msg ), + .send_data__rdy( fu_crossbar__send_data__rdy ), + .send_data__val( fu_crossbar__send_data__val ) + ); + + //------------------------------------------------------------- + // End of component fu_crossbar + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component register_cluster + //------------------------------------------------------------- + + logic [0:0] register_cluster__clk; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 register_cluster__inport_opt; + logic [0:0] register_cluster__reset; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_const__msg [0:3]; + logic [0:0] register_cluster__recv_data_from_const__rdy [0:3]; + logic [0:0] register_cluster__recv_data_from_const__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_fu_crossbar__msg [0:3]; + logic [0:0] register_cluster__recv_data_from_fu_crossbar__rdy [0:3]; + logic [0:0] register_cluster__recv_data_from_fu_crossbar__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_routing_crossbar__msg [0:3]; + logic [0:0] register_cluster__recv_data_from_routing_crossbar__rdy [0:3]; + logic [0:0] register_cluster__recv_data_from_routing_crossbar__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__send_data_to_fu__msg [0:3]; + logic [0:0] register_cluster__send_data_to_fu__rdy [0:3]; + logic [0:0] register_cluster__send_data_to_fu__val [0:3]; + + RegisterClusterRTL__7f2febb613462546 register_cluster + ( + .clk( register_cluster__clk ), + .inport_opt( register_cluster__inport_opt ), + .reset( register_cluster__reset ), + .recv_data_from_const__msg( register_cluster__recv_data_from_const__msg ), + .recv_data_from_const__rdy( register_cluster__recv_data_from_const__rdy ), + .recv_data_from_const__val( register_cluster__recv_data_from_const__val ), + .recv_data_from_fu_crossbar__msg( register_cluster__recv_data_from_fu_crossbar__msg ), + .recv_data_from_fu_crossbar__rdy( register_cluster__recv_data_from_fu_crossbar__rdy ), + .recv_data_from_fu_crossbar__val( register_cluster__recv_data_from_fu_crossbar__val ), + .recv_data_from_routing_crossbar__msg( register_cluster__recv_data_from_routing_crossbar__msg ), + .recv_data_from_routing_crossbar__rdy( register_cluster__recv_data_from_routing_crossbar__rdy ), + .recv_data_from_routing_crossbar__val( register_cluster__recv_data_from_routing_crossbar__val ), + .send_data_to_fu__msg( register_cluster__send_data_to_fu__msg ), + .send_data_to_fu__rdy( register_cluster__send_data_to_fu__rdy ), + .send_data_to_fu__val( register_cluster__send_data_to_fu__val ) + ); + + //------------------------------------------------------------- + // End of component register_cluster + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component routing_crossbar + //------------------------------------------------------------- + + logic [1:0] routing_crossbar__cgra_id; + logic [0:0] routing_crossbar__clear; + logic [0:0] routing_crossbar__clk; + logic [0:0] routing_crossbar__compute_done; + logic [0:0] routing_crossbar__crossbar_id; + logic [2:0] routing_crossbar__crossbar_outport [0:7]; + logic [3:0] routing_crossbar__ctrl_addr_inport; + logic [2:0] routing_crossbar__prologue_count_inport [0:15][0:3]; + logic [0:0] routing_crossbar__reset; + logic [4:0] routing_crossbar__tile_id; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 routing_crossbar__recv_data__msg [0:3]; + logic [0:0] routing_crossbar__recv_data__rdy [0:3]; + logic [0:0] routing_crossbar__recv_data__val [0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 routing_crossbar__recv_opt__msg; + logic [0:0] routing_crossbar__recv_opt__rdy; + logic [0:0] routing_crossbar__recv_opt__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 routing_crossbar__send_data__msg [0:7]; + logic [0:0] routing_crossbar__send_data__rdy [0:7]; + logic [0:0] routing_crossbar__send_data__val [0:7]; + + CrossbarRTL__cad4150dfdc32fbd routing_crossbar + ( + .cgra_id( routing_crossbar__cgra_id ), + .clear( routing_crossbar__clear ), + .clk( routing_crossbar__clk ), + .compute_done( routing_crossbar__compute_done ), + .crossbar_id( routing_crossbar__crossbar_id ), + .crossbar_outport( routing_crossbar__crossbar_outport ), + .ctrl_addr_inport( routing_crossbar__ctrl_addr_inport ), + .prologue_count_inport( routing_crossbar__prologue_count_inport ), + .reset( routing_crossbar__reset ), + .tile_id( routing_crossbar__tile_id ), + .recv_data__msg( routing_crossbar__recv_data__msg ), + .recv_data__rdy( routing_crossbar__recv_data__rdy ), + .recv_data__val( routing_crossbar__recv_data__val ), + .recv_opt__msg( routing_crossbar__recv_opt__msg ), + .recv_opt__rdy( routing_crossbar__recv_opt__rdy ), + .recv_opt__val( routing_crossbar__recv_opt__val ), + .send_data__msg( routing_crossbar__send_data__msg ), + .send_data__rdy( routing_crossbar__send_data__rdy ), + .send_data__val( routing_crossbar__send_data__val ) + ); + + //------------------------------------------------------------- + // End of component routing_crossbar + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component tile_in_channel[0:3] + //------------------------------------------------------------- + + logic [0:0] tile_in_channel__clk [0:3]; + logic [0:0] tile_in_channel__reset [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_in_channel__recv__msg [0:3]; + logic [0:0] tile_in_channel__recv__rdy [0:3]; + logic [0:0] tile_in_channel__recv__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_in_channel__send__msg [0:3]; + logic [0:0] tile_in_channel__send__rdy [0:3]; + logic [0:0] tile_in_channel__send__val [0:3]; + + ChannelRTL__694d252f21ac798b tile_in_channel__0 + ( + .clk( tile_in_channel__clk[0] ), + .reset( tile_in_channel__reset[0] ), + .recv__msg( tile_in_channel__recv__msg[0] ), + .recv__rdy( tile_in_channel__recv__rdy[0] ), + .recv__val( tile_in_channel__recv__val[0] ), + .send__msg( tile_in_channel__send__msg[0] ), + .send__rdy( tile_in_channel__send__rdy[0] ), + .send__val( tile_in_channel__send__val[0] ) + ); + + ChannelRTL__694d252f21ac798b tile_in_channel__1 + ( + .clk( tile_in_channel__clk[1] ), + .reset( tile_in_channel__reset[1] ), + .recv__msg( tile_in_channel__recv__msg[1] ), + .recv__rdy( tile_in_channel__recv__rdy[1] ), + .recv__val( tile_in_channel__recv__val[1] ), + .send__msg( tile_in_channel__send__msg[1] ), + .send__rdy( tile_in_channel__send__rdy[1] ), + .send__val( tile_in_channel__send__val[1] ) + ); + + ChannelRTL__694d252f21ac798b tile_in_channel__2 + ( + .clk( tile_in_channel__clk[2] ), + .reset( tile_in_channel__reset[2] ), + .recv__msg( tile_in_channel__recv__msg[2] ), + .recv__rdy( tile_in_channel__recv__rdy[2] ), + .recv__val( tile_in_channel__recv__val[2] ), + .send__msg( tile_in_channel__send__msg[2] ), + .send__rdy( tile_in_channel__send__rdy[2] ), + .send__val( tile_in_channel__send__val[2] ) + ); + + ChannelRTL__694d252f21ac798b tile_in_channel__3 + ( + .clk( tile_in_channel__clk[3] ), + .reset( tile_in_channel__reset[3] ), + .recv__msg( tile_in_channel__recv__msg[3] ), + .recv__rdy( tile_in_channel__recv__rdy[3] ), + .recv__val( tile_in_channel__recv__val[3] ), + .send__msg( tile_in_channel__send__msg[3] ), + .send__rdy( tile_in_channel__send__rdy[3] ), + .send__val( tile_in_channel__send__val[3] ) + ); + + //------------------------------------------------------------- + // End of component tile_in_channel[0:3] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component tile_out_or_link[0:3] + //------------------------------------------------------------- + + logic [0:0] tile_out_or_link__clk [0:3]; + logic [0:0] tile_out_or_link__reset [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__recv_fu__msg [0:3]; + logic [0:0] tile_out_or_link__recv_fu__rdy [0:3]; + logic [0:0] tile_out_or_link__recv_fu__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__recv_xbar__msg [0:3]; + logic [0:0] tile_out_or_link__recv_xbar__rdy [0:3]; + logic [0:0] tile_out_or_link__recv_xbar__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__send__msg [0:3]; + logic [0:0] tile_out_or_link__send__rdy [0:3]; + logic [0:0] tile_out_or_link__send__val [0:3]; + + LinkOrRTL__0fce34ff986f61fe tile_out_or_link__0 + ( + .clk( tile_out_or_link__clk[0] ), + .reset( tile_out_or_link__reset[0] ), + .recv_fu__msg( tile_out_or_link__recv_fu__msg[0] ), + .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[0] ), + .recv_fu__val( tile_out_or_link__recv_fu__val[0] ), + .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[0] ), + .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[0] ), + .recv_xbar__val( tile_out_or_link__recv_xbar__val[0] ), + .send__msg( tile_out_or_link__send__msg[0] ), + .send__rdy( tile_out_or_link__send__rdy[0] ), + .send__val( tile_out_or_link__send__val[0] ) + ); + + LinkOrRTL__0fce34ff986f61fe tile_out_or_link__1 + ( + .clk( tile_out_or_link__clk[1] ), + .reset( tile_out_or_link__reset[1] ), + .recv_fu__msg( tile_out_or_link__recv_fu__msg[1] ), + .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[1] ), + .recv_fu__val( tile_out_or_link__recv_fu__val[1] ), + .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[1] ), + .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[1] ), + .recv_xbar__val( tile_out_or_link__recv_xbar__val[1] ), + .send__msg( tile_out_or_link__send__msg[1] ), + .send__rdy( tile_out_or_link__send__rdy[1] ), + .send__val( tile_out_or_link__send__val[1] ) + ); + + LinkOrRTL__0fce34ff986f61fe tile_out_or_link__2 + ( + .clk( tile_out_or_link__clk[2] ), + .reset( tile_out_or_link__reset[2] ), + .recv_fu__msg( tile_out_or_link__recv_fu__msg[2] ), + .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[2] ), + .recv_fu__val( tile_out_or_link__recv_fu__val[2] ), + .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[2] ), + .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[2] ), + .recv_xbar__val( tile_out_or_link__recv_xbar__val[2] ), + .send__msg( tile_out_or_link__send__msg[2] ), + .send__rdy( tile_out_or_link__send__rdy[2] ), + .send__val( tile_out_or_link__send__val[2] ) + ); + + LinkOrRTL__0fce34ff986f61fe tile_out_or_link__3 + ( + .clk( tile_out_or_link__clk[3] ), + .reset( tile_out_or_link__reset[3] ), + .recv_fu__msg( tile_out_or_link__recv_fu__msg[3] ), + .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[3] ), + .recv_fu__val( tile_out_or_link__recv_fu__val[3] ), + .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[3] ), + .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[3] ), + .recv_xbar__val( tile_out_or_link__recv_xbar__val[3] ), + .send__msg( tile_out_or_link__send__msg[3] ), + .send__rdy( tile_out_or_link__send__rdy[3] ), + .send__val( tile_out_or_link__send__val[3] ) + ); + + //------------------------------------------------------------- + // End of component tile_out_or_link[0:3] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:236 + // @update + // def feed_pkt(): + // s.ctrl_mem.recv_pkt_from_controller.msg @= CtrlPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) # , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.const_mem.recv_const.msg @= DataType(0, 0, 0, 0) + // s.ctrl_mem.recv_pkt_from_controller.val @= 0 + // s.const_mem.recv_const.val @= 0 + // s.recv_from_controller_pkt.rdy @= 0 + // + // if s.recv_from_controller_pkt.val & \ + // ((s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_LAUNCH)): + // s.ctrl_mem.recv_pkt_from_controller.val @= 1 + // s.ctrl_mem.recv_pkt_from_controller.msg @= s.recv_from_controller_pkt.msg + // s.recv_from_controller_pkt.rdy @= s.ctrl_mem.recv_pkt_from_controller.rdy + // elif s.recv_from_controller_pkt.val & (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONST): + // s.const_mem.recv_const.val @= 1 + // s.const_mem.recv_const.msg @= s.recv_from_controller_pkt.msg.payload.data + // s.recv_from_controller_pkt.rdy @= s.const_mem.recv_const.rdy + + always_comb begin : feed_pkt + ctrl_mem__recv_pkt_from_controller__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; + const_mem__recv_const__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + ctrl_mem__recv_pkt_from_controller__val = 1'd0; + const_mem__recv_const__val = 1'd0; + recv_from_controller_pkt__rdy = 1'd0; + if ( recv_from_controller_pkt__val & ( ( ( ( ( ( ( ( ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) ) begin + ctrl_mem__recv_pkt_from_controller__val = 1'd1; + ctrl_mem__recv_pkt_from_controller__msg = recv_from_controller_pkt__msg; + recv_from_controller_pkt__rdy = ctrl_mem__recv_pkt_from_controller__rdy; + end + else if ( recv_from_controller_pkt__val & ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONST ) ) ) begin + const_mem__recv_const__val = 1'd1; + const_mem__recv_const__msg = recv_from_controller_pkt__msg.payload.data; + recv_from_controller_pkt__rdy = const_mem__recv_const__rdy; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:292 + // @update + // def notify_const_mem(): + // s.const_mem.ctrl_proceed @= s.ctrl_mem.send_ctrl.rdy & s.ctrl_mem.send_ctrl.val + + always_comb begin : notify_const_mem + const_mem__ctrl_proceed = ctrl_mem__send_ctrl__rdy & ctrl_mem__send_ctrl__val; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:311 + // @update + // def notify_crossbars_compute_status(): + // s.routing_crossbar.compute_done @= s.element_done + // s.fu_crossbar.compute_done @= s.element_done + + always_comb begin : notify_crossbars_compute_status + routing_crossbar__compute_done = element_done; + fu_crossbar__compute_done = element_done; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:272 + // @update + // def update_opt(): + // s.element.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg + // s.routing_crossbar.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg + // s.fu_crossbar.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg + // + // # FIXME: Do we still need separate element and routing_xbar? + // # FIXME: Do we need to consider reg bank here? + // s.element.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.element_done + // s.routing_crossbar.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.routing_crossbar_done + // s.fu_crossbar.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.fu_crossbar_done + // + // # FIXME: yo96, rename ctrl.rdy to ctrl.proceed or sth similar. + // # Allows either the FU-related go out first or routing-xbar go out first. And only + // # allows the ctrl signal proceed till all the sub-modules done their own job (once). + // s.ctrl_mem.send_ctrl.rdy @= (s.element.recv_opt.rdy | s.element_done) & \ + // (s.routing_crossbar.recv_opt.rdy | s.routing_crossbar_done) & \ + // (s.fu_crossbar.recv_opt.rdy | s.fu_crossbar_done) + + always_comb begin : update_opt + element__recv_opt__msg = ctrl_mem__send_ctrl__msg; + routing_crossbar__recv_opt__msg = ctrl_mem__send_ctrl__msg; + fu_crossbar__recv_opt__msg = ctrl_mem__send_ctrl__msg; + element__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~element_done ); + routing_crossbar__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~routing_crossbar_done ); + fu_crossbar__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~fu_crossbar_done ); + ctrl_mem__send_ctrl__rdy = ( ( element__recv_opt__rdy | element_done ) & ( routing_crossbar__recv_opt__rdy | routing_crossbar_done ) ) & ( fu_crossbar__recv_opt__rdy | fu_crossbar_done ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:262 + // @update + // def update_send_out_signal(): + // s.send_to_controller_pkt.val @= 0 + // s.send_to_controller_pkt.msg @= CtrlPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) # , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // if s.ctrl_mem.send_pkt_to_controller.val: + // s.send_to_controller_pkt.val @= 1 + // s.send_to_controller_pkt.msg @= s.ctrl_mem.send_pkt_to_controller.msg + // s.ctrl_mem.send_pkt_to_controller.rdy @= s.send_to_controller_pkt.rdy + + always_comb begin : update_send_out_signal + send_to_controller_pkt__val = 1'd0; + send_to_controller_pkt__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; + if ( ctrl_mem__send_pkt_to_controller__val ) begin + send_to_controller_pkt__val = 1'd1; + send_to_controller_pkt__msg = ctrl_mem__send_pkt_to_controller__msg; + end + ctrl_mem__send_pkt_to_controller__rdy = send_to_controller_pkt__rdy; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:297 + // @update_ff + // def already_done(): + // if s.reset | s.ctrl_mem.send_ctrl.rdy: + // s.element_done <<= 0 + // s.fu_crossbar_done <<= 0 + // s.routing_crossbar_done <<= 0 + // else: + // if s.element.recv_opt.rdy: + // s.element_done <<= 1 + // if s.fu_crossbar.recv_opt.rdy: + // s.fu_crossbar_done <<= 1 + // if s.routing_crossbar.recv_opt.rdy: + // s.routing_crossbar_done <<= 1 + + always_ff @(posedge clk) begin : already_done + if ( reset | ctrl_mem__send_ctrl__rdy ) begin + element_done <= 1'd0; + fu_crossbar_done <= 1'd0; + routing_crossbar_done <= 1'd0; + end + else begin + if ( element__recv_opt__rdy ) begin + element_done <= 1'd1; + end + if ( fu_crossbar__recv_opt__rdy ) begin + fu_crossbar_done <= 1'd1; + end + if ( routing_crossbar__recv_opt__rdy ) begin + routing_crossbar_done <= 1'd1; + end + end + end + + assign element__clk = clk; + assign element__reset = reset; + assign const_mem__clk = clk; + assign const_mem__reset = reset; + assign routing_crossbar__clk = clk; + assign routing_crossbar__reset = reset; + assign fu_crossbar__clk = clk; + assign fu_crossbar__reset = reset; + assign register_cluster__clk = clk; + assign register_cluster__reset = reset; + assign ctrl_mem__clk = clk; + assign ctrl_mem__reset = reset; + assign tile_in_channel__clk[0] = clk; + assign tile_in_channel__reset[0] = reset; + assign tile_in_channel__clk[1] = clk; + assign tile_in_channel__reset[1] = reset; + assign tile_in_channel__clk[2] = clk; + assign tile_in_channel__reset[2] = reset; + assign tile_in_channel__clk[3] = clk; + assign tile_in_channel__reset[3] = reset; + assign tile_out_or_link__clk[0] = clk; + assign tile_out_or_link__reset[0] = reset; + assign tile_out_or_link__clk[1] = clk; + assign tile_out_or_link__reset[1] = reset; + assign tile_out_or_link__clk[2] = clk; + assign tile_out_or_link__reset[2] = reset; + assign tile_out_or_link__clk[3] = clk; + assign tile_out_or_link__reset[3] = reset; + assign element__tile_id = tile_id; + assign ctrl_mem__cgra_id = cgra_id; + assign ctrl_mem__tile_id = tile_id; + assign fu_crossbar__cgra_id = cgra_id; + assign fu_crossbar__tile_id = tile_id; + assign routing_crossbar__cgra_id = cgra_id; + assign routing_crossbar__tile_id = tile_id; + assign routing_crossbar__crossbar_id = 1'd0; + assign fu_crossbar__crossbar_id = 1'd1; + assign element__recv_const__msg = const_mem__send_const__msg; + assign const_mem__send_const__rdy = element__recv_const__rdy; + assign element__recv_const__val = const_mem__send_const__val; + assign ctrl_mem__recv_from_element__msg = element__send_to_ctrl_mem__msg; + assign element__send_to_ctrl_mem__rdy = ctrl_mem__recv_from_element__rdy; + assign ctrl_mem__recv_from_element__val = element__send_to_ctrl_mem__val; + assign element__recv_from_ctrl_mem__msg = ctrl_mem__send_to_element__msg; + assign ctrl_mem__send_to_element__rdy = element__recv_from_ctrl_mem__rdy; + assign element__recv_from_ctrl_mem__val = ctrl_mem__send_to_element__val; + assign routing_crossbar__ctrl_addr_inport = ctrl_mem__ctrl_addr_outport; + assign fu_crossbar__ctrl_addr_inport = ctrl_mem__ctrl_addr_outport; + assign element__prologue_count_inport = ctrl_mem__prologue_count_outport_fu; + assign routing_crossbar__prologue_count_inport[0][0] = ctrl_mem__prologue_count_outport_routing_crossbar[0][0]; + assign routing_crossbar__prologue_count_inport[0][1] = ctrl_mem__prologue_count_outport_routing_crossbar[0][1]; + assign routing_crossbar__prologue_count_inport[0][2] = ctrl_mem__prologue_count_outport_routing_crossbar[0][2]; + assign routing_crossbar__prologue_count_inport[0][3] = ctrl_mem__prologue_count_outport_routing_crossbar[0][3]; + assign fu_crossbar__prologue_count_inport[0][0] = ctrl_mem__prologue_count_outport_fu_crossbar[0][0]; + assign fu_crossbar__prologue_count_inport[0][1] = ctrl_mem__prologue_count_outport_fu_crossbar[0][1]; + assign routing_crossbar__prologue_count_inport[1][0] = ctrl_mem__prologue_count_outport_routing_crossbar[1][0]; + assign routing_crossbar__prologue_count_inport[1][1] = ctrl_mem__prologue_count_outport_routing_crossbar[1][1]; + assign routing_crossbar__prologue_count_inport[1][2] = ctrl_mem__prologue_count_outport_routing_crossbar[1][2]; + assign routing_crossbar__prologue_count_inport[1][3] = ctrl_mem__prologue_count_outport_routing_crossbar[1][3]; + assign fu_crossbar__prologue_count_inport[1][0] = ctrl_mem__prologue_count_outport_fu_crossbar[1][0]; + assign fu_crossbar__prologue_count_inport[1][1] = ctrl_mem__prologue_count_outport_fu_crossbar[1][1]; + assign routing_crossbar__prologue_count_inport[2][0] = ctrl_mem__prologue_count_outport_routing_crossbar[2][0]; + assign routing_crossbar__prologue_count_inport[2][1] = ctrl_mem__prologue_count_outport_routing_crossbar[2][1]; + assign routing_crossbar__prologue_count_inport[2][2] = ctrl_mem__prologue_count_outport_routing_crossbar[2][2]; + assign routing_crossbar__prologue_count_inport[2][3] = ctrl_mem__prologue_count_outport_routing_crossbar[2][3]; + assign fu_crossbar__prologue_count_inport[2][0] = ctrl_mem__prologue_count_outport_fu_crossbar[2][0]; + assign fu_crossbar__prologue_count_inport[2][1] = ctrl_mem__prologue_count_outport_fu_crossbar[2][1]; + assign routing_crossbar__prologue_count_inport[3][0] = ctrl_mem__prologue_count_outport_routing_crossbar[3][0]; + assign routing_crossbar__prologue_count_inport[3][1] = ctrl_mem__prologue_count_outport_routing_crossbar[3][1]; + assign routing_crossbar__prologue_count_inport[3][2] = ctrl_mem__prologue_count_outport_routing_crossbar[3][2]; + assign routing_crossbar__prologue_count_inport[3][3] = ctrl_mem__prologue_count_outport_routing_crossbar[3][3]; + assign fu_crossbar__prologue_count_inport[3][0] = ctrl_mem__prologue_count_outport_fu_crossbar[3][0]; + assign fu_crossbar__prologue_count_inport[3][1] = ctrl_mem__prologue_count_outport_fu_crossbar[3][1]; + assign routing_crossbar__prologue_count_inport[4][0] = ctrl_mem__prologue_count_outport_routing_crossbar[4][0]; + assign routing_crossbar__prologue_count_inport[4][1] = ctrl_mem__prologue_count_outport_routing_crossbar[4][1]; + assign routing_crossbar__prologue_count_inport[4][2] = ctrl_mem__prologue_count_outport_routing_crossbar[4][2]; + assign routing_crossbar__prologue_count_inport[4][3] = ctrl_mem__prologue_count_outport_routing_crossbar[4][3]; + assign fu_crossbar__prologue_count_inport[4][0] = ctrl_mem__prologue_count_outport_fu_crossbar[4][0]; + assign fu_crossbar__prologue_count_inport[4][1] = ctrl_mem__prologue_count_outport_fu_crossbar[4][1]; + assign routing_crossbar__prologue_count_inport[5][0] = ctrl_mem__prologue_count_outport_routing_crossbar[5][0]; + assign routing_crossbar__prologue_count_inport[5][1] = ctrl_mem__prologue_count_outport_routing_crossbar[5][1]; + assign routing_crossbar__prologue_count_inport[5][2] = ctrl_mem__prologue_count_outport_routing_crossbar[5][2]; + assign routing_crossbar__prologue_count_inport[5][3] = ctrl_mem__prologue_count_outport_routing_crossbar[5][3]; + assign fu_crossbar__prologue_count_inport[5][0] = ctrl_mem__prologue_count_outport_fu_crossbar[5][0]; + assign fu_crossbar__prologue_count_inport[5][1] = ctrl_mem__prologue_count_outport_fu_crossbar[5][1]; + assign routing_crossbar__prologue_count_inport[6][0] = ctrl_mem__prologue_count_outport_routing_crossbar[6][0]; + assign routing_crossbar__prologue_count_inport[6][1] = ctrl_mem__prologue_count_outport_routing_crossbar[6][1]; + assign routing_crossbar__prologue_count_inport[6][2] = ctrl_mem__prologue_count_outport_routing_crossbar[6][2]; + assign routing_crossbar__prologue_count_inport[6][3] = ctrl_mem__prologue_count_outport_routing_crossbar[6][3]; + assign fu_crossbar__prologue_count_inport[6][0] = ctrl_mem__prologue_count_outport_fu_crossbar[6][0]; + assign fu_crossbar__prologue_count_inport[6][1] = ctrl_mem__prologue_count_outport_fu_crossbar[6][1]; + assign routing_crossbar__prologue_count_inport[7][0] = ctrl_mem__prologue_count_outport_routing_crossbar[7][0]; + assign routing_crossbar__prologue_count_inport[7][1] = ctrl_mem__prologue_count_outport_routing_crossbar[7][1]; + assign routing_crossbar__prologue_count_inport[7][2] = ctrl_mem__prologue_count_outport_routing_crossbar[7][2]; + assign routing_crossbar__prologue_count_inport[7][3] = ctrl_mem__prologue_count_outport_routing_crossbar[7][3]; + assign fu_crossbar__prologue_count_inport[7][0] = ctrl_mem__prologue_count_outport_fu_crossbar[7][0]; + assign fu_crossbar__prologue_count_inport[7][1] = ctrl_mem__prologue_count_outport_fu_crossbar[7][1]; + assign routing_crossbar__prologue_count_inport[8][0] = ctrl_mem__prologue_count_outport_routing_crossbar[8][0]; + assign routing_crossbar__prologue_count_inport[8][1] = ctrl_mem__prologue_count_outport_routing_crossbar[8][1]; + assign routing_crossbar__prologue_count_inport[8][2] = ctrl_mem__prologue_count_outport_routing_crossbar[8][2]; + assign routing_crossbar__prologue_count_inport[8][3] = ctrl_mem__prologue_count_outport_routing_crossbar[8][3]; + assign fu_crossbar__prologue_count_inport[8][0] = ctrl_mem__prologue_count_outport_fu_crossbar[8][0]; + assign fu_crossbar__prologue_count_inport[8][1] = ctrl_mem__prologue_count_outport_fu_crossbar[8][1]; + assign routing_crossbar__prologue_count_inport[9][0] = ctrl_mem__prologue_count_outport_routing_crossbar[9][0]; + assign routing_crossbar__prologue_count_inport[9][1] = ctrl_mem__prologue_count_outport_routing_crossbar[9][1]; + assign routing_crossbar__prologue_count_inport[9][2] = ctrl_mem__prologue_count_outport_routing_crossbar[9][2]; + assign routing_crossbar__prologue_count_inport[9][3] = ctrl_mem__prologue_count_outport_routing_crossbar[9][3]; + assign fu_crossbar__prologue_count_inport[9][0] = ctrl_mem__prologue_count_outport_fu_crossbar[9][0]; + assign fu_crossbar__prologue_count_inport[9][1] = ctrl_mem__prologue_count_outport_fu_crossbar[9][1]; + assign routing_crossbar__prologue_count_inport[10][0] = ctrl_mem__prologue_count_outport_routing_crossbar[10][0]; + assign routing_crossbar__prologue_count_inport[10][1] = ctrl_mem__prologue_count_outport_routing_crossbar[10][1]; + assign routing_crossbar__prologue_count_inport[10][2] = ctrl_mem__prologue_count_outport_routing_crossbar[10][2]; + assign routing_crossbar__prologue_count_inport[10][3] = ctrl_mem__prologue_count_outport_routing_crossbar[10][3]; + assign fu_crossbar__prologue_count_inport[10][0] = ctrl_mem__prologue_count_outport_fu_crossbar[10][0]; + assign fu_crossbar__prologue_count_inport[10][1] = ctrl_mem__prologue_count_outport_fu_crossbar[10][1]; + assign routing_crossbar__prologue_count_inport[11][0] = ctrl_mem__prologue_count_outport_routing_crossbar[11][0]; + assign routing_crossbar__prologue_count_inport[11][1] = ctrl_mem__prologue_count_outport_routing_crossbar[11][1]; + assign routing_crossbar__prologue_count_inport[11][2] = ctrl_mem__prologue_count_outport_routing_crossbar[11][2]; + assign routing_crossbar__prologue_count_inport[11][3] = ctrl_mem__prologue_count_outport_routing_crossbar[11][3]; + assign fu_crossbar__prologue_count_inport[11][0] = ctrl_mem__prologue_count_outport_fu_crossbar[11][0]; + assign fu_crossbar__prologue_count_inport[11][1] = ctrl_mem__prologue_count_outport_fu_crossbar[11][1]; + assign routing_crossbar__prologue_count_inport[12][0] = ctrl_mem__prologue_count_outport_routing_crossbar[12][0]; + assign routing_crossbar__prologue_count_inport[12][1] = ctrl_mem__prologue_count_outport_routing_crossbar[12][1]; + assign routing_crossbar__prologue_count_inport[12][2] = ctrl_mem__prologue_count_outport_routing_crossbar[12][2]; + assign routing_crossbar__prologue_count_inport[12][3] = ctrl_mem__prologue_count_outport_routing_crossbar[12][3]; + assign fu_crossbar__prologue_count_inport[12][0] = ctrl_mem__prologue_count_outport_fu_crossbar[12][0]; + assign fu_crossbar__prologue_count_inport[12][1] = ctrl_mem__prologue_count_outport_fu_crossbar[12][1]; + assign routing_crossbar__prologue_count_inport[13][0] = ctrl_mem__prologue_count_outport_routing_crossbar[13][0]; + assign routing_crossbar__prologue_count_inport[13][1] = ctrl_mem__prologue_count_outport_routing_crossbar[13][1]; + assign routing_crossbar__prologue_count_inport[13][2] = ctrl_mem__prologue_count_outport_routing_crossbar[13][2]; + assign routing_crossbar__prologue_count_inport[13][3] = ctrl_mem__prologue_count_outport_routing_crossbar[13][3]; + assign fu_crossbar__prologue_count_inport[13][0] = ctrl_mem__prologue_count_outport_fu_crossbar[13][0]; + assign fu_crossbar__prologue_count_inport[13][1] = ctrl_mem__prologue_count_outport_fu_crossbar[13][1]; + assign routing_crossbar__prologue_count_inport[14][0] = ctrl_mem__prologue_count_outport_routing_crossbar[14][0]; + assign routing_crossbar__prologue_count_inport[14][1] = ctrl_mem__prologue_count_outport_routing_crossbar[14][1]; + assign routing_crossbar__prologue_count_inport[14][2] = ctrl_mem__prologue_count_outport_routing_crossbar[14][2]; + assign routing_crossbar__prologue_count_inport[14][3] = ctrl_mem__prologue_count_outport_routing_crossbar[14][3]; + assign fu_crossbar__prologue_count_inport[14][0] = ctrl_mem__prologue_count_outport_fu_crossbar[14][0]; + assign fu_crossbar__prologue_count_inport[14][1] = ctrl_mem__prologue_count_outport_fu_crossbar[14][1]; + assign routing_crossbar__prologue_count_inport[15][0] = ctrl_mem__prologue_count_outport_routing_crossbar[15][0]; + assign routing_crossbar__prologue_count_inport[15][1] = ctrl_mem__prologue_count_outport_routing_crossbar[15][1]; + assign routing_crossbar__prologue_count_inport[15][2] = ctrl_mem__prologue_count_outport_routing_crossbar[15][2]; + assign routing_crossbar__prologue_count_inport[15][3] = ctrl_mem__prologue_count_outport_routing_crossbar[15][3]; + assign fu_crossbar__prologue_count_inport[15][0] = ctrl_mem__prologue_count_outport_fu_crossbar[15][0]; + assign fu_crossbar__prologue_count_inport[15][1] = ctrl_mem__prologue_count_outport_fu_crossbar[15][1]; + assign element__to_mem_raddr__rdy[0] = 1'd0; + assign element__from_mem_rdata__val[0] = 1'd0; + assign element__from_mem_rdata__msg[0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[0] = 1'd0; + assign element__to_mem_wdata__rdy[0] = 1'd0; + assign element__to_mem_raddr__rdy[1] = 1'd0; + assign element__from_mem_rdata__val[1] = 1'd0; + assign element__from_mem_rdata__msg[1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[1] = 1'd0; + assign element__to_mem_wdata__rdy[1] = 1'd0; + assign element__to_mem_raddr__rdy[2] = 1'd0; + assign element__from_mem_rdata__val[2] = 1'd0; + assign element__from_mem_rdata__msg[2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[2] = 1'd0; + assign element__to_mem_wdata__rdy[2] = 1'd0; + assign element__to_mem_raddr__rdy[3] = 1'd0; + assign element__from_mem_rdata__val[3] = 1'd0; + assign element__from_mem_rdata__msg[3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[3] = 1'd0; + assign element__to_mem_wdata__rdy[3] = 1'd0; + assign element__to_mem_raddr__rdy[4] = 1'd0; + assign element__from_mem_rdata__val[4] = 1'd0; + assign element__from_mem_rdata__msg[4] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[4] = 1'd0; + assign element__to_mem_wdata__rdy[4] = 1'd0; + assign element__to_mem_raddr__rdy[5] = 1'd0; + assign element__from_mem_rdata__val[5] = 1'd0; + assign element__from_mem_rdata__msg[5] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[5] = 1'd0; + assign element__to_mem_wdata__rdy[5] = 1'd0; + assign element__to_mem_raddr__rdy[6] = 1'd0; + assign element__from_mem_rdata__val[6] = 1'd0; + assign element__from_mem_rdata__msg[6] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[6] = 1'd0; + assign element__to_mem_wdata__rdy[6] = 1'd0; + assign to_mem_raddr__msg = element__to_mem_raddr__msg[7]; + assign element__to_mem_raddr__rdy[7] = to_mem_raddr__rdy; + assign to_mem_raddr__val = element__to_mem_raddr__val[7]; + assign element__from_mem_rdata__msg[7] = from_mem_rdata__msg; + assign from_mem_rdata__rdy = element__from_mem_rdata__rdy[7]; + assign element__from_mem_rdata__val[7] = from_mem_rdata__val; + assign to_mem_waddr__msg = element__to_mem_waddr__msg[7]; + assign element__to_mem_waddr__rdy[7] = to_mem_waddr__rdy; + assign to_mem_waddr__val = element__to_mem_waddr__val[7]; + assign to_mem_wdata__msg = element__to_mem_wdata__msg[7]; + assign element__to_mem_wdata__rdy[7] = to_mem_wdata__rdy; + assign to_mem_wdata__val = element__to_mem_wdata__val[7]; + assign element__to_mem_raddr__rdy[8] = 1'd0; + assign element__from_mem_rdata__val[8] = 1'd0; + assign element__from_mem_rdata__msg[8] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[8] = 1'd0; + assign element__to_mem_wdata__rdy[8] = 1'd0; + assign element__to_mem_raddr__rdy[9] = 1'd0; + assign element__from_mem_rdata__val[9] = 1'd0; + assign element__from_mem_rdata__msg[9] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[9] = 1'd0; + assign element__to_mem_wdata__rdy[9] = 1'd0; + assign element__to_mem_raddr__rdy[10] = 1'd0; + assign element__from_mem_rdata__val[10] = 1'd0; + assign element__from_mem_rdata__msg[10] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[10] = 1'd0; + assign element__to_mem_wdata__rdy[10] = 1'd0; + assign element__to_mem_raddr__rdy[11] = 1'd0; + assign element__from_mem_rdata__val[11] = 1'd0; + assign element__from_mem_rdata__msg[11] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[11] = 1'd0; + assign element__to_mem_wdata__rdy[11] = 1'd0; + assign element__to_mem_raddr__rdy[12] = 1'd0; + assign element__from_mem_rdata__val[12] = 1'd0; + assign element__from_mem_rdata__msg[12] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[12] = 1'd0; + assign element__to_mem_wdata__rdy[12] = 1'd0; + assign element__to_mem_raddr__rdy[13] = 1'd0; + assign element__from_mem_rdata__val[13] = 1'd0; + assign element__from_mem_rdata__msg[13] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[13] = 1'd0; + assign element__to_mem_wdata__rdy[13] = 1'd0; + assign element__to_mem_raddr__rdy[14] = 1'd0; + assign element__from_mem_rdata__val[14] = 1'd0; + assign element__from_mem_rdata__msg[14] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[14] = 1'd0; + assign element__to_mem_wdata__rdy[14] = 1'd0; + assign tile_in_channel__recv__msg[0] = recv_data__msg[0]; + assign recv_data__rdy[0] = tile_in_channel__recv__rdy[0]; + assign tile_in_channel__recv__val[0] = recv_data__val[0]; + assign routing_crossbar__recv_data__msg[0] = tile_in_channel__send__msg[0]; + assign tile_in_channel__send__rdy[0] = routing_crossbar__recv_data__rdy[0]; + assign routing_crossbar__recv_data__val[0] = tile_in_channel__send__val[0]; + assign tile_in_channel__recv__msg[1] = recv_data__msg[1]; + assign recv_data__rdy[1] = tile_in_channel__recv__rdy[1]; + assign tile_in_channel__recv__val[1] = recv_data__val[1]; + assign routing_crossbar__recv_data__msg[1] = tile_in_channel__send__msg[1]; + assign tile_in_channel__send__rdy[1] = routing_crossbar__recv_data__rdy[1]; + assign routing_crossbar__recv_data__val[1] = tile_in_channel__send__val[1]; + assign tile_in_channel__recv__msg[2] = recv_data__msg[2]; + assign recv_data__rdy[2] = tile_in_channel__recv__rdy[2]; + assign tile_in_channel__recv__val[2] = recv_data__val[2]; + assign routing_crossbar__recv_data__msg[2] = tile_in_channel__send__msg[2]; + assign tile_in_channel__send__rdy[2] = routing_crossbar__recv_data__rdy[2]; + assign routing_crossbar__recv_data__val[2] = tile_in_channel__send__val[2]; + assign tile_in_channel__recv__msg[3] = recv_data__msg[3]; + assign recv_data__rdy[3] = tile_in_channel__recv__rdy[3]; + assign tile_in_channel__recv__val[3] = recv_data__val[3]; + assign routing_crossbar__recv_data__msg[3] = tile_in_channel__send__msg[3]; + assign tile_in_channel__send__rdy[3] = routing_crossbar__recv_data__rdy[3]; + assign routing_crossbar__recv_data__val[3] = tile_in_channel__send__val[3]; + assign routing_crossbar__crossbar_outport[0] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[0]; + assign fu_crossbar__crossbar_outport[0] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[0]; + assign routing_crossbar__crossbar_outport[1] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[1]; + assign fu_crossbar__crossbar_outport[1] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[1]; + assign routing_crossbar__crossbar_outport[2] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[2]; + assign fu_crossbar__crossbar_outport[2] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[2]; + assign routing_crossbar__crossbar_outport[3] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[3]; + assign fu_crossbar__crossbar_outport[3] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[3]; + assign routing_crossbar__crossbar_outport[4] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[4]; + assign fu_crossbar__crossbar_outport[4] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[4]; + assign routing_crossbar__crossbar_outport[5] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[5]; + assign fu_crossbar__crossbar_outport[5] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[5]; + assign routing_crossbar__crossbar_outport[6] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[6]; + assign fu_crossbar__crossbar_outport[6] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[6]; + assign routing_crossbar__crossbar_outport[7] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[7]; + assign fu_crossbar__crossbar_outport[7] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[7]; + assign fu_crossbar__recv_data__msg[0] = element__send_out__msg[0]; + assign element__send_out__rdy[0] = fu_crossbar__recv_data__rdy[0]; + assign fu_crossbar__recv_data__val[0] = element__send_out__val[0]; + assign fu_crossbar__recv_data__msg[1] = element__send_out__msg[1]; + assign element__send_out__rdy[1] = fu_crossbar__recv_data__rdy[1]; + assign fu_crossbar__recv_data__val[1] = element__send_out__val[1]; + assign tile_out_or_link__recv_fu__msg[0] = fu_crossbar__send_data__msg[0]; + assign fu_crossbar__send_data__rdy[0] = tile_out_or_link__recv_fu__rdy[0]; + assign tile_out_or_link__recv_fu__val[0] = fu_crossbar__send_data__val[0]; + assign tile_out_or_link__recv_xbar__msg[0] = routing_crossbar__send_data__msg[0]; + assign routing_crossbar__send_data__rdy[0] = tile_out_or_link__recv_xbar__rdy[0]; + assign tile_out_or_link__recv_xbar__val[0] = routing_crossbar__send_data__val[0]; + assign send_data__msg[0] = tile_out_or_link__send__msg[0]; + assign tile_out_or_link__send__rdy[0] = send_data__rdy[0]; + assign send_data__val[0] = tile_out_or_link__send__val[0]; + assign tile_out_or_link__recv_fu__msg[1] = fu_crossbar__send_data__msg[1]; + assign fu_crossbar__send_data__rdy[1] = tile_out_or_link__recv_fu__rdy[1]; + assign tile_out_or_link__recv_fu__val[1] = fu_crossbar__send_data__val[1]; + assign tile_out_or_link__recv_xbar__msg[1] = routing_crossbar__send_data__msg[1]; + assign routing_crossbar__send_data__rdy[1] = tile_out_or_link__recv_xbar__rdy[1]; + assign tile_out_or_link__recv_xbar__val[1] = routing_crossbar__send_data__val[1]; + assign send_data__msg[1] = tile_out_or_link__send__msg[1]; + assign tile_out_or_link__send__rdy[1] = send_data__rdy[1]; + assign send_data__val[1] = tile_out_or_link__send__val[1]; + assign tile_out_or_link__recv_fu__msg[2] = fu_crossbar__send_data__msg[2]; + assign fu_crossbar__send_data__rdy[2] = tile_out_or_link__recv_fu__rdy[2]; + assign tile_out_or_link__recv_fu__val[2] = fu_crossbar__send_data__val[2]; + assign tile_out_or_link__recv_xbar__msg[2] = routing_crossbar__send_data__msg[2]; + assign routing_crossbar__send_data__rdy[2] = tile_out_or_link__recv_xbar__rdy[2]; + assign tile_out_or_link__recv_xbar__val[2] = routing_crossbar__send_data__val[2]; + assign send_data__msg[2] = tile_out_or_link__send__msg[2]; + assign tile_out_or_link__send__rdy[2] = send_data__rdy[2]; + assign send_data__val[2] = tile_out_or_link__send__val[2]; + assign tile_out_or_link__recv_fu__msg[3] = fu_crossbar__send_data__msg[3]; + assign fu_crossbar__send_data__rdy[3] = tile_out_or_link__recv_fu__rdy[3]; + assign tile_out_or_link__recv_fu__val[3] = fu_crossbar__send_data__val[3]; + assign tile_out_or_link__recv_xbar__msg[3] = routing_crossbar__send_data__msg[3]; + assign routing_crossbar__send_data__rdy[3] = tile_out_or_link__recv_xbar__rdy[3]; + assign tile_out_or_link__recv_xbar__val[3] = routing_crossbar__send_data__val[3]; + assign send_data__msg[3] = tile_out_or_link__send__msg[3]; + assign tile_out_or_link__send__rdy[3] = send_data__rdy[3]; + assign send_data__val[3] = tile_out_or_link__send__val[3]; + assign register_cluster__recv_data_from_routing_crossbar__msg[0] = routing_crossbar__send_data__msg[4]; + assign routing_crossbar__send_data__rdy[4] = register_cluster__recv_data_from_routing_crossbar__rdy[0]; + assign register_cluster__recv_data_from_routing_crossbar__val[0] = routing_crossbar__send_data__val[4]; + assign register_cluster__recv_data_from_fu_crossbar__msg[0] = fu_crossbar__send_data__msg[4]; + assign fu_crossbar__send_data__rdy[4] = register_cluster__recv_data_from_fu_crossbar__rdy[0]; + assign register_cluster__recv_data_from_fu_crossbar__val[0] = fu_crossbar__send_data__val[4]; + assign register_cluster__recv_data_from_const__msg[0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign register_cluster__recv_data_from_const__val[0] = 1'd0; + assign element__recv_in__msg[0] = register_cluster__send_data_to_fu__msg[0]; + assign register_cluster__send_data_to_fu__rdy[0] = element__recv_in__rdy[0]; + assign element__recv_in__val[0] = register_cluster__send_data_to_fu__val[0]; + assign register_cluster__inport_opt = ctrl_mem__send_ctrl__msg; + assign register_cluster__recv_data_from_routing_crossbar__msg[1] = routing_crossbar__send_data__msg[5]; + assign routing_crossbar__send_data__rdy[5] = register_cluster__recv_data_from_routing_crossbar__rdy[1]; + assign register_cluster__recv_data_from_routing_crossbar__val[1] = routing_crossbar__send_data__val[5]; + assign register_cluster__recv_data_from_fu_crossbar__msg[1] = fu_crossbar__send_data__msg[5]; + assign fu_crossbar__send_data__rdy[5] = register_cluster__recv_data_from_fu_crossbar__rdy[1]; + assign register_cluster__recv_data_from_fu_crossbar__val[1] = fu_crossbar__send_data__val[5]; + assign register_cluster__recv_data_from_const__msg[1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign register_cluster__recv_data_from_const__val[1] = 1'd0; + assign element__recv_in__msg[1] = register_cluster__send_data_to_fu__msg[1]; + assign register_cluster__send_data_to_fu__rdy[1] = element__recv_in__rdy[1]; + assign element__recv_in__val[1] = register_cluster__send_data_to_fu__val[1]; + assign register_cluster__recv_data_from_routing_crossbar__msg[2] = routing_crossbar__send_data__msg[6]; + assign routing_crossbar__send_data__rdy[6] = register_cluster__recv_data_from_routing_crossbar__rdy[2]; + assign register_cluster__recv_data_from_routing_crossbar__val[2] = routing_crossbar__send_data__val[6]; + assign register_cluster__recv_data_from_fu_crossbar__msg[2] = fu_crossbar__send_data__msg[6]; + assign fu_crossbar__send_data__rdy[6] = register_cluster__recv_data_from_fu_crossbar__rdy[2]; + assign register_cluster__recv_data_from_fu_crossbar__val[2] = fu_crossbar__send_data__val[6]; + assign register_cluster__recv_data_from_const__msg[2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign register_cluster__recv_data_from_const__val[2] = 1'd0; + assign element__recv_in__msg[2] = register_cluster__send_data_to_fu__msg[2]; + assign register_cluster__send_data_to_fu__rdy[2] = element__recv_in__rdy[2]; + assign element__recv_in__val[2] = register_cluster__send_data_to_fu__val[2]; + assign register_cluster__recv_data_from_routing_crossbar__msg[3] = routing_crossbar__send_data__msg[7]; + assign routing_crossbar__send_data__rdy[7] = register_cluster__recv_data_from_routing_crossbar__rdy[3]; + assign register_cluster__recv_data_from_routing_crossbar__val[3] = routing_crossbar__send_data__val[7]; + assign register_cluster__recv_data_from_fu_crossbar__msg[3] = fu_crossbar__send_data__msg[7]; + assign fu_crossbar__send_data__rdy[7] = register_cluster__recv_data_from_fu_crossbar__rdy[3]; + assign register_cluster__recv_data_from_fu_crossbar__val[3] = fu_crossbar__send_data__val[7]; + assign register_cluster__recv_data_from_const__msg[3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign register_cluster__recv_data_from_const__val[3] = 1'd0; + assign element__recv_in__msg[3] = register_cluster__send_data_to_fu__msg[3]; + assign register_cluster__send_data_to_fu__rdy[3] = element__recv_in__rdy[3]; + assign element__recv_in__val[3] = register_cluster__send_data_to_fu__val[3]; + assign element__clear[0] = 1'd0; + assign element__clear[1] = 1'd0; + assign element__clear[2] = 1'd0; + assign element__clear[3] = 1'd0; + assign element__clear[4] = 1'd0; + assign element__clear[5] = 1'd0; + assign element__clear[6] = 1'd0; + assign element__clear[7] = 1'd0; + assign element__clear[8] = 1'd0; + assign element__clear[9] = 1'd0; + assign element__clear[10] = 1'd0; + assign element__clear[11] = 1'd0; + assign element__clear[12] = 1'd0; + assign element__clear[13] = 1'd0; + assign element__clear[14] = 1'd0; + assign fu_crossbar__clear = 1'd0; + assign routing_crossbar__clear = 1'd0; + +endmodule + + +// PyMTL Component CgraRTL Definition +// Full name: CgraRTL__CgraPayloadType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__multi_cgra_rows_2__multi_cgra_columns_2__width_4__height_4__ctrl_mem_size_16__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_registers_per_reg_bank_16__num_ctrl_4__total_steps_38__mem_access_is_combinational_True__FunctionUnit_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ]__cgra_topology_Mesh__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)}__is_multi_cgra_True__has_ctrl_ring_True +// At /home/ajokai/cgra/VectorCGRAfork0/cgra/CgraRTL.py + +module CgraRTL__72d915b46abe89cb +( + input logic [6:0] address_lower , + input logic [6:0] address_upper , + input logic [1:0] cgra_id , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_east__msg [0:3] , + output logic [0:0] recv_data_on_boundary_east__rdy [0:3] , + input logic [0:0] recv_data_on_boundary_east__val [0:3] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_north__msg [0:3] , + output logic [0:0] recv_data_on_boundary_north__rdy [0:3] , + input logic [0:0] recv_data_on_boundary_north__val [0:3] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_south__msg [0:3] , + output logic [0:0] recv_data_on_boundary_south__rdy [0:3] , + input logic [0:0] recv_data_on_boundary_south__val [0:3] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_west__msg [0:3] , + output logic [0:0] recv_data_on_boundary_west__rdy [0:3] , + input logic [0:0] recv_data_on_boundary_west__val [0:3] , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , + output logic [0:0] recv_from_cpu_pkt__rdy , + input logic [0:0] recv_from_cpu_pkt__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_inter_cgra_noc__msg , + output logic [0:0] recv_from_inter_cgra_noc__rdy , + input logic [0:0] recv_from_inter_cgra_noc__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_east__msg [0:3] , + input logic [0:0] send_data_on_boundary_east__rdy [0:3] , + output logic [0:0] send_data_on_boundary_east__val [0:3] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_north__msg [0:3] , + input logic [0:0] send_data_on_boundary_north__rdy [0:3] , + output logic [0:0] send_data_on_boundary_north__val [0:3] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_south__msg [0:3] , + input logic [0:0] send_data_on_boundary_south__rdy [0:3] , + output logic [0:0] send_data_on_boundary_south__val [0:3] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_west__msg [0:3] , + input logic [0:0] send_data_on_boundary_west__rdy [0:3] , + output logic [0:0] send_data_on_boundary_west__val [0:3] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , + input logic [0:0] send_to_cpu_pkt__rdy , + output logic [0:0] send_to_cpu_pkt__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_inter_cgra_noc__msg , + input logic [0:0] send_to_inter_cgra_noc__rdy , + output logic [0:0] send_to_inter_cgra_noc__val +); + //------------------------------------------------------------- + // Component controller + //------------------------------------------------------------- + + logic [1:0] controller__cgra_id; + logic [0:0] controller__clk; + logic [0:0] controller__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__recv_from_cpu_pkt__msg; + logic [0:0] controller__recv_from_cpu_pkt__rdy; + logic [0:0] controller__recv_from_cpu_pkt__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__recv_from_ctrl_ring_pkt__msg; + logic [0:0] controller__recv_from_ctrl_ring_pkt__rdy; + logic [0:0] controller__recv_from_ctrl_ring_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_inter_cgra_noc__msg; + logic [0:0] controller__recv_from_inter_cgra_noc__rdy; + logic [0:0] controller__recv_from_inter_cgra_noc__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_load_request_pkt__msg; + logic [0:0] controller__recv_from_tile_load_request_pkt__rdy; + logic [0:0] controller__recv_from_tile_load_request_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_load_response_pkt__msg; + logic [0:0] controller__recv_from_tile_load_response_pkt__rdy; + logic [0:0] controller__recv_from_tile_load_response_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_store_request_pkt__msg; + logic [0:0] controller__recv_from_tile_store_request_pkt__rdy; + logic [0:0] controller__recv_from_tile_store_request_pkt__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__send_to_cpu_pkt__msg; + logic [0:0] controller__send_to_cpu_pkt__rdy; + logic [0:0] controller__send_to_cpu_pkt__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__send_to_ctrl_ring_pkt__msg; + logic [0:0] controller__send_to_ctrl_ring_pkt__rdy; + logic [0:0] controller__send_to_ctrl_ring_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_inter_cgra_noc__msg; + logic [0:0] controller__send_to_inter_cgra_noc__rdy; + logic [0:0] controller__send_to_inter_cgra_noc__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_mem_load_request__msg; + logic [0:0] controller__send_to_mem_load_request__rdy; + logic [0:0] controller__send_to_mem_load_request__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_mem_store_request__msg; + logic [0:0] controller__send_to_mem_store_request__rdy; + logic [0:0] controller__send_to_mem_store_request__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_tile_load_response__msg; + logic [0:0] controller__send_to_tile_load_response__rdy; + logic [0:0] controller__send_to_tile_load_response__val; + + ControllerRTL__e06602ce343fdc8d controller + ( + .cgra_id( controller__cgra_id ), + .clk( controller__clk ), + .reset( controller__reset ), + .recv_from_cpu_pkt__msg( controller__recv_from_cpu_pkt__msg ), + .recv_from_cpu_pkt__rdy( controller__recv_from_cpu_pkt__rdy ), + .recv_from_cpu_pkt__val( controller__recv_from_cpu_pkt__val ), + .recv_from_ctrl_ring_pkt__msg( controller__recv_from_ctrl_ring_pkt__msg ), + .recv_from_ctrl_ring_pkt__rdy( controller__recv_from_ctrl_ring_pkt__rdy ), + .recv_from_ctrl_ring_pkt__val( controller__recv_from_ctrl_ring_pkt__val ), + .recv_from_inter_cgra_noc__msg( controller__recv_from_inter_cgra_noc__msg ), + .recv_from_inter_cgra_noc__rdy( controller__recv_from_inter_cgra_noc__rdy ), + .recv_from_inter_cgra_noc__val( controller__recv_from_inter_cgra_noc__val ), + .recv_from_tile_load_request_pkt__msg( controller__recv_from_tile_load_request_pkt__msg ), + .recv_from_tile_load_request_pkt__rdy( controller__recv_from_tile_load_request_pkt__rdy ), + .recv_from_tile_load_request_pkt__val( controller__recv_from_tile_load_request_pkt__val ), + .recv_from_tile_load_response_pkt__msg( controller__recv_from_tile_load_response_pkt__msg ), + .recv_from_tile_load_response_pkt__rdy( controller__recv_from_tile_load_response_pkt__rdy ), + .recv_from_tile_load_response_pkt__val( controller__recv_from_tile_load_response_pkt__val ), + .recv_from_tile_store_request_pkt__msg( controller__recv_from_tile_store_request_pkt__msg ), + .recv_from_tile_store_request_pkt__rdy( controller__recv_from_tile_store_request_pkt__rdy ), + .recv_from_tile_store_request_pkt__val( controller__recv_from_tile_store_request_pkt__val ), + .send_to_cpu_pkt__msg( controller__send_to_cpu_pkt__msg ), + .send_to_cpu_pkt__rdy( controller__send_to_cpu_pkt__rdy ), + .send_to_cpu_pkt__val( controller__send_to_cpu_pkt__val ), + .send_to_ctrl_ring_pkt__msg( controller__send_to_ctrl_ring_pkt__msg ), + .send_to_ctrl_ring_pkt__rdy( controller__send_to_ctrl_ring_pkt__rdy ), + .send_to_ctrl_ring_pkt__val( controller__send_to_ctrl_ring_pkt__val ), + .send_to_inter_cgra_noc__msg( controller__send_to_inter_cgra_noc__msg ), + .send_to_inter_cgra_noc__rdy( controller__send_to_inter_cgra_noc__rdy ), + .send_to_inter_cgra_noc__val( controller__send_to_inter_cgra_noc__val ), + .send_to_mem_load_request__msg( controller__send_to_mem_load_request__msg ), + .send_to_mem_load_request__rdy( controller__send_to_mem_load_request__rdy ), + .send_to_mem_load_request__val( controller__send_to_mem_load_request__val ), + .send_to_mem_store_request__msg( controller__send_to_mem_store_request__msg ), + .send_to_mem_store_request__rdy( controller__send_to_mem_store_request__rdy ), + .send_to_mem_store_request__val( controller__send_to_mem_store_request__val ), + .send_to_tile_load_response__msg( controller__send_to_tile_load_response__msg ), + .send_to_tile_load_response__rdy( controller__send_to_tile_load_response__rdy ), + .send_to_tile_load_response__val( controller__send_to_tile_load_response__val ) + ); + + //------------------------------------------------------------- + // End of component controller + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component ctrl_ring + //------------------------------------------------------------- + + logic [0:0] ctrl_ring__clk; + logic [0:0] ctrl_ring__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_ring__recv__msg [0:16]; + logic [0:0] ctrl_ring__recv__rdy [0:16]; + logic [0:0] ctrl_ring__recv__val [0:16]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_ring__send__msg [0:16]; + logic [0:0] ctrl_ring__send__rdy [0:16]; + logic [0:0] ctrl_ring__send__val [0:16]; + + RingNetworkRTL__8866f4e00dbc912a ctrl_ring + ( + .clk( ctrl_ring__clk ), + .reset( ctrl_ring__reset ), + .recv__msg( ctrl_ring__recv__msg ), + .recv__rdy( ctrl_ring__recv__rdy ), + .recv__val( ctrl_ring__recv__val ), + .send__msg( ctrl_ring__send__msg ), + .send__rdy( ctrl_ring__send__rdy ), + .send__val( ctrl_ring__send__val ) + ); + + //------------------------------------------------------------- + // End of component ctrl_ring + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component data_mem + //------------------------------------------------------------- + + logic [6:0] data_mem__address_lower; + logic [6:0] data_mem__address_upper; + logic [1:0] data_mem__cgra_id; + logic [0:0] data_mem__clk; + logic [0:0] data_mem__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_load_request__msg; + logic [0:0] data_mem__recv_from_noc_load_request__rdy; + logic [0:0] data_mem__recv_from_noc_load_request__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_load_response_pkt__msg; + logic [0:0] data_mem__recv_from_noc_load_response_pkt__rdy; + logic [0:0] data_mem__recv_from_noc_load_response_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_store_request__msg; + logic [0:0] data_mem__recv_from_noc_store_request__rdy; + logic [0:0] data_mem__recv_from_noc_store_request__val; + logic [6:0] data_mem__recv_raddr__msg [0:6]; + logic [0:0] data_mem__recv_raddr__rdy [0:6]; + logic [0:0] data_mem__recv_raddr__val [0:6]; + logic [6:0] data_mem__recv_waddr__msg [0:6]; + logic [0:0] data_mem__recv_waddr__rdy [0:6]; + logic [0:0] data_mem__recv_waddr__val [0:6]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data_mem__recv_wdata__msg [0:6]; + logic [0:0] data_mem__recv_wdata__rdy [0:6]; + logic [0:0] data_mem__recv_wdata__val [0:6]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data_mem__send_rdata__msg [0:6]; + logic [0:0] data_mem__send_rdata__rdy [0:6]; + logic [0:0] data_mem__send_rdata__val [0:6]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_load_request_pkt__msg; + logic [0:0] data_mem__send_to_noc_load_request_pkt__rdy; + logic [0:0] data_mem__send_to_noc_load_request_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_load_response_pkt__msg; + logic [0:0] data_mem__send_to_noc_load_response_pkt__rdy; + logic [0:0] data_mem__send_to_noc_load_response_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_store_pkt__msg; + logic [0:0] data_mem__send_to_noc_store_pkt__rdy; + logic [0:0] data_mem__send_to_noc_store_pkt__val; + + DataMemControllerRTL__20df9b544ed809f0 data_mem + ( + .address_lower( data_mem__address_lower ), + .address_upper( data_mem__address_upper ), + .cgra_id( data_mem__cgra_id ), + .clk( data_mem__clk ), + .reset( data_mem__reset ), + .recv_from_noc_load_request__msg( data_mem__recv_from_noc_load_request__msg ), + .recv_from_noc_load_request__rdy( data_mem__recv_from_noc_load_request__rdy ), + .recv_from_noc_load_request__val( data_mem__recv_from_noc_load_request__val ), + .recv_from_noc_load_response_pkt__msg( data_mem__recv_from_noc_load_response_pkt__msg ), + .recv_from_noc_load_response_pkt__rdy( data_mem__recv_from_noc_load_response_pkt__rdy ), + .recv_from_noc_load_response_pkt__val( data_mem__recv_from_noc_load_response_pkt__val ), + .recv_from_noc_store_request__msg( data_mem__recv_from_noc_store_request__msg ), + .recv_from_noc_store_request__rdy( data_mem__recv_from_noc_store_request__rdy ), + .recv_from_noc_store_request__val( data_mem__recv_from_noc_store_request__val ), + .recv_raddr__msg( data_mem__recv_raddr__msg ), + .recv_raddr__rdy( data_mem__recv_raddr__rdy ), + .recv_raddr__val( data_mem__recv_raddr__val ), + .recv_waddr__msg( data_mem__recv_waddr__msg ), + .recv_waddr__rdy( data_mem__recv_waddr__rdy ), + .recv_waddr__val( data_mem__recv_waddr__val ), + .recv_wdata__msg( data_mem__recv_wdata__msg ), + .recv_wdata__rdy( data_mem__recv_wdata__rdy ), + .recv_wdata__val( data_mem__recv_wdata__val ), + .send_rdata__msg( data_mem__send_rdata__msg ), + .send_rdata__rdy( data_mem__send_rdata__rdy ), + .send_rdata__val( data_mem__send_rdata__val ), + .send_to_noc_load_request_pkt__msg( data_mem__send_to_noc_load_request_pkt__msg ), + .send_to_noc_load_request_pkt__rdy( data_mem__send_to_noc_load_request_pkt__rdy ), + .send_to_noc_load_request_pkt__val( data_mem__send_to_noc_load_request_pkt__val ), + .send_to_noc_load_response_pkt__msg( data_mem__send_to_noc_load_response_pkt__msg ), + .send_to_noc_load_response_pkt__rdy( data_mem__send_to_noc_load_response_pkt__rdy ), + .send_to_noc_load_response_pkt__val( data_mem__send_to_noc_load_response_pkt__val ), + .send_to_noc_store_pkt__msg( data_mem__send_to_noc_store_pkt__msg ), + .send_to_noc_store_pkt__rdy( data_mem__send_to_noc_store_pkt__rdy ), + .send_to_noc_store_pkt__val( data_mem__send_to_noc_store_pkt__val ) + ); + + //------------------------------------------------------------- + // End of component data_mem + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component tile[0:15] + //------------------------------------------------------------- + + logic [1:0] tile__cgra_id [0:15]; + logic [0:0] tile__clk [0:15]; + logic [0:0] tile__reset [0:15]; + logic [4:0] tile__tile_id [0:15]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__from_mem_rdata__msg [0:15]; + logic [0:0] tile__from_mem_rdata__rdy [0:15]; + logic [0:0] tile__from_mem_rdata__val [0:15]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__recv_data__msg [0:15][0:3]; + logic [0:0] tile__recv_data__rdy [0:15][0:3]; + logic [0:0] tile__recv_data__val [0:15][0:3]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 tile__recv_from_controller_pkt__msg [0:15]; + logic [0:0] tile__recv_from_controller_pkt__rdy [0:15]; + logic [0:0] tile__recv_from_controller_pkt__val [0:15]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__send_data__msg [0:15][0:3]; + logic [0:0] tile__send_data__rdy [0:15][0:3]; + logic [0:0] tile__send_data__val [0:15][0:3]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 tile__send_to_controller_pkt__msg [0:15]; + logic [0:0] tile__send_to_controller_pkt__rdy [0:15]; + logic [0:0] tile__send_to_controller_pkt__val [0:15]; + logic [6:0] tile__to_mem_raddr__msg [0:15]; + logic [0:0] tile__to_mem_raddr__rdy [0:15]; + logic [0:0] tile__to_mem_raddr__val [0:15]; + logic [6:0] tile__to_mem_waddr__msg [0:15]; + logic [0:0] tile__to_mem_waddr__rdy [0:15]; + logic [0:0] tile__to_mem_waddr__val [0:15]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__to_mem_wdata__msg [0:15]; + logic [0:0] tile__to_mem_wdata__rdy [0:15]; + logic [0:0] tile__to_mem_wdata__val [0:15]; + + TileRTL__78da5e3970e1cd1d tile__0 + ( + .cgra_id( tile__cgra_id[0] ), + .clk( tile__clk[0] ), + .reset( tile__reset[0] ), + .tile_id( tile__tile_id[0] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[0] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[0] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[0] ), + .recv_data__msg( tile__recv_data__msg[0] ), + .recv_data__rdy( tile__recv_data__rdy[0] ), + .recv_data__val( tile__recv_data__val[0] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[0] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[0] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[0] ), + .send_data__msg( tile__send_data__msg[0] ), + .send_data__rdy( tile__send_data__rdy[0] ), + .send_data__val( tile__send_data__val[0] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[0] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[0] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[0] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[0] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[0] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[0] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[0] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[0] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[0] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[0] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[0] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[0] ) + ); + + TileRTL__78da5e3970e1cd1d tile__1 + ( + .cgra_id( tile__cgra_id[1] ), + .clk( tile__clk[1] ), + .reset( tile__reset[1] ), + .tile_id( tile__tile_id[1] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[1] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[1] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[1] ), + .recv_data__msg( tile__recv_data__msg[1] ), + .recv_data__rdy( tile__recv_data__rdy[1] ), + .recv_data__val( tile__recv_data__val[1] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[1] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[1] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[1] ), + .send_data__msg( tile__send_data__msg[1] ), + .send_data__rdy( tile__send_data__rdy[1] ), + .send_data__val( tile__send_data__val[1] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[1] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[1] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[1] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[1] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[1] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[1] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[1] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[1] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[1] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[1] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[1] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[1] ) + ); + + TileRTL__78da5e3970e1cd1d tile__2 + ( + .cgra_id( tile__cgra_id[2] ), + .clk( tile__clk[2] ), + .reset( tile__reset[2] ), + .tile_id( tile__tile_id[2] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[2] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[2] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[2] ), + .recv_data__msg( tile__recv_data__msg[2] ), + .recv_data__rdy( tile__recv_data__rdy[2] ), + .recv_data__val( tile__recv_data__val[2] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[2] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[2] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[2] ), + .send_data__msg( tile__send_data__msg[2] ), + .send_data__rdy( tile__send_data__rdy[2] ), + .send_data__val( tile__send_data__val[2] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[2] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[2] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[2] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[2] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[2] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[2] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[2] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[2] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[2] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[2] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[2] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[2] ) + ); + + TileRTL__78da5e3970e1cd1d tile__3 + ( + .cgra_id( tile__cgra_id[3] ), + .clk( tile__clk[3] ), + .reset( tile__reset[3] ), + .tile_id( tile__tile_id[3] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[3] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[3] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[3] ), + .recv_data__msg( tile__recv_data__msg[3] ), + .recv_data__rdy( tile__recv_data__rdy[3] ), + .recv_data__val( tile__recv_data__val[3] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[3] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[3] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[3] ), + .send_data__msg( tile__send_data__msg[3] ), + .send_data__rdy( tile__send_data__rdy[3] ), + .send_data__val( tile__send_data__val[3] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[3] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[3] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[3] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[3] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[3] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[3] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[3] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[3] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[3] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[3] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[3] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[3] ) + ); + + TileRTL__78da5e3970e1cd1d tile__4 + ( + .cgra_id( tile__cgra_id[4] ), + .clk( tile__clk[4] ), + .reset( tile__reset[4] ), + .tile_id( tile__tile_id[4] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[4] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[4] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[4] ), + .recv_data__msg( tile__recv_data__msg[4] ), + .recv_data__rdy( tile__recv_data__rdy[4] ), + .recv_data__val( tile__recv_data__val[4] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[4] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[4] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[4] ), + .send_data__msg( tile__send_data__msg[4] ), + .send_data__rdy( tile__send_data__rdy[4] ), + .send_data__val( tile__send_data__val[4] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[4] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[4] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[4] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[4] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[4] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[4] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[4] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[4] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[4] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[4] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[4] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[4] ) + ); + + TileRTL__78da5e3970e1cd1d tile__5 + ( + .cgra_id( tile__cgra_id[5] ), + .clk( tile__clk[5] ), + .reset( tile__reset[5] ), + .tile_id( tile__tile_id[5] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[5] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[5] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[5] ), + .recv_data__msg( tile__recv_data__msg[5] ), + .recv_data__rdy( tile__recv_data__rdy[5] ), + .recv_data__val( tile__recv_data__val[5] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[5] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[5] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[5] ), + .send_data__msg( tile__send_data__msg[5] ), + .send_data__rdy( tile__send_data__rdy[5] ), + .send_data__val( tile__send_data__val[5] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[5] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[5] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[5] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[5] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[5] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[5] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[5] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[5] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[5] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[5] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[5] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[5] ) + ); + + TileRTL__78da5e3970e1cd1d tile__6 + ( + .cgra_id( tile__cgra_id[6] ), + .clk( tile__clk[6] ), + .reset( tile__reset[6] ), + .tile_id( tile__tile_id[6] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[6] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[6] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[6] ), + .recv_data__msg( tile__recv_data__msg[6] ), + .recv_data__rdy( tile__recv_data__rdy[6] ), + .recv_data__val( tile__recv_data__val[6] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[6] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[6] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[6] ), + .send_data__msg( tile__send_data__msg[6] ), + .send_data__rdy( tile__send_data__rdy[6] ), + .send_data__val( tile__send_data__val[6] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[6] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[6] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[6] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[6] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[6] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[6] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[6] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[6] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[6] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[6] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[6] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[6] ) + ); + + TileRTL__78da5e3970e1cd1d tile__7 + ( + .cgra_id( tile__cgra_id[7] ), + .clk( tile__clk[7] ), + .reset( tile__reset[7] ), + .tile_id( tile__tile_id[7] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[7] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[7] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[7] ), + .recv_data__msg( tile__recv_data__msg[7] ), + .recv_data__rdy( tile__recv_data__rdy[7] ), + .recv_data__val( tile__recv_data__val[7] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[7] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[7] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[7] ), + .send_data__msg( tile__send_data__msg[7] ), + .send_data__rdy( tile__send_data__rdy[7] ), + .send_data__val( tile__send_data__val[7] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[7] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[7] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[7] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[7] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[7] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[7] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[7] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[7] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[7] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[7] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[7] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[7] ) + ); + + TileRTL__78da5e3970e1cd1d tile__8 + ( + .cgra_id( tile__cgra_id[8] ), + .clk( tile__clk[8] ), + .reset( tile__reset[8] ), + .tile_id( tile__tile_id[8] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[8] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[8] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[8] ), + .recv_data__msg( tile__recv_data__msg[8] ), + .recv_data__rdy( tile__recv_data__rdy[8] ), + .recv_data__val( tile__recv_data__val[8] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[8] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[8] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[8] ), + .send_data__msg( tile__send_data__msg[8] ), + .send_data__rdy( tile__send_data__rdy[8] ), + .send_data__val( tile__send_data__val[8] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[8] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[8] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[8] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[8] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[8] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[8] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[8] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[8] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[8] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[8] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[8] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[8] ) + ); + + TileRTL__78da5e3970e1cd1d tile__9 + ( + .cgra_id( tile__cgra_id[9] ), + .clk( tile__clk[9] ), + .reset( tile__reset[9] ), + .tile_id( tile__tile_id[9] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[9] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[9] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[9] ), + .recv_data__msg( tile__recv_data__msg[9] ), + .recv_data__rdy( tile__recv_data__rdy[9] ), + .recv_data__val( tile__recv_data__val[9] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[9] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[9] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[9] ), + .send_data__msg( tile__send_data__msg[9] ), + .send_data__rdy( tile__send_data__rdy[9] ), + .send_data__val( tile__send_data__val[9] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[9] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[9] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[9] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[9] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[9] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[9] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[9] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[9] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[9] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[9] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[9] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[9] ) + ); + + TileRTL__78da5e3970e1cd1d tile__10 + ( + .cgra_id( tile__cgra_id[10] ), + .clk( tile__clk[10] ), + .reset( tile__reset[10] ), + .tile_id( tile__tile_id[10] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[10] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[10] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[10] ), + .recv_data__msg( tile__recv_data__msg[10] ), + .recv_data__rdy( tile__recv_data__rdy[10] ), + .recv_data__val( tile__recv_data__val[10] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[10] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[10] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[10] ), + .send_data__msg( tile__send_data__msg[10] ), + .send_data__rdy( tile__send_data__rdy[10] ), + .send_data__val( tile__send_data__val[10] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[10] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[10] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[10] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[10] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[10] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[10] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[10] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[10] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[10] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[10] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[10] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[10] ) + ); + + TileRTL__78da5e3970e1cd1d tile__11 + ( + .cgra_id( tile__cgra_id[11] ), + .clk( tile__clk[11] ), + .reset( tile__reset[11] ), + .tile_id( tile__tile_id[11] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[11] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[11] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[11] ), + .recv_data__msg( tile__recv_data__msg[11] ), + .recv_data__rdy( tile__recv_data__rdy[11] ), + .recv_data__val( tile__recv_data__val[11] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[11] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[11] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[11] ), + .send_data__msg( tile__send_data__msg[11] ), + .send_data__rdy( tile__send_data__rdy[11] ), + .send_data__val( tile__send_data__val[11] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[11] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[11] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[11] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[11] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[11] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[11] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[11] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[11] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[11] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[11] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[11] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[11] ) + ); + + TileRTL__78da5e3970e1cd1d tile__12 + ( + .cgra_id( tile__cgra_id[12] ), + .clk( tile__clk[12] ), + .reset( tile__reset[12] ), + .tile_id( tile__tile_id[12] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[12] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[12] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[12] ), + .recv_data__msg( tile__recv_data__msg[12] ), + .recv_data__rdy( tile__recv_data__rdy[12] ), + .recv_data__val( tile__recv_data__val[12] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[12] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[12] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[12] ), + .send_data__msg( tile__send_data__msg[12] ), + .send_data__rdy( tile__send_data__rdy[12] ), + .send_data__val( tile__send_data__val[12] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[12] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[12] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[12] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[12] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[12] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[12] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[12] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[12] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[12] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[12] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[12] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[12] ) + ); + + TileRTL__78da5e3970e1cd1d tile__13 + ( + .cgra_id( tile__cgra_id[13] ), + .clk( tile__clk[13] ), + .reset( tile__reset[13] ), + .tile_id( tile__tile_id[13] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[13] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[13] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[13] ), + .recv_data__msg( tile__recv_data__msg[13] ), + .recv_data__rdy( tile__recv_data__rdy[13] ), + .recv_data__val( tile__recv_data__val[13] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[13] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[13] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[13] ), + .send_data__msg( tile__send_data__msg[13] ), + .send_data__rdy( tile__send_data__rdy[13] ), + .send_data__val( tile__send_data__val[13] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[13] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[13] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[13] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[13] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[13] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[13] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[13] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[13] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[13] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[13] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[13] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[13] ) + ); + + TileRTL__78da5e3970e1cd1d tile__14 + ( + .cgra_id( tile__cgra_id[14] ), + .clk( tile__clk[14] ), + .reset( tile__reset[14] ), + .tile_id( tile__tile_id[14] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[14] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[14] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[14] ), + .recv_data__msg( tile__recv_data__msg[14] ), + .recv_data__rdy( tile__recv_data__rdy[14] ), + .recv_data__val( tile__recv_data__val[14] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[14] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[14] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[14] ), + .send_data__msg( tile__send_data__msg[14] ), + .send_data__rdy( tile__send_data__rdy[14] ), + .send_data__val( tile__send_data__val[14] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[14] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[14] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[14] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[14] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[14] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[14] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[14] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[14] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[14] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[14] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[14] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[14] ) + ); + + TileRTL__78da5e3970e1cd1d tile__15 + ( + .cgra_id( tile__cgra_id[15] ), + .clk( tile__clk[15] ), + .reset( tile__reset[15] ), + .tile_id( tile__tile_id[15] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[15] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[15] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[15] ), + .recv_data__msg( tile__recv_data__msg[15] ), + .recv_data__rdy( tile__recv_data__rdy[15] ), + .recv_data__val( tile__recv_data__val[15] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[15] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[15] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[15] ), + .send_data__msg( tile__send_data__msg[15] ), + .send_data__rdy( tile__send_data__rdy[15] ), + .send_data__val( tile__send_data__val[15] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[15] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[15] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[15] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[15] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[15] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[15] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[15] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[15] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[15] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[15] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[15] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[15] ) + ); + + //------------------------------------------------------------- + // End of component tile[0:15] + //------------------------------------------------------------- + + assign tile__clk[0] = clk; + assign tile__reset[0] = reset; + assign tile__clk[1] = clk; + assign tile__reset[1] = reset; + assign tile__clk[2] = clk; + assign tile__reset[2] = reset; + assign tile__clk[3] = clk; + assign tile__reset[3] = reset; + assign tile__clk[4] = clk; + assign tile__reset[4] = reset; + assign tile__clk[5] = clk; + assign tile__reset[5] = reset; + assign tile__clk[6] = clk; + assign tile__reset[6] = reset; + assign tile__clk[7] = clk; + assign tile__reset[7] = reset; + assign tile__clk[8] = clk; + assign tile__reset[8] = reset; + assign tile__clk[9] = clk; + assign tile__reset[9] = reset; + assign tile__clk[10] = clk; + assign tile__reset[10] = reset; + assign tile__clk[11] = clk; + assign tile__reset[11] = reset; + assign tile__clk[12] = clk; + assign tile__reset[12] = reset; + assign tile__clk[13] = clk; + assign tile__reset[13] = reset; + assign tile__clk[14] = clk; + assign tile__reset[14] = reset; + assign tile__clk[15] = clk; + assign tile__reset[15] = reset; + assign data_mem__clk = clk; + assign data_mem__reset = reset; + assign controller__clk = clk; + assign controller__reset = reset; + assign ctrl_ring__clk = clk; + assign ctrl_ring__reset = reset; + assign controller__cgra_id = cgra_id; + assign data_mem__cgra_id = cgra_id; + assign data_mem__address_lower = address_lower; + assign data_mem__address_upper = address_upper; + assign data_mem__recv_from_noc_load_request__msg = controller__send_to_mem_load_request__msg; + assign controller__send_to_mem_load_request__rdy = data_mem__recv_from_noc_load_request__rdy; + assign data_mem__recv_from_noc_load_request__val = controller__send_to_mem_load_request__val; + assign data_mem__recv_from_noc_store_request__msg = controller__send_to_mem_store_request__msg; + assign controller__send_to_mem_store_request__rdy = data_mem__recv_from_noc_store_request__rdy; + assign data_mem__recv_from_noc_store_request__val = controller__send_to_mem_store_request__val; + assign data_mem__recv_from_noc_load_response_pkt__msg = controller__send_to_tile_load_response__msg; + assign controller__send_to_tile_load_response__rdy = data_mem__recv_from_noc_load_response_pkt__rdy; + assign data_mem__recv_from_noc_load_response_pkt__val = controller__send_to_tile_load_response__val; + assign controller__recv_from_tile_load_request_pkt__msg = data_mem__send_to_noc_load_request_pkt__msg; + assign data_mem__send_to_noc_load_request_pkt__rdy = controller__recv_from_tile_load_request_pkt__rdy; + assign controller__recv_from_tile_load_request_pkt__val = data_mem__send_to_noc_load_request_pkt__val; + assign controller__recv_from_tile_load_response_pkt__msg = data_mem__send_to_noc_load_response_pkt__msg; + assign data_mem__send_to_noc_load_response_pkt__rdy = controller__recv_from_tile_load_response_pkt__rdy; + assign controller__recv_from_tile_load_response_pkt__val = data_mem__send_to_noc_load_response_pkt__val; + assign controller__recv_from_tile_store_request_pkt__msg = data_mem__send_to_noc_store_pkt__msg; + assign data_mem__send_to_noc_store_pkt__rdy = controller__recv_from_tile_store_request_pkt__rdy; + assign controller__recv_from_tile_store_request_pkt__val = data_mem__send_to_noc_store_pkt__val; + assign controller__recv_from_inter_cgra_noc__msg = recv_from_inter_cgra_noc__msg; + assign recv_from_inter_cgra_noc__rdy = controller__recv_from_inter_cgra_noc__rdy; + assign controller__recv_from_inter_cgra_noc__val = recv_from_inter_cgra_noc__val; + assign send_to_inter_cgra_noc__msg = controller__send_to_inter_cgra_noc__msg; + assign controller__send_to_inter_cgra_noc__rdy = send_to_inter_cgra_noc__rdy; + assign send_to_inter_cgra_noc__val = controller__send_to_inter_cgra_noc__val; + assign controller__recv_from_cpu_pkt__msg = recv_from_cpu_pkt__msg; + assign recv_from_cpu_pkt__rdy = controller__recv_from_cpu_pkt__rdy; + assign controller__recv_from_cpu_pkt__val = recv_from_cpu_pkt__val; + assign send_to_cpu_pkt__msg = controller__send_to_cpu_pkt__msg; + assign controller__send_to_cpu_pkt__rdy = send_to_cpu_pkt__rdy; + assign send_to_cpu_pkt__val = controller__send_to_cpu_pkt__val; + assign tile__tile_id[0] = 5'd0; + assign tile__cgra_id[0] = cgra_id; + assign tile__tile_id[1] = 5'd1; + assign tile__cgra_id[1] = cgra_id; + assign tile__tile_id[2] = 5'd2; + assign tile__cgra_id[2] = cgra_id; + assign tile__tile_id[3] = 5'd3; + assign tile__cgra_id[3] = cgra_id; + assign tile__tile_id[4] = 5'd4; + assign tile__cgra_id[4] = cgra_id; + assign tile__tile_id[5] = 5'd5; + assign tile__cgra_id[5] = cgra_id; + assign tile__tile_id[6] = 5'd6; + assign tile__cgra_id[6] = cgra_id; + assign tile__tile_id[7] = 5'd7; + assign tile__cgra_id[7] = cgra_id; + assign tile__tile_id[8] = 5'd8; + assign tile__cgra_id[8] = cgra_id; + assign tile__tile_id[9] = 5'd9; + assign tile__cgra_id[9] = cgra_id; + assign tile__tile_id[10] = 5'd10; + assign tile__cgra_id[10] = cgra_id; + assign tile__tile_id[11] = 5'd11; + assign tile__cgra_id[11] = cgra_id; + assign tile__tile_id[12] = 5'd12; + assign tile__cgra_id[12] = cgra_id; + assign tile__tile_id[13] = 5'd13; + assign tile__cgra_id[13] = cgra_id; + assign tile__tile_id[14] = 5'd14; + assign tile__cgra_id[14] = cgra_id; + assign tile__tile_id[15] = 5'd15; + assign tile__cgra_id[15] = cgra_id; + assign tile__recv_from_controller_pkt__msg[0] = ctrl_ring__send__msg[0]; + assign ctrl_ring__send__rdy[0] = tile__recv_from_controller_pkt__rdy[0]; + assign tile__recv_from_controller_pkt__val[0] = ctrl_ring__send__val[0]; + assign ctrl_ring__recv__msg[0] = tile__send_to_controller_pkt__msg[0]; + assign tile__send_to_controller_pkt__rdy[0] = ctrl_ring__recv__rdy[0]; + assign ctrl_ring__recv__val[0] = tile__send_to_controller_pkt__val[0]; + assign tile__recv_from_controller_pkt__msg[1] = ctrl_ring__send__msg[1]; + assign ctrl_ring__send__rdy[1] = tile__recv_from_controller_pkt__rdy[1]; + assign tile__recv_from_controller_pkt__val[1] = ctrl_ring__send__val[1]; + assign ctrl_ring__recv__msg[1] = tile__send_to_controller_pkt__msg[1]; + assign tile__send_to_controller_pkt__rdy[1] = ctrl_ring__recv__rdy[1]; + assign ctrl_ring__recv__val[1] = tile__send_to_controller_pkt__val[1]; + assign tile__recv_from_controller_pkt__msg[2] = ctrl_ring__send__msg[2]; + assign ctrl_ring__send__rdy[2] = tile__recv_from_controller_pkt__rdy[2]; + assign tile__recv_from_controller_pkt__val[2] = ctrl_ring__send__val[2]; + assign ctrl_ring__recv__msg[2] = tile__send_to_controller_pkt__msg[2]; + assign tile__send_to_controller_pkt__rdy[2] = ctrl_ring__recv__rdy[2]; + assign ctrl_ring__recv__val[2] = tile__send_to_controller_pkt__val[2]; + assign tile__recv_from_controller_pkt__msg[3] = ctrl_ring__send__msg[3]; + assign ctrl_ring__send__rdy[3] = tile__recv_from_controller_pkt__rdy[3]; + assign tile__recv_from_controller_pkt__val[3] = ctrl_ring__send__val[3]; + assign ctrl_ring__recv__msg[3] = tile__send_to_controller_pkt__msg[3]; + assign tile__send_to_controller_pkt__rdy[3] = ctrl_ring__recv__rdy[3]; + assign ctrl_ring__recv__val[3] = tile__send_to_controller_pkt__val[3]; + assign tile__recv_from_controller_pkt__msg[4] = ctrl_ring__send__msg[4]; + assign ctrl_ring__send__rdy[4] = tile__recv_from_controller_pkt__rdy[4]; + assign tile__recv_from_controller_pkt__val[4] = ctrl_ring__send__val[4]; + assign ctrl_ring__recv__msg[4] = tile__send_to_controller_pkt__msg[4]; + assign tile__send_to_controller_pkt__rdy[4] = ctrl_ring__recv__rdy[4]; + assign ctrl_ring__recv__val[4] = tile__send_to_controller_pkt__val[4]; + assign tile__recv_from_controller_pkt__msg[5] = ctrl_ring__send__msg[5]; + assign ctrl_ring__send__rdy[5] = tile__recv_from_controller_pkt__rdy[5]; + assign tile__recv_from_controller_pkt__val[5] = ctrl_ring__send__val[5]; + assign ctrl_ring__recv__msg[5] = tile__send_to_controller_pkt__msg[5]; + assign tile__send_to_controller_pkt__rdy[5] = ctrl_ring__recv__rdy[5]; + assign ctrl_ring__recv__val[5] = tile__send_to_controller_pkt__val[5]; + assign tile__recv_from_controller_pkt__msg[6] = ctrl_ring__send__msg[6]; + assign ctrl_ring__send__rdy[6] = tile__recv_from_controller_pkt__rdy[6]; + assign tile__recv_from_controller_pkt__val[6] = ctrl_ring__send__val[6]; + assign ctrl_ring__recv__msg[6] = tile__send_to_controller_pkt__msg[6]; + assign tile__send_to_controller_pkt__rdy[6] = ctrl_ring__recv__rdy[6]; + assign ctrl_ring__recv__val[6] = tile__send_to_controller_pkt__val[6]; + assign tile__recv_from_controller_pkt__msg[7] = ctrl_ring__send__msg[7]; + assign ctrl_ring__send__rdy[7] = tile__recv_from_controller_pkt__rdy[7]; + assign tile__recv_from_controller_pkt__val[7] = ctrl_ring__send__val[7]; + assign ctrl_ring__recv__msg[7] = tile__send_to_controller_pkt__msg[7]; + assign tile__send_to_controller_pkt__rdy[7] = ctrl_ring__recv__rdy[7]; + assign ctrl_ring__recv__val[7] = tile__send_to_controller_pkt__val[7]; + assign tile__recv_from_controller_pkt__msg[8] = ctrl_ring__send__msg[8]; + assign ctrl_ring__send__rdy[8] = tile__recv_from_controller_pkt__rdy[8]; + assign tile__recv_from_controller_pkt__val[8] = ctrl_ring__send__val[8]; + assign ctrl_ring__recv__msg[8] = tile__send_to_controller_pkt__msg[8]; + assign tile__send_to_controller_pkt__rdy[8] = ctrl_ring__recv__rdy[8]; + assign ctrl_ring__recv__val[8] = tile__send_to_controller_pkt__val[8]; + assign tile__recv_from_controller_pkt__msg[9] = ctrl_ring__send__msg[9]; + assign ctrl_ring__send__rdy[9] = tile__recv_from_controller_pkt__rdy[9]; + assign tile__recv_from_controller_pkt__val[9] = ctrl_ring__send__val[9]; + assign ctrl_ring__recv__msg[9] = tile__send_to_controller_pkt__msg[9]; + assign tile__send_to_controller_pkt__rdy[9] = ctrl_ring__recv__rdy[9]; + assign ctrl_ring__recv__val[9] = tile__send_to_controller_pkt__val[9]; + assign tile__recv_from_controller_pkt__msg[10] = ctrl_ring__send__msg[10]; + assign ctrl_ring__send__rdy[10] = tile__recv_from_controller_pkt__rdy[10]; + assign tile__recv_from_controller_pkt__val[10] = ctrl_ring__send__val[10]; + assign ctrl_ring__recv__msg[10] = tile__send_to_controller_pkt__msg[10]; + assign tile__send_to_controller_pkt__rdy[10] = ctrl_ring__recv__rdy[10]; + assign ctrl_ring__recv__val[10] = tile__send_to_controller_pkt__val[10]; + assign tile__recv_from_controller_pkt__msg[11] = ctrl_ring__send__msg[11]; + assign ctrl_ring__send__rdy[11] = tile__recv_from_controller_pkt__rdy[11]; + assign tile__recv_from_controller_pkt__val[11] = ctrl_ring__send__val[11]; + assign ctrl_ring__recv__msg[11] = tile__send_to_controller_pkt__msg[11]; + assign tile__send_to_controller_pkt__rdy[11] = ctrl_ring__recv__rdy[11]; + assign ctrl_ring__recv__val[11] = tile__send_to_controller_pkt__val[11]; + assign tile__recv_from_controller_pkt__msg[12] = ctrl_ring__send__msg[12]; + assign ctrl_ring__send__rdy[12] = tile__recv_from_controller_pkt__rdy[12]; + assign tile__recv_from_controller_pkt__val[12] = ctrl_ring__send__val[12]; + assign ctrl_ring__recv__msg[12] = tile__send_to_controller_pkt__msg[12]; + assign tile__send_to_controller_pkt__rdy[12] = ctrl_ring__recv__rdy[12]; + assign ctrl_ring__recv__val[12] = tile__send_to_controller_pkt__val[12]; + assign tile__recv_from_controller_pkt__msg[13] = ctrl_ring__send__msg[13]; + assign ctrl_ring__send__rdy[13] = tile__recv_from_controller_pkt__rdy[13]; + assign tile__recv_from_controller_pkt__val[13] = ctrl_ring__send__val[13]; + assign ctrl_ring__recv__msg[13] = tile__send_to_controller_pkt__msg[13]; + assign tile__send_to_controller_pkt__rdy[13] = ctrl_ring__recv__rdy[13]; + assign ctrl_ring__recv__val[13] = tile__send_to_controller_pkt__val[13]; + assign tile__recv_from_controller_pkt__msg[14] = ctrl_ring__send__msg[14]; + assign ctrl_ring__send__rdy[14] = tile__recv_from_controller_pkt__rdy[14]; + assign tile__recv_from_controller_pkt__val[14] = ctrl_ring__send__val[14]; + assign ctrl_ring__recv__msg[14] = tile__send_to_controller_pkt__msg[14]; + assign tile__send_to_controller_pkt__rdy[14] = ctrl_ring__recv__rdy[14]; + assign ctrl_ring__recv__val[14] = tile__send_to_controller_pkt__val[14]; + assign tile__recv_from_controller_pkt__msg[15] = ctrl_ring__send__msg[15]; + assign ctrl_ring__send__rdy[15] = tile__recv_from_controller_pkt__rdy[15]; + assign tile__recv_from_controller_pkt__val[15] = ctrl_ring__send__val[15]; + assign ctrl_ring__recv__msg[15] = tile__send_to_controller_pkt__msg[15]; + assign tile__send_to_controller_pkt__rdy[15] = ctrl_ring__recv__rdy[15]; + assign ctrl_ring__recv__val[15] = tile__send_to_controller_pkt__val[15]; + assign ctrl_ring__recv__msg[16] = controller__send_to_ctrl_ring_pkt__msg; + assign controller__send_to_ctrl_ring_pkt__rdy = ctrl_ring__recv__rdy[16]; + assign ctrl_ring__recv__val[16] = controller__send_to_ctrl_ring_pkt__val; + assign controller__recv_from_ctrl_ring_pkt__msg = ctrl_ring__send__msg[16]; + assign ctrl_ring__send__rdy[16] = controller__recv_from_ctrl_ring_pkt__rdy; + assign controller__recv_from_ctrl_ring_pkt__val = ctrl_ring__send__val[16]; + assign tile__recv_data__msg[4][1] = tile__send_data__msg[0][0]; + assign tile__send_data__rdy[0][0] = tile__recv_data__rdy[4][1]; + assign tile__recv_data__val[4][1] = tile__send_data__val[0][0]; + assign tile__recv_data__msg[1][2] = tile__send_data__msg[0][3]; + assign tile__send_data__rdy[0][3] = tile__recv_data__rdy[1][2]; + assign tile__recv_data__val[1][2] = tile__send_data__val[0][3]; + assign send_data_on_boundary_south__msg[0] = tile__send_data__msg[0][1]; + assign tile__send_data__rdy[0][1] = send_data_on_boundary_south__rdy[0]; + assign send_data_on_boundary_south__val[0] = tile__send_data__val[0][1]; + assign tile__recv_data__msg[0][1] = recv_data_on_boundary_south__msg[0]; + assign recv_data_on_boundary_south__rdy[0] = tile__recv_data__rdy[0][1]; + assign tile__recv_data__val[0][1] = recv_data_on_boundary_south__val[0]; + assign send_data_on_boundary_west__msg[0] = tile__send_data__msg[0][2]; + assign tile__send_data__rdy[0][2] = send_data_on_boundary_west__rdy[0]; + assign send_data_on_boundary_west__val[0] = tile__send_data__val[0][2]; + assign tile__recv_data__msg[0][2] = recv_data_on_boundary_west__msg[0]; + assign recv_data_on_boundary_west__rdy[0] = tile__recv_data__rdy[0][2]; + assign tile__recv_data__val[0][2] = recv_data_on_boundary_west__val[0]; + assign data_mem__recv_raddr__msg[0] = tile__to_mem_raddr__msg[0]; + assign tile__to_mem_raddr__rdy[0] = data_mem__recv_raddr__rdy[0]; + assign data_mem__recv_raddr__val[0] = tile__to_mem_raddr__val[0]; + assign tile__from_mem_rdata__msg[0] = data_mem__send_rdata__msg[0]; + assign data_mem__send_rdata__rdy[0] = tile__from_mem_rdata__rdy[0]; + assign tile__from_mem_rdata__val[0] = data_mem__send_rdata__val[0]; + assign data_mem__recv_waddr__msg[0] = tile__to_mem_waddr__msg[0]; + assign tile__to_mem_waddr__rdy[0] = data_mem__recv_waddr__rdy[0]; + assign data_mem__recv_waddr__val[0] = tile__to_mem_waddr__val[0]; + assign data_mem__recv_wdata__msg[0] = tile__to_mem_wdata__msg[0]; + assign tile__to_mem_wdata__rdy[0] = data_mem__recv_wdata__rdy[0]; + assign data_mem__recv_wdata__val[0] = tile__to_mem_wdata__val[0]; + assign tile__recv_data__msg[5][1] = tile__send_data__msg[1][0]; + assign tile__send_data__rdy[1][0] = tile__recv_data__rdy[5][1]; + assign tile__recv_data__val[5][1] = tile__send_data__val[1][0]; + assign tile__recv_data__msg[0][3] = tile__send_data__msg[1][2]; + assign tile__send_data__rdy[1][2] = tile__recv_data__rdy[0][3]; + assign tile__recv_data__val[0][3] = tile__send_data__val[1][2]; + assign tile__recv_data__msg[2][2] = tile__send_data__msg[1][3]; + assign tile__send_data__rdy[1][3] = tile__recv_data__rdy[2][2]; + assign tile__recv_data__val[2][2] = tile__send_data__val[1][3]; + assign send_data_on_boundary_south__msg[1] = tile__send_data__msg[1][1]; + assign tile__send_data__rdy[1][1] = send_data_on_boundary_south__rdy[1]; + assign send_data_on_boundary_south__val[1] = tile__send_data__val[1][1]; + assign tile__recv_data__msg[1][1] = recv_data_on_boundary_south__msg[1]; + assign recv_data_on_boundary_south__rdy[1] = tile__recv_data__rdy[1][1]; + assign tile__recv_data__val[1][1] = recv_data_on_boundary_south__val[1]; + assign data_mem__recv_raddr__msg[1] = tile__to_mem_raddr__msg[1]; + assign tile__to_mem_raddr__rdy[1] = data_mem__recv_raddr__rdy[1]; + assign data_mem__recv_raddr__val[1] = tile__to_mem_raddr__val[1]; + assign tile__from_mem_rdata__msg[1] = data_mem__send_rdata__msg[1]; + assign data_mem__send_rdata__rdy[1] = tile__from_mem_rdata__rdy[1]; + assign tile__from_mem_rdata__val[1] = data_mem__send_rdata__val[1]; + assign data_mem__recv_waddr__msg[1] = tile__to_mem_waddr__msg[1]; + assign tile__to_mem_waddr__rdy[1] = data_mem__recv_waddr__rdy[1]; + assign data_mem__recv_waddr__val[1] = tile__to_mem_waddr__val[1]; + assign data_mem__recv_wdata__msg[1] = tile__to_mem_wdata__msg[1]; + assign tile__to_mem_wdata__rdy[1] = data_mem__recv_wdata__rdy[1]; + assign data_mem__recv_wdata__val[1] = tile__to_mem_wdata__val[1]; + assign tile__recv_data__msg[6][1] = tile__send_data__msg[2][0]; + assign tile__send_data__rdy[2][0] = tile__recv_data__rdy[6][1]; + assign tile__recv_data__val[6][1] = tile__send_data__val[2][0]; + assign tile__recv_data__msg[1][3] = tile__send_data__msg[2][2]; + assign tile__send_data__rdy[2][2] = tile__recv_data__rdy[1][3]; + assign tile__recv_data__val[1][3] = tile__send_data__val[2][2]; + assign tile__recv_data__msg[3][2] = tile__send_data__msg[2][3]; + assign tile__send_data__rdy[2][3] = tile__recv_data__rdy[3][2]; + assign tile__recv_data__val[3][2] = tile__send_data__val[2][3]; + assign send_data_on_boundary_south__msg[2] = tile__send_data__msg[2][1]; + assign tile__send_data__rdy[2][1] = send_data_on_boundary_south__rdy[2]; + assign send_data_on_boundary_south__val[2] = tile__send_data__val[2][1]; + assign tile__recv_data__msg[2][1] = recv_data_on_boundary_south__msg[2]; + assign recv_data_on_boundary_south__rdy[2] = tile__recv_data__rdy[2][1]; + assign tile__recv_data__val[2][1] = recv_data_on_boundary_south__val[2]; + assign data_mem__recv_raddr__msg[2] = tile__to_mem_raddr__msg[2]; + assign tile__to_mem_raddr__rdy[2] = data_mem__recv_raddr__rdy[2]; + assign data_mem__recv_raddr__val[2] = tile__to_mem_raddr__val[2]; + assign tile__from_mem_rdata__msg[2] = data_mem__send_rdata__msg[2]; + assign data_mem__send_rdata__rdy[2] = tile__from_mem_rdata__rdy[2]; + assign tile__from_mem_rdata__val[2] = data_mem__send_rdata__val[2]; + assign data_mem__recv_waddr__msg[2] = tile__to_mem_waddr__msg[2]; + assign tile__to_mem_waddr__rdy[2] = data_mem__recv_waddr__rdy[2]; + assign data_mem__recv_waddr__val[2] = tile__to_mem_waddr__val[2]; + assign data_mem__recv_wdata__msg[2] = tile__to_mem_wdata__msg[2]; + assign tile__to_mem_wdata__rdy[2] = data_mem__recv_wdata__rdy[2]; + assign data_mem__recv_wdata__val[2] = tile__to_mem_wdata__val[2]; + assign tile__recv_data__msg[7][1] = tile__send_data__msg[3][0]; + assign tile__send_data__rdy[3][0] = tile__recv_data__rdy[7][1]; + assign tile__recv_data__val[7][1] = tile__send_data__val[3][0]; + assign tile__recv_data__msg[2][3] = tile__send_data__msg[3][2]; + assign tile__send_data__rdy[3][2] = tile__recv_data__rdy[2][3]; + assign tile__recv_data__val[2][3] = tile__send_data__val[3][2]; + assign send_data_on_boundary_south__msg[3] = tile__send_data__msg[3][1]; + assign tile__send_data__rdy[3][1] = send_data_on_boundary_south__rdy[3]; + assign send_data_on_boundary_south__val[3] = tile__send_data__val[3][1]; + assign tile__recv_data__msg[3][1] = recv_data_on_boundary_south__msg[3]; + assign recv_data_on_boundary_south__rdy[3] = tile__recv_data__rdy[3][1]; + assign tile__recv_data__val[3][1] = recv_data_on_boundary_south__val[3]; + assign send_data_on_boundary_east__msg[0] = tile__send_data__msg[3][3]; + assign tile__send_data__rdy[3][3] = send_data_on_boundary_east__rdy[0]; + assign send_data_on_boundary_east__val[0] = tile__send_data__val[3][3]; + assign tile__recv_data__msg[3][3] = recv_data_on_boundary_east__msg[0]; + assign recv_data_on_boundary_east__rdy[0] = tile__recv_data__rdy[3][3]; + assign tile__recv_data__val[3][3] = recv_data_on_boundary_east__val[0]; + assign data_mem__recv_raddr__msg[3] = tile__to_mem_raddr__msg[3]; + assign tile__to_mem_raddr__rdy[3] = data_mem__recv_raddr__rdy[3]; + assign data_mem__recv_raddr__val[3] = tile__to_mem_raddr__val[3]; + assign tile__from_mem_rdata__msg[3] = data_mem__send_rdata__msg[3]; + assign data_mem__send_rdata__rdy[3] = tile__from_mem_rdata__rdy[3]; + assign tile__from_mem_rdata__val[3] = data_mem__send_rdata__val[3]; + assign data_mem__recv_waddr__msg[3] = tile__to_mem_waddr__msg[3]; + assign tile__to_mem_waddr__rdy[3] = data_mem__recv_waddr__rdy[3]; + assign data_mem__recv_waddr__val[3] = tile__to_mem_waddr__val[3]; + assign data_mem__recv_wdata__msg[3] = tile__to_mem_wdata__msg[3]; + assign tile__to_mem_wdata__rdy[3] = data_mem__recv_wdata__rdy[3]; + assign data_mem__recv_wdata__val[3] = tile__to_mem_wdata__val[3]; + assign tile__recv_data__msg[0][0] = tile__send_data__msg[4][1]; + assign tile__send_data__rdy[4][1] = tile__recv_data__rdy[0][0]; + assign tile__recv_data__val[0][0] = tile__send_data__val[4][1]; + assign tile__recv_data__msg[8][1] = tile__send_data__msg[4][0]; + assign tile__send_data__rdy[4][0] = tile__recv_data__rdy[8][1]; + assign tile__recv_data__val[8][1] = tile__send_data__val[4][0]; + assign tile__recv_data__msg[5][2] = tile__send_data__msg[4][3]; + assign tile__send_data__rdy[4][3] = tile__recv_data__rdy[5][2]; + assign tile__recv_data__val[5][2] = tile__send_data__val[4][3]; + assign send_data_on_boundary_west__msg[1] = tile__send_data__msg[4][2]; + assign tile__send_data__rdy[4][2] = send_data_on_boundary_west__rdy[1]; + assign send_data_on_boundary_west__val[1] = tile__send_data__val[4][2]; + assign tile__recv_data__msg[4][2] = recv_data_on_boundary_west__msg[1]; + assign recv_data_on_boundary_west__rdy[1] = tile__recv_data__rdy[4][2]; + assign tile__recv_data__val[4][2] = recv_data_on_boundary_west__val[1]; + assign data_mem__recv_raddr__msg[4] = tile__to_mem_raddr__msg[4]; + assign tile__to_mem_raddr__rdy[4] = data_mem__recv_raddr__rdy[4]; + assign data_mem__recv_raddr__val[4] = tile__to_mem_raddr__val[4]; + assign tile__from_mem_rdata__msg[4] = data_mem__send_rdata__msg[4]; + assign data_mem__send_rdata__rdy[4] = tile__from_mem_rdata__rdy[4]; + assign tile__from_mem_rdata__val[4] = data_mem__send_rdata__val[4]; + assign data_mem__recv_waddr__msg[4] = tile__to_mem_waddr__msg[4]; + assign tile__to_mem_waddr__rdy[4] = data_mem__recv_waddr__rdy[4]; + assign data_mem__recv_waddr__val[4] = tile__to_mem_waddr__val[4]; + assign data_mem__recv_wdata__msg[4] = tile__to_mem_wdata__msg[4]; + assign tile__to_mem_wdata__rdy[4] = data_mem__recv_wdata__rdy[4]; + assign data_mem__recv_wdata__val[4] = tile__to_mem_wdata__val[4]; + assign tile__recv_data__msg[1][0] = tile__send_data__msg[5][1]; + assign tile__send_data__rdy[5][1] = tile__recv_data__rdy[1][0]; + assign tile__recv_data__val[1][0] = tile__send_data__val[5][1]; + assign tile__recv_data__msg[9][1] = tile__send_data__msg[5][0]; + assign tile__send_data__rdy[5][0] = tile__recv_data__rdy[9][1]; + assign tile__recv_data__val[9][1] = tile__send_data__val[5][0]; + assign tile__recv_data__msg[4][3] = tile__send_data__msg[5][2]; + assign tile__send_data__rdy[5][2] = tile__recv_data__rdy[4][3]; + assign tile__recv_data__val[4][3] = tile__send_data__val[5][2]; + assign tile__recv_data__msg[6][2] = tile__send_data__msg[5][3]; + assign tile__send_data__rdy[5][3] = tile__recv_data__rdy[6][2]; + assign tile__recv_data__val[6][2] = tile__send_data__val[5][3]; + assign tile__to_mem_raddr__rdy[5] = 1'd0; + assign tile__from_mem_rdata__val[5] = 1'd0; + assign tile__from_mem_rdata__msg[5] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[5] = 1'd0; + assign tile__to_mem_wdata__rdy[5] = 1'd0; + assign tile__recv_data__msg[2][0] = tile__send_data__msg[6][1]; + assign tile__send_data__rdy[6][1] = tile__recv_data__rdy[2][0]; + assign tile__recv_data__val[2][0] = tile__send_data__val[6][1]; + assign tile__recv_data__msg[10][1] = tile__send_data__msg[6][0]; + assign tile__send_data__rdy[6][0] = tile__recv_data__rdy[10][1]; + assign tile__recv_data__val[10][1] = tile__send_data__val[6][0]; + assign tile__recv_data__msg[5][3] = tile__send_data__msg[6][2]; + assign tile__send_data__rdy[6][2] = tile__recv_data__rdy[5][3]; + assign tile__recv_data__val[5][3] = tile__send_data__val[6][2]; + assign tile__recv_data__msg[7][2] = tile__send_data__msg[6][3]; + assign tile__send_data__rdy[6][3] = tile__recv_data__rdy[7][2]; + assign tile__recv_data__val[7][2] = tile__send_data__val[6][3]; + assign tile__to_mem_raddr__rdy[6] = 1'd0; + assign tile__from_mem_rdata__val[6] = 1'd0; + assign tile__from_mem_rdata__msg[6] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[6] = 1'd0; + assign tile__to_mem_wdata__rdy[6] = 1'd0; + assign tile__recv_data__msg[3][0] = tile__send_data__msg[7][1]; + assign tile__send_data__rdy[7][1] = tile__recv_data__rdy[3][0]; + assign tile__recv_data__val[3][0] = tile__send_data__val[7][1]; + assign tile__recv_data__msg[11][1] = tile__send_data__msg[7][0]; + assign tile__send_data__rdy[7][0] = tile__recv_data__rdy[11][1]; + assign tile__recv_data__val[11][1] = tile__send_data__val[7][0]; + assign tile__recv_data__msg[6][3] = tile__send_data__msg[7][2]; + assign tile__send_data__rdy[7][2] = tile__recv_data__rdy[6][3]; + assign tile__recv_data__val[6][3] = tile__send_data__val[7][2]; + assign send_data_on_boundary_east__msg[1] = tile__send_data__msg[7][3]; + assign tile__send_data__rdy[7][3] = send_data_on_boundary_east__rdy[1]; + assign send_data_on_boundary_east__val[1] = tile__send_data__val[7][3]; + assign tile__recv_data__msg[7][3] = recv_data_on_boundary_east__msg[1]; + assign recv_data_on_boundary_east__rdy[1] = tile__recv_data__rdy[7][3]; + assign tile__recv_data__val[7][3] = recv_data_on_boundary_east__val[1]; + assign tile__to_mem_raddr__rdy[7] = 1'd0; + assign tile__from_mem_rdata__val[7] = 1'd0; + assign tile__from_mem_rdata__msg[7] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[7] = 1'd0; + assign tile__to_mem_wdata__rdy[7] = 1'd0; + assign tile__recv_data__msg[4][0] = tile__send_data__msg[8][1]; + assign tile__send_data__rdy[8][1] = tile__recv_data__rdy[4][0]; + assign tile__recv_data__val[4][0] = tile__send_data__val[8][1]; + assign tile__recv_data__msg[12][1] = tile__send_data__msg[8][0]; + assign tile__send_data__rdy[8][0] = tile__recv_data__rdy[12][1]; + assign tile__recv_data__val[12][1] = tile__send_data__val[8][0]; + assign tile__recv_data__msg[9][2] = tile__send_data__msg[8][3]; + assign tile__send_data__rdy[8][3] = tile__recv_data__rdy[9][2]; + assign tile__recv_data__val[9][2] = tile__send_data__val[8][3]; + assign send_data_on_boundary_west__msg[2] = tile__send_data__msg[8][2]; + assign tile__send_data__rdy[8][2] = send_data_on_boundary_west__rdy[2]; + assign send_data_on_boundary_west__val[2] = tile__send_data__val[8][2]; + assign tile__recv_data__msg[8][2] = recv_data_on_boundary_west__msg[2]; + assign recv_data_on_boundary_west__rdy[2] = tile__recv_data__rdy[8][2]; + assign tile__recv_data__val[8][2] = recv_data_on_boundary_west__val[2]; + assign data_mem__recv_raddr__msg[5] = tile__to_mem_raddr__msg[8]; + assign tile__to_mem_raddr__rdy[8] = data_mem__recv_raddr__rdy[5]; + assign data_mem__recv_raddr__val[5] = tile__to_mem_raddr__val[8]; + assign tile__from_mem_rdata__msg[8] = data_mem__send_rdata__msg[5]; + assign data_mem__send_rdata__rdy[5] = tile__from_mem_rdata__rdy[8]; + assign tile__from_mem_rdata__val[8] = data_mem__send_rdata__val[5]; + assign data_mem__recv_waddr__msg[5] = tile__to_mem_waddr__msg[8]; + assign tile__to_mem_waddr__rdy[8] = data_mem__recv_waddr__rdy[5]; + assign data_mem__recv_waddr__val[5] = tile__to_mem_waddr__val[8]; + assign data_mem__recv_wdata__msg[5] = tile__to_mem_wdata__msg[8]; + assign tile__to_mem_wdata__rdy[8] = data_mem__recv_wdata__rdy[5]; + assign data_mem__recv_wdata__val[5] = tile__to_mem_wdata__val[8]; + assign tile__recv_data__msg[5][0] = tile__send_data__msg[9][1]; + assign tile__send_data__rdy[9][1] = tile__recv_data__rdy[5][0]; + assign tile__recv_data__val[5][0] = tile__send_data__val[9][1]; + assign tile__recv_data__msg[13][1] = tile__send_data__msg[9][0]; + assign tile__send_data__rdy[9][0] = tile__recv_data__rdy[13][1]; + assign tile__recv_data__val[13][1] = tile__send_data__val[9][0]; + assign tile__recv_data__msg[8][3] = tile__send_data__msg[9][2]; + assign tile__send_data__rdy[9][2] = tile__recv_data__rdy[8][3]; + assign tile__recv_data__val[8][3] = tile__send_data__val[9][2]; + assign tile__recv_data__msg[10][2] = tile__send_data__msg[9][3]; + assign tile__send_data__rdy[9][3] = tile__recv_data__rdy[10][2]; + assign tile__recv_data__val[10][2] = tile__send_data__val[9][3]; + assign tile__to_mem_raddr__rdy[9] = 1'd0; + assign tile__from_mem_rdata__val[9] = 1'd0; + assign tile__from_mem_rdata__msg[9] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[9] = 1'd0; + assign tile__to_mem_wdata__rdy[9] = 1'd0; + assign tile__recv_data__msg[6][0] = tile__send_data__msg[10][1]; + assign tile__send_data__rdy[10][1] = tile__recv_data__rdy[6][0]; + assign tile__recv_data__val[6][0] = tile__send_data__val[10][1]; + assign tile__recv_data__msg[14][1] = tile__send_data__msg[10][0]; + assign tile__send_data__rdy[10][0] = tile__recv_data__rdy[14][1]; + assign tile__recv_data__val[14][1] = tile__send_data__val[10][0]; + assign tile__recv_data__msg[9][3] = tile__send_data__msg[10][2]; + assign tile__send_data__rdy[10][2] = tile__recv_data__rdy[9][3]; + assign tile__recv_data__val[9][3] = tile__send_data__val[10][2]; + assign tile__recv_data__msg[11][2] = tile__send_data__msg[10][3]; + assign tile__send_data__rdy[10][3] = tile__recv_data__rdy[11][2]; + assign tile__recv_data__val[11][2] = tile__send_data__val[10][3]; + assign tile__to_mem_raddr__rdy[10] = 1'd0; + assign tile__from_mem_rdata__val[10] = 1'd0; + assign tile__from_mem_rdata__msg[10] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[10] = 1'd0; + assign tile__to_mem_wdata__rdy[10] = 1'd0; + assign tile__recv_data__msg[7][0] = tile__send_data__msg[11][1]; + assign tile__send_data__rdy[11][1] = tile__recv_data__rdy[7][0]; + assign tile__recv_data__val[7][0] = tile__send_data__val[11][1]; + assign tile__recv_data__msg[15][1] = tile__send_data__msg[11][0]; + assign tile__send_data__rdy[11][0] = tile__recv_data__rdy[15][1]; + assign tile__recv_data__val[15][1] = tile__send_data__val[11][0]; + assign tile__recv_data__msg[10][3] = tile__send_data__msg[11][2]; + assign tile__send_data__rdy[11][2] = tile__recv_data__rdy[10][3]; + assign tile__recv_data__val[10][3] = tile__send_data__val[11][2]; + assign send_data_on_boundary_east__msg[2] = tile__send_data__msg[11][3]; + assign tile__send_data__rdy[11][3] = send_data_on_boundary_east__rdy[2]; + assign send_data_on_boundary_east__val[2] = tile__send_data__val[11][3]; + assign tile__recv_data__msg[11][3] = recv_data_on_boundary_east__msg[2]; + assign recv_data_on_boundary_east__rdy[2] = tile__recv_data__rdy[11][3]; + assign tile__recv_data__val[11][3] = recv_data_on_boundary_east__val[2]; + assign tile__to_mem_raddr__rdy[11] = 1'd0; + assign tile__from_mem_rdata__val[11] = 1'd0; + assign tile__from_mem_rdata__msg[11] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[11] = 1'd0; + assign tile__to_mem_wdata__rdy[11] = 1'd0; + assign tile__recv_data__msg[8][0] = tile__send_data__msg[12][1]; + assign tile__send_data__rdy[12][1] = tile__recv_data__rdy[8][0]; + assign tile__recv_data__val[8][0] = tile__send_data__val[12][1]; + assign tile__recv_data__msg[13][2] = tile__send_data__msg[12][3]; + assign tile__send_data__rdy[12][3] = tile__recv_data__rdy[13][2]; + assign tile__recv_data__val[13][2] = tile__send_data__val[12][3]; + assign send_data_on_boundary_north__msg[0] = tile__send_data__msg[12][0]; + assign tile__send_data__rdy[12][0] = send_data_on_boundary_north__rdy[0]; + assign send_data_on_boundary_north__val[0] = tile__send_data__val[12][0]; + assign tile__recv_data__msg[12][0] = recv_data_on_boundary_north__msg[0]; + assign recv_data_on_boundary_north__rdy[0] = tile__recv_data__rdy[12][0]; + assign tile__recv_data__val[12][0] = recv_data_on_boundary_north__val[0]; + assign send_data_on_boundary_west__msg[3] = tile__send_data__msg[12][2]; + assign tile__send_data__rdy[12][2] = send_data_on_boundary_west__rdy[3]; + assign send_data_on_boundary_west__val[3] = tile__send_data__val[12][2]; + assign tile__recv_data__msg[12][2] = recv_data_on_boundary_west__msg[3]; + assign recv_data_on_boundary_west__rdy[3] = tile__recv_data__rdy[12][2]; + assign tile__recv_data__val[12][2] = recv_data_on_boundary_west__val[3]; + assign data_mem__recv_raddr__msg[6] = tile__to_mem_raddr__msg[12]; + assign tile__to_mem_raddr__rdy[12] = data_mem__recv_raddr__rdy[6]; + assign data_mem__recv_raddr__val[6] = tile__to_mem_raddr__val[12]; + assign tile__from_mem_rdata__msg[12] = data_mem__send_rdata__msg[6]; + assign data_mem__send_rdata__rdy[6] = tile__from_mem_rdata__rdy[12]; + assign tile__from_mem_rdata__val[12] = data_mem__send_rdata__val[6]; + assign data_mem__recv_waddr__msg[6] = tile__to_mem_waddr__msg[12]; + assign tile__to_mem_waddr__rdy[12] = data_mem__recv_waddr__rdy[6]; + assign data_mem__recv_waddr__val[6] = tile__to_mem_waddr__val[12]; + assign data_mem__recv_wdata__msg[6] = tile__to_mem_wdata__msg[12]; + assign tile__to_mem_wdata__rdy[12] = data_mem__recv_wdata__rdy[6]; + assign data_mem__recv_wdata__val[6] = tile__to_mem_wdata__val[12]; + assign tile__recv_data__msg[9][0] = tile__send_data__msg[13][1]; + assign tile__send_data__rdy[13][1] = tile__recv_data__rdy[9][0]; + assign tile__recv_data__val[9][0] = tile__send_data__val[13][1]; + assign tile__recv_data__msg[12][3] = tile__send_data__msg[13][2]; + assign tile__send_data__rdy[13][2] = tile__recv_data__rdy[12][3]; + assign tile__recv_data__val[12][3] = tile__send_data__val[13][2]; + assign tile__recv_data__msg[14][2] = tile__send_data__msg[13][3]; + assign tile__send_data__rdy[13][3] = tile__recv_data__rdy[14][2]; + assign tile__recv_data__val[14][2] = tile__send_data__val[13][3]; + assign send_data_on_boundary_north__msg[1] = tile__send_data__msg[13][0]; + assign tile__send_data__rdy[13][0] = send_data_on_boundary_north__rdy[1]; + assign send_data_on_boundary_north__val[1] = tile__send_data__val[13][0]; + assign tile__recv_data__msg[13][0] = recv_data_on_boundary_north__msg[1]; + assign recv_data_on_boundary_north__rdy[1] = tile__recv_data__rdy[13][0]; + assign tile__recv_data__val[13][0] = recv_data_on_boundary_north__val[1]; + assign tile__to_mem_raddr__rdy[13] = 1'd0; + assign tile__from_mem_rdata__val[13] = 1'd0; + assign tile__from_mem_rdata__msg[13] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[13] = 1'd0; + assign tile__to_mem_wdata__rdy[13] = 1'd0; + assign tile__recv_data__msg[10][0] = tile__send_data__msg[14][1]; + assign tile__send_data__rdy[14][1] = tile__recv_data__rdy[10][0]; + assign tile__recv_data__val[10][0] = tile__send_data__val[14][1]; + assign tile__recv_data__msg[13][3] = tile__send_data__msg[14][2]; + assign tile__send_data__rdy[14][2] = tile__recv_data__rdy[13][3]; + assign tile__recv_data__val[13][3] = tile__send_data__val[14][2]; + assign tile__recv_data__msg[15][2] = tile__send_data__msg[14][3]; + assign tile__send_data__rdy[14][3] = tile__recv_data__rdy[15][2]; + assign tile__recv_data__val[15][2] = tile__send_data__val[14][3]; + assign send_data_on_boundary_north__msg[2] = tile__send_data__msg[14][0]; + assign tile__send_data__rdy[14][0] = send_data_on_boundary_north__rdy[2]; + assign send_data_on_boundary_north__val[2] = tile__send_data__val[14][0]; + assign tile__recv_data__msg[14][0] = recv_data_on_boundary_north__msg[2]; + assign recv_data_on_boundary_north__rdy[2] = tile__recv_data__rdy[14][0]; + assign tile__recv_data__val[14][0] = recv_data_on_boundary_north__val[2]; + assign tile__to_mem_raddr__rdy[14] = 1'd0; + assign tile__from_mem_rdata__val[14] = 1'd0; + assign tile__from_mem_rdata__msg[14] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[14] = 1'd0; + assign tile__to_mem_wdata__rdy[14] = 1'd0; + assign tile__recv_data__msg[11][0] = tile__send_data__msg[15][1]; + assign tile__send_data__rdy[15][1] = tile__recv_data__rdy[11][0]; + assign tile__recv_data__val[11][0] = tile__send_data__val[15][1]; + assign tile__recv_data__msg[14][3] = tile__send_data__msg[15][2]; + assign tile__send_data__rdy[15][2] = tile__recv_data__rdy[14][3]; + assign tile__recv_data__val[14][3] = tile__send_data__val[15][2]; + assign send_data_on_boundary_north__msg[3] = tile__send_data__msg[15][0]; + assign tile__send_data__rdy[15][0] = send_data_on_boundary_north__rdy[3]; + assign send_data_on_boundary_north__val[3] = tile__send_data__val[15][0]; + assign tile__recv_data__msg[15][0] = recv_data_on_boundary_north__msg[3]; + assign recv_data_on_boundary_north__rdy[3] = tile__recv_data__rdy[15][0]; + assign tile__recv_data__val[15][0] = recv_data_on_boundary_north__val[3]; + assign send_data_on_boundary_east__msg[3] = tile__send_data__msg[15][3]; + assign tile__send_data__rdy[15][3] = send_data_on_boundary_east__rdy[3]; + assign send_data_on_boundary_east__val[3] = tile__send_data__val[15][3]; + assign tile__recv_data__msg[15][3] = recv_data_on_boundary_east__msg[3]; + assign recv_data_on_boundary_east__rdy[3] = tile__recv_data__rdy[15][3]; + assign tile__recv_data__val[15][3] = recv_data_on_boundary_east__val[3]; + assign tile__to_mem_raddr__rdy[15] = 1'd0; + assign tile__from_mem_rdata__val[15] = 1'd0; + assign tile__from_mem_rdata__msg[15] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[15] = 1'd0; + assign tile__to_mem_wdata__rdy[15] = 1'd0; + +endmodule + + +// PyMTL Component InputUnitRTL Definition +// Full name: InputUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_NormalQueueRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py + +module InputUnitRTL__8ea2cb5fb7536c6c +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queue + //------------------------------------------------------------- + + logic [0:0] queue__clk; + logic [1:0] queue__count; + logic [0:0] queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__recv__msg; + logic [0:0] queue__recv__rdy; + logic [0:0] queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__send__msg; + logic [0:0] queue__send__rdy; + logic [0:0] queue__send__val; + + NormalQueueRTL__c7280ffb0786127e queue + ( + .clk( queue__clk ), + .count( queue__count ), + .reset( queue__reset ), + .recv__msg( queue__recv__msg ), + .recv__rdy( queue__recv__rdy ), + .recv__val( queue__recv__val ), + .send__msg( queue__send__msg ), + .send__rdy( queue__send__rdy ), + .send__val( queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component queue + //------------------------------------------------------------- + + assign queue__clk = clk; + assign queue__reset = reset; + assign queue__recv__msg = recv__msg; + assign recv__rdy = queue__recv__rdy; + assign queue__recv__val = recv__val; + assign send__msg = queue__send__msg; + assign queue__send__rdy = send__rdy; + assign send__val = queue__send__val; + +endmodule + + +// PyMTL Component OutputUnitRTL Definition +// Full name: OutputUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_None +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py + +module OutputUnitRTL__e43ef936c3b236b0 +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + assign send__msg = recv__msg; + assign recv__rdy = send__rdy; + assign send__val = recv__val; + +endmodule + + +// PyMTL Component DORYMeshRouteUnitRTL Definition +// Full name: DORYMeshRouteUnitRTL__MsgType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__num_outports_5 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py + +module DORYMeshRouteUnitRTL__cf2d804ed36fdf23 +( + input logic [0:0] clk , + input MeshPosition_2x2__pos_x_1__pos_y_1 pos , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:4] , + input logic [0:0] send__rdy [0:4] , + output logic [0:0] send__val [0:4] +); + localparam logic [2:0] __const__num_outports_at_up_ru_routing = 3'd5; + localparam logic [2:0] __const__SELF = 3'd4; + localparam logic [0:0] __const__SOUTH = 1'd1; + localparam logic [0:0] __const__NORTH = 1'd0; + localparam logic [1:0] __const__WEST = 2'd2; + localparam logic [1:0] __const__EAST = 2'd3; + logic [2:0] out_dir; + logic [4:0] send_rdy; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py:57 + // @update + // def up_ru_recv_rdy(): + // s.recv.rdy @= s.send_rdy[ s.out_dir ] + + always_comb begin : up_ru_recv_rdy + recv__rdy = send_rdy[out_dir]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py:38 + // @update + // def up_ru_routing(): + // s.out_dir @= Bits3(0) + // for i in range( num_outports ): + // s.send[i].val @= Bits1(0) + // + // if s.recv.val: + // if (s.pos.pos_x == s.recv.msg.dst_x) & (s.pos.pos_y == s.recv.msg.dst_y): + // s.out_dir @= SELF + // elif s.recv.msg.dst_y < s.pos.pos_y: + // s.out_dir @= SOUTH + // elif s.recv.msg.dst_y > s.pos.pos_y: + // s.out_dir @= NORTH + // elif s.recv.msg.dst_x < s.pos.pos_x: + // s.out_dir @= WEST + // else: + // s.out_dir @= EAST + // s.send[ s.out_dir ].val @= Bits1(1) + + always_comb begin : up_ru_routing + out_dir = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) + send__val[3'(i)] = 1'd0; + if ( recv__val ) begin + if ( ( pos.pos_x == recv__msg.dst_x ) & ( pos.pos_y == recv__msg.dst_y ) ) begin + out_dir = 3'( __const__SELF ); + end + else if ( recv__msg.dst_y < pos.pos_y ) begin + out_dir = 3'( __const__SOUTH ); + end + else if ( recv__msg.dst_y > pos.pos_y ) begin + out_dir = 3'( __const__NORTH ); + end + else if ( recv__msg.dst_x < pos.pos_x ) begin + out_dir = 3'( __const__WEST ); + end + else + out_dir = 3'( __const__EAST ); + send__val[out_dir] = 1'd1; + end + end + + assign send__msg[0] = recv__msg; + assign send_rdy[0:0] = send__rdy[0]; + assign send__msg[1] = recv__msg; + assign send_rdy[1:1] = send__rdy[1]; + assign send__msg[2] = recv__msg; + assign send_rdy[2:2] = send__rdy[2]; + assign send__msg[3] = recv__msg; + assign send_rdy[3:3] = send__rdy[3]; + assign send__msg[4] = recv__msg; + assign send_rdy[4:4] = send__rdy[4]; + +endmodule + + +// PyMTL Component RegEnRst Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py + +module RegEnRst__Type_Bits5__reset_value_1 +( + input logic [0:0] clk , + input logic [0:0] en , + input logic [4:0] in_ , + output logic [4:0] out , + input logic [0:0] reset +); + localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 + // @update_ff + // def up_regenrst(): + // if s.reset: s.out <<= reset_value + // elif s.en: s.out <<= s.in_ + + always_ff @(posedge clk) begin : up_regenrst + if ( reset ) begin + out <= 5'( __const__reset_value_at_up_regenrst ); + end + else if ( en ) begin + out <= in_; + end + end + +endmodule + + +// PyMTL Component RoundRobinArbiterEn Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py + +module RoundRobinArbiterEn__nreqs_5 +( + input logic [0:0] clk , + input logic [0:0] en , + output logic [4:0] grants , + input logic [4:0] reqs , + input logic [0:0] reset +); + localparam logic [2:0] __const__nreqs_at_comb_reqs_int = 3'd5; + localparam logic [3:0] __const__nreqsX2_at_comb_reqs_int = 4'd10; + localparam logic [2:0] __const__nreqs_at_comb_grants = 3'd5; + localparam logic [2:0] __const__nreqs_at_comb_priority_int = 3'd5; + localparam logic [3:0] __const__nreqsX2_at_comb_priority_int = 4'd10; + localparam logic [3:0] __const__nreqsX2_at_comb_kills = 4'd10; + localparam logic [3:0] __const__nreqsX2_at_comb_grants_int = 4'd10; + logic [9:0] grants_int; + logic [10:0] kills; + logic [0:0] priority_en; + logic [9:0] priority_int; + logic [9:0] reqs_int; + //------------------------------------------------------------- + // Component priority_reg + //------------------------------------------------------------- + + logic [0:0] priority_reg__clk; + logic [0:0] priority_reg__en; + logic [4:0] priority_reg__in_; + logic [4:0] priority_reg__out; + logic [0:0] priority_reg__reset; + + RegEnRst__Type_Bits5__reset_value_1 priority_reg + ( + .clk( priority_reg__clk ), + .en( priority_reg__en ), + .in_( priority_reg__in_ ), + .out( priority_reg__out ), + .reset( priority_reg__reset ) + ); + + //------------------------------------------------------------- + // End of component priority_reg + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 + // @update + // def comb_grants(): + // for i in range( nreqs ): + // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] + + always_comb begin : comb_grants + for ( int unsigned i = 1'd0; i < 3'( __const__nreqs_at_comb_grants ); i += 1'd1 ) + grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 + // @update + // def comb_grants_int(): + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.grants_int[i] @= s.reqs_int[i] + // else: + // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] + + always_comb begin : comb_grants_int + for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + grants_int[4'(i)] = reqs_int[4'(i)]; + end + else + grants_int[4'(i)] = ( ~kills[4'(i)] ) & reqs_int[4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 + // @update + // def comb_kills(): + // s.kills[0] @= 1 + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.kills[i+1] @= s.reqs_int[i] + // else: + // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) + + always_comb begin : comb_kills + kills[4'd0] = 1'd1; + for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + kills[4'(i) + 4'd1] = reqs_int[4'(i)]; + end + else + kills[4'(i) + 4'd1] = kills[4'(i)] | ( ( ~kills[4'(i)] ) & reqs_int[4'(i)] ); + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 + // @update + // def comb_priority_en(): + // s.priority_en @= ( s.grants != 0 ) & s.en + + always_comb begin : comb_priority_en + priority_en = ( grants != 5'd0 ) & en; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 + // @update + // def comb_priority_int(): + // s.priority_int[ 0:nreqs ] @= s.priority_reg.out + // s.priority_int[nreqs:nreqsX2] @= 0 + + always_comb begin : comb_priority_int + priority_int[4'd4:4'd0] = priority_reg__out; + priority_int[4'd9:4'( __const__nreqs_at_comb_priority_int )] = 5'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 + // @update + // def comb_reqs_int(): + // s.reqs_int [ 0:nreqs ] @= s.reqs + // s.reqs_int [nreqs:nreqsX2] @= s.reqs + + always_comb begin : comb_reqs_int + reqs_int[4'd4:4'd0] = reqs; + reqs_int[4'd9:4'( __const__nreqs_at_comb_reqs_int )] = reqs; + end + + assign priority_reg__clk = clk; + assign priority_reg__reset = reset; + assign priority_reg__en = priority_en; + assign priority_reg__in_[4:1] = grants[3:0]; + assign priority_reg__in_[0:0] = grants[4:4]; + +endmodule + + +// PyMTL Component Encoder Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py + +module Encoder__in_nbits_5__out_nbits_3 +( + input logic [0:0] clk , + input logic [4:0] in_ , + output logic [2:0] out , + input logic [0:0] reset +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 + // @update + // def encode(): + // s.out @= 0 + // for i in range( s.in_nbits ): + // if s.in_[i]: + // s.out @= i + + always_comb begin : encode + out = 3'd0; + for ( int unsigned i = 1'd0; i < 3'd5; i += 1'd1 ) + if ( in_[3'(i)] ) begin + out = 3'(i); + end + end + +endmodule + + +// PyMTL Component Mux Definition +// Full name: Mux__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__ninputs_5 +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__5c29509c868f9669 +( + input logic [0:0] clk , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d in_ [0:4], + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d out , + input logic [0:0] reset , + input logic [2:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component SwitchUnitRTL Definition +// Full name: SwitchUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_inports_5 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py + +module SwitchUnitRTL__1ccc072d8fcd170f +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:4] , + output logic [0:0] recv__rdy [0:4] , + input logic [0:0] recv__val [0:4] , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd5; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [4:0] arbiter__grants; + logic [4:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_5 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [4:0] encoder__in_; + logic [2:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_5__out_nbits_3 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mux__in_ [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mux__out; + logic [0:0] mux__reset; + logic [2:0] mux__sel; + + Mux__5c29509c868f9669 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 + // @update + // def up_get_en(): + // for i in range( num_inports ): + // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) + + always_comb begin : up_get_en + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) + recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 + // @update + // def up_send_val(): + // s.send.val @= s.arbiter.grants > 0 + + always_comb begin : up_send_val + send__val = arbiter__grants > 5'd0; + end + + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign arbiter__en = 1'd1; + assign mux__clk = clk; + assign mux__reset = reset; + assign send__msg = mux__out; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign encoder__in_ = arbiter__grants; + assign mux__sel = encoder__out; + assign arbiter__reqs[0:0] = recv__val[0]; + assign mux__in_[0] = recv__msg[0]; + assign arbiter__reqs[1:1] = recv__val[1]; + assign mux__in_[1] = recv__msg[1]; + assign arbiter__reqs[2:2] = recv__val[2]; + assign mux__in_[2] = recv__msg[2]; + assign arbiter__reqs[3:3] = recv__val[3]; + assign mux__in_[3] = recv__msg[3]; + assign arbiter__reqs[4:4] = recv__val[4]; + assign mux__in_[4] = recv__msg[4]; + +endmodule + + +// PyMTL Component MeshRouterRTL Definition +// Full name: MeshRouterRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__InputUnitType_InputUnitRTL__RouteUnitType_DORYMeshRouteUnitRTL__SwitchUnitType_SwitchUnitRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/MeshRouterRTL.py + +module MeshRouterRTL__574f02d875fdbb92 +( + input logic [0:0] clk , + input MeshPosition_2x2__pos_x_1__pos_y_1 pos , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:4] , + output logic [0:0] recv__rdy [0:4] , + input logic [0:0] recv__val [0:4] , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:4] , + input logic [0:0] send__rdy [0:4] , + output logic [0:0] send__val [0:4] +); + //------------------------------------------------------------- + // Component input_units[0:4] + //------------------------------------------------------------- + + logic [0:0] input_units__clk [0:4]; + logic [0:0] input_units__reset [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d input_units__recv__msg [0:4]; + logic [0:0] input_units__recv__rdy [0:4]; + logic [0:0] input_units__recv__val [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d input_units__send__msg [0:4]; + logic [0:0] input_units__send__rdy [0:4]; + logic [0:0] input_units__send__val [0:4]; + + InputUnitRTL__8ea2cb5fb7536c6c input_units__0 + ( + .clk( input_units__clk[0] ), + .reset( input_units__reset[0] ), + .recv__msg( input_units__recv__msg[0] ), + .recv__rdy( input_units__recv__rdy[0] ), + .recv__val( input_units__recv__val[0] ), + .send__msg( input_units__send__msg[0] ), + .send__rdy( input_units__send__rdy[0] ), + .send__val( input_units__send__val[0] ) + ); + + InputUnitRTL__8ea2cb5fb7536c6c input_units__1 + ( + .clk( input_units__clk[1] ), + .reset( input_units__reset[1] ), + .recv__msg( input_units__recv__msg[1] ), + .recv__rdy( input_units__recv__rdy[1] ), + .recv__val( input_units__recv__val[1] ), + .send__msg( input_units__send__msg[1] ), + .send__rdy( input_units__send__rdy[1] ), + .send__val( input_units__send__val[1] ) + ); + + InputUnitRTL__8ea2cb5fb7536c6c input_units__2 + ( + .clk( input_units__clk[2] ), + .reset( input_units__reset[2] ), + .recv__msg( input_units__recv__msg[2] ), + .recv__rdy( input_units__recv__rdy[2] ), + .recv__val( input_units__recv__val[2] ), + .send__msg( input_units__send__msg[2] ), + .send__rdy( input_units__send__rdy[2] ), + .send__val( input_units__send__val[2] ) + ); + + InputUnitRTL__8ea2cb5fb7536c6c input_units__3 + ( + .clk( input_units__clk[3] ), + .reset( input_units__reset[3] ), + .recv__msg( input_units__recv__msg[3] ), + .recv__rdy( input_units__recv__rdy[3] ), + .recv__val( input_units__recv__val[3] ), + .send__msg( input_units__send__msg[3] ), + .send__rdy( input_units__send__rdy[3] ), + .send__val( input_units__send__val[3] ) + ); + + InputUnitRTL__8ea2cb5fb7536c6c input_units__4 + ( + .clk( input_units__clk[4] ), + .reset( input_units__reset[4] ), + .recv__msg( input_units__recv__msg[4] ), + .recv__rdy( input_units__recv__rdy[4] ), + .recv__val( input_units__recv__val[4] ), + .send__msg( input_units__send__msg[4] ), + .send__rdy( input_units__send__rdy[4] ), + .send__val( input_units__send__val[4] ) + ); + + //------------------------------------------------------------- + // End of component input_units[0:4] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component output_units[0:4] + //------------------------------------------------------------- + + logic [0:0] output_units__clk [0:4]; + logic [0:0] output_units__reset [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d output_units__recv__msg [0:4]; + logic [0:0] output_units__recv__rdy [0:4]; + logic [0:0] output_units__recv__val [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d output_units__send__msg [0:4]; + logic [0:0] output_units__send__rdy [0:4]; + logic [0:0] output_units__send__val [0:4]; + + OutputUnitRTL__e43ef936c3b236b0 output_units__0 + ( + .clk( output_units__clk[0] ), + .reset( output_units__reset[0] ), + .recv__msg( output_units__recv__msg[0] ), + .recv__rdy( output_units__recv__rdy[0] ), + .recv__val( output_units__recv__val[0] ), + .send__msg( output_units__send__msg[0] ), + .send__rdy( output_units__send__rdy[0] ), + .send__val( output_units__send__val[0] ) + ); + + OutputUnitRTL__e43ef936c3b236b0 output_units__1 + ( + .clk( output_units__clk[1] ), + .reset( output_units__reset[1] ), + .recv__msg( output_units__recv__msg[1] ), + .recv__rdy( output_units__recv__rdy[1] ), + .recv__val( output_units__recv__val[1] ), + .send__msg( output_units__send__msg[1] ), + .send__rdy( output_units__send__rdy[1] ), + .send__val( output_units__send__val[1] ) + ); + + OutputUnitRTL__e43ef936c3b236b0 output_units__2 + ( + .clk( output_units__clk[2] ), + .reset( output_units__reset[2] ), + .recv__msg( output_units__recv__msg[2] ), + .recv__rdy( output_units__recv__rdy[2] ), + .recv__val( output_units__recv__val[2] ), + .send__msg( output_units__send__msg[2] ), + .send__rdy( output_units__send__rdy[2] ), + .send__val( output_units__send__val[2] ) + ); + + OutputUnitRTL__e43ef936c3b236b0 output_units__3 + ( + .clk( output_units__clk[3] ), + .reset( output_units__reset[3] ), + .recv__msg( output_units__recv__msg[3] ), + .recv__rdy( output_units__recv__rdy[3] ), + .recv__val( output_units__recv__val[3] ), + .send__msg( output_units__send__msg[3] ), + .send__rdy( output_units__send__rdy[3] ), + .send__val( output_units__send__val[3] ) + ); + + OutputUnitRTL__e43ef936c3b236b0 output_units__4 + ( + .clk( output_units__clk[4] ), + .reset( output_units__reset[4] ), + .recv__msg( output_units__recv__msg[4] ), + .recv__rdy( output_units__recv__rdy[4] ), + .recv__val( output_units__recv__val[4] ), + .send__msg( output_units__send__msg[4] ), + .send__rdy( output_units__send__rdy[4] ), + .send__val( output_units__send__val[4] ) + ); + + //------------------------------------------------------------- + // End of component output_units[0:4] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component route_units[0:4] + //------------------------------------------------------------- + + logic [0:0] route_units__clk [0:4]; + MeshPosition_2x2__pos_x_1__pos_y_1 route_units__pos [0:4]; + logic [0:0] route_units__reset [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d route_units__recv__msg [0:4]; + logic [0:0] route_units__recv__rdy [0:4]; + logic [0:0] route_units__recv__val [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d route_units__send__msg [0:4][0:4]; + logic [0:0] route_units__send__rdy [0:4][0:4]; + logic [0:0] route_units__send__val [0:4][0:4]; + + DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__0 + ( + .clk( route_units__clk[0] ), + .pos( route_units__pos[0] ), + .reset( route_units__reset[0] ), + .recv__msg( route_units__recv__msg[0] ), + .recv__rdy( route_units__recv__rdy[0] ), + .recv__val( route_units__recv__val[0] ), + .send__msg( route_units__send__msg[0] ), + .send__rdy( route_units__send__rdy[0] ), + .send__val( route_units__send__val[0] ) + ); + + DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__1 + ( + .clk( route_units__clk[1] ), + .pos( route_units__pos[1] ), + .reset( route_units__reset[1] ), + .recv__msg( route_units__recv__msg[1] ), + .recv__rdy( route_units__recv__rdy[1] ), + .recv__val( route_units__recv__val[1] ), + .send__msg( route_units__send__msg[1] ), + .send__rdy( route_units__send__rdy[1] ), + .send__val( route_units__send__val[1] ) + ); + + DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__2 + ( + .clk( route_units__clk[2] ), + .pos( route_units__pos[2] ), + .reset( route_units__reset[2] ), + .recv__msg( route_units__recv__msg[2] ), + .recv__rdy( route_units__recv__rdy[2] ), + .recv__val( route_units__recv__val[2] ), + .send__msg( route_units__send__msg[2] ), + .send__rdy( route_units__send__rdy[2] ), + .send__val( route_units__send__val[2] ) + ); + + DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__3 + ( + .clk( route_units__clk[3] ), + .pos( route_units__pos[3] ), + .reset( route_units__reset[3] ), + .recv__msg( route_units__recv__msg[3] ), + .recv__rdy( route_units__recv__rdy[3] ), + .recv__val( route_units__recv__val[3] ), + .send__msg( route_units__send__msg[3] ), + .send__rdy( route_units__send__rdy[3] ), + .send__val( route_units__send__val[3] ) + ); + + DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__4 + ( + .clk( route_units__clk[4] ), + .pos( route_units__pos[4] ), + .reset( route_units__reset[4] ), + .recv__msg( route_units__recv__msg[4] ), + .recv__rdy( route_units__recv__rdy[4] ), + .recv__val( route_units__recv__val[4] ), + .send__msg( route_units__send__msg[4] ), + .send__rdy( route_units__send__rdy[4] ), + .send__val( route_units__send__val[4] ) + ); + + //------------------------------------------------------------- + // End of component route_units[0:4] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component switch_units[0:4] + //------------------------------------------------------------- + + logic [0:0] switch_units__clk [0:4]; + logic [0:0] switch_units__reset [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d switch_units__recv__msg [0:4][0:4]; + logic [0:0] switch_units__recv__rdy [0:4][0:4]; + logic [0:0] switch_units__recv__val [0:4][0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d switch_units__send__msg [0:4]; + logic [0:0] switch_units__send__rdy [0:4]; + logic [0:0] switch_units__send__val [0:4]; + + SwitchUnitRTL__1ccc072d8fcd170f switch_units__0 + ( + .clk( switch_units__clk[0] ), + .reset( switch_units__reset[0] ), + .recv__msg( switch_units__recv__msg[0] ), + .recv__rdy( switch_units__recv__rdy[0] ), + .recv__val( switch_units__recv__val[0] ), + .send__msg( switch_units__send__msg[0] ), + .send__rdy( switch_units__send__rdy[0] ), + .send__val( switch_units__send__val[0] ) + ); + + SwitchUnitRTL__1ccc072d8fcd170f switch_units__1 + ( + .clk( switch_units__clk[1] ), + .reset( switch_units__reset[1] ), + .recv__msg( switch_units__recv__msg[1] ), + .recv__rdy( switch_units__recv__rdy[1] ), + .recv__val( switch_units__recv__val[1] ), + .send__msg( switch_units__send__msg[1] ), + .send__rdy( switch_units__send__rdy[1] ), + .send__val( switch_units__send__val[1] ) + ); + + SwitchUnitRTL__1ccc072d8fcd170f switch_units__2 + ( + .clk( switch_units__clk[2] ), + .reset( switch_units__reset[2] ), + .recv__msg( switch_units__recv__msg[2] ), + .recv__rdy( switch_units__recv__rdy[2] ), + .recv__val( switch_units__recv__val[2] ), + .send__msg( switch_units__send__msg[2] ), + .send__rdy( switch_units__send__rdy[2] ), + .send__val( switch_units__send__val[2] ) + ); + + SwitchUnitRTL__1ccc072d8fcd170f switch_units__3 + ( + .clk( switch_units__clk[3] ), + .reset( switch_units__reset[3] ), + .recv__msg( switch_units__recv__msg[3] ), + .recv__rdy( switch_units__recv__rdy[3] ), + .recv__val( switch_units__recv__val[3] ), + .send__msg( switch_units__send__msg[3] ), + .send__rdy( switch_units__send__rdy[3] ), + .send__val( switch_units__send__val[3] ) + ); + + SwitchUnitRTL__1ccc072d8fcd170f switch_units__4 + ( + .clk( switch_units__clk[4] ), + .reset( switch_units__reset[4] ), + .recv__msg( switch_units__recv__msg[4] ), + .recv__rdy( switch_units__recv__rdy[4] ), + .recv__val( switch_units__recv__val[4] ), + .send__msg( switch_units__send__msg[4] ), + .send__rdy( switch_units__send__rdy[4] ), + .send__val( switch_units__send__val[4] ) + ); + + //------------------------------------------------------------- + // End of component switch_units[0:4] + //------------------------------------------------------------- + + assign input_units__clk[0] = clk; + assign input_units__reset[0] = reset; + assign input_units__clk[1] = clk; + assign input_units__reset[1] = reset; + assign input_units__clk[2] = clk; + assign input_units__reset[2] = reset; + assign input_units__clk[3] = clk; + assign input_units__reset[3] = reset; + assign input_units__clk[4] = clk; + assign input_units__reset[4] = reset; + assign route_units__clk[0] = clk; + assign route_units__reset[0] = reset; + assign route_units__clk[1] = clk; + assign route_units__reset[1] = reset; + assign route_units__clk[2] = clk; + assign route_units__reset[2] = reset; + assign route_units__clk[3] = clk; + assign route_units__reset[3] = reset; + assign route_units__clk[4] = clk; + assign route_units__reset[4] = reset; + assign switch_units__clk[0] = clk; + assign switch_units__reset[0] = reset; + assign switch_units__clk[1] = clk; + assign switch_units__reset[1] = reset; + assign switch_units__clk[2] = clk; + assign switch_units__reset[2] = reset; + assign switch_units__clk[3] = clk; + assign switch_units__reset[3] = reset; + assign switch_units__clk[4] = clk; + assign switch_units__reset[4] = reset; + assign output_units__clk[0] = clk; + assign output_units__reset[0] = reset; + assign output_units__clk[1] = clk; + assign output_units__reset[1] = reset; + assign output_units__clk[2] = clk; + assign output_units__reset[2] = reset; + assign output_units__clk[3] = clk; + assign output_units__reset[3] = reset; + assign output_units__clk[4] = clk; + assign output_units__reset[4] = reset; + assign input_units__recv__msg[0] = recv__msg[0]; + assign recv__rdy[0] = input_units__recv__rdy[0]; + assign input_units__recv__val[0] = recv__val[0]; + assign route_units__recv__msg[0] = input_units__send__msg[0]; + assign input_units__send__rdy[0] = route_units__recv__rdy[0]; + assign route_units__recv__val[0] = input_units__send__val[0]; + assign route_units__pos[0] = pos; + assign input_units__recv__msg[1] = recv__msg[1]; + assign recv__rdy[1] = input_units__recv__rdy[1]; + assign input_units__recv__val[1] = recv__val[1]; + assign route_units__recv__msg[1] = input_units__send__msg[1]; + assign input_units__send__rdy[1] = route_units__recv__rdy[1]; + assign route_units__recv__val[1] = input_units__send__val[1]; + assign route_units__pos[1] = pos; + assign input_units__recv__msg[2] = recv__msg[2]; + assign recv__rdy[2] = input_units__recv__rdy[2]; + assign input_units__recv__val[2] = recv__val[2]; + assign route_units__recv__msg[2] = input_units__send__msg[2]; + assign input_units__send__rdy[2] = route_units__recv__rdy[2]; + assign route_units__recv__val[2] = input_units__send__val[2]; + assign route_units__pos[2] = pos; + assign input_units__recv__msg[3] = recv__msg[3]; + assign recv__rdy[3] = input_units__recv__rdy[3]; + assign input_units__recv__val[3] = recv__val[3]; + assign route_units__recv__msg[3] = input_units__send__msg[3]; + assign input_units__send__rdy[3] = route_units__recv__rdy[3]; + assign route_units__recv__val[3] = input_units__send__val[3]; + assign route_units__pos[3] = pos; + assign input_units__recv__msg[4] = recv__msg[4]; + assign recv__rdy[4] = input_units__recv__rdy[4]; + assign input_units__recv__val[4] = recv__val[4]; + assign route_units__recv__msg[4] = input_units__send__msg[4]; + assign input_units__send__rdy[4] = route_units__recv__rdy[4]; + assign route_units__recv__val[4] = input_units__send__val[4]; + assign route_units__pos[4] = pos; + assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; + assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; + assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; + assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; + assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; + assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; + assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; + assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; + assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; + assign switch_units__recv__msg[3][0] = route_units__send__msg[0][3]; + assign route_units__send__rdy[0][3] = switch_units__recv__rdy[3][0]; + assign switch_units__recv__val[3][0] = route_units__send__val[0][3]; + assign switch_units__recv__msg[4][0] = route_units__send__msg[0][4]; + assign route_units__send__rdy[0][4] = switch_units__recv__rdy[4][0]; + assign switch_units__recv__val[4][0] = route_units__send__val[0][4]; + assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; + assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; + assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; + assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; + assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; + assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; + assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; + assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; + assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; + assign switch_units__recv__msg[3][1] = route_units__send__msg[1][3]; + assign route_units__send__rdy[1][3] = switch_units__recv__rdy[3][1]; + assign switch_units__recv__val[3][1] = route_units__send__val[1][3]; + assign switch_units__recv__msg[4][1] = route_units__send__msg[1][4]; + assign route_units__send__rdy[1][4] = switch_units__recv__rdy[4][1]; + assign switch_units__recv__val[4][1] = route_units__send__val[1][4]; + assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; + assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; + assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; + assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; + assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; + assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; + assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; + assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; + assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; + assign switch_units__recv__msg[3][2] = route_units__send__msg[2][3]; + assign route_units__send__rdy[2][3] = switch_units__recv__rdy[3][2]; + assign switch_units__recv__val[3][2] = route_units__send__val[2][3]; + assign switch_units__recv__msg[4][2] = route_units__send__msg[2][4]; + assign route_units__send__rdy[2][4] = switch_units__recv__rdy[4][2]; + assign switch_units__recv__val[4][2] = route_units__send__val[2][4]; + assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; + assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; + assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; + assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; + assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; + assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; + assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; + assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; + assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; + assign switch_units__recv__msg[3][3] = route_units__send__msg[3][3]; + assign route_units__send__rdy[3][3] = switch_units__recv__rdy[3][3]; + assign switch_units__recv__val[3][3] = route_units__send__val[3][3]; + assign switch_units__recv__msg[4][3] = route_units__send__msg[3][4]; + assign route_units__send__rdy[3][4] = switch_units__recv__rdy[4][3]; + assign switch_units__recv__val[4][3] = route_units__send__val[3][4]; + assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; + assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; + assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; + assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; + assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; + assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; + assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; + assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; + assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; + assign switch_units__recv__msg[3][4] = route_units__send__msg[4][3]; + assign route_units__send__rdy[4][3] = switch_units__recv__rdy[3][4]; + assign switch_units__recv__val[3][4] = route_units__send__val[4][3]; + assign switch_units__recv__msg[4][4] = route_units__send__msg[4][4]; + assign route_units__send__rdy[4][4] = switch_units__recv__rdy[4][4]; + assign switch_units__recv__val[4][4] = route_units__send__val[4][4]; + assign output_units__recv__msg[0] = switch_units__send__msg[0]; + assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; + assign output_units__recv__val[0] = switch_units__send__val[0]; + assign send__msg[0] = output_units__send__msg[0]; + assign output_units__send__rdy[0] = send__rdy[0]; + assign send__val[0] = output_units__send__val[0]; + assign output_units__recv__msg[1] = switch_units__send__msg[1]; + assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; + assign output_units__recv__val[1] = switch_units__send__val[1]; + assign send__msg[1] = output_units__send__msg[1]; + assign output_units__send__rdy[1] = send__rdy[1]; + assign send__val[1] = output_units__send__val[1]; + assign output_units__recv__msg[2] = switch_units__send__msg[2]; + assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; + assign output_units__recv__val[2] = switch_units__send__val[2]; + assign send__msg[2] = output_units__send__msg[2]; + assign output_units__send__rdy[2] = send__rdy[2]; + assign send__val[2] = output_units__send__val[2]; + assign output_units__recv__msg[3] = switch_units__send__msg[3]; + assign switch_units__send__rdy[3] = output_units__recv__rdy[3]; + assign output_units__recv__val[3] = switch_units__send__val[3]; + assign send__msg[3] = output_units__send__msg[3]; + assign output_units__send__rdy[3] = send__rdy[3]; + assign send__val[3] = output_units__send__val[3]; + assign output_units__recv__msg[4] = switch_units__send__msg[4]; + assign switch_units__send__rdy[4] = output_units__recv__rdy[4]; + assign output_units__recv__val[4] = switch_units__send__val[4]; + assign send__msg[4] = output_units__send__msg[4]; + assign output_units__send__rdy[4] = send__rdy[4]; + assign send__val[4] = output_units__send__val[4]; + +endmodule + + +// PyMTL Component MeshNetworkRTL Definition +// Full name: MeshNetworkRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__ncols_2__nrows_2__chl_lat_1 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/MeshNetworkRTL.py + +module MeshNetworkRTL__4ca7f469967df194 +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:3] , + output logic [0:0] recv__rdy [0:3] , + input logic [0:0] recv__val [0:3] , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:3] , + input logic [0:0] send__rdy [0:3] , + output logic [0:0] send__val [0:3] +); + //------------------------------------------------------------- + // Component channels[0:7] + //------------------------------------------------------------- + + logic [0:0] channels__clk [0:7]; + logic [0:0] channels__reset [0:7]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d channels__recv__msg [0:7]; + logic [0:0] channels__recv__rdy [0:7]; + logic [0:0] channels__recv__val [0:7]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d channels__send__msg [0:7]; + logic [0:0] channels__send__rdy [0:7]; + logic [0:0] channels__send__val [0:7]; + + ChannelRTL__551ecec02ed96ac9 channels__0 + ( + .clk( channels__clk[0] ), + .reset( channels__reset[0] ), + .recv__msg( channels__recv__msg[0] ), + .recv__rdy( channels__recv__rdy[0] ), + .recv__val( channels__recv__val[0] ), + .send__msg( channels__send__msg[0] ), + .send__rdy( channels__send__rdy[0] ), + .send__val( channels__send__val[0] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__1 + ( + .clk( channels__clk[1] ), + .reset( channels__reset[1] ), + .recv__msg( channels__recv__msg[1] ), + .recv__rdy( channels__recv__rdy[1] ), + .recv__val( channels__recv__val[1] ), + .send__msg( channels__send__msg[1] ), + .send__rdy( channels__send__rdy[1] ), + .send__val( channels__send__val[1] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__2 + ( + .clk( channels__clk[2] ), + .reset( channels__reset[2] ), + .recv__msg( channels__recv__msg[2] ), + .recv__rdy( channels__recv__rdy[2] ), + .recv__val( channels__recv__val[2] ), + .send__msg( channels__send__msg[2] ), + .send__rdy( channels__send__rdy[2] ), + .send__val( channels__send__val[2] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__3 + ( + .clk( channels__clk[3] ), + .reset( channels__reset[3] ), + .recv__msg( channels__recv__msg[3] ), + .recv__rdy( channels__recv__rdy[3] ), + .recv__val( channels__recv__val[3] ), + .send__msg( channels__send__msg[3] ), + .send__rdy( channels__send__rdy[3] ), + .send__val( channels__send__val[3] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__4 + ( + .clk( channels__clk[4] ), + .reset( channels__reset[4] ), + .recv__msg( channels__recv__msg[4] ), + .recv__rdy( channels__recv__rdy[4] ), + .recv__val( channels__recv__val[4] ), + .send__msg( channels__send__msg[4] ), + .send__rdy( channels__send__rdy[4] ), + .send__val( channels__send__val[4] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__5 + ( + .clk( channels__clk[5] ), + .reset( channels__reset[5] ), + .recv__msg( channels__recv__msg[5] ), + .recv__rdy( channels__recv__rdy[5] ), + .recv__val( channels__recv__val[5] ), + .send__msg( channels__send__msg[5] ), + .send__rdy( channels__send__rdy[5] ), + .send__val( channels__send__val[5] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__6 + ( + .clk( channels__clk[6] ), + .reset( channels__reset[6] ), + .recv__msg( channels__recv__msg[6] ), + .recv__rdy( channels__recv__rdy[6] ), + .recv__val( channels__recv__val[6] ), + .send__msg( channels__send__msg[6] ), + .send__rdy( channels__send__rdy[6] ), + .send__val( channels__send__val[6] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__7 + ( + .clk( channels__clk[7] ), + .reset( channels__reset[7] ), + .recv__msg( channels__recv__msg[7] ), + .recv__rdy( channels__recv__rdy[7] ), + .recv__val( channels__recv__val[7] ), + .send__msg( channels__send__msg[7] ), + .send__rdy( channels__send__rdy[7] ), + .send__val( channels__send__val[7] ) + ); + + //------------------------------------------------------------- + // End of component channels[0:7] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component routers[0:3] + //------------------------------------------------------------- + + logic [0:0] routers__clk [0:3]; + MeshPosition_2x2__pos_x_1__pos_y_1 routers__pos [0:3]; + logic [0:0] routers__reset [0:3]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d routers__recv__msg [0:3][0:4]; + logic [0:0] routers__recv__rdy [0:3][0:4]; + logic [0:0] routers__recv__val [0:3][0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d routers__send__msg [0:3][0:4]; + logic [0:0] routers__send__rdy [0:3][0:4]; + logic [0:0] routers__send__val [0:3][0:4]; + + MeshRouterRTL__574f02d875fdbb92 routers__0 + ( + .clk( routers__clk[0] ), + .pos( routers__pos[0] ), + .reset( routers__reset[0] ), + .recv__msg( routers__recv__msg[0] ), + .recv__rdy( routers__recv__rdy[0] ), + .recv__val( routers__recv__val[0] ), + .send__msg( routers__send__msg[0] ), + .send__rdy( routers__send__rdy[0] ), + .send__val( routers__send__val[0] ) + ); + + MeshRouterRTL__574f02d875fdbb92 routers__1 + ( + .clk( routers__clk[1] ), + .pos( routers__pos[1] ), + .reset( routers__reset[1] ), + .recv__msg( routers__recv__msg[1] ), + .recv__rdy( routers__recv__rdy[1] ), + .recv__val( routers__recv__val[1] ), + .send__msg( routers__send__msg[1] ), + .send__rdy( routers__send__rdy[1] ), + .send__val( routers__send__val[1] ) + ); + + MeshRouterRTL__574f02d875fdbb92 routers__2 + ( + .clk( routers__clk[2] ), + .pos( routers__pos[2] ), + .reset( routers__reset[2] ), + .recv__msg( routers__recv__msg[2] ), + .recv__rdy( routers__recv__rdy[2] ), + .recv__val( routers__recv__val[2] ), + .send__msg( routers__send__msg[2] ), + .send__rdy( routers__send__rdy[2] ), + .send__val( routers__send__val[2] ) + ); + + MeshRouterRTL__574f02d875fdbb92 routers__3 + ( + .clk( routers__clk[3] ), + .pos( routers__pos[3] ), + .reset( routers__reset[3] ), + .recv__msg( routers__recv__msg[3] ), + .recv__rdy( routers__recv__rdy[3] ), + .recv__val( routers__recv__val[3] ), + .send__msg( routers__send__msg[3] ), + .send__rdy( routers__send__rdy[3] ), + .send__val( routers__send__val[3] ) + ); + + //------------------------------------------------------------- + // End of component routers[0:3] + //------------------------------------------------------------- + + assign routers__clk[0] = clk; + assign routers__reset[0] = reset; + assign routers__clk[1] = clk; + assign routers__reset[1] = reset; + assign routers__clk[2] = clk; + assign routers__reset[2] = reset; + assign routers__clk[3] = clk; + assign routers__reset[3] = reset; + assign channels__clk[0] = clk; + assign channels__reset[0] = reset; + assign channels__clk[1] = clk; + assign channels__reset[1] = reset; + assign channels__clk[2] = clk; + assign channels__reset[2] = reset; + assign channels__clk[3] = clk; + assign channels__reset[3] = reset; + assign channels__clk[4] = clk; + assign channels__reset[4] = reset; + assign channels__clk[5] = clk; + assign channels__reset[5] = reset; + assign channels__clk[6] = clk; + assign channels__reset[6] = reset; + assign channels__clk[7] = clk; + assign channels__reset[7] = reset; + assign routers__pos[0].pos_x = 1'd0; + assign routers__pos[0].pos_y = 1'd0; + assign routers__pos[1].pos_x = 1'd1; + assign routers__pos[1].pos_y = 1'd0; + assign routers__pos[2].pos_x = 1'd0; + assign routers__pos[2].pos_y = 1'd1; + assign routers__pos[3].pos_x = 1'd1; + assign routers__pos[3].pos_y = 1'd1; + assign channels__recv__msg[0] = routers__send__msg[0][0]; + assign routers__send__rdy[0][0] = channels__recv__rdy[0]; + assign channels__recv__val[0] = routers__send__val[0][0]; + assign routers__recv__msg[2][1] = channels__send__msg[0]; + assign channels__send__rdy[0] = routers__recv__rdy[2][1]; + assign routers__recv__val[2][1] = channels__send__val[0]; + assign channels__recv__msg[1] = routers__send__msg[0][3]; + assign routers__send__rdy[0][3] = channels__recv__rdy[1]; + assign channels__recv__val[1] = routers__send__val[0][3]; + assign routers__recv__msg[1][2] = channels__send__msg[1]; + assign channels__send__rdy[1] = routers__recv__rdy[1][2]; + assign routers__recv__val[1][2] = channels__send__val[1]; + assign routers__recv__msg[0][4] = recv__msg[0]; + assign recv__rdy[0] = routers__recv__rdy[0][4]; + assign routers__recv__val[0][4] = recv__val[0]; + assign send__msg[0] = routers__send__msg[0][4]; + assign routers__send__rdy[0][4] = send__rdy[0]; + assign send__val[0] = routers__send__val[0][4]; + assign routers__send__rdy[0][1] = 1'd0; + assign routers__recv__val[0][1] = 1'd0; + assign routers__recv__msg[0][1] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign routers__send__rdy[0][2] = 1'd0; + assign routers__recv__val[0][2] = 1'd0; + assign routers__recv__msg[0][2] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign channels__recv__msg[2] = routers__send__msg[1][0]; + assign routers__send__rdy[1][0] = channels__recv__rdy[2]; + assign channels__recv__val[2] = routers__send__val[1][0]; + assign routers__recv__msg[3][1] = channels__send__msg[2]; + assign channels__send__rdy[2] = routers__recv__rdy[3][1]; + assign routers__recv__val[3][1] = channels__send__val[2]; + assign channels__recv__msg[3] = routers__send__msg[1][2]; + assign routers__send__rdy[1][2] = channels__recv__rdy[3]; + assign channels__recv__val[3] = routers__send__val[1][2]; + assign routers__recv__msg[0][3] = channels__send__msg[3]; + assign channels__send__rdy[3] = routers__recv__rdy[0][3]; + assign routers__recv__val[0][3] = channels__send__val[3]; + assign routers__recv__msg[1][4] = recv__msg[1]; + assign recv__rdy[1] = routers__recv__rdy[1][4]; + assign routers__recv__val[1][4] = recv__val[1]; + assign send__msg[1] = routers__send__msg[1][4]; + assign routers__send__rdy[1][4] = send__rdy[1]; + assign send__val[1] = routers__send__val[1][4]; + assign routers__send__rdy[1][1] = 1'd0; + assign routers__recv__val[1][1] = 1'd0; + assign routers__recv__msg[1][1] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign routers__send__rdy[1][3] = 1'd0; + assign routers__recv__val[1][3] = 1'd0; + assign routers__recv__msg[1][3] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign channels__recv__msg[4] = routers__send__msg[2][1]; + assign routers__send__rdy[2][1] = channels__recv__rdy[4]; + assign channels__recv__val[4] = routers__send__val[2][1]; + assign routers__recv__msg[0][0] = channels__send__msg[4]; + assign channels__send__rdy[4] = routers__recv__rdy[0][0]; + assign routers__recv__val[0][0] = channels__send__val[4]; + assign channels__recv__msg[5] = routers__send__msg[2][3]; + assign routers__send__rdy[2][3] = channels__recv__rdy[5]; + assign channels__recv__val[5] = routers__send__val[2][3]; + assign routers__recv__msg[3][2] = channels__send__msg[5]; + assign channels__send__rdy[5] = routers__recv__rdy[3][2]; + assign routers__recv__val[3][2] = channels__send__val[5]; + assign routers__recv__msg[2][4] = recv__msg[2]; + assign recv__rdy[2] = routers__recv__rdy[2][4]; + assign routers__recv__val[2][4] = recv__val[2]; + assign send__msg[2] = routers__send__msg[2][4]; + assign routers__send__rdy[2][4] = send__rdy[2]; + assign send__val[2] = routers__send__val[2][4]; + assign routers__send__rdy[2][0] = 1'd0; + assign routers__recv__val[2][0] = 1'd0; + assign routers__recv__msg[2][0] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign routers__send__rdy[2][2] = 1'd0; + assign routers__recv__val[2][2] = 1'd0; + assign routers__recv__msg[2][2] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign channels__recv__msg[6] = routers__send__msg[3][1]; + assign routers__send__rdy[3][1] = channels__recv__rdy[6]; + assign channels__recv__val[6] = routers__send__val[3][1]; + assign routers__recv__msg[1][0] = channels__send__msg[6]; + assign channels__send__rdy[6] = routers__recv__rdy[1][0]; + assign routers__recv__val[1][0] = channels__send__val[6]; + assign channels__recv__msg[7] = routers__send__msg[3][2]; + assign routers__send__rdy[3][2] = channels__recv__rdy[7]; + assign channels__recv__val[7] = routers__send__val[3][2]; + assign routers__recv__msg[2][3] = channels__send__msg[7]; + assign channels__send__rdy[7] = routers__recv__rdy[2][3]; + assign routers__recv__val[2][3] = channels__send__val[7]; + assign routers__recv__msg[3][4] = recv__msg[3]; + assign recv__rdy[3] = routers__recv__rdy[3][4]; + assign routers__recv__val[3][4] = recv__val[3]; + assign send__msg[3] = routers__send__msg[3][4]; + assign routers__send__rdy[3][4] = send__rdy[3]; + assign send__val[3] = routers__send__val[3][4]; + assign routers__send__rdy[3][0] = 1'd0; + assign routers__recv__val[3][0] = 1'd0; + assign routers__recv__msg[3][0] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign routers__send__rdy[3][3] = 1'd0; + assign routers__recv__val[3][3] = 1'd0; + assign routers__recv__msg[3][3] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + +endmodule + + +// PyMTL Component MeshMultiCgraRTL Definition +// Full name: MeshMultiCgraRTL__CgraPayloadType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__cgra_rows_2__cgra_columns_2__tile_rows_4__tile_columns_4__ctrl_mem_size_16__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_registers_per_reg_bank_16__num_ctrl_4__total_steps_38__mem_access_is_combinational_True__FunctionUnit_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ]__per_cgra_topology_Mesh__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__support_task_switching_False +// At /home/ajokai/cgra/VectorCGRAfork0/multi_cgra/MeshMultiCgraRTL.py + +module MeshMultiCgraRTL__975ce70dc1a0740a +( + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , + output logic [0:0] recv_from_cpu_pkt__rdy , + input logic [0:0] recv_from_cpu_pkt__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , + input logic [0:0] send_to_cpu_pkt__rdy , + output logic [0:0] send_to_cpu_pkt__val +); + //------------------------------------------------------------- + // Component cgra[0:3] + //------------------------------------------------------------- + + logic [6:0] cgra__address_lower [0:3]; + logic [6:0] cgra__address_upper [0:3]; + logic [1:0] cgra__cgra_id [0:3]; + logic [0:0] cgra__clk [0:3]; + logic [0:0] cgra__reset [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_east__msg [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_east__rdy [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_east__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_north__msg [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_north__rdy [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_north__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_south__msg [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_south__rdy [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_south__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_west__msg [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_west__rdy [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_west__val [0:3][0:3]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 cgra__recv_from_cpu_pkt__msg [0:3]; + logic [0:0] cgra__recv_from_cpu_pkt__rdy [0:3]; + logic [0:0] cgra__recv_from_cpu_pkt__val [0:3]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d cgra__recv_from_inter_cgra_noc__msg [0:3]; + logic [0:0] cgra__recv_from_inter_cgra_noc__rdy [0:3]; + logic [0:0] cgra__recv_from_inter_cgra_noc__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_east__msg [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_east__rdy [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_east__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_north__msg [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_north__rdy [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_north__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_south__msg [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_south__rdy [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_south__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_west__msg [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_west__rdy [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_west__val [0:3][0:3]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 cgra__send_to_cpu_pkt__msg [0:3]; + logic [0:0] cgra__send_to_cpu_pkt__rdy [0:3]; + logic [0:0] cgra__send_to_cpu_pkt__val [0:3]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d cgra__send_to_inter_cgra_noc__msg [0:3]; + logic [0:0] cgra__send_to_inter_cgra_noc__rdy [0:3]; + logic [0:0] cgra__send_to_inter_cgra_noc__val [0:3]; + + CgraRTL__72d915b46abe89cb cgra__0 + ( + .address_lower( cgra__address_lower[0] ), + .address_upper( cgra__address_upper[0] ), + .cgra_id( cgra__cgra_id[0] ), + .clk( cgra__clk[0] ), + .reset( cgra__reset[0] ), + .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[0] ), + .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[0] ), + .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[0] ), + .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[0] ), + .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[0] ), + .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[0] ), + .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[0] ), + .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[0] ), + .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[0] ), + .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[0] ), + .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[0] ), + .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[0] ), + .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[0] ), + .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[0] ), + .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[0] ), + .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[0] ), + .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[0] ), + .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[0] ), + .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[0] ), + .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[0] ), + .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[0] ), + .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[0] ), + .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[0] ), + .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[0] ), + .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[0] ), + .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[0] ), + .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[0] ), + .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[0] ), + .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[0] ), + .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[0] ), + .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[0] ), + .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[0] ), + .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[0] ), + .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[0] ), + .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[0] ), + .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[0] ) + ); + + CgraRTL__72d915b46abe89cb cgra__1 + ( + .address_lower( cgra__address_lower[1] ), + .address_upper( cgra__address_upper[1] ), + .cgra_id( cgra__cgra_id[1] ), + .clk( cgra__clk[1] ), + .reset( cgra__reset[1] ), + .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[1] ), + .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[1] ), + .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[1] ), + .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[1] ), + .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[1] ), + .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[1] ), + .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[1] ), + .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[1] ), + .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[1] ), + .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[1] ), + .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[1] ), + .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[1] ), + .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[1] ), + .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[1] ), + .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[1] ), + .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[1] ), + .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[1] ), + .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[1] ), + .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[1] ), + .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[1] ), + .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[1] ), + .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[1] ), + .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[1] ), + .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[1] ), + .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[1] ), + .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[1] ), + .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[1] ), + .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[1] ), + .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[1] ), + .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[1] ), + .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[1] ), + .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[1] ), + .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[1] ), + .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[1] ), + .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[1] ), + .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[1] ) + ); + + CgraRTL__72d915b46abe89cb cgra__2 + ( + .address_lower( cgra__address_lower[2] ), + .address_upper( cgra__address_upper[2] ), + .cgra_id( cgra__cgra_id[2] ), + .clk( cgra__clk[2] ), + .reset( cgra__reset[2] ), + .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[2] ), + .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[2] ), + .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[2] ), + .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[2] ), + .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[2] ), + .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[2] ), + .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[2] ), + .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[2] ), + .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[2] ), + .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[2] ), + .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[2] ), + .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[2] ), + .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[2] ), + .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[2] ), + .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[2] ), + .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[2] ), + .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[2] ), + .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[2] ), + .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[2] ), + .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[2] ), + .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[2] ), + .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[2] ), + .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[2] ), + .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[2] ), + .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[2] ), + .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[2] ), + .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[2] ), + .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[2] ), + .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[2] ), + .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[2] ), + .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[2] ), + .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[2] ), + .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[2] ), + .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[2] ), + .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[2] ), + .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[2] ) + ); + + CgraRTL__72d915b46abe89cb cgra__3 + ( + .address_lower( cgra__address_lower[3] ), + .address_upper( cgra__address_upper[3] ), + .cgra_id( cgra__cgra_id[3] ), + .clk( cgra__clk[3] ), + .reset( cgra__reset[3] ), + .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[3] ), + .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[3] ), + .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[3] ), + .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[3] ), + .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[3] ), + .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[3] ), + .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[3] ), + .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[3] ), + .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[3] ), + .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[3] ), + .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[3] ), + .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[3] ), + .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[3] ), + .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[3] ), + .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[3] ), + .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[3] ), + .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[3] ), + .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[3] ), + .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[3] ), + .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[3] ), + .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[3] ), + .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[3] ), + .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[3] ), + .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[3] ), + .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[3] ), + .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[3] ), + .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[3] ), + .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[3] ), + .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[3] ), + .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[3] ), + .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[3] ), + .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[3] ), + .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[3] ), + .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[3] ), + .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[3] ), + .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[3] ) + ); + + //------------------------------------------------------------- + // End of component cgra[0:3] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mesh + //------------------------------------------------------------- + + logic [0:0] mesh__clk; + logic [0:0] mesh__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mesh__recv__msg [0:3]; + logic [0:0] mesh__recv__rdy [0:3]; + logic [0:0] mesh__recv__val [0:3]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mesh__send__msg [0:3]; + logic [0:0] mesh__send__rdy [0:3]; + logic [0:0] mesh__send__val [0:3]; + + MeshNetworkRTL__4ca7f469967df194 mesh + ( + .clk( mesh__clk ), + .reset( mesh__reset ), + .recv__msg( mesh__recv__msg ), + .recv__rdy( mesh__recv__rdy ), + .recv__val( mesh__recv__val ), + .send__msg( mesh__send__msg ), + .send__rdy( mesh__send__rdy ), + .send__val( mesh__send__val ) + ); + + //------------------------------------------------------------- + // End of component mesh + //------------------------------------------------------------- + + assign cgra__clk[0] = clk; + assign cgra__reset[0] = reset; + assign cgra__clk[1] = clk; + assign cgra__reset[1] = reset; + assign cgra__clk[2] = clk; + assign cgra__reset[2] = reset; + assign cgra__clk[3] = clk; + assign cgra__reset[3] = reset; + assign mesh__clk = clk; + assign mesh__reset = reset; + assign cgra__recv_from_inter_cgra_noc__msg[0] = mesh__send__msg[0]; + assign mesh__send__rdy[0] = cgra__recv_from_inter_cgra_noc__rdy[0]; + assign cgra__recv_from_inter_cgra_noc__val[0] = mesh__send__val[0]; + assign mesh__recv__msg[0] = cgra__send_to_inter_cgra_noc__msg[0]; + assign cgra__send_to_inter_cgra_noc__rdy[0] = mesh__recv__rdy[0]; + assign mesh__recv__val[0] = cgra__send_to_inter_cgra_noc__val[0]; + assign cgra__recv_from_inter_cgra_noc__msg[1] = mesh__send__msg[1]; + assign mesh__send__rdy[1] = cgra__recv_from_inter_cgra_noc__rdy[1]; + assign cgra__recv_from_inter_cgra_noc__val[1] = mesh__send__val[1]; + assign mesh__recv__msg[1] = cgra__send_to_inter_cgra_noc__msg[1]; + assign cgra__send_to_inter_cgra_noc__rdy[1] = mesh__recv__rdy[1]; + assign mesh__recv__val[1] = cgra__send_to_inter_cgra_noc__val[1]; + assign cgra__recv_from_inter_cgra_noc__msg[2] = mesh__send__msg[2]; + assign mesh__send__rdy[2] = cgra__recv_from_inter_cgra_noc__rdy[2]; + assign cgra__recv_from_inter_cgra_noc__val[2] = mesh__send__val[2]; + assign mesh__recv__msg[2] = cgra__send_to_inter_cgra_noc__msg[2]; + assign cgra__send_to_inter_cgra_noc__rdy[2] = mesh__recv__rdy[2]; + assign mesh__recv__val[2] = cgra__send_to_inter_cgra_noc__val[2]; + assign cgra__recv_from_inter_cgra_noc__msg[3] = mesh__send__msg[3]; + assign mesh__send__rdy[3] = cgra__recv_from_inter_cgra_noc__rdy[3]; + assign cgra__recv_from_inter_cgra_noc__val[3] = mesh__send__val[3]; + assign mesh__recv__msg[3] = cgra__send_to_inter_cgra_noc__msg[3]; + assign cgra__send_to_inter_cgra_noc__rdy[3] = mesh__recv__rdy[3]; + assign mesh__recv__val[3] = cgra__send_to_inter_cgra_noc__val[3]; + assign cgra__cgra_id[0] = 2'd0; + assign cgra__cgra_id[1] = 2'd1; + assign cgra__cgra_id[2] = 2'd2; + assign cgra__cgra_id[3] = 2'd3; + assign cgra__address_lower[0] = 7'd0; + assign cgra__address_upper[0] = 7'd31; + assign cgra__address_lower[1] = 7'd32; + assign cgra__address_upper[1] = 7'd63; + assign cgra__address_lower[2] = 7'd64; + assign cgra__address_upper[2] = 7'd95; + assign cgra__address_lower[3] = 7'd96; + assign cgra__address_upper[3] = 7'd127; + assign cgra__recv_from_cpu_pkt__msg[0] = recv_from_cpu_pkt__msg; + assign recv_from_cpu_pkt__rdy = cgra__recv_from_cpu_pkt__rdy[0]; + assign cgra__recv_from_cpu_pkt__val[0] = recv_from_cpu_pkt__val; + assign send_to_cpu_pkt__msg = cgra__send_to_cpu_pkt__msg[0]; + assign cgra__send_to_cpu_pkt__rdy[0] = send_to_cpu_pkt__rdy; + assign send_to_cpu_pkt__val = cgra__send_to_cpu_pkt__val[0]; + assign cgra__recv_from_cpu_pkt__val[1] = 1'd0; + assign cgra__recv_from_cpu_pkt__msg[1] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign cgra__send_to_cpu_pkt__rdy[1] = 1'd0; + assign cgra__recv_from_cpu_pkt__val[2] = 1'd0; + assign cgra__recv_from_cpu_pkt__msg[2] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign cgra__send_to_cpu_pkt__rdy[2] = 1'd0; + assign cgra__recv_from_cpu_pkt__val[3] = 1'd0; + assign cgra__recv_from_cpu_pkt__msg[3] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign cgra__send_to_cpu_pkt__rdy[3] = 1'd0; + assign cgra__send_data_on_boundary_south__rdy[0][0] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[0][0] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[0][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[0][1] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[0][1] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[0][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[0][2] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[0][2] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[0][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[0][3] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[0][3] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[0][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[0][0] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[0][0] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[0][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[0][1] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[0][1] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[0][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[0][2] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[0][2] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[0][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[0][3] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[0][3] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[0][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[1][0] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[1][0] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[1][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[1][1] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[1][1] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[1][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[1][2] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[1][2] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[1][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[1][3] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[1][3] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[1][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__recv_data_on_boundary_east__msg[0][0] = cgra__send_data_on_boundary_west__msg[1][0]; + assign cgra__send_data_on_boundary_west__rdy[1][0] = cgra__recv_data_on_boundary_east__rdy[0][0]; + assign cgra__recv_data_on_boundary_east__val[0][0] = cgra__send_data_on_boundary_west__val[1][0]; + assign cgra__recv_data_on_boundary_west__msg[1][0] = cgra__send_data_on_boundary_east__msg[0][0]; + assign cgra__send_data_on_boundary_east__rdy[0][0] = cgra__recv_data_on_boundary_west__rdy[1][0]; + assign cgra__recv_data_on_boundary_west__val[1][0] = cgra__send_data_on_boundary_east__val[0][0]; + assign cgra__recv_data_on_boundary_east__msg[0][1] = cgra__send_data_on_boundary_west__msg[1][1]; + assign cgra__send_data_on_boundary_west__rdy[1][1] = cgra__recv_data_on_boundary_east__rdy[0][1]; + assign cgra__recv_data_on_boundary_east__val[0][1] = cgra__send_data_on_boundary_west__val[1][1]; + assign cgra__recv_data_on_boundary_west__msg[1][1] = cgra__send_data_on_boundary_east__msg[0][1]; + assign cgra__send_data_on_boundary_east__rdy[0][1] = cgra__recv_data_on_boundary_west__rdy[1][1]; + assign cgra__recv_data_on_boundary_west__val[1][1] = cgra__send_data_on_boundary_east__val[0][1]; + assign cgra__recv_data_on_boundary_east__msg[0][2] = cgra__send_data_on_boundary_west__msg[1][2]; + assign cgra__send_data_on_boundary_west__rdy[1][2] = cgra__recv_data_on_boundary_east__rdy[0][2]; + assign cgra__recv_data_on_boundary_east__val[0][2] = cgra__send_data_on_boundary_west__val[1][2]; + assign cgra__recv_data_on_boundary_west__msg[1][2] = cgra__send_data_on_boundary_east__msg[0][2]; + assign cgra__send_data_on_boundary_east__rdy[0][2] = cgra__recv_data_on_boundary_west__rdy[1][2]; + assign cgra__recv_data_on_boundary_west__val[1][2] = cgra__send_data_on_boundary_east__val[0][2]; + assign cgra__recv_data_on_boundary_east__msg[0][3] = cgra__send_data_on_boundary_west__msg[1][3]; + assign cgra__send_data_on_boundary_west__rdy[1][3] = cgra__recv_data_on_boundary_east__rdy[0][3]; + assign cgra__recv_data_on_boundary_east__val[0][3] = cgra__send_data_on_boundary_west__val[1][3]; + assign cgra__recv_data_on_boundary_west__msg[1][3] = cgra__send_data_on_boundary_east__msg[0][3]; + assign cgra__send_data_on_boundary_east__rdy[0][3] = cgra__recv_data_on_boundary_west__rdy[1][3]; + assign cgra__recv_data_on_boundary_west__val[1][3] = cgra__send_data_on_boundary_east__val[0][3]; + assign cgra__send_data_on_boundary_east__rdy[1][0] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[1][0] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[1][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[1][1] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[1][1] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[1][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[1][2] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[1][2] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[1][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[1][3] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[1][3] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[1][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__recv_data_on_boundary_north__msg[0][0] = cgra__send_data_on_boundary_south__msg[2][0]; + assign cgra__send_data_on_boundary_south__rdy[2][0] = cgra__recv_data_on_boundary_north__rdy[0][0]; + assign cgra__recv_data_on_boundary_north__val[0][0] = cgra__send_data_on_boundary_south__val[2][0]; + assign cgra__recv_data_on_boundary_south__msg[2][0] = cgra__send_data_on_boundary_north__msg[0][0]; + assign cgra__send_data_on_boundary_north__rdy[0][0] = cgra__recv_data_on_boundary_south__rdy[2][0]; + assign cgra__recv_data_on_boundary_south__val[2][0] = cgra__send_data_on_boundary_north__val[0][0]; + assign cgra__recv_data_on_boundary_north__msg[0][1] = cgra__send_data_on_boundary_south__msg[2][1]; + assign cgra__send_data_on_boundary_south__rdy[2][1] = cgra__recv_data_on_boundary_north__rdy[0][1]; + assign cgra__recv_data_on_boundary_north__val[0][1] = cgra__send_data_on_boundary_south__val[2][1]; + assign cgra__recv_data_on_boundary_south__msg[2][1] = cgra__send_data_on_boundary_north__msg[0][1]; + assign cgra__send_data_on_boundary_north__rdy[0][1] = cgra__recv_data_on_boundary_south__rdy[2][1]; + assign cgra__recv_data_on_boundary_south__val[2][1] = cgra__send_data_on_boundary_north__val[0][1]; + assign cgra__recv_data_on_boundary_north__msg[0][2] = cgra__send_data_on_boundary_south__msg[2][2]; + assign cgra__send_data_on_boundary_south__rdy[2][2] = cgra__recv_data_on_boundary_north__rdy[0][2]; + assign cgra__recv_data_on_boundary_north__val[0][2] = cgra__send_data_on_boundary_south__val[2][2]; + assign cgra__recv_data_on_boundary_south__msg[2][2] = cgra__send_data_on_boundary_north__msg[0][2]; + assign cgra__send_data_on_boundary_north__rdy[0][2] = cgra__recv_data_on_boundary_south__rdy[2][2]; + assign cgra__recv_data_on_boundary_south__val[2][2] = cgra__send_data_on_boundary_north__val[0][2]; + assign cgra__recv_data_on_boundary_north__msg[0][3] = cgra__send_data_on_boundary_south__msg[2][3]; + assign cgra__send_data_on_boundary_south__rdy[2][3] = cgra__recv_data_on_boundary_north__rdy[0][3]; + assign cgra__recv_data_on_boundary_north__val[0][3] = cgra__send_data_on_boundary_south__val[2][3]; + assign cgra__recv_data_on_boundary_south__msg[2][3] = cgra__send_data_on_boundary_north__msg[0][3]; + assign cgra__send_data_on_boundary_north__rdy[0][3] = cgra__recv_data_on_boundary_south__rdy[2][3]; + assign cgra__recv_data_on_boundary_south__val[2][3] = cgra__send_data_on_boundary_north__val[0][3]; + assign cgra__send_data_on_boundary_north__rdy[2][0] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[2][0] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[2][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[2][1] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[2][1] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[2][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[2][2] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[2][2] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[2][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[2][3] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[2][3] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[2][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[2][0] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[2][0] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[2][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[2][1] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[2][1] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[2][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[2][2] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[2][2] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[2][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[2][3] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[2][3] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[2][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__recv_data_on_boundary_north__msg[1][0] = cgra__send_data_on_boundary_south__msg[3][0]; + assign cgra__send_data_on_boundary_south__rdy[3][0] = cgra__recv_data_on_boundary_north__rdy[1][0]; + assign cgra__recv_data_on_boundary_north__val[1][0] = cgra__send_data_on_boundary_south__val[3][0]; + assign cgra__recv_data_on_boundary_south__msg[3][0] = cgra__send_data_on_boundary_north__msg[1][0]; + assign cgra__send_data_on_boundary_north__rdy[1][0] = cgra__recv_data_on_boundary_south__rdy[3][0]; + assign cgra__recv_data_on_boundary_south__val[3][0] = cgra__send_data_on_boundary_north__val[1][0]; + assign cgra__recv_data_on_boundary_north__msg[1][1] = cgra__send_data_on_boundary_south__msg[3][1]; + assign cgra__send_data_on_boundary_south__rdy[3][1] = cgra__recv_data_on_boundary_north__rdy[1][1]; + assign cgra__recv_data_on_boundary_north__val[1][1] = cgra__send_data_on_boundary_south__val[3][1]; + assign cgra__recv_data_on_boundary_south__msg[3][1] = cgra__send_data_on_boundary_north__msg[1][1]; + assign cgra__send_data_on_boundary_north__rdy[1][1] = cgra__recv_data_on_boundary_south__rdy[3][1]; + assign cgra__recv_data_on_boundary_south__val[3][1] = cgra__send_data_on_boundary_north__val[1][1]; + assign cgra__recv_data_on_boundary_north__msg[1][2] = cgra__send_data_on_boundary_south__msg[3][2]; + assign cgra__send_data_on_boundary_south__rdy[3][2] = cgra__recv_data_on_boundary_north__rdy[1][2]; + assign cgra__recv_data_on_boundary_north__val[1][2] = cgra__send_data_on_boundary_south__val[3][2]; + assign cgra__recv_data_on_boundary_south__msg[3][2] = cgra__send_data_on_boundary_north__msg[1][2]; + assign cgra__send_data_on_boundary_north__rdy[1][2] = cgra__recv_data_on_boundary_south__rdy[3][2]; + assign cgra__recv_data_on_boundary_south__val[3][2] = cgra__send_data_on_boundary_north__val[1][2]; + assign cgra__recv_data_on_boundary_north__msg[1][3] = cgra__send_data_on_boundary_south__msg[3][3]; + assign cgra__send_data_on_boundary_south__rdy[3][3] = cgra__recv_data_on_boundary_north__rdy[1][3]; + assign cgra__recv_data_on_boundary_north__val[1][3] = cgra__send_data_on_boundary_south__val[3][3]; + assign cgra__recv_data_on_boundary_south__msg[3][3] = cgra__send_data_on_boundary_north__msg[1][3]; + assign cgra__send_data_on_boundary_north__rdy[1][3] = cgra__recv_data_on_boundary_south__rdy[3][3]; + assign cgra__recv_data_on_boundary_south__val[3][3] = cgra__send_data_on_boundary_north__val[1][3]; + assign cgra__send_data_on_boundary_north__rdy[3][0] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[3][0] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[3][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[3][1] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[3][1] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[3][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[3][2] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[3][2] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[3][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[3][3] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[3][3] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[3][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__recv_data_on_boundary_east__msg[2][0] = cgra__send_data_on_boundary_west__msg[3][0]; + assign cgra__send_data_on_boundary_west__rdy[3][0] = cgra__recv_data_on_boundary_east__rdy[2][0]; + assign cgra__recv_data_on_boundary_east__val[2][0] = cgra__send_data_on_boundary_west__val[3][0]; + assign cgra__recv_data_on_boundary_west__msg[3][0] = cgra__send_data_on_boundary_east__msg[2][0]; + assign cgra__send_data_on_boundary_east__rdy[2][0] = cgra__recv_data_on_boundary_west__rdy[3][0]; + assign cgra__recv_data_on_boundary_west__val[3][0] = cgra__send_data_on_boundary_east__val[2][0]; + assign cgra__recv_data_on_boundary_east__msg[2][1] = cgra__send_data_on_boundary_west__msg[3][1]; + assign cgra__send_data_on_boundary_west__rdy[3][1] = cgra__recv_data_on_boundary_east__rdy[2][1]; + assign cgra__recv_data_on_boundary_east__val[2][1] = cgra__send_data_on_boundary_west__val[3][1]; + assign cgra__recv_data_on_boundary_west__msg[3][1] = cgra__send_data_on_boundary_east__msg[2][1]; + assign cgra__send_data_on_boundary_east__rdy[2][1] = cgra__recv_data_on_boundary_west__rdy[3][1]; + assign cgra__recv_data_on_boundary_west__val[3][1] = cgra__send_data_on_boundary_east__val[2][1]; + assign cgra__recv_data_on_boundary_east__msg[2][2] = cgra__send_data_on_boundary_west__msg[3][2]; + assign cgra__send_data_on_boundary_west__rdy[3][2] = cgra__recv_data_on_boundary_east__rdy[2][2]; + assign cgra__recv_data_on_boundary_east__val[2][2] = cgra__send_data_on_boundary_west__val[3][2]; + assign cgra__recv_data_on_boundary_west__msg[3][2] = cgra__send_data_on_boundary_east__msg[2][2]; + assign cgra__send_data_on_boundary_east__rdy[2][2] = cgra__recv_data_on_boundary_west__rdy[3][2]; + assign cgra__recv_data_on_boundary_west__val[3][2] = cgra__send_data_on_boundary_east__val[2][2]; + assign cgra__recv_data_on_boundary_east__msg[2][3] = cgra__send_data_on_boundary_west__msg[3][3]; + assign cgra__send_data_on_boundary_west__rdy[3][3] = cgra__recv_data_on_boundary_east__rdy[2][3]; + assign cgra__recv_data_on_boundary_east__val[2][3] = cgra__send_data_on_boundary_west__val[3][3]; + assign cgra__recv_data_on_boundary_west__msg[3][3] = cgra__send_data_on_boundary_east__msg[2][3]; + assign cgra__send_data_on_boundary_east__rdy[2][3] = cgra__recv_data_on_boundary_west__rdy[3][3]; + assign cgra__recv_data_on_boundary_west__val[3][3] = cgra__send_data_on_boundary_east__val[2][3]; + assign cgra__send_data_on_boundary_east__rdy[3][0] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[3][0] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[3][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[3][1] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[3][1] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[3][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[3][2] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[3][2] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[3][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[3][3] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[3][3] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[3][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + +endmodule diff --git a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v new file mode 100644 index 00000000..3abd9dd5 --- /dev/null +++ b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v @@ -0,0 +1,138 @@ + +// VT_INPUT_DELAY, VTB_OUTPUT_ASSERT_DELAY are timestamps relative to the rising edge. +`define VTB_INPUT_DELAY 1 +`define VTB_OUTPUT_ASSERT_DELAY 3 + +// CYCLE_TIME and INTRA_CYCLE_TIME are duration of time. +`define CYCLE_TIME 4 +`define INTRA_CYCLE_TIME (`VTB_OUTPUT_ASSERT_DELAY-`VTB_INPUT_DELAY) + +`timescale 1ns/1ns + +`define T(a0,a1,a2,a3,a4,a5) \ + t(a0,a1,a2,a3,a4,a5,`__LINE__) + +// Tick one extra cycle upon an error. +`define VTB_TEST_FAIL(lineno, out, ref, port_name) \ + $display("- Timestamp : %0d (default unit: ns)", $time); \ + $display("- Cycle number : %0d (variable: cycle_count)", cycle_count); \ + $display("- line number : line %0d in MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v.cases", lineno); \ + $display("- port name : %s", port_name); \ + $display("- expected value : 0x%x", ref); \ + $display("- actual value : 0x%x", out); \ + $display(""); \ + #(`CYCLE_TIME-`INTRA_CYCLE_TIME); \ + cycle_count += 1; \ + #`CYCLE_TIME; \ + cycle_count += 1; \ + $fatal; + +`define CHECK(lineno, out, ref, port_name) \ + if ((|(out ^ out)) == 1'b0) ; \ + else begin \ + $display(""); \ + $display("The test bench received a value containing X/Z's! Please note"); \ + $display("that the VTB is pessmistic about X's and you should make sure"); \ + $display("all output ports of your DUT does not produce X's after reset."); \ + `VTB_TEST_FAIL(lineno, out, ref, port_name) \ + end \ + if (out != ref) begin \ + $display(""); \ + $display("The test bench received an incorrect value!"); \ + `VTB_TEST_FAIL(lineno, out, ref, port_name) \ + end + +module MeshMultiCgraRTL__975ce70dc1a0740a_tb; + // convention + logic clk; + logic reset; + integer cycle_count; + + logic [216:0] recv_from_cpu_pkt__msg ; + logic [0:0] recv_from_cpu_pkt__rdy ; + logic [0:0] recv_from_cpu_pkt__val ; + logic [216:0] send_to_cpu_pkt__msg ; + logic [0:0] send_to_cpu_pkt__rdy ; + logic [0:0] send_to_cpu_pkt__val ; + + task t( + input logic [216:0] inp_recv_from_cpu_pkt__msg, + input logic [0:0] ref_recv_from_cpu_pkt__rdy, + input logic [0:0] inp_recv_from_cpu_pkt__val, + input logic [216:0] ref_send_to_cpu_pkt__msg, + input logic [0:0] inp_send_to_cpu_pkt__rdy, + input logic [0:0] ref_send_to_cpu_pkt__val, + integer lineno + ); + begin + recv_from_cpu_pkt__msg = inp_recv_from_cpu_pkt__msg; + recv_from_cpu_pkt__val = inp_recv_from_cpu_pkt__val; + send_to_cpu_pkt__rdy = inp_send_to_cpu_pkt__rdy; + #`INTRA_CYCLE_TIME; + `CHECK(lineno, recv_from_cpu_pkt__rdy, ref_recv_from_cpu_pkt__rdy, "recv_from_cpu_pkt.rdy (recv_from_cpu_pkt__rdy in Verilog)"); + `CHECK(lineno, send_to_cpu_pkt__msg, ref_send_to_cpu_pkt__msg, "send_to_cpu_pkt.msg (send_to_cpu_pkt__msg in Verilog)"); + `CHECK(lineno, send_to_cpu_pkt__val, ref_send_to_cpu_pkt__val, "send_to_cpu_pkt.val (send_to_cpu_pkt__val in Verilog)"); + #(`CYCLE_TIME-`INTRA_CYCLE_TIME); + cycle_count += 1; + end + endtask + + // use 25% clock cycle, so #1 for setup #2 for sim #1 for hold + always #(`CYCLE_TIME/2) clk = ~clk; + + // DUT name + // By default we use the translated name of the Verilog component. But you can change + // that by defining the VTB_TOP_MODULE_NAME macro through the simulator command line + // options (e.g., for VCS you can do +define+VTB_TOP_MODULE_NAME=YourTopModuleName). +`ifdef VTB_TOP_MODULE_NAME + `VTB_TOP_MODULE_NAME DUT +`else + MeshMultiCgraRTL__975ce70dc1a0740a DUT +`endif + ( + .clk(clk), + .reset(reset), + .recv_from_cpu_pkt__msg(recv_from_cpu_pkt__msg), + .recv_from_cpu_pkt__rdy(recv_from_cpu_pkt__rdy), + .recv_from_cpu_pkt__val(recv_from_cpu_pkt__val), + .send_to_cpu_pkt__msg(send_to_cpu_pkt__msg), + .send_to_cpu_pkt__rdy(send_to_cpu_pkt__rdy), + .send_to_cpu_pkt__val(send_to_cpu_pkt__val) + ); + + initial begin + assert(0 <= `VTB_INPUT_DELAY) + else $fatal("\n=====\n\nVTB_INPUT_DELAY should >= 0\n\n=====\n"); + + assert(`VTB_INPUT_DELAY < `VTB_OUTPUT_ASSERT_DELAY) + else $fatal("\n=====\n\nVTB_OUTPUT_ASSERT_DELAY should be larger than VTB_INPUT_DELAY\n\n=====\n"); + + assert(`VTB_OUTPUT_ASSERT_DELAY <= `CYCLE_TIME) + else $fatal("\n=====\n\nVTB_OUTPUT_ASSERT_DELAY should be smaller than or equal to CYCLE_TIME\n\n=====\n"); + + cycle_count = 0; + clk = 1'b0; // NEED TO DO THIS TO HAVE FALLING EDGE AT TIME 0 + reset = 1'b1; // TODO reset active low/high + #(`CYCLE_TIME/2); + + // Now we are talking + #`VTB_INPUT_DELAY; + #`CYCLE_TIME; + cycle_count = 1; + #`CYCLE_TIME; + cycle_count = 2; + // 2 cycles plus input delay + reset = 1'b0; + + `include "MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v.cases" + + $display(""); + $display(" [ passed ]"); + $display(""); + + // Tick one extra cycle for better waveform + #`CYCLE_TIME; + cycle_count += 1; + $finish; + end +endmodule diff --git a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v.cases b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v.cases new file mode 100644 index 00000000..7641020c --- /dev/null +++ b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v.cases @@ -0,0 +1,201 @@ +`T('h0000000000000000000000000000000000000000000000000000000,'h1,'h0,'h0000000000000000000000000000000000000000000000000000000,'h1,'h0); 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From aa1d18459b20a701d9c8fbbf16b9e2a8cbbddfc7 Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Mon, 5 Jan 2026 23:52:54 -0700 Subject: [PATCH 02/12] [Vector FU] Ensuring the whole signal is assigned to avoid xprop in SV. --- fu/vector/VectorAllReduceRTL.py | 1 + fu/vector/VectorMulComboRTL.py | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/fu/vector/VectorAllReduceRTL.py b/fu/vector/VectorAllReduceRTL.py index 58d91ac4..cd740f61 100644 --- a/fu/vector/VectorAllReduceRTL.py +++ b/fu/vector/VectorAllReduceRTL.py @@ -90,6 +90,7 @@ def construct(s, DataType, CtrlType, high = (i + 1) * sub_bw # s.connect() works with slice objects directly during elaboration. s.temp_result[i][0:sub_bw] //= s.recv_in[0].msg.payload[low:high] + s.temp_result[i][sub_bw:data_bitwidth] //= 0 @update def update_result(): diff --git a/fu/vector/VectorMulComboRTL.py b/fu/vector/VectorMulComboRTL.py index 880f88d1..b77236e9 100644 --- a/fu/vector/VectorMulComboRTL.py +++ b/fu/vector/VectorMulComboRTL.py @@ -95,8 +95,8 @@ def update_input_output(): for i in range(num_lanes): s.temp_result[i] @= TempDataType(0) - s.Fu[i].recv_in[0].msg[0:sub_bw] @= FuDataType() - s.Fu[i].recv_in[1].msg[0:sub_bw] @= FuDataType() + s.Fu[i].recv_in[0].msg @= 0 + s.Fu[i].recv_in[1].msg @= 0 if s.recv_opt.msg.operation == OPT_VEC_MUL: # Connection: split into vectorized FUs From a57fdfa9d481ee27dcf942673635a331fdbbd98e Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Mon, 5 Jan 2026 23:53:58 -0700 Subject: [PATCH 03/12] [PyMTL output] Adding generated RTL file with init fixes. --- ...__explicit_vector_global_reduce__pickled.v | 23496 ++++++++++++++++ 1 file changed, 23496 insertions(+) create mode 100644 multi_cgra/test/MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v diff --git a/multi_cgra/test/MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v b/multi_cgra/test/MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v new file mode 100644 index 00000000..8b2e5fa9 --- /dev/null +++ b/multi_cgra/test/MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v @@ -0,0 +1,23496 @@ +//------------------------------------------------------------------------- +// MeshMultiCgraRTL__explicit_vector_global_reduce.v +//------------------------------------------------------------------------- +// This file is generated by PyMTL SystemVerilog translation pass. + +// PyMTL BitStruct CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Definition +typedef struct packed { + logic [63:0] payload; + logic [0:0] predicate; + logic [0:0] bypass; + logic [0:0] delay; +} CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1; + +// PyMTL BitStruct CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Definition +typedef struct packed { + logic [6:0] operation; + logic [3:0][2:0] fu_in; + logic [7:0][2:0] routing_xbar_outport; + logic [7:0][1:0] fu_xbar_outport; + logic [2:0] vector_factor_power; + logic [0:0] is_last_ctrl; + logic [3:0][1:0] write_reg_from; + logic [3:0][3:0] write_reg_idx; + logic [3:0][0:0] read_reg_from; + logic [3:0][3:0] read_reg_idx; +} CGRAConfig_7_4_2_4_4_3__49d22cda396bec88; + +// PyMTL BitStruct MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Definition +typedef struct packed { + logic [4:0] cmd; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; + logic [6:0] data_addr; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 ctrl; + logic [3:0] ctrl_addr; +} MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a; + +// PyMTL BitStruct InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d Definition +typedef struct packed { + logic [1:0] src; + logic [1:0] dst; + logic [0:0] src_x; + logic [0:0] src_y; + logic [0:0] dst_x; + logic [0:0] dst_y; + logic [4:0] src_tile_id; + logic [4:0] dst_tile_id; + logic [2:0] remote_src_port; + logic [7:0] opaque; + logic [1:0] vc_id; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a payload; +} InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d; + +// PyMTL BitStruct IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 Definition +typedef struct packed { + logic [4:0] src; + logic [4:0] dst; + logic [1:0] src_cgra_id; + logic [1:0] dst_cgra_id; + logic [0:0] src_cgra_x; + logic [0:0] src_cgra_y; + logic [0:0] dst_cgra_x; + logic [0:0] dst_cgra_y; + logic [7:0] opaque; + logic [0:0] vc_id; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a payload; +} IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69; + +// PyMTL BitStruct ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad Definition +typedef struct packed { + logic [0:0] dst; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d inter_cgra_pkt; +} ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad; + +// PyMTL BitStruct MemAccessPacket_8_3_128__43c148781d2f2a57 Definition +typedef struct packed { + logic [2:0] src; + logic [1:0] dst; + logic [6:0] addr; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; + logic [1:0] src_cgra; + logic [4:0] src_tile; + logic [2:0] remote_src_port; + logic [0:0] streaming_rd; + logic [6:0] streaming_rd_stride; + logic [6:0] streaming_rd_end_addr; +} MemAccessPacket_8_3_128__43c148781d2f2a57; + +// PyMTL BitStruct MemAccessPacket_3_8_128__9f21b0bcdad2c061 Definition +typedef struct packed { + logic [1:0] src; + logic [2:0] dst; + logic [6:0] addr; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; + logic [1:0] src_cgra; + logic [4:0] src_tile; + logic [2:0] remote_src_port; + logic [0:0] streaming_rd; + logic [6:0] streaming_rd_stride; + logic [6:0] streaming_rd_end_addr; +} MemAccessPacket_3_8_128__9f21b0bcdad2c061; + +// PyMTL BitStruct MeshPosition_2x2__pos_x_1__pos_y_1 Definition +typedef struct packed { + logic [0:0] pos_x; + logic [0:0] pos_y; +} MeshPosition_2x2__pos_x_1__pos_y_1; + +// PyMTL Component NormalQueueCtrlRTL Definition +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueCtrlRTL__num_entries_2 +( + input logic [0:0] clk , + output logic [1:0] count , + output logic [0:0] raddr , + output logic [0:0] recv_rdy , + input logic [0:0] recv_val , + input logic [0:0] reset , + input logic [0:0] send_rdy , + output logic [0:0] send_val , + output logic [0:0] waddr , + output logic [0:0] wen +); + localparam logic [1:0] __const__num_entries_at__lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy = 2'd2; + localparam logic [1:0] __const__num_entries_at_up_reg = 2'd2; + logic [0:0] head; + logic [0:0] recv_xfer; + logic [0:0] send_xfer; + logic [0:0] tail; + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:121 + // s.recv_rdy //= lambda: s.count < num_entries + + always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy + recv_rdy = count < 2'( __const__num_entries_at__lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy ); + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:124 + // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy + + always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_xfer + recv_xfer = recv_val & recv_rdy; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:122 + // s.send_val //= lambda: s.count > 0 + + always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_send_val + send_val = count > 2'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:125 + // s.send_xfer //= lambda: s.send_val & s.send_rdy + + always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_send_xfer + send_xfer = send_val & send_rdy; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:127 + // @update_ff + // def up_reg(): + // + // if s.reset: + // s.head <<= 0 + // s.tail <<= 0 + // s.count <<= 0 + // + // else: + // if s.recv_xfer: + // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 + // + // if s.send_xfer: + // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 + // + // if s.recv_xfer & ~s.send_xfer: + // s.count <<= s.count + 1 + // elif ~s.recv_xfer & s.send_xfer: + // s.count <<= s.count - 1 + + always_ff @(posedge clk) begin : up_reg + if ( reset ) begin + head <= 1'd0; + tail <= 1'd0; + count <= 2'd0; + end + else begin + if ( recv_xfer ) begin + tail <= ( tail < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? tail + 1'd1 : 1'd0; + end + if ( send_xfer ) begin + head <= ( head < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? head + 1'd1 : 1'd0; + end + if ( recv_xfer & ( ~send_xfer ) ) begin + count <= count + 2'd1; + end + else if ( ( ~recv_xfer ) & send_xfer ) begin + count <= count - 2'd1; + end + end + end + + assign wen = recv_xfer; + assign waddr = tail; + assign raddr = head; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__a60a466e6e87778c +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__b5f6715511792c61 +( + input logic [0:0] clk , + input logic [0:0] raddr , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv_msg , + input logic [0:0] reset , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__a60a466e6e87778c rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__b5f6715511792c61 +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__raddr; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad dpath__recv_msg; + logic [0:0] dpath__reset; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__b5f6715511792c61 dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component InputUnitRTL Definition +// Full name: InputUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__QueueType_NormalQueueRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py + +module InputUnitRTL__d71c3d07db1f649e +( + input logic [0:0] clk , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queue + //------------------------------------------------------------- + + logic [0:0] queue__clk; + logic [1:0] queue__count; + logic [0:0] queue__reset; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad queue__recv__msg; + logic [0:0] queue__recv__rdy; + logic [0:0] queue__recv__val; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad queue__send__msg; + logic [0:0] queue__send__rdy; + logic [0:0] queue__send__val; + + NormalQueueRTL__b5f6715511792c61 queue + ( + .clk( queue__clk ), + .count( queue__count ), + .reset( queue__reset ), + .recv__msg( queue__recv__msg ), + .recv__rdy( queue__recv__rdy ), + .recv__val( queue__recv__val ), + .send__msg( queue__send__msg ), + .send__rdy( queue__send__rdy ), + .send__val( queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component queue + //------------------------------------------------------------- + + assign queue__clk = clk; + assign queue__reset = reset; + assign queue__recv__msg = recv__msg; + assign recv__rdy = queue__recv__rdy; + assign queue__recv__val = recv__val; + assign send__msg = queue__send__msg; + assign queue__send__rdy = send__rdy; + assign send__val = queue__send__val; + +endmodule + + +// PyMTL Component OutputUnitRTL Definition +// Full name: OutputUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__QueueType_None +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py + +module OutputUnitRTL__c199f9a52ff41678 +( + input logic [0:0] clk , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + assign send__msg = recv__msg; + assign recv__rdy = send__rdy; + assign send__val = recv__val; + +endmodule + + +// PyMTL Component XbarRouteUnitRTL Definition +// Full name: XbarRouteUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_outports_1 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py + +module XbarRouteUnitRTL__2110ed3935ab4c25 +( + input logic [0:0] clk , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg [0:0] , + input logic [0:0] send__rdy [0:0] , + output logic [0:0] send__val [0:0] +); + localparam logic [0:0] __const__num_outports_at_up_ru_routing = 1'd1; + logic [0:0] out_dir; + logic [0:0] send_val; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 + // @update + // def up_ru_recv_rdy(): + // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 + + always_comb begin : up_ru_recv_rdy + recv__rdy = send__rdy[out_dir] > 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 + // @update + // def up_ru_routing(): + // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) + // + // for i in range( num_outports ): + // s.send[i].val @= b1(0) + // + // if s.recv.val: + // s.send[ s.out_dir ].val @= b1(1) + + always_comb begin : up_ru_routing + out_dir = recv__msg.dst; + for ( int unsigned i = 1'd0; i < 1'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) + send__val[1'(i)] = 1'd0; + if ( recv__val ) begin + send__val[out_dir] = 1'd1; + end + end + + assign send__msg[0] = recv__msg; + assign send_val[0:0] = send__val[0]; + +endmodule + + +// PyMTL Component RegEnRst Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py + +module RegEnRst__Type_Bits6__reset_value_1 +( + input logic [0:0] clk , + input logic [0:0] en , + input logic [5:0] in_ , + output logic [5:0] out , + input logic [0:0] reset +); + localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 + // @update_ff + // def up_regenrst(): + // if s.reset: s.out <<= reset_value + // elif s.en: s.out <<= s.in_ + + always_ff @(posedge clk) begin : up_regenrst + if ( reset ) begin + out <= 6'( __const__reset_value_at_up_regenrst ); + end + else if ( en ) begin + out <= in_; + end + end + +endmodule + + +// PyMTL Component RoundRobinArbiterEn Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py + +module RoundRobinArbiterEn__nreqs_6 +( + input logic [0:0] clk , + input logic [0:0] en , + output logic [5:0] grants , + input logic [5:0] reqs , + input logic [0:0] reset +); + localparam logic [2:0] __const__nreqs_at_comb_reqs_int = 3'd6; + localparam logic [3:0] __const__nreqsX2_at_comb_reqs_int = 4'd12; + localparam logic [2:0] __const__nreqs_at_comb_grants = 3'd6; + localparam logic [2:0] __const__nreqs_at_comb_priority_int = 3'd6; + localparam logic [3:0] __const__nreqsX2_at_comb_priority_int = 4'd12; + localparam logic [3:0] __const__nreqsX2_at_comb_kills = 4'd12; + localparam logic [3:0] __const__nreqsX2_at_comb_grants_int = 4'd12; + logic [11:0] grants_int; + logic [12:0] kills; + logic [0:0] priority_en; + logic [11:0] priority_int; + logic [11:0] reqs_int; + //------------------------------------------------------------- + // Component priority_reg + //------------------------------------------------------------- + + logic [0:0] priority_reg__clk; + logic [0:0] priority_reg__en; + logic [5:0] priority_reg__in_; + logic [5:0] priority_reg__out; + logic [0:0] priority_reg__reset; + + RegEnRst__Type_Bits6__reset_value_1 priority_reg + ( + .clk( priority_reg__clk ), + .en( priority_reg__en ), + .in_( priority_reg__in_ ), + .out( priority_reg__out ), + .reset( priority_reg__reset ) + ); + + //------------------------------------------------------------- + // End of component priority_reg + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 + // @update + // def comb_grants(): + // for i in range( nreqs ): + // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] + + always_comb begin : comb_grants + for ( int unsigned i = 1'd0; i < 3'( __const__nreqs_at_comb_grants ); i += 1'd1 ) + grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 + // @update + // def comb_grants_int(): + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.grants_int[i] @= s.reqs_int[i] + // else: + // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] + + always_comb begin : comb_grants_int + for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + grants_int[4'(i)] = reqs_int[4'(i)]; + end + else + grants_int[4'(i)] = ( ~kills[4'(i)] ) & reqs_int[4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 + // @update + // def comb_kills(): + // s.kills[0] @= 1 + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.kills[i+1] @= s.reqs_int[i] + // else: + // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) + + always_comb begin : comb_kills + kills[4'd0] = 1'd1; + for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + kills[4'(i) + 4'd1] = reqs_int[4'(i)]; + end + else + kills[4'(i) + 4'd1] = kills[4'(i)] | ( ( ~kills[4'(i)] ) & reqs_int[4'(i)] ); + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 + // @update + // def comb_priority_en(): + // s.priority_en @= ( s.grants != 0 ) & s.en + + always_comb begin : comb_priority_en + priority_en = ( grants != 6'd0 ) & en; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 + // @update + // def comb_priority_int(): + // s.priority_int[ 0:nreqs ] @= s.priority_reg.out + // s.priority_int[nreqs:nreqsX2] @= 0 + + always_comb begin : comb_priority_int + priority_int[4'd5:4'd0] = priority_reg__out; + priority_int[4'd11:4'( __const__nreqs_at_comb_priority_int )] = 6'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 + // @update + // def comb_reqs_int(): + // s.reqs_int [ 0:nreqs ] @= s.reqs + // s.reqs_int [nreqs:nreqsX2] @= s.reqs + + always_comb begin : comb_reqs_int + reqs_int[4'd5:4'd0] = reqs; + reqs_int[4'd11:4'( __const__nreqs_at_comb_reqs_int )] = reqs; + end + + assign priority_reg__clk = clk; + assign priority_reg__reset = reset; + assign priority_reg__en = priority_en; + assign priority_reg__in_[5:1] = grants[4:0]; + assign priority_reg__in_[0:0] = grants[5:5]; + +endmodule + + +// PyMTL Component Encoder Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py + +module Encoder__in_nbits_6__out_nbits_3 +( + input logic [0:0] clk , + input logic [5:0] in_ , + output logic [2:0] out , + input logic [0:0] reset +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 + // @update + // def encode(): + // s.out @= 0 + // for i in range( s.in_nbits ): + // if s.in_[i]: + // s.out @= i + + always_comb begin : encode + out = 3'd0; + for ( int unsigned i = 1'd0; i < 3'd6; i += 1'd1 ) + if ( in_[3'(i)] ) begin + out = 3'(i); + end + end + +endmodule + + +// PyMTL Component Mux Definition +// Full name: Mux__Type_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__ninputs_6 +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__899292f481a8b227 +( + input logic [0:0] clk , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad in_ [0:5], + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad out , + input logic [0:0] reset , + input logic [2:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component SwitchUnitRTL Definition +// Full name: SwitchUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_inports_6 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py + +module SwitchUnitRTL__2dc7ee83ee1f485f +( + input logic [0:0] clk , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg [0:5] , + output logic [0:0] recv__rdy [0:5] , + input logic [0:0] recv__val [0:5] , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd6; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [5:0] arbiter__grants; + logic [5:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_6 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [5:0] encoder__in_; + logic [2:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_6__out_nbits_3 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad mux__in_ [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad mux__out; + logic [0:0] mux__reset; + logic [2:0] mux__sel; + + Mux__899292f481a8b227 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 + // @update + // def up_get_en(): + // for i in range( num_inports ): + // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) + + always_comb begin : up_get_en + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) + recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 + // @update + // def up_send_val(): + // s.send.val @= s.arbiter.grants > 0 + + always_comb begin : up_send_val + send__val = arbiter__grants > 6'd0; + end + + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign arbiter__en = 1'd1; + assign mux__clk = clk; + assign mux__reset = reset; + assign send__msg = mux__out; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign encoder__in_ = arbiter__grants; + assign mux__sel = encoder__out; + assign arbiter__reqs[0:0] = recv__val[0]; + assign mux__in_[0] = recv__msg[0]; + assign arbiter__reqs[1:1] = recv__val[1]; + assign mux__in_[1] = recv__msg[1]; + assign arbiter__reqs[2:2] = recv__val[2]; + assign mux__in_[2] = recv__msg[2]; + assign arbiter__reqs[3:3] = recv__val[3]; + assign mux__in_[3] = recv__msg[3]; + assign arbiter__reqs[4:4] = recv__val[4]; + assign mux__in_[4] = recv__msg[4]; + assign arbiter__reqs[5:5] = recv__val[5]; + assign mux__in_[5] = recv__msg[5]; + +endmodule + + +// PyMTL Component XbarRTL Definition +// Full name: XbarRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_inports_6__num_outports_1__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRTL.py + +module XbarRTL__51e7846dd37f4a41 +( + input logic [0:0] clk , + input logic [0:0] reset , + input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg [0:5] , + output logic [0:0] recv__rdy [0:5] , + input logic [0:0] recv__val [0:5] , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg [0:0] , + input logic [0:0] send__rdy [0:0] , + output logic [0:0] send__val [0:0] +); + //------------------------------------------------------------- + // Component input_units[0:5] + //------------------------------------------------------------- + + logic [0:0] input_units__clk [0:5]; + logic [0:0] input_units__reset [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad input_units__recv__msg [0:5]; + logic [0:0] input_units__recv__rdy [0:5]; + logic [0:0] input_units__recv__val [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad input_units__send__msg [0:5]; + logic [0:0] input_units__send__rdy [0:5]; + logic [0:0] input_units__send__val [0:5]; + + InputUnitRTL__d71c3d07db1f649e input_units__0 + ( + .clk( input_units__clk[0] ), + .reset( input_units__reset[0] ), + .recv__msg( input_units__recv__msg[0] ), + .recv__rdy( input_units__recv__rdy[0] ), + .recv__val( input_units__recv__val[0] ), + .send__msg( input_units__send__msg[0] ), + .send__rdy( input_units__send__rdy[0] ), + .send__val( input_units__send__val[0] ) + ); + + InputUnitRTL__d71c3d07db1f649e input_units__1 + ( + .clk( input_units__clk[1] ), + .reset( input_units__reset[1] ), + .recv__msg( input_units__recv__msg[1] ), + .recv__rdy( input_units__recv__rdy[1] ), + .recv__val( input_units__recv__val[1] ), + .send__msg( input_units__send__msg[1] ), + .send__rdy( input_units__send__rdy[1] ), + .send__val( input_units__send__val[1] ) + ); + + InputUnitRTL__d71c3d07db1f649e input_units__2 + ( + .clk( input_units__clk[2] ), + .reset( input_units__reset[2] ), + .recv__msg( input_units__recv__msg[2] ), + .recv__rdy( input_units__recv__rdy[2] ), + .recv__val( input_units__recv__val[2] ), + .send__msg( input_units__send__msg[2] ), + .send__rdy( input_units__send__rdy[2] ), + .send__val( input_units__send__val[2] ) + ); + + InputUnitRTL__d71c3d07db1f649e input_units__3 + ( + .clk( input_units__clk[3] ), + .reset( input_units__reset[3] ), + .recv__msg( input_units__recv__msg[3] ), + .recv__rdy( input_units__recv__rdy[3] ), + .recv__val( input_units__recv__val[3] ), + .send__msg( input_units__send__msg[3] ), + .send__rdy( input_units__send__rdy[3] ), + .send__val( input_units__send__val[3] ) + ); + + InputUnitRTL__d71c3d07db1f649e input_units__4 + ( + .clk( input_units__clk[4] ), + .reset( input_units__reset[4] ), + .recv__msg( input_units__recv__msg[4] ), + .recv__rdy( input_units__recv__rdy[4] ), + .recv__val( input_units__recv__val[4] ), + .send__msg( input_units__send__msg[4] ), + .send__rdy( input_units__send__rdy[4] ), + .send__val( input_units__send__val[4] ) + ); + + InputUnitRTL__d71c3d07db1f649e input_units__5 + ( + .clk( input_units__clk[5] ), + .reset( input_units__reset[5] ), + .recv__msg( input_units__recv__msg[5] ), + .recv__rdy( input_units__recv__rdy[5] ), + .recv__val( input_units__recv__val[5] ), + .send__msg( input_units__send__msg[5] ), + .send__rdy( input_units__send__rdy[5] ), + .send__val( input_units__send__val[5] ) + ); + + //------------------------------------------------------------- + // End of component input_units[0:5] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component output_units[0:0] + //------------------------------------------------------------- + + logic [0:0] output_units__clk [0:0]; + logic [0:0] output_units__reset [0:0]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad output_units__recv__msg [0:0]; + logic [0:0] output_units__recv__rdy [0:0]; + logic [0:0] output_units__recv__val [0:0]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad output_units__send__msg [0:0]; + logic [0:0] output_units__send__rdy [0:0]; + logic [0:0] output_units__send__val [0:0]; + + OutputUnitRTL__c199f9a52ff41678 output_units__0 + ( + .clk( output_units__clk[0] ), + .reset( output_units__reset[0] ), + .recv__msg( output_units__recv__msg[0] ), + .recv__rdy( output_units__recv__rdy[0] ), + .recv__val( output_units__recv__val[0] ), + .send__msg( output_units__send__msg[0] ), + .send__rdy( output_units__send__rdy[0] ), + .send__val( output_units__send__val[0] ) + ); + + //------------------------------------------------------------- + // End of component output_units[0:0] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component route_units[0:5] + //------------------------------------------------------------- + + logic [0:0] route_units__clk [0:5]; + logic [0:0] route_units__reset [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad route_units__recv__msg [0:5]; + logic [0:0] route_units__recv__rdy [0:5]; + logic [0:0] route_units__recv__val [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad route_units__send__msg [0:5][0:0]; + logic [0:0] route_units__send__rdy [0:5][0:0]; + logic [0:0] route_units__send__val [0:5][0:0]; + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__0 + ( + .clk( route_units__clk[0] ), + .reset( route_units__reset[0] ), + .recv__msg( route_units__recv__msg[0] ), + .recv__rdy( route_units__recv__rdy[0] ), + .recv__val( route_units__recv__val[0] ), + .send__msg( route_units__send__msg[0] ), + .send__rdy( route_units__send__rdy[0] ), + .send__val( route_units__send__val[0] ) + ); + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__1 + ( + .clk( route_units__clk[1] ), + .reset( route_units__reset[1] ), + .recv__msg( route_units__recv__msg[1] ), + .recv__rdy( route_units__recv__rdy[1] ), + .recv__val( route_units__recv__val[1] ), + .send__msg( route_units__send__msg[1] ), + .send__rdy( route_units__send__rdy[1] ), + .send__val( route_units__send__val[1] ) + ); + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__2 + ( + .clk( route_units__clk[2] ), + .reset( route_units__reset[2] ), + .recv__msg( route_units__recv__msg[2] ), + .recv__rdy( route_units__recv__rdy[2] ), + .recv__val( route_units__recv__val[2] ), + .send__msg( route_units__send__msg[2] ), + .send__rdy( route_units__send__rdy[2] ), + .send__val( route_units__send__val[2] ) + ); + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__3 + ( + .clk( route_units__clk[3] ), + .reset( route_units__reset[3] ), + .recv__msg( route_units__recv__msg[3] ), + .recv__rdy( route_units__recv__rdy[3] ), + .recv__val( route_units__recv__val[3] ), + .send__msg( route_units__send__msg[3] ), + .send__rdy( route_units__send__rdy[3] ), + .send__val( route_units__send__val[3] ) + ); + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__4 + ( + .clk( route_units__clk[4] ), + .reset( route_units__reset[4] ), + .recv__msg( route_units__recv__msg[4] ), + .recv__rdy( route_units__recv__rdy[4] ), + .recv__val( route_units__recv__val[4] ), + .send__msg( route_units__send__msg[4] ), + .send__rdy( route_units__send__rdy[4] ), + .send__val( route_units__send__val[4] ) + ); + + XbarRouteUnitRTL__2110ed3935ab4c25 route_units__5 + ( + .clk( route_units__clk[5] ), + .reset( route_units__reset[5] ), + .recv__msg( route_units__recv__msg[5] ), + .recv__rdy( route_units__recv__rdy[5] ), + .recv__val( route_units__recv__val[5] ), + .send__msg( route_units__send__msg[5] ), + .send__rdy( route_units__send__rdy[5] ), + .send__val( route_units__send__val[5] ) + ); + + //------------------------------------------------------------- + // End of component route_units[0:5] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component switch_units[0:0] + //------------------------------------------------------------- + + logic [0:0] switch_units__clk [0:0]; + logic [0:0] switch_units__reset [0:0]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad switch_units__recv__msg [0:0][0:5]; + logic [0:0] switch_units__recv__rdy [0:0][0:5]; + logic [0:0] switch_units__recv__val [0:0][0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad switch_units__send__msg [0:0]; + logic [0:0] switch_units__send__rdy [0:0]; + logic [0:0] switch_units__send__val [0:0]; + + SwitchUnitRTL__2dc7ee83ee1f485f switch_units__0 + ( + .clk( switch_units__clk[0] ), + .reset( switch_units__reset[0] ), + .recv__msg( switch_units__recv__msg[0] ), + .recv__rdy( switch_units__recv__rdy[0] ), + .recv__val( switch_units__recv__val[0] ), + .send__msg( switch_units__send__msg[0] ), + .send__rdy( switch_units__send__rdy[0] ), + .send__val( switch_units__send__val[0] ) + ); + + //------------------------------------------------------------- + // End of component switch_units[0:0] + //------------------------------------------------------------- + + assign input_units__clk[0] = clk; + assign input_units__reset[0] = reset; + assign input_units__clk[1] = clk; + assign input_units__reset[1] = reset; + assign input_units__clk[2] = clk; + assign input_units__reset[2] = reset; + assign input_units__clk[3] = clk; + assign input_units__reset[3] = reset; + assign input_units__clk[4] = clk; + assign input_units__reset[4] = reset; + assign input_units__clk[5] = clk; + assign input_units__reset[5] = reset; + assign route_units__clk[0] = clk; + assign route_units__reset[0] = reset; + assign route_units__clk[1] = clk; + assign route_units__reset[1] = reset; + assign route_units__clk[2] = clk; + assign route_units__reset[2] = reset; + assign route_units__clk[3] = clk; + assign route_units__reset[3] = reset; + assign route_units__clk[4] = clk; + assign route_units__reset[4] = reset; + assign route_units__clk[5] = clk; + assign route_units__reset[5] = reset; + assign switch_units__clk[0] = clk; + assign switch_units__reset[0] = reset; + assign output_units__clk[0] = clk; + assign output_units__reset[0] = reset; + assign input_units__recv__msg[0] = recv__msg[0]; + assign recv__rdy[0] = input_units__recv__rdy[0]; + assign input_units__recv__val[0] = recv__val[0]; + assign route_units__recv__msg[0] = input_units__send__msg[0]; + assign input_units__send__rdy[0] = route_units__recv__rdy[0]; + assign route_units__recv__val[0] = input_units__send__val[0]; + assign input_units__recv__msg[1] = recv__msg[1]; + assign recv__rdy[1] = input_units__recv__rdy[1]; + assign input_units__recv__val[1] = recv__val[1]; + assign route_units__recv__msg[1] = input_units__send__msg[1]; + assign input_units__send__rdy[1] = route_units__recv__rdy[1]; + assign route_units__recv__val[1] = input_units__send__val[1]; + assign input_units__recv__msg[2] = recv__msg[2]; + assign recv__rdy[2] = input_units__recv__rdy[2]; + assign input_units__recv__val[2] = recv__val[2]; + assign route_units__recv__msg[2] = input_units__send__msg[2]; + assign input_units__send__rdy[2] = route_units__recv__rdy[2]; + assign route_units__recv__val[2] = input_units__send__val[2]; + assign input_units__recv__msg[3] = recv__msg[3]; + assign recv__rdy[3] = input_units__recv__rdy[3]; + assign input_units__recv__val[3] = recv__val[3]; + assign route_units__recv__msg[3] = input_units__send__msg[3]; + assign input_units__send__rdy[3] = route_units__recv__rdy[3]; + assign route_units__recv__val[3] = input_units__send__val[3]; + assign input_units__recv__msg[4] = recv__msg[4]; + assign recv__rdy[4] = input_units__recv__rdy[4]; + assign input_units__recv__val[4] = recv__val[4]; + assign route_units__recv__msg[4] = input_units__send__msg[4]; + assign input_units__send__rdy[4] = route_units__recv__rdy[4]; + assign route_units__recv__val[4] = input_units__send__val[4]; + assign input_units__recv__msg[5] = recv__msg[5]; + assign recv__rdy[5] = input_units__recv__rdy[5]; + assign input_units__recv__val[5] = recv__val[5]; + assign route_units__recv__msg[5] = input_units__send__msg[5]; + assign input_units__send__rdy[5] = route_units__recv__rdy[5]; + assign route_units__recv__val[5] = input_units__send__val[5]; + assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; + assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; + assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; + assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; + assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; + assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; + assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; + assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; + assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; + assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; + assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; + assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; + assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; + assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; + assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; + assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; + assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; + assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; + assign output_units__recv__msg[0] = switch_units__send__msg[0]; + assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; + assign output_units__recv__val[0] = switch_units__send__val[0]; + assign send__msg[0] = output_units__send__msg[0]; + assign output_units__send__rdy[0] = send__rdy[0]; + assign send__val[0] = output_units__send__val[0]; + +endmodule + + +// PyMTL Component NormalQueueCtrlRTL Definition +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueCtrlRTL__num_entries_16 +( + input logic [0:0] clk , + output logic [4:0] count , + output logic [3:0] raddr , + output logic [0:0] recv_rdy , + input logic [0:0] recv_val , + input logic [0:0] reset , + input logic [0:0] send_rdy , + output logic [0:0] send_val , + output logic [3:0] waddr , + output logic [0:0] wen +); + localparam logic [4:0] __const__num_entries_at__lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy = 5'd16; + localparam logic [4:0] __const__num_entries_at_up_reg = 5'd16; + logic [3:0] head; + logic [0:0] recv_xfer; + logic [0:0] send_xfer; + logic [3:0] tail; + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:121 + // s.recv_rdy //= lambda: s.count < num_entries + + always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy + recv_rdy = count < 5'( __const__num_entries_at__lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy ); + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:124 + // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy + + always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_xfer + recv_xfer = recv_val & recv_rdy; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:122 + // s.send_val //= lambda: s.count > 0 + + always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_send_val + send_val = count > 5'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:125 + // s.send_xfer //= lambda: s.send_val & s.send_rdy + + always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_send_xfer + send_xfer = send_val & send_rdy; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:127 + // @update_ff + // def up_reg(): + // + // if s.reset: + // s.head <<= 0 + // s.tail <<= 0 + // s.count <<= 0 + // + // else: + // if s.recv_xfer: + // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 + // + // if s.send_xfer: + // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 + // + // if s.recv_xfer & ~s.send_xfer: + // s.count <<= s.count + 1 + // elif ~s.recv_xfer & s.send_xfer: + // s.count <<= s.count - 1 + + always_ff @(posedge clk) begin : up_reg + if ( reset ) begin + head <= 4'd0; + tail <= 4'd0; + count <= 5'd0; + end + else begin + if ( recv_xfer ) begin + tail <= ( tail < ( 4'( __const__num_entries_at_up_reg ) - 4'd1 ) ) ? tail + 4'd1 : 4'd0; + end + if ( send_xfer ) begin + head <= ( head < ( 4'( __const__num_entries_at_up_reg ) - 4'd1 ) ) ? head + 4'd1 : 4'd0; + end + if ( recv_xfer & ( ~send_xfer ) ) begin + count <= count + 5'd1; + end + else if ( ( ~recv_xfer ) & send_xfer ) begin + count <= count - 5'd1; + end + end + end + + assign wen = recv_xfer; + assign waddr = tail; + assign raddr = head; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__nregs_16__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__769ad531033521b3 +( + input logic [0:0] clk , + input logic [3:0] raddr [0:0], + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rdata [0:0], + input logic [0:0] reset , + input logic [3:0] waddr [0:0], + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d regs [0:15]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_16 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__a1611e9294891a09 +( + input logic [0:0] clk , + input logic [3:0] raddr , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_msg , + input logic [0:0] reset , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_msg , + input logic [3:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [3:0] rf__raddr [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [3:0] rf__waddr [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__769ad531033521b3 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_16 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__a1611e9294891a09 +( + input logic [0:0] clk , + output logic [4:0] count , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [4:0] ctrl__count; + logic [3:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [3:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_16 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [3:0] dpath__raddr; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__recv_msg; + logic [0:0] dpath__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__send_msg; + logic [3:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__a1611e9294891a09 dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component GlobalReduceUnitRTL Definition +// Full name: GlobalReduceUnitRTL__InterCgraPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d +// At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py + +module GlobalReduceUnitRTL__7c4d8effbf794a25 +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_count__msg , + output logic [0:0] recv_count__rdy , + input logic [0:0] recv_count__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_data__msg , + output logic [0:0] recv_data__rdy , + input logic [0:0] recv_data__val , + output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL = 5'd19; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 receiving_count; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reduce_add_value; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reduce_mul_value; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 sending_count; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 target_count; + //------------------------------------------------------------- + // Component queue + //------------------------------------------------------------- + + logic [0:0] queue__clk; + logic [4:0] queue__count; + logic [0:0] queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__recv__msg; + logic [0:0] queue__recv__rdy; + logic [0:0] queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__send__msg; + logic [0:0] queue__send__rdy; + logic [0:0] queue__send__val; + + NormalQueueRTL__a1611e9294891a09 queue + ( + .clk( queue__clk ), + .count( queue__count ), + .reset( queue__reset ), + .recv__msg( queue__recv__msg ), + .recv__rdy( queue__recv__rdy ), + .recv__val( queue__recv__val ), + .send__msg( queue__send__msg ), + .send__rdy( queue__send__rdy ), + .send__val( queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component queue + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:45 + // @update + // def set_recv_rdy(): + // s.recv_data.rdy @= 0 + // s.queue.recv.val @= 0 + // s.queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // if s.target_count.payload > s.receiving_count.payload: + // s.recv_data.rdy @= s.queue.recv.rdy + // s.queue.recv.msg @= s.recv_data.msg + // s.queue.recv.val @= s.recv_data.val + + always_comb begin : set_recv_rdy + recv_data__rdy = 1'd0; + queue__recv__val = 1'd0; + queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + if ( target_count.payload > receiving_count.payload ) begin + recv_data__rdy = queue__recv__rdy; + queue__recv__msg = recv_data__msg; + queue__recv__val = recv_data__val; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:74 + // @update + // def update_send(): + // s.send.msg @= ControllerXbarPktType(0, 0) + // s.send.val @= 0 + // s.queue.send.rdy @= 0 + // if (s.target_count.payload > 0) & (s.receiving_count.payload == s.target_count.payload): + // # Updates the cmd type, result value, and src/dst. + // if s.queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: + // s.send.msg.inter_cgra_pkt.payload.cmd @= CMD_GLOBAL_REDUCE_ADD_RESPONSE + // s.send.msg.inter_cgra_pkt.payload.data @= s.reduce_add_value + // elif s.queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL: + // s.send.msg.inter_cgra_pkt.payload.cmd @= CMD_GLOBAL_REDUCE_MUL_RESPONSE + // s.send.msg.inter_cgra_pkt.payload.data @= s.reduce_mul_value + // s.send.msg.inter_cgra_pkt.src @= s.queue.send.msg.dst + // s.send.msg.inter_cgra_pkt.dst @= s.queue.send.msg.src + // s.send.msg.inter_cgra_pkt.src_x @= s.queue.send.msg.dst_x + // s.send.msg.inter_cgra_pkt.src_y @= s.queue.send.msg.dst_y + // s.send.msg.inter_cgra_pkt.dst_x @= s.queue.send.msg.src_x + // s.send.msg.inter_cgra_pkt.dst_y @= s.queue.send.msg.src_y + // s.send.msg.inter_cgra_pkt.src_tile_id @= s.queue.send.msg.dst_tile_id + // s.send.msg.inter_cgra_pkt.dst_tile_id @= s.queue.send.msg.src_tile_id + // s.queue.send.rdy @= s.send.rdy + // s.send.val @= s.queue.send.val + + always_comb begin : update_send + send__msg = { 1'd0, 221'd0 }; + send__val = 1'd0; + queue__send__rdy = 1'd0; + if ( ( target_count.payload > 64'd0 ) & ( receiving_count.payload == target_count.payload ) ) begin + if ( queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin + send__msg.inter_cgra_pkt.payload.cmd = 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ); + send__msg.inter_cgra_pkt.payload.data = reduce_add_value; + end + else if ( queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL ) ) begin + send__msg.inter_cgra_pkt.payload.cmd = 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ); + send__msg.inter_cgra_pkt.payload.data = reduce_mul_value; + end + send__msg.inter_cgra_pkt.src = queue__send__msg.dst; + send__msg.inter_cgra_pkt.dst = queue__send__msg.src; + send__msg.inter_cgra_pkt.src_x = queue__send__msg.dst_x; + send__msg.inter_cgra_pkt.src_y = queue__send__msg.dst_y; + send__msg.inter_cgra_pkt.dst_x = queue__send__msg.src_x; + send__msg.inter_cgra_pkt.dst_y = queue__send__msg.src_y; + send__msg.inter_cgra_pkt.src_tile_id = queue__send__msg.dst_tile_id; + send__msg.inter_cgra_pkt.dst_tile_id = queue__send__msg.src_tile_id; + queue__send__rdy = send__rdy; + send__val = queue__send__val; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:98 + // @update_ff + // def accumulate_value(): + // if s.reset | (s.sending_count == s.target_count): + // s.reduce_add_value <<= DataType(0, 0, 0, 0) + // s.reduce_mul_value <<= DataType(1, 0, 0, 0) + // else: + // if s.recv_data.val & \ + // s.recv_data.rdy: + // if s.recv_data.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: + // s.reduce_add_value <<= DataType(s.reduce_add_value.payload + s.recv_data.msg.payload.data.payload, + // s.recv_data.msg.payload.data.predicate, + // 0, + // 0) + // elif s.recv_data.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL: + // s.reduce_mul_value <<= DataType(s.reduce_mul_value.payload * s.recv_data.msg.payload.data.payload, + // s.recv_data.msg.payload.data.predicate, + // 0, + // 0) + + always_ff @(posedge clk) begin : accumulate_value + if ( reset | ( sending_count == target_count ) ) begin + reduce_add_value <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + reduce_mul_value <= { 64'd1, 1'd0, 1'd0, 1'd0 }; + end + else if ( recv_data__val & recv_data__rdy ) begin + if ( recv_data__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin + reduce_add_value <= { reduce_add_value.payload + recv_data__msg.payload.data.payload, recv_data__msg.payload.data.predicate, 1'd0, 1'd0 }; + end + else if ( recv_data__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL ) ) begin + reduce_mul_value <= { reduce_mul_value.payload * recv_data__msg.payload.data.payload, recv_data__msg.payload.data.predicate, 1'd0, 1'd0 }; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:55 + // @update_ff + // def update_count(): + // if s.reset: + // s.target_count <<= DataType(0, 0, 0, 0) + // s.receiving_count <<= DataType(0, 0, 0, 0) + // s.sending_count <<= DataType(0, 0, 0, 0) + // else: + // if s.recv_count.val & s.recv_count.rdy: + // s.target_count <<= DataType(s.recv_count.msg.payload.data.payload, 0, 0, 0) + // if s.recv_data.val & s.recv_data.rdy: + // s.receiving_count <<= DataType(s.receiving_count.payload + 1, 0, 0, 0) + // if s.send.rdy & s.send.val: + // s.sending_count <<= DataType(s.sending_count.payload + 1, 0, 0, 0) + // elif (s.sending_count == s.receiving_count) & \ + // (s.sending_count == s.target_count) & \ + // (s.target_count.payload > 0): + // s.sending_count <<= DataType(0, 0, 0, 0) + // s.receiving_count <<= DataType(0, 0, 0, 0) + + always_ff @(posedge clk) begin : update_count + if ( reset ) begin + target_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + receiving_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + sending_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + else begin + if ( recv_count__val & recv_count__rdy ) begin + target_count <= { recv_count__msg.payload.data.payload, 1'd0, 1'd0, 1'd0 }; + end + if ( recv_data__val & recv_data__rdy ) begin + receiving_count <= { receiving_count.payload + 64'd1, 1'd0, 1'd0, 1'd0 }; + end + if ( send__rdy & send__val ) begin + sending_count <= { sending_count.payload + 64'd1, 1'd0, 1'd0, 1'd0 }; + end + else if ( ( ( sending_count == receiving_count ) & ( sending_count == target_count ) ) & ( target_count.payload > 64'd0 ) ) begin + sending_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + receiving_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + end + end + + assign queue__clk = clk; + assign queue__reset = reset; + assign recv_count__rdy = 1'd1; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__80167091524f71e4 +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__a1c7a5a18a302c36 +( + input logic [0:0] clk , + input logic [0:0] raddr , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_msg , + input logic [0:0] reset , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__80167091524f71e4 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__a1c7a5a18a302c36 +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__raddr; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__recv_msg; + logic [0:0] dpath__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__a1c7a5a18a302c36 dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__96d83eaf701da4cb +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__c7280ffb0786127e +( + input logic [0:0] clk , + input logic [0:0] raddr , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_msg , + input logic [0:0] reset , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__96d83eaf701da4cb rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__c7280ffb0786127e +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__raddr; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__recv_msg; + logic [0:0] dpath__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__c7280ffb0786127e dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component ChannelRTL Definition +// Full name: ChannelRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_NormalQueueRTL__latency_1 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py + +module ChannelRTL__551ecec02ed96ac9 +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queues[0:0] + //------------------------------------------------------------- + + logic [0:0] queues__clk [0:0]; + logic [1:0] queues__count [0:0]; + logic [0:0] queues__reset [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queues__recv__msg [0:0]; + logic [0:0] queues__recv__rdy [0:0]; + logic [0:0] queues__recv__val [0:0]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queues__send__msg [0:0]; + logic [0:0] queues__send__rdy [0:0]; + logic [0:0] queues__send__val [0:0]; + + NormalQueueRTL__c7280ffb0786127e queues__0 + ( + .clk( queues__clk[0] ), + .count( queues__count[0] ), + .reset( queues__reset[0] ), + .recv__msg( queues__recv__msg[0] ), + .recv__rdy( queues__recv__rdy[0] ), + .recv__val( queues__recv__val[0] ), + .send__msg( queues__send__msg[0] ), + .send__rdy( queues__send__rdy[0] ), + .send__val( queues__send__val[0] ) + ); + + //------------------------------------------------------------- + // End of component queues[0:0] + //------------------------------------------------------------- + + assign queues__clk[0] = clk; + assign queues__reset[0] = reset; + assign queues__recv__msg[0] = recv__msg; + assign recv__rdy = queues__recv__rdy[0]; + assign queues__recv__val[0] = recv__val; + assign send__msg = queues__send__msg[0]; + assign queues__send__rdy[0] = send__rdy; + assign send__val = queues__send__val[0]; + +endmodule + + +// PyMTL Component ControllerRTL Definition +// Full name: ControllerRTL__InterCgraPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__multi_cgra_rows_2__multi_cgra_columns_2__num_tiles_16__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)} +// At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py + +module ControllerRTL__e06602ce343fdc8d +( + input logic [1:0] cgra_id , + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , + output logic [0:0] recv_from_cpu_pkt__rdy , + input logic [0:0] recv_from_cpu_pkt__val , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_ctrl_ring_pkt__msg , + output logic [0:0] recv_from_ctrl_ring_pkt__rdy , + input logic [0:0] recv_from_ctrl_ring_pkt__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_inter_cgra_noc__msg , + output logic [0:0] recv_from_inter_cgra_noc__rdy , + input logic [0:0] recv_from_inter_cgra_noc__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt__msg , + output logic [0:0] recv_from_tile_load_request_pkt__rdy , + input logic [0:0] recv_from_tile_load_request_pkt__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt__msg , + output logic [0:0] recv_from_tile_load_response_pkt__rdy , + input logic [0:0] recv_from_tile_load_response_pkt__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt__msg , + output logic [0:0] recv_from_tile_store_request_pkt__rdy , + input logic [0:0] recv_from_tile_store_request_pkt__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , + input logic [0:0] send_to_cpu_pkt__rdy , + output logic [0:0] send_to_cpu_pkt__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_ctrl_ring_pkt__msg , + input logic [0:0] send_to_ctrl_ring_pkt__rdy , + output logic [0:0] send_to_ctrl_ring_pkt__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_inter_cgra_noc__msg , + input logic [0:0] send_to_inter_cgra_noc__rdy , + output logic [0:0] send_to_inter_cgra_noc__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request__msg , + input logic [0:0] send_to_mem_load_request__rdy , + output logic [0:0] send_to_mem_load_request__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request__msg , + input logic [0:0] send_to_mem_store_request__rdy , + output logic [0:0] send_to_mem_store_request__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response__msg , + input logic [0:0] send_to_tile_load_response__rdy , + output logic [0:0] send_to_tile_load_response__val +); + localparam logic [2:0] __const__CONTROLLER_CROSSBAR_INPORTS = 3'd6; + localparam logic [4:0] __const__num_tiles_at_update_received_msg = 5'd16; + localparam logic [3:0] __const__CMD_LOAD_REQUEST = 4'd10; + localparam logic [3:0] __const__CMD_STORE_REQUEST = 4'd12; + localparam logic [3:0] __const__CMD_LOAD_RESPONSE = 4'd11; + localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_COUNT = 5'd17; + localparam logic [1:0] __const__CMD_CONFIG = 2'd3; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; + localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; + localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; + localparam logic [3:0] __const__CMD_CONFIG_CTRL_LOWER_BOUND = 4'd9; + localparam logic [3:0] __const__CMD_CONST = 4'd13; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; + localparam logic [0:0] __const__CMD_PAUSE = 1'd1; + localparam logic [4:0] __const__CMD_PRESERVE = 5'd22; + localparam logic [3:0] __const__CMD_RESUME = 4'd15; + localparam logic [4:0] __const__CMD_RECORD_PHI_ADDR = 5'd16; + localparam logic [1:0] __const__CMD_TERMINATE = 2'd2; + localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; + localparam logic [2:0] __const__addr_offset_nbits_at_capture_addr_dst_id = 3'd5; + logic [1:0] addr2controller_lut [0:3]; + logic [1:0] addr_dst_id; + logic [0:0] idTo2d_x_lut [0:3]; + logic [0:0] idTo2d_y_lut [0:3]; + //------------------------------------------------------------- + // Component crossbar + //------------------------------------------------------------- + + logic [0:0] crossbar__clk; + logic [0:0] crossbar__reset; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad crossbar__recv__msg [0:5]; + logic [0:0] crossbar__recv__rdy [0:5]; + logic [0:0] crossbar__recv__val [0:5]; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad crossbar__send__msg [0:0]; + logic [0:0] crossbar__send__rdy [0:0]; + logic [0:0] crossbar__send__val [0:0]; + + XbarRTL__51e7846dd37f4a41 crossbar + ( + .clk( crossbar__clk ), + .reset( crossbar__reset ), + .recv__msg( crossbar__recv__msg ), + .recv__rdy( crossbar__recv__rdy ), + .recv__val( crossbar__recv__val ), + .send__msg( crossbar__send__msg ), + .send__rdy( crossbar__send__rdy ), + .send__val( crossbar__send__val ) + ); + + //------------------------------------------------------------- + // End of component crossbar + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component global_reduce_unit + //------------------------------------------------------------- + + logic [0:0] global_reduce_unit__clk; + logic [0:0] global_reduce_unit__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d global_reduce_unit__recv_count__msg; + logic [0:0] global_reduce_unit__recv_count__rdy; + logic [0:0] global_reduce_unit__recv_count__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d global_reduce_unit__recv_data__msg; + logic [0:0] global_reduce_unit__recv_data__rdy; + logic [0:0] global_reduce_unit__recv_data__val; + ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad global_reduce_unit__send__msg; + logic [0:0] global_reduce_unit__send__rdy; + logic [0:0] global_reduce_unit__send__val; + + GlobalReduceUnitRTL__7c4d8effbf794a25 global_reduce_unit + ( + .clk( global_reduce_unit__clk ), + .reset( global_reduce_unit__reset ), + .recv_count__msg( global_reduce_unit__recv_count__msg ), + .recv_count__rdy( global_reduce_unit__recv_count__rdy ), + .recv_count__val( global_reduce_unit__recv_count__val ), + .recv_data__msg( global_reduce_unit__recv_data__msg ), + .recv_data__rdy( global_reduce_unit__recv_data__rdy ), + .recv_data__val( global_reduce_unit__recv_data__val ), + .send__msg( global_reduce_unit__send__msg ), + .send__rdy( global_reduce_unit__send__rdy ), + .send__val( global_reduce_unit__send__val ) + ); + + //------------------------------------------------------------- + // End of component global_reduce_unit + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component recv_from_cpu_pkt_queue + //------------------------------------------------------------- + + logic [0:0] recv_from_cpu_pkt_queue__clk; + logic [1:0] recv_from_cpu_pkt_queue__count; + logic [0:0] recv_from_cpu_pkt_queue__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt_queue__recv__msg; + logic [0:0] recv_from_cpu_pkt_queue__recv__rdy; + logic [0:0] recv_from_cpu_pkt_queue__recv__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt_queue__send__msg; + logic [0:0] recv_from_cpu_pkt_queue__send__rdy; + logic [0:0] recv_from_cpu_pkt_queue__send__val; + + NormalQueueRTL__a1c7a5a18a302c36 recv_from_cpu_pkt_queue + ( + .clk( recv_from_cpu_pkt_queue__clk ), + .count( recv_from_cpu_pkt_queue__count ), + .reset( recv_from_cpu_pkt_queue__reset ), + .recv__msg( recv_from_cpu_pkt_queue__recv__msg ), + .recv__rdy( recv_from_cpu_pkt_queue__recv__rdy ), + .recv__val( recv_from_cpu_pkt_queue__recv__val ), + .send__msg( recv_from_cpu_pkt_queue__send__msg ), + .send__rdy( recv_from_cpu_pkt_queue__send__rdy ), + .send__val( recv_from_cpu_pkt_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_from_cpu_pkt_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component recv_from_tile_load_request_pkt_queue + //------------------------------------------------------------- + + logic [0:0] recv_from_tile_load_request_pkt_queue__clk; + logic [0:0] recv_from_tile_load_request_pkt_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt_queue__recv__msg; + logic [0:0] recv_from_tile_load_request_pkt_queue__recv__rdy; + logic [0:0] recv_from_tile_load_request_pkt_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt_queue__send__msg; + logic [0:0] recv_from_tile_load_request_pkt_queue__send__rdy; + logic [0:0] recv_from_tile_load_request_pkt_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 recv_from_tile_load_request_pkt_queue + ( + .clk( recv_from_tile_load_request_pkt_queue__clk ), + .reset( recv_from_tile_load_request_pkt_queue__reset ), + .recv__msg( recv_from_tile_load_request_pkt_queue__recv__msg ), + .recv__rdy( recv_from_tile_load_request_pkt_queue__recv__rdy ), + .recv__val( recv_from_tile_load_request_pkt_queue__recv__val ), + .send__msg( recv_from_tile_load_request_pkt_queue__send__msg ), + .send__rdy( recv_from_tile_load_request_pkt_queue__send__rdy ), + .send__val( recv_from_tile_load_request_pkt_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_from_tile_load_request_pkt_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component recv_from_tile_load_response_pkt_queue + //------------------------------------------------------------- + + logic [0:0] recv_from_tile_load_response_pkt_queue__clk; + logic [0:0] recv_from_tile_load_response_pkt_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt_queue__recv__msg; + logic [0:0] recv_from_tile_load_response_pkt_queue__recv__rdy; + logic [0:0] recv_from_tile_load_response_pkt_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt_queue__send__msg; + logic [0:0] recv_from_tile_load_response_pkt_queue__send__rdy; + logic [0:0] recv_from_tile_load_response_pkt_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 recv_from_tile_load_response_pkt_queue + ( + .clk( recv_from_tile_load_response_pkt_queue__clk ), + .reset( recv_from_tile_load_response_pkt_queue__reset ), + .recv__msg( recv_from_tile_load_response_pkt_queue__recv__msg ), + .recv__rdy( recv_from_tile_load_response_pkt_queue__recv__rdy ), + .recv__val( recv_from_tile_load_response_pkt_queue__recv__val ), + .send__msg( recv_from_tile_load_response_pkt_queue__send__msg ), + .send__rdy( recv_from_tile_load_response_pkt_queue__send__rdy ), + .send__val( recv_from_tile_load_response_pkt_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_from_tile_load_response_pkt_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component recv_from_tile_store_request_pkt_queue + //------------------------------------------------------------- + + logic [0:0] recv_from_tile_store_request_pkt_queue__clk; + logic [0:0] recv_from_tile_store_request_pkt_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt_queue__recv__msg; + logic [0:0] recv_from_tile_store_request_pkt_queue__recv__rdy; + logic [0:0] recv_from_tile_store_request_pkt_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt_queue__send__msg; + logic [0:0] recv_from_tile_store_request_pkt_queue__send__rdy; + logic [0:0] recv_from_tile_store_request_pkt_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 recv_from_tile_store_request_pkt_queue + ( + .clk( recv_from_tile_store_request_pkt_queue__clk ), + .reset( recv_from_tile_store_request_pkt_queue__reset ), + .recv__msg( recv_from_tile_store_request_pkt_queue__recv__msg ), + .recv__rdy( recv_from_tile_store_request_pkt_queue__recv__rdy ), + .recv__val( recv_from_tile_store_request_pkt_queue__recv__val ), + .send__msg( recv_from_tile_store_request_pkt_queue__send__msg ), + .send__rdy( recv_from_tile_store_request_pkt_queue__send__rdy ), + .send__val( recv_from_tile_store_request_pkt_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_from_tile_store_request_pkt_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component send_to_cpu_pkt_queue + //------------------------------------------------------------- + + logic [0:0] send_to_cpu_pkt_queue__clk; + logic [1:0] send_to_cpu_pkt_queue__count; + logic [0:0] send_to_cpu_pkt_queue__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt_queue__recv__msg; + logic [0:0] send_to_cpu_pkt_queue__recv__rdy; + logic [0:0] send_to_cpu_pkt_queue__recv__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt_queue__send__msg; + logic [0:0] send_to_cpu_pkt_queue__send__rdy; + logic [0:0] send_to_cpu_pkt_queue__send__val; + + NormalQueueRTL__a1c7a5a18a302c36 send_to_cpu_pkt_queue + ( + .clk( send_to_cpu_pkt_queue__clk ), + .count( send_to_cpu_pkt_queue__count ), + .reset( send_to_cpu_pkt_queue__reset ), + .recv__msg( send_to_cpu_pkt_queue__recv__msg ), + .recv__rdy( send_to_cpu_pkt_queue__recv__rdy ), + .recv__val( send_to_cpu_pkt_queue__recv__val ), + .send__msg( send_to_cpu_pkt_queue__send__msg ), + .send__rdy( send_to_cpu_pkt_queue__send__rdy ), + .send__val( send_to_cpu_pkt_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component send_to_cpu_pkt_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component send_to_mem_load_request_queue + //------------------------------------------------------------- + + logic [0:0] send_to_mem_load_request_queue__clk; + logic [0:0] send_to_mem_load_request_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request_queue__recv__msg; + logic [0:0] send_to_mem_load_request_queue__recv__rdy; + logic [0:0] send_to_mem_load_request_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request_queue__send__msg; + logic [0:0] send_to_mem_load_request_queue__send__rdy; + logic [0:0] send_to_mem_load_request_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 send_to_mem_load_request_queue + ( + .clk( send_to_mem_load_request_queue__clk ), + .reset( send_to_mem_load_request_queue__reset ), + .recv__msg( send_to_mem_load_request_queue__recv__msg ), + .recv__rdy( send_to_mem_load_request_queue__recv__rdy ), + .recv__val( send_to_mem_load_request_queue__recv__val ), + .send__msg( send_to_mem_load_request_queue__send__msg ), + .send__rdy( send_to_mem_load_request_queue__send__rdy ), + .send__val( send_to_mem_load_request_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component send_to_mem_load_request_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component send_to_mem_store_request_queue + //------------------------------------------------------------- + + logic [0:0] send_to_mem_store_request_queue__clk; + logic [0:0] send_to_mem_store_request_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request_queue__recv__msg; + logic [0:0] send_to_mem_store_request_queue__recv__rdy; + logic [0:0] send_to_mem_store_request_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request_queue__send__msg; + logic [0:0] send_to_mem_store_request_queue__send__rdy; + logic [0:0] send_to_mem_store_request_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 send_to_mem_store_request_queue + ( + .clk( send_to_mem_store_request_queue__clk ), + .reset( send_to_mem_store_request_queue__reset ), + .recv__msg( send_to_mem_store_request_queue__recv__msg ), + .recv__rdy( send_to_mem_store_request_queue__recv__rdy ), + .recv__val( send_to_mem_store_request_queue__recv__val ), + .send__msg( send_to_mem_store_request_queue__send__msg ), + .send__rdy( send_to_mem_store_request_queue__send__rdy ), + .send__val( send_to_mem_store_request_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component send_to_mem_store_request_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component send_to_tile_load_response_queue + //------------------------------------------------------------- + + logic [0:0] send_to_tile_load_response_queue__clk; + logic [0:0] send_to_tile_load_response_queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response_queue__recv__msg; + logic [0:0] send_to_tile_load_response_queue__recv__rdy; + logic [0:0] send_to_tile_load_response_queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response_queue__send__msg; + logic [0:0] send_to_tile_load_response_queue__send__rdy; + logic [0:0] send_to_tile_load_response_queue__send__val; + + ChannelRTL__551ecec02ed96ac9 send_to_tile_load_response_queue + ( + .clk( send_to_tile_load_response_queue__clk ), + .reset( send_to_tile_load_response_queue__reset ), + .recv__msg( send_to_tile_load_response_queue__recv__msg ), + .recv__rdy( send_to_tile_load_response_queue__recv__rdy ), + .recv__val( send_to_tile_load_response_queue__recv__val ), + .send__msg( send_to_tile_load_response_queue__send__msg ), + .send__rdy( send_to_tile_load_response_queue__send__rdy ), + .send__val( send_to_tile_load_response_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component send_to_tile_load_response_queue + //------------------------------------------------------------- + logic [0:0] __tmpvar__update_received_msg_kLoadRequestInportIdx; + logic [0:0] __tmpvar__update_received_msg_kLoadResponseInportIdx; + logic [1:0] __tmpvar__update_received_msg_kStoreRequestInportIdx; + logic [1:0] __tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx; + logic [2:0] __tmpvar__update_received_msg_kFromInterTileRingIdx; + logic [2:0] __tmpvar__update_received_msg_kFromReduceUnitIdx; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d __tmpvar__update_received_msg_received_pkt; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:362 + // @update + // def capture_addr_dst_id(): + // s.addr_dst_id @= s.addr2controller_lut[trunc(s.crossbar.send[0].msg.inter_cgra_pkt.payload.data_addr >> addr_offset_nbits, CgraIdType)] + + always_comb begin : capture_addr_dst_id + addr_dst_id = addr2controller_lut[2'(crossbar__send__msg[1'd0].inter_cgra_pkt.payload.data_addr >> 3'( __const__addr_offset_nbits_at_capture_addr_dst_id ))]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:141 + // @update + // def update_received_msg(): + // kLoadRequestInportIdx = 0 + // kLoadResponseInportIdx = 1 + // kStoreRequestInportIdx = 2 + // kFromCpuCtrlAndDataIdx = 3 + // kFromInterTileRingIdx = 4 + // kFromReduceUnitIdx = 5 + // + // s.send_to_cpu_pkt_queue.recv.val @= 0 + // s.send_to_cpu_pkt_queue.recv.msg @= IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.recv_from_ctrl_ring_pkt.rdy @= 0 + // + // for i in range(CONTROLLER_CROSSBAR_INPORTS): + // s.crossbar.recv[i].val @= 0 + // s.crossbar.recv[i].msg @= ControllerXbarPktType(0, 0) + // + // # For the command signal from inter-tile/intra-cgra control ring. + // s.crossbar.recv[kFromInterTileRingIdx].val @= s.recv_from_ctrl_ring_pkt.val + // s.recv_from_ctrl_ring_pkt.rdy @= s.crossbar.recv[kFromInterTileRingIdx].rdy + // s.crossbar.recv[kFromInterTileRingIdx].msg @= \ + // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) + // InterCgraPktType(s.cgra_id, + // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_id, + // s.idTo2d_x_lut[s.cgra_id], # src_x + // s.idTo2d_y_lut[s.cgra_id], # src_y + // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_x, # dst_x + // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_y, # dst_y + // s.recv_from_ctrl_ring_pkt.msg.src, # src_tile_id + // s.recv_from_ctrl_ring_pkt.msg.dst, # dst_tile_id + // 0, # remote_src_port, only used for inter-cgra remote load request/response. + // 0, # opaque + // 0, # vc_id. No need to specify vc_id for self produce-consume pkt thanks to the additional VC buffer. + // s.recv_from_ctrl_ring_pkt.msg.payload)) + // + // # For the load request from local tiles. + // s.crossbar.recv[kLoadRequestInportIdx].val @= s.recv_from_tile_load_request_pkt_queue.send.val + // s.recv_from_tile_load_request_pkt_queue.send.rdy @= s.crossbar.recv[kLoadRequestInportIdx].rdy + // s.crossbar.recv[kLoadRequestInportIdx].msg @= \ + // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) + // s.recv_from_tile_load_request_pkt_queue.send.msg) + // + // # For the store request from local tiles. + // s.crossbar.recv[kStoreRequestInportIdx].val @= s.recv_from_tile_store_request_pkt_queue.send.val + // s.recv_from_tile_store_request_pkt_queue.send.rdy @= s.crossbar.recv[kStoreRequestInportIdx].rdy + // s.crossbar.recv[kStoreRequestInportIdx].msg @= \ + // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) + // s.recv_from_tile_store_request_pkt_queue.send.msg) + // + // # For the load response (i.e., the data towards other) from local memory. + // s.crossbar.recv[kLoadResponseInportIdx].val @= \ + // s.recv_from_tile_load_response_pkt_queue.send.val + // s.recv_from_tile_load_response_pkt_queue.send.rdy @= s.crossbar.recv[kLoadResponseInportIdx].rdy + // s.crossbar.recv[kLoadResponseInportIdx].msg @= \ + // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) + // s.recv_from_tile_load_response_pkt_queue.send.msg) + // + // # For the load response (i.e., the data towards other) from local memory. + // s.crossbar.recv[kFromReduceUnitIdx].val @= \ + // s.global_reduce_unit.send.val + // s.global_reduce_unit.send.rdy @= s.crossbar.recv[kFromReduceUnitIdx].rdy + // s.crossbar.recv[kFromReduceUnitIdx].msg @= s.global_reduce_unit.send.msg + // + // # For the ctrl and data preloading. + // s.crossbar.recv[kFromCpuCtrlAndDataIdx].val @= \ + // s.recv_from_cpu_pkt_queue.send.val + // s.recv_from_cpu_pkt_queue.send.rdy @= s.crossbar.recv[kFromCpuCtrlAndDataIdx].rdy + // s.crossbar.recv[kFromCpuCtrlAndDataIdx].msg @= \ + // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) + // InterCgraPktType(s.cgra_id, # src + // s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id, # dst + // 0, # src_x + // 0, # src_y + // s.idTo2d_x_lut[s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id], # dst_x + // s.idTo2d_y_lut[s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id], # dst_y + // num_tiles, # src_tile_id, num_tiles is used to indicate the request is from CPU, so the LOAD response can come back. + // s.recv_from_cpu_pkt_queue.send.msg.dst, # dst_tile_id + // 0, # remote_src_port, only used for inter-cgra remote load request/response. + // 0, # opaque + // 0, # vc_id + // s.recv_from_cpu_pkt_queue.send.msg.payload)) + // + // # TODO: For the other cmd types. + // + // + // # @update + // # def update_received_msg_from_noc(): + // + // # Initiates the signals. + // s.send_to_mem_load_request_queue.recv.val @= 0 + // s.send_to_mem_store_request_queue.recv.val @= 0 + // s.send_to_tile_load_response_queue.recv.val @= 0 + // + // s.send_to_mem_load_request_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.send_to_mem_store_request_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.send_to_tile_load_response_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // + // s.recv_from_inter_cgra_noc.rdy @= 0 + // s.send_to_ctrl_ring_pkt.val @= 0 + // s.send_to_ctrl_ring_pkt.msg @= IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.global_reduce_unit.recv_count.val @= 0 + // s.global_reduce_unit.recv_count.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.global_reduce_unit.recv_data.val @= 0 + // s.global_reduce_unit.recv_data.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // + // # For the load request from NoC. + // received_pkt = s.recv_from_inter_cgra_noc.msg + // if s.recv_from_inter_cgra_noc.val: + // if s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LOAD_REQUEST: + // s.send_to_mem_load_request_queue.recv.val @= 1 + // + // if s.send_to_mem_load_request_queue.recv.rdy: + // s.recv_from_inter_cgra_noc.rdy @= 1 + // s.send_to_mem_load_request_queue.recv.msg @= received_pkt + // + // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_STORE_REQUEST: + // s.send_to_mem_store_request_queue.recv.msg @= received_pkt + // s.send_to_mem_store_request_queue.recv.val @= 1 + // + // if s.send_to_mem_store_request_queue.recv.rdy: + // s.recv_from_inter_cgra_noc.rdy @= 1 + // + // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LOAD_RESPONSE: + // # FIXME: This condition needs to check whether this controller is the + // # one connecting to CPU, and with the help from additional field indicating + // # whether the packet is originally from CPU. + // # https://github.com/tancheng/VectorCGRA/issues/116. + // if s.recv_from_inter_cgra_noc.msg.dst_tile_id == num_tiles: + // s.recv_from_inter_cgra_noc.rdy @= s.send_to_cpu_pkt_queue.recv.rdy + // s.send_to_cpu_pkt_queue.recv.val @= 1 + // s.send_to_cpu_pkt_queue.recv.msg @= \ + // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src + // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst + // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x + // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y + // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x + // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y + // 0, # opaque + // 0, # vc_id + // s.recv_from_inter_cgra_noc.msg.payload) + // + // else: + // s.recv_from_inter_cgra_noc.rdy @= s.send_to_tile_load_response_queue.recv.rdy + // s.send_to_tile_load_response_queue.recv.msg @= received_pkt + // s.send_to_tile_load_response_queue.recv.val @= 1 + // + // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_COMPLETE: + // s.recv_from_inter_cgra_noc.rdy @= s.send_to_cpu_pkt_queue.recv.rdy + // s.send_to_cpu_pkt_queue.recv.val @= 1 + // s.send_to_cpu_pkt_queue.recv.msg @= \ + // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src + // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst + // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x + // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y + // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x + // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y + // 0, # opaque + // 0, # vc_id + // s.recv_from_inter_cgra_noc.msg.payload) + // + // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: + // s.recv_from_inter_cgra_noc.rdy @= s.global_reduce_unit.recv_data.rdy + // s.global_reduce_unit.recv_data.val @= 1 + // s.global_reduce_unit.recv_data.msg @= s.recv_from_inter_cgra_noc.msg + // + // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_COUNT: + // s.recv_from_inter_cgra_noc.rdy @= s.global_reduce_unit.recv_count.rdy + // s.global_reduce_unit.recv_count.val @= 1 + // s.global_reduce_unit.recv_count.msg @= s.recv_from_inter_cgra_noc.msg + // + // elif (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONST) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_PAUSE) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_PRESERVE) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_RESUME) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_RECORD_PHI_ADDR) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_TERMINATE) | \ + // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LAUNCH): + // s.recv_from_inter_cgra_noc.rdy @= s.send_to_ctrl_ring_pkt.rdy + // s.send_to_ctrl_ring_pkt.val @= s.recv_from_inter_cgra_noc.val + // s.send_to_ctrl_ring_pkt.msg @= \ + // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src + // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst + // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id + // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x + // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y + // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x + // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y + // 0, # opaque + // 0, # vc_id + // s.recv_from_inter_cgra_noc.msg.payload) + // + // # else: + // # # TODO: Handle other cmd types. + // # assert(False) + + always_comb begin : update_received_msg + __tmpvar__update_received_msg_kLoadRequestInportIdx = 1'd0; + __tmpvar__update_received_msg_kLoadResponseInportIdx = 1'd1; + __tmpvar__update_received_msg_kStoreRequestInportIdx = 2'd2; + __tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx = 2'd3; + __tmpvar__update_received_msg_kFromInterTileRingIdx = 3'd4; + __tmpvar__update_received_msg_kFromReduceUnitIdx = 3'd5; + send_to_cpu_pkt_queue__recv__val = 1'd0; + send_to_cpu_pkt_queue__recv__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; + recv_from_ctrl_ring_pkt__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__CONTROLLER_CROSSBAR_INPORTS ); i += 1'd1 ) begin + crossbar__recv__val[3'(i)] = 1'd0; + crossbar__recv__msg[3'(i)] = { 1'd0, 221'd0 }; + end + crossbar__recv__val[__tmpvar__update_received_msg_kFromInterTileRingIdx] = recv_from_ctrl_ring_pkt__val; + recv_from_ctrl_ring_pkt__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromInterTileRingIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kFromInterTileRingIdx] = { 1'd0, { cgra_id, recv_from_ctrl_ring_pkt__msg.dst_cgra_id, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], recv_from_ctrl_ring_pkt__msg.dst_cgra_x, recv_from_ctrl_ring_pkt__msg.dst_cgra_y, recv_from_ctrl_ring_pkt__msg.src, recv_from_ctrl_ring_pkt__msg.dst, 3'd0, 8'd0, 2'd0, recv_from_ctrl_ring_pkt__msg.payload } }; + crossbar__recv__val[__tmpvar__update_received_msg_kLoadRequestInportIdx] = recv_from_tile_load_request_pkt_queue__send__val; + recv_from_tile_load_request_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kLoadRequestInportIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kLoadRequestInportIdx] = { 1'd0, recv_from_tile_load_request_pkt_queue__send__msg }; + crossbar__recv__val[__tmpvar__update_received_msg_kStoreRequestInportIdx] = recv_from_tile_store_request_pkt_queue__send__val; + recv_from_tile_store_request_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kStoreRequestInportIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kStoreRequestInportIdx] = { 1'd0, recv_from_tile_store_request_pkt_queue__send__msg }; + crossbar__recv__val[__tmpvar__update_received_msg_kLoadResponseInportIdx] = recv_from_tile_load_response_pkt_queue__send__val; + recv_from_tile_load_response_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kLoadResponseInportIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kLoadResponseInportIdx] = { 1'd0, recv_from_tile_load_response_pkt_queue__send__msg }; + crossbar__recv__val[__tmpvar__update_received_msg_kFromReduceUnitIdx] = global_reduce_unit__send__val; + global_reduce_unit__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromReduceUnitIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kFromReduceUnitIdx] = global_reduce_unit__send__msg; + crossbar__recv__val[__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx] = recv_from_cpu_pkt_queue__send__val; + recv_from_cpu_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx)]; + crossbar__recv__msg[__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx] = { 1'd0, { cgra_id, recv_from_cpu_pkt_queue__send__msg.dst_cgra_id, 1'd0, 1'd0, idTo2d_x_lut[recv_from_cpu_pkt_queue__send__msg.dst_cgra_id], idTo2d_y_lut[recv_from_cpu_pkt_queue__send__msg.dst_cgra_id], 5'( __const__num_tiles_at_update_received_msg ), recv_from_cpu_pkt_queue__send__msg.dst, 3'd0, 8'd0, 2'd0, recv_from_cpu_pkt_queue__send__msg.payload } }; + send_to_mem_load_request_queue__recv__val = 1'd0; + send_to_mem_store_request_queue__recv__val = 1'd0; + send_to_tile_load_response_queue__recv__val = 1'd0; + send_to_mem_load_request_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + send_to_mem_store_request_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + send_to_tile_load_response_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + recv_from_inter_cgra_noc__rdy = 1'd0; + send_to_ctrl_ring_pkt__val = 1'd0; + send_to_ctrl_ring_pkt__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; + global_reduce_unit__recv_count__val = 1'd0; + global_reduce_unit__recv_count__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + global_reduce_unit__recv_data__val = 1'd0; + global_reduce_unit__recv_data__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; + __tmpvar__update_received_msg_received_pkt = recv_from_inter_cgra_noc__msg; + if ( recv_from_inter_cgra_noc__val ) begin + if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LOAD_REQUEST ) ) begin + send_to_mem_load_request_queue__recv__val = 1'd1; + if ( send_to_mem_load_request_queue__recv__rdy ) begin + recv_from_inter_cgra_noc__rdy = 1'd1; + send_to_mem_load_request_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; + end + end + else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_STORE_REQUEST ) ) begin + send_to_mem_store_request_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; + send_to_mem_store_request_queue__recv__val = 1'd1; + if ( send_to_mem_store_request_queue__recv__rdy ) begin + recv_from_inter_cgra_noc__rdy = 1'd1; + end + end + else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LOAD_RESPONSE ) ) begin + if ( recv_from_inter_cgra_noc__msg.dst_tile_id == 5'( __const__num_tiles_at_update_received_msg ) ) begin + recv_from_inter_cgra_noc__rdy = send_to_cpu_pkt_queue__recv__rdy; + send_to_cpu_pkt_queue__recv__val = 1'd1; + send_to_cpu_pkt_queue__recv__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; + end + else begin + recv_from_inter_cgra_noc__rdy = send_to_tile_load_response_queue__recv__rdy; + send_to_tile_load_response_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; + send_to_tile_load_response_queue__recv__val = 1'd1; + end + end + else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_COMPLETE ) ) begin + recv_from_inter_cgra_noc__rdy = send_to_cpu_pkt_queue__recv__rdy; + send_to_cpu_pkt_queue__recv__val = 1'd1; + send_to_cpu_pkt_queue__recv__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; + end + else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin + recv_from_inter_cgra_noc__rdy = global_reduce_unit__recv_data__rdy; + global_reduce_unit__recv_data__val = 1'd1; + global_reduce_unit__recv_data__msg = recv_from_inter_cgra_noc__msg; + end + else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_COUNT ) ) begin + recv_from_inter_cgra_noc__rdy = global_reduce_unit__recv_count__rdy; + global_reduce_unit__recv_count__val = 1'd1; + global_reduce_unit__recv_count__msg = recv_from_inter_cgra_noc__msg; + end + else if ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONST ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_PAUSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_PRESERVE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_RECORD_PHI_ADDR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) begin + recv_from_inter_cgra_noc__rdy = send_to_ctrl_ring_pkt__rdy; + send_to_ctrl_ring_pkt__val = recv_from_inter_cgra_noc__val; + send_to_ctrl_ring_pkt__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:350 + // @update + // def update_sending_to_noc_msg(): + // s.send_to_inter_cgra_noc.val @= s.crossbar.send[0].val + // s.crossbar.send[0].rdy @= s.send_to_inter_cgra_noc.rdy + // s.send_to_inter_cgra_noc.msg @= s.crossbar.send[0].msg.inter_cgra_pkt + // # addr_dst_id = 0 + // if (s.crossbar.send[0].msg.inter_cgra_pkt.payload.cmd == CMD_LOAD_REQUEST) | \ + // (s.crossbar.send[0].msg.inter_cgra_pkt.payload.cmd == CMD_STORE_REQUEST): + // s.send_to_inter_cgra_noc.msg.dst @= s.addr_dst_id + // s.send_to_inter_cgra_noc.msg.dst_x @= s.idTo2d_x_lut[s.addr_dst_id] + // s.send_to_inter_cgra_noc.msg.dst_y @= s.idTo2d_y_lut[s.addr_dst_id] + + always_comb begin : update_sending_to_noc_msg + send_to_inter_cgra_noc__val = crossbar__send__val[1'd0]; + crossbar__send__rdy[1'd0] = send_to_inter_cgra_noc__rdy; + send_to_inter_cgra_noc__msg = crossbar__send__msg[1'd0].inter_cgra_pkt; + if ( ( crossbar__send__msg[1'd0].inter_cgra_pkt.payload.cmd == 5'( __const__CMD_LOAD_REQUEST ) ) | ( crossbar__send__msg[1'd0].inter_cgra_pkt.payload.cmd == 5'( __const__CMD_STORE_REQUEST ) ) ) begin + send_to_inter_cgra_noc__msg.dst = addr_dst_id; + send_to_inter_cgra_noc__msg.dst_x = idTo2d_x_lut[addr_dst_id]; + send_to_inter_cgra_noc__msg.dst_y = idTo2d_y_lut[addr_dst_id]; + end + end + + assign recv_from_tile_load_request_pkt_queue__clk = clk; + assign recv_from_tile_load_request_pkt_queue__reset = reset; + assign recv_from_tile_load_response_pkt_queue__clk = clk; + assign recv_from_tile_load_response_pkt_queue__reset = reset; + assign recv_from_tile_store_request_pkt_queue__clk = clk; + assign recv_from_tile_store_request_pkt_queue__reset = reset; + assign send_to_mem_load_request_queue__clk = clk; + assign send_to_mem_load_request_queue__reset = reset; + assign send_to_tile_load_response_queue__clk = clk; + assign send_to_tile_load_response_queue__reset = reset; + assign send_to_mem_store_request_queue__clk = clk; + assign send_to_mem_store_request_queue__reset = reset; + assign crossbar__clk = clk; + assign crossbar__reset = reset; + assign recv_from_cpu_pkt_queue__clk = clk; + assign recv_from_cpu_pkt_queue__reset = reset; + assign send_to_cpu_pkt_queue__clk = clk; + assign send_to_cpu_pkt_queue__reset = reset; + assign global_reduce_unit__clk = clk; + assign global_reduce_unit__reset = reset; + assign addr2controller_lut[0] = 2'd0; + assign addr2controller_lut[1] = 2'd1; + assign addr2controller_lut[2] = 2'd2; + assign addr2controller_lut[3] = 2'd3; + assign idTo2d_x_lut[0] = 1'd0; + assign idTo2d_y_lut[0] = 1'd0; + assign idTo2d_x_lut[1] = 1'd1; + assign idTo2d_y_lut[1] = 1'd0; + assign idTo2d_x_lut[2] = 1'd0; + assign idTo2d_y_lut[2] = 1'd1; + assign idTo2d_x_lut[3] = 1'd1; + assign idTo2d_y_lut[3] = 1'd1; + assign recv_from_tile_load_request_pkt_queue__recv__msg = recv_from_tile_load_request_pkt__msg; + assign recv_from_tile_load_request_pkt__rdy = recv_from_tile_load_request_pkt_queue__recv__rdy; + assign recv_from_tile_load_request_pkt_queue__recv__val = recv_from_tile_load_request_pkt__val; + assign recv_from_tile_load_response_pkt_queue__recv__msg = recv_from_tile_load_response_pkt__msg; + assign recv_from_tile_load_response_pkt__rdy = recv_from_tile_load_response_pkt_queue__recv__rdy; + assign recv_from_tile_load_response_pkt_queue__recv__val = recv_from_tile_load_response_pkt__val; + assign recv_from_tile_store_request_pkt_queue__recv__msg = recv_from_tile_store_request_pkt__msg; + assign recv_from_tile_store_request_pkt__rdy = recv_from_tile_store_request_pkt_queue__recv__rdy; + assign recv_from_tile_store_request_pkt_queue__recv__val = recv_from_tile_store_request_pkt__val; + assign send_to_mem_load_request__msg = send_to_mem_load_request_queue__send__msg; + assign send_to_mem_load_request_queue__send__rdy = send_to_mem_load_request__rdy; + assign send_to_mem_load_request__val = send_to_mem_load_request_queue__send__val; + assign send_to_tile_load_response__msg = send_to_tile_load_response_queue__send__msg; + assign send_to_tile_load_response_queue__send__rdy = send_to_tile_load_response__rdy; + assign send_to_tile_load_response__val = send_to_tile_load_response_queue__send__val; + assign send_to_mem_store_request__msg = send_to_mem_store_request_queue__send__msg; + assign send_to_mem_store_request_queue__send__rdy = send_to_mem_store_request__rdy; + assign send_to_mem_store_request__val = send_to_mem_store_request_queue__send__val; + assign recv_from_cpu_pkt_queue__recv__msg = recv_from_cpu_pkt__msg; + assign recv_from_cpu_pkt__rdy = recv_from_cpu_pkt_queue__recv__rdy; + assign recv_from_cpu_pkt_queue__recv__val = recv_from_cpu_pkt__val; + assign send_to_cpu_pkt__msg = send_to_cpu_pkt_queue__send__msg; + assign send_to_cpu_pkt_queue__send__rdy = send_to_cpu_pkt__rdy; + assign send_to_cpu_pkt__val = send_to_cpu_pkt_queue__send__val; + +endmodule + + +// PyMTL Component Counter Definition +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/rtl/Counter.py + +module Counter__Type_Bits2__reset_value_2 +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] decr , + input logic [0:0] incr , + input logic [0:0] load , + input logic [1:0] load_value , + input logic [0:0] reset +); + localparam logic [1:0] __const__reset_value_at_up_count = 2'd2; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/rtl/Counter.py:28 + // @update_ff + // def up_count(): + // + // if s.reset: + // s.count <<= reset_value + // + // elif s.load: + // s.count <<= s.load_value + // + // elif s.incr & ~s.decr: + // s.count <<= s.count + 1 + // + // elif ~s.incr & s.decr: + // s.count <<= s.count - 1 + + always_ff @(posedge clk) begin : up_count + if ( reset ) begin + count <= 2'( __const__reset_value_at_up_count ); + end + else if ( load ) begin + count <= load_value; + end + else if ( incr & ( ~decr ) ) begin + count <= count + 2'd1; + end + else if ( ( ~incr ) & decr ) begin + count <= count - 2'd1; + end + end + +endmodule + + +// PyMTL Component RecvRTL2CreditSendRTL Definition +// Full name: RecvRTL2CreditSendRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py + +module RecvRTL2CreditSendRTL__6d49e584a986d10c +( + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output logic [0:0] send__en , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__yum [0:1] +); + localparam logic [1:0] __const__vc_at_up_credit_send = 2'd2; + localparam logic [1:0] __const__vc_at_up_counter_decr = 2'd2; + //------------------------------------------------------------- + // Component credit[0:1] + //------------------------------------------------------------- + + logic [0:0] credit__clk [0:1]; + logic [1:0] credit__count [0:1]; + logic [0:0] credit__decr [0:1]; + logic [0:0] credit__incr [0:1]; + logic [0:0] credit__load [0:1]; + logic [1:0] credit__load_value [0:1]; + logic [0:0] credit__reset [0:1]; + + Counter__Type_Bits2__reset_value_2 credit__0 + ( + .clk( credit__clk[0] ), + .count( credit__count[0] ), + .decr( credit__decr[0] ), + .incr( credit__incr[0] ), + .load( credit__load[0] ), + .load_value( credit__load_value[0] ), + .reset( credit__reset[0] ) + ); + + Counter__Type_Bits2__reset_value_2 credit__1 + ( + .clk( credit__clk[1] ), + .count( credit__count[1] ), + .decr( credit__decr[1] ), + .incr( credit__incr[1] ), + .load( credit__load[1] ), + .load_value( credit__load_value[1] ), + .reset( credit__reset[1] ) + ); + + //------------------------------------------------------------- + // End of component credit[0:1] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:149 + // @update + // def up_counter_decr(): + // for i in range( vc ): + // s.credit[i].decr @= s.send.en & ( i == s.send.msg.vc_id ) + + always_comb begin : up_counter_decr + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_counter_decr ); i += 1'd1 ) + credit__decr[1'(i)] = send__en & ( 1'(i) == send__msg.vc_id ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:137 + // @update + // def up_credit_send(): + // s.send.en @= 0 + // s.recv.rdy @= 0 + // # NOTE: recv.rdy depends on recv.val. + // # Be careful about combinationl loop. + // if s.recv.val: + // for i in range( vc ): + // if ( i == s.recv.msg.vc_id ) & ( s.credit[i].count > 0 ): + // s.send.en @= 1 + // s.recv.rdy @= 1 + + always_comb begin : up_credit_send + send__en = 1'd0; + recv__rdy = 1'd0; + if ( recv__val ) begin + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_credit_send ); i += 1'd1 ) + if ( ( 1'(i) == recv__msg.vc_id ) & ( credit__count[1'(i)] > 2'd0 ) ) begin + send__en = 1'd1; + recv__rdy = 1'd1; + end + end + end + + assign credit__clk[0] = clk; + assign credit__reset[0] = reset; + assign credit__clk[1] = clk; + assign credit__reset[1] = reset; + assign send__msg = recv__msg; + assign credit__incr[0] = send__yum[0]; + assign credit__load[0] = 1'd0; + assign credit__load_value[0] = 2'd0; + assign credit__incr[1] = send__yum[1]; + assign credit__load[1] = 1'd0; + assign credit__load_value[1] = 2'd0; + +endmodule + + +// PyMTL Component InputUnitCreditRTL Definition +// Full name: InputUnitCreditRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__QueueType_NormalQueueRTL__vc_2__credit_line_2 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py + +module InputUnitCreditRTL__797fe657f4e9d44e +( + input logic [0:0] clk , + input logic [0:0] reset , + input logic [0:0] recv__en , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__yum [0:1] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:1] , + input logic [0:0] send__rdy [0:1] , + output logic [0:0] send__val [0:1] +); + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ = 1'd0; + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ = 1'd1; + localparam logic [1:0] __const__vc_at_up_enq = 2'd2; + //------------------------------------------------------------- + // Component buffers[0:1] + //------------------------------------------------------------- + + logic [0:0] buffers__clk [0:1]; + logic [1:0] buffers__count [0:1]; + logic [0:0] buffers__reset [0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__recv__msg [0:1]; + logic [0:0] buffers__recv__rdy [0:1]; + logic [0:0] buffers__recv__val [0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__send__msg [0:1]; + logic [0:0] buffers__send__rdy [0:1]; + logic [0:0] buffers__send__val [0:1]; + + NormalQueueRTL__a1c7a5a18a302c36 buffers__0 + ( + .clk( buffers__clk[0] ), + .count( buffers__count[0] ), + .reset( buffers__reset[0] ), + .recv__msg( buffers__recv__msg[0] ), + .recv__rdy( buffers__recv__rdy[0] ), + .recv__val( buffers__recv__val[0] ), + .send__msg( buffers__send__msg[0] ), + .send__rdy( buffers__send__rdy[0] ), + .send__val( buffers__send__val[0] ) + ); + + NormalQueueRTL__a1c7a5a18a302c36 buffers__1 + ( + .clk( buffers__clk[1] ), + .count( buffers__count[1] ), + .reset( buffers__reset[1] ), + .recv__msg( buffers__recv__msg[1] ), + .recv__rdy( buffers__recv__rdy[1] ), + .recv__val( buffers__recv__val[1] ), + .send__msg( buffers__send__msg[1] ), + .send__rdy( buffers__send__rdy[1] ), + .send__val( buffers__send__val[1] ) + ); + + //------------------------------------------------------------- + // End of component buffers[0:1] + //------------------------------------------------------------- + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:39 + // s.recv.yum[i] //= lambda: s.send[i].val & s.send[i].rdy + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ + recv__yum[1'd0] = send__val[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ )] & send__rdy[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ )]; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:39 + // s.recv.yum[i] //= lambda: s.send[i].val & s.send[i].rdy + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ + recv__yum[1'd1] = send__val[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ )] & send__rdy[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ )]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:41 + // @update + // def up_enq(): + // if s.recv.en: + // for i in range( vc ): + // s.buffers[i].recv.val @= ( s.recv.msg.vc_id == i ) + // else: + // for i in range( vc ): + // s.buffers[i].recv.val @= 0 + + always_comb begin : up_enq + if ( recv__en ) begin + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) + buffers__recv__val[1'(i)] = recv__msg.vc_id == 1'(i); + end + else + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) + buffers__recv__val[1'(i)] = 1'd0; + end + + assign buffers__clk[0] = clk; + assign buffers__reset[0] = reset; + assign buffers__clk[1] = clk; + assign buffers__reset[1] = reset; + assign buffers__recv__msg[0] = recv__msg; + assign send__msg[0] = buffers__send__msg[0]; + assign buffers__send__rdy[0] = send__rdy[0]; + assign send__val[0] = buffers__send__val[0]; + assign buffers__recv__msg[1] = recv__msg; + assign send__msg[1] = buffers__send__msg[1]; + assign buffers__send__rdy[1] = send__rdy[1]; + assign send__val[1] = buffers__send__val[1]; + +endmodule + + +// PyMTL Component OutputUnitCreditRTL Definition +// Full name: OutputUnitCreditRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py + +module OutputUnitCreditRTL__6d49e584a986d10c +( + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output logic [0:0] send__en , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__yum [0:1] +); + localparam logic [1:0] __const__vc_at_up_credit_send = 2'd2; + localparam logic [1:0] __const__vc_at_up_counter_decr = 2'd2; + //------------------------------------------------------------- + // Component credit[0:1] + //------------------------------------------------------------- + + logic [0:0] credit__clk [0:1]; + logic [1:0] credit__count [0:1]; + logic [0:0] credit__decr [0:1]; + logic [0:0] credit__incr [0:1]; + logic [0:0] credit__load [0:1]; + logic [1:0] credit__load_value [0:1]; + logic [0:0] credit__reset [0:1]; + + Counter__Type_Bits2__reset_value_2 credit__0 + ( + .clk( credit__clk[0] ), + .count( credit__count[0] ), + .decr( credit__decr[0] ), + .incr( credit__incr[0] ), + .load( credit__load[0] ), + .load_value( credit__load_value[0] ), + .reset( credit__reset[0] ) + ); + + Counter__Type_Bits2__reset_value_2 credit__1 + ( + .clk( credit__clk[1] ), + .count( credit__count[1] ), + .decr( credit__decr[1] ), + .incr( credit__incr[1] ), + .load( credit__load[1] ), + .load_value( credit__load_value[1] ), + .reset( credit__reset[1] ) + ); + + //------------------------------------------------------------- + // End of component credit[0:1] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py:47 + // @update + // def up_counter_decr(): + // for i in range( vc ): + // s.credit[i].decr @= s.send.en & ( i == s.send.msg.vc_id ) + + always_comb begin : up_counter_decr + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_counter_decr ); i += 1'd1 ) + credit__decr[1'(i)] = send__en & ( 1'(i) == send__msg.vc_id ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py:35 + // @update + // def up_credit_send(): + // s.send.en @= 0 + // s.recv.rdy @= 0 + // # NOTE: Here the recv.rdy depends on recv.val. + // # Be careful about combinational loop. + // if s.recv.val: + // for i in range( vc ): + // if (i == s.recv.msg.vc_id) & (s.credit[i].count > 0): + // s.send.en @= 1 + // s.recv.rdy @= 1 + + always_comb begin : up_credit_send + send__en = 1'd0; + recv__rdy = 1'd0; + if ( recv__val ) begin + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_credit_send ); i += 1'd1 ) + if ( ( 1'(i) == recv__msg.vc_id ) & ( credit__count[1'(i)] > 2'd0 ) ) begin + send__en = 1'd1; + recv__rdy = 1'd1; + end + end + end + + assign credit__clk[0] = clk; + assign credit__reset[0] = reset; + assign credit__clk[1] = clk; + assign credit__reset[1] = reset; + assign send__msg = recv__msg; + assign credit__incr[0] = send__yum[0]; + assign credit__load[0] = 1'd0; + assign credit__load_value[0] = 2'd0; + assign credit__incr[1] = send__yum[1]; + assign credit__load[1] = 1'd0; + assign credit__load_value[1] = 2'd0; + +endmodule + + +// PyMTL Component RingRouteUnitRTL Definition +// Full name: RingRouteUnitRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py + +module RingRouteUnitRTL__6d1cae73cf31e9a0 +( + input logic [0:0] clk , + input logic [4:0] pos , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:2] , + input logic [0:0] send__rdy [0:2] , + output logic [0:0] send__val [0:2] +); + localparam logic [1:0] __const__SELF = 2'd2; + localparam logic [0:0] __const__LEFT = 1'd0; + localparam logic [0:0] __const__RIGHT = 1'd1; + logic [4:0] left_dist; + logic [1:0] out_dir; + logic [4:0] right_dist; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg_wire; + logic [2:0] send_rdy; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:51 + // @update + // def up_left_right_dist(): + // if s.recv.msg.dst < s.pos: + // s.left_dist @= zext(s.pos, DistType) - zext(s.recv.msg.dst, DistType) + // s.right_dist @= zext(s.last_idx, DistType) - zext(s.pos, DistType) + zext(s.recv.msg.dst, DistType) + 1 + // else: + // s.left_dist @= 1 + zext(s.last_idx, DistType) + zext(s.pos, DistType) - zext(s.recv.msg.dst, DistType) + // s.right_dist @= zext(s.recv.msg.dst, DistType) - zext(s.pos, DistType) + + always_comb begin : up_left_right_dist + if ( recv__msg.dst < pos ) begin + left_dist = pos - recv__msg.dst; + right_dist = ( ( 5'd16 - pos ) + recv__msg.dst ) + 5'd1; + end + else begin + left_dist = ( ( 5'd1 + 5'd16 ) + pos ) - recv__msg.dst; + right_dist = recv__msg.dst - pos; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:85 + // @update + // def up_ru_recv_rdy(): + // s.recv.rdy @= s.send_rdy[ s.out_dir ] + + always_comb begin : up_ru_recv_rdy + recv__rdy = send_rdy[out_dir]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:60 + // @update + // def up_ru_routing(): + // + // s.out_dir @= 0 + // s.send_msg_wire @= s.recv.msg + // for i in range( s.num_outports ): + // s.send[i].val @= 0 + // s.send[i].msg @= s.recv.msg + // + // if s.recv.val: + // if s.pos == s.recv.msg.dst: + // s.out_dir @= SELF + // elif s.left_dist < s.right_dist: + // s.out_dir @= LEFT + // else: + // s.out_dir @= RIGHT + // + // if ( s.pos == s.last_idx ) & ( s.out_dir == RIGHT ): + // s.send_msg_wire.vc_id @= 1 + // elif ( s.pos == 0 ) & ( s.out_dir == LEFT ): + // s.send_msg_wire.vc_id @= 1 + // + // s.send[ s.out_dir ].val @= 1 + // s.send[ s.out_dir ].msg @= s.send_msg_wire + + always_comb begin : up_ru_routing + out_dir = 2'd0; + send_msg_wire = recv__msg; + for ( int unsigned i = 1'd0; i < 2'd3; i += 1'd1 ) begin + send__val[2'(i)] = 1'd0; + send__msg[2'(i)] = recv__msg; + end + if ( recv__val ) begin + if ( pos == recv__msg.dst ) begin + out_dir = 2'( __const__SELF ); + end + else if ( left_dist < right_dist ) begin + out_dir = 2'( __const__LEFT ); + end + else + out_dir = 2'( __const__RIGHT ); + if ( ( pos == 5'd16 ) & ( out_dir == 2'( __const__RIGHT ) ) ) begin + send_msg_wire.vc_id = 1'd1; + end + else if ( ( pos == 5'd0 ) & ( out_dir == 2'( __const__LEFT ) ) ) begin + send_msg_wire.vc_id = 1'd1; + end + send__val[out_dir] = 1'd1; + send__msg[out_dir] = send_msg_wire; + end + end + + assign send_rdy[0:0] = send__rdy[0]; + assign send_rdy[1:1] = send__rdy[1]; + assign send_rdy[2:2] = send__rdy[2]; + +endmodule + + +// PyMTL Component Mux Definition +// Full name: Mux__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ninputs_6 +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__1cc75bdfd067f505 +( + input logic [0:0] clk , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 in_ [0:5], + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 out , + input logic [0:0] reset , + input logic [2:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component SwitchUnitRTL Definition +// Full name: SwitchUnitRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_inports_6 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py + +module SwitchUnitRTL__ae7d6e1a8f952f91 +( + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:5] , + output logic [0:0] recv__rdy [0:5] , + input logic [0:0] recv__val [0:5] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd6; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [5:0] arbiter__grants; + logic [5:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_6 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [5:0] encoder__in_; + logic [2:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_6__out_nbits_3 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__in_ [0:5]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__out; + logic [0:0] mux__reset; + logic [2:0] mux__sel; + + Mux__1cc75bdfd067f505 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 + // @update + // def up_get_en(): + // for i in range( num_inports ): + // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) + + always_comb begin : up_get_en + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) + recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 + // @update + // def up_send_val(): + // s.send.val @= s.arbiter.grants > 0 + + always_comb begin : up_send_val + send__val = arbiter__grants > 6'd0; + end + + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign arbiter__en = 1'd1; + assign mux__clk = clk; + assign mux__reset = reset; + assign send__msg = mux__out; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign encoder__in_ = arbiter__grants; + assign mux__sel = encoder__out; + assign arbiter__reqs[0:0] = recv__val[0]; + assign mux__in_[0] = recv__msg[0]; + assign arbiter__reqs[1:1] = recv__val[1]; + assign mux__in_[1] = recv__msg[1]; + assign arbiter__reqs[2:2] = recv__val[2]; + assign mux__in_[2] = recv__msg[2]; + assign arbiter__reqs[3:3] = recv__val[3]; + assign mux__in_[3] = recv__msg[3]; + assign arbiter__reqs[4:4] = recv__val[4]; + assign mux__in_[4] = recv__msg[4]; + assign arbiter__reqs[5:5] = recv__val[5]; + assign mux__in_[5] = recv__msg[5]; + +endmodule + + +// PyMTL Component RingRouterRTL Definition +// Full name: RingRouterRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17__InputUnitType_InputUnitCreditRTL__RouteUnitType_RingRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitCreditRTL__vc_2__credit_line_2 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouterRTL.py + +module RingRouterRTL__6e670e447e1766e0 +( + input logic [0:0] clk , + input logic [4:0] pos , + input logic [0:0] reset , + input logic [0:0] recv__en [0:2] , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:2] , + output logic [0:0] recv__yum [0:2][0:1] , + output logic [0:0] send__en [0:2] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:2] , + input logic [0:0] send__yum [0:2][0:1] +); + //------------------------------------------------------------- + // Component input_units[0:2] + //------------------------------------------------------------- + + logic [0:0] input_units__clk [0:2]; + logic [0:0] input_units__reset [0:2]; + logic [0:0] input_units__recv__en [0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 input_units__recv__msg [0:2]; + logic [0:0] input_units__recv__yum [0:2][0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 input_units__send__msg [0:2][0:1]; + logic [0:0] input_units__send__rdy [0:2][0:1]; + logic [0:0] input_units__send__val [0:2][0:1]; + + InputUnitCreditRTL__797fe657f4e9d44e input_units__0 + ( + .clk( input_units__clk[0] ), + .reset( input_units__reset[0] ), + .recv__en( input_units__recv__en[0] ), + .recv__msg( input_units__recv__msg[0] ), + .recv__yum( input_units__recv__yum[0] ), + .send__msg( input_units__send__msg[0] ), + .send__rdy( input_units__send__rdy[0] ), + .send__val( input_units__send__val[0] ) + ); + + InputUnitCreditRTL__797fe657f4e9d44e input_units__1 + ( + .clk( input_units__clk[1] ), + .reset( input_units__reset[1] ), + .recv__en( input_units__recv__en[1] ), + .recv__msg( input_units__recv__msg[1] ), + .recv__yum( input_units__recv__yum[1] ), + .send__msg( input_units__send__msg[1] ), + .send__rdy( input_units__send__rdy[1] ), + .send__val( input_units__send__val[1] ) + ); + + InputUnitCreditRTL__797fe657f4e9d44e input_units__2 + ( + .clk( input_units__clk[2] ), + .reset( input_units__reset[2] ), + .recv__en( input_units__recv__en[2] ), + .recv__msg( input_units__recv__msg[2] ), + .recv__yum( input_units__recv__yum[2] ), + .send__msg( input_units__send__msg[2] ), + .send__rdy( input_units__send__rdy[2] ), + .send__val( input_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component input_units[0:2] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component output_units[0:2] + //------------------------------------------------------------- + + logic [0:0] output_units__clk [0:2]; + logic [0:0] output_units__reset [0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 output_units__recv__msg [0:2]; + logic [0:0] output_units__recv__rdy [0:2]; + logic [0:0] output_units__recv__val [0:2]; + logic [0:0] output_units__send__en [0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 output_units__send__msg [0:2]; + logic [0:0] output_units__send__yum [0:2][0:1]; + + OutputUnitCreditRTL__6d49e584a986d10c output_units__0 + ( + .clk( output_units__clk[0] ), + .reset( output_units__reset[0] ), + .recv__msg( output_units__recv__msg[0] ), + .recv__rdy( output_units__recv__rdy[0] ), + .recv__val( output_units__recv__val[0] ), + .send__en( output_units__send__en[0] ), + .send__msg( output_units__send__msg[0] ), + .send__yum( output_units__send__yum[0] ) + ); + + OutputUnitCreditRTL__6d49e584a986d10c output_units__1 + ( + .clk( output_units__clk[1] ), + .reset( output_units__reset[1] ), + .recv__msg( output_units__recv__msg[1] ), + .recv__rdy( output_units__recv__rdy[1] ), + .recv__val( output_units__recv__val[1] ), + .send__en( output_units__send__en[1] ), + .send__msg( output_units__send__msg[1] ), + .send__yum( output_units__send__yum[1] ) + ); + + OutputUnitCreditRTL__6d49e584a986d10c output_units__2 + ( + .clk( output_units__clk[2] ), + .reset( output_units__reset[2] ), + .recv__msg( output_units__recv__msg[2] ), + .recv__rdy( output_units__recv__rdy[2] ), + .recv__val( output_units__recv__val[2] ), + .send__en( output_units__send__en[2] ), + .send__msg( output_units__send__msg[2] ), + .send__yum( output_units__send__yum[2] ) + ); + + //------------------------------------------------------------- + // End of component output_units[0:2] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component route_units[0:5] + //------------------------------------------------------------- + + logic [0:0] route_units__clk [0:5]; + logic [4:0] route_units__pos [0:5]; + logic [0:0] route_units__reset [0:5]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 route_units__recv__msg [0:5]; + logic [0:0] route_units__recv__rdy [0:5]; + logic [0:0] route_units__recv__val [0:5]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 route_units__send__msg [0:5][0:2]; + logic [0:0] route_units__send__rdy [0:5][0:2]; + logic [0:0] route_units__send__val [0:5][0:2]; + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__0 + ( + .clk( route_units__clk[0] ), + .pos( route_units__pos[0] ), + .reset( route_units__reset[0] ), + .recv__msg( route_units__recv__msg[0] ), + .recv__rdy( route_units__recv__rdy[0] ), + .recv__val( route_units__recv__val[0] ), + .send__msg( route_units__send__msg[0] ), + .send__rdy( route_units__send__rdy[0] ), + .send__val( route_units__send__val[0] ) + ); + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__1 + ( + .clk( route_units__clk[1] ), + .pos( route_units__pos[1] ), + .reset( route_units__reset[1] ), + .recv__msg( route_units__recv__msg[1] ), + .recv__rdy( route_units__recv__rdy[1] ), + .recv__val( route_units__recv__val[1] ), + .send__msg( route_units__send__msg[1] ), + .send__rdy( route_units__send__rdy[1] ), + .send__val( route_units__send__val[1] ) + ); + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__2 + ( + .clk( route_units__clk[2] ), + .pos( route_units__pos[2] ), + .reset( route_units__reset[2] ), + .recv__msg( route_units__recv__msg[2] ), + .recv__rdy( route_units__recv__rdy[2] ), + .recv__val( route_units__recv__val[2] ), + .send__msg( route_units__send__msg[2] ), + .send__rdy( route_units__send__rdy[2] ), + .send__val( route_units__send__val[2] ) + ); + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__3 + ( + .clk( route_units__clk[3] ), + .pos( route_units__pos[3] ), + .reset( route_units__reset[3] ), + .recv__msg( route_units__recv__msg[3] ), + .recv__rdy( route_units__recv__rdy[3] ), + .recv__val( route_units__recv__val[3] ), + .send__msg( route_units__send__msg[3] ), + .send__rdy( route_units__send__rdy[3] ), + .send__val( route_units__send__val[3] ) + ); + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__4 + ( + .clk( route_units__clk[4] ), + .pos( route_units__pos[4] ), + .reset( route_units__reset[4] ), + .recv__msg( route_units__recv__msg[4] ), + .recv__rdy( route_units__recv__rdy[4] ), + .recv__val( route_units__recv__val[4] ), + .send__msg( route_units__send__msg[4] ), + .send__rdy( route_units__send__rdy[4] ), + .send__val( route_units__send__val[4] ) + ); + + RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__5 + ( + .clk( route_units__clk[5] ), + .pos( route_units__pos[5] ), + .reset( route_units__reset[5] ), + .recv__msg( route_units__recv__msg[5] ), + .recv__rdy( route_units__recv__rdy[5] ), + .recv__val( route_units__recv__val[5] ), + .send__msg( route_units__send__msg[5] ), + .send__rdy( route_units__send__rdy[5] ), + .send__val( route_units__send__val[5] ) + ); + + //------------------------------------------------------------- + // End of component route_units[0:5] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component switch_units[0:2] + //------------------------------------------------------------- + + logic [0:0] switch_units__clk [0:2]; + logic [0:0] switch_units__reset [0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 switch_units__recv__msg [0:2][0:5]; + logic [0:0] switch_units__recv__rdy [0:2][0:5]; + logic [0:0] switch_units__recv__val [0:2][0:5]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 switch_units__send__msg [0:2]; + logic [0:0] switch_units__send__rdy [0:2]; + logic [0:0] switch_units__send__val [0:2]; + + SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__0 + ( + .clk( switch_units__clk[0] ), + .reset( switch_units__reset[0] ), + .recv__msg( switch_units__recv__msg[0] ), + .recv__rdy( switch_units__recv__rdy[0] ), + .recv__val( switch_units__recv__val[0] ), + .send__msg( switch_units__send__msg[0] ), + .send__rdy( switch_units__send__rdy[0] ), + .send__val( switch_units__send__val[0] ) + ); + + SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__1 + ( + .clk( switch_units__clk[1] ), + .reset( switch_units__reset[1] ), + .recv__msg( switch_units__recv__msg[1] ), + .recv__rdy( switch_units__recv__rdy[1] ), + .recv__val( switch_units__recv__val[1] ), + .send__msg( switch_units__send__msg[1] ), + .send__rdy( switch_units__send__rdy[1] ), + .send__val( switch_units__send__val[1] ) + ); + + SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__2 + ( + .clk( switch_units__clk[2] ), + .reset( switch_units__reset[2] ), + .recv__msg( switch_units__recv__msg[2] ), + .recv__rdy( switch_units__recv__rdy[2] ), + .recv__val( switch_units__recv__val[2] ), + .send__msg( switch_units__send__msg[2] ), + .send__rdy( switch_units__send__rdy[2] ), + .send__val( switch_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component switch_units[0:2] + //------------------------------------------------------------- + + assign input_units__clk[0] = clk; + assign input_units__reset[0] = reset; + assign input_units__clk[1] = clk; + assign input_units__reset[1] = reset; + assign input_units__clk[2] = clk; + assign input_units__reset[2] = reset; + assign route_units__clk[0] = clk; + assign route_units__reset[0] = reset; + assign route_units__clk[1] = clk; + assign route_units__reset[1] = reset; + assign route_units__clk[2] = clk; + assign route_units__reset[2] = reset; + assign route_units__clk[3] = clk; + assign route_units__reset[3] = reset; + assign route_units__clk[4] = clk; + assign route_units__reset[4] = reset; + assign route_units__clk[5] = clk; + assign route_units__reset[5] = reset; + assign switch_units__clk[0] = clk; + assign switch_units__reset[0] = reset; + assign switch_units__clk[1] = clk; + assign switch_units__reset[1] = reset; + assign switch_units__clk[2] = clk; + assign switch_units__reset[2] = reset; + assign output_units__clk[0] = clk; + assign output_units__reset[0] = reset; + assign output_units__clk[1] = clk; + assign output_units__reset[1] = reset; + assign output_units__clk[2] = clk; + assign output_units__reset[2] = reset; + assign input_units__recv__en[0] = recv__en[0]; + assign input_units__recv__msg[0] = recv__msg[0]; + assign recv__yum[0][0] = input_units__recv__yum[0][0]; + assign recv__yum[0][1] = input_units__recv__yum[0][1]; + assign route_units__recv__msg[0] = input_units__send__msg[0][0]; + assign input_units__send__rdy[0][0] = route_units__recv__rdy[0]; + assign route_units__recv__val[0] = input_units__send__val[0][0]; + assign route_units__pos[0] = pos; + assign route_units__recv__msg[1] = input_units__send__msg[0][1]; + assign input_units__send__rdy[0][1] = route_units__recv__rdy[1]; + assign route_units__recv__val[1] = input_units__send__val[0][1]; + assign route_units__pos[1] = pos; + assign input_units__recv__en[1] = recv__en[1]; + assign input_units__recv__msg[1] = recv__msg[1]; + assign recv__yum[1][0] = input_units__recv__yum[1][0]; + assign recv__yum[1][1] = input_units__recv__yum[1][1]; + assign route_units__recv__msg[2] = input_units__send__msg[1][0]; + assign input_units__send__rdy[1][0] = route_units__recv__rdy[2]; + assign route_units__recv__val[2] = input_units__send__val[1][0]; + assign route_units__pos[2] = pos; + assign route_units__recv__msg[3] = input_units__send__msg[1][1]; + assign input_units__send__rdy[1][1] = route_units__recv__rdy[3]; + assign route_units__recv__val[3] = input_units__send__val[1][1]; + assign route_units__pos[3] = pos; + assign input_units__recv__en[2] = recv__en[2]; + assign input_units__recv__msg[2] = recv__msg[2]; + assign recv__yum[2][0] = input_units__recv__yum[2][0]; + assign recv__yum[2][1] = input_units__recv__yum[2][1]; + assign route_units__recv__msg[4] = input_units__send__msg[2][0]; + assign input_units__send__rdy[2][0] = route_units__recv__rdy[4]; + assign route_units__recv__val[4] = input_units__send__val[2][0]; + assign route_units__pos[4] = pos; + assign route_units__recv__msg[5] = input_units__send__msg[2][1]; + assign input_units__send__rdy[2][1] = route_units__recv__rdy[5]; + assign route_units__recv__val[5] = input_units__send__val[2][1]; + assign route_units__pos[5] = pos; + assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; + assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; + assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; + assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; + assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; + assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; + assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; + assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; + assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; + assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; + assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; + assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; + assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; + assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; + assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; + assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; + assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; + assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; + assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; + assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; + assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; + assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; + assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; + assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; + assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; + assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; + assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; + assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; + assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; + assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; + assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; + assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; + assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; + assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; + assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; + assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; + assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; + assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; + assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; + assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; + assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; + assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; + assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; + assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; + assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; + assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; + assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; + assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; + assign switch_units__recv__msg[1][5] = route_units__send__msg[5][1]; + assign route_units__send__rdy[5][1] = switch_units__recv__rdy[1][5]; + assign switch_units__recv__val[1][5] = route_units__send__val[5][1]; + assign switch_units__recv__msg[2][5] = route_units__send__msg[5][2]; + assign route_units__send__rdy[5][2] = switch_units__recv__rdy[2][5]; + assign switch_units__recv__val[2][5] = route_units__send__val[5][2]; + assign output_units__recv__msg[0] = switch_units__send__msg[0]; + assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; + assign output_units__recv__val[0] = switch_units__send__val[0]; + assign send__en[0] = output_units__send__en[0]; + assign send__msg[0] = output_units__send__msg[0]; + assign output_units__send__yum[0][0] = send__yum[0][0]; + assign output_units__send__yum[0][1] = send__yum[0][1]; + assign output_units__recv__msg[1] = switch_units__send__msg[1]; + assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; + assign output_units__recv__val[1] = switch_units__send__val[1]; + assign send__en[1] = output_units__send__en[1]; + assign send__msg[1] = output_units__send__msg[1]; + assign output_units__send__yum[1][0] = send__yum[1][0]; + assign output_units__send__yum[1][1] = send__yum[1][1]; + assign output_units__recv__msg[2] = switch_units__send__msg[2]; + assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; + assign output_units__recv__val[2] = switch_units__send__val[2]; + assign send__en[2] = output_units__send__en[2]; + assign send__msg[2] = output_units__send__msg[2]; + assign output_units__send__yum[2][0] = send__yum[2][0]; + assign output_units__send__yum[2][1] = send__yum[2][1]; + +endmodule + + +// PyMTL Component RegEnRst Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py + +module RegEnRst__Type_Bits2__reset_value_1 +( + input logic [0:0] clk , + input logic [0:0] en , + input logic [1:0] in_ , + output logic [1:0] out , + input logic [0:0] reset +); + localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 + // @update_ff + // def up_regenrst(): + // if s.reset: s.out <<= reset_value + // elif s.en: s.out <<= s.in_ + + always_ff @(posedge clk) begin : up_regenrst + if ( reset ) begin + out <= 2'( __const__reset_value_at_up_regenrst ); + end + else if ( en ) begin + out <= in_; + end + end + +endmodule + + +// PyMTL Component RoundRobinArbiterEn Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py + +module RoundRobinArbiterEn__nreqs_2 +( + input logic [0:0] clk , + input logic [0:0] en , + output logic [1:0] grants , + input logic [1:0] reqs , + input logic [0:0] reset +); + localparam logic [1:0] __const__nreqs_at_comb_reqs_int = 2'd2; + localparam logic [2:0] __const__nreqsX2_at_comb_reqs_int = 3'd4; + localparam logic [1:0] __const__nreqs_at_comb_grants = 2'd2; + localparam logic [1:0] __const__nreqs_at_comb_priority_int = 2'd2; + localparam logic [2:0] __const__nreqsX2_at_comb_priority_int = 3'd4; + localparam logic [2:0] __const__nreqsX2_at_comb_kills = 3'd4; + localparam logic [2:0] __const__nreqsX2_at_comb_grants_int = 3'd4; + logic [3:0] grants_int; + logic [4:0] kills; + logic [0:0] priority_en; + logic [3:0] priority_int; + logic [3:0] reqs_int; + //------------------------------------------------------------- + // Component priority_reg + //------------------------------------------------------------- + + logic [0:0] priority_reg__clk; + logic [0:0] priority_reg__en; + logic [1:0] priority_reg__in_; + logic [1:0] priority_reg__out; + logic [0:0] priority_reg__reset; + + RegEnRst__Type_Bits2__reset_value_1 priority_reg + ( + .clk( priority_reg__clk ), + .en( priority_reg__en ), + .in_( priority_reg__in_ ), + .out( priority_reg__out ), + .reset( priority_reg__reset ) + ); + + //------------------------------------------------------------- + // End of component priority_reg + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 + // @update + // def comb_grants(): + // for i in range( nreqs ): + // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] + + always_comb begin : comb_grants + for ( int unsigned i = 1'd0; i < 2'( __const__nreqs_at_comb_grants ); i += 1'd1 ) + grants[1'(i)] = grants_int[2'(i)] | grants_int[2'( __const__nreqs_at_comb_grants ) + 2'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 + // @update + // def comb_grants_int(): + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.grants_int[i] @= s.reqs_int[i] + // else: + // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] + + always_comb begin : comb_grants_int + for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) + if ( priority_int[2'(i)] ) begin + grants_int[2'(i)] = reqs_int[2'(i)]; + end + else + grants_int[2'(i)] = ( ~kills[3'(i)] ) & reqs_int[2'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 + // @update + // def comb_kills(): + // s.kills[0] @= 1 + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.kills[i+1] @= s.reqs_int[i] + // else: + // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) + + always_comb begin : comb_kills + kills[3'd0] = 1'd1; + for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) + if ( priority_int[2'(i)] ) begin + kills[3'(i) + 3'd1] = reqs_int[2'(i)]; + end + else + kills[3'(i) + 3'd1] = kills[3'(i)] | ( ( ~kills[3'(i)] ) & reqs_int[2'(i)] ); + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 + // @update + // def comb_priority_en(): + // s.priority_en @= ( s.grants != 0 ) & s.en + + always_comb begin : comb_priority_en + priority_en = ( grants != 2'd0 ) & en; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 + // @update + // def comb_priority_int(): + // s.priority_int[ 0:nreqs ] @= s.priority_reg.out + // s.priority_int[nreqs:nreqsX2] @= 0 + + always_comb begin : comb_priority_int + priority_int[2'd1:2'd0] = priority_reg__out; + priority_int[2'd3:2'( __const__nreqs_at_comb_priority_int )] = 2'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 + // @update + // def comb_reqs_int(): + // s.reqs_int [ 0:nreqs ] @= s.reqs + // s.reqs_int [nreqs:nreqsX2] @= s.reqs + + always_comb begin : comb_reqs_int + reqs_int[2'd1:2'd0] = reqs; + reqs_int[2'd3:2'( __const__nreqs_at_comb_reqs_int )] = reqs; + end + + assign priority_reg__clk = clk; + assign priority_reg__reset = reset; + assign priority_reg__en = priority_en; + assign priority_reg__in_[1:1] = grants[0:0]; + assign priority_reg__in_[0:0] = grants[1:1]; + +endmodule + + +// PyMTL Component BypassQueueCtrlRTL Definition +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueCtrlRTL__num_entries_2 +( + input logic [0:0] clk , + output logic [1:0] count , + output logic [0:0] mux_sel , + output logic [0:0] raddr , + output logic [0:0] recv_rdy , + input logic [0:0] recv_val , + input logic [0:0] reset , + input logic [0:0] send_rdy , + output logic [0:0] send_val , + output logic [0:0] waddr , + output logic [0:0] wen +); + localparam logic [1:0] __const__num_entries_at__lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy = 2'd2; + localparam logic [1:0] __const__num_entries_at_up_reg = 2'd2; + logic [0:0] head; + logic [0:0] recv_xfer; + logic [0:0] send_xfer; + logic [0:0] tail; + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:645 + // s.mux_sel //= lambda: s.count == 0 + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_mux_sel + mux_sel = count == 2'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:642 + // s.recv_rdy //= lambda: s.count < num_entries + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy + recv_rdy = count < 2'( __const__num_entries_at__lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy ); + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:647 + // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_xfer + recv_xfer = recv_val & recv_rdy; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:643 + // s.send_val //= lambda: (s.count > 0) | s.recv_val + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_send_val + send_val = ( count > 2'd0 ) | recv_val; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:648 + // s.send_xfer //= lambda: s.send_val & s.send_rdy + + always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_send_xfer + send_xfer = send_val & send_rdy; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:650 + // @update_ff + // def up_reg(): + // + // if s.reset: + // s.head <<= 0 + // s.tail <<= 0 + // s.count <<= 0 + // + // else: + // if s.recv_xfer: + // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 + // + // if s.send_xfer: + // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 + // + // if s.recv_xfer & ~s.send_xfer: + // s.count <<= s.count + 1 + // if ~s.recv_xfer & s.send_xfer: + // s.count <<= s.count - 1 + + always_ff @(posedge clk) begin : up_reg + if ( reset ) begin + head <= 1'd0; + tail <= 1'd0; + count <= 2'd0; + end + else begin + if ( recv_xfer ) begin + tail <= ( tail < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? tail + 1'd1 : 1'd0; + end + if ( send_xfer ) begin + head <= ( head < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? head + 1'd1 : 1'd0; + end + if ( recv_xfer & ( ~send_xfer ) ) begin + count <= count + 2'd1; + end + if ( ( ~recv_xfer ) & send_xfer ) begin + count <= count - 2'd1; + end + end + end + + assign wen = recv_xfer; + assign waddr = tail; + assign raddr = head; + +endmodule + + +// PyMTL Component Mux Definition +// Full name: Mux__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ninputs_2 +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__4754a371c6cda085 +( + input logic [0:0] clk , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 in_ [0:1], + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 out , + input logic [0:0] reset , + input logic [0:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component BypassQueueDpathRTL Definition +// Full name: BypassQueueDpathRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueDpathRTL__a1c7a5a18a302c36 +( + input logic [0:0] clk , + input logic [0:0] mux_sel , + input logic [0:0] raddr , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_msg , + input logic [0:0] reset , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__in_ [0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__out; + logic [0:0] mux__reset; + logic [0:0] mux__sel; + + Mux__4754a371c6cda085 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__80167091524f71e4 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + assign mux__clk = clk; + assign mux__reset = reset; + assign mux__sel = mux_sel; + assign mux__in_[0] = rf__rdata[0]; + assign mux__in_[1] = recv_msg; + assign send_msg = mux__out; + +endmodule + + +// PyMTL Component BypassQueueRTL Definition +// Full name: BypassQueueRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueRTL__a1c7a5a18a302c36 +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__mux_sel; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + BypassQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .mux_sel( ctrl__mux_sel ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__mux_sel; + logic [0:0] dpath__raddr; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__recv_msg; + logic [0:0] dpath__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + BypassQueueDpathRTL__a1c7a5a18a302c36 dpath + ( + .clk( dpath__clk ), + .mux_sel( dpath__mux_sel ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign dpath__mux_sel = ctrl__mux_sel; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign count = ctrl__count; + assign dpath__recv_msg = recv__msg; + assign send__msg = dpath__send_msg; + +endmodule + + +// PyMTL Component Encoder Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py + +module Encoder__in_nbits_2__out_nbits_1 +( + input logic [0:0] clk , + input logic [1:0] in_ , + output logic [0:0] out , + input logic [0:0] reset +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 + // @update + // def encode(): + // s.out @= 0 + // for i in range( s.in_nbits ): + // if s.in_[i]: + // s.out @= i + + always_comb begin : encode + out = 1'd0; + for ( int unsigned i = 1'd0; i < 2'd2; i += 1'd1 ) + if ( in_[1'(i)] ) begin + out = 1'(i); + end + end + +endmodule + + +// PyMTL Component CreditRecvRTL2SendRTL Definition +// Full name: CreditRecvRTL2SendRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2__QType_BypassQueueRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py + +module CreditRecvRTL2SendRTL__0d4276a185d5c616 +( + input logic [0:0] clk , + input logic [0:0] reset , + input logic [0:0] recv__en , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , + output logic [0:0] recv__yum [0:1] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [1:0] __const__vc_at_up_enq = 2'd2; + localparam logic [1:0] __const__vc_at_up_deq_and_send = 2'd2; + localparam logic [1:0] __const__vc_at_up_yummy = 2'd2; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [1:0] arbiter__grants; + logic [1:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_2 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component buffers[0:1] + //------------------------------------------------------------- + + logic [0:0] buffers__clk [0:1]; + logic [1:0] buffers__count [0:1]; + logic [0:0] buffers__reset [0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__recv__msg [0:1]; + logic [0:0] buffers__recv__rdy [0:1]; + logic [0:0] buffers__recv__val [0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__send__msg [0:1]; + logic [0:0] buffers__send__rdy [0:1]; + logic [0:0] buffers__send__val [0:1]; + + BypassQueueRTL__a1c7a5a18a302c36 buffers__0 + ( + .clk( buffers__clk[0] ), + .count( buffers__count[0] ), + .reset( buffers__reset[0] ), + .recv__msg( buffers__recv__msg[0] ), + .recv__rdy( buffers__recv__rdy[0] ), + .recv__val( buffers__recv__val[0] ), + .send__msg( buffers__send__msg[0] ), + .send__rdy( buffers__send__rdy[0] ), + .send__val( buffers__send__val[0] ) + ); + + BypassQueueRTL__a1c7a5a18a302c36 buffers__1 + ( + .clk( buffers__clk[1] ), + .count( buffers__count[1] ), + .reset( buffers__reset[1] ), + .recv__msg( buffers__recv__msg[1] ), + .recv__rdy( buffers__recv__rdy[1] ), + .recv__val( buffers__recv__val[1] ), + .send__msg( buffers__send__msg[1] ), + .send__rdy( buffers__send__rdy[1] ), + .send__val( buffers__send__val[1] ) + ); + + //------------------------------------------------------------- + // End of component buffers[0:1] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [1:0] encoder__in_; + logic [0:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_2__out_nbits_1 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:205 + // @update + // def up_deq_and_send(): + // for i in range( vc ): + // s.buffers[i].send.rdy @= 0 + // + // s.send.msg @= s.buffers[ s.encoder.out ].send.msg + // + // if s.arbiter.grants > 0: + // s.send.val @= 1 + // s.buffers[ s.encoder.out ].send.rdy @= s.send.rdy + // else: + // s.send.val @= 0 + + always_comb begin : up_deq_and_send + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_deq_and_send ); i += 1'd1 ) + buffers__send__rdy[1'(i)] = 1'd0; + send__msg = buffers__send__msg[encoder__out]; + if ( arbiter__grants > 2'd0 ) begin + send__val = 1'd1; + buffers__send__rdy[encoder__out] = send__rdy; + end + else + send__val = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:194 + // @update + // def up_enq(): + // if s.recv.en: + // for i in range( vc ): + // s.buffers[i].recv.val @= ( s.recv.msg.vc_id == i ) + // else: + // for i in range( vc ): + // s.buffers[i].recv.val @= 0 + + always_comb begin : up_enq + if ( recv__en ) begin + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) + buffers__recv__val[1'(i)] = recv__msg.vc_id == 1'(i); + end + else + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) + buffers__recv__val[1'(i)] = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:218 + // @update + // def up_yummy(): + // for i in range( vc ): + // s.recv.yum[i] @= s.buffers[i].send.val & s.buffers[i].send.rdy + + always_comb begin : up_yummy + for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_yummy ); i += 1'd1 ) + recv__yum[1'(i)] = buffers__send__val[1'(i)] & buffers__send__rdy[1'(i)]; + end + + assign buffers__clk[0] = clk; + assign buffers__reset[0] = reset; + assign buffers__clk[1] = clk; + assign buffers__reset[1] = reset; + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign buffers__recv__msg[0] = recv__msg; + assign arbiter__reqs[0:0] = buffers__send__val[0]; + assign buffers__recv__msg[1] = recv__msg; + assign arbiter__reqs[1:1] = buffers__send__val[1]; + assign encoder__in_ = arbiter__grants; + assign arbiter__en = send__val; + +endmodule + + +// PyMTL Component RingNetworkRTL Definition +// Full name: RingNetworkRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17__chl_lat_1__vc_2__credit_line_2 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingNetworkRTL.py + +module RingNetworkRTL__8866f4e00dbc912a +( + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:16] , + output logic [0:0] recv__rdy [0:16] , + input logic [0:0] recv__val [0:16] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:16] , + input logic [0:0] send__rdy [0:16] , + output logic [0:0] send__val [0:16] +); + //------------------------------------------------------------- + // Component recv_adp[0:16] + //------------------------------------------------------------- + + logic [0:0] recv_adp__clk [0:16]; + logic [0:0] recv_adp__reset [0:16]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_adp__recv__msg [0:16]; + logic [0:0] recv_adp__recv__rdy [0:16]; + logic [0:0] recv_adp__recv__val [0:16]; + logic [0:0] recv_adp__send__en [0:16]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_adp__send__msg [0:16]; + logic [0:0] recv_adp__send__yum [0:16][0:1]; + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__0 + ( + .clk( recv_adp__clk[0] ), + .reset( recv_adp__reset[0] ), + .recv__msg( recv_adp__recv__msg[0] ), + .recv__rdy( recv_adp__recv__rdy[0] ), + .recv__val( recv_adp__recv__val[0] ), + .send__en( recv_adp__send__en[0] ), + .send__msg( recv_adp__send__msg[0] ), + .send__yum( recv_adp__send__yum[0] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__1 + ( + .clk( recv_adp__clk[1] ), + .reset( recv_adp__reset[1] ), + .recv__msg( recv_adp__recv__msg[1] ), + .recv__rdy( recv_adp__recv__rdy[1] ), + .recv__val( recv_adp__recv__val[1] ), + .send__en( recv_adp__send__en[1] ), + .send__msg( recv_adp__send__msg[1] ), + .send__yum( recv_adp__send__yum[1] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__2 + ( + .clk( recv_adp__clk[2] ), + .reset( recv_adp__reset[2] ), + .recv__msg( recv_adp__recv__msg[2] ), + .recv__rdy( recv_adp__recv__rdy[2] ), + .recv__val( recv_adp__recv__val[2] ), + .send__en( recv_adp__send__en[2] ), + .send__msg( recv_adp__send__msg[2] ), + .send__yum( recv_adp__send__yum[2] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__3 + ( + .clk( recv_adp__clk[3] ), + .reset( recv_adp__reset[3] ), + .recv__msg( recv_adp__recv__msg[3] ), + .recv__rdy( recv_adp__recv__rdy[3] ), + .recv__val( recv_adp__recv__val[3] ), + .send__en( recv_adp__send__en[3] ), + .send__msg( recv_adp__send__msg[3] ), + .send__yum( recv_adp__send__yum[3] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__4 + ( + .clk( recv_adp__clk[4] ), + .reset( recv_adp__reset[4] ), + .recv__msg( recv_adp__recv__msg[4] ), + .recv__rdy( recv_adp__recv__rdy[4] ), + .recv__val( recv_adp__recv__val[4] ), + .send__en( recv_adp__send__en[4] ), + .send__msg( recv_adp__send__msg[4] ), + .send__yum( recv_adp__send__yum[4] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__5 + ( + .clk( recv_adp__clk[5] ), + .reset( recv_adp__reset[5] ), + .recv__msg( recv_adp__recv__msg[5] ), + .recv__rdy( recv_adp__recv__rdy[5] ), + .recv__val( recv_adp__recv__val[5] ), + .send__en( recv_adp__send__en[5] ), + .send__msg( recv_adp__send__msg[5] ), + .send__yum( recv_adp__send__yum[5] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__6 + ( + .clk( recv_adp__clk[6] ), + .reset( recv_adp__reset[6] ), + .recv__msg( recv_adp__recv__msg[6] ), + .recv__rdy( recv_adp__recv__rdy[6] ), + .recv__val( recv_adp__recv__val[6] ), + .send__en( recv_adp__send__en[6] ), + .send__msg( recv_adp__send__msg[6] ), + .send__yum( recv_adp__send__yum[6] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__7 + ( + .clk( recv_adp__clk[7] ), + .reset( recv_adp__reset[7] ), + .recv__msg( recv_adp__recv__msg[7] ), + .recv__rdy( recv_adp__recv__rdy[7] ), + .recv__val( recv_adp__recv__val[7] ), + .send__en( recv_adp__send__en[7] ), + .send__msg( recv_adp__send__msg[7] ), + .send__yum( recv_adp__send__yum[7] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__8 + ( + .clk( recv_adp__clk[8] ), + .reset( recv_adp__reset[8] ), + .recv__msg( recv_adp__recv__msg[8] ), + .recv__rdy( recv_adp__recv__rdy[8] ), + .recv__val( recv_adp__recv__val[8] ), + .send__en( recv_adp__send__en[8] ), + .send__msg( recv_adp__send__msg[8] ), + .send__yum( recv_adp__send__yum[8] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__9 + ( + .clk( recv_adp__clk[9] ), + .reset( recv_adp__reset[9] ), + .recv__msg( recv_adp__recv__msg[9] ), + .recv__rdy( recv_adp__recv__rdy[9] ), + .recv__val( recv_adp__recv__val[9] ), + .send__en( recv_adp__send__en[9] ), + .send__msg( recv_adp__send__msg[9] ), + .send__yum( recv_adp__send__yum[9] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__10 + ( + .clk( recv_adp__clk[10] ), + .reset( recv_adp__reset[10] ), + .recv__msg( recv_adp__recv__msg[10] ), + .recv__rdy( recv_adp__recv__rdy[10] ), + .recv__val( recv_adp__recv__val[10] ), + .send__en( recv_adp__send__en[10] ), + .send__msg( recv_adp__send__msg[10] ), + .send__yum( recv_adp__send__yum[10] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__11 + ( + .clk( recv_adp__clk[11] ), + .reset( recv_adp__reset[11] ), + .recv__msg( recv_adp__recv__msg[11] ), + .recv__rdy( recv_adp__recv__rdy[11] ), + .recv__val( recv_adp__recv__val[11] ), + .send__en( recv_adp__send__en[11] ), + .send__msg( recv_adp__send__msg[11] ), + .send__yum( recv_adp__send__yum[11] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__12 + ( + .clk( recv_adp__clk[12] ), + .reset( recv_adp__reset[12] ), + .recv__msg( recv_adp__recv__msg[12] ), + .recv__rdy( recv_adp__recv__rdy[12] ), + .recv__val( recv_adp__recv__val[12] ), + .send__en( recv_adp__send__en[12] ), + .send__msg( recv_adp__send__msg[12] ), + .send__yum( recv_adp__send__yum[12] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__13 + ( + .clk( recv_adp__clk[13] ), + .reset( recv_adp__reset[13] ), + .recv__msg( recv_adp__recv__msg[13] ), + .recv__rdy( recv_adp__recv__rdy[13] ), + .recv__val( recv_adp__recv__val[13] ), + .send__en( recv_adp__send__en[13] ), + .send__msg( recv_adp__send__msg[13] ), + .send__yum( recv_adp__send__yum[13] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__14 + ( + .clk( recv_adp__clk[14] ), + .reset( recv_adp__reset[14] ), + .recv__msg( recv_adp__recv__msg[14] ), + .recv__rdy( recv_adp__recv__rdy[14] ), + .recv__val( recv_adp__recv__val[14] ), + .send__en( recv_adp__send__en[14] ), + .send__msg( recv_adp__send__msg[14] ), + .send__yum( recv_adp__send__yum[14] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__15 + ( + .clk( recv_adp__clk[15] ), + .reset( recv_adp__reset[15] ), + .recv__msg( recv_adp__recv__msg[15] ), + .recv__rdy( recv_adp__recv__rdy[15] ), + .recv__val( recv_adp__recv__val[15] ), + .send__en( recv_adp__send__en[15] ), + .send__msg( recv_adp__send__msg[15] ), + .send__yum( recv_adp__send__yum[15] ) + ); + + RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__16 + ( + .clk( recv_adp__clk[16] ), + .reset( recv_adp__reset[16] ), + .recv__msg( recv_adp__recv__msg[16] ), + .recv__rdy( recv_adp__recv__rdy[16] ), + .recv__val( recv_adp__recv__val[16] ), + .send__en( recv_adp__send__en[16] ), + .send__msg( recv_adp__send__msg[16] ), + .send__yum( recv_adp__send__yum[16] ) + ); + + //------------------------------------------------------------- + // End of component recv_adp[0:16] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component routers[0:16] + //------------------------------------------------------------- + + logic [0:0] routers__clk [0:16]; + logic [4:0] routers__pos [0:16]; + logic [0:0] routers__reset [0:16]; + logic [0:0] routers__recv__en [0:16][0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 routers__recv__msg [0:16][0:2]; + logic [0:0] routers__recv__yum [0:16][0:2][0:1]; + logic [0:0] routers__send__en [0:16][0:2]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 routers__send__msg [0:16][0:2]; + logic [0:0] routers__send__yum [0:16][0:2][0:1]; + + RingRouterRTL__6e670e447e1766e0 routers__0 + ( + .clk( routers__clk[0] ), + .pos( routers__pos[0] ), + .reset( routers__reset[0] ), + .recv__en( routers__recv__en[0] ), + .recv__msg( routers__recv__msg[0] ), + .recv__yum( routers__recv__yum[0] ), + .send__en( routers__send__en[0] ), + .send__msg( routers__send__msg[0] ), + .send__yum( routers__send__yum[0] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__1 + ( + .clk( routers__clk[1] ), + .pos( routers__pos[1] ), + .reset( routers__reset[1] ), + .recv__en( routers__recv__en[1] ), + .recv__msg( routers__recv__msg[1] ), + .recv__yum( routers__recv__yum[1] ), + .send__en( routers__send__en[1] ), + .send__msg( routers__send__msg[1] ), + .send__yum( routers__send__yum[1] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__2 + ( + .clk( routers__clk[2] ), + .pos( routers__pos[2] ), + .reset( routers__reset[2] ), + .recv__en( routers__recv__en[2] ), + .recv__msg( routers__recv__msg[2] ), + .recv__yum( routers__recv__yum[2] ), + .send__en( routers__send__en[2] ), + .send__msg( routers__send__msg[2] ), + .send__yum( routers__send__yum[2] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__3 + ( + .clk( routers__clk[3] ), + .pos( routers__pos[3] ), + .reset( routers__reset[3] ), + .recv__en( routers__recv__en[3] ), + .recv__msg( routers__recv__msg[3] ), + .recv__yum( routers__recv__yum[3] ), + .send__en( routers__send__en[3] ), + .send__msg( routers__send__msg[3] ), + .send__yum( routers__send__yum[3] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__4 + ( + .clk( routers__clk[4] ), + .pos( routers__pos[4] ), + .reset( routers__reset[4] ), + .recv__en( routers__recv__en[4] ), + .recv__msg( routers__recv__msg[4] ), + .recv__yum( routers__recv__yum[4] ), + .send__en( routers__send__en[4] ), + .send__msg( routers__send__msg[4] ), + .send__yum( routers__send__yum[4] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__5 + ( + .clk( routers__clk[5] ), + .pos( routers__pos[5] ), + .reset( routers__reset[5] ), + .recv__en( routers__recv__en[5] ), + .recv__msg( routers__recv__msg[5] ), + .recv__yum( routers__recv__yum[5] ), + .send__en( routers__send__en[5] ), + .send__msg( routers__send__msg[5] ), + .send__yum( routers__send__yum[5] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__6 + ( + .clk( routers__clk[6] ), + .pos( routers__pos[6] ), + .reset( routers__reset[6] ), + .recv__en( routers__recv__en[6] ), + .recv__msg( routers__recv__msg[6] ), + .recv__yum( routers__recv__yum[6] ), + .send__en( routers__send__en[6] ), + .send__msg( routers__send__msg[6] ), + .send__yum( routers__send__yum[6] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__7 + ( + .clk( routers__clk[7] ), + .pos( routers__pos[7] ), + .reset( routers__reset[7] ), + .recv__en( routers__recv__en[7] ), + .recv__msg( routers__recv__msg[7] ), + .recv__yum( routers__recv__yum[7] ), + .send__en( routers__send__en[7] ), + .send__msg( routers__send__msg[7] ), + .send__yum( routers__send__yum[7] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__8 + ( + .clk( routers__clk[8] ), + .pos( routers__pos[8] ), + .reset( routers__reset[8] ), + .recv__en( routers__recv__en[8] ), + .recv__msg( routers__recv__msg[8] ), + .recv__yum( routers__recv__yum[8] ), + .send__en( routers__send__en[8] ), + .send__msg( routers__send__msg[8] ), + .send__yum( routers__send__yum[8] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__9 + ( + .clk( routers__clk[9] ), + .pos( routers__pos[9] ), + .reset( routers__reset[9] ), + .recv__en( routers__recv__en[9] ), + .recv__msg( routers__recv__msg[9] ), + .recv__yum( routers__recv__yum[9] ), + .send__en( routers__send__en[9] ), + .send__msg( routers__send__msg[9] ), + .send__yum( routers__send__yum[9] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__10 + ( + .clk( routers__clk[10] ), + .pos( routers__pos[10] ), + .reset( routers__reset[10] ), + .recv__en( routers__recv__en[10] ), + .recv__msg( routers__recv__msg[10] ), + .recv__yum( routers__recv__yum[10] ), + .send__en( routers__send__en[10] ), + .send__msg( routers__send__msg[10] ), + .send__yum( routers__send__yum[10] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__11 + ( + .clk( routers__clk[11] ), + .pos( routers__pos[11] ), + .reset( routers__reset[11] ), + .recv__en( routers__recv__en[11] ), + .recv__msg( routers__recv__msg[11] ), + .recv__yum( routers__recv__yum[11] ), + .send__en( routers__send__en[11] ), + .send__msg( routers__send__msg[11] ), + .send__yum( routers__send__yum[11] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__12 + ( + .clk( routers__clk[12] ), + .pos( routers__pos[12] ), + .reset( routers__reset[12] ), + .recv__en( routers__recv__en[12] ), + .recv__msg( routers__recv__msg[12] ), + .recv__yum( routers__recv__yum[12] ), + .send__en( routers__send__en[12] ), + .send__msg( routers__send__msg[12] ), + .send__yum( routers__send__yum[12] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__13 + ( + .clk( routers__clk[13] ), + .pos( routers__pos[13] ), + .reset( routers__reset[13] ), + .recv__en( routers__recv__en[13] ), + .recv__msg( routers__recv__msg[13] ), + .recv__yum( routers__recv__yum[13] ), + .send__en( routers__send__en[13] ), + .send__msg( routers__send__msg[13] ), + .send__yum( routers__send__yum[13] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__14 + ( + .clk( routers__clk[14] ), + .pos( routers__pos[14] ), + .reset( routers__reset[14] ), + .recv__en( routers__recv__en[14] ), + .recv__msg( routers__recv__msg[14] ), + .recv__yum( routers__recv__yum[14] ), + .send__en( routers__send__en[14] ), + .send__msg( routers__send__msg[14] ), + .send__yum( routers__send__yum[14] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__15 + ( + .clk( routers__clk[15] ), + .pos( routers__pos[15] ), + .reset( routers__reset[15] ), + .recv__en( routers__recv__en[15] ), + .recv__msg( routers__recv__msg[15] ), + .recv__yum( routers__recv__yum[15] ), + .send__en( routers__send__en[15] ), + .send__msg( routers__send__msg[15] ), + .send__yum( routers__send__yum[15] ) + ); + + RingRouterRTL__6e670e447e1766e0 routers__16 + ( + .clk( routers__clk[16] ), + .pos( routers__pos[16] ), + .reset( routers__reset[16] ), + .recv__en( routers__recv__en[16] ), + .recv__msg( routers__recv__msg[16] ), + .recv__yum( routers__recv__yum[16] ), + .send__en( routers__send__en[16] ), + .send__msg( routers__send__msg[16] ), + .send__yum( routers__send__yum[16] ) + ); + + //------------------------------------------------------------- + // End of component routers[0:16] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component send_adp[0:16] + //------------------------------------------------------------- + + logic [0:0] send_adp__clk [0:16]; + logic [0:0] send_adp__reset [0:16]; + logic [0:0] send_adp__recv__en [0:16]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_adp__recv__msg [0:16]; + logic [0:0] send_adp__recv__yum [0:16][0:1]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_adp__send__msg [0:16]; + logic [0:0] send_adp__send__rdy [0:16]; + logic [0:0] send_adp__send__val [0:16]; + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__0 + ( + .clk( send_adp__clk[0] ), + .reset( send_adp__reset[0] ), + .recv__en( send_adp__recv__en[0] ), + .recv__msg( send_adp__recv__msg[0] ), + .recv__yum( send_adp__recv__yum[0] ), + .send__msg( send_adp__send__msg[0] ), + .send__rdy( send_adp__send__rdy[0] ), + .send__val( send_adp__send__val[0] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__1 + ( + .clk( send_adp__clk[1] ), + .reset( send_adp__reset[1] ), + .recv__en( send_adp__recv__en[1] ), + .recv__msg( send_adp__recv__msg[1] ), + .recv__yum( send_adp__recv__yum[1] ), + .send__msg( send_adp__send__msg[1] ), + .send__rdy( send_adp__send__rdy[1] ), + .send__val( send_adp__send__val[1] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__2 + ( + .clk( send_adp__clk[2] ), + .reset( send_adp__reset[2] ), + .recv__en( send_adp__recv__en[2] ), + .recv__msg( send_adp__recv__msg[2] ), + .recv__yum( send_adp__recv__yum[2] ), + .send__msg( send_adp__send__msg[2] ), + .send__rdy( send_adp__send__rdy[2] ), + .send__val( send_adp__send__val[2] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__3 + ( + .clk( send_adp__clk[3] ), + .reset( send_adp__reset[3] ), + .recv__en( send_adp__recv__en[3] ), + .recv__msg( send_adp__recv__msg[3] ), + .recv__yum( send_adp__recv__yum[3] ), + .send__msg( send_adp__send__msg[3] ), + .send__rdy( send_adp__send__rdy[3] ), + .send__val( send_adp__send__val[3] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__4 + ( + .clk( send_adp__clk[4] ), + .reset( send_adp__reset[4] ), + .recv__en( send_adp__recv__en[4] ), + .recv__msg( send_adp__recv__msg[4] ), + .recv__yum( send_adp__recv__yum[4] ), + .send__msg( send_adp__send__msg[4] ), + .send__rdy( send_adp__send__rdy[4] ), + .send__val( send_adp__send__val[4] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__5 + ( + .clk( send_adp__clk[5] ), + .reset( send_adp__reset[5] ), + .recv__en( send_adp__recv__en[5] ), + .recv__msg( send_adp__recv__msg[5] ), + .recv__yum( send_adp__recv__yum[5] ), + .send__msg( send_adp__send__msg[5] ), + .send__rdy( send_adp__send__rdy[5] ), + .send__val( send_adp__send__val[5] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__6 + ( + .clk( send_adp__clk[6] ), + .reset( send_adp__reset[6] ), + .recv__en( send_adp__recv__en[6] ), + .recv__msg( send_adp__recv__msg[6] ), + .recv__yum( send_adp__recv__yum[6] ), + .send__msg( send_adp__send__msg[6] ), + .send__rdy( send_adp__send__rdy[6] ), + .send__val( send_adp__send__val[6] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__7 + ( + .clk( send_adp__clk[7] ), + .reset( send_adp__reset[7] ), + .recv__en( send_adp__recv__en[7] ), + .recv__msg( send_adp__recv__msg[7] ), + .recv__yum( send_adp__recv__yum[7] ), + .send__msg( send_adp__send__msg[7] ), + .send__rdy( send_adp__send__rdy[7] ), + .send__val( send_adp__send__val[7] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__8 + ( + .clk( send_adp__clk[8] ), + .reset( send_adp__reset[8] ), + .recv__en( send_adp__recv__en[8] ), + .recv__msg( send_adp__recv__msg[8] ), + .recv__yum( send_adp__recv__yum[8] ), + .send__msg( send_adp__send__msg[8] ), + .send__rdy( send_adp__send__rdy[8] ), + .send__val( send_adp__send__val[8] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__9 + ( + .clk( send_adp__clk[9] ), + .reset( send_adp__reset[9] ), + .recv__en( send_adp__recv__en[9] ), + .recv__msg( send_adp__recv__msg[9] ), + .recv__yum( send_adp__recv__yum[9] ), + .send__msg( send_adp__send__msg[9] ), + .send__rdy( send_adp__send__rdy[9] ), + .send__val( send_adp__send__val[9] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__10 + ( + .clk( send_adp__clk[10] ), + .reset( send_adp__reset[10] ), + .recv__en( send_adp__recv__en[10] ), + .recv__msg( send_adp__recv__msg[10] ), + .recv__yum( send_adp__recv__yum[10] ), + .send__msg( send_adp__send__msg[10] ), + .send__rdy( send_adp__send__rdy[10] ), + .send__val( send_adp__send__val[10] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__11 + ( + .clk( send_adp__clk[11] ), + .reset( send_adp__reset[11] ), + .recv__en( send_adp__recv__en[11] ), + .recv__msg( send_adp__recv__msg[11] ), + .recv__yum( send_adp__recv__yum[11] ), + .send__msg( send_adp__send__msg[11] ), + .send__rdy( send_adp__send__rdy[11] ), + .send__val( send_adp__send__val[11] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__12 + ( + .clk( send_adp__clk[12] ), + .reset( send_adp__reset[12] ), + .recv__en( send_adp__recv__en[12] ), + .recv__msg( send_adp__recv__msg[12] ), + .recv__yum( send_adp__recv__yum[12] ), + .send__msg( send_adp__send__msg[12] ), + .send__rdy( send_adp__send__rdy[12] ), + .send__val( send_adp__send__val[12] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__13 + ( + .clk( send_adp__clk[13] ), + .reset( send_adp__reset[13] ), + .recv__en( send_adp__recv__en[13] ), + .recv__msg( send_adp__recv__msg[13] ), + .recv__yum( send_adp__recv__yum[13] ), + .send__msg( send_adp__send__msg[13] ), + .send__rdy( send_adp__send__rdy[13] ), + .send__val( send_adp__send__val[13] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__14 + ( + .clk( send_adp__clk[14] ), + .reset( send_adp__reset[14] ), + .recv__en( send_adp__recv__en[14] ), + .recv__msg( send_adp__recv__msg[14] ), + .recv__yum( send_adp__recv__yum[14] ), + .send__msg( send_adp__send__msg[14] ), + .send__rdy( send_adp__send__rdy[14] ), + .send__val( send_adp__send__val[14] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__15 + ( + .clk( send_adp__clk[15] ), + .reset( send_adp__reset[15] ), + .recv__en( send_adp__recv__en[15] ), + .recv__msg( send_adp__recv__msg[15] ), + .recv__yum( send_adp__recv__yum[15] ), + .send__msg( send_adp__send__msg[15] ), + .send__rdy( send_adp__send__rdy[15] ), + .send__val( send_adp__send__val[15] ) + ); + + CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__16 + ( + .clk( send_adp__clk[16] ), + .reset( send_adp__reset[16] ), + .recv__en( send_adp__recv__en[16] ), + .recv__msg( send_adp__recv__msg[16] ), + .recv__yum( send_adp__recv__yum[16] ), + .send__msg( send_adp__send__msg[16] ), + .send__rdy( send_adp__send__rdy[16] ), + .send__val( send_adp__send__val[16] ) + ); + + //------------------------------------------------------------- + // End of component send_adp[0:16] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingNetworkRTL.py:58 + // @update + // def up_pos(): + // for r in range( s.num_routers ): + // s.routers[r].pos @= r + + always_comb begin : up_pos + for ( int unsigned r = 1'd0; r < 5'd17; r += 1'd1 ) + routers__pos[5'(r)] = 5'(r); + end + + assign routers__clk[0] = clk; + assign routers__reset[0] = reset; + assign routers__clk[1] = clk; + assign routers__reset[1] = reset; + assign routers__clk[2] = clk; + assign routers__reset[2] = reset; + assign routers__clk[3] = clk; + assign routers__reset[3] = reset; + assign routers__clk[4] = clk; + assign routers__reset[4] = reset; + assign routers__clk[5] = clk; + assign routers__reset[5] = reset; + assign routers__clk[6] = clk; + assign routers__reset[6] = reset; + assign routers__clk[7] = clk; + assign routers__reset[7] = reset; + assign routers__clk[8] = clk; + assign routers__reset[8] = reset; + assign routers__clk[9] = clk; + assign routers__reset[9] = reset; + assign routers__clk[10] = clk; + assign routers__reset[10] = reset; + assign routers__clk[11] = clk; + assign routers__reset[11] = reset; + assign routers__clk[12] = clk; + assign routers__reset[12] = reset; + assign routers__clk[13] = clk; + assign routers__reset[13] = reset; + assign routers__clk[14] = clk; + assign routers__reset[14] = reset; + assign routers__clk[15] = clk; + assign routers__reset[15] = reset; + assign routers__clk[16] = clk; + assign routers__reset[16] = reset; + assign recv_adp__clk[0] = clk; + assign recv_adp__reset[0] = reset; + assign recv_adp__clk[1] = clk; + assign recv_adp__reset[1] = reset; + assign recv_adp__clk[2] = clk; + assign recv_adp__reset[2] = reset; + assign recv_adp__clk[3] = clk; + assign recv_adp__reset[3] = reset; + assign recv_adp__clk[4] = clk; + assign recv_adp__reset[4] = reset; + assign recv_adp__clk[5] = clk; + assign recv_adp__reset[5] = reset; + assign recv_adp__clk[6] = clk; + assign recv_adp__reset[6] = reset; + assign recv_adp__clk[7] = clk; + assign recv_adp__reset[7] = reset; + assign recv_adp__clk[8] = clk; + assign recv_adp__reset[8] = reset; + assign recv_adp__clk[9] = clk; + assign recv_adp__reset[9] = reset; + assign recv_adp__clk[10] = clk; + assign recv_adp__reset[10] = reset; + assign recv_adp__clk[11] = clk; + assign recv_adp__reset[11] = reset; + assign recv_adp__clk[12] = clk; + assign recv_adp__reset[12] = reset; + assign recv_adp__clk[13] = clk; + assign recv_adp__reset[13] = reset; + assign recv_adp__clk[14] = clk; + assign recv_adp__reset[14] = reset; + assign recv_adp__clk[15] = clk; + assign recv_adp__reset[15] = reset; + assign recv_adp__clk[16] = clk; + assign recv_adp__reset[16] = reset; + assign send_adp__clk[0] = clk; + assign send_adp__reset[0] = reset; + assign send_adp__clk[1] = clk; + assign send_adp__reset[1] = reset; + assign send_adp__clk[2] = clk; + assign send_adp__reset[2] = reset; + assign send_adp__clk[3] = clk; + assign send_adp__reset[3] = reset; + assign send_adp__clk[4] = clk; + assign send_adp__reset[4] = reset; + assign send_adp__clk[5] = clk; + assign send_adp__reset[5] = reset; + assign send_adp__clk[6] = clk; + assign send_adp__reset[6] = reset; + assign send_adp__clk[7] = clk; + assign send_adp__reset[7] = reset; + assign send_adp__clk[8] = clk; + assign send_adp__reset[8] = reset; + assign send_adp__clk[9] = clk; + assign send_adp__reset[9] = reset; + assign send_adp__clk[10] = clk; + assign send_adp__reset[10] = reset; + assign send_adp__clk[11] = clk; + assign send_adp__reset[11] = reset; + assign send_adp__clk[12] = clk; + assign send_adp__reset[12] = reset; + assign send_adp__clk[13] = clk; + assign send_adp__reset[13] = reset; + assign send_adp__clk[14] = clk; + assign send_adp__reset[14] = reset; + assign send_adp__clk[15] = clk; + assign send_adp__reset[15] = reset; + assign send_adp__clk[16] = clk; + assign send_adp__reset[16] = reset; + assign routers__recv__en[1][0] = routers__send__en[0][1]; + assign routers__recv__msg[1][0] = routers__send__msg[0][1]; + assign routers__send__yum[0][1][0] = routers__recv__yum[1][0][0]; + assign routers__send__yum[0][1][1] = routers__recv__yum[1][0][1]; + assign routers__recv__en[0][1] = routers__send__en[1][0]; + assign routers__recv__msg[0][1] = routers__send__msg[1][0]; + assign routers__send__yum[1][0][0] = routers__recv__yum[0][1][0]; + assign routers__send__yum[1][0][1] = routers__recv__yum[0][1][1]; + assign recv_adp__recv__msg[0] = recv__msg[0]; + assign recv__rdy[0] = recv_adp__recv__rdy[0]; + assign recv_adp__recv__val[0] = recv__val[0]; + assign routers__recv__en[0][2] = recv_adp__send__en[0]; + assign routers__recv__msg[0][2] = recv_adp__send__msg[0]; + assign recv_adp__send__yum[0][0] = routers__recv__yum[0][2][0]; + assign recv_adp__send__yum[0][1] = routers__recv__yum[0][2][1]; + assign send_adp__recv__en[0] = routers__send__en[0][2]; + assign send_adp__recv__msg[0] = routers__send__msg[0][2]; + assign routers__send__yum[0][2][0] = send_adp__recv__yum[0][0]; + assign routers__send__yum[0][2][1] = send_adp__recv__yum[0][1]; + assign send__msg[0] = send_adp__send__msg[0]; + assign send_adp__send__rdy[0] = send__rdy[0]; + assign send__val[0] = send_adp__send__val[0]; + assign routers__recv__en[2][0] = routers__send__en[1][1]; + assign routers__recv__msg[2][0] = routers__send__msg[1][1]; + assign routers__send__yum[1][1][0] = routers__recv__yum[2][0][0]; + assign routers__send__yum[1][1][1] = routers__recv__yum[2][0][1]; + assign routers__recv__en[1][1] = routers__send__en[2][0]; + assign routers__recv__msg[1][1] = routers__send__msg[2][0]; + assign routers__send__yum[2][0][0] = routers__recv__yum[1][1][0]; + assign routers__send__yum[2][0][1] = routers__recv__yum[1][1][1]; + assign recv_adp__recv__msg[1] = recv__msg[1]; + assign recv__rdy[1] = recv_adp__recv__rdy[1]; + assign recv_adp__recv__val[1] = recv__val[1]; + assign routers__recv__en[1][2] = recv_adp__send__en[1]; + assign routers__recv__msg[1][2] = recv_adp__send__msg[1]; + assign recv_adp__send__yum[1][0] = routers__recv__yum[1][2][0]; + assign recv_adp__send__yum[1][1] = routers__recv__yum[1][2][1]; + assign send_adp__recv__en[1] = routers__send__en[1][2]; + assign send_adp__recv__msg[1] = routers__send__msg[1][2]; + assign routers__send__yum[1][2][0] = send_adp__recv__yum[1][0]; + assign routers__send__yum[1][2][1] = send_adp__recv__yum[1][1]; + assign send__msg[1] = send_adp__send__msg[1]; + assign send_adp__send__rdy[1] = send__rdy[1]; + assign send__val[1] = send_adp__send__val[1]; + assign routers__recv__en[3][0] = routers__send__en[2][1]; + assign routers__recv__msg[3][0] = routers__send__msg[2][1]; + assign routers__send__yum[2][1][0] = routers__recv__yum[3][0][0]; + assign routers__send__yum[2][1][1] = routers__recv__yum[3][0][1]; + assign routers__recv__en[2][1] = routers__send__en[3][0]; + assign routers__recv__msg[2][1] = routers__send__msg[3][0]; + assign routers__send__yum[3][0][0] = routers__recv__yum[2][1][0]; + assign routers__send__yum[3][0][1] = routers__recv__yum[2][1][1]; + assign recv_adp__recv__msg[2] = recv__msg[2]; + assign recv__rdy[2] = recv_adp__recv__rdy[2]; + assign recv_adp__recv__val[2] = recv__val[2]; + assign routers__recv__en[2][2] = recv_adp__send__en[2]; + assign routers__recv__msg[2][2] = recv_adp__send__msg[2]; + assign recv_adp__send__yum[2][0] = routers__recv__yum[2][2][0]; + assign recv_adp__send__yum[2][1] = routers__recv__yum[2][2][1]; + assign send_adp__recv__en[2] = routers__send__en[2][2]; + assign send_adp__recv__msg[2] = routers__send__msg[2][2]; + assign routers__send__yum[2][2][0] = send_adp__recv__yum[2][0]; + assign routers__send__yum[2][2][1] = send_adp__recv__yum[2][1]; + assign send__msg[2] = send_adp__send__msg[2]; + assign send_adp__send__rdy[2] = send__rdy[2]; + assign send__val[2] = send_adp__send__val[2]; + assign routers__recv__en[4][0] = routers__send__en[3][1]; + assign routers__recv__msg[4][0] = routers__send__msg[3][1]; + assign routers__send__yum[3][1][0] = routers__recv__yum[4][0][0]; + assign routers__send__yum[3][1][1] = routers__recv__yum[4][0][1]; + assign routers__recv__en[3][1] = routers__send__en[4][0]; + assign routers__recv__msg[3][1] = routers__send__msg[4][0]; + assign routers__send__yum[4][0][0] = routers__recv__yum[3][1][0]; + assign routers__send__yum[4][0][1] = routers__recv__yum[3][1][1]; + assign recv_adp__recv__msg[3] = recv__msg[3]; + assign recv__rdy[3] = recv_adp__recv__rdy[3]; + assign recv_adp__recv__val[3] = recv__val[3]; + assign routers__recv__en[3][2] = recv_adp__send__en[3]; + assign routers__recv__msg[3][2] = recv_adp__send__msg[3]; + assign recv_adp__send__yum[3][0] = routers__recv__yum[3][2][0]; + assign recv_adp__send__yum[3][1] = routers__recv__yum[3][2][1]; + assign send_adp__recv__en[3] = routers__send__en[3][2]; + assign send_adp__recv__msg[3] = routers__send__msg[3][2]; + assign routers__send__yum[3][2][0] = send_adp__recv__yum[3][0]; + assign routers__send__yum[3][2][1] = send_adp__recv__yum[3][1]; + assign send__msg[3] = send_adp__send__msg[3]; + assign send_adp__send__rdy[3] = send__rdy[3]; + assign send__val[3] = send_adp__send__val[3]; + assign routers__recv__en[5][0] = routers__send__en[4][1]; + assign routers__recv__msg[5][0] = routers__send__msg[4][1]; + assign routers__send__yum[4][1][0] = routers__recv__yum[5][0][0]; + assign routers__send__yum[4][1][1] = routers__recv__yum[5][0][1]; + assign routers__recv__en[4][1] = routers__send__en[5][0]; + assign routers__recv__msg[4][1] = routers__send__msg[5][0]; + assign routers__send__yum[5][0][0] = routers__recv__yum[4][1][0]; + assign routers__send__yum[5][0][1] = routers__recv__yum[4][1][1]; + assign recv_adp__recv__msg[4] = recv__msg[4]; + assign recv__rdy[4] = recv_adp__recv__rdy[4]; + assign recv_adp__recv__val[4] = recv__val[4]; + assign routers__recv__en[4][2] = recv_adp__send__en[4]; + assign routers__recv__msg[4][2] = recv_adp__send__msg[4]; + assign recv_adp__send__yum[4][0] = routers__recv__yum[4][2][0]; + assign recv_adp__send__yum[4][1] = routers__recv__yum[4][2][1]; + assign send_adp__recv__en[4] = routers__send__en[4][2]; + assign send_adp__recv__msg[4] = routers__send__msg[4][2]; + assign routers__send__yum[4][2][0] = send_adp__recv__yum[4][0]; + assign routers__send__yum[4][2][1] = send_adp__recv__yum[4][1]; + assign send__msg[4] = send_adp__send__msg[4]; + assign send_adp__send__rdy[4] = send__rdy[4]; + assign send__val[4] = send_adp__send__val[4]; + assign routers__recv__en[6][0] = routers__send__en[5][1]; + assign routers__recv__msg[6][0] = routers__send__msg[5][1]; + assign routers__send__yum[5][1][0] = routers__recv__yum[6][0][0]; + assign routers__send__yum[5][1][1] = routers__recv__yum[6][0][1]; + assign routers__recv__en[5][1] = routers__send__en[6][0]; + assign routers__recv__msg[5][1] = routers__send__msg[6][0]; + assign routers__send__yum[6][0][0] = routers__recv__yum[5][1][0]; + assign routers__send__yum[6][0][1] = routers__recv__yum[5][1][1]; + assign recv_adp__recv__msg[5] = recv__msg[5]; + assign recv__rdy[5] = recv_adp__recv__rdy[5]; + assign recv_adp__recv__val[5] = recv__val[5]; + assign routers__recv__en[5][2] = recv_adp__send__en[5]; + assign routers__recv__msg[5][2] = recv_adp__send__msg[5]; + assign recv_adp__send__yum[5][0] = routers__recv__yum[5][2][0]; + assign recv_adp__send__yum[5][1] = routers__recv__yum[5][2][1]; + assign send_adp__recv__en[5] = routers__send__en[5][2]; + assign send_adp__recv__msg[5] = routers__send__msg[5][2]; + assign routers__send__yum[5][2][0] = send_adp__recv__yum[5][0]; + assign routers__send__yum[5][2][1] = send_adp__recv__yum[5][1]; + assign send__msg[5] = send_adp__send__msg[5]; + assign send_adp__send__rdy[5] = send__rdy[5]; + assign send__val[5] = send_adp__send__val[5]; + assign routers__recv__en[7][0] = routers__send__en[6][1]; + assign routers__recv__msg[7][0] = routers__send__msg[6][1]; + assign routers__send__yum[6][1][0] = routers__recv__yum[7][0][0]; + assign routers__send__yum[6][1][1] = routers__recv__yum[7][0][1]; + assign routers__recv__en[6][1] = routers__send__en[7][0]; + assign routers__recv__msg[6][1] = routers__send__msg[7][0]; + assign routers__send__yum[7][0][0] = routers__recv__yum[6][1][0]; + assign routers__send__yum[7][0][1] = routers__recv__yum[6][1][1]; + assign recv_adp__recv__msg[6] = recv__msg[6]; + assign recv__rdy[6] = recv_adp__recv__rdy[6]; + assign recv_adp__recv__val[6] = recv__val[6]; + assign routers__recv__en[6][2] = recv_adp__send__en[6]; + assign routers__recv__msg[6][2] = recv_adp__send__msg[6]; + assign recv_adp__send__yum[6][0] = routers__recv__yum[6][2][0]; + assign recv_adp__send__yum[6][1] = routers__recv__yum[6][2][1]; + assign send_adp__recv__en[6] = routers__send__en[6][2]; + assign send_adp__recv__msg[6] = routers__send__msg[6][2]; + assign routers__send__yum[6][2][0] = send_adp__recv__yum[6][0]; + assign routers__send__yum[6][2][1] = send_adp__recv__yum[6][1]; + assign send__msg[6] = send_adp__send__msg[6]; + assign send_adp__send__rdy[6] = send__rdy[6]; + assign send__val[6] = send_adp__send__val[6]; + assign routers__recv__en[8][0] = routers__send__en[7][1]; + assign routers__recv__msg[8][0] = routers__send__msg[7][1]; + assign routers__send__yum[7][1][0] = routers__recv__yum[8][0][0]; + assign routers__send__yum[7][1][1] = routers__recv__yum[8][0][1]; + assign routers__recv__en[7][1] = routers__send__en[8][0]; + assign routers__recv__msg[7][1] = routers__send__msg[8][0]; + assign routers__send__yum[8][0][0] = routers__recv__yum[7][1][0]; + assign routers__send__yum[8][0][1] = routers__recv__yum[7][1][1]; + assign recv_adp__recv__msg[7] = recv__msg[7]; + assign recv__rdy[7] = recv_adp__recv__rdy[7]; + assign recv_adp__recv__val[7] = recv__val[7]; + assign routers__recv__en[7][2] = recv_adp__send__en[7]; + assign routers__recv__msg[7][2] = recv_adp__send__msg[7]; + assign recv_adp__send__yum[7][0] = routers__recv__yum[7][2][0]; + assign recv_adp__send__yum[7][1] = routers__recv__yum[7][2][1]; + assign send_adp__recv__en[7] = routers__send__en[7][2]; + assign send_adp__recv__msg[7] = routers__send__msg[7][2]; + assign routers__send__yum[7][2][0] = send_adp__recv__yum[7][0]; + assign routers__send__yum[7][2][1] = send_adp__recv__yum[7][1]; + assign send__msg[7] = send_adp__send__msg[7]; + assign send_adp__send__rdy[7] = send__rdy[7]; + assign send__val[7] = send_adp__send__val[7]; + assign routers__recv__en[9][0] = routers__send__en[8][1]; + assign routers__recv__msg[9][0] = routers__send__msg[8][1]; + assign routers__send__yum[8][1][0] = routers__recv__yum[9][0][0]; + assign routers__send__yum[8][1][1] = routers__recv__yum[9][0][1]; + assign routers__recv__en[8][1] = routers__send__en[9][0]; + assign routers__recv__msg[8][1] = routers__send__msg[9][0]; + assign routers__send__yum[9][0][0] = routers__recv__yum[8][1][0]; + assign routers__send__yum[9][0][1] = routers__recv__yum[8][1][1]; + assign recv_adp__recv__msg[8] = recv__msg[8]; + assign recv__rdy[8] = recv_adp__recv__rdy[8]; + assign recv_adp__recv__val[8] = recv__val[8]; + assign routers__recv__en[8][2] = recv_adp__send__en[8]; + assign routers__recv__msg[8][2] = recv_adp__send__msg[8]; + assign recv_adp__send__yum[8][0] = routers__recv__yum[8][2][0]; + assign recv_adp__send__yum[8][1] = routers__recv__yum[8][2][1]; + assign send_adp__recv__en[8] = routers__send__en[8][2]; + assign send_adp__recv__msg[8] = routers__send__msg[8][2]; + assign routers__send__yum[8][2][0] = send_adp__recv__yum[8][0]; + assign routers__send__yum[8][2][1] = send_adp__recv__yum[8][1]; + assign send__msg[8] = send_adp__send__msg[8]; + assign send_adp__send__rdy[8] = send__rdy[8]; + assign send__val[8] = send_adp__send__val[8]; + assign routers__recv__en[10][0] = routers__send__en[9][1]; + assign routers__recv__msg[10][0] = routers__send__msg[9][1]; + assign routers__send__yum[9][1][0] = routers__recv__yum[10][0][0]; + assign routers__send__yum[9][1][1] = routers__recv__yum[10][0][1]; + assign routers__recv__en[9][1] = routers__send__en[10][0]; + assign routers__recv__msg[9][1] = routers__send__msg[10][0]; + assign routers__send__yum[10][0][0] = routers__recv__yum[9][1][0]; + assign routers__send__yum[10][0][1] = routers__recv__yum[9][1][1]; + assign recv_adp__recv__msg[9] = recv__msg[9]; + assign recv__rdy[9] = recv_adp__recv__rdy[9]; + assign recv_adp__recv__val[9] = recv__val[9]; + assign routers__recv__en[9][2] = recv_adp__send__en[9]; + assign routers__recv__msg[9][2] = recv_adp__send__msg[9]; + assign recv_adp__send__yum[9][0] = routers__recv__yum[9][2][0]; + assign recv_adp__send__yum[9][1] = routers__recv__yum[9][2][1]; + assign send_adp__recv__en[9] = routers__send__en[9][2]; + assign send_adp__recv__msg[9] = routers__send__msg[9][2]; + assign routers__send__yum[9][2][0] = send_adp__recv__yum[9][0]; + assign routers__send__yum[9][2][1] = send_adp__recv__yum[9][1]; + assign send__msg[9] = send_adp__send__msg[9]; + assign send_adp__send__rdy[9] = send__rdy[9]; + assign send__val[9] = send_adp__send__val[9]; + assign routers__recv__en[11][0] = routers__send__en[10][1]; + assign routers__recv__msg[11][0] = routers__send__msg[10][1]; + assign routers__send__yum[10][1][0] = routers__recv__yum[11][0][0]; + assign routers__send__yum[10][1][1] = routers__recv__yum[11][0][1]; + assign routers__recv__en[10][1] = routers__send__en[11][0]; + assign routers__recv__msg[10][1] = routers__send__msg[11][0]; + assign routers__send__yum[11][0][0] = routers__recv__yum[10][1][0]; + assign routers__send__yum[11][0][1] = routers__recv__yum[10][1][1]; + assign recv_adp__recv__msg[10] = recv__msg[10]; + assign recv__rdy[10] = recv_adp__recv__rdy[10]; + assign recv_adp__recv__val[10] = recv__val[10]; + assign routers__recv__en[10][2] = recv_adp__send__en[10]; + assign routers__recv__msg[10][2] = recv_adp__send__msg[10]; + assign recv_adp__send__yum[10][0] = routers__recv__yum[10][2][0]; + assign recv_adp__send__yum[10][1] = routers__recv__yum[10][2][1]; + assign send_adp__recv__en[10] = routers__send__en[10][2]; + assign send_adp__recv__msg[10] = routers__send__msg[10][2]; + assign routers__send__yum[10][2][0] = send_adp__recv__yum[10][0]; + assign routers__send__yum[10][2][1] = send_adp__recv__yum[10][1]; + assign send__msg[10] = send_adp__send__msg[10]; + assign send_adp__send__rdy[10] = send__rdy[10]; + assign send__val[10] = send_adp__send__val[10]; + assign routers__recv__en[12][0] = routers__send__en[11][1]; + assign routers__recv__msg[12][0] = routers__send__msg[11][1]; + assign routers__send__yum[11][1][0] = routers__recv__yum[12][0][0]; + assign routers__send__yum[11][1][1] = routers__recv__yum[12][0][1]; + assign routers__recv__en[11][1] = routers__send__en[12][0]; + assign routers__recv__msg[11][1] = routers__send__msg[12][0]; + assign routers__send__yum[12][0][0] = routers__recv__yum[11][1][0]; + assign routers__send__yum[12][0][1] = routers__recv__yum[11][1][1]; + assign recv_adp__recv__msg[11] = recv__msg[11]; + assign recv__rdy[11] = recv_adp__recv__rdy[11]; + assign recv_adp__recv__val[11] = recv__val[11]; + assign routers__recv__en[11][2] = recv_adp__send__en[11]; + assign routers__recv__msg[11][2] = recv_adp__send__msg[11]; + assign recv_adp__send__yum[11][0] = routers__recv__yum[11][2][0]; + assign recv_adp__send__yum[11][1] = routers__recv__yum[11][2][1]; + assign send_adp__recv__en[11] = routers__send__en[11][2]; + assign send_adp__recv__msg[11] = routers__send__msg[11][2]; + assign routers__send__yum[11][2][0] = send_adp__recv__yum[11][0]; + assign routers__send__yum[11][2][1] = send_adp__recv__yum[11][1]; + assign send__msg[11] = send_adp__send__msg[11]; + assign send_adp__send__rdy[11] = send__rdy[11]; + assign send__val[11] = send_adp__send__val[11]; + assign routers__recv__en[13][0] = routers__send__en[12][1]; + assign routers__recv__msg[13][0] = routers__send__msg[12][1]; + assign routers__send__yum[12][1][0] = routers__recv__yum[13][0][0]; + assign routers__send__yum[12][1][1] = routers__recv__yum[13][0][1]; + assign routers__recv__en[12][1] = routers__send__en[13][0]; + assign routers__recv__msg[12][1] = routers__send__msg[13][0]; + assign routers__send__yum[13][0][0] = routers__recv__yum[12][1][0]; + assign routers__send__yum[13][0][1] = routers__recv__yum[12][1][1]; + assign recv_adp__recv__msg[12] = recv__msg[12]; + assign recv__rdy[12] = recv_adp__recv__rdy[12]; + assign recv_adp__recv__val[12] = recv__val[12]; + assign routers__recv__en[12][2] = recv_adp__send__en[12]; + assign routers__recv__msg[12][2] = recv_adp__send__msg[12]; + assign recv_adp__send__yum[12][0] = routers__recv__yum[12][2][0]; + assign recv_adp__send__yum[12][1] = routers__recv__yum[12][2][1]; + assign send_adp__recv__en[12] = routers__send__en[12][2]; + assign send_adp__recv__msg[12] = routers__send__msg[12][2]; + assign routers__send__yum[12][2][0] = send_adp__recv__yum[12][0]; + assign routers__send__yum[12][2][1] = send_adp__recv__yum[12][1]; + assign send__msg[12] = send_adp__send__msg[12]; + assign send_adp__send__rdy[12] = send__rdy[12]; + assign send__val[12] = send_adp__send__val[12]; + assign routers__recv__en[14][0] = routers__send__en[13][1]; + assign routers__recv__msg[14][0] = routers__send__msg[13][1]; + assign routers__send__yum[13][1][0] = routers__recv__yum[14][0][0]; + assign routers__send__yum[13][1][1] = routers__recv__yum[14][0][1]; + assign routers__recv__en[13][1] = routers__send__en[14][0]; + assign routers__recv__msg[13][1] = routers__send__msg[14][0]; + assign routers__send__yum[14][0][0] = routers__recv__yum[13][1][0]; + assign routers__send__yum[14][0][1] = routers__recv__yum[13][1][1]; + assign recv_adp__recv__msg[13] = recv__msg[13]; + assign recv__rdy[13] = recv_adp__recv__rdy[13]; + assign recv_adp__recv__val[13] = recv__val[13]; + assign routers__recv__en[13][2] = recv_adp__send__en[13]; + assign routers__recv__msg[13][2] = recv_adp__send__msg[13]; + assign recv_adp__send__yum[13][0] = routers__recv__yum[13][2][0]; + assign recv_adp__send__yum[13][1] = routers__recv__yum[13][2][1]; + assign send_adp__recv__en[13] = routers__send__en[13][2]; + assign send_adp__recv__msg[13] = routers__send__msg[13][2]; + assign routers__send__yum[13][2][0] = send_adp__recv__yum[13][0]; + assign routers__send__yum[13][2][1] = send_adp__recv__yum[13][1]; + assign send__msg[13] = send_adp__send__msg[13]; + assign send_adp__send__rdy[13] = send__rdy[13]; + assign send__val[13] = send_adp__send__val[13]; + assign routers__recv__en[15][0] = routers__send__en[14][1]; + assign routers__recv__msg[15][0] = routers__send__msg[14][1]; + assign routers__send__yum[14][1][0] = routers__recv__yum[15][0][0]; + assign routers__send__yum[14][1][1] = routers__recv__yum[15][0][1]; + assign routers__recv__en[14][1] = routers__send__en[15][0]; + assign routers__recv__msg[14][1] = routers__send__msg[15][0]; + assign routers__send__yum[15][0][0] = routers__recv__yum[14][1][0]; + assign routers__send__yum[15][0][1] = routers__recv__yum[14][1][1]; + assign recv_adp__recv__msg[14] = recv__msg[14]; + assign recv__rdy[14] = recv_adp__recv__rdy[14]; + assign recv_adp__recv__val[14] = recv__val[14]; + assign routers__recv__en[14][2] = recv_adp__send__en[14]; + assign routers__recv__msg[14][2] = recv_adp__send__msg[14]; + assign recv_adp__send__yum[14][0] = routers__recv__yum[14][2][0]; + assign recv_adp__send__yum[14][1] = routers__recv__yum[14][2][1]; + assign send_adp__recv__en[14] = routers__send__en[14][2]; + assign send_adp__recv__msg[14] = routers__send__msg[14][2]; + assign routers__send__yum[14][2][0] = send_adp__recv__yum[14][0]; + assign routers__send__yum[14][2][1] = send_adp__recv__yum[14][1]; + assign send__msg[14] = send_adp__send__msg[14]; + assign send_adp__send__rdy[14] = send__rdy[14]; + assign send__val[14] = send_adp__send__val[14]; + assign routers__recv__en[16][0] = routers__send__en[15][1]; + assign routers__recv__msg[16][0] = routers__send__msg[15][1]; + assign routers__send__yum[15][1][0] = routers__recv__yum[16][0][0]; + assign routers__send__yum[15][1][1] = routers__recv__yum[16][0][1]; + assign routers__recv__en[15][1] = routers__send__en[16][0]; + assign routers__recv__msg[15][1] = routers__send__msg[16][0]; + assign routers__send__yum[16][0][0] = routers__recv__yum[15][1][0]; + assign routers__send__yum[16][0][1] = routers__recv__yum[15][1][1]; + assign recv_adp__recv__msg[15] = recv__msg[15]; + assign recv__rdy[15] = recv_adp__recv__rdy[15]; + assign recv_adp__recv__val[15] = recv__val[15]; + assign routers__recv__en[15][2] = recv_adp__send__en[15]; + assign routers__recv__msg[15][2] = recv_adp__send__msg[15]; + assign recv_adp__send__yum[15][0] = routers__recv__yum[15][2][0]; + assign recv_adp__send__yum[15][1] = routers__recv__yum[15][2][1]; + assign send_adp__recv__en[15] = routers__send__en[15][2]; + assign send_adp__recv__msg[15] = routers__send__msg[15][2]; + assign routers__send__yum[15][2][0] = send_adp__recv__yum[15][0]; + assign routers__send__yum[15][2][1] = send_adp__recv__yum[15][1]; + assign send__msg[15] = send_adp__send__msg[15]; + assign send_adp__send__rdy[15] = send__rdy[15]; + assign send__val[15] = send_adp__send__val[15]; + assign routers__recv__en[0][0] = routers__send__en[16][1]; + assign routers__recv__msg[0][0] = routers__send__msg[16][1]; + assign routers__send__yum[16][1][0] = routers__recv__yum[0][0][0]; + assign routers__send__yum[16][1][1] = routers__recv__yum[0][0][1]; + assign routers__recv__en[16][1] = routers__send__en[0][0]; + assign routers__recv__msg[16][1] = routers__send__msg[0][0]; + assign routers__send__yum[0][0][0] = routers__recv__yum[16][1][0]; + assign routers__send__yum[0][0][1] = routers__recv__yum[16][1][1]; + assign recv_adp__recv__msg[16] = recv__msg[16]; + assign recv__rdy[16] = recv_adp__recv__rdy[16]; + assign recv_adp__recv__val[16] = recv__val[16]; + assign routers__recv__en[16][2] = recv_adp__send__en[16]; + assign routers__recv__msg[16][2] = recv_adp__send__msg[16]; + assign recv_adp__send__yum[16][0] = routers__recv__yum[16][2][0]; + assign recv_adp__send__yum[16][1] = routers__recv__yum[16][2][1]; + assign send_adp__recv__en[16] = routers__send__en[16][2]; + assign send_adp__recv__msg[16] = routers__send__msg[16][2]; + assign routers__send__yum[16][2][0] = send_adp__recv__yum[16][0]; + assign routers__send__yum[16][2][1] = send_adp__recv__yum[16][1]; + assign send__msg[16] = send_adp__send__msg[16]; + assign send_adp__send__rdy[16] = send__rdy[16]; + assign send__val[16] = send_adp__send__val[16]; + +endmodule + + +// PyMTL Component ChannelRTL Definition +// Full name: ChannelRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_NormalQueueRTL__latency_0 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py + +module ChannelRTL__c31a2b1c86c6a129 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + assign send__msg = recv__msg; + assign recv__rdy = send__rdy; + assign send__val = recv__val; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__nregs_16__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__bd22936ec5812d0d +( + input logic [0:0] clk , + input logic [3:0] raddr [0:0], + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rdata [0:0], + input logic [0:0] reset , + input logic [3:0] waddr [0:0], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 regs [0:15]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component DataMemWrapperRTL Definition +// Full name: DataMemWrapperRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__MemReadType_MemAccessPacket_8_3_128__43c148781d2f2a57__MemWriteType_MemAccessPacket_8_3_128__43c148781d2f2a57__MemResponseType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__global_data_mem_size_128__per_bank_data_mem_size_16__is_combinational_True +// At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py + +module DataMemWrapperRTL__33e0a5b37976e571 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_rd__msg , + output logic [0:0] recv_rd__rdy , + input logic [0:0] recv_rd__val , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_wr__msg , + output logic [0:0] recv_wr__rdy , + input logic [0:0] recv_wr__val , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [4:0] __const__per_bank_data_mem_size_at_request_memory = 5'd16; + logic [6:0] streaming_rd_addr; + MemAccessPacket_8_3_128__43c148781d2f2a57 streaming_rd_read_reqeust; + logic [0:0] streaming_rd_status; + //------------------------------------------------------------- + // Component channel_rd + //------------------------------------------------------------- + + logic [0:0] channel_rd__clk; + logic [0:0] channel_rd__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 channel_rd__recv__msg; + logic [0:0] channel_rd__recv__rdy; + logic [0:0] channel_rd__recv__val; + MemAccessPacket_8_3_128__43c148781d2f2a57 channel_rd__send__msg; + logic [0:0] channel_rd__send__rdy; + logic [0:0] channel_rd__send__val; + + ChannelRTL__c31a2b1c86c6a129 channel_rd + ( + .clk( channel_rd__clk ), + .reset( channel_rd__reset ), + .recv__msg( channel_rd__recv__msg ), + .recv__rdy( channel_rd__recv__rdy ), + .recv__val( channel_rd__recv__val ), + .send__msg( channel_rd__send__msg ), + .send__rdy( channel_rd__send__rdy ), + .send__val( channel_rd__send__val ) + ); + + //------------------------------------------------------------- + // End of component channel_rd + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component channel_wr + //------------------------------------------------------------- + + logic [0:0] channel_wr__clk; + logic [0:0] channel_wr__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 channel_wr__recv__msg; + logic [0:0] channel_wr__recv__rdy; + logic [0:0] channel_wr__recv__val; + MemAccessPacket_8_3_128__43c148781d2f2a57 channel_wr__send__msg; + logic [0:0] channel_wr__send__rdy; + logic [0:0] channel_wr__send__val; + + ChannelRTL__c31a2b1c86c6a129 channel_wr + ( + .clk( channel_wr__clk ), + .reset( channel_wr__reset ), + .recv__msg( channel_wr__recv__msg ), + .recv__rdy( channel_wr__recv__rdy ), + .recv__val( channel_wr__recv__val ), + .send__msg( channel_wr__send__msg ), + .send__rdy( channel_wr__send__rdy ), + .send__val( channel_wr__send__val ) + ); + + //------------------------------------------------------------- + // End of component channel_wr + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component memory + //------------------------------------------------------------- + + logic [0:0] memory__clk; + logic [3:0] memory__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 memory__rdata [0:0]; + logic [0:0] memory__reset; + logic [3:0] memory__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 memory__wdata [0:0]; + logic [0:0] memory__wen [0:0]; + + RegisterFile__bd22936ec5812d0d memory + ( + .clk( memory__clk ), + .raddr( memory__raddr ), + .rdata( memory__rdata ), + .reset( memory__reset ), + .waddr( memory__waddr ), + .wdata( memory__wdata ), + .wen( memory__wen ) + ); + + //------------------------------------------------------------- + // End of component memory + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:76 + // @update + // def compose_send_msg(): + // s.send.msg @= MemResponseType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) + // # TODO: change to pipe's out's wen. + // # Streaming read example: + // # At cycle 0, s.channel_rd issues one single streaming read request (indicated by + // # s.channel_rd.send.msg.streaming_rd = 1) with s.channel_rd.send.msg.addr = 2, + // # s.channel_rd.send.msg.streaming_rd_stride = 2, and s.channel_rd.send.msg.streaming_rd_end_addr = 6. + // # Then s.send will return the multiple response data from addr=2, addr=4, and addr=6 + // # at cycle 0, cycle 1, and cycle 2, respectively. + // if s.streaming_rd_status: + // s.send.msg.src @= s.streaming_rd_read_reqeust.dst + // s.send.msg.dst @= s.streaming_rd_read_reqeust.src + // s.send.msg.addr @= s.streaming_rd_addr + // s.send.msg.data @= s.memory.rdata[0] + // s.send.msg.src_cgra @= s.streaming_rd_read_reqeust.src_cgra + // s.send.msg.src_tile @= s.streaming_rd_read_reqeust.src_tile + // s.send.msg.remote_src_port @= s.streaming_rd_read_reqeust.remote_src_port + // elif s.channel_rd.send.val: + // s.send.msg.src @= s.channel_rd.send.msg.dst + // s.send.msg.dst @= s.channel_rd.send.msg.src + // s.send.msg.addr @= s.channel_rd.send.msg.addr + // s.send.msg.data @= s.memory.rdata[0] + // s.send.msg.src_cgra @= s.channel_rd.send.msg.src_cgra + // s.send.msg.src_tile @= s.channel_rd.send.msg.src_tile + // s.send.msg.remote_src_port @= s.channel_rd.send.msg.remote_src_port + + always_comb begin : compose_send_msg + send__msg = { 2'd0, 3'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; + if ( streaming_rd_status ) begin + send__msg.src = streaming_rd_read_reqeust.dst; + send__msg.dst = streaming_rd_read_reqeust.src; + send__msg.addr = streaming_rd_addr; + send__msg.data = memory__rdata[1'd0]; + send__msg.src_cgra = streaming_rd_read_reqeust.src_cgra; + send__msg.src_tile = streaming_rd_read_reqeust.src_tile; + send__msg.remote_src_port = streaming_rd_read_reqeust.remote_src_port; + end + else if ( channel_rd__send__val ) begin + send__msg.src = channel_rd__send__msg.dst; + send__msg.dst = channel_rd__send__msg.src; + send__msg.addr = channel_rd__send__msg.addr; + send__msg.data = memory__rdata[1'd0]; + send__msg.src_cgra = channel_rd__send__msg.src_cgra; + send__msg.src_tile = channel_rd__send__msg.src_tile; + send__msg.remote_src_port = channel_rd__send__msg.remote_src_port; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:123 + // @update + // def notify_channel_rdy(): + // # TODO: change to SRAM's rdy when replacing register file + // # with SRAM. + // if s.streaming_rd_status: + // # Issue one streaming request at one time. + // s.channel_rd.send.rdy @= 0 + // else: + // s.channel_rd.send.rdy @= s.send.rdy + // s.channel_wr.send.rdy @= 1 + + always_comb begin : notify_channel_rdy + if ( streaming_rd_status ) begin + channel_rd__send__rdy = 1'd0; + end + else + channel_rd__send__rdy = send__rdy; + channel_wr__send__rdy = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:134 + // @update + // def notify_send_val(): + // # TODO: change to SRAM's valid when replacing register file + // # with SRAM. + // if s.streaming_rd_status: + // # Keep sending read data during streaming status. + // s.send.val @= 1 + // else: + // s.send.val @= s.channel_rd.send.val + + always_comb begin : notify_send_val + if ( streaming_rd_status ) begin + send__val = 1'd1; + end + else + send__val = channel_rd__send__val; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:103 + // @update + // def request_memory(): + // # Default values. + // s.memory.wen[0] @= 0 + // s.memory.raddr[0] @= PerBankAddrType(0) + // s.memory.waddr[0] @= PerBankAddrType(0) + // s.memory.wdata[0] @= DataType(0, 0, 0, 0) + // + // if s.streaming_rd_status: + // s.memory.raddr[0] @= \ + // trunc(s.streaming_rd_addr % per_bank_data_mem_size, PerBankAddrType) + // if s.channel_rd.send.val: + // s.memory.raddr[0] @= \ + // trunc(s.channel_rd.send.msg.addr % per_bank_data_mem_size, PerBankAddrType) + // if s.channel_wr.send.val: + // s.memory.waddr[0] @= \ + // trunc(s.channel_wr.send.msg.addr % per_bank_data_mem_size, PerBankAddrType) + // s.memory.wdata[0] @= s.channel_wr.send.msg.data + // s.memory.wen[0] @= 1 + + always_comb begin : request_memory + memory__wen[1'd0] = 1'd0; + memory__raddr[1'd0] = 4'd0; + memory__waddr[1'd0] = 4'd0; + memory__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + if ( streaming_rd_status ) begin + memory__raddr[1'd0] = 4'(streaming_rd_addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); + end + if ( channel_rd__send__val ) begin + memory__raddr[1'd0] = 4'(channel_rd__send__msg.addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); + end + if ( channel_wr__send__val ) begin + memory__waddr[1'd0] = 4'(channel_wr__send__msg.addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); + memory__wdata[1'd0] = channel_wr__send__msg.data; + memory__wen[1'd0] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:63 + // @update_ff + // def update_streaming_rd_regs(): + // if s.channel_rd.send.val & s.channel_rd.send.msg.streaming_rd: + // s.streaming_rd_status <<= 1 + // s.streaming_rd_addr <<= s.channel_rd.send.msg.addr + s.channel_rd.send.msg.streaming_rd_stride + // s.streaming_rd_read_reqeust <<= s.channel_rd.send.msg + // elif s.streaming_rd_addr == s.streaming_rd_read_reqeust.streaming_rd_end_addr: + // s.streaming_rd_status <<= 0 + // s.streaming_rd_addr <<= GlobalAddrType(0) + // s.streaming_rd_read_reqeust <<= MemReadType() + // else: + // s.streaming_rd_addr <<= s.streaming_rd_addr + s.streaming_rd_read_reqeust.streaming_rd_stride + + always_ff @(posedge clk) begin : update_streaming_rd_regs + if ( channel_rd__send__val & channel_rd__send__msg.streaming_rd ) begin + streaming_rd_status <= 1'd1; + streaming_rd_addr <= channel_rd__send__msg.addr + channel_rd__send__msg.streaming_rd_stride; + streaming_rd_read_reqeust <= channel_rd__send__msg; + end + else if ( streaming_rd_addr == streaming_rd_read_reqeust.streaming_rd_end_addr ) begin + streaming_rd_status <= 1'd0; + streaming_rd_addr <= 7'd0; + streaming_rd_read_reqeust <= { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; + end + else + streaming_rd_addr <= streaming_rd_addr + streaming_rd_read_reqeust.streaming_rd_stride; + end + + assign memory__clk = clk; + assign memory__reset = reset; + assign channel_rd__clk = clk; + assign channel_rd__reset = reset; + assign channel_wr__clk = clk; + assign channel_wr__reset = reset; + assign channel_rd__recv__msg = recv_rd__msg; + assign recv_rd__rdy = channel_rd__recv__rdy; + assign channel_rd__recv__val = recv_rd__val; + assign channel_wr__recv__msg = recv_wr__msg; + assign recv_wr__rdy = channel_wr__recv__rdy; + assign channel_wr__recv__val = recv_wr__val; + +endmodule + + +// PyMTL Component Mux Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_2 +( + input logic [0:0] clk , + input MemAccessPacket_8_3_128__43c148781d2f2a57 in_ [0:1], + output MemAccessPacket_8_3_128__43c148781d2f2a57 out , + input logic [0:0] reset , + input logic [0:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__7305dd76cfb05fd9 +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output MemAccessPacket_8_3_128__43c148781d2f2a57 rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input MemAccessPacket_8_3_128__43c148781d2f2a57 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + MemAccessPacket_8_3_128__43c148781d2f2a57 regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component BypassQueueDpathRTL Definition +// Full name: BypassQueueDpathRTL__EntryType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueDpathRTL__4eac613e5285098c +( + input logic [0:0] clk , + input logic [0:0] mux_sel , + input logic [0:0] raddr , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_msg , + input logic [0:0] reset , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + MemAccessPacket_8_3_128__43c148781d2f2a57 mux__in_ [0:1]; + MemAccessPacket_8_3_128__43c148781d2f2a57 mux__out; + logic [0:0] mux__reset; + logic [0:0] mux__sel; + + Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_2 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + MemAccessPacket_8_3_128__43c148781d2f2a57 rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + MemAccessPacket_8_3_128__43c148781d2f2a57 rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__7305dd76cfb05fd9 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + assign mux__clk = clk; + assign mux__reset = reset; + assign mux__sel = mux_sel; + assign mux__in_[0] = rf__rdata[0]; + assign mux__in_[1] = recv_msg; + assign send_msg = mux__out; + +endmodule + + +// PyMTL Component BypassQueueRTL Definition +// Full name: BypassQueueRTL__EntryType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueRTL__4eac613e5285098c +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__mux_sel; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + BypassQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .mux_sel( ctrl__mux_sel ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__mux_sel; + logic [0:0] dpath__raddr; + MemAccessPacket_8_3_128__43c148781d2f2a57 dpath__recv_msg; + logic [0:0] dpath__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + BypassQueueDpathRTL__4eac613e5285098c dpath + ( + .clk( dpath__clk ), + .mux_sel( dpath__mux_sel ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign dpath__mux_sel = ctrl__mux_sel; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign count = ctrl__count; + assign dpath__recv_msg = recv__msg; + assign send__msg = dpath__send_msg; + +endmodule + + +// PyMTL Component InputUnitRTL Definition +// Full name: InputUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_BypassQueueRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py + +module InputUnitRTL__1864e8652261553b +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queue + //------------------------------------------------------------- + + logic [0:0] queue__clk; + logic [1:0] queue__count; + logic [0:0] queue__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 queue__recv__msg; + logic [0:0] queue__recv__rdy; + logic [0:0] queue__recv__val; + MemAccessPacket_8_3_128__43c148781d2f2a57 queue__send__msg; + logic [0:0] queue__send__rdy; + logic [0:0] queue__send__val; + + BypassQueueRTL__4eac613e5285098c queue + ( + .clk( queue__clk ), + .count( queue__count ), + .reset( queue__reset ), + .recv__msg( queue__recv__msg ), + .recv__rdy( queue__recv__rdy ), + .recv__val( queue__recv__val ), + .send__msg( queue__send__msg ), + .send__rdy( queue__send__rdy ), + .send__val( queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component queue + //------------------------------------------------------------- + + assign queue__clk = clk; + assign queue__reset = reset; + assign queue__recv__msg = recv__msg; + assign recv__rdy = queue__recv__rdy; + assign queue__recv__val = recv__val; + assign send__msg = queue__send__msg; + assign queue__send__rdy = send__rdy; + assign send__val = queue__send__val; + +endmodule + + +// PyMTL Component OutputUnitRTL Definition +// Full name: OutputUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_None +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py + +module OutputUnitRTL__a3f8631b75bafad0 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + assign send__msg = recv__msg; + assign recv__rdy = send__rdy; + assign send__val = recv__val; + +endmodule + + +// PyMTL Component XbarRouteUnitRTL Definition +// Full name: XbarRouteUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_outports_3 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py + +module XbarRouteUnitRTL__32c7752a7c15587d +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg [0:2] , + input logic [0:0] send__rdy [0:2] , + output logic [0:0] send__val [0:2] +); + localparam logic [1:0] __const__num_outports_at_up_ru_routing = 2'd3; + logic [1:0] out_dir; + logic [2:0] send_val; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 + // @update + // def up_ru_recv_rdy(): + // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 + + always_comb begin : up_ru_recv_rdy + recv__rdy = send__rdy[out_dir] > 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 + // @update + // def up_ru_routing(): + // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) + // + // for i in range( num_outports ): + // s.send[i].val @= b1(0) + // + // if s.recv.val: + // s.send[ s.out_dir ].val @= b1(1) + + always_comb begin : up_ru_routing + out_dir = recv__msg.dst; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) + send__val[2'(i)] = 1'd0; + if ( recv__val ) begin + send__val[out_dir] = 1'd1; + end + end + + assign send__msg[0] = recv__msg; + assign send_val[0:0] = send__val[0]; + assign send__msg[1] = recv__msg; + assign send_val[1:1] = send__val[1]; + assign send__msg[2] = recv__msg; + assign send_val[2:2] = send__val[2]; + +endmodule + + +// PyMTL Component RegEnRst Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py + +module RegEnRst__Type_Bits8__reset_value_1 +( + input logic [0:0] clk , + input logic [0:0] en , + input logic [7:0] in_ , + output logic [7:0] out , + input logic [0:0] reset +); + localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 + // @update_ff + // def up_regenrst(): + // if s.reset: s.out <<= reset_value + // elif s.en: s.out <<= s.in_ + + always_ff @(posedge clk) begin : up_regenrst + if ( reset ) begin + out <= 8'( __const__reset_value_at_up_regenrst ); + end + else if ( en ) begin + out <= in_; + end + end + +endmodule + + +// PyMTL Component RoundRobinArbiterEn Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py + +module RoundRobinArbiterEn__nreqs_8 +( + input logic [0:0] clk , + input logic [0:0] en , + output logic [7:0] grants , + input logic [7:0] reqs , + input logic [0:0] reset +); + localparam logic [3:0] __const__nreqs_at_comb_reqs_int = 4'd8; + localparam logic [4:0] __const__nreqsX2_at_comb_reqs_int = 5'd16; + localparam logic [3:0] __const__nreqs_at_comb_grants = 4'd8; + localparam logic [3:0] __const__nreqs_at_comb_priority_int = 4'd8; + localparam logic [4:0] __const__nreqsX2_at_comb_priority_int = 5'd16; + localparam logic [4:0] __const__nreqsX2_at_comb_kills = 5'd16; + localparam logic [4:0] __const__nreqsX2_at_comb_grants_int = 5'd16; + logic [15:0] grants_int; + logic [16:0] kills; + logic [0:0] priority_en; + logic [15:0] priority_int; + logic [15:0] reqs_int; + //------------------------------------------------------------- + // Component priority_reg + //------------------------------------------------------------- + + logic [0:0] priority_reg__clk; + logic [0:0] priority_reg__en; + logic [7:0] priority_reg__in_; + logic [7:0] priority_reg__out; + logic [0:0] priority_reg__reset; + + RegEnRst__Type_Bits8__reset_value_1 priority_reg + ( + .clk( priority_reg__clk ), + .en( priority_reg__en ), + .in_( priority_reg__in_ ), + .out( priority_reg__out ), + .reset( priority_reg__reset ) + ); + + //------------------------------------------------------------- + // End of component priority_reg + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 + // @update + // def comb_grants(): + // for i in range( nreqs ): + // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] + + always_comb begin : comb_grants + for ( int unsigned i = 1'd0; i < 4'( __const__nreqs_at_comb_grants ); i += 1'd1 ) + grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 + // @update + // def comb_grants_int(): + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.grants_int[i] @= s.reqs_int[i] + // else: + // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] + + always_comb begin : comb_grants_int + for ( int unsigned i = 1'd0; i < 5'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + grants_int[4'(i)] = reqs_int[4'(i)]; + end + else + grants_int[4'(i)] = ( ~kills[5'(i)] ) & reqs_int[4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 + // @update + // def comb_kills(): + // s.kills[0] @= 1 + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.kills[i+1] @= s.reqs_int[i] + // else: + // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) + + always_comb begin : comb_kills + kills[5'd0] = 1'd1; + for ( int unsigned i = 1'd0; i < 5'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + kills[5'(i) + 5'd1] = reqs_int[4'(i)]; + end + else + kills[5'(i) + 5'd1] = kills[5'(i)] | ( ( ~kills[5'(i)] ) & reqs_int[4'(i)] ); + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 + // @update + // def comb_priority_en(): + // s.priority_en @= ( s.grants != 0 ) & s.en + + always_comb begin : comb_priority_en + priority_en = ( grants != 8'd0 ) & en; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 + // @update + // def comb_priority_int(): + // s.priority_int[ 0:nreqs ] @= s.priority_reg.out + // s.priority_int[nreqs:nreqsX2] @= 0 + + always_comb begin : comb_priority_int + priority_int[4'd7:4'd0] = priority_reg__out; + priority_int[4'd15:4'( __const__nreqs_at_comb_priority_int )] = 8'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 + // @update + // def comb_reqs_int(): + // s.reqs_int [ 0:nreqs ] @= s.reqs + // s.reqs_int [nreqs:nreqsX2] @= s.reqs + + always_comb begin : comb_reqs_int + reqs_int[4'd7:4'd0] = reqs; + reqs_int[4'd15:4'( __const__nreqs_at_comb_reqs_int )] = reqs; + end + + assign priority_reg__clk = clk; + assign priority_reg__reset = reset; + assign priority_reg__en = priority_en; + assign priority_reg__in_[7:1] = grants[6:0]; + assign priority_reg__in_[0:0] = grants[7:7]; + +endmodule + + +// PyMTL Component Encoder Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py + +module Encoder__in_nbits_8__out_nbits_3 +( + input logic [0:0] clk , + input logic [7:0] in_ , + output logic [2:0] out , + input logic [0:0] reset +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 + // @update + // def encode(): + // s.out @= 0 + // for i in range( s.in_nbits ): + // if s.in_[i]: + // s.out @= i + + always_comb begin : encode + out = 3'd0; + for ( int unsigned i = 1'd0; i < 4'd8; i += 1'd1 ) + if ( in_[3'(i)] ) begin + out = 3'(i); + end + end + +endmodule + + +// PyMTL Component Mux Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_8 +( + input logic [0:0] clk , + input MemAccessPacket_8_3_128__43c148781d2f2a57 in_ [0:7], + output MemAccessPacket_8_3_128__43c148781d2f2a57 out , + input logic [0:0] reset , + input logic [2:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component SwitchUnitRTL Definition +// Full name: SwitchUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_inports_8 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py + +module SwitchUnitRTL__10097976fa423359 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg [0:7] , + output logic [0:0] recv__rdy [0:7] , + input logic [0:0] recv__val [0:7] , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [3:0] __const__num_inports_at_up_get_en = 4'd8; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [7:0] arbiter__grants; + logic [7:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_8 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [7:0] encoder__in_; + logic [2:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_8__out_nbits_3 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + MemAccessPacket_8_3_128__43c148781d2f2a57 mux__in_ [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 mux__out; + logic [0:0] mux__reset; + logic [2:0] mux__sel; + + Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_8 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 + // @update + // def up_get_en(): + // for i in range( num_inports ): + // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) + + always_comb begin : up_get_en + for ( int unsigned i = 1'd0; i < 4'( __const__num_inports_at_up_get_en ); i += 1'd1 ) + recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 + // @update + // def up_send_val(): + // s.send.val @= s.arbiter.grants > 0 + + always_comb begin : up_send_val + send__val = arbiter__grants > 8'd0; + end + + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign arbiter__en = 1'd1; + assign mux__clk = clk; + assign mux__reset = reset; + assign send__msg = mux__out; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign encoder__in_ = arbiter__grants; + assign mux__sel = encoder__out; + assign arbiter__reqs[0:0] = recv__val[0]; + assign mux__in_[0] = recv__msg[0]; + assign arbiter__reqs[1:1] = recv__val[1]; + assign mux__in_[1] = recv__msg[1]; + assign arbiter__reqs[2:2] = recv__val[2]; + assign mux__in_[2] = recv__msg[2]; + assign arbiter__reqs[3:3] = recv__val[3]; + assign mux__in_[3] = recv__msg[3]; + assign arbiter__reqs[4:4] = recv__val[4]; + assign mux__in_[4] = recv__msg[4]; + assign arbiter__reqs[5:5] = recv__val[5]; + assign mux__in_[5] = recv__msg[5]; + assign arbiter__reqs[6:6] = recv__val[6]; + assign mux__in_[6] = recv__msg[6]; + assign arbiter__reqs[7:7] = recv__val[7]; + assign mux__in_[7] = recv__msg[7]; + +endmodule + + +// PyMTL Component XbarBypassQueueRTL Definition +// Full name: XbarBypassQueueRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_inports_8__num_outports_3__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarBypassQueueRTL.py + +module XbarBypassQueueRTL__045133ee283ca701 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg [0:7] , + output logic [0:0] recv__rdy [0:7] , + input logic [0:0] recv__val [0:7] , + output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg [0:2] , + input logic [0:0] send__rdy [0:2] , + output logic [0:0] send__val [0:2] +); + //------------------------------------------------------------- + // Component input_units[0:7] + //------------------------------------------------------------- + + logic [0:0] input_units__clk [0:7]; + logic [0:0] input_units__reset [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 input_units__recv__msg [0:7]; + logic [0:0] input_units__recv__rdy [0:7]; + logic [0:0] input_units__recv__val [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 input_units__send__msg [0:7]; + logic [0:0] input_units__send__rdy [0:7]; + logic [0:0] input_units__send__val [0:7]; + + InputUnitRTL__1864e8652261553b input_units__0 + ( + .clk( input_units__clk[0] ), + .reset( input_units__reset[0] ), + .recv__msg( input_units__recv__msg[0] ), + .recv__rdy( input_units__recv__rdy[0] ), + .recv__val( input_units__recv__val[0] ), + .send__msg( input_units__send__msg[0] ), + .send__rdy( input_units__send__rdy[0] ), + .send__val( input_units__send__val[0] ) + ); + + InputUnitRTL__1864e8652261553b input_units__1 + ( + .clk( input_units__clk[1] ), + .reset( input_units__reset[1] ), + .recv__msg( input_units__recv__msg[1] ), + .recv__rdy( input_units__recv__rdy[1] ), + .recv__val( input_units__recv__val[1] ), + .send__msg( input_units__send__msg[1] ), + .send__rdy( input_units__send__rdy[1] ), + .send__val( input_units__send__val[1] ) + ); + + InputUnitRTL__1864e8652261553b input_units__2 + ( + .clk( input_units__clk[2] ), + .reset( input_units__reset[2] ), + .recv__msg( input_units__recv__msg[2] ), + .recv__rdy( input_units__recv__rdy[2] ), + .recv__val( input_units__recv__val[2] ), + .send__msg( input_units__send__msg[2] ), + .send__rdy( input_units__send__rdy[2] ), + .send__val( input_units__send__val[2] ) + ); + + InputUnitRTL__1864e8652261553b input_units__3 + ( + .clk( input_units__clk[3] ), + .reset( input_units__reset[3] ), + .recv__msg( input_units__recv__msg[3] ), + .recv__rdy( input_units__recv__rdy[3] ), + .recv__val( input_units__recv__val[3] ), + .send__msg( input_units__send__msg[3] ), + .send__rdy( input_units__send__rdy[3] ), + .send__val( input_units__send__val[3] ) + ); + + InputUnitRTL__1864e8652261553b input_units__4 + ( + .clk( input_units__clk[4] ), + .reset( input_units__reset[4] ), + .recv__msg( input_units__recv__msg[4] ), + .recv__rdy( input_units__recv__rdy[4] ), + .recv__val( input_units__recv__val[4] ), + .send__msg( input_units__send__msg[4] ), + .send__rdy( input_units__send__rdy[4] ), + .send__val( input_units__send__val[4] ) + ); + + InputUnitRTL__1864e8652261553b input_units__5 + ( + .clk( input_units__clk[5] ), + .reset( input_units__reset[5] ), + .recv__msg( input_units__recv__msg[5] ), + .recv__rdy( input_units__recv__rdy[5] ), + .recv__val( input_units__recv__val[5] ), + .send__msg( input_units__send__msg[5] ), + .send__rdy( input_units__send__rdy[5] ), + .send__val( input_units__send__val[5] ) + ); + + InputUnitRTL__1864e8652261553b input_units__6 + ( + .clk( input_units__clk[6] ), + .reset( input_units__reset[6] ), + .recv__msg( input_units__recv__msg[6] ), + .recv__rdy( input_units__recv__rdy[6] ), + .recv__val( input_units__recv__val[6] ), + .send__msg( input_units__send__msg[6] ), + .send__rdy( input_units__send__rdy[6] ), + .send__val( input_units__send__val[6] ) + ); + + InputUnitRTL__1864e8652261553b input_units__7 + ( + .clk( input_units__clk[7] ), + .reset( input_units__reset[7] ), + .recv__msg( input_units__recv__msg[7] ), + .recv__rdy( input_units__recv__rdy[7] ), + .recv__val( input_units__recv__val[7] ), + .send__msg( input_units__send__msg[7] ), + .send__rdy( input_units__send__rdy[7] ), + .send__val( input_units__send__val[7] ) + ); + + //------------------------------------------------------------- + // End of component input_units[0:7] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component output_units[0:2] + //------------------------------------------------------------- + + logic [0:0] output_units__clk [0:2]; + logic [0:0] output_units__reset [0:2]; + MemAccessPacket_8_3_128__43c148781d2f2a57 output_units__recv__msg [0:2]; + logic [0:0] output_units__recv__rdy [0:2]; + logic [0:0] output_units__recv__val [0:2]; + MemAccessPacket_8_3_128__43c148781d2f2a57 output_units__send__msg [0:2]; + logic [0:0] output_units__send__rdy [0:2]; + logic [0:0] output_units__send__val [0:2]; + + OutputUnitRTL__a3f8631b75bafad0 output_units__0 + ( + .clk( output_units__clk[0] ), + .reset( output_units__reset[0] ), + .recv__msg( output_units__recv__msg[0] ), + .recv__rdy( output_units__recv__rdy[0] ), + .recv__val( output_units__recv__val[0] ), + .send__msg( output_units__send__msg[0] ), + .send__rdy( output_units__send__rdy[0] ), + .send__val( output_units__send__val[0] ) + ); + + OutputUnitRTL__a3f8631b75bafad0 output_units__1 + ( + .clk( output_units__clk[1] ), + .reset( output_units__reset[1] ), + .recv__msg( output_units__recv__msg[1] ), + .recv__rdy( output_units__recv__rdy[1] ), + .recv__val( output_units__recv__val[1] ), + .send__msg( output_units__send__msg[1] ), + .send__rdy( output_units__send__rdy[1] ), + .send__val( output_units__send__val[1] ) + ); + + OutputUnitRTL__a3f8631b75bafad0 output_units__2 + ( + .clk( output_units__clk[2] ), + .reset( output_units__reset[2] ), + .recv__msg( output_units__recv__msg[2] ), + .recv__rdy( output_units__recv__rdy[2] ), + .recv__val( output_units__recv__val[2] ), + .send__msg( output_units__send__msg[2] ), + .send__rdy( output_units__send__rdy[2] ), + .send__val( output_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component output_units[0:2] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component route_units[0:7] + //------------------------------------------------------------- + + logic [0:0] route_units__clk [0:7]; + logic [0:0] route_units__reset [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 route_units__recv__msg [0:7]; + logic [0:0] route_units__recv__rdy [0:7]; + logic [0:0] route_units__recv__val [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 route_units__send__msg [0:7][0:2]; + logic [0:0] route_units__send__rdy [0:7][0:2]; + logic [0:0] route_units__send__val [0:7][0:2]; + + XbarRouteUnitRTL__32c7752a7c15587d route_units__0 + ( + .clk( route_units__clk[0] ), + .reset( route_units__reset[0] ), + .recv__msg( route_units__recv__msg[0] ), + .recv__rdy( route_units__recv__rdy[0] ), + .recv__val( route_units__recv__val[0] ), + .send__msg( route_units__send__msg[0] ), + .send__rdy( route_units__send__rdy[0] ), + .send__val( route_units__send__val[0] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__1 + ( + .clk( route_units__clk[1] ), + .reset( route_units__reset[1] ), + .recv__msg( route_units__recv__msg[1] ), + .recv__rdy( route_units__recv__rdy[1] ), + .recv__val( route_units__recv__val[1] ), + .send__msg( route_units__send__msg[1] ), + .send__rdy( route_units__send__rdy[1] ), + .send__val( route_units__send__val[1] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__2 + ( + .clk( route_units__clk[2] ), + .reset( route_units__reset[2] ), + .recv__msg( route_units__recv__msg[2] ), + .recv__rdy( route_units__recv__rdy[2] ), + .recv__val( route_units__recv__val[2] ), + .send__msg( route_units__send__msg[2] ), + .send__rdy( route_units__send__rdy[2] ), + .send__val( route_units__send__val[2] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__3 + ( + .clk( route_units__clk[3] ), + .reset( route_units__reset[3] ), + .recv__msg( route_units__recv__msg[3] ), + .recv__rdy( route_units__recv__rdy[3] ), + .recv__val( route_units__recv__val[3] ), + .send__msg( route_units__send__msg[3] ), + .send__rdy( route_units__send__rdy[3] ), + .send__val( route_units__send__val[3] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__4 + ( + .clk( route_units__clk[4] ), + .reset( route_units__reset[4] ), + .recv__msg( route_units__recv__msg[4] ), + .recv__rdy( route_units__recv__rdy[4] ), + .recv__val( route_units__recv__val[4] ), + .send__msg( route_units__send__msg[4] ), + .send__rdy( route_units__send__rdy[4] ), + .send__val( route_units__send__val[4] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__5 + ( + .clk( route_units__clk[5] ), + .reset( route_units__reset[5] ), + .recv__msg( route_units__recv__msg[5] ), + .recv__rdy( route_units__recv__rdy[5] ), + .recv__val( route_units__recv__val[5] ), + .send__msg( route_units__send__msg[5] ), + .send__rdy( route_units__send__rdy[5] ), + .send__val( route_units__send__val[5] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__6 + ( + .clk( route_units__clk[6] ), + .reset( route_units__reset[6] ), + .recv__msg( route_units__recv__msg[6] ), + .recv__rdy( route_units__recv__rdy[6] ), + .recv__val( route_units__recv__val[6] ), + .send__msg( route_units__send__msg[6] ), + .send__rdy( route_units__send__rdy[6] ), + .send__val( route_units__send__val[6] ) + ); + + XbarRouteUnitRTL__32c7752a7c15587d route_units__7 + ( + .clk( route_units__clk[7] ), + .reset( route_units__reset[7] ), + .recv__msg( route_units__recv__msg[7] ), + .recv__rdy( route_units__recv__rdy[7] ), + .recv__val( route_units__recv__val[7] ), + .send__msg( route_units__send__msg[7] ), + .send__rdy( route_units__send__rdy[7] ), + .send__val( route_units__send__val[7] ) + ); + + //------------------------------------------------------------- + // End of component route_units[0:7] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component switch_units[0:2] + //------------------------------------------------------------- + + logic [0:0] switch_units__clk [0:2]; + logic [0:0] switch_units__reset [0:2]; + MemAccessPacket_8_3_128__43c148781d2f2a57 switch_units__recv__msg [0:2][0:7]; + logic [0:0] switch_units__recv__rdy [0:2][0:7]; + logic [0:0] switch_units__recv__val [0:2][0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 switch_units__send__msg [0:2]; + logic [0:0] switch_units__send__rdy [0:2]; + logic [0:0] switch_units__send__val [0:2]; + + SwitchUnitRTL__10097976fa423359 switch_units__0 + ( + .clk( switch_units__clk[0] ), + .reset( switch_units__reset[0] ), + .recv__msg( switch_units__recv__msg[0] ), + .recv__rdy( switch_units__recv__rdy[0] ), + .recv__val( switch_units__recv__val[0] ), + .send__msg( switch_units__send__msg[0] ), + .send__rdy( switch_units__send__rdy[0] ), + .send__val( switch_units__send__val[0] ) + ); + + SwitchUnitRTL__10097976fa423359 switch_units__1 + ( + .clk( switch_units__clk[1] ), + .reset( switch_units__reset[1] ), + .recv__msg( switch_units__recv__msg[1] ), + .recv__rdy( switch_units__recv__rdy[1] ), + .recv__val( switch_units__recv__val[1] ), + .send__msg( switch_units__send__msg[1] ), + .send__rdy( switch_units__send__rdy[1] ), + .send__val( switch_units__send__val[1] ) + ); + + SwitchUnitRTL__10097976fa423359 switch_units__2 + ( + .clk( switch_units__clk[2] ), + .reset( switch_units__reset[2] ), + .recv__msg( switch_units__recv__msg[2] ), + .recv__rdy( switch_units__recv__rdy[2] ), + .recv__val( switch_units__recv__val[2] ), + .send__msg( switch_units__send__msg[2] ), + .send__rdy( switch_units__send__rdy[2] ), + .send__val( switch_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component switch_units[0:2] + //------------------------------------------------------------- + + assign input_units__clk[0] = clk; + assign input_units__reset[0] = reset; + assign input_units__clk[1] = clk; + assign input_units__reset[1] = reset; + assign input_units__clk[2] = clk; + assign input_units__reset[2] = reset; + assign input_units__clk[3] = clk; + assign input_units__reset[3] = reset; + assign input_units__clk[4] = clk; + assign input_units__reset[4] = reset; + assign input_units__clk[5] = clk; + assign input_units__reset[5] = reset; + assign input_units__clk[6] = clk; + assign input_units__reset[6] = reset; + assign input_units__clk[7] = clk; + assign input_units__reset[7] = reset; + assign route_units__clk[0] = clk; + assign route_units__reset[0] = reset; + assign route_units__clk[1] = clk; + assign route_units__reset[1] = reset; + assign route_units__clk[2] = clk; + assign route_units__reset[2] = reset; + assign route_units__clk[3] = clk; + assign route_units__reset[3] = reset; + assign route_units__clk[4] = clk; + assign route_units__reset[4] = reset; + assign route_units__clk[5] = clk; + assign route_units__reset[5] = reset; + assign route_units__clk[6] = clk; + assign route_units__reset[6] = reset; + assign route_units__clk[7] = clk; + assign route_units__reset[7] = reset; + assign switch_units__clk[0] = clk; + assign switch_units__reset[0] = reset; + assign switch_units__clk[1] = clk; + assign switch_units__reset[1] = reset; + assign switch_units__clk[2] = clk; + assign switch_units__reset[2] = reset; + assign output_units__clk[0] = clk; + assign output_units__reset[0] = reset; + assign output_units__clk[1] = clk; + assign output_units__reset[1] = reset; + assign output_units__clk[2] = clk; + assign output_units__reset[2] = reset; + assign input_units__recv__msg[0] = recv__msg[0]; + assign recv__rdy[0] = input_units__recv__rdy[0]; + assign input_units__recv__val[0] = recv__val[0]; + assign route_units__recv__msg[0] = input_units__send__msg[0]; + assign input_units__send__rdy[0] = route_units__recv__rdy[0]; + assign route_units__recv__val[0] = input_units__send__val[0]; + assign input_units__recv__msg[1] = recv__msg[1]; + assign recv__rdy[1] = input_units__recv__rdy[1]; + assign input_units__recv__val[1] = recv__val[1]; + assign route_units__recv__msg[1] = input_units__send__msg[1]; + assign input_units__send__rdy[1] = route_units__recv__rdy[1]; + assign route_units__recv__val[1] = input_units__send__val[1]; + assign input_units__recv__msg[2] = recv__msg[2]; + assign recv__rdy[2] = input_units__recv__rdy[2]; + assign input_units__recv__val[2] = recv__val[2]; + assign route_units__recv__msg[2] = input_units__send__msg[2]; + assign input_units__send__rdy[2] = route_units__recv__rdy[2]; + assign route_units__recv__val[2] = input_units__send__val[2]; + assign input_units__recv__msg[3] = recv__msg[3]; + assign recv__rdy[3] = input_units__recv__rdy[3]; + assign input_units__recv__val[3] = recv__val[3]; + assign route_units__recv__msg[3] = input_units__send__msg[3]; + assign input_units__send__rdy[3] = route_units__recv__rdy[3]; + assign route_units__recv__val[3] = input_units__send__val[3]; + assign input_units__recv__msg[4] = recv__msg[4]; + assign recv__rdy[4] = input_units__recv__rdy[4]; + assign input_units__recv__val[4] = recv__val[4]; + assign route_units__recv__msg[4] = input_units__send__msg[4]; + assign input_units__send__rdy[4] = route_units__recv__rdy[4]; + assign route_units__recv__val[4] = input_units__send__val[4]; + assign input_units__recv__msg[5] = recv__msg[5]; + assign recv__rdy[5] = input_units__recv__rdy[5]; + assign input_units__recv__val[5] = recv__val[5]; + assign route_units__recv__msg[5] = input_units__send__msg[5]; + assign input_units__send__rdy[5] = route_units__recv__rdy[5]; + assign route_units__recv__val[5] = input_units__send__val[5]; + assign input_units__recv__msg[6] = recv__msg[6]; + assign recv__rdy[6] = input_units__recv__rdy[6]; + assign input_units__recv__val[6] = recv__val[6]; + assign route_units__recv__msg[6] = input_units__send__msg[6]; + assign input_units__send__rdy[6] = route_units__recv__rdy[6]; + assign route_units__recv__val[6] = input_units__send__val[6]; + assign input_units__recv__msg[7] = recv__msg[7]; + assign recv__rdy[7] = input_units__recv__rdy[7]; + assign input_units__recv__val[7] = recv__val[7]; + assign route_units__recv__msg[7] = input_units__send__msg[7]; + assign input_units__send__rdy[7] = route_units__recv__rdy[7]; + assign route_units__recv__val[7] = input_units__send__val[7]; + assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; + assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; + assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; + assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; + assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; + assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; + assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; + assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; + assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; + assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; + assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; + assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; + assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; + assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; + assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; + assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; + assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; + assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; + assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; + assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; + assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; + assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; + assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; + assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; + assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; + assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; + assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; + assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; + assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; + assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; + assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; + assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; + assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; + assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; + assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; + assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; + assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; + assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; + assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; + assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; + assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; + assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; + assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; + assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; + assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; + assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; + assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; + assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; + assign switch_units__recv__msg[1][5] = route_units__send__msg[5][1]; + assign route_units__send__rdy[5][1] = switch_units__recv__rdy[1][5]; + assign switch_units__recv__val[1][5] = route_units__send__val[5][1]; + assign switch_units__recv__msg[2][5] = route_units__send__msg[5][2]; + assign route_units__send__rdy[5][2] = switch_units__recv__rdy[2][5]; + assign switch_units__recv__val[2][5] = route_units__send__val[5][2]; + assign switch_units__recv__msg[0][6] = route_units__send__msg[6][0]; + assign route_units__send__rdy[6][0] = switch_units__recv__rdy[0][6]; + assign switch_units__recv__val[0][6] = route_units__send__val[6][0]; + assign switch_units__recv__msg[1][6] = route_units__send__msg[6][1]; + assign route_units__send__rdy[6][1] = switch_units__recv__rdy[1][6]; + assign switch_units__recv__val[1][6] = route_units__send__val[6][1]; + assign switch_units__recv__msg[2][6] = route_units__send__msg[6][2]; + assign route_units__send__rdy[6][2] = switch_units__recv__rdy[2][6]; + assign switch_units__recv__val[2][6] = route_units__send__val[6][2]; + assign switch_units__recv__msg[0][7] = route_units__send__msg[7][0]; + assign route_units__send__rdy[7][0] = switch_units__recv__rdy[0][7]; + assign switch_units__recv__val[0][7] = route_units__send__val[7][0]; + assign switch_units__recv__msg[1][7] = route_units__send__msg[7][1]; + assign route_units__send__rdy[7][1] = switch_units__recv__rdy[1][7]; + assign switch_units__recv__val[1][7] = route_units__send__val[7][1]; + assign switch_units__recv__msg[2][7] = route_units__send__msg[7][2]; + assign route_units__send__rdy[7][2] = switch_units__recv__rdy[2][7]; + assign switch_units__recv__val[2][7] = route_units__send__val[7][2]; + assign output_units__recv__msg[0] = switch_units__send__msg[0]; + assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; + assign output_units__recv__val[0] = switch_units__send__val[0]; + assign send__msg[0] = output_units__send__msg[0]; + assign output_units__send__rdy[0] = send__rdy[0]; + assign send__val[0] = output_units__send__val[0]; + assign output_units__recv__msg[1] = switch_units__send__msg[1]; + assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; + assign output_units__recv__val[1] = switch_units__send__val[1]; + assign send__msg[1] = output_units__send__msg[1]; + assign output_units__send__rdy[1] = send__rdy[1]; + assign send__val[1] = output_units__send__val[1]; + assign output_units__recv__msg[2] = switch_units__send__msg[2]; + assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; + assign output_units__recv__val[2] = switch_units__send__val[2]; + assign send__msg[2] = output_units__send__msg[2]; + assign output_units__send__rdy[2] = send__rdy[2]; + assign send__val[2] = output_units__send__val[2]; + +endmodule + + +// PyMTL Component Mux Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_2 +( + input logic [0:0] clk , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 in_ [0:1], + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 out , + input logic [0:0] reset , + input logic [0:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__3969b2773d1d2f8e +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component BypassQueueDpathRTL Definition +// Full name: BypassQueueDpathRTL__EntryType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueDpathRTL__60d0395b9f70f062 +( + input logic [0:0] clk , + input logic [0:0] mux_sel , + input logic [0:0] raddr , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv_msg , + input logic [0:0] reset , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__in_ [0:1]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__out; + logic [0:0] mux__reset; + logic [0:0] mux__sel; + + Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_2 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__3969b2773d1d2f8e rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + assign mux__clk = clk; + assign mux__reset = reset; + assign mux__sel = mux_sel; + assign mux__in_[0] = rf__rdata[0]; + assign mux__in_[1] = recv_msg; + assign send_msg = mux__out; + +endmodule + + +// PyMTL Component BypassQueueRTL Definition +// Full name: BypassQueueRTL__EntryType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module BypassQueueRTL__60d0395b9f70f062 +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__mux_sel; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + BypassQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .mux_sel( ctrl__mux_sel ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__mux_sel; + logic [0:0] dpath__raddr; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 dpath__recv_msg; + logic [0:0] dpath__reset; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + BypassQueueDpathRTL__60d0395b9f70f062 dpath + ( + .clk( dpath__clk ), + .mux_sel( dpath__mux_sel ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign dpath__mux_sel = ctrl__mux_sel; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign count = ctrl__count; + assign dpath__recv_msg = recv__msg; + assign send__msg = dpath__send_msg; + +endmodule + + +// PyMTL Component InputUnitRTL Definition +// Full name: InputUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__QueueType_BypassQueueRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py + +module InputUnitRTL__cff279ef5009e7c6 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queue + //------------------------------------------------------------- + + logic [0:0] queue__clk; + logic [1:0] queue__count; + logic [0:0] queue__reset; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 queue__recv__msg; + logic [0:0] queue__recv__rdy; + logic [0:0] queue__recv__val; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 queue__send__msg; + logic [0:0] queue__send__rdy; + logic [0:0] queue__send__val; + + BypassQueueRTL__60d0395b9f70f062 queue + ( + .clk( queue__clk ), + .count( queue__count ), + .reset( queue__reset ), + .recv__msg( queue__recv__msg ), + .recv__rdy( queue__recv__rdy ), + .recv__val( queue__recv__val ), + .send__msg( queue__send__msg ), + .send__rdy( queue__send__rdy ), + .send__val( queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component queue + //------------------------------------------------------------- + + assign queue__clk = clk; + assign queue__reset = reset; + assign queue__recv__msg = recv__msg; + assign recv__rdy = queue__recv__rdy; + assign queue__recv__val = recv__val; + assign send__msg = queue__send__msg; + assign queue__send__rdy = send__rdy; + assign send__val = queue__send__val; + +endmodule + + +// PyMTL Component OutputUnitRTL Definition +// Full name: OutputUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__QueueType_None +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py + +module OutputUnitRTL__e96d78a3d0126314 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + assign send__msg = recv__msg; + assign recv__rdy = send__rdy; + assign send__val = recv__val; + +endmodule + + +// PyMTL Component XbarRouteUnitRTL Definition +// Full name: XbarRouteUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_outports_8 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py + +module XbarRouteUnitRTL__c063f4910bbc0b50 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg [0:7] , + input logic [0:0] send__rdy [0:7] , + output logic [0:0] send__val [0:7] +); + localparam logic [3:0] __const__num_outports_at_up_ru_routing = 4'd8; + logic [2:0] out_dir; + logic [7:0] send_val; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 + // @update + // def up_ru_recv_rdy(): + // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 + + always_comb begin : up_ru_recv_rdy + recv__rdy = send__rdy[out_dir] > 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 + // @update + // def up_ru_routing(): + // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) + // + // for i in range( num_outports ): + // s.send[i].val @= b1(0) + // + // if s.recv.val: + // s.send[ s.out_dir ].val @= b1(1) + + always_comb begin : up_ru_routing + out_dir = recv__msg.dst; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) + send__val[3'(i)] = 1'd0; + if ( recv__val ) begin + send__val[out_dir] = 1'd1; + end + end + + assign send__msg[0] = recv__msg; + assign send_val[0:0] = send__val[0]; + assign send__msg[1] = recv__msg; + assign send_val[1:1] = send__val[1]; + assign send__msg[2] = recv__msg; + assign send_val[2:2] = send__val[2]; + assign send__msg[3] = recv__msg; + assign send_val[3:3] = send__val[3]; + assign send__msg[4] = recv__msg; + assign send_val[4:4] = send__val[4]; + assign send__msg[5] = recv__msg; + assign send_val[5:5] = send__val[5]; + assign send__msg[6] = recv__msg; + assign send_val[6:6] = send__val[6]; + assign send__msg[7] = recv__msg; + assign send_val[7:7] = send__val[7]; + +endmodule + + +// PyMTL Component RegEnRst Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py + +module RegEnRst__Type_Bits3__reset_value_1 +( + input logic [0:0] clk , + input logic [0:0] en , + input logic [2:0] in_ , + output logic [2:0] out , + input logic [0:0] reset +); + localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 + // @update_ff + // def up_regenrst(): + // if s.reset: s.out <<= reset_value + // elif s.en: s.out <<= s.in_ + + always_ff @(posedge clk) begin : up_regenrst + if ( reset ) begin + out <= 3'( __const__reset_value_at_up_regenrst ); + end + else if ( en ) begin + out <= in_; + end + end + +endmodule + + +// PyMTL Component RoundRobinArbiterEn Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py + +module RoundRobinArbiterEn__nreqs_3 +( + input logic [0:0] clk , + input logic [0:0] en , + output logic [2:0] grants , + input logic [2:0] reqs , + input logic [0:0] reset +); + localparam logic [1:0] __const__nreqs_at_comb_reqs_int = 2'd3; + localparam logic [2:0] __const__nreqsX2_at_comb_reqs_int = 3'd6; + localparam logic [1:0] __const__nreqs_at_comb_grants = 2'd3; + localparam logic [1:0] __const__nreqs_at_comb_priority_int = 2'd3; + localparam logic [2:0] __const__nreqsX2_at_comb_priority_int = 3'd6; + localparam logic [2:0] __const__nreqsX2_at_comb_kills = 3'd6; + localparam logic [2:0] __const__nreqsX2_at_comb_grants_int = 3'd6; + logic [5:0] grants_int; + logic [6:0] kills; + logic [0:0] priority_en; + logic [5:0] priority_int; + logic [5:0] reqs_int; + //------------------------------------------------------------- + // Component priority_reg + //------------------------------------------------------------- + + logic [0:0] priority_reg__clk; + logic [0:0] priority_reg__en; + logic [2:0] priority_reg__in_; + logic [2:0] priority_reg__out; + logic [0:0] priority_reg__reset; + + RegEnRst__Type_Bits3__reset_value_1 priority_reg + ( + .clk( priority_reg__clk ), + .en( priority_reg__en ), + .in_( priority_reg__in_ ), + .out( priority_reg__out ), + .reset( priority_reg__reset ) + ); + + //------------------------------------------------------------- + // End of component priority_reg + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 + // @update + // def comb_grants(): + // for i in range( nreqs ): + // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] + + always_comb begin : comb_grants + for ( int unsigned i = 1'd0; i < 2'( __const__nreqs_at_comb_grants ); i += 1'd1 ) + grants[2'(i)] = grants_int[3'(i)] | grants_int[3'( __const__nreqs_at_comb_grants ) + 3'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 + // @update + // def comb_grants_int(): + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.grants_int[i] @= s.reqs_int[i] + // else: + // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] + + always_comb begin : comb_grants_int + for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) + if ( priority_int[3'(i)] ) begin + grants_int[3'(i)] = reqs_int[3'(i)]; + end + else + grants_int[3'(i)] = ( ~kills[3'(i)] ) & reqs_int[3'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 + // @update + // def comb_kills(): + // s.kills[0] @= 1 + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.kills[i+1] @= s.reqs_int[i] + // else: + // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) + + always_comb begin : comb_kills + kills[3'd0] = 1'd1; + for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) + if ( priority_int[3'(i)] ) begin + kills[3'(i) + 3'd1] = reqs_int[3'(i)]; + end + else + kills[3'(i) + 3'd1] = kills[3'(i)] | ( ( ~kills[3'(i)] ) & reqs_int[3'(i)] ); + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 + // @update + // def comb_priority_en(): + // s.priority_en @= ( s.grants != 0 ) & s.en + + always_comb begin : comb_priority_en + priority_en = ( grants != 3'd0 ) & en; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 + // @update + // def comb_priority_int(): + // s.priority_int[ 0:nreqs ] @= s.priority_reg.out + // s.priority_int[nreqs:nreqsX2] @= 0 + + always_comb begin : comb_priority_int + priority_int[3'd2:3'd0] = priority_reg__out; + priority_int[3'd5:3'( __const__nreqs_at_comb_priority_int )] = 3'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 + // @update + // def comb_reqs_int(): + // s.reqs_int [ 0:nreqs ] @= s.reqs + // s.reqs_int [nreqs:nreqsX2] @= s.reqs + + always_comb begin : comb_reqs_int + reqs_int[3'd2:3'd0] = reqs; + reqs_int[3'd5:3'( __const__nreqs_at_comb_reqs_int )] = reqs; + end + + assign priority_reg__clk = clk; + assign priority_reg__reset = reset; + assign priority_reg__en = priority_en; + assign priority_reg__in_[2:1] = grants[1:0]; + assign priority_reg__in_[0:0] = grants[2:2]; + +endmodule + + +// PyMTL Component Encoder Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py + +module Encoder__in_nbits_3__out_nbits_2 +( + input logic [0:0] clk , + input logic [2:0] in_ , + output logic [1:0] out , + input logic [0:0] reset +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 + // @update + // def encode(): + // s.out @= 0 + // for i in range( s.in_nbits ): + // if s.in_[i]: + // s.out @= i + + always_comb begin : encode + out = 2'd0; + for ( int unsigned i = 1'd0; i < 2'd3; i += 1'd1 ) + if ( in_[2'(i)] ) begin + out = 2'(i); + end + end + +endmodule + + +// PyMTL Component Mux Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_3 +( + input logic [0:0] clk , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 in_ [0:2], + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 out , + input logic [0:0] reset , + input logic [1:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component SwitchUnitRTL Definition +// Full name: SwitchUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_inports_3 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py + +module SwitchUnitRTL__4cc70db240bb572a +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg [0:2] , + output logic [0:0] recv__rdy [0:2] , + input logic [0:0] recv__val [0:2] , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [1:0] __const__num_inports_at_up_get_en = 2'd3; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [2:0] arbiter__grants; + logic [2:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_3 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [2:0] encoder__in_; + logic [1:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_3__out_nbits_2 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__in_ [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__out; + logic [0:0] mux__reset; + logic [1:0] mux__sel; + + Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_3 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 + // @update + // def up_get_en(): + // for i in range( num_inports ): + // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) + + always_comb begin : up_get_en + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_up_get_en ); i += 1'd1 ) + recv__rdy[2'(i)] = send__rdy & ( mux__sel == 2'(i) ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 + // @update + // def up_send_val(): + // s.send.val @= s.arbiter.grants > 0 + + always_comb begin : up_send_val + send__val = arbiter__grants > 3'd0; + end + + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign arbiter__en = 1'd1; + assign mux__clk = clk; + assign mux__reset = reset; + assign send__msg = mux__out; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign encoder__in_ = arbiter__grants; + assign mux__sel = encoder__out; + assign arbiter__reqs[0:0] = recv__val[0]; + assign mux__in_[0] = recv__msg[0]; + assign arbiter__reqs[1:1] = recv__val[1]; + assign mux__in_[1] = recv__msg[1]; + assign arbiter__reqs[2:2] = recv__val[2]; + assign mux__in_[2] = recv__msg[2]; + +endmodule + + +// PyMTL Component XbarBypassQueueRTL Definition +// Full name: XbarBypassQueueRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_inports_3__num_outports_8__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarBypassQueueRTL.py + +module XbarBypassQueueRTL__510da12df6787984 +( + input logic [0:0] clk , + input logic [0:0] reset , + input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg [0:2] , + output logic [0:0] recv__rdy [0:2] , + input logic [0:0] recv__val [0:2] , + output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg [0:7] , + input logic [0:0] send__rdy [0:7] , + output logic [0:0] send__val [0:7] +); + //------------------------------------------------------------- + // Component input_units[0:2] + //------------------------------------------------------------- + + logic [0:0] input_units__clk [0:2]; + logic [0:0] input_units__reset [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 input_units__recv__msg [0:2]; + logic [0:0] input_units__recv__rdy [0:2]; + logic [0:0] input_units__recv__val [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 input_units__send__msg [0:2]; + logic [0:0] input_units__send__rdy [0:2]; + logic [0:0] input_units__send__val [0:2]; + + InputUnitRTL__cff279ef5009e7c6 input_units__0 + ( + .clk( input_units__clk[0] ), + .reset( input_units__reset[0] ), + .recv__msg( input_units__recv__msg[0] ), + .recv__rdy( input_units__recv__rdy[0] ), + .recv__val( input_units__recv__val[0] ), + .send__msg( input_units__send__msg[0] ), + .send__rdy( input_units__send__rdy[0] ), + .send__val( input_units__send__val[0] ) + ); + + InputUnitRTL__cff279ef5009e7c6 input_units__1 + ( + .clk( input_units__clk[1] ), + .reset( input_units__reset[1] ), + .recv__msg( input_units__recv__msg[1] ), + .recv__rdy( input_units__recv__rdy[1] ), + .recv__val( input_units__recv__val[1] ), + .send__msg( input_units__send__msg[1] ), + .send__rdy( input_units__send__rdy[1] ), + .send__val( input_units__send__val[1] ) + ); + + InputUnitRTL__cff279ef5009e7c6 input_units__2 + ( + .clk( input_units__clk[2] ), + .reset( input_units__reset[2] ), + .recv__msg( input_units__recv__msg[2] ), + .recv__rdy( input_units__recv__rdy[2] ), + .recv__val( input_units__recv__val[2] ), + .send__msg( input_units__send__msg[2] ), + .send__rdy( input_units__send__rdy[2] ), + .send__val( input_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component input_units[0:2] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component output_units[0:7] + //------------------------------------------------------------- + + logic [0:0] output_units__clk [0:7]; + logic [0:0] output_units__reset [0:7]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 output_units__recv__msg [0:7]; + logic [0:0] output_units__recv__rdy [0:7]; + logic [0:0] output_units__recv__val [0:7]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 output_units__send__msg [0:7]; + logic [0:0] output_units__send__rdy [0:7]; + logic [0:0] output_units__send__val [0:7]; + + OutputUnitRTL__e96d78a3d0126314 output_units__0 + ( + .clk( output_units__clk[0] ), + .reset( output_units__reset[0] ), + .recv__msg( output_units__recv__msg[0] ), + .recv__rdy( output_units__recv__rdy[0] ), + .recv__val( output_units__recv__val[0] ), + .send__msg( output_units__send__msg[0] ), + .send__rdy( output_units__send__rdy[0] ), + .send__val( output_units__send__val[0] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__1 + ( + .clk( output_units__clk[1] ), + .reset( output_units__reset[1] ), + .recv__msg( output_units__recv__msg[1] ), + .recv__rdy( output_units__recv__rdy[1] ), + .recv__val( output_units__recv__val[1] ), + .send__msg( output_units__send__msg[1] ), + .send__rdy( output_units__send__rdy[1] ), + .send__val( output_units__send__val[1] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__2 + ( + .clk( output_units__clk[2] ), + .reset( output_units__reset[2] ), + .recv__msg( output_units__recv__msg[2] ), + .recv__rdy( output_units__recv__rdy[2] ), + .recv__val( output_units__recv__val[2] ), + .send__msg( output_units__send__msg[2] ), + .send__rdy( output_units__send__rdy[2] ), + .send__val( output_units__send__val[2] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__3 + ( + .clk( output_units__clk[3] ), + .reset( output_units__reset[3] ), + .recv__msg( output_units__recv__msg[3] ), + .recv__rdy( output_units__recv__rdy[3] ), + .recv__val( output_units__recv__val[3] ), + .send__msg( output_units__send__msg[3] ), + .send__rdy( output_units__send__rdy[3] ), + .send__val( output_units__send__val[3] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__4 + ( + .clk( output_units__clk[4] ), + .reset( output_units__reset[4] ), + .recv__msg( output_units__recv__msg[4] ), + .recv__rdy( output_units__recv__rdy[4] ), + .recv__val( output_units__recv__val[4] ), + .send__msg( output_units__send__msg[4] ), + .send__rdy( output_units__send__rdy[4] ), + .send__val( output_units__send__val[4] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__5 + ( + .clk( output_units__clk[5] ), + .reset( output_units__reset[5] ), + .recv__msg( output_units__recv__msg[5] ), + .recv__rdy( output_units__recv__rdy[5] ), + .recv__val( output_units__recv__val[5] ), + .send__msg( output_units__send__msg[5] ), + .send__rdy( output_units__send__rdy[5] ), + .send__val( output_units__send__val[5] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__6 + ( + .clk( output_units__clk[6] ), + .reset( output_units__reset[6] ), + .recv__msg( output_units__recv__msg[6] ), + .recv__rdy( output_units__recv__rdy[6] ), + .recv__val( output_units__recv__val[6] ), + .send__msg( output_units__send__msg[6] ), + .send__rdy( output_units__send__rdy[6] ), + .send__val( output_units__send__val[6] ) + ); + + OutputUnitRTL__e96d78a3d0126314 output_units__7 + ( + .clk( output_units__clk[7] ), + .reset( output_units__reset[7] ), + .recv__msg( output_units__recv__msg[7] ), + .recv__rdy( output_units__recv__rdy[7] ), + .recv__val( output_units__recv__val[7] ), + .send__msg( output_units__send__msg[7] ), + .send__rdy( output_units__send__rdy[7] ), + .send__val( output_units__send__val[7] ) + ); + + //------------------------------------------------------------- + // End of component output_units[0:7] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component route_units[0:2] + //------------------------------------------------------------- + + logic [0:0] route_units__clk [0:2]; + logic [0:0] route_units__reset [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 route_units__recv__msg [0:2]; + logic [0:0] route_units__recv__rdy [0:2]; + logic [0:0] route_units__recv__val [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 route_units__send__msg [0:2][0:7]; + logic [0:0] route_units__send__rdy [0:2][0:7]; + logic [0:0] route_units__send__val [0:2][0:7]; + + XbarRouteUnitRTL__c063f4910bbc0b50 route_units__0 + ( + .clk( route_units__clk[0] ), + .reset( route_units__reset[0] ), + .recv__msg( route_units__recv__msg[0] ), + .recv__rdy( route_units__recv__rdy[0] ), + .recv__val( route_units__recv__val[0] ), + .send__msg( route_units__send__msg[0] ), + .send__rdy( route_units__send__rdy[0] ), + .send__val( route_units__send__val[0] ) + ); + + XbarRouteUnitRTL__c063f4910bbc0b50 route_units__1 + ( + .clk( route_units__clk[1] ), + .reset( route_units__reset[1] ), + .recv__msg( route_units__recv__msg[1] ), + .recv__rdy( route_units__recv__rdy[1] ), + .recv__val( route_units__recv__val[1] ), + .send__msg( route_units__send__msg[1] ), + .send__rdy( route_units__send__rdy[1] ), + .send__val( route_units__send__val[1] ) + ); + + XbarRouteUnitRTL__c063f4910bbc0b50 route_units__2 + ( + .clk( route_units__clk[2] ), + .reset( route_units__reset[2] ), + .recv__msg( route_units__recv__msg[2] ), + .recv__rdy( route_units__recv__rdy[2] ), + .recv__val( route_units__recv__val[2] ), + .send__msg( route_units__send__msg[2] ), + .send__rdy( route_units__send__rdy[2] ), + .send__val( route_units__send__val[2] ) + ); + + //------------------------------------------------------------- + // End of component route_units[0:2] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component switch_units[0:7] + //------------------------------------------------------------- + + logic [0:0] switch_units__clk [0:7]; + logic [0:0] switch_units__reset [0:7]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 switch_units__recv__msg [0:7][0:2]; + logic [0:0] switch_units__recv__rdy [0:7][0:2]; + logic [0:0] switch_units__recv__val [0:7][0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 switch_units__send__msg [0:7]; + logic [0:0] switch_units__send__rdy [0:7]; + logic [0:0] switch_units__send__val [0:7]; + + SwitchUnitRTL__4cc70db240bb572a switch_units__0 + ( + .clk( switch_units__clk[0] ), + .reset( switch_units__reset[0] ), + .recv__msg( switch_units__recv__msg[0] ), + .recv__rdy( switch_units__recv__rdy[0] ), + .recv__val( switch_units__recv__val[0] ), + .send__msg( switch_units__send__msg[0] ), + .send__rdy( switch_units__send__rdy[0] ), + .send__val( switch_units__send__val[0] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__1 + ( + .clk( switch_units__clk[1] ), + .reset( switch_units__reset[1] ), + .recv__msg( switch_units__recv__msg[1] ), + .recv__rdy( switch_units__recv__rdy[1] ), + .recv__val( switch_units__recv__val[1] ), + .send__msg( switch_units__send__msg[1] ), + .send__rdy( switch_units__send__rdy[1] ), + .send__val( switch_units__send__val[1] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__2 + ( + .clk( switch_units__clk[2] ), + .reset( switch_units__reset[2] ), + .recv__msg( switch_units__recv__msg[2] ), + .recv__rdy( switch_units__recv__rdy[2] ), + .recv__val( switch_units__recv__val[2] ), + .send__msg( switch_units__send__msg[2] ), + .send__rdy( switch_units__send__rdy[2] ), + .send__val( switch_units__send__val[2] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__3 + ( + .clk( switch_units__clk[3] ), + .reset( switch_units__reset[3] ), + .recv__msg( switch_units__recv__msg[3] ), + .recv__rdy( switch_units__recv__rdy[3] ), + .recv__val( switch_units__recv__val[3] ), + .send__msg( switch_units__send__msg[3] ), + .send__rdy( switch_units__send__rdy[3] ), + .send__val( switch_units__send__val[3] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__4 + ( + .clk( switch_units__clk[4] ), + .reset( switch_units__reset[4] ), + .recv__msg( switch_units__recv__msg[4] ), + .recv__rdy( switch_units__recv__rdy[4] ), + .recv__val( switch_units__recv__val[4] ), + .send__msg( switch_units__send__msg[4] ), + .send__rdy( switch_units__send__rdy[4] ), + .send__val( switch_units__send__val[4] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__5 + ( + .clk( switch_units__clk[5] ), + .reset( switch_units__reset[5] ), + .recv__msg( switch_units__recv__msg[5] ), + .recv__rdy( switch_units__recv__rdy[5] ), + .recv__val( switch_units__recv__val[5] ), + .send__msg( switch_units__send__msg[5] ), + .send__rdy( switch_units__send__rdy[5] ), + .send__val( switch_units__send__val[5] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__6 + ( + .clk( switch_units__clk[6] ), + .reset( switch_units__reset[6] ), + .recv__msg( switch_units__recv__msg[6] ), + .recv__rdy( switch_units__recv__rdy[6] ), + .recv__val( switch_units__recv__val[6] ), + .send__msg( switch_units__send__msg[6] ), + .send__rdy( switch_units__send__rdy[6] ), + .send__val( switch_units__send__val[6] ) + ); + + SwitchUnitRTL__4cc70db240bb572a switch_units__7 + ( + .clk( switch_units__clk[7] ), + .reset( switch_units__reset[7] ), + .recv__msg( switch_units__recv__msg[7] ), + .recv__rdy( switch_units__recv__rdy[7] ), + .recv__val( switch_units__recv__val[7] ), + .send__msg( switch_units__send__msg[7] ), + .send__rdy( switch_units__send__rdy[7] ), + .send__val( switch_units__send__val[7] ) + ); + + //------------------------------------------------------------- + // End of component switch_units[0:7] + //------------------------------------------------------------- + + assign input_units__clk[0] = clk; + assign input_units__reset[0] = reset; + assign input_units__clk[1] = clk; + assign input_units__reset[1] = reset; + assign input_units__clk[2] = clk; + assign input_units__reset[2] = reset; + assign route_units__clk[0] = clk; + assign route_units__reset[0] = reset; + assign route_units__clk[1] = clk; + assign route_units__reset[1] = reset; + assign route_units__clk[2] = clk; + assign route_units__reset[2] = reset; + assign switch_units__clk[0] = clk; + assign switch_units__reset[0] = reset; + assign switch_units__clk[1] = clk; + assign switch_units__reset[1] = reset; + assign switch_units__clk[2] = clk; + assign switch_units__reset[2] = reset; + assign switch_units__clk[3] = clk; + assign switch_units__reset[3] = reset; + assign switch_units__clk[4] = clk; + assign switch_units__reset[4] = reset; + assign switch_units__clk[5] = clk; + assign switch_units__reset[5] = reset; + assign switch_units__clk[6] = clk; + assign switch_units__reset[6] = reset; + assign switch_units__clk[7] = clk; + assign switch_units__reset[7] = reset; + assign output_units__clk[0] = clk; + assign output_units__reset[0] = reset; + assign output_units__clk[1] = clk; + assign output_units__reset[1] = reset; + assign output_units__clk[2] = clk; + assign output_units__reset[2] = reset; + assign output_units__clk[3] = clk; + assign output_units__reset[3] = reset; + assign output_units__clk[4] = clk; + assign output_units__reset[4] = reset; + assign output_units__clk[5] = clk; + assign output_units__reset[5] = reset; + assign output_units__clk[6] = clk; + assign output_units__reset[6] = reset; + assign output_units__clk[7] = clk; + assign output_units__reset[7] = reset; + assign input_units__recv__msg[0] = recv__msg[0]; + assign recv__rdy[0] = input_units__recv__rdy[0]; + assign input_units__recv__val[0] = recv__val[0]; + assign route_units__recv__msg[0] = input_units__send__msg[0]; + assign input_units__send__rdy[0] = route_units__recv__rdy[0]; + assign route_units__recv__val[0] = input_units__send__val[0]; + assign input_units__recv__msg[1] = recv__msg[1]; + assign recv__rdy[1] = input_units__recv__rdy[1]; + assign input_units__recv__val[1] = recv__val[1]; + assign route_units__recv__msg[1] = input_units__send__msg[1]; + assign input_units__send__rdy[1] = route_units__recv__rdy[1]; + assign route_units__recv__val[1] = input_units__send__val[1]; + assign input_units__recv__msg[2] = recv__msg[2]; + assign recv__rdy[2] = input_units__recv__rdy[2]; + assign input_units__recv__val[2] = recv__val[2]; + assign route_units__recv__msg[2] = input_units__send__msg[2]; + assign input_units__send__rdy[2] = route_units__recv__rdy[2]; + assign route_units__recv__val[2] = input_units__send__val[2]; + assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; + assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; + assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; + assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; + assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; + assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; + assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; + assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; + assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; + assign switch_units__recv__msg[3][0] = route_units__send__msg[0][3]; + assign route_units__send__rdy[0][3] = switch_units__recv__rdy[3][0]; + assign switch_units__recv__val[3][0] = route_units__send__val[0][3]; + assign switch_units__recv__msg[4][0] = route_units__send__msg[0][4]; + assign route_units__send__rdy[0][4] = switch_units__recv__rdy[4][0]; + assign switch_units__recv__val[4][0] = route_units__send__val[0][4]; + assign switch_units__recv__msg[5][0] = route_units__send__msg[0][5]; + assign route_units__send__rdy[0][5] = switch_units__recv__rdy[5][0]; + assign switch_units__recv__val[5][0] = route_units__send__val[0][5]; + assign switch_units__recv__msg[6][0] = route_units__send__msg[0][6]; + assign route_units__send__rdy[0][6] = switch_units__recv__rdy[6][0]; + assign switch_units__recv__val[6][0] = route_units__send__val[0][6]; + assign switch_units__recv__msg[7][0] = route_units__send__msg[0][7]; + assign route_units__send__rdy[0][7] = switch_units__recv__rdy[7][0]; + assign switch_units__recv__val[7][0] = route_units__send__val[0][7]; + assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; + assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; + assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; + assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; + assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; + assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; + assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; + assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; + assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; + assign switch_units__recv__msg[3][1] = route_units__send__msg[1][3]; + assign route_units__send__rdy[1][3] = switch_units__recv__rdy[3][1]; + assign switch_units__recv__val[3][1] = route_units__send__val[1][3]; + assign switch_units__recv__msg[4][1] = route_units__send__msg[1][4]; + assign route_units__send__rdy[1][4] = switch_units__recv__rdy[4][1]; + assign switch_units__recv__val[4][1] = route_units__send__val[1][4]; + assign switch_units__recv__msg[5][1] = route_units__send__msg[1][5]; + assign route_units__send__rdy[1][5] = switch_units__recv__rdy[5][1]; + assign switch_units__recv__val[5][1] = route_units__send__val[1][5]; + assign switch_units__recv__msg[6][1] = route_units__send__msg[1][6]; + assign route_units__send__rdy[1][6] = switch_units__recv__rdy[6][1]; + assign switch_units__recv__val[6][1] = route_units__send__val[1][6]; + assign switch_units__recv__msg[7][1] = route_units__send__msg[1][7]; + assign route_units__send__rdy[1][7] = switch_units__recv__rdy[7][1]; + assign switch_units__recv__val[7][1] = route_units__send__val[1][7]; + assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; + assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; + assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; + assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; + assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; + assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; + assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; + assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; + assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; + assign switch_units__recv__msg[3][2] = route_units__send__msg[2][3]; + assign route_units__send__rdy[2][3] = switch_units__recv__rdy[3][2]; + assign switch_units__recv__val[3][2] = route_units__send__val[2][3]; + assign switch_units__recv__msg[4][2] = route_units__send__msg[2][4]; + assign route_units__send__rdy[2][4] = switch_units__recv__rdy[4][2]; + assign switch_units__recv__val[4][2] = route_units__send__val[2][4]; + assign switch_units__recv__msg[5][2] = route_units__send__msg[2][5]; + assign route_units__send__rdy[2][5] = switch_units__recv__rdy[5][2]; + assign switch_units__recv__val[5][2] = route_units__send__val[2][5]; + assign switch_units__recv__msg[6][2] = route_units__send__msg[2][6]; + assign route_units__send__rdy[2][6] = switch_units__recv__rdy[6][2]; + assign switch_units__recv__val[6][2] = route_units__send__val[2][6]; + assign switch_units__recv__msg[7][2] = route_units__send__msg[2][7]; + assign route_units__send__rdy[2][7] = switch_units__recv__rdy[7][2]; + assign switch_units__recv__val[7][2] = route_units__send__val[2][7]; + assign output_units__recv__msg[0] = switch_units__send__msg[0]; + assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; + assign output_units__recv__val[0] = switch_units__send__val[0]; + assign send__msg[0] = output_units__send__msg[0]; + assign output_units__send__rdy[0] = send__rdy[0]; + assign send__val[0] = output_units__send__val[0]; + assign output_units__recv__msg[1] = switch_units__send__msg[1]; + assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; + assign output_units__recv__val[1] = switch_units__send__val[1]; + assign send__msg[1] = output_units__send__msg[1]; + assign output_units__send__rdy[1] = send__rdy[1]; + assign send__val[1] = output_units__send__val[1]; + assign output_units__recv__msg[2] = switch_units__send__msg[2]; + assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; + assign output_units__recv__val[2] = switch_units__send__val[2]; + assign send__msg[2] = output_units__send__msg[2]; + assign output_units__send__rdy[2] = send__rdy[2]; + assign send__val[2] = output_units__send__val[2]; + assign output_units__recv__msg[3] = switch_units__send__msg[3]; + assign switch_units__send__rdy[3] = output_units__recv__rdy[3]; + assign output_units__recv__val[3] = switch_units__send__val[3]; + assign send__msg[3] = output_units__send__msg[3]; + assign output_units__send__rdy[3] = send__rdy[3]; + assign send__val[3] = output_units__send__val[3]; + assign output_units__recv__msg[4] = switch_units__send__msg[4]; + assign switch_units__send__rdy[4] = output_units__recv__rdy[4]; + assign output_units__recv__val[4] = switch_units__send__val[4]; + assign send__msg[4] = output_units__send__msg[4]; + assign output_units__send__rdy[4] = send__rdy[4]; + assign send__val[4] = output_units__send__val[4]; + assign output_units__recv__msg[5] = switch_units__send__msg[5]; + assign switch_units__send__rdy[5] = output_units__recv__rdy[5]; + assign output_units__recv__val[5] = switch_units__send__val[5]; + assign send__msg[5] = output_units__send__msg[5]; + assign output_units__send__rdy[5] = send__rdy[5]; + assign send__val[5] = output_units__send__val[5]; + assign output_units__recv__msg[6] = switch_units__send__msg[6]; + assign switch_units__send__rdy[6] = output_units__recv__rdy[6]; + assign output_units__recv__val[6] = switch_units__send__val[6]; + assign send__msg[6] = output_units__send__msg[6]; + assign output_units__send__rdy[6] = send__rdy[6]; + assign send__val[6] = output_units__send__val[6]; + assign output_units__recv__msg[7] = switch_units__send__msg[7]; + assign switch_units__send__rdy[7] = output_units__recv__rdy[7]; + assign output_units__recv__val[7] = switch_units__send__val[7]; + assign send__msg[7] = output_units__send__msg[7]; + assign output_units__send__rdy[7] = send__rdy[7]; + assign send__val[7] = output_units__send__val[7]; + +endmodule + + +// PyMTL Component DataMemControllerRTL Definition +// Full name: DataMemControllerRTL__NocPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_rd_tiles_7__num_wr_tiles_7__multi_cgra_rows_2__multi_cgra_columns_2__num_tiles_16__mem_access_is_combinational_True__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)} +// At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py + +module DataMemControllerRTL__20df9b544ed809f0 +( + input logic [6:0] address_lower , + input logic [6:0] address_upper , + input logic [1:0] cgra_id , + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_load_request__msg , + output logic [0:0] recv_from_noc_load_request__rdy , + input logic [0:0] recv_from_noc_load_request__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_load_response_pkt__msg , + output logic [0:0] recv_from_noc_load_response_pkt__rdy , + input logic [0:0] recv_from_noc_load_response_pkt__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_store_request__msg , + output logic [0:0] recv_from_noc_store_request__rdy , + input logic [0:0] recv_from_noc_store_request__val , + input logic [6:0] recv_raddr__msg [0:6] , + output logic [0:0] recv_raddr__rdy [0:6] , + input logic [0:0] recv_raddr__val [0:6] , + input logic [6:0] recv_waddr__msg [0:6] , + output logic [0:0] recv_waddr__rdy [0:6] , + input logic [0:0] recv_waddr__val [0:6] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_wdata__msg [0:6] , + output logic [0:0] recv_wdata__rdy [0:6] , + input logic [0:0] recv_wdata__val [0:6] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_rdata__msg [0:6] , + input logic [0:0] send_rdata__rdy [0:6] , + output logic [0:0] send_rdata__val [0:6] , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_load_request_pkt__msg , + input logic [0:0] send_to_noc_load_request_pkt__rdy , + output logic [0:0] send_to_noc_load_request_pkt__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_load_response_pkt__msg , + input logic [0:0] send_to_noc_load_response_pkt__rdy , + output logic [0:0] send_to_noc_load_response_pkt__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_store_pkt__msg , + input logic [0:0] send_to_noc_store_pkt__rdy , + output logic [0:0] send_to_noc_store_pkt__val +); + localparam logic [3:0] __const__num_xbar_in_rd_ports_at_assemble_xbar_pkt = 4'd8; + localparam logic [3:0] __const__num_xbar_in_wr_ports_at_assemble_xbar_pkt = 4'd8; + localparam logic [2:0] __const__num_rd_tiles_at_assemble_xbar_pkt = 3'd7; + localparam logic [2:0] __const__per_bank_addr_nbits_at_assemble_xbar_pkt = 3'd4; + localparam logic [1:0] __const__num_banks_per_cgra_at_assemble_xbar_pkt = 2'd2; + localparam logic [2:0] __const__num_wr_tiles_at_assemble_xbar_pkt = 3'd7; + localparam logic [2:0] __const__num_rd_tiles_at_update_all = 3'd7; + localparam logic [2:0] __const__num_wr_tiles_at_update_all = 3'd7; + localparam logic [3:0] __const__num_xbar_in_rd_ports_at_update_all = 4'd8; + localparam logic [3:0] __const__num_xbar_in_wr_ports_at_update_all = 4'd8; + localparam logic [3:0] __const__CMD_LOAD_RESPONSE = 4'd11; + localparam logic [1:0] __const__num_banks_per_cgra_at_update_all = 2'd2; + localparam logic [3:0] __const__CMD_LOAD_REQUEST = 4'd10; + localparam logic [3:0] __const__CMD_STORE_REQUEST = 4'd12; + logic [0:0] idTo2d_x_lut [0:3]; + logic [0:0] idTo2d_y_lut [0:3]; + MemAccessPacket_8_3_128__43c148781d2f2a57 rd_pkt [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 wr_pkt [0:7]; + //------------------------------------------------------------- + // Component memory_wrapper[0:1] + //------------------------------------------------------------- + + logic [0:0] memory_wrapper__clk [0:1]; + logic [0:0] memory_wrapper__reset [0:1]; + MemAccessPacket_8_3_128__43c148781d2f2a57 memory_wrapper__recv_rd__msg [0:1]; + logic [0:0] memory_wrapper__recv_rd__rdy [0:1]; + logic [0:0] memory_wrapper__recv_rd__val [0:1]; + MemAccessPacket_8_3_128__43c148781d2f2a57 memory_wrapper__recv_wr__msg [0:1]; + logic [0:0] memory_wrapper__recv_wr__rdy [0:1]; + logic [0:0] memory_wrapper__recv_wr__val [0:1]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 memory_wrapper__send__msg [0:1]; + logic [0:0] memory_wrapper__send__rdy [0:1]; + logic [0:0] memory_wrapper__send__val [0:1]; + + DataMemWrapperRTL__33e0a5b37976e571 memory_wrapper__0 + ( + .clk( memory_wrapper__clk[0] ), + .reset( memory_wrapper__reset[0] ), + .recv_rd__msg( memory_wrapper__recv_rd__msg[0] ), + .recv_rd__rdy( memory_wrapper__recv_rd__rdy[0] ), + .recv_rd__val( memory_wrapper__recv_rd__val[0] ), + .recv_wr__msg( memory_wrapper__recv_wr__msg[0] ), + .recv_wr__rdy( memory_wrapper__recv_wr__rdy[0] ), + .recv_wr__val( memory_wrapper__recv_wr__val[0] ), + .send__msg( memory_wrapper__send__msg[0] ), + .send__rdy( memory_wrapper__send__rdy[0] ), + .send__val( memory_wrapper__send__val[0] ) + ); + + DataMemWrapperRTL__33e0a5b37976e571 memory_wrapper__1 + ( + .clk( memory_wrapper__clk[1] ), + .reset( memory_wrapper__reset[1] ), + .recv_rd__msg( memory_wrapper__recv_rd__msg[1] ), + .recv_rd__rdy( memory_wrapper__recv_rd__rdy[1] ), + .recv_rd__val( memory_wrapper__recv_rd__val[1] ), + .recv_wr__msg( memory_wrapper__recv_wr__msg[1] ), + .recv_wr__rdy( memory_wrapper__recv_wr__rdy[1] ), + .recv_wr__val( memory_wrapper__recv_wr__val[1] ), + .send__msg( memory_wrapper__send__msg[1] ), + .send__rdy( memory_wrapper__send__rdy[1] ), + .send__val( memory_wrapper__send__val[1] ) + ); + + //------------------------------------------------------------- + // End of component memory_wrapper[0:1] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component read_crossbar + //------------------------------------------------------------- + + logic [0:0] read_crossbar__clk; + logic [0:0] read_crossbar__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 read_crossbar__recv__msg [0:7]; + logic [0:0] read_crossbar__recv__rdy [0:7]; + logic [0:0] read_crossbar__recv__val [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 read_crossbar__send__msg [0:2]; + logic [0:0] read_crossbar__send__rdy [0:2]; + logic [0:0] read_crossbar__send__val [0:2]; + + XbarBypassQueueRTL__045133ee283ca701 read_crossbar + ( + .clk( read_crossbar__clk ), + .reset( read_crossbar__reset ), + .recv__msg( read_crossbar__recv__msg ), + .recv__rdy( read_crossbar__recv__rdy ), + .recv__val( read_crossbar__recv__val ), + .send__msg( read_crossbar__send__msg ), + .send__rdy( read_crossbar__send__rdy ), + .send__val( read_crossbar__send__val ) + ); + + //------------------------------------------------------------- + // End of component read_crossbar + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component response_crossbar + //------------------------------------------------------------- + + logic [0:0] response_crossbar__clk; + logic [0:0] response_crossbar__reset; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 response_crossbar__recv__msg [0:2]; + logic [0:0] response_crossbar__recv__rdy [0:2]; + logic [0:0] response_crossbar__recv__val [0:2]; + MemAccessPacket_3_8_128__9f21b0bcdad2c061 response_crossbar__send__msg [0:7]; + logic [0:0] response_crossbar__send__rdy [0:7]; + logic [0:0] response_crossbar__send__val [0:7]; + + XbarBypassQueueRTL__510da12df6787984 response_crossbar + ( + .clk( response_crossbar__clk ), + .reset( response_crossbar__reset ), + .recv__msg( response_crossbar__recv__msg ), + .recv__rdy( response_crossbar__recv__rdy ), + .recv__val( response_crossbar__recv__val ), + .send__msg( response_crossbar__send__msg ), + .send__rdy( response_crossbar__send__rdy ), + .send__val( response_crossbar__send__val ) + ); + + //------------------------------------------------------------- + // End of component response_crossbar + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component write_crossbar + //------------------------------------------------------------- + + logic [0:0] write_crossbar__clk; + logic [0:0] write_crossbar__reset; + MemAccessPacket_8_3_128__43c148781d2f2a57 write_crossbar__recv__msg [0:7]; + logic [0:0] write_crossbar__recv__rdy [0:7]; + logic [0:0] write_crossbar__recv__val [0:7]; + MemAccessPacket_8_3_128__43c148781d2f2a57 write_crossbar__send__msg [0:2]; + logic [0:0] write_crossbar__send__rdy [0:2]; + logic [0:0] write_crossbar__send__val [0:2]; + + XbarBypassQueueRTL__045133ee283ca701 write_crossbar + ( + .clk( write_crossbar__clk ), + .reset( write_crossbar__reset ), + .recv__msg( write_crossbar__recv__msg ), + .recv__rdy( write_crossbar__recv__rdy ), + .recv__val( write_crossbar__recv__val ), + .send__msg( write_crossbar__send__msg ), + .send__rdy( write_crossbar__send__rdy ), + .send__val( write_crossbar__send__val ) + ); + + //------------------------------------------------------------- + // End of component write_crossbar + //------------------------------------------------------------- + logic [6:0] __tmpvar__assemble_xbar_pkt_recv_raddr; + logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_load_local; + logic [6:0] __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc; + logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc; + logic [6:0] __tmpvar__assemble_xbar_pkt_recv_waddr; + logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_store_local; + logic [6:0] __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc; + logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc; + logic [1:0] __tmpvar__update_all_from_cgra_id; + logic [4:0] __tmpvar__update_all_from_tile_id; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py:159 + // @update + // def assemble_xbar_pkt(): + // for i in range(num_xbar_in_rd_ports): + // s.rd_pkt[i] @= MemReadPktType(i, 0, 0, DataType(0, 0, 0, 0), 0, 0, i, 0, 0, 0) + // + // for i in range(num_xbar_in_wr_ports): + // s.wr_pkt[i] @= MemWritePktType(i, 0, 0, DataType(0, 0, 0, 0), 0, 0, i, 0, 0, 0) + // + // for i in range(num_rd_tiles): + // recv_raddr = s.recv_raddr[i].msg + // # Calculates the target bank index for load. + // if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper): + // bank_index_load_local = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType) + // else: + // bank_index_load_local = XbarOutRdType(num_banks_per_cgra) + // # FIXME: change to exact tile id. + // s.rd_pkt[i] @= MemReadPktType(i, # src + // bank_index_load_local, # dst + // recv_raddr, # addr + // DataType(0, 0, 0, 0), # data + // s.cgra_id, # src_cgra + // 0, # src_tile + // i, # remote_src_port + // 0, # streaming_rd + // 0, # streaming_rd_stride + // 0) # streaming_rd_end_addr + // + // recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr + // # Calculates the target bank index. + // if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper): + // bank_index_load_from_noc = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType) + // else: + // bank_index_load_from_noc = XbarOutRdType(num_banks_per_cgra) + // s.rd_pkt[num_rd_tiles] @= MemReadPktType(num_rd_tiles, # src + // bank_index_load_from_noc, # dst + // recv_raddr_from_noc, # addr + // DataType(0, 0, 0, 0), # data + // s.recv_from_noc_load_request.msg.src, # src_cgra + // s.recv_from_noc_load_request.msg.src_tile_id, # src_tile + // s.recv_from_noc_load_request.msg.remote_src_port, # remote_src_port + // 0, # streaming_rd + // 0, # streaming_rd_stride + // 0) # streaming_rd_end_addr + // + // + // for i in range(num_wr_tiles): + // recv_waddr = s.recv_waddr[i].msg + // # Calculates the target bank index for store. + // if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper): + // bank_index_store_local = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType) + // else: + // bank_index_store_local = XbarOutWrType(num_banks_per_cgra) + // s.wr_pkt[i] @= MemWritePktType(i, # src + // bank_index_store_local, # dst + // recv_waddr, # addr + // s.recv_wdata[i].msg, # data + // 0, # src_cgra + // 0, # src_tile + // i, # remote_src_port + // 0, # streaming_rd + // 0, # streaming_rd_stride + // 0) # streaming_rd_end_addr + // + // + // recv_waddr_from_noc = s.recv_from_noc_store_request.msg.payload.data_addr + // recv_wdata_from_noc = s.recv_from_noc_store_request.msg.payload.data + // if (recv_waddr_from_noc >= s.address_lower) & (recv_waddr_from_noc <= s.address_upper): + // bank_index_store_from_noc = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType) + // else: + // bank_index_store_from_noc = XbarOutWrType(num_banks_per_cgra) + // s.wr_pkt[num_wr_tiles] @= MemWritePktType(num_wr_tiles, # src + // bank_index_store_from_noc, # dst + // recv_waddr_from_noc, # addr + // recv_wdata_from_noc, # data + // 0, # src_cgra + // 0, # src_tile + // num_wr_tiles, # remote_src_port + // 0, # streaming_rd + // 0, # streaming_rd_stride + // 0) # streaming_rd_end_addr + + always_comb begin : assemble_xbar_pkt + for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_assemble_xbar_pkt ); i += 1'd1 ) + rd_pkt[3'(i)] = { 3'(i), 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; + for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_wr_ports_at_assemble_xbar_pkt ); i += 1'd1 ) + wr_pkt[3'(i)] = { 3'(i), 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; + for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_assemble_xbar_pkt ); i += 1'd1 ) begin + __tmpvar__assemble_xbar_pkt_recv_raddr = recv_raddr__msg[3'(i)]; + if ( ( __tmpvar__assemble_xbar_pkt_recv_raddr >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_raddr <= address_upper ) ) begin + __tmpvar__assemble_xbar_pkt_bank_index_load_local = 2'(( __tmpvar__assemble_xbar_pkt_recv_raddr - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); + end + else + __tmpvar__assemble_xbar_pkt_bank_index_load_local = 2'd2; + rd_pkt[3'(i)] = { 3'(i), __tmpvar__assemble_xbar_pkt_bank_index_load_local, __tmpvar__assemble_xbar_pkt_recv_raddr, { 64'd0, 1'd0, 1'd0, 1'd0 }, cgra_id, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; + end + __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc = recv_from_noc_load_request__msg.payload.data_addr; + if ( ( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc <= address_upper ) ) begin + __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc = 2'(( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); + end + else + __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc = 2'd2; + rd_pkt[3'( __const__num_rd_tiles_at_assemble_xbar_pkt )] = { 3'( __const__num_rd_tiles_at_assemble_xbar_pkt ), __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc, __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc, { 64'd0, 1'd0, 1'd0, 1'd0 }, recv_from_noc_load_request__msg.src, recv_from_noc_load_request__msg.src_tile_id, recv_from_noc_load_request__msg.remote_src_port, 1'd0, 7'd0, 7'd0 }; + for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ); i += 1'd1 ) begin + __tmpvar__assemble_xbar_pkt_recv_waddr = recv_waddr__msg[3'(i)]; + if ( ( __tmpvar__assemble_xbar_pkt_recv_waddr >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_waddr <= address_upper ) ) begin + __tmpvar__assemble_xbar_pkt_bank_index_store_local = 2'(( __tmpvar__assemble_xbar_pkt_recv_waddr - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); + end + else + __tmpvar__assemble_xbar_pkt_bank_index_store_local = 2'd2; + wr_pkt[3'(i)] = { 3'(i), __tmpvar__assemble_xbar_pkt_bank_index_store_local, __tmpvar__assemble_xbar_pkt_recv_waddr, recv_wdata__msg[3'(i)], 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; + end + __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc = recv_from_noc_store_request__msg.payload.data_addr; + __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc = recv_from_noc_store_request__msg.payload.data; + if ( ( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc <= address_upper ) ) begin + __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc = 2'(( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); + end + else + __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc = 2'd2; + wr_pkt[3'( __const__num_wr_tiles_at_assemble_xbar_pkt )] = { 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ), __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc, __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc, __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc, 2'd0, 5'd0, 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ), 1'd0, 7'd0, 7'd0 }; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py:242 + // @update + // def update_all(): + // # Initializes the signals. + // for i in range(num_rd_tiles): + // s.recv_raddr[i].rdy @= 0 + // s.recv_from_noc_load_request.rdy @= 0 + // + // for i in range(num_wr_tiles): + // s.recv_waddr[i].rdy @= 0 + // # s.recv_wdata_bypass_q[i].send.rdy @= 0 + // s.recv_from_noc_store_request.rdy @= 0 + // # s.recv_wdata_bypass_q[num_wr_tiles].send.rdy @= 0 + // + // for i in range(num_rd_tiles): + // s.send_rdata[i].val @= 0 + // s.send_rdata[i].msg @= DataType() + // s.send_to_noc_load_response_pkt.val @= 0 + // + // s.send_to_noc_load_response_pkt.msg @= \ + // NocPktType(0, # src + // 0, # dst + // 0, # src_x + // 0, # src_y + // 0, # dst_x + // 0, # dst_y + // 0, # src_tile_id + // 0, # dst_tile_id + // 0, # remote_src_port + // 0, # opaque + // 0, # vc_id + // CgraPayloadType(0, 0, 0, 0, 0)) + // + // + // for i in range(num_wr_tiles): + // s.recv_wdata[i].rdy @= 0 + // + // s.send_to_noc_store_pkt.msg @= \ + // NocPktType(0, # src + // 0, # dst + // 0, # src_x + // 0, # src_y + // 0, # dst_x + // 0, # dst_y + // 0, # src_tile_id + // 0, # dst_tile_id + // 0, # remote_src_port + // 0, # opaque + // 0, # vc_id + // CgraPayloadType(0, 0, 0, 0, 0)) + // + // s.send_to_noc_store_pkt.val @= 0 + // + // for i in range(num_xbar_in_rd_ports): + // s.read_crossbar.recv[i].val @= 0 + // s.read_crossbar.recv[i].msg @= MemReadPktType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) + // + // s.recv_from_noc_load_response_pkt.rdy @= 0 + // + // for i in range(num_xbar_in_wr_ports): + // s.write_crossbar.recv[i].val @= 0 + // s.write_crossbar.recv[i].msg @= MemWritePktType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) + // + // s.send_to_noc_load_request_pkt.msg @= \ + // NocPktType(0, # src + // 0, # dst + // 0, # src_x + // 0, # src_y + // 0, # dst_x + // 0, # dst_y + // 0, # src_tile_id + // 0, # dst_tile_id + // 0, # remote_src_port + // 0, # opaque + // 0, # vc_id + // CgraPayloadType(0, 0, 0, 0, 0)) + // + // s.send_to_noc_load_request_pkt.val @= 0 + // + // # Connects the load request ports (from tiles and NoC) to the xbar targetting memory and NoC. + // for i in range(num_rd_tiles): + // s.read_crossbar.recv[i].val @= s.recv_raddr[i].val + // s.read_crossbar.recv[i].msg @= s.rd_pkt[i] + // s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy + // s.read_crossbar.recv[num_rd_tiles].val @= s.recv_from_noc_load_request.val + // s.read_crossbar.recv[num_rd_tiles].msg @= s.rd_pkt[num_rd_tiles] + // s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[num_rd_tiles].rdy + // + // # Connects the store request ports (from tiles and NoC) to the xbar targetting memory and NoC. + // for i in range(num_wr_tiles): + // s.write_crossbar.recv[i].val @= s.recv_waddr[i].val + // s.write_crossbar.recv[i].msg @= s.wr_pkt[i] + // s.recv_waddr[i].rdy @= s.write_crossbar.recv[i].rdy + // s.recv_wdata[i].rdy @= s.write_crossbar.recv[i].rdy + // s.write_crossbar.recv[num_wr_tiles].val @= s.recv_from_noc_store_request.val + // s.write_crossbar.recv[num_wr_tiles].msg @= s.wr_pkt[num_wr_tiles] + // s.recv_from_noc_store_request.rdy @= s.write_crossbar.recv[num_wr_tiles].rdy + // + // # Connects the response ports to tiles and NoC from the xbar. + // # Number of load responses is expected to be the same as the number of load requests. + // for i in range(num_xbar_in_rd_ports): + // if i < num_rd_tiles: + // s.send_rdata[RdTileIdType(i)].msg @= s.response_crossbar.send[i].msg.data + // s.send_rdata[RdTileIdType(i)].val @= s.response_crossbar.send[i].val + // s.response_crossbar.send[i].rdy @= s.send_rdata[RdTileIdType(i)].rdy + // else: + // from_cgra_id = s.response_crossbar.send[i].msg.src_cgra + // from_tile_id = s.response_crossbar.send[i].msg.src_tile + // s.send_to_noc_load_response_pkt.msg @= \ + // NocPktType( + // s.cgra_id, # src_cgra_id + // from_cgra_id, # dst_cgra_id + // s.idTo2d_x_lut[s.cgra_id], # src_cgra_x + // s.idTo2d_y_lut[s.cgra_id], # src_cgra_y + // s.idTo2d_x_lut[from_cgra_id], # dst_cgra_x + // s.idTo2d_y_lut[from_cgra_id], # dst_cgra_y + // 0, # src_tile_id set as 0 as it is from memory rather than a specific tile. + // from_tile_id, # dst_tile_id + // s.response_crossbar.send[i].msg.remote_src_port, # remote_src_port, carries the original source port id towards the src. + // 0, # opaque + // 0, # vc_id + // CgraPayloadType( + // CMD_LOAD_RESPONSE, + // s.response_crossbar.send[i].msg.data, + // s.response_crossbar.send[i].msg.addr, 0, 0)) + // + // s.send_to_noc_load_response_pkt.val @= s.response_crossbar.send[i].val + // s.response_crossbar.send[i].rdy @= s.send_to_noc_load_response_pkt.rdy + // + // # Handles the request (not response) towards the others via the NoC. The dst would be + // # updated in the controller. + // s.send_to_noc_load_request_pkt.msg @= \ + // NocPktType(s.cgra_id, # src + // 0, # dst + // s.idTo2d_x_lut[s.cgra_id], # src_x + // s.idTo2d_y_lut[s.cgra_id], # src_y + // 0, # dst_x + // 0, # dst_y + // 0, # src_tile_id + // 0, # dst_tile_id + // s.read_crossbar.send[num_banks_per_cgra].msg.src, # remote_src_port + // 0, # opaque + // 0, # vc_id + // CgraPayloadType( + // CMD_LOAD_REQUEST, + // 0, + // s.read_crossbar.send[num_banks_per_cgra].msg.addr, 0, 0)) + // + // s.send_to_noc_load_request_pkt.val @= s.read_crossbar.send[num_banks_per_cgra].val + // # TODO: https://github.com/tancheng/VectorCGRA/issues/26 -- Modify this part for non-blocking access. + // # 'val` indicates the data is arbitrated successfully. + // s.recv_from_noc_load_response_pkt.rdy @= s.response_crossbar.recv[num_banks_per_cgra].rdy + // s.response_crossbar.recv[num_banks_per_cgra].val @= s.recv_from_noc_load_response_pkt.val + // s.response_crossbar.recv[num_banks_per_cgra].msg @= \ + // MemResponsePktType(num_banks_per_cgra, + // s.recv_from_noc_load_response_pkt.msg.remote_src_port, + // s.recv_from_noc_load_response_pkt.msg.payload.data_addr, + // s.recv_from_noc_load_response_pkt.msg.payload.data, + // s.recv_from_noc_load_response_pkt.msg.src, + // s.recv_from_noc_load_response_pkt.msg.src_tile_id, + // 0, + // 0, # streaming_rd + // 0, # streaming_rd_stride + // 0) # streaming_rd_end_addr + // + // # Allows other load request towards NoC when the previous one is not responded. There + // # could be out-of-order load response, i.e., potential consistency issue. + // s.read_crossbar.send[num_banks_per_cgra].rdy @= s.send_to_noc_load_request_pkt.rdy + // + // # Handles the write port towards the NoC. + // s.send_to_noc_store_pkt.msg @= \ + // NocPktType(s.cgra_id, # src + // 0, # dst + // s.idTo2d_x_lut[s.cgra_id], # src_x + // s.idTo2d_y_lut[s.cgra_id], # src_y + // 0, # dst_x + // 0, # dst_y + // 0, # src_tile_id + // 0, # dst_tile_id + // s.write_crossbar.send[num_banks_per_cgra].msg.src, # remote_src_port + // 0, # opaque + // 0, # vc_id + // CgraPayloadType( + // CMD_STORE_REQUEST, + // s.write_crossbar.send[num_banks_per_cgra].msg.data, + // s.write_crossbar.send[num_banks_per_cgra].msg.addr, 0, 0)) + // + // s.send_to_noc_store_pkt.val @= s.write_crossbar.send[num_banks_per_cgra].val + // s.write_crossbar.send[num_banks_per_cgra].rdy @= s.send_to_noc_store_pkt.rdy + + always_comb begin : update_all + for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) + recv_raddr__rdy[3'(i)] = 1'd0; + recv_from_noc_load_request__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) + recv_waddr__rdy[3'(i)] = 1'd0; + recv_from_noc_store_request__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) begin + send_rdata__val[3'(i)] = 1'd0; + send_rdata__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + send_to_noc_load_response_pkt__val = 1'd0; + send_to_noc_load_response_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; + for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) + recv_wdata__rdy[3'(i)] = 1'd0; + send_to_noc_store_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; + send_to_noc_store_pkt__val = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_update_all ); i += 1'd1 ) begin + read_crossbar__recv__val[3'(i)] = 1'd0; + read_crossbar__recv__msg[3'(i)] = { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; + end + recv_from_noc_load_response_pkt__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_wr_ports_at_update_all ); i += 1'd1 ) begin + write_crossbar__recv__val[3'(i)] = 1'd0; + write_crossbar__recv__msg[3'(i)] = { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; + end + send_to_noc_load_request_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; + send_to_noc_load_request_pkt__val = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) begin + read_crossbar__recv__val[3'(i)] = recv_raddr__val[3'(i)]; + read_crossbar__recv__msg[3'(i)] = rd_pkt[3'(i)]; + recv_raddr__rdy[3'(i)] = read_crossbar__recv__rdy[3'(i)]; + end + read_crossbar__recv__val[3'( __const__num_rd_tiles_at_update_all )] = recv_from_noc_load_request__val; + read_crossbar__recv__msg[3'( __const__num_rd_tiles_at_update_all )] = rd_pkt[3'( __const__num_rd_tiles_at_update_all )]; + recv_from_noc_load_request__rdy = read_crossbar__recv__rdy[3'( __const__num_rd_tiles_at_update_all )]; + for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) begin + write_crossbar__recv__val[3'(i)] = recv_waddr__val[3'(i)]; + write_crossbar__recv__msg[3'(i)] = wr_pkt[3'(i)]; + recv_waddr__rdy[3'(i)] = write_crossbar__recv__rdy[3'(i)]; + recv_wdata__rdy[3'(i)] = write_crossbar__recv__rdy[3'(i)]; + end + write_crossbar__recv__val[3'( __const__num_wr_tiles_at_update_all )] = recv_from_noc_store_request__val; + write_crossbar__recv__msg[3'( __const__num_wr_tiles_at_update_all )] = wr_pkt[3'( __const__num_wr_tiles_at_update_all )]; + recv_from_noc_store_request__rdy = write_crossbar__recv__rdy[3'( __const__num_wr_tiles_at_update_all )]; + for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_update_all ); i += 1'd1 ) + if ( 3'(i) < 3'( __const__num_rd_tiles_at_update_all ) ) begin + send_rdata__msg[3'( 3'(i) )] = response_crossbar__send__msg[3'(i)].data; + send_rdata__val[3'( 3'(i) )] = response_crossbar__send__val[3'(i)]; + response_crossbar__send__rdy[3'(i)] = send_rdata__rdy[3'( 3'(i) )]; + end + else begin + __tmpvar__update_all_from_cgra_id = response_crossbar__send__msg[3'(i)].src_cgra; + __tmpvar__update_all_from_tile_id = response_crossbar__send__msg[3'(i)].src_tile; + send_to_noc_load_response_pkt__msg = { cgra_id, __tmpvar__update_all_from_cgra_id, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], idTo2d_x_lut[__tmpvar__update_all_from_cgra_id], idTo2d_y_lut[__tmpvar__update_all_from_cgra_id], 5'd0, __tmpvar__update_all_from_tile_id, response_crossbar__send__msg[3'(i)].remote_src_port, 8'd0, 2'd0, { 5'( __const__CMD_LOAD_RESPONSE ), response_crossbar__send__msg[3'(i)].data, response_crossbar__send__msg[3'(i)].addr, 107'd0, 4'd0 } }; + send_to_noc_load_response_pkt__val = response_crossbar__send__val[3'(i)]; + response_crossbar__send__rdy[3'(i)] = send_to_noc_load_response_pkt__rdy; + end + send_to_noc_load_request_pkt__msg = { cgra_id, 2'd0, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], 1'd0, 1'd0, 5'd0, 5'd0, read_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].src, 8'd0, 2'd0, { 5'( __const__CMD_LOAD_REQUEST ), 67'd0, read_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].addr, 107'd0, 4'd0 } }; + send_to_noc_load_request_pkt__val = read_crossbar__send__val[2'( __const__num_banks_per_cgra_at_update_all )]; + recv_from_noc_load_response_pkt__rdy = response_crossbar__recv__rdy[2'( __const__num_banks_per_cgra_at_update_all )]; + response_crossbar__recv__val[2'( __const__num_banks_per_cgra_at_update_all )] = recv_from_noc_load_response_pkt__val; + response_crossbar__recv__msg[2'( __const__num_banks_per_cgra_at_update_all )] = { 2'( __const__num_banks_per_cgra_at_update_all ), recv_from_noc_load_response_pkt__msg.remote_src_port, recv_from_noc_load_response_pkt__msg.payload.data_addr, recv_from_noc_load_response_pkt__msg.payload.data, recv_from_noc_load_response_pkt__msg.src, recv_from_noc_load_response_pkt__msg.src_tile_id, 3'd0, 1'd0, 7'd0, 7'd0 }; + read_crossbar__send__rdy[2'( __const__num_banks_per_cgra_at_update_all )] = send_to_noc_load_request_pkt__rdy; + send_to_noc_store_pkt__msg = { cgra_id, 2'd0, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], 1'd0, 1'd0, 5'd0, 5'd0, write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].src, 8'd0, 2'd0, { 5'( __const__CMD_STORE_REQUEST ), write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].data, write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].addr, 107'd0, 4'd0 } }; + send_to_noc_store_pkt__val = write_crossbar__send__val[2'( __const__num_banks_per_cgra_at_update_all )]; + write_crossbar__send__rdy[2'( __const__num_banks_per_cgra_at_update_all )] = send_to_noc_store_pkt__rdy; + end + + assign memory_wrapper__clk[0] = clk; + assign memory_wrapper__reset[0] = reset; + assign memory_wrapper__clk[1] = clk; + assign memory_wrapper__reset[1] = reset; + assign read_crossbar__clk = clk; + assign read_crossbar__reset = reset; + assign write_crossbar__clk = clk; + assign write_crossbar__reset = reset; + assign response_crossbar__clk = clk; + assign response_crossbar__reset = reset; + assign idTo2d_x_lut[0] = 1'd0; + assign idTo2d_y_lut[0] = 1'd0; + assign idTo2d_x_lut[1] = 1'd1; + assign idTo2d_y_lut[1] = 1'd0; + assign idTo2d_x_lut[2] = 1'd0; + assign idTo2d_y_lut[2] = 1'd1; + assign idTo2d_x_lut[3] = 1'd1; + assign idTo2d_y_lut[3] = 1'd1; + assign memory_wrapper__recv_rd__msg[0] = read_crossbar__send__msg[0]; + assign read_crossbar__send__rdy[0] = memory_wrapper__recv_rd__rdy[0]; + assign memory_wrapper__recv_rd__val[0] = read_crossbar__send__val[0]; + assign memory_wrapper__recv_wr__msg[0] = write_crossbar__send__msg[0]; + assign write_crossbar__send__rdy[0] = memory_wrapper__recv_wr__rdy[0]; + assign memory_wrapper__recv_wr__val[0] = write_crossbar__send__val[0]; + assign response_crossbar__recv__msg[0] = memory_wrapper__send__msg[0]; + assign memory_wrapper__send__rdy[0] = response_crossbar__recv__rdy[0]; + assign response_crossbar__recv__val[0] = memory_wrapper__send__val[0]; + assign memory_wrapper__recv_rd__msg[1] = read_crossbar__send__msg[1]; + assign read_crossbar__send__rdy[1] = memory_wrapper__recv_rd__rdy[1]; + assign memory_wrapper__recv_rd__val[1] = read_crossbar__send__val[1]; + assign memory_wrapper__recv_wr__msg[1] = write_crossbar__send__msg[1]; + assign write_crossbar__send__rdy[1] = memory_wrapper__recv_wr__rdy[1]; + assign memory_wrapper__recv_wr__val[1] = write_crossbar__send__val[1]; + assign response_crossbar__recv__msg[1] = memory_wrapper__send__msg[1]; + assign memory_wrapper__send__rdy[1] = response_crossbar__recv__rdy[1]; + assign response_crossbar__recv__val[1] = memory_wrapper__send__val[1]; + +endmodule + + +// PyMTL Component ConstQueueDynamicRTL Definition +// Full name: ConstQueueDynamicRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__const_mem_size_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py + +module ConstQueueDynamicRTL__9d3397f72f19af52 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] ctrl_proceed , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_const__msg , + input logic [0:0] send_const__rdy , + output logic [0:0] send_const__val +); + localparam logic [4:0] __const__const_mem_size_at_load_const = 5'd16; + localparam logic [4:0] __const__const_mem_size_at_update_wr_cur = 5'd16; + logic [3:0] rd_cur; + logic [4:0] wr_cur; + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__bd22936ec5812d0d reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [0:0] __tmpvar__load_const_not_full; + logic [0:0] __tmpvar__update_wr_cur_not_full; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:56 + // @update + // def load_const(): + // # Initializes signals. + // s.reg_file.waddr[0] @= AddrType() + // s.reg_file.wdata[0] @= DataType() + // s.reg_file.wen[0] @= 0 + // + // not_full = s.wr_cur < const_mem_size + // s.recv_const.rdy @= not_full + // + // if s.recv_const.val & not_full: + // s.reg_file.waddr[0] @= trunc(s.wr_cur, AddrType) + // s.reg_file.wdata[0] @= s.recv_const.msg + // s.reg_file.wen[0] @= 1 + + always_comb begin : load_const + reg_file__waddr[1'd0] = 4'd0; + reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__wen[1'd0] = 1'd0; + __tmpvar__load_const_not_full = wr_cur < 5'( __const__const_mem_size_at_load_const ); + recv_const__rdy = __tmpvar__load_const_not_full; + if ( recv_const__val & __tmpvar__load_const_not_full ) begin + reg_file__waddr[1'd0] = 4'(wr_cur); + reg_file__wdata[1'd0] = recv_const__msg; + reg_file__wen[1'd0] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:83 + // @update + // def update_send_val(): + // # Checks if read cursor is in front of write cursor. + // if (zext(s.rd_cur, WrCurType) < s.wr_cur): + // s.send_const.val @= 1 + // else: + // s.send_const.val @= 0 + + always_comb begin : update_send_val + if ( { { 1 { 1'b0 } }, rd_cur } < wr_cur ) begin + send_const__val = 1'd1; + end + else + send_const__val = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:92 + // @update_ff + // def update_rd_cur(): + // if s.reset | s.clear: + // s.rd_cur <<= 0 + // else: + // # Checks whether the "reader" successfully read the data at rd_cur, + // # and proceed rd_cur accordingly. + // if s.send_const.rdy & s.ctrl_proceed: + // if zext((s.rd_cur), WrCurType) < (s.wr_cur - 1): + // s.rd_cur <<= s.rd_cur + 1 + // else: + // s.rd_cur <<= 0 + + always_ff @(posedge clk) begin : update_rd_cur + if ( reset | clear ) begin + rd_cur <= 4'd0; + end + else if ( send_const__rdy & ctrl_proceed ) begin + if ( { { 1 { 1'b0 } }, rd_cur } < ( wr_cur - 5'd1 ) ) begin + rd_cur <= rd_cur + 4'd1; + end + else + rd_cur <= 4'd0; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:72 + // @update_ff + // def update_wr_cur(): + // not_full = (s.wr_cur < const_mem_size) + // if s.reset | s.clear: + // s.wr_cur <<= 0 + // # Checks if there's a valid const (from producer) to be written. + // else: + // if s.recv_const.val & not_full: + // s.wr_cur <<= s.wr_cur + 1 + + always_ff @(posedge clk) begin : update_wr_cur + __tmpvar__update_wr_cur_not_full = wr_cur < 5'( __const__const_mem_size_at_update_wr_cur ); + if ( reset | clear ) begin + wr_cur <= 5'd0; + end + else if ( recv_const__val & __tmpvar__update_wr_cur_not_full ) begin + wr_cur <= wr_cur + 5'd1; + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + assign send_const__msg = reg_file__rdata[0]; + assign reg_file__raddr[0] = rd_cur; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__736a0143e1873b49 +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__66f570731410737c +( + input logic [0:0] clk , + input logic [0:0] raddr , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_msg , + input logic [0:0] reset , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__736a0143e1873b49 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__66f570731410737c +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__raddr; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a dpath__recv_msg; + logic [0:0] dpath__reset; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__66f570731410737c dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__nregs_16__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__46d8b36a7a21259f +( + input logic [0:0] clk , + input logic [3:0] raddr [0:0], + output CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 rdata [0:0], + input logic [0:0] reset , + input logic [3:0] waddr [0:0], + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 regs [0:15]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component CtrlMemDynamicRTL Definition +// Full name: CtrlMemDynamicRTL__IntraCgraPktType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ctrl_mem_size_16__num_fu_inports_4__num_fu_outports_2__num_tile_inports_4__num_tile_outports_4__num_cgras_4__num_tiles_16__ctrl_count_per_iter_4__total_ctrl_steps_38 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py + +module CtrlMemDynamicRTL__427d547b7d58aa8e +( + input logic [1:0] cgra_id , + input logic [0:0] clk , + output logic [3:0] ctrl_addr_outport , + output logic [2:0] prologue_count_outport_fu , + output logic [2:0] prologue_count_outport_fu_crossbar [0:15][0:1], + output logic [2:0] prologue_count_outport_routing_crossbar [0:15][0:3], + input logic [0:0] reset , + input logic [4:0] tile_id , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element__msg , + output logic [0:0] recv_from_element__rdy , + input logic [0:0] recv_from_element__val , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller__msg , + output logic [0:0] recv_pkt_from_controller__rdy , + input logic [0:0] recv_pkt_from_controller__val , + output CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 send_ctrl__msg , + input logic [0:0] send_ctrl__rdy , + output logic [0:0] send_ctrl__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_pkt_to_controller__msg , + input logic [0:0] send_pkt_to_controller__rdy , + output logic [0:0] send_pkt_to_controller__val , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_element__msg , + input logic [0:0] send_to_element__rdy , + output logic [0:0] send_to_element__val +); + localparam logic [2:0] __const__num_fu_inports_at_update_msg = 3'd4; + localparam logic [3:0] __const__num_routing_outports_at_update_msg = 4'd8; + localparam logic [1:0] __const__CMD_CONFIG = 2'd3; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; + localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; + localparam logic [1:0] __const__CMD_TERMINATE = 2'd2; + localparam logic [0:0] __const__CMD_PAUSE = 1'd1; + localparam logic [4:0] __const__CMD_PRESERVE = 5'd22; + localparam logic [3:0] __const__CMD_RESUME = 4'd15; + localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; + localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; + localparam logic [3:0] __const__CMD_CONFIG_CTRL_LOWER_BOUND = 4'd9; + localparam logic [4:0] __const__CMD_RECORD_PHI_ADDR = 5'd16; + localparam logic [4:0] __const__num_tiles_at_update_send_pkt_to_controller = 5'd16; + localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [4:0] __const__ctrl_mem_size_at_update_raddr_and_fu_prologue = 5'd16; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_outport = 5'd16; + localparam logic [2:0] __const__num_tile_inports_at_update_prologue_outport = 3'd4; + localparam logic [1:0] __const__num_fu_outports_at_update_prologue_outport = 2'd2; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_reg = 5'd16; + localparam logic [2:0] __const__num_tile_inports_at_update_prologue_reg = 3'd4; + localparam logic [1:0] __const__num_fu_outports_at_update_prologue_reg = 2'd2; + localparam logic [2:0] __const__ctrl_count_per_iter_at_update_ctrl_count_per_iter = 3'd4; + localparam logic [5:0] __const__total_ctrl_steps_at_update_total_ctrl_steps = 6'd38; + logic [3:0] ctrl_count_lower_bound; + logic [2:0] ctrl_count_per_iter_val; + logic [4:0] ctrl_count_upper_bound; + logic [2:0] prologue_count_reg_fu [0:15]; + logic [2:0] prologue_count_reg_fu_crossbar [0:15][0:1]; + logic [2:0] prologue_count_reg_routing_crossbar [0:15][0:3]; + logic [0:0] sent_complete; + logic [0:0] start_iterate_ctrl; + logic [10:0] times; + logic [10:0] total_ctrl_steps_val; + //------------------------------------------------------------- + // Component recv_from_element_queue + //------------------------------------------------------------- + + logic [0:0] recv_from_element_queue__clk; + logic [1:0] recv_from_element_queue__count; + logic [0:0] recv_from_element_queue__reset; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element_queue__recv__msg; + logic [0:0] recv_from_element_queue__recv__rdy; + logic [0:0] recv_from_element_queue__recv__val; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element_queue__send__msg; + logic [0:0] recv_from_element_queue__send__rdy; + logic [0:0] recv_from_element_queue__send__val; + + NormalQueueRTL__66f570731410737c recv_from_element_queue + ( + .clk( recv_from_element_queue__clk ), + .count( recv_from_element_queue__count ), + .reset( recv_from_element_queue__reset ), + .recv__msg( recv_from_element_queue__recv__msg ), + .recv__rdy( recv_from_element_queue__recv__rdy ), + .recv__val( recv_from_element_queue__recv__val ), + .send__msg( recv_from_element_queue__send__msg ), + .send__rdy( recv_from_element_queue__send__rdy ), + .send__val( recv_from_element_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_from_element_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component recv_pkt_from_controller_queue + //------------------------------------------------------------- + + logic [0:0] recv_pkt_from_controller_queue__clk; + logic [1:0] recv_pkt_from_controller_queue__count; + logic [0:0] recv_pkt_from_controller_queue__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller_queue__recv__msg; + logic [0:0] recv_pkt_from_controller_queue__recv__rdy; + logic [0:0] recv_pkt_from_controller_queue__recv__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller_queue__send__msg; + logic [0:0] recv_pkt_from_controller_queue__send__rdy; + logic [0:0] recv_pkt_from_controller_queue__send__val; + + NormalQueueRTL__a1c7a5a18a302c36 recv_pkt_from_controller_queue + ( + .clk( recv_pkt_from_controller_queue__clk ), + .count( recv_pkt_from_controller_queue__count ), + .reset( recv_pkt_from_controller_queue__reset ), + .recv__msg( recv_pkt_from_controller_queue__recv__msg ), + .recv__rdy( recv_pkt_from_controller_queue__recv__rdy ), + .recv__val( recv_pkt_from_controller_queue__recv__val ), + .send__msg( recv_pkt_from_controller_queue__send__msg ), + .send__rdy( recv_pkt_from_controller_queue__send__rdy ), + .send__val( recv_pkt_from_controller_queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component recv_pkt_from_controller_queue + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__46d8b36a7a21259f reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [2:0] __tmpvar__update_prologue_reg_temp_routing_crossbar_in; + logic [1:0] __tmpvar__update_prologue_reg_temp_fu_crossbar_in; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:157 + // @update + // def update_ctrl_addr_outport(): + // s.ctrl_addr_outport @= s.reg_file.raddr[0] + + always_comb begin : update_ctrl_addr_outport + ctrl_addr_outport = reg_file__raddr[1'd0]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:94 + // @update + // def update_msg(): + // s.recv_pkt_from_controller_queue.send.rdy @= 0 + // s.send_to_element.msg @= CgraPayloadType(0, 0, 0, 0, 0) + // s.send_to_element.val @= 0 + // s.reg_file.wen[0] @= 0 + // s.reg_file.waddr[0] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr + // # Initializes the fields of the control signal. + // s.reg_file.wdata[0].operation @= 0 + // for i in range(num_fu_inports): + // s.reg_file.wdata[0].fu_in[i] @= 0 + // s.reg_file.wdata[0].write_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_from[i] + // s.reg_file.wdata[0].write_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_idx[i] + // s.reg_file.wdata[0].read_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_from[i] + // s.reg_file.wdata[0].read_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_idx[i] + // for i in range(num_routing_outports): + // s.reg_file.wdata[0].routing_xbar_outport[i] @= 0 + // s.reg_file.wdata[0].fu_xbar_outport[i] @= 0 + // s.reg_file.wdata[0].vector_factor_power @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.vector_factor_power + // s.reg_file.wdata[0].is_last_ctrl @= 0 + // + // if s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG): + // s.reg_file.wen[0] @= 1 + // s.reg_file.waddr[0] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr + // # Fills the fields of the control signal. + // s.reg_file.wdata[0].operation @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.operation + // for i in range(num_fu_inports): + // s.reg_file.wdata[0].fu_in[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_in[i] + // s.reg_file.wdata[0].write_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_from[i] + // s.reg_file.wdata[0].write_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_idx[i] + // s.reg_file.wdata[0].read_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_from[i] + // s.reg_file.wdata[0].read_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_idx[i] + // for i in range(num_routing_outports): + // s.reg_file.wdata[0].routing_xbar_outport[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.routing_xbar_outport[i] + // s.reg_file.wdata[0].fu_xbar_outport[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_xbar_outport[i] + // s.reg_file.wdata[0].vector_factor_power @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.vector_factor_power + // s.reg_file.wdata[0].is_last_ctrl @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.is_last_ctrl + // elif s.recv_pkt_from_controller_queue.send.val & \ + // ((s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE)): + // s.send_to_element.msg @= s.recv_pkt_from_controller_queue.send.msg.payload + // s.send_to_element.val @= 1 + // + // if (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_PAUSE) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_PRESERVE) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RECORD_PHI_ADDR) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE): + // s.recv_pkt_from_controller_queue.send.rdy @= 1 + // # TODO: Extend for the other commands. Maybe another queue to + // # handle complicated actions. + // # else: + + always_comb begin : update_msg + recv_pkt_from_controller_queue__send__rdy = 1'd0; + send_to_element__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + send_to_element__val = 1'd0; + reg_file__wen[1'd0] = 1'd0; + reg_file__waddr[1'd0] = recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr; + reg_file__wdata[1'd0].operation = 7'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_fu_inports_at_update_msg ); i += 1'd1 ) begin + reg_file__wdata[1'd0].fu_in[2'(i)] = 3'd0; + reg_file__wdata[1'd0].write_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_from[2'(i)]; + reg_file__wdata[1'd0].write_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_idx[2'(i)]; + reg_file__wdata[1'd0].read_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_from[2'(i)]; + reg_file__wdata[1'd0].read_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_idx[2'(i)]; + end + for ( int unsigned i = 1'd0; i < 4'( __const__num_routing_outports_at_update_msg ); i += 1'd1 ) begin + reg_file__wdata[1'd0].routing_xbar_outport[3'(i)] = 3'd0; + reg_file__wdata[1'd0].fu_xbar_outport[3'(i)] = 2'd0; + end + reg_file__wdata[1'd0].vector_factor_power = recv_pkt_from_controller_queue__send__msg.payload.ctrl.vector_factor_power; + reg_file__wdata[1'd0].is_last_ctrl = 1'd0; + if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) ) begin + reg_file__wen[1'd0] = 1'd1; + reg_file__waddr[1'd0] = recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr; + reg_file__wdata[1'd0].operation = recv_pkt_from_controller_queue__send__msg.payload.ctrl.operation; + for ( int unsigned i = 1'd0; i < 3'( __const__num_fu_inports_at_update_msg ); i += 1'd1 ) begin + reg_file__wdata[1'd0].fu_in[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_in[2'(i)]; + reg_file__wdata[1'd0].write_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_from[2'(i)]; + reg_file__wdata[1'd0].write_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_idx[2'(i)]; + reg_file__wdata[1'd0].read_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_from[2'(i)]; + reg_file__wdata[1'd0].read_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_idx[2'(i)]; + end + for ( int unsigned i = 1'd0; i < 4'( __const__num_routing_outports_at_update_msg ); i += 1'd1 ) begin + reg_file__wdata[1'd0].routing_xbar_outport[3'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.routing_xbar_outport[3'(i)]; + reg_file__wdata[1'd0].fu_xbar_outport[3'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_xbar_outport[3'(i)]; + end + reg_file__wdata[1'd0].vector_factor_power = recv_pkt_from_controller_queue__send__msg.payload.ctrl.vector_factor_power; + reg_file__wdata[1'd0].is_last_ctrl = recv_pkt_from_controller_queue__send__msg.payload.ctrl.is_last_ctrl; + end + else if ( recv_pkt_from_controller_queue__send__val & ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) ) begin + send_to_element__msg = recv_pkt_from_controller_queue__send__msg.payload; + send_to_element__val = 1'd1; + end + if ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_PAUSE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_PRESERVE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RECORD_PHI_ADDR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) begin + recv_pkt_from_controller_queue__send__rdy = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:255 + // @update + // def update_prologue_outport(): + // s.prologue_count_outport_fu @= s.prologue_count_reg_fu[s.reg_file.raddr[0]] + // for addr in range(ctrl_mem_size): + // for i in range(num_tile_inports): + // s.prologue_count_outport_routing_crossbar[addr][i] @= \ + // s.prologue_count_reg_routing_crossbar[addr][i] + // for i in range(num_fu_outports): + // s.prologue_count_outport_fu_crossbar[addr][i] @= \ + // s.prologue_count_reg_fu_crossbar[addr][i] + + always_comb begin : update_prologue_outport + prologue_count_outport_fu = prologue_count_reg_fu[reg_file__raddr[1'd0]]; + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_outport ); addr += 1'd1 ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_tile_inports_at_update_prologue_outport ); i += 1'd1 ) + prologue_count_outport_routing_crossbar[4'(addr)][2'(i)] = prologue_count_reg_routing_crossbar[4'(addr)][2'(i)]; + for ( int unsigned i = 1'd0; i < 2'( __const__num_fu_outports_at_update_prologue_outport ); i += 1'd1 ) + prologue_count_outport_fu_crossbar[4'(addr)][1'(i)] = prologue_count_reg_fu_crossbar[4'(addr)][1'(i)]; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:181 + // @update + // def update_send_ctrl(): + // s.send_ctrl.val @= 0 + // if s.start_iterate_ctrl == b1(1): + // if s.sent_complete: + // s.send_ctrl.val @= 0 + // elif ((s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val)) | \ + // (s.reg_file.rdata[0].operation == OPT_START): + // s.send_ctrl.val @= b1(0) + // else: + // s.send_ctrl.val @= 1 + // if s.recv_pkt_from_controller_queue.send.val & \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE): + // s.send_ctrl.val @= b1(0) + + always_comb begin : update_send_ctrl + send_ctrl__val = 1'd0; + if ( start_iterate_ctrl == 1'd1 ) begin + if ( sent_complete ) begin + send_ctrl__val = 1'd0; + end + else if ( ( ( total_ctrl_steps_val > 11'd0 ) & ( times == total_ctrl_steps_val ) ) | ( reg_file__rdata[1'd0].operation == 7'( __const__OPT_START ) ) ) begin + send_ctrl__val = 1'd0; + end + else + send_ctrl__val = 1'd1; + end + if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) begin + send_ctrl__val = 1'd0; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:161 + // @update + // def update_send_pkt_to_controller(): + // s.send_pkt_to_controller.val @= 0 + // s.send_pkt_to_controller.msg @= IntraCgraPktType(0, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, CgraPayloadType(CMD_COMPLETE, 0, 0, 0, 0)) + // s.recv_from_element_queue.send.rdy @= 0 + // if s.start_iterate_ctrl == b1(1): + // if s.recv_from_element_queue.send.val & (~s.sent_complete): + // s.send_pkt_to_controller.msg @= \ + // IntraCgraPktType(s.tile_id, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, + // s.recv_from_element_queue.send.msg) + // s.send_pkt_to_controller.val @= 1 + // s.recv_from_element_queue.send.rdy @= s.send_pkt_to_controller.rdy + // elif ((s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val)) | \ + // (s.reg_file.rdata[0].operation == OPT_START): + // # Sends COMPLETE signal to Controller when the last ctrl signal is done. + // if ~s.sent_complete & (s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val) & s.start_iterate_ctrl: + // s.send_pkt_to_controller.msg @= \ + // IntraCgraPktType(s.tile_id, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, CgraPayloadType(CMD_COMPLETE, 0, 0, 0, 0)) + // s.send_pkt_to_controller.val @= 1 + + always_comb begin : update_send_pkt_to_controller + send_pkt_to_controller__val = 1'd0; + send_pkt_to_controller__msg = { 5'd0, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'( __const__CMD_COMPLETE ), 67'd0, 7'd0, 107'd0, 4'd0 } }; + recv_from_element_queue__send__rdy = 1'd0; + if ( start_iterate_ctrl == 1'd1 ) begin + if ( recv_from_element_queue__send__val & ( ~sent_complete ) ) begin + send_pkt_to_controller__msg = { tile_id, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, recv_from_element_queue__send__msg }; + send_pkt_to_controller__val = 1'd1; + recv_from_element_queue__send__rdy = send_pkt_to_controller__rdy; + end + else if ( ( ( total_ctrl_steps_val > 11'd0 ) & ( times == total_ctrl_steps_val ) ) | ( reg_file__rdata[1'd0].operation == 7'( __const__OPT_START ) ) ) begin + if ( ( ( ( ~sent_complete ) & ( total_ctrl_steps_val > 11'd0 ) ) & ( times == total_ctrl_steps_val ) ) & start_iterate_ctrl ) begin + send_pkt_to_controller__msg = { tile_id, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'( __const__CMD_COMPLETE ), 67'd0, 7'd0, 107'd0, 4'd0 } }; + send_pkt_to_controller__val = 1'd1; + end + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:298 + // @update + // def update_upper_bound(): + // s.ctrl_count_upper_bound @= zext(s.ctrl_count_lower_bound, UpperBoundType) + zext(s.ctrl_count_per_iter_val, UpperBoundType) + + always_comb begin : update_upper_bound + ctrl_count_upper_bound = { { 1 { 1'b0 } }, ctrl_count_lower_bound } + { { 2 { 1'b0 } }, ctrl_count_per_iter_val }; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:210 + // @update_ff + // def issue_complete(): + // if s.reset: + // s.sent_complete <<= 0 + // else: + // if s.send_pkt_to_controller.val & \ + // s.send_pkt_to_controller.rdy & \ + // (s.send_pkt_to_controller.msg.payload.cmd == CMD_COMPLETE): + // s.sent_complete <<= 1 + // elif s.recv_pkt_from_controller_queue.send.val & ( (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME) ): + // s.sent_complete <<= 0 + + always_ff @(posedge clk) begin : issue_complete + if ( reset ) begin + sent_complete <= 1'd0; + end + else if ( ( send_pkt_to_controller__val & send_pkt_to_controller__rdy ) & ( send_pkt_to_controller__msg.payload.cmd == 5'( __const__CMD_COMPLETE ) ) ) begin + sent_complete <= 1'd1; + end + else if ( recv_pkt_from_controller_queue__send__val & ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) ) begin + sent_complete <= 1'd0; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:284 + // @update_ff + // def update_ctrl_count_per_iter(): + // if s.reset: + // s.ctrl_count_per_iter_val <<= PCType(ctrl_count_per_iter) + // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER): + // s.ctrl_count_per_iter_val <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PCType) + + always_ff @(posedge clk) begin : update_ctrl_count_per_iter + if ( reset ) begin + ctrl_count_per_iter_val <= 3'd4; + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) begin + ctrl_count_per_iter_val <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:291 + // @update_ff + // def update_lower_bound(): + // if s.reset: + // s.ctrl_count_lower_bound <<= CtrlAddrType(0) + // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND): + // s.ctrl_count_lower_bound <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, CtrlAddrType) + + always_ff @(posedge clk) begin : update_lower_bound + if ( reset ) begin + ctrl_count_lower_bound <= 4'd0; + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) begin + ctrl_count_lower_bound <= 4'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:266 + // @update_ff + // def update_prologue_reg(): + // if s.reset: + // for addr in range(ctrl_mem_size): + // for i in range(num_tile_inports): + // s.prologue_count_reg_routing_crossbar[addr][i] <<= 0 + // for i in range(num_fu_outports): + // s.prologue_count_reg_fu_crossbar[addr][i] <<= 0 + // else: + // if s.recv_pkt_from_controller_queue.send.val & \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR): + // temp_routing_crossbar_in = s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.routing_xbar_outport[0] + // s.prologue_count_reg_routing_crossbar[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr][trunc(temp_routing_crossbar_in, TileInPortType)] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) + // elif s.recv_pkt_from_controller_queue.send.val & \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR): + // temp_fu_crossbar_in = s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_xbar_outport[0] + // s.prologue_count_reg_fu_crossbar[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr][trunc(temp_fu_crossbar_in, FuOutPortType)] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) + + always_ff @(posedge clk) begin : update_prologue_reg + if ( reset ) begin + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_reg ); addr += 1'd1 ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_tile_inports_at_update_prologue_reg ); i += 1'd1 ) + prologue_count_reg_routing_crossbar[4'(addr)][2'(i)] <= 3'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_fu_outports_at_update_prologue_reg ); i += 1'd1 ) + prologue_count_reg_fu_crossbar[4'(addr)][1'(i)] <= 3'd0; + end + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) begin + __tmpvar__update_prologue_reg_temp_routing_crossbar_in = recv_pkt_from_controller_queue__send__msg.payload.ctrl.routing_xbar_outport[3'd0]; + prologue_count_reg_routing_crossbar[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr][2'(__tmpvar__update_prologue_reg_temp_routing_crossbar_in)] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) begin + __tmpvar__update_prologue_reg_temp_fu_crossbar_in = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_xbar_outport[3'd0]; + prologue_count_reg_fu_crossbar[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr][1'(__tmpvar__update_prologue_reg_temp_fu_crossbar_in)] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:223 + // @update_ff + // def update_raddr_and_fu_prologue(): + // if s.reset: + // s.times <<= 0 + // s.reg_file.raddr[0] <<= 0 + // for i in range(ctrl_mem_size): + // s.prologue_count_reg_fu[i] <<= 0 + // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND): + // s.reg_file.raddr[0] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, CtrlAddrType) + // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE): + // s.times <<= TimeType(0) + // else: + // if s.recv_pkt_from_controller_queue.send.val & \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU): + // s.prologue_count_reg_fu[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr] <<= \ + // trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) + // + // if s.start_iterate_ctrl == b1(1): + // if ((s.total_ctrl_steps_val == 0) | \ + // (s.times < s.total_ctrl_steps_val)) & \ + // s.send_ctrl.rdy & s.send_ctrl.val: + // s.times <<= s.times + TimeType(1) + // + // # Reads the next ctrl signal only when the current one is done. + // if s.send_ctrl.rdy & s.send_ctrl.val: + // if zext(s.reg_file.raddr[0], UpperBoundType) == s.ctrl_count_upper_bound - UpperBoundType(1): + // s.reg_file.raddr[0] <<= s.ctrl_count_lower_bound + // else: + // s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + CtrlAddrType(1) + // if s.prologue_count_reg_fu[s.reg_file.raddr[0]] > 0: + // s.prologue_count_reg_fu[s.reg_file.raddr[0]] <<= s.prologue_count_reg_fu[s.reg_file.raddr[0]] - 1 + + always_ff @(posedge clk) begin : update_raddr_and_fu_prologue + if ( reset ) begin + times <= 11'd0; + reg_file__raddr[1'd0] <= 4'd0; + for ( int unsigned i = 1'd0; i < 5'( __const__ctrl_mem_size_at_update_raddr_and_fu_prologue ); i += 1'd1 ) + prologue_count_reg_fu[4'(i)] <= 3'd0; + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) begin + reg_file__raddr[1'd0] <= 4'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) begin + times <= 11'd0; + end + else begin + if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) begin + prologue_count_reg_fu[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + if ( start_iterate_ctrl == 1'd1 ) begin + if ( ( ( ( total_ctrl_steps_val == 11'd0 ) | ( times < total_ctrl_steps_val ) ) & send_ctrl__rdy ) & send_ctrl__val ) begin + times <= times + 11'd1; + end + if ( send_ctrl__rdy & send_ctrl__val ) begin + if ( { { 1 { 1'b0 } }, reg_file__raddr[1'd0] } == ( ctrl_count_upper_bound - 5'd1 ) ) begin + reg_file__raddr[1'd0] <= ctrl_count_lower_bound; + end + else + reg_file__raddr[1'd0] <= reg_file__raddr[1'd0] + 4'd1; + if ( prologue_count_reg_fu[reg_file__raddr[1'd0]] > 3'd0 ) begin + prologue_count_reg_fu[reg_file__raddr[1'd0]] <= prologue_count_reg_fu[reg_file__raddr[1'd0]] - 3'd1; + end + end + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:302 + // @update_ff + // def update_total_ctrl_steps(): + // if s.reset: + // s.total_ctrl_steps_val <<= TimeType(total_ctrl_steps) + // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT): + // s.total_ctrl_steps_val <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, TimeType) + + always_ff @(posedge clk) begin : update_total_ctrl_steps + if ( reset ) begin + total_ctrl_steps_val <= 11'd38; + end + else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) begin + total_ctrl_steps_val <= 11'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:196 + // @update_ff + // def update_whether_we_can_iterate_ctrl(): + // if s.reset: + // s.start_iterate_ctrl <<= 0 + // else: + // if s.recv_pkt_from_controller_queue.send.val: + // if (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ + // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME): + // s.start_iterate_ctrl <<= 1 + // # TODO: issue #191, stop iterate ctrl after 10 cycels during pausing status, + // # so as to clear channels safely. + // elif s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE: + // s.start_iterate_ctrl <<= 0 + + always_ff @(posedge clk) begin : update_whether_we_can_iterate_ctrl + if ( reset ) begin + start_iterate_ctrl <= 1'd0; + end + else if ( recv_pkt_from_controller_queue__send__val ) begin + if ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) begin + start_iterate_ctrl <= 1'd1; + end + else if ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) begin + start_iterate_ctrl <= 1'd0; + end + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + assign recv_pkt_from_controller_queue__clk = clk; + assign recv_pkt_from_controller_queue__reset = reset; + assign recv_from_element_queue__clk = clk; + assign recv_from_element_queue__reset = reset; + assign send_ctrl__msg = reg_file__rdata[0]; + assign recv_pkt_from_controller_queue__recv__msg = recv_pkt_from_controller__msg; + assign recv_pkt_from_controller__rdy = recv_pkt_from_controller_queue__recv__rdy; + assign recv_pkt_from_controller_queue__recv__val = recv_pkt_from_controller__val; + assign recv_from_element_queue__recv__msg = recv_from_element__msg; + assign recv_from_element__rdy = recv_from_element_queue__recv__rdy; + assign recv_from_element_queue__recv__val = recv_from_element__val; + +endmodule + + +// PyMTL Component AdderRTL Definition +// Full name: AdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py + +module AdderRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_ADD = 7'd2; + localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; + localparam logic [6:0] __const__OPT_INC = 7'd3; + localparam logic [6:0] __const__OPT_SUB = 7'd4; + localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; + localparam logic [6:0] __const__OPT_PAS = 7'd31; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py:45 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // s.in0 @= 0 + // s.in1 @= 0 + // # For pick input register + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // # Though different operations might not need to consume + // # all the operands, as long as the opcode indicating it + // # is an operand, the data would disappear from the register. + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != 0: + // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) + // if s.recv_opt.msg.fu_in[1] != 0: + // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_ADD: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_ADD_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // s.recv_const.rdy @= s.send_out[0].rdy + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_INC: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.const_one.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_PAS: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_const__msg.payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; + recv_const__rdy = send_out__rdy[1'd0]; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + 64'd1; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_const__msg.payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component MulRTL Definition +// Full name: MulRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_32 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py + +module MulRTL__903abe7e5de73fa1 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_MUL = 7'd7; + localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py:44 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != 0: + // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) + // if s.recv_opt.msg.fu_in[1] != 0: + // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_MUL: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_MUL_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_const__msg.payload; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component AdderRTL Definition +// Full name: AdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_32 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py + +module AdderRTL__903abe7e5de73fa1 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_ADD = 7'd2; + localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; + localparam logic [6:0] __const__OPT_INC = 7'd3; + localparam logic [6:0] __const__OPT_SUB = 7'd4; + localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; + localparam logic [6:0] __const__OPT_PAS = 7'd31; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py:45 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // s.in0 @= 0 + // s.in1 @= 0 + // # For pick input register + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // # Though different operations might not need to consume + // # all the operands, as long as the opcode indicating it + // # is an operand, the data would disappear from the register. + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != 0: + // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) + // if s.recv_opt.msg.fu_in[1] != 0: + // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_ADD: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_ADD_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // s.recv_const.rdy @= s.send_out[0].rdy + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_INC: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.const_one.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_PAS: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_const__msg.payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; + recv_const__rdy = send_out__rdy[1'd0]; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + 64'd1; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_const__msg.payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component SeqMulAdderRTL Definition +// Full name: SeqMulAdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/double/SeqMulAdderRTL.py + +module SeqMulAdderRTL__b741248a3a1dca5f +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_MUL_ADD = 7'd18; + localparam logic [6:0] __const__OPT_MUL = 7'd7; + localparam logic [6:0] __const__OPT_ADD = 7'd2; + localparam logic [6:0] __const__OPT_MUL_CONST_ADD = 7'd30; + localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; + localparam logic [6:0] __const__OPT_PAS = 7'd31; + localparam logic [6:0] __const__OPT_MUL_SUB = 7'd19; + localparam logic [6:0] __const__OPT_SUB = 7'd4; + localparam logic [6:0] __const__OPT_START = 7'd0; + //------------------------------------------------------------- + // Component Fu0 + //------------------------------------------------------------- + + logic [0:0] Fu0__clear; + logic [0:0] Fu0__clk; + logic [0:0] Fu0__reset; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__from_mem_rdata__msg; + logic [0:0] Fu0__from_mem_rdata__rdy; + logic [0:0] Fu0__from_mem_rdata__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__recv_const__msg; + logic [0:0] Fu0__recv_const__rdy; + logic [0:0] Fu0__recv_const__val; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu0__recv_from_ctrl_mem__msg; + logic [0:0] Fu0__recv_from_ctrl_mem__rdy; + logic [0:0] Fu0__recv_from_ctrl_mem__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__recv_in__msg [0:3]; + logic [0:0] Fu0__recv_in__rdy [0:3]; + logic [0:0] Fu0__recv_in__val [0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu0__recv_opt__msg; + logic [0:0] Fu0__recv_opt__rdy; + logic [0:0] Fu0__recv_opt__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__send_out__msg [0:1]; + logic [0:0] Fu0__send_out__rdy [0:1]; + logic [0:0] Fu0__send_out__val [0:1]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu0__send_to_ctrl_mem__msg; + logic [0:0] Fu0__send_to_ctrl_mem__rdy; + logic [0:0] Fu0__send_to_ctrl_mem__val; + logic [6:0] Fu0__to_mem_raddr__msg; + logic [0:0] Fu0__to_mem_raddr__rdy; + logic [0:0] Fu0__to_mem_raddr__val; + logic [6:0] Fu0__to_mem_waddr__msg; + logic [0:0] Fu0__to_mem_waddr__rdy; + logic [0:0] Fu0__to_mem_waddr__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__to_mem_wdata__msg; + logic [0:0] Fu0__to_mem_wdata__rdy; + logic [0:0] Fu0__to_mem_wdata__val; + + MulRTL__903abe7e5de73fa1 Fu0 + ( + .clear( Fu0__clear ), + .clk( Fu0__clk ), + .reset( Fu0__reset ), + .from_mem_rdata__msg( Fu0__from_mem_rdata__msg ), + .from_mem_rdata__rdy( Fu0__from_mem_rdata__rdy ), + .from_mem_rdata__val( Fu0__from_mem_rdata__val ), + .recv_const__msg( Fu0__recv_const__msg ), + .recv_const__rdy( Fu0__recv_const__rdy ), + .recv_const__val( Fu0__recv_const__val ), + .recv_from_ctrl_mem__msg( Fu0__recv_from_ctrl_mem__msg ), + .recv_from_ctrl_mem__rdy( Fu0__recv_from_ctrl_mem__rdy ), + .recv_from_ctrl_mem__val( Fu0__recv_from_ctrl_mem__val ), + .recv_in__msg( Fu0__recv_in__msg ), + .recv_in__rdy( Fu0__recv_in__rdy ), + .recv_in__val( Fu0__recv_in__val ), + .recv_opt__msg( Fu0__recv_opt__msg ), + .recv_opt__rdy( Fu0__recv_opt__rdy ), + .recv_opt__val( Fu0__recv_opt__val ), + .send_out__msg( Fu0__send_out__msg ), + .send_out__rdy( Fu0__send_out__rdy ), + .send_out__val( Fu0__send_out__val ), + .send_to_ctrl_mem__msg( Fu0__send_to_ctrl_mem__msg ), + .send_to_ctrl_mem__rdy( Fu0__send_to_ctrl_mem__rdy ), + .send_to_ctrl_mem__val( Fu0__send_to_ctrl_mem__val ), + .to_mem_raddr__msg( Fu0__to_mem_raddr__msg ), + .to_mem_raddr__rdy( Fu0__to_mem_raddr__rdy ), + .to_mem_raddr__val( Fu0__to_mem_raddr__val ), + .to_mem_waddr__msg( Fu0__to_mem_waddr__msg ), + .to_mem_waddr__rdy( Fu0__to_mem_waddr__rdy ), + .to_mem_waddr__val( Fu0__to_mem_waddr__val ), + .to_mem_wdata__msg( Fu0__to_mem_wdata__msg ), + .to_mem_wdata__rdy( Fu0__to_mem_wdata__rdy ), + .to_mem_wdata__val( Fu0__to_mem_wdata__val ) + ); + + //------------------------------------------------------------- + // End of component Fu0 + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component Fu1 + //------------------------------------------------------------- + + logic [0:0] Fu1__clear; + logic [0:0] Fu1__clk; + logic [0:0] Fu1__reset; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__from_mem_rdata__msg; + logic [0:0] Fu1__from_mem_rdata__rdy; + logic [0:0] Fu1__from_mem_rdata__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__recv_const__msg; + logic [0:0] Fu1__recv_const__rdy; + logic [0:0] Fu1__recv_const__val; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu1__recv_from_ctrl_mem__msg; + logic [0:0] Fu1__recv_from_ctrl_mem__rdy; + logic [0:0] Fu1__recv_from_ctrl_mem__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__recv_in__msg [0:3]; + logic [0:0] Fu1__recv_in__rdy [0:3]; + logic [0:0] Fu1__recv_in__val [0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu1__recv_opt__msg; + logic [0:0] Fu1__recv_opt__rdy; + logic [0:0] Fu1__recv_opt__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__send_out__msg [0:1]; + logic [0:0] Fu1__send_out__rdy [0:1]; + logic [0:0] Fu1__send_out__val [0:1]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu1__send_to_ctrl_mem__msg; + logic [0:0] Fu1__send_to_ctrl_mem__rdy; + logic [0:0] Fu1__send_to_ctrl_mem__val; + logic [6:0] Fu1__to_mem_raddr__msg; + logic [0:0] Fu1__to_mem_raddr__rdy; + logic [0:0] Fu1__to_mem_raddr__val; + logic [6:0] Fu1__to_mem_waddr__msg; + logic [0:0] Fu1__to_mem_waddr__rdy; + logic [0:0] Fu1__to_mem_waddr__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__to_mem_wdata__msg; + logic [0:0] Fu1__to_mem_wdata__rdy; + logic [0:0] Fu1__to_mem_wdata__val; + + AdderRTL__903abe7e5de73fa1 Fu1 + ( + .clear( Fu1__clear ), + .clk( Fu1__clk ), + .reset( Fu1__reset ), + .from_mem_rdata__msg( Fu1__from_mem_rdata__msg ), + .from_mem_rdata__rdy( Fu1__from_mem_rdata__rdy ), + .from_mem_rdata__val( Fu1__from_mem_rdata__val ), + .recv_const__msg( Fu1__recv_const__msg ), + .recv_const__rdy( Fu1__recv_const__rdy ), + .recv_const__val( Fu1__recv_const__val ), + .recv_from_ctrl_mem__msg( Fu1__recv_from_ctrl_mem__msg ), + .recv_from_ctrl_mem__rdy( Fu1__recv_from_ctrl_mem__rdy ), + .recv_from_ctrl_mem__val( Fu1__recv_from_ctrl_mem__val ), + .recv_in__msg( Fu1__recv_in__msg ), + .recv_in__rdy( Fu1__recv_in__rdy ), + .recv_in__val( Fu1__recv_in__val ), + .recv_opt__msg( Fu1__recv_opt__msg ), + .recv_opt__rdy( Fu1__recv_opt__rdy ), + .recv_opt__val( Fu1__recv_opt__val ), + .send_out__msg( Fu1__send_out__msg ), + .send_out__rdy( Fu1__send_out__rdy ), + .send_out__val( Fu1__send_out__val ), + .send_to_ctrl_mem__msg( Fu1__send_to_ctrl_mem__msg ), + .send_to_ctrl_mem__rdy( Fu1__send_to_ctrl_mem__rdy ), + .send_to_ctrl_mem__val( Fu1__send_to_ctrl_mem__val ), + .to_mem_raddr__msg( Fu1__to_mem_raddr__msg ), + .to_mem_raddr__rdy( Fu1__to_mem_raddr__rdy ), + .to_mem_raddr__val( Fu1__to_mem_raddr__val ), + .to_mem_waddr__msg( Fu1__to_mem_waddr__msg ), + .to_mem_waddr__rdy( Fu1__to_mem_waddr__rdy ), + .to_mem_waddr__val( Fu1__to_mem_waddr__val ), + .to_mem_wdata__msg( Fu1__to_mem_wdata__msg ), + .to_mem_wdata__rdy( Fu1__to_mem_wdata__rdy ), + .to_mem_wdata__val( Fu1__to_mem_wdata__val ) + ); + + //------------------------------------------------------------- + // End of component Fu1 + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:90 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= AddrType(0) + // s.to_mem_raddr.msg @= AddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/double/SeqMulAdderRTL.py:32 + // @update + // def update_opt(): + // + // s.Fu0.recv_opt.msg @= s.recv_opt.msg + // s.Fu1.recv_opt.msg @= s.recv_opt.msg + // + // s.Fu0.recv_opt.msg.fu_in[0] @= 1 + // s.Fu0.recv_opt.msg.fu_in[1] @= 2 + // s.Fu1.recv_opt.msg.fu_in[0] @= 1 + // s.Fu1.recv_opt.msg.fu_in[1] @= 2 + // + // if s.recv_opt.msg.operation == OPT_MUL_ADD: + // s.Fu0.recv_opt.msg.operation @= OPT_MUL + // s.Fu1.recv_opt.msg.operation @= OPT_ADD + // elif s.recv_opt.msg.operation == OPT_MUL_CONST_ADD: + // s.Fu0.recv_opt.msg.operation @= OPT_MUL_CONST + // s.Fu1.recv_opt.msg.operation @= OPT_ADD + // elif s.recv_opt.msg.operation == OPT_MUL_CONST: + // s.Fu0.recv_opt.msg.operation @= OPT_MUL_CONST + // s.Fu1.recv_opt.msg.operation @= OPT_PAS + // elif s.recv_opt.msg.operation == OPT_MUL_SUB: + // s.Fu0.recv_opt.msg.operation @= OPT_MUL + // s.Fu1.recv_opt.msg.operation @= OPT_SUB + // else: + // # Indicates no computation should happen no this fused FU. + // # This is necessary to avoid the OPT_MUL_CONST be executed + // # by both Mul and MulAdder. + // s.Fu0.recv_opt.msg.operation @= OPT_START + // s.Fu1.recv_opt.msg.operation @= OPT_START + // + // # TODO: need to handle the other cases + + always_comb begin : update_opt + Fu0__recv_opt__msg = recv_opt__msg; + Fu1__recv_opt__msg = recv_opt__msg; + Fu0__recv_opt__msg.fu_in[2'd0] = 3'd1; + Fu0__recv_opt__msg.fu_in[2'd1] = 3'd2; + Fu1__recv_opt__msg.fu_in[2'd0] = 3'd1; + Fu1__recv_opt__msg.fu_in[2'd1] = 3'd2; + if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_ADD ) ) begin + Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL ); + Fu1__recv_opt__msg.operation = 7'( __const__OPT_ADD ); + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST_ADD ) ) begin + Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL_CONST ); + Fu1__recv_opt__msg.operation = 7'( __const__OPT_ADD ); + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin + Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL_CONST ); + Fu1__recv_opt__msg.operation = 7'( __const__OPT_PAS ); + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_SUB ) ) begin + Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL ); + Fu1__recv_opt__msg.operation = 7'( __const__OPT_SUB ); + end + else begin + Fu0__recv_opt__msg.operation = 7'( __const__OPT_START ); + Fu1__recv_opt__msg.operation = 7'( __const__OPT_START ); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:100 + // @update + // def update_send_to_controller(): + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + + always_comb begin : update_send_to_controller + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:68 + // @update + // def update_signal(): + // + // s.recv_in[0].rdy @= s.Fu0.recv_in[0].rdy + // s.recv_in[1].rdy @= s.Fu0.recv_in[1].rdy + // s.recv_in[2].rdy @= s.Fu1.recv_in[1].rdy + // + // s.Fu0.recv_in[0].val @= s.recv_in[0].val + // s.Fu0.recv_in[1].val @= s.recv_in[1].val + // s.Fu1.recv_in[0].val @= s.Fu0.send_out[0].val + // s.Fu1.recv_in[1].val @= s.recv_in[2].val + // + // s.Fu0.recv_opt.val @= s.recv_opt.val + // s.Fu1.recv_opt.val @= s.recv_opt.val + // + // s.recv_opt.rdy @= s.Fu0.recv_opt.rdy & s.Fu1.recv_opt.rdy + // + // s.send_out[0].val @= s.Fu1.send_out[0].val + // + // s.Fu0.send_out[0].rdy @= s.Fu1.recv_in[0].rdy + // s.Fu1.send_out[0].rdy @= s.send_out[0].rdy + + always_comb begin : update_signal + recv_in__rdy[2'd0] = Fu0__recv_in__rdy[2'd0]; + recv_in__rdy[2'd1] = Fu0__recv_in__rdy[2'd1]; + recv_in__rdy[2'd2] = Fu1__recv_in__rdy[2'd1]; + Fu0__recv_in__val[2'd0] = recv_in__val[2'd0]; + Fu0__recv_in__val[2'd1] = recv_in__val[2'd1]; + Fu1__recv_in__val[2'd0] = Fu0__send_out__val[1'd0]; + Fu1__recv_in__val[2'd1] = recv_in__val[2'd2]; + Fu0__recv_opt__val = recv_opt__val; + Fu1__recv_opt__val = recv_opt__val; + recv_opt__rdy = Fu0__recv_opt__rdy & Fu1__recv_opt__rdy; + send_out__val[1'd0] = Fu1__send_out__val[1'd0]; + Fu0__send_out__rdy[1'd0] = Fu1__recv_in__rdy[2'd0]; + Fu1__send_out__rdy[1'd0] = send_out__rdy[1'd0]; + end + + assign Fu0__clk = clk; + assign Fu0__reset = reset; + assign Fu1__clk = clk; + assign Fu1__reset = reset; + assign Fu0__recv_in__msg[0] = recv_in__msg[0]; + assign Fu0__recv_in__msg[1] = recv_in__msg[1]; + assign Fu1__recv_in__msg[1] = recv_in__msg[2]; + assign Fu1__recv_in__msg[0] = Fu0__send_out__msg[0]; + assign send_out__msg[0] = Fu1__send_out__msg[0]; + assign Fu0__recv_const__msg = recv_const__msg; + assign recv_const__rdy = Fu0__recv_const__rdy; + assign Fu0__recv_const__val = recv_const__val; + +endmodule + + +// PyMTL Component VectorMulRTL Definition +// Full name: VectorMulRTL__bw_16__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulRTL.py + +module VectorMulRTL__848c3e0c53bb478c +( + input logic [0:0] clk , + input logic [0:0] reset , + input logic [31:0] recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input logic [31:0] recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output logic [31:0] send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] +); + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_MUL = 7'd7; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] recv_all_val; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulRTL.py:55 + // @update + // def comb_logic(): + // s.recv_all_val @= 0 + // # Picks input register. + // s.in0 @= FuInType(0) + // s.in1 @= FuInType(0) + // + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range( num_outports ): + // s.send_out[i].val @= b1(0) + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_MUL: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg * s.recv_in[s.in1_idx].msg + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = 32'd0; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin + send_out__msg[1'd0] = recv_in__msg[in0_idx] * recv_in__msg[in1_idx]; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component VectorMulComboRTL Definition +// Full name: VectorMulComboRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py + +module VectorMulComboRTL__e2d25a29972e2033 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [1:0] __const__num_outports_at_update_input_output = 2'd2; + localparam logic [2:0] __const__num_lanes_at_update_input_output = 3'd4; + localparam logic [6:0] __const__OPT_VEC_MUL = 7'd55; + localparam logic [4:0] __const__sub_bw_at_update_input_output = 5'd16; + localparam logic [5:0] __const__sub_bw_2_at_update_input_output = 6'd32; + localparam logic [5:0] __const__sub_bw_3_at_update_input_output = 6'd48; + localparam logic [6:0] __const__sub_bw_4_at_update_input_output = 7'd64; + localparam logic [6:0] __const__data_bitwidth_at_update_input_output = 7'd64; + localparam logic [6:0] __const__OPT_VEC_MUL_COMBINED = 7'd75; + localparam logic [2:0] __const__num_lanes_at_update_signal = 3'd4; + localparam logic [1:0] __const__num_outports_at_update_signal = 2'd2; + localparam logic [2:0] __const__num_lanes_at_update_opt = 3'd4; + localparam logic [6:0] __const__OPT_NAH = 7'd1; + localparam logic [6:0] __const__OPT_MUL = 7'd7; + logic [63:0] temp_result [0:3]; + //------------------------------------------------------------- + // Component Fu[0:3] + //------------------------------------------------------------- + + logic [0:0] Fu__clk [0:3]; + logic [0:0] Fu__reset [0:3]; + logic [31:0] Fu__recv_const__msg [0:3]; + logic [0:0] Fu__recv_const__rdy [0:3]; + logic [0:0] Fu__recv_const__val [0:3]; + logic [31:0] Fu__recv_in__msg [0:3][0:3]; + logic [0:0] Fu__recv_in__rdy [0:3][0:3]; + logic [0:0] Fu__recv_in__val [0:3][0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu__recv_opt__msg [0:3]; + logic [0:0] Fu__recv_opt__rdy [0:3]; + logic [0:0] Fu__recv_opt__val [0:3]; + logic [31:0] Fu__send_out__msg [0:3][0:1]; + logic [0:0] Fu__send_out__rdy [0:3][0:1]; + logic [0:0] Fu__send_out__val [0:3][0:1]; + + VectorMulRTL__848c3e0c53bb478c Fu__0 + ( + .clk( Fu__clk[0] ), + .reset( Fu__reset[0] ), + .recv_const__msg( Fu__recv_const__msg[0] ), + .recv_const__rdy( Fu__recv_const__rdy[0] ), + .recv_const__val( Fu__recv_const__val[0] ), + .recv_in__msg( Fu__recv_in__msg[0] ), + .recv_in__rdy( Fu__recv_in__rdy[0] ), + .recv_in__val( Fu__recv_in__val[0] ), + .recv_opt__msg( Fu__recv_opt__msg[0] ), + .recv_opt__rdy( Fu__recv_opt__rdy[0] ), + .recv_opt__val( Fu__recv_opt__val[0] ), + .send_out__msg( Fu__send_out__msg[0] ), + .send_out__rdy( Fu__send_out__rdy[0] ), + .send_out__val( Fu__send_out__val[0] ) + ); + + VectorMulRTL__848c3e0c53bb478c Fu__1 + ( + .clk( Fu__clk[1] ), + .reset( Fu__reset[1] ), + .recv_const__msg( Fu__recv_const__msg[1] ), + .recv_const__rdy( Fu__recv_const__rdy[1] ), + .recv_const__val( Fu__recv_const__val[1] ), + .recv_in__msg( Fu__recv_in__msg[1] ), + .recv_in__rdy( Fu__recv_in__rdy[1] ), + .recv_in__val( Fu__recv_in__val[1] ), + .recv_opt__msg( Fu__recv_opt__msg[1] ), + .recv_opt__rdy( Fu__recv_opt__rdy[1] ), + .recv_opt__val( Fu__recv_opt__val[1] ), + .send_out__msg( Fu__send_out__msg[1] ), + .send_out__rdy( Fu__send_out__rdy[1] ), + .send_out__val( Fu__send_out__val[1] ) + ); + + VectorMulRTL__848c3e0c53bb478c Fu__2 + ( + .clk( Fu__clk[2] ), + .reset( Fu__reset[2] ), + .recv_const__msg( Fu__recv_const__msg[2] ), + .recv_const__rdy( Fu__recv_const__rdy[2] ), + .recv_const__val( Fu__recv_const__val[2] ), + .recv_in__msg( Fu__recv_in__msg[2] ), + .recv_in__rdy( Fu__recv_in__rdy[2] ), + .recv_in__val( Fu__recv_in__val[2] ), + .recv_opt__msg( Fu__recv_opt__msg[2] ), + .recv_opt__rdy( Fu__recv_opt__rdy[2] ), + .recv_opt__val( Fu__recv_opt__val[2] ), + .send_out__msg( Fu__send_out__msg[2] ), + .send_out__rdy( Fu__send_out__rdy[2] ), + .send_out__val( Fu__send_out__val[2] ) + ); + + VectorMulRTL__848c3e0c53bb478c Fu__3 + ( + .clk( Fu__clk[3] ), + .reset( Fu__reset[3] ), + .recv_const__msg( Fu__recv_const__msg[3] ), + .recv_const__rdy( Fu__recv_const__rdy[3] ), + .recv_const__val( Fu__recv_const__val[3] ), + .recv_in__msg( Fu__recv_in__msg[3] ), + .recv_in__rdy( Fu__recv_in__rdy[3] ), + .recv_in__val( Fu__recv_in__val[3] ), + .recv_opt__msg( Fu__recv_opt__msg[3] ), + .recv_opt__rdy( Fu__recv_opt__rdy[3] ), + .recv_opt__val( Fu__recv_opt__val[3] ), + .send_out__msg( Fu__send_out__msg[3] ), + .send_out__rdy( Fu__send_out__rdy[3] ), + .send_out__val( Fu__send_out__val[3] ) + ); + + //------------------------------------------------------------- + // End of component Fu[0:3] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:80 + // @update + // def update_input_output(): + // + // # Initialization to avoid latches + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // + // s.send_out[0].val @= s.Fu[0].send_out[0].val & \ + // s.recv_opt.val + // s.send_out[0].msg.payload @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // + // s.recv_from_ctrl_mem.rdy @= 0 + // + // for i in range(num_lanes): + // s.temp_result[i] @= TempDataType(0) + // s.Fu[i].recv_in[0].msg @= 0 + // s.Fu[i].recv_in[1].msg @= 0 + // + // if s.recv_opt.msg.operation == OPT_VEC_MUL: + // # Connection: split into vectorized FUs + // s.Fu[0].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] + // s.Fu[0].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] + // s.Fu[1].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] + // s.Fu[1].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] + // s.Fu[2].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw_2:sub_bw_3] + // s.Fu[2].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw_2:sub_bw_3] + // s.Fu[3].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw_3:sub_bw_4] + // s.Fu[3].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw_3:sub_bw_4] + // + // for i in range(num_lanes): + // s.temp_result[i] @= TempDataType(0) + // s.temp_result[i][0:sub_bw_2] @= s.Fu[i].send_out[0].msg[0:sub_bw_2] + // + // s.send_out[0].msg.payload[0:data_bitwidth] @= \ + // (s.temp_result[3] << (sub_bw * 3)) + \ + // (s.temp_result[2] << (sub_bw * 2)) + \ + // (s.temp_result[1] << sub_bw) + \ + // s.temp_result[0] + // + // elif s.recv_opt.msg.operation == OPT_VEC_MUL_COMBINED: # with highest precision + // s.Fu[0].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] + // s.Fu[0].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] + // s.Fu[1].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] + // s.Fu[1].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] + // s.Fu[2].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] + // s.Fu[2].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] + // s.Fu[3].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] + // s.Fu[3].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] + // + // for i in range(num_lanes): + // s.temp_result[i] @= TempDataType(0) + // s.temp_result[i][0:sub_bw_2] @= s.Fu[i].send_out[0].msg[0:sub_bw_2] + // + // s.send_out[0].msg.payload[0:data_bitwidth] @= \ + // s.temp_result[0] + \ + // (s.temp_result[1] << sub_bw) + \ + // (s.temp_result[2] << sub_bw) + \ + // (s.temp_result[3] << (sub_bw * 2)) + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + + always_comb begin : update_input_output + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_input_output ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + send_out__val[1'd0] = Fu__send_out__val[2'd0][1'd0] & recv_opt__val; + send_out__msg[1'd0].payload = 64'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin + temp_result[2'(i)] = 64'd0; + Fu__recv_in__msg[2'(i)][2'd0] = 32'd0; + Fu__recv_in__msg[2'(i)][2'd1] = 32'd0; + end + if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL ) ) begin + Fu__recv_in__msg[2'd0][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd0][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd1][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + Fu__recv_in__msg[2'd1][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + Fu__recv_in__msg[2'd2][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd47:6'( __const__sub_bw_2_at_update_input_output )]; + Fu__recv_in__msg[2'd2][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd47:6'( __const__sub_bw_2_at_update_input_output )]; + Fu__recv_in__msg[2'd3][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd63:6'( __const__sub_bw_3_at_update_input_output )]; + Fu__recv_in__msg[2'd3][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd63:6'( __const__sub_bw_3_at_update_input_output )]; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin + temp_result[2'(i)] = 64'd0; + temp_result[2'(i)][6'd31:6'd0] = Fu__send_out__msg[2'(i)][1'd0][5'd31:5'd0]; + end + send_out__msg[1'd0].payload[6'd63:6'd0] = ( ( ( temp_result[2'd3] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd3 ) ) + ( temp_result[2'd2] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd2 ) ) ) + ( temp_result[2'd1] << 5'( __const__sub_bw_at_update_input_output ) ) ) + temp_result[2'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL_COMBINED ) ) begin + Fu__recv_in__msg[2'd0][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd0][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd1][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd1][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + Fu__recv_in__msg[2'd2][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + Fu__recv_in__msg[2'd2][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; + Fu__recv_in__msg[2'd3][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + Fu__recv_in__msg[2'd3][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin + temp_result[2'(i)] = 64'd0; + temp_result[2'(i)][6'd31:6'd0] = Fu__send_out__msg[2'(i)][1'd0][5'd31:5'd0]; + end + send_out__msg[1'd0].payload[6'd63:6'd0] = ( ( temp_result[2'd0] + ( temp_result[2'd1] << 5'( __const__sub_bw_at_update_input_output ) ) ) + ( temp_result[2'd2] << 5'( __const__sub_bw_at_update_input_output ) ) ) + ( temp_result[2'd3] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd2 ) ); + end + else + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_input_output ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:183 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= AddrType(0) + // s.to_mem_raddr.msg @= AddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:168 + // @update + // def update_opt(): + // s.send_out[0].msg.predicate @= b1(0) + // + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.fu_in[0] @= 1 + // s.Fu[i].recv_opt.msg.fu_in[1] @= 2 + // s.Fu[i].recv_opt.msg.operation @= OPT_NAH + // + // if (s.recv_opt.msg.operation == OPT_VEC_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_MUL_COMBINED): + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.operation @= OPT_MUL + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate + + always_comb begin : update_opt + send_out__msg[1'd0].predicate = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].fu_in[2'd0] = 3'd1; + Fu__recv_opt__msg[2'(i)].fu_in[2'd1] = 3'd2; + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_NAH ); + end + if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL_COMBINED ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_MUL ); + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:146 + // @update + // def update_signal(): + // s.recv_in[0].rdy @= s.Fu[0].recv_in[0].rdy + // s.recv_in[1].rdy @= s.Fu[0].recv_in[1].rdy + // + // for i in range(num_lanes): + // s.Fu[i].recv_opt.val @= s.recv_opt.val + // + // # Note that the predication for a combined FU should be identical/shareable, + // # which means the computation in different basic block cannot be combined. + // # s.Fu[i].recv_opt.msg.predicate = s.recv_opt.msg.predicate + // + // s.Fu[i].recv_in[0].val @= s.recv_in[0].val + // s.Fu[i].recv_in[1].val @= s.recv_in[1].val + // s.Fu[i].recv_const.val @= s.recv_const.val + // + // for j in range(num_outports): + // s.Fu[i].send_out[j].rdy @= s.send_out[j].rdy + // + // s.recv_const.rdy @= s.Fu[0].recv_const.rdy + // s.recv_opt.rdy @= s.send_out[0].rdy + + always_comb begin : update_signal + recv_in__rdy[2'd0] = Fu__recv_in__rdy[2'd0][2'd0]; + recv_in__rdy[2'd1] = Fu__recv_in__rdy[2'd0][2'd1]; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_signal ); i += 1'd1 ) begin + Fu__recv_opt__val[2'(i)] = recv_opt__val; + Fu__recv_in__val[2'(i)][2'd0] = recv_in__val[2'd0]; + Fu__recv_in__val[2'(i)][2'd1] = recv_in__val[2'd1]; + Fu__recv_const__val[2'(i)] = recv_const__val; + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_signal ); j += 1'd1 ) + Fu__send_out__rdy[2'(i)][1'(j)] = send_out__rdy[1'(j)]; + end + recv_const__rdy = Fu__recv_const__rdy[2'd0]; + recv_opt__rdy = send_out__rdy[1'd0]; + end + + assign Fu__clk[0] = clk; + assign Fu__reset[0] = reset; + assign Fu__clk[1] = clk; + assign Fu__reset[1] = reset; + assign Fu__clk[2] = clk; + assign Fu__reset[2] = reset; + assign Fu__clk[3] = clk; + assign Fu__reset[3] = reset; + +endmodule + + +// PyMTL Component VectorAdderRTL Definition +// Full name: VectorAdderRTL__bw_16__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderRTL.py + +module VectorAdderRTL__848c3e0c53bb478c +( + input logic [0:0] carry_in , + output logic [0:0] carry_out , + input logic [0:0] clk , + input logic [0:0] combine_adder , + input logic [0:0] reset , + input logic [16:0] recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input logic [16:0] recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output logic [16:0] send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] +); + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_ADD = 7'd2; + localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; + localparam logic [6:0] __const__OPT_INC = 7'd3; + localparam logic [6:0] __const__OPT_SUB = 7'd4; + localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; + localparam logic [6:0] __const__OPT_PAS = 7'd31; + localparam logic [4:0] __const__bw_at_comb_logic = 5'd16; + logic [16:0] carry_in_temp; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] recv_all_val; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderRTL.py:58 + // @update + // def comb_logic(): + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= b1(0) + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.carry_in_temp[0] @= s.carry_in & s.combine_adder + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_ADD: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.recv_in[s.in1_idx].msg + s.carry_in_temp + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_ADD_CONST: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.recv_const.msg + s.carry_in_temp + // s.recv_const.rdy @= s.send_out[0].rdy + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_INC: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.const_one + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - s.recv_in[s.in1_idx].msg - s.carry_in_temp + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_SUB_CONST: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - s.recv_const.msg - s.carry_in_temp + // s.recv_const.rdy @= s.send_out[0].rdy + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_PAS: + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + // + // s.carry_out @= s.send_out[0].msg[bw:bw+1] + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = 17'd0; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + carry_in_temp[5'd0] = carry_in & combine_adder; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin + send_out__msg[1'd0] = ( recv_in__msg[in0_idx] + recv_in__msg[in1_idx] ) + carry_in_temp; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin + send_out__msg[1'd0] = ( recv_in__msg[in0_idx] + recv_const__msg ) + carry_in_temp; + recv_const__rdy = send_out__rdy[1'd0]; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin + send_out__msg[1'd0] = recv_in__msg[in0_idx] + 17'd1; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin + send_out__msg[1'd0] = ( recv_in__msg[in0_idx] - recv_in__msg[in1_idx] ) - carry_in_temp; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin + send_out__msg[1'd0] = ( recv_in__msg[in0_idx] - recv_const__msg ) - carry_in_temp; + recv_const__rdy = send_out__rdy[1'd0]; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin + send_out__msg[1'd0] = recv_in__msg[in0_idx]; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + carry_out = send_out__msg[1'd0][5'd16:5'( __const__bw_at_comb_logic )]; + end + + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component VectorAdderComboRTL Definition +// Full name: VectorAdderComboRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py + +module VectorAdderComboRTL__e2d25a29972e2033 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [2:0] __const__num_lanes_at_update_signal = 3'd4; + localparam logic [1:0] __const__num_outports_at_update_signal = 2'd2; + localparam logic [1:0] __const__num_outports_at_update_opt = 2'd2; + localparam logic [2:0] __const__num_lanes_at_update_opt = 3'd4; + localparam logic [6:0] __const__OPT_NAH = 7'd1; + localparam logic [6:0] __const__OPT_VEC_ADD = 7'd51; + localparam logic [6:0] __const__OPT_VEC_ADD_COMBINED = 7'd71; + localparam logic [6:0] __const__OPT_ADD = 7'd2; + localparam logic [6:0] __const__OPT_VEC_SUB = 7'd53; + localparam logic [6:0] __const__OPT_VEC_SUB_COMBINED = 7'd73; + localparam logic [6:0] __const__OPT_SUB = 7'd4; + localparam logic [6:0] __const__OPT_VEC_ADD_CONST = 7'd52; + localparam logic [6:0] __const__OPT_VEC_ADD_CONST_COMBINED = 7'd72; + localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; + localparam logic [6:0] __const__OPT_VEC_SUB_CONST = 7'd54; + localparam logic [6:0] __const__OPT_VEC_SUB_CONST_COMBINED = 7'd74; + localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; + //------------------------------------------------------------- + // Component Fu[0:3] + //------------------------------------------------------------- + + logic [0:0] Fu__carry_in [0:3]; + logic [0:0] Fu__carry_out [0:3]; + logic [0:0] Fu__clk [0:3]; + logic [0:0] Fu__combine_adder [0:3]; + logic [0:0] Fu__reset [0:3]; + logic [16:0] Fu__recv_const__msg [0:3]; + logic [0:0] Fu__recv_const__rdy [0:3]; + logic [0:0] Fu__recv_const__val [0:3]; + logic [16:0] Fu__recv_in__msg [0:3][0:3]; + logic [0:0] Fu__recv_in__rdy [0:3][0:3]; + logic [0:0] Fu__recv_in__val [0:3][0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu__recv_opt__msg [0:3]; + logic [0:0] Fu__recv_opt__rdy [0:3]; + logic [0:0] Fu__recv_opt__val [0:3]; + logic [16:0] Fu__send_out__msg [0:3][0:1]; + logic [0:0] Fu__send_out__rdy [0:3][0:1]; + logic [0:0] Fu__send_out__val [0:3][0:1]; + + VectorAdderRTL__848c3e0c53bb478c Fu__0 + ( + .carry_in( Fu__carry_in[0] ), + .carry_out( Fu__carry_out[0] ), + .clk( Fu__clk[0] ), + .combine_adder( Fu__combine_adder[0] ), + .reset( Fu__reset[0] ), + .recv_const__msg( Fu__recv_const__msg[0] ), + .recv_const__rdy( Fu__recv_const__rdy[0] ), + .recv_const__val( Fu__recv_const__val[0] ), + .recv_in__msg( Fu__recv_in__msg[0] ), + .recv_in__rdy( Fu__recv_in__rdy[0] ), + .recv_in__val( Fu__recv_in__val[0] ), + .recv_opt__msg( Fu__recv_opt__msg[0] ), + .recv_opt__rdy( Fu__recv_opt__rdy[0] ), + .recv_opt__val( Fu__recv_opt__val[0] ), + .send_out__msg( Fu__send_out__msg[0] ), + .send_out__rdy( Fu__send_out__rdy[0] ), + .send_out__val( Fu__send_out__val[0] ) + ); + + VectorAdderRTL__848c3e0c53bb478c Fu__1 + ( + .carry_in( Fu__carry_in[1] ), + .carry_out( Fu__carry_out[1] ), + .clk( Fu__clk[1] ), + .combine_adder( Fu__combine_adder[1] ), + .reset( Fu__reset[1] ), + .recv_const__msg( Fu__recv_const__msg[1] ), + .recv_const__rdy( Fu__recv_const__rdy[1] ), + .recv_const__val( Fu__recv_const__val[1] ), + .recv_in__msg( Fu__recv_in__msg[1] ), + .recv_in__rdy( Fu__recv_in__rdy[1] ), + .recv_in__val( Fu__recv_in__val[1] ), + .recv_opt__msg( Fu__recv_opt__msg[1] ), + .recv_opt__rdy( Fu__recv_opt__rdy[1] ), + .recv_opt__val( Fu__recv_opt__val[1] ), + .send_out__msg( Fu__send_out__msg[1] ), + .send_out__rdy( Fu__send_out__rdy[1] ), + .send_out__val( Fu__send_out__val[1] ) + ); + + VectorAdderRTL__848c3e0c53bb478c Fu__2 + ( + .carry_in( Fu__carry_in[2] ), + .carry_out( Fu__carry_out[2] ), + .clk( Fu__clk[2] ), + .combine_adder( Fu__combine_adder[2] ), + .reset( Fu__reset[2] ), + .recv_const__msg( Fu__recv_const__msg[2] ), + .recv_const__rdy( Fu__recv_const__rdy[2] ), + .recv_const__val( Fu__recv_const__val[2] ), + .recv_in__msg( Fu__recv_in__msg[2] ), + .recv_in__rdy( Fu__recv_in__rdy[2] ), + .recv_in__val( Fu__recv_in__val[2] ), + .recv_opt__msg( Fu__recv_opt__msg[2] ), + .recv_opt__rdy( Fu__recv_opt__rdy[2] ), + .recv_opt__val( Fu__recv_opt__val[2] ), + .send_out__msg( Fu__send_out__msg[2] ), + .send_out__rdy( Fu__send_out__rdy[2] ), + .send_out__val( Fu__send_out__val[2] ) + ); + + VectorAdderRTL__848c3e0c53bb478c Fu__3 + ( + .carry_in( Fu__carry_in[3] ), + .carry_out( Fu__carry_out[3] ), + .clk( Fu__clk[3] ), + .combine_adder( Fu__combine_adder[3] ), + .reset( Fu__reset[3] ), + .recv_const__msg( Fu__recv_const__msg[3] ), + .recv_const__rdy( Fu__recv_const__rdy[3] ), + .recv_const__val( Fu__recv_const__val[3] ), + .recv_in__msg( Fu__recv_in__msg[3] ), + .recv_in__rdy( Fu__recv_in__rdy[3] ), + .recv_in__val( Fu__recv_in__val[3] ), + .recv_opt__msg( Fu__recv_opt__msg[3] ), + .recv_opt__rdy( Fu__recv_opt__rdy[3] ), + .recv_opt__val( Fu__recv_opt__val[3] ), + .send_out__msg( Fu__send_out__msg[3] ), + .send_out__rdy( Fu__send_out__rdy[3] ), + .send_out__val( Fu__send_out__val[3] ) + ); + + //------------------------------------------------------------- + // End of component Fu[0:3] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:158 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= AddrType(0) + // s.to_mem_raddr.msg @= AddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:108 + // @update + // def update_opt(): + // + // for j in range( num_outports ): + // s.send_out[j].val @= b1(0) + // s.send_out[j].msg.predicate @= b1(0) + // + // s.send_out[0].val @= s.Fu[0].send_out[0].val & \ + // s.recv_opt.val + // + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.fu_in[0] @= 1 + // s.Fu[i].recv_opt.msg.fu_in[1] @= 2 + // s.Fu[i].recv_opt.msg.operation @= OPT_NAH + // s.Fu[i].combine_adder @= 0 + // + // if ( s.recv_opt.msg.operation == OPT_VEC_ADD ) | \ + // ( s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED ): + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.operation @= OPT_ADD + // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED) + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate + // + // elif ( s.recv_opt.msg.operation == OPT_VEC_SUB ) | \ + // ( s.recv_opt.msg.operation == OPT_VEC_SUB_COMBINED ): + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.operation @= OPT_SUB + // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_SUB_COMBINED) + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate + // + // # elif ( s.recv_opt.msg.operation == OPT_VEC_ADD_CONST ) | \ + // # ( s.recv_opt.msg.operation == OPT_ADD_CONST ): + // elif (s.recv_opt.msg.operation == OPT_VEC_ADD_CONST) | \ + // (s.recv_opt.msg.operation == OPT_VEC_ADD_CONST_COMBINED): + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.operation @= OPT_ADD_CONST + // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED) + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate + // + // elif (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST ) | \ + // (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST_COMBINED ): + // for i in range(num_lanes): + // s.Fu[i].recv_opt.msg.operation @= OPT_SUB_CONST + // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST_COMBINED) + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + + always_comb begin : update_opt + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_opt ); j += 1'd1 ) begin + send_out__val[1'(j)] = 1'd0; + send_out__msg[1'(j)].predicate = 1'd0; + end + send_out__val[1'd0] = Fu__send_out__val[2'd0][1'd0] & recv_opt__val; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].fu_in[2'd0] = 3'd1; + Fu__recv_opt__msg[2'(i)].fu_in[2'd1] = 3'd2; + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_NAH ); + Fu__combine_adder[2'(i)] = 1'd0; + end + if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_ADD ); + Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ); + end + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_COMBINED ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_SUB ); + Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_COMBINED ); + end + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_CONST_COMBINED ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_ADD_CONST ); + Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ); + end + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST_COMBINED ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin + Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_SUB_CONST ); + Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST_COMBINED ); + end + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; + end + else + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_opt ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:82 + // @update + // def update_signal(): + // s.recv_in[0].rdy @= s.Fu[0].recv_in[0].rdy + // s.recv_in[1].rdy @= s.Fu[0].recv_in[1].rdy + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // + // s.recv_from_ctrl_mem.rdy @= 0 + // + // for i in range(num_lanes): + // s.Fu[i].recv_opt.val @= s.recv_opt.val + // + // for j in range(num_outports): + // s.Fu[i].send_out[j].rdy @= s.send_out[j].rdy + // + // s.Fu[i].recv_in[0].val @= s.recv_in[0].val + // s.Fu[i].recv_in[1].val @= s.recv_in[1].val + // s.Fu[i].recv_const.val @= s.recv_const.val + // + // # Note that the predication for a combined FU should be identical/shareable, + // # which means the computation in different basic block cannot be combined. + // # s.Fu[i].recv_opt.msg.predicate = s.recv_opt.msg.predicate + // s.recv_const.rdy @= s.Fu[0].recv_const.rdy + // s.recv_opt.rdy @= s.Fu[0].recv_opt.rdy + + always_comb begin : update_signal + recv_in__rdy[2'd0] = Fu__recv_in__rdy[2'd0][2'd0]; + recv_in__rdy[2'd1] = Fu__recv_in__rdy[2'd0][2'd1]; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_signal ); i += 1'd1 ) begin + Fu__recv_opt__val[2'(i)] = recv_opt__val; + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_signal ); j += 1'd1 ) + Fu__send_out__rdy[2'(i)][1'(j)] = send_out__rdy[1'(j)]; + Fu__recv_in__val[2'(i)][2'd0] = recv_in__val[2'd0]; + Fu__recv_in__val[2'(i)][2'd1] = recv_in__val[2'd1]; + Fu__recv_const__val[2'(i)] = recv_const__val; + end + recv_const__rdy = Fu__recv_const__rdy[2'd0]; + recv_opt__rdy = Fu__recv_opt__rdy[2'd0]; + end + + assign Fu__clk[0] = clk; + assign Fu__reset[0] = reset; + assign Fu__clk[1] = clk; + assign Fu__reset[1] = reset; + assign Fu__clk[2] = clk; + assign Fu__reset[2] = reset; + assign Fu__clk[3] = clk; + assign Fu__reset[3] = reset; + assign Fu__carry_in[0] = 1'd0; + assign Fu__carry_in[1] = Fu__carry_out[0]; + assign Fu__carry_in[2] = Fu__carry_out[1]; + assign Fu__carry_in[3] = Fu__carry_out[2]; + assign Fu__recv_in__msg[0][0][15:0] = recv_in__msg[0].payload[15:0]; + assign Fu__recv_in__msg[0][1][15:0] = recv_in__msg[1].payload[15:0]; + assign Fu__recv_const__msg[0][15:0] = recv_const__msg.payload[15:0]; + assign send_out__msg[0].payload[15:0] = Fu__send_out__msg[0][0][15:0]; + assign Fu__recv_in__msg[1][0][15:0] = recv_in__msg[0].payload[31:16]; + assign Fu__recv_in__msg[1][1][15:0] = recv_in__msg[1].payload[31:16]; + assign Fu__recv_const__msg[1][15:0] = recv_const__msg.payload[31:16]; + assign send_out__msg[0].payload[31:16] = Fu__send_out__msg[1][0][15:0]; + assign Fu__recv_in__msg[2][0][15:0] = recv_in__msg[0].payload[47:32]; + assign Fu__recv_in__msg[2][1][15:0] = recv_in__msg[1].payload[47:32]; + assign Fu__recv_const__msg[2][15:0] = recv_const__msg.payload[47:32]; + assign send_out__msg[0].payload[47:32] = Fu__send_out__msg[2][0][15:0]; + assign Fu__recv_in__msg[3][0][15:0] = recv_in__msg[0].payload[63:48]; + assign Fu__recv_in__msg[3][1][15:0] = recv_in__msg[1].payload[63:48]; + assign Fu__recv_const__msg[3][15:0] = recv_const__msg.payload[63:48]; + assign send_out__msg[0].payload[63:48] = Fu__send_out__msg[3][0][15:0]; + +endmodule + + +// PyMTL Component SumUnit Definition +// At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py + +module SumUnit__DataType_Bits64__num_inputs_4 +( + input logic [0:0] clk , + input logic [63:0] in_ [0:3], + output logic [63:0] out , + input logic [0:0] reset +); + logic [63:0] partial_sum [0:3]; + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py:37 + // s.out //= lambda: s.partial_sum[s.num_inputs-1] + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_out + out = partial_sum[3'd4 - 3'd1]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py:31 + // @update + // def up_sum(): + // s.partial_sum[0] @= s.in_[0] + // for i in range( 1, s.num_inputs ): + // s.partial_sum[i] @= s.partial_sum[i-1] + s.in_[i] + + always_comb begin : up_sum + partial_sum[2'd0] = in_[2'd0]; + for ( int unsigned i = 1'd1; i < 3'd4; i += 1'd1 ) + partial_sum[2'(i)] = partial_sum[2'(i) - 2'd1] + in_[2'(i)]; + end + +endmodule + + +// PyMTL Component ReduceMulUnit Definition +// At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/ReduceMulUnit.py + +module ReduceMulUnit__DataType_Bits64__num_inputs_4 +( + input logic [0:0] clk , + input logic [63:0] in_ [0:3], + output logic [63:0] out , + input logic [0:0] reset +); + logic [63:0] partial_sum [0:3]; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/ReduceMulUnit.py:32 + // @update + // def up_sum(): + // s.partial_sum[0] @= s.in_[0] + // for i in range( 1, s.num_inputs ): + // s.partial_sum[i] @= s.partial_sum[i-1] * s.in_[i] + + always_comb begin : up_sum + partial_sum[2'd0] = in_[2'd0]; + for ( int unsigned i = 1'd1; i < 3'd4; i += 1'd1 ) + partial_sum[2'(i)] = partial_sum[2'(i) - 2'd1] * in_[2'(i)]; + end + + assign out = partial_sum[3]; + +endmodule + + +// PyMTL Component VectorAllReduceRTL Definition +// Full name: VectorAllReduceRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py + +module VectorAllReduceRTL__e2d25a29972e2033 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD = 7'd56; + localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_BASE = 7'd68; + localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_GLOBAL = 7'd76; + localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL = 7'd78; + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ = 1'd0; + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ = 1'd1; + localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ = 2'd2; + localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ = 2'd3; + localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL = 7'd57; + localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_BASE = 7'd69; + localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_GLOBAL = 7'd77; + localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL = 7'd79; + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ = 1'd0; + localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ = 1'd1; + localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ = 2'd2; + localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ = 2'd3; + localparam logic [6:0] __const__data_bitwidth_at_update_result = 7'd64; + localparam logic [2:0] __const__num_inports_at_update_signal = 3'd4; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL = 5'd19; + logic [0:0] already_sent_to_controller; + logic [63:0] temp_result [0:3]; + //------------------------------------------------------------- + // Component reduce_add + //------------------------------------------------------------- + + logic [0:0] reduce_add__clk; + logic [63:0] reduce_add__in_ [0:3]; + logic [63:0] reduce_add__out; + logic [0:0] reduce_add__reset; + + SumUnit__DataType_Bits64__num_inputs_4 reduce_add + ( + .clk( reduce_add__clk ), + .in_( reduce_add__in_ ), + .out( reduce_add__out ), + .reset( reduce_add__reset ) + ); + + //------------------------------------------------------------- + // End of component reduce_add + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component reduce_mul + //------------------------------------------------------------- + + logic [0:0] reduce_mul__clk; + logic [63:0] reduce_mul__in_ [0:3]; + logic [63:0] reduce_mul__out; + logic [0:0] reduce_mul__reset; + + ReduceMulUnit__DataType_Bits64__num_inputs_4 reduce_mul + ( + .clk( reduce_mul__clk ), + .in_( reduce_mul__in_ ), + .out( reduce_mul__out ), + .reset( reduce_mul__reset ) + ); + + //------------------------------------------------------------- + // End of component reduce_mul + //------------------------------------------------------------- + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 + // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ + reduce_add__in_[2'd0] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 + // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ + reduce_add__in_[2'd1] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 + // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ + reduce_add__in_[2'd2] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 + // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ + reduce_add__in_[2'd3] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 + // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ + reduce_mul__in_[2'd0] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 + // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ + reduce_mul__in_[2'd1] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 + // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ + reduce_mul__in_[2'd2] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ )] : 64'd0; + end + + // PyMTL Lambda Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 + // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) + + always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ + reduce_mul__in_[2'd3] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ )] : 64'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:234 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:195 + // @update + // def update_predicate(): + // s.send_out[0].msg.predicate @= 0 + // if ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL)): + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate + // elif ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)): + // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & \ + // s.recv_in[1].msg.predicate + // elif ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)): + // s.send_out[0].msg.predicate @= s.recv_from_ctrl_mem.msg.data.predicate & \ + // s.recv_in[1].msg.predicate + + always_comb begin : update_predicate + send_out__msg[1'd0].predicate = 1'd0; + if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) begin + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) begin + send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) begin + send_out__msg[1'd0].predicate = recv_from_ctrl_mem__msg.data.predicate & recv_in__msg[2'd1].predicate; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:95 + // @update + // def update_result(): + // # Connection: splits data into vectorized wires. + // s.send_out[0].msg.payload @= 0 + // + // if s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_add.out + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_add.out + s.recv_in[1].msg.payload + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_mul.out + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_mul.out * s.recv_in[1].msg.payload + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] + s.recv_in[1].msg.payload + // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL: + // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] * s.recv_in[1].msg.payload + + always_comb begin : update_result + send_out__msg[1'd0].payload = 64'd0; + if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_add__out; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_add__out + recv_in__msg[2'd1].payload; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_mul__out; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_mul__out * recv_in__msg[2'd1].payload; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0] + recv_in__msg[2'd1].payload; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) begin + send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0] * recv_in__msg[2'd1].payload; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:117 + // @update + // def update_signal(): + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // + // s.recv_from_ctrl_mem.rdy @= 0 + // + // s.recv_in[0].rdy @= (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)) & \ + // s.send_out[0].rdy) | \ + // (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ + // s.send_to_ctrl_mem.rdy) + // s.recv_opt.rdy @= s.send_out[0].rdy + // s.recv_in[1].rdy @= (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)) & \ + // s.send_out[0].rdy) | \ + // (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ + // s.send_to_ctrl_mem.rdy) + // s.send_out[0].val @= (s.recv_in[0].val & \ + // s.recv_opt.val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL))) | \ + // (s.recv_in[0].val & \ + // s.recv_in[1].val & \ + // s.recv_opt.val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE))) | \ + // (s.recv_opt.val & \ + // s.recv_from_ctrl_mem.val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL))) | \ + // (s.recv_opt.val & \ + // s.recv_from_ctrl_mem.val & \ + // s.recv_in[1].val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL))) + // + // if s.recv_opt.val & \ + // ~s.already_sent_to_controller & \ + // (s.recv_in[0].val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL))) | \ + // (s.recv_in[0].val & \ + // s.recv_in[1].val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL))): + // s.send_to_ctrl_mem.val @= 1 + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL): + // s.send_to_ctrl_mem.msg @= \ + // s.CgraPayloadType(CMD_GLOBAL_REDUCE_ADD, + // DataType(s.reduce_add.out, + // s.recv_in[0].msg.predicate, 0, 0), + // 0, + // s.recv_opt.msg, + // 0) + // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL): + // s.send_to_ctrl_mem.msg @= \ + // s.CgraPayloadType(CMD_GLOBAL_REDUCE_MUL, + // DataType(s.reduce_add.out, + // s.recv_in[0].msg.predicate, 0, 0), + // 0, + // s.recv_opt.msg, + // 0) + // + // if s.recv_opt.val & s.already_sent_to_controller: + // s.recv_from_ctrl_mem.rdy @= 1 + + always_comb begin : update_signal + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + recv_in__rdy[2'd0] = ( ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) & send_out__rdy[1'd0] ) | ( ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) & send_to_ctrl_mem__rdy ); + recv_opt__rdy = send_out__rdy[1'd0]; + recv_in__rdy[2'd1] = ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) & send_out__rdy[1'd0] ) | ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) & send_to_ctrl_mem__rdy ); + send_out__val[1'd0] = ( ( ( ( recv_in__val[2'd0] & recv_opt__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) ) | ( ( ( recv_in__val[2'd0] & recv_in__val[2'd1] ) & recv_opt__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) ) ) | ( ( recv_opt__val & recv_from_ctrl_mem__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) ) ) | ( ( ( recv_opt__val & recv_from_ctrl_mem__val ) & recv_in__val[2'd1] ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ); + if ( ( ( recv_opt__val & ( ~already_sent_to_controller ) ) & ( recv_in__val[2'd0] & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) ) ) | ( ( recv_in__val[2'd0] & recv_in__val[2'd1] ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) ) begin + send_to_ctrl_mem__val = 1'd1; + if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) begin + send_to_ctrl_mem__msg = { 5'( __const__CMD_GLOBAL_REDUCE_ADD ), { reduce_add__out, recv_in__msg[2'd0].predicate, 1'd0, 1'd0 }, 7'd0, recv_opt__msg, 4'd0 }; + end + if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) begin + send_to_ctrl_mem__msg = { 5'( __const__CMD_GLOBAL_REDUCE_MUL ), { reduce_add__out, recv_in__msg[2'd0].predicate, 1'd0, 1'd0 }, 7'd0, recv_opt__msg, 4'd0 }; + end + end + if ( recv_opt__val & already_sent_to_controller ) begin + recv_from_ctrl_mem__rdy = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:210 + // @update_ff + // def update_already_sent_to_controller(): + // if s.reset: + // s.already_sent_to_controller <<= 0 + // else: + // if s.recv_opt.val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ + // ~s.already_sent_to_controller & \ + // s.send_to_ctrl_mem.val & \ + // s.send_to_ctrl_mem.rdy: + // s.already_sent_to_controller <<= 1 + // # Recovers already_sent_to_controller once the ctrl proceeds to the next one. + // elif s.recv_opt.val & \ + // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ + // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ + // s.already_sent_to_controller & \ + // s.recv_opt.rdy: + // s.already_sent_to_controller <<= 0 + + always_ff @(posedge clk) begin : update_already_sent_to_controller + if ( reset ) begin + already_sent_to_controller <= 1'd0; + end + else if ( ( ( ( recv_opt__val & ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) & ( ~already_sent_to_controller ) ) & send_to_ctrl_mem__val ) & send_to_ctrl_mem__rdy ) begin + already_sent_to_controller <= 1'd1; + end + else if ( ( ( recv_opt__val & ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) & already_sent_to_controller ) & recv_opt__rdy ) begin + already_sent_to_controller <= 1'd0; + end + end + + assign reduce_add__clk = clk; + assign reduce_add__reset = reset; + assign reduce_mul__clk = clk; + assign reduce_mul__reset = reset; + assign temp_result[0][15:0] = recv_in__msg[0].payload[15:0]; + assign temp_result[0][63:16] = 48'd0; + assign temp_result[1][15:0] = recv_in__msg[0].payload[31:16]; + assign temp_result[1][63:16] = 48'd0; + assign temp_result[2][15:0] = recv_in__msg[0].payload[47:32]; + assign temp_result[2][63:16] = 48'd0; + assign temp_result[3][15:0] = recv_in__msg[0].payload[63:48]; + assign temp_result[3][63:16] = 48'd0; + +endmodule + + +// PyMTL Component NahRTL Definition +// Full name: NahRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/NahRTL.py + +module NahRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_NAH = 7'd1; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/NahRTL.py:28 + // @update + // def comb_logic(): + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // # For pick input register + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // + // for i in range( num_outports ): + // # s.send_out[i].val @= s.recv_opt.val + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val & (s.recv_opt.msg.operation == OPT_NAH): + // s.recv_opt.rdy @= 1 + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + + always_comb begin : comb_logic + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val & ( recv_opt__msg.operation == 7'( __const__OPT_NAH ) ) ) begin + recv_opt__rdy = 1'd1; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + +endmodule + + +// PyMTL Component MulRTL Definition +// Full name: MulRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py + +module MulRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_MUL = 7'd7; + localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py:44 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != 0: + // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) + // if s.recv_opt.msg.fu_in[1] != 0: + // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_MUL: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_MUL_CONST: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_const.msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_const__msg.payload; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component LogicRTL Definition +// Full name: LogicRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/LogicRTL.py + +module LogicRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_OR = 7'd8; + localparam logic [6:0] __const__OPT_AND = 7'd10; + localparam logic [6:0] __const__OPT_BIT_NOT = 7'd43; + localparam logic [6:0] __const__OPT_NOT = 7'd11; + localparam logic [6:0] __const__OPT_XOR = 7'd9; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/LogicRTL.py:44 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range( num_outports ): + // s.send_out[i].val @= b1(0) + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_OR: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload | s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_AND: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload & s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_BIT_NOT: + // s.send_out[0].msg.payload @= ~ s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_NOT: + // if s.recv_in[s.in0_idx].msg.payload == 0: + // s.send_out[0].msg.payload @= 1 + // else: + // s.send_out[0].msg.payload @= 0 + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_XOR: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload ^ s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_OR ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload | recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_AND ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload & recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_BIT_NOT ) ) begin + send_out__msg[1'd0].payload = ~recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_NOT ) ) begin + if ( recv_in__msg[in0_idx].payload == 64'd0 ) begin + send_out__msg[1'd0].payload = 64'd1; + end + else + send_out__msg[1'd0].payload = 64'd0; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_XOR ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload ^ recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component ShifterRTL Definition +// Full name: ShifterRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/ShifterRTL.py + +module ShifterRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_LLS = 7'd5; + localparam logic [6:0] __const__OPT_LRS = 7'd6; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/ShifterRTL.py:44 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= FuInType(0) + // s.in1 @= FuInType(0) + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_LLS: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload << s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_LRS: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload >> s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_LLS ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload << recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_LRS ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload >> recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component PhiRTL Definition +// Full name: PhiRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py + +module PhiRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_PHI = 7'd17; + localparam logic [6:0] __const__OPT_PHI_START = 7'd84; + localparam logic [6:0] __const__OPT_PHI_CONST = 7'd32; + logic [0:0] first; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py:48 + // @update + // def comb_logic(): + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // # TODO: decision needs to be made. Adder could be in FU vector width. Or only effective once on the boundary. + // # if s.recv_opt.val: + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_PHI: + // if s.recv_in[s.in0_idx].msg.predicate == Bits1(1): + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // elif s.recv_in[s.in1_idx].msg.predicate == Bits1(1): + // s.send_out[0].msg.payload @= s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // else: # No predecessor is active. + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= 0 + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_PHI_START: + // if s.first: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // elif s.recv_in[s.in0_idx].msg.predicate == Bits1(1): + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // elif s.recv_in[s.in1_idx].msg.predicate == Bits1(1): + // s.send_out[0].msg.payload @= s.recv_in[s.in1_idx].msg.payload + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // else: # No predecessor is active. + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // s.send_out[0].msg.predicate @= 0 + // s.recv_all_val @= ((s.first & s.recv_in[s.in0_idx].val) | \ + // (~s.first & s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val)) + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= ~s.first & s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_PHI_CONST: + // if s.first: + // s.send_out[0].msg.payload @= s.recv_const.msg.payload + // else: + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // + // s.recv_all_val @= ((s.first & s.recv_const.val) | \ + // (~s.first & s.recv_in[s.in0_idx].val)) + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // if s.first: + // s.send_out[0].msg.predicate @= s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // else: + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_PHI ) ) begin + if ( recv_in__msg[in0_idx].predicate == 1'd1 ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = reached_vector_factor; + end + else if ( recv_in__msg[in1_idx].predicate == 1'd1 ) begin + send_out__msg[1'd0].payload = recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = reached_vector_factor; + end + else begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = 1'd0; + end + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_PHI_START ) ) begin + if ( first ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = reached_vector_factor; + end + else if ( recv_in__msg[in0_idx].predicate == 1'd1 ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = reached_vector_factor; + end + else if ( recv_in__msg[in1_idx].predicate == 1'd1 ) begin + send_out__msg[1'd0].payload = recv_in__msg[in1_idx].payload; + send_out__msg[1'd0].predicate = reached_vector_factor; + end + else begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + send_out__msg[1'd0].predicate = 1'd0; + end + recv_all_val = ( first & recv_in__val[in0_idx] ) | ( ( ( ~first ) & recv_in__val[in0_idx] ) & recv_in__val[in1_idx] ); + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = ( ( ~first ) & recv_all_val ) & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_PHI_CONST ) ) begin + if ( first ) begin + send_out__msg[1'd0].payload = recv_const__msg.payload; + end + else + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + recv_all_val = ( first & recv_const__val ) | ( ( ~first ) & recv_in__val[in0_idx] ); + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + if ( first ) begin + send_out__msg[1'd0].predicate = recv_const__msg.predicate & reached_vector_factor; + end + else + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py:141 + // @update_ff + // def br_start_once(): + // if s.reset | s.clear: + // s.first <<= b1(1) + // if ((s.recv_opt.msg.operation == OPT_PHI_CONST) | (s.recv_opt.msg.operation == OPT_PHI_START)) & s.reached_vector_factor: + // s.first <<= b1(0) + + always_ff @(posedge clk) begin : br_start_once + if ( reset | clear ) begin + first <= 1'd1; + end + if ( ( ( recv_opt__msg.operation == 7'( __const__OPT_PHI_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_PHI_START ) ) ) & reached_vector_factor ) begin + first <= 1'd0; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component CompRTL Definition +// Full name: CompRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/CompRTL.py + +module CompRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_one = { 64'd1, 1'd0, 1'd0, 1'd0 }; + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_read_reg = 3'd4; + localparam logic [1:0] __const__num_outports_at_read_reg = 2'd2; + localparam logic [6:0] __const__OPT_EQ = 7'd14; + localparam logic [6:0] __const__OPT_NE = 7'd45; + localparam logic [6:0] __const__OPT_EQ_CONST = 7'd33; + localparam logic [6:0] __const__OPT_NE_CONST = 7'd46; + localparam logic [6:0] __const__OPT_LT = 7'd60; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/CompRTL.py:48 + // @update + // def read_reg(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= FuInType(0) + // s.in1 @= FuInType(0) + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType( 0 ): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if (s.recv_opt.msg.operation == OPT_EQ) | (s.recv_opt.msg.operation == OPT_NE): + // if (s.recv_opt.msg.operation == OPT_EQ) & \ + // (s.recv_in[s.in0_idx].msg.payload == s.recv_in[s.in1_idx].msg.payload): + // s.send_out[0].msg @= s.const_one + // elif (s.recv_opt.msg.operation == OPT_NE) & \ + // (s.recv_in[s.in0_idx].msg.payload != s.recv_in[s.in1_idx].msg.payload): + // s.send_out[0].msg @= s.const_one + // else: + // s.send_out[0].msg @= s.const_zero + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif (s.recv_opt.msg.operation == OPT_EQ_CONST) | (s.recv_opt.msg.operation == OPT_NE_CONST): + // if (s.recv_opt.msg.operation == OPT_EQ_CONST) & \ + // (s.recv_in[s.in0_idx].msg.payload == s.recv_const.msg.payload): + // s.send_out[0].msg @= s.const_one + // elif (s.recv_opt.msg.operation == OPT_NE_CONST) & \ + // (s.recv_in[s.in0_idx].msg.payload != s.recv_const.msg.payload): + // s.send_out[0].msg @= s.const_one + // else: + // s.send_out[0].msg @= s.const_zero + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // elif s.recv_opt.msg.operation == OPT_LT: + // if s.recv_in[s.in0_idx].msg.payload < s.recv_in[s.in1_idx].msg.payload: + // s.send_out[0].msg @= s.const_one + // else: + // s.send_out[0].msg @= s.const_zero + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : read_reg + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_read_reg ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_read_reg ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_NE ) ) ) begin + if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ ) ) & ( recv_in__msg[in0_idx].payload == recv_in__msg[in1_idx].payload ) ) begin + send_out__msg[1'd0] = const_one; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_NE ) ) & ( recv_in__msg[in0_idx].payload != recv_in__msg[in1_idx].payload ) ) begin + send_out__msg[1'd0] = const_one; + end + else + send_out__msg[1'd0] = const_zero; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_NE_CONST ) ) ) begin + if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ_CONST ) ) & ( recv_in__msg[in0_idx].payload == recv_const__msg.payload ) ) begin + send_out__msg[1'd0] = const_one; + end + else if ( ( recv_opt__msg.operation == 7'( __const__OPT_NE_CONST ) ) & ( recv_in__msg[in0_idx].payload != recv_const__msg.payload ) ) begin + send_out__msg[1'd0] = const_one; + end + else + send_out__msg[1'd0] = const_zero; + send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_LT ) ) begin + if ( recv_in__msg[in0_idx].payload < recv_in__msg[in1_idx].payload ) begin + send_out__msg[1'd0] = const_one; + end + else + send_out__msg[1'd0] = const_zero; + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_read_reg ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component GrantRTL Definition +// Full name: GrantRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py + +module GrantRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_GRT_PRED = 7'd16; + localparam logic [6:0] __const__OPT_GRT_ALWAYS = 7'd34; + localparam logic [6:0] __const__OPT_GRT_ONCE = 7'd47; + logic [0:0] already_grt_once; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py:46 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= 0 + // s.in1 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= b1(0) + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_GRT_PRED: + // # GRANT_PREDICATE is used to apply (`and` operation) predicate onto a value. + // # The second operand would be used/treated as the predicate condition that + // # is usually coming from a `cmp` operation. + // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + // # Only updates predicate if the condition is true. Note that we respect + // # condition's (operand_1's) both value and predicate. + // if s.recv_in[s.in1_idx].msg.payload != s.const_zero.payload: + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // elif s.recv_opt.msg.operation == OPT_GRT_ALWAYS: + // # GRANT_ALWAYS is used to apply `true` predicate onto a value regardless + // # its original predicate value. This is usually used for the constant declared + // # in the entry block of a function, and then being used as a bound variable + // # in some streaming loop. Note that if we fuse the constant and the grant_always, + // # we may not need this operation, as the constant is usually preloaded into the + // # ConstQueue with `true` predicate. + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + // # Always updates predicate as true. + // s.send_out[0].msg.predicate @= s.reached_vector_factor + // + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // elif s.recv_opt.msg.operation == OPT_GRT_ONCE: + // # GRANT_ONCE is used to apply `true` predicate onto a value only once. This + // # is usually used for the constant declared in the entry block of a function. + // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + // # Only updates predicate as true for the first time. + // s.send_out[0].msg.predicate @= s.reached_vector_factor & ~s.already_grt_once + // + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // + // else: + // for j in range( num_outports ): + // s.send_out[j].val @= b1( 0 ) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_PRED ) ) begin + send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; + if ( recv_in__msg[in1_idx].payload != 64'd0 ) begin + send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + end + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ALWAYS ) ) begin + send_out__msg[1'd0] = recv_in__msg[in0_idx]; + send_out__msg[1'd0].predicate = reached_vector_factor; + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ONCE ) ) begin + send_out__msg[1'd0] = recv_in__msg[in0_idx]; + send_out__msg[1'd0].predicate = reached_vector_factor & ( ~already_grt_once ); + recv_all_val = recv_in__val[in0_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py:123 + // @update_ff + // def record_grt_once(): + // if s.reset | s.clear: + // s.already_grt_once <<= 0 + // else: + // if ~s.already_grt_once & s.send_out[0].val & s.send_out[0].rdy & (s.recv_opt.msg.operation == OPT_GRT_ONCE): + // s.already_grt_once <<= 1 + // else: + // s.already_grt_once <<= s.already_grt_once + + always_ff @(posedge clk) begin : record_grt_once + if ( reset | clear ) begin + already_grt_once <= 1'd0; + end + else if ( ( ( ( ~already_grt_once ) & send_out__val[1'd0] ) & send_out__rdy[1'd0] ) & ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ONCE ) ) ) begin + already_grt_once <= 1'd1; + end + else + already_grt_once <= already_grt_once; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + +endmodule + + +// PyMTL Component MemUnitRTL Definition +// Full name: MemUnitRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py + +module MemUnitRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_LD = 7'd12; + localparam logic [6:0] __const__OPT_ADD_CONST_LD = 7'd81; + localparam logic [6:0] __const__OPT_LD_CONST = 7'd28; + localparam logic [6:0] __const__OPT_STR = 7'd13; + localparam logic [6:0] __const__OPT_STR_CONST = 7'd58; + logic [0:0] already_sent_raddr; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [3:0] recv_in_val_vector; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:81 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register + // s.in0 @= FuInType(0) + // s.in1 @= FuInType(0) + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != 0: + // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) + // if s.recv_opt.msg.fu_in[1] != 0: + // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) + // + // s.to_mem_waddr.val @= 0 + // s.to_mem_waddr.msg @= AddrType() + // s.to_mem_wdata.val @= 0 + // s.to_mem_wdata.msg @= DataType() + // s.to_mem_raddr.val @= 0 + // s.to_mem_raddr.msg @= AddrType() + // s.from_mem_rdata.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_LD: + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_raddr.rdy + // s.to_mem_raddr.msg @= AddrType(s.recv_in[s.in0_idx].msg.payload[0:AddrType.nbits]) + // # Do not access memory by setting raddr.val=0 if the raddr has predicate=0. + // # Note that this only happends "once" when all the required inputs are arrived. + // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): + // s.to_mem_raddr.val @= 0 + // else: + // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr + // s.from_mem_rdata.rdy @= s.send_out[0].rdy + // # Although we do not access memory when raddr has predicate=0, + // # we still need to simulate that memory returns a fake data with predicate=0, + // # so that the consumer will not block due to the lack of data. + // # Then all initiated iterations can be normally drained. + // # Note that this only happends "after" all the required inputs are arrived. + // # Otherwise, the recv_opt's opcode would be consumed at the wrong timing. + // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): + // s.send_out[0].val @= s.recv_all_val + // s.send_out[0].msg.predicate @= 0 + // s.recv_opt.rdy @= s.send_out[0].rdy + // else: + // s.send_out[0].val @= s.from_mem_rdata.val + // s.send_out[0].msg @= s.from_mem_rdata.msg + // # Predicate of 0 is already handled and returned with fake data. So just + // # use the from_mem_rdata's predicate here. + // s.send_out[0].msg.predicate @= s.from_mem_rdata.msg.predicate & \ + // s.reached_vector_factor + // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val + // + // # ADD_CONST_LD indicates the address is added on a const, then perform load. + // elif s.recv_opt.msg.operation == OPT_ADD_CONST_LD: + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_raddr.rdy + // # It is okay to always set recv_const.rdy=1 here, because the const queue + // # would only proceed once the operation is done executing. + // s.recv_const.rdy @= 1 + // s.to_mem_raddr.msg @= AddrType(s.recv_in[s.in0_idx].msg.payload[0:AddrType.nbits] + + // s.recv_const.msg.payload[0:AddrType.nbits]) + // # Do not access memory by setting raddr.val=0 if the raddr has predicate=0. + // # Note that this only happends "once" when all the required inputs are arrived. + // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): + // s.to_mem_raddr.val @= 0 + // else: + // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr + // s.from_mem_rdata.rdy @= s.send_out[0].rdy + // # Although we do not access memory when raddr has predicate=0, + // # we still need to simulate that memory returns a fake data with predicate=0, + // # so that the consumer will not block due to the lack of data. + // # Then all initiated iterations can be normally drained. + // # Note that this only happends "after" all the required inputs are arrived. + // # Otherwise, the recv_opt's opcode would be consumed at the wrong timing. + // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): + // s.send_out[0].val @= s.recv_all_val + // s.send_out[0].msg.predicate @= 0 + // s.recv_opt.rdy @= s.send_out[0].rdy + // else: + // s.send_out[0].val @= s.from_mem_rdata.val + // s.send_out[0].msg @= s.from_mem_rdata.msg + // # Predicate of 0 is already handled and returned with fake data. So just + // # use the from_mem_rdata's predicate here. + // s.send_out[0].msg.predicate @= s.from_mem_rdata.msg.predicate & \ + // s.reached_vector_factor + // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val + // + // # LD_CONST indicates the address is a const. + // elif s.recv_opt.msg.operation == OPT_LD_CONST: + // s.recv_all_val @= s.recv_const.val + // # It is okay to always set recv_const.rdy=1 here, because the const queue + // # would only proceed once the operation is done executing. + // s.recv_const.rdy @= 1 + // s.to_mem_raddr.msg @= AddrType(s.recv_const.msg.payload[0:AddrType.nbits]) + // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr + // s.from_mem_rdata.rdy @= s.send_out[0].rdy + // s.send_out[0].val @= s.from_mem_rdata.val + // s.send_out[0].msg @= s.from_mem_rdata.msg + // s.send_out[0].msg.predicate @= s.recv_const.msg.predicate & \ + // s.from_mem_rdata.msg.predicate & \ + // s.reached_vector_factor + // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val + // + // elif s.recv_opt.msg.operation == OPT_STR: + // s.recv_all_val @= s.recv_in[s.in0_idx].val & \ + // s.recv_in[s.in1_idx].val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // s.to_mem_waddr.msg @= AddrType(s.recv_in[0].msg.payload[0:AddrType.nbits]) + // s.to_mem_waddr.val @= s.recv_all_val + // s.to_mem_wdata.msg @= s.recv_in[s.in1_idx].msg + // s.to_mem_wdata.msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.reached_vector_factor + // s.to_mem_wdata.val @= s.recv_all_val + // + // # `send_out` is meaningless for store operation. + // s.send_out[0].val @= b1(0) + // + // s.recv_opt.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // + // # STR_CONST indicates the address is a const. + // elif s.recv_opt.msg.operation == OPT_STR_CONST: + // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val + // s.recv_const.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // # Only needs one input register to indicate the storing data. + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // s.to_mem_waddr.msg @= AddrType(s.recv_const.msg.payload[0:AddrType.nbits]) + // s.to_mem_waddr.val @= s.recv_all_val & \ + // s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate + // s.to_mem_wdata.msg @= s.recv_in[s.in0_idx].msg + // s.to_mem_wdata.msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate & \ + // s.reached_vector_factor + // s.to_mem_wdata.val @= s.recv_all_val & \ + // s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_const.msg.predicate + // + // # `send_out` is meaningless for store operation. + // s.send_out[0].val @= b1(0) + // + // s.recv_opt.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy + // + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + end + to_mem_waddr__val = 1'd0; + to_mem_waddr__msg = 7'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + to_mem_raddr__val = 1'd0; + to_mem_raddr__msg = 7'd0; + from_mem_rdata__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_LD ) ) begin + recv_all_val = recv_in__val[in0_idx]; + recv_in__rdy[in0_idx] = recv_all_val & to_mem_raddr__rdy; + to_mem_raddr__msg = 7'( recv_in__msg[in0_idx].payload[6'd6:6'd0] ); + if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin + to_mem_raddr__val = 1'd0; + end + else + to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); + from_mem_rdata__rdy = send_out__rdy[1'd0]; + if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin + send_out__val[1'd0] = recv_all_val; + send_out__msg[1'd0].predicate = 1'd0; + recv_opt__rdy = send_out__rdy[1'd0]; + end + else begin + send_out__val[1'd0] = from_mem_rdata__val; + send_out__msg[1'd0] = from_mem_rdata__msg; + send_out__msg[1'd0].predicate = from_mem_rdata__msg.predicate & reached_vector_factor; + recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; + end + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST_LD ) ) begin + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + recv_in__rdy[in0_idx] = recv_all_val & to_mem_raddr__rdy; + recv_const__rdy = 1'd1; + to_mem_raddr__msg = 7'( recv_in__msg[in0_idx].payload[6'd6:6'd0] + recv_const__msg.payload[6'd6:6'd0] ); + if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin + to_mem_raddr__val = 1'd0; + end + else + to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); + from_mem_rdata__rdy = send_out__rdy[1'd0]; + if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin + send_out__val[1'd0] = recv_all_val; + send_out__msg[1'd0].predicate = 1'd0; + recv_opt__rdy = send_out__rdy[1'd0]; + end + else begin + send_out__val[1'd0] = from_mem_rdata__val; + send_out__msg[1'd0] = from_mem_rdata__msg; + send_out__msg[1'd0].predicate = from_mem_rdata__msg.predicate & reached_vector_factor; + recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; + end + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_LD_CONST ) ) begin + recv_all_val = recv_const__val; + recv_const__rdy = 1'd1; + to_mem_raddr__msg = 7'( recv_const__msg.payload[6'd6:6'd0] ); + to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); + from_mem_rdata__rdy = send_out__rdy[1'd0]; + send_out__val[1'd0] = from_mem_rdata__val; + send_out__msg[1'd0] = from_mem_rdata__msg; + send_out__msg[1'd0].predicate = ( recv_const__msg.predicate & from_mem_rdata__msg.predicate ) & reached_vector_factor; + recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_STR ) ) begin + recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; + recv_in__rdy[in0_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + recv_in__rdy[in1_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + to_mem_waddr__msg = 7'( recv_in__msg[2'd0].payload[6'd6:6'd0] ); + to_mem_waddr__val = recv_all_val; + to_mem_wdata__msg = recv_in__msg[in1_idx]; + to_mem_wdata__msg.predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; + to_mem_wdata__val = recv_all_val; + send_out__val[1'd0] = 1'd0; + recv_opt__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + end + else if ( recv_opt__msg.operation == 7'( __const__OPT_STR_CONST ) ) begin + recv_all_val = recv_in__val[in0_idx] & recv_const__val; + recv_const__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + recv_in__rdy[in0_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + to_mem_waddr__msg = 7'( recv_const__msg.payload[6'd6:6'd0] ); + to_mem_waddr__val = ( recv_all_val & recv_in__msg[in0_idx].predicate ) & recv_const__msg.predicate; + to_mem_wdata__msg = recv_in__msg[in0_idx]; + to_mem_wdata__msg.predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; + to_mem_wdata__val = ( recv_all_val & recv_in__msg[in0_idx].predicate ) & recv_const__msg.predicate; + send_out__val[1'd0] = 1'd0; + recv_opt__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:245 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:269 + // @update_ff + // def update_already_sent_raddr(): + // if s.reset: + // s.already_sent_raddr <<= 0 + // else: + // if ~s.recv_opt.val: + // s.already_sent_raddr <<= 0 + // elif s.from_mem_rdata.val & s.from_mem_rdata.rdy: + // # Clears the flag when the data has returned (s.from_mem_rdata.val) + // # and successfully delivered to the destination (s.from_mem_rdata.rdy). + // s.already_sent_raddr <<= 0 + // elif s.to_mem_raddr.val & \ + // s.to_mem_raddr.rdy & \ + // ~s.already_sent_raddr: + // s.already_sent_raddr <<= 1 + // else: + // s.already_sent_raddr <<= s.already_sent_raddr + + always_ff @(posedge clk) begin : update_already_sent_raddr + if ( reset ) begin + already_sent_raddr <= 1'd0; + end + else if ( ~recv_opt__val ) begin + already_sent_raddr <= 1'd0; + end + else if ( from_mem_rdata__val & from_mem_rdata__rdy ) begin + already_sent_raddr <= 1'd0; + end + else if ( ( to_mem_raddr__val & to_mem_raddr__rdy ) & ( ~already_sent_raddr ) ) begin + already_sent_raddr <= 1'd1; + end + else + already_sent_raddr <= already_sent_raddr; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:253 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + assign vector_factor_power = 3'd0; + +endmodule + + +// PyMTL Component SelRTL Definition +// Full name: SelRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py + +module SelRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_SEL = 7'd27; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [2:0] in1; + logic [1:0] in1_idx; + logic [2:0] in2; + logic [1:0] in2_idx; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:88 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register, Selector needs at least 3 inputs + // s.in0 @= FuInType(0) + // s.in1 @= FuInType(0) + // s.in2 @= FuInType(0) + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= s.send_out[0].rdy + // + // for i in range(num_outports): + // s.send_out[i].val @= 0 + // s.send_out[i].msg @= DataType() + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // if s.recv_opt.msg.fu_in[1] != FuInType(0): + // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) + // if s.recv_opt.msg.fu_in[2] != FuInType(0): + // s.in2 @= s.recv_opt.msg.fu_in[2] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_SEL: + // if s.recv_in[s.in0_idx].msg.payload == s.true.payload: + // s.send_out[0].msg @= s.recv_in[s.in1_idx].msg + // else: + // s.send_out[0].msg @= s.recv_in[s.in2_idx].msg + // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ + // s.recv_in[s.in1_idx].msg.predicate & \ + // s.recv_in[s.in2_idx].msg.predicate & \ + // s.reached_vector_factor + // s.recv_all_val @= s.recv_in[s.in0_idx].val & \ + // s.recv_in[s.in1_idx].val & \ + // s.recv_in[s.in2_idx].val + // s.send_out[0].val @= s.recv_all_val + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_in[s.in2_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy + // else: + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.recv_opt.rdy @= 0 + // s.recv_in[s.in0_idx].rdy @= 0 + // s.recv_in[s.in1_idx].rdy @= 0 + // s.recv_in[s.in2_idx].rdy @= 0 + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + in1 = 3'd0; + in2 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + recv_const__rdy = 1'd0; + recv_opt__rdy = send_out__rdy[1'd0]; + for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin + send_out__val[1'(i)] = 1'd0; + send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin + in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; + end + if ( recv_opt__msg.fu_in[2'd2] != 3'd0 ) begin + in2 = recv_opt__msg.fu_in[2'd2] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_SEL ) ) begin + if ( recv_in__msg[in0_idx].payload == 64'd1 ) begin + send_out__msg[1'd0] = recv_in__msg[in1_idx]; + end + else + send_out__msg[1'd0] = recv_in__msg[in2_idx]; + send_out__msg[1'd0].predicate = ( ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & recv_in__msg[in2_idx].predicate ) & reached_vector_factor; + recv_all_val = ( recv_in__val[in0_idx] & recv_in__val[in1_idx] ) & recv_in__val[in2_idx]; + send_out__val[1'd0] = recv_all_val; + recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_in__rdy[in2_idx] = recv_all_val & send_out__rdy[1'd0]; + recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; + end + else begin + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) + send_out__val[1'(j)] = 1'd0; + recv_opt__rdy = 1'd0; + recv_in__rdy[in0_idx] = 1'd0; + recv_in__rdy[in1_idx] = 1'd0; + recv_in__rdy[in2_idx] = 1'd0; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:78 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= AddrType(0) + // s.to_mem_raddr.msg @= AddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:144 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:152 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign in0_idx = in0[1:0]; + assign in1_idx = in1[1:0]; + assign in2_idx = in2[1:0]; + assign vector_factor_power = 3'd0; + +endmodule + + +// PyMTL Component RetRTL Definition +// Full name: RetRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 +// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py + +module RetRTL__45df3c5556ff02e3 +( + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_RET = 7'd35; + localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; + logic [0:0] already_done; + logic [2:0] in0; + logic [1:0] in0_idx; + logic [0:0] latency; + logic [0:0] reached_vector_factor; + logic [0:0] recv_all_val; + logic [7:0] vector_factor_counter; + logic [2:0] vector_factor_power; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py:48 + // @update + // def comb_logic(): + // + // s.recv_all_val @= 0 + // # For pick input register. + // s.in0 @= 0 + // for i in range(num_inports): + // s.recv_in[i].rdy @= b1(0) + // + // for j in range(num_outports): + // s.send_out[j].val @= 0 + // s.send_out[j].msg @= DataType() + // + // s.send_to_ctrl_mem.val @= 0 + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) + // s.recv_from_ctrl_mem.rdy @= 0 + // + // s.recv_const.rdy @= 0 + // s.recv_opt.rdy @= 0 + // + // if s.recv_opt.val: + // if s.recv_opt.msg.fu_in[0] != FuInType(0): + // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) + // + // if s.recv_opt.val: + // if s.recv_opt.msg.operation == OPT_RET: + // s.recv_all_val @= s.recv_in[s.in0_idx].val + // # Value to be returned is usually granted with a predicate: + // # https://github.com/coredac/dataflow/blob/b9ffc097d67429017323e3d50d3984655f756b91/test/neura/ctrl/branch_for.mlir#L150. + // if s.already_done: + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val + // s.recv_opt.rdy @= s.recv_all_val + // elif s.recv_in[s.in0_idx].msg.predicate: + // # Only when the predicate is true, the value will be sent back to CPU. + // s.send_to_ctrl_mem.val @= s.recv_all_val & s.reached_vector_factor + // # s.send_to_ctrl_mem.msg @= s.recv_in[s.in0_idx].msg + // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(CMD_COMPLETE, s.recv_in[s.in0_idx].msg, 0, s.recv_opt.msg, 0) + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.reached_vector_factor & s.send_to_ctrl_mem.rdy + // s.recv_opt.rdy @= s.recv_all_val & s.reached_vector_factor & s.send_to_ctrl_mem.rdy + // else: + // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.reached_vector_factor + // s.recv_opt.rdy @= s.recv_all_val & s.reached_vector_factor + + always_comb begin : comb_logic + recv_all_val = 1'd0; + in0 = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) + recv_in__rdy[2'(i)] = 1'd0; + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin + send_out__val[1'(j)] = 1'd0; + send_out__msg[1'(j)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + send_to_ctrl_mem__val = 1'd0; + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + recv_from_ctrl_mem__rdy = 1'd0; + recv_const__rdy = 1'd0; + recv_opt__rdy = 1'd0; + if ( recv_opt__val ) begin + if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin + in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; + end + end + if ( recv_opt__val ) begin + if ( recv_opt__msg.operation == 7'( __const__OPT_RET ) ) begin + recv_all_val = recv_in__val[in0_idx]; + if ( already_done ) begin + recv_in__rdy[in0_idx] = recv_all_val; + recv_opt__rdy = recv_all_val; + end + else if ( recv_in__msg[in0_idx].predicate ) begin + send_to_ctrl_mem__val = recv_all_val & reached_vector_factor; + send_to_ctrl_mem__msg = { 5'( __const__CMD_COMPLETE ), recv_in__msg[in0_idx], 7'd0, recv_opt__msg, 4'd0 }; + recv_in__rdy[in0_idx] = ( recv_all_val & reached_vector_factor ) & send_to_ctrl_mem__rdy; + recv_opt__rdy = ( recv_all_val & reached_vector_factor ) & send_to_ctrl_mem__rdy; + end + else begin + recv_in__rdy[in0_idx] = recv_all_val & reached_vector_factor; + recv_opt__rdy = recv_all_val & reached_vector_factor; + end + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 + // @update + // def update_mem(): + // s.to_mem_waddr.val @= b1(0) + // s.to_mem_wdata.val @= b1(0) + // s.to_mem_wdata.msg @= s.const_zero + // s.to_mem_waddr.msg @= DataAddrType(0) + // s.to_mem_raddr.msg @= DataAddrType(0) + // s.to_mem_raddr.val @= b1(0) + // s.from_mem_rdata.rdy @= b1(0) + + always_comb begin : update_mem + to_mem_waddr__val = 1'd0; + to_mem_wdata__val = 1'd0; + to_mem_wdata__msg = const_zero; + to_mem_waddr__msg = 7'd0; + to_mem_raddr__msg = 7'd0; + to_mem_raddr__val = 1'd0; + from_mem_rdata__rdy = 1'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 + // @update + // def update_reached_vector_factor(): + // s.reached_vector_factor @= 0 + // if s.recv_opt.val & (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.reached_vector_factor @= 1 + + always_comb begin : update_reached_vector_factor + reached_vector_factor = 1'd0; + if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + reached_vector_factor = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 + // @update_ff + // def proceed_latency(): + // if s.recv_opt.msg.operation == OPT_START: + // s.latency <<= LatencyType(0) + // elif s.latency == latency - 1: + // s.latency <<= LatencyType(0) + // else: + // s.latency <<= s.latency + LatencyType(1) + + always_ff @(posedge clk) begin : proceed_latency + if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin + latency <= 1'd0; + end + else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin + latency <= 1'd0; + end + else + latency <= latency + 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py:91 + // @update_ff + // def update_already_done(): + // if s.reset | s.clear: + // s.already_done <<= 0 + // else: + // if s.recv_opt.val & \ + // (s.recv_opt.msg.operation == OPT_RET) & \ + // ~s.already_done & \ + // s.recv_all_val & \ + // s.send_to_ctrl_mem.val & \ + // s.send_to_ctrl_mem.rdy: + // s.already_done <<= 1 + // else: + // s.already_done <<= s.already_done + + always_ff @(posedge clk) begin : update_already_done + if ( reset | clear ) begin + already_done <= 1'd0; + end + else if ( ( ( ( ( recv_opt__val & ( recv_opt__msg.operation == 7'( __const__OPT_RET ) ) ) & ( ~already_done ) ) & recv_all_val ) & send_to_ctrl_mem__val ) & send_to_ctrl_mem__rdy ) begin + already_done <= 1'd1; + end + else + already_done <= already_done; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 + // @update_ff + // def update_vector_factor_counter(): + // if s.reset: + // s.vector_factor_counter <<= 0 + // else: + // if s.recv_opt.val: + // if s.recv_opt.msg.is_last_ctrl & \ + // (s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ + // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): + // s.vector_factor_counter <<= s.vector_factor_counter + \ + // (VectorFactorType(1) << zext(s.vector_factor_power, \ + // VectorFactorType)) + // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: + // s.vector_factor_counter <<= 0 + + always_ff @(posedge clk) begin : update_vector_factor_counter + if ( reset ) begin + vector_factor_counter <= 8'd0; + end + else if ( recv_opt__val ) begin + if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin + vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); + end + else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin + vector_factor_counter <= 8'd0; + end + end + end + + assign vector_factor_power = 3'd0; + assign in0_idx = in0[1:0]; + +endmodule + + +// PyMTL Component FlexibleFuRTL Definition +// Full name: FlexibleFuRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__num_tiles_16__FuList_[, , , , , , , , , , , , , , ]__exec_lantency_{} +// At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py + +module FlexibleFuRTL__07217382918d0fc2 +( + input logic [0:0] clear [0:14], + input logic [0:0] clk , + input logic [2:0] prologue_count_inport , + input logic [0:0] reset , + input logic [4:0] tile_id , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg [0:14] , + output logic [0:0] from_mem_rdata__rdy [0:14] , + input logic [0:0] from_mem_rdata__val [0:14] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , + output logic [0:0] recv_const__rdy , + input logic [0:0] recv_const__val , + input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , + output logic [0:0] recv_from_ctrl_mem__rdy , + input logic [0:0] recv_from_ctrl_mem__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , + output logic [0:0] recv_in__rdy [0:3] , + input logic [0:0] recv_in__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , + input logic [0:0] send_out__rdy [0:1] , + output logic [0:0] send_out__val [0:1] , + output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , + input logic [0:0] send_to_ctrl_mem__rdy , + output logic [0:0] send_to_ctrl_mem__val , + output logic [6:0] to_mem_raddr__msg [0:14] , + input logic [0:0] to_mem_raddr__rdy [0:14] , + output logic [0:0] to_mem_raddr__val [0:14] , + output logic [6:0] to_mem_waddr__msg [0:14] , + input logic [0:0] to_mem_waddr__rdy [0:14] , + output logic [0:0] to_mem_waddr__val [0:14] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg [0:14] , + input logic [0:0] to_mem_wdata__rdy [0:14] , + output logic [0:0] to_mem_wdata__val [0:14] +); + localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; + localparam logic [6:0] __const__OPT_NAH = 7'd1; + localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; + logic [14:0] fu_recv_const_rdy_vector; + logic [14:0] fu_recv_in_rdy_vector [0:3]; + logic [14:0] fu_recv_opt_rdy_vector; + logic [14:0] recv_from_controller_rdy_vector; + //------------------------------------------------------------- + // Component fu[0:14] + //------------------------------------------------------------- + + logic [0:0] fu__clear [0:14]; + logic [0:0] fu__clk [0:14]; + logic [0:0] fu__reset [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__from_mem_rdata__msg [0:14]; + logic [0:0] fu__from_mem_rdata__rdy [0:14]; + logic [0:0] fu__from_mem_rdata__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__recv_const__msg [0:14]; + logic [0:0] fu__recv_const__rdy [0:14]; + logic [0:0] fu__recv_const__val [0:14]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a fu__recv_from_ctrl_mem__msg [0:14]; + logic [0:0] fu__recv_from_ctrl_mem__rdy [0:14]; + logic [0:0] fu__recv_from_ctrl_mem__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__recv_in__msg [0:14][0:3]; + logic [0:0] fu__recv_in__rdy [0:14][0:3]; + logic [0:0] fu__recv_in__val [0:14][0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 fu__recv_opt__msg [0:14]; + logic [0:0] fu__recv_opt__rdy [0:14]; + logic [0:0] fu__recv_opt__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__send_out__msg [0:14][0:1]; + logic [0:0] fu__send_out__rdy [0:14][0:1]; + logic [0:0] fu__send_out__val [0:14][0:1]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a fu__send_to_ctrl_mem__msg [0:14]; + logic [0:0] fu__send_to_ctrl_mem__rdy [0:14]; + logic [0:0] fu__send_to_ctrl_mem__val [0:14]; + logic [6:0] fu__to_mem_raddr__msg [0:14]; + logic [0:0] fu__to_mem_raddr__rdy [0:14]; + logic [0:0] fu__to_mem_raddr__val [0:14]; + logic [6:0] fu__to_mem_waddr__msg [0:14]; + logic [0:0] fu__to_mem_waddr__rdy [0:14]; + logic [0:0] fu__to_mem_waddr__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__to_mem_wdata__msg [0:14]; + logic [0:0] fu__to_mem_wdata__rdy [0:14]; + logic [0:0] fu__to_mem_wdata__val [0:14]; + + AdderRTL__45df3c5556ff02e3 fu__0 + ( + .clear( fu__clear[0] ), + .clk( fu__clk[0] ), + .reset( fu__reset[0] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[0] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[0] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[0] ), + .recv_const__msg( fu__recv_const__msg[0] ), + .recv_const__rdy( fu__recv_const__rdy[0] ), + .recv_const__val( fu__recv_const__val[0] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[0] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[0] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[0] ), + .recv_in__msg( fu__recv_in__msg[0] ), + .recv_in__rdy( fu__recv_in__rdy[0] ), + .recv_in__val( fu__recv_in__val[0] ), + .recv_opt__msg( fu__recv_opt__msg[0] ), + .recv_opt__rdy( fu__recv_opt__rdy[0] ), + .recv_opt__val( fu__recv_opt__val[0] ), + .send_out__msg( fu__send_out__msg[0] ), + .send_out__rdy( fu__send_out__rdy[0] ), + .send_out__val( fu__send_out__val[0] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[0] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[0] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[0] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[0] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[0] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[0] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[0] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[0] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[0] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[0] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[0] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[0] ) + ); + + MulRTL__45df3c5556ff02e3 fu__1 + ( + .clear( fu__clear[1] ), + .clk( fu__clk[1] ), + .reset( fu__reset[1] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[1] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[1] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[1] ), + .recv_const__msg( fu__recv_const__msg[1] ), + .recv_const__rdy( fu__recv_const__rdy[1] ), + .recv_const__val( fu__recv_const__val[1] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[1] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[1] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[1] ), + .recv_in__msg( fu__recv_in__msg[1] ), + .recv_in__rdy( fu__recv_in__rdy[1] ), + .recv_in__val( fu__recv_in__val[1] ), + .recv_opt__msg( fu__recv_opt__msg[1] ), + .recv_opt__rdy( fu__recv_opt__rdy[1] ), + .recv_opt__val( fu__recv_opt__val[1] ), + .send_out__msg( fu__send_out__msg[1] ), + .send_out__rdy( fu__send_out__rdy[1] ), + .send_out__val( fu__send_out__val[1] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[1] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[1] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[1] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[1] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[1] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[1] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[1] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[1] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[1] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[1] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[1] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[1] ) + ); + + LogicRTL__45df3c5556ff02e3 fu__2 + ( + .clear( fu__clear[2] ), + .clk( fu__clk[2] ), + .reset( fu__reset[2] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[2] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[2] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[2] ), + .recv_const__msg( fu__recv_const__msg[2] ), + .recv_const__rdy( fu__recv_const__rdy[2] ), + .recv_const__val( fu__recv_const__val[2] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[2] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[2] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[2] ), + .recv_in__msg( fu__recv_in__msg[2] ), + .recv_in__rdy( fu__recv_in__rdy[2] ), + .recv_in__val( fu__recv_in__val[2] ), + .recv_opt__msg( fu__recv_opt__msg[2] ), + .recv_opt__rdy( fu__recv_opt__rdy[2] ), + .recv_opt__val( fu__recv_opt__val[2] ), + .send_out__msg( fu__send_out__msg[2] ), + .send_out__rdy( fu__send_out__rdy[2] ), + .send_out__val( fu__send_out__val[2] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[2] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[2] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[2] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[2] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[2] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[2] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[2] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[2] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[2] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[2] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[2] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[2] ) + ); + + ShifterRTL__45df3c5556ff02e3 fu__3 + ( + .clear( fu__clear[3] ), + .clk( fu__clk[3] ), + .reset( fu__reset[3] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[3] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[3] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[3] ), + .recv_const__msg( fu__recv_const__msg[3] ), + .recv_const__rdy( fu__recv_const__rdy[3] ), + .recv_const__val( fu__recv_const__val[3] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[3] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[3] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[3] ), + .recv_in__msg( fu__recv_in__msg[3] ), + .recv_in__rdy( fu__recv_in__rdy[3] ), + .recv_in__val( fu__recv_in__val[3] ), + .recv_opt__msg( fu__recv_opt__msg[3] ), + .recv_opt__rdy( fu__recv_opt__rdy[3] ), + .recv_opt__val( fu__recv_opt__val[3] ), + .send_out__msg( fu__send_out__msg[3] ), + .send_out__rdy( fu__send_out__rdy[3] ), + .send_out__val( fu__send_out__val[3] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[3] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[3] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[3] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[3] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[3] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[3] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[3] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[3] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[3] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[3] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[3] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[3] ) + ); + + PhiRTL__45df3c5556ff02e3 fu__4 + ( + .clear( fu__clear[4] ), + .clk( fu__clk[4] ), + .reset( fu__reset[4] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[4] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[4] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[4] ), + .recv_const__msg( fu__recv_const__msg[4] ), + .recv_const__rdy( fu__recv_const__rdy[4] ), + .recv_const__val( fu__recv_const__val[4] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[4] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[4] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[4] ), + .recv_in__msg( fu__recv_in__msg[4] ), + .recv_in__rdy( fu__recv_in__rdy[4] ), + .recv_in__val( fu__recv_in__val[4] ), + .recv_opt__msg( fu__recv_opt__msg[4] ), + .recv_opt__rdy( fu__recv_opt__rdy[4] ), + .recv_opt__val( fu__recv_opt__val[4] ), + .send_out__msg( fu__send_out__msg[4] ), + .send_out__rdy( fu__send_out__rdy[4] ), + .send_out__val( fu__send_out__val[4] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[4] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[4] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[4] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[4] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[4] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[4] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[4] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[4] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[4] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[4] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[4] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[4] ) + ); + + CompRTL__45df3c5556ff02e3 fu__5 + ( + .clear( fu__clear[5] ), + .clk( fu__clk[5] ), + .reset( fu__reset[5] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[5] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[5] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[5] ), + .recv_const__msg( fu__recv_const__msg[5] ), + .recv_const__rdy( fu__recv_const__rdy[5] ), + .recv_const__val( fu__recv_const__val[5] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[5] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[5] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[5] ), + .recv_in__msg( fu__recv_in__msg[5] ), + .recv_in__rdy( fu__recv_in__rdy[5] ), + .recv_in__val( fu__recv_in__val[5] ), + .recv_opt__msg( fu__recv_opt__msg[5] ), + .recv_opt__rdy( fu__recv_opt__rdy[5] ), + .recv_opt__val( fu__recv_opt__val[5] ), + .send_out__msg( fu__send_out__msg[5] ), + .send_out__rdy( fu__send_out__rdy[5] ), + .send_out__val( fu__send_out__val[5] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[5] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[5] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[5] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[5] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[5] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[5] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[5] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[5] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[5] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[5] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[5] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[5] ) + ); + + GrantRTL__45df3c5556ff02e3 fu__6 + ( + .clear( fu__clear[6] ), + .clk( fu__clk[6] ), + .reset( fu__reset[6] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[6] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[6] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[6] ), + .recv_const__msg( fu__recv_const__msg[6] ), + .recv_const__rdy( fu__recv_const__rdy[6] ), + .recv_const__val( fu__recv_const__val[6] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[6] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[6] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[6] ), + .recv_in__msg( fu__recv_in__msg[6] ), + .recv_in__rdy( fu__recv_in__rdy[6] ), + .recv_in__val( fu__recv_in__val[6] ), + .recv_opt__msg( fu__recv_opt__msg[6] ), + .recv_opt__rdy( fu__recv_opt__rdy[6] ), + .recv_opt__val( fu__recv_opt__val[6] ), + .send_out__msg( fu__send_out__msg[6] ), + .send_out__rdy( fu__send_out__rdy[6] ), + .send_out__val( fu__send_out__val[6] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[6] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[6] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[6] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[6] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[6] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[6] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[6] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[6] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[6] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[6] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[6] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[6] ) + ); + + MemUnitRTL__45df3c5556ff02e3 fu__7 + ( + .clear( fu__clear[7] ), + .clk( fu__clk[7] ), + .reset( fu__reset[7] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[7] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[7] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[7] ), + .recv_const__msg( fu__recv_const__msg[7] ), + .recv_const__rdy( fu__recv_const__rdy[7] ), + .recv_const__val( fu__recv_const__val[7] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[7] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[7] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[7] ), + .recv_in__msg( fu__recv_in__msg[7] ), + .recv_in__rdy( fu__recv_in__rdy[7] ), + .recv_in__val( fu__recv_in__val[7] ), + .recv_opt__msg( fu__recv_opt__msg[7] ), + .recv_opt__rdy( fu__recv_opt__rdy[7] ), + .recv_opt__val( fu__recv_opt__val[7] ), + .send_out__msg( fu__send_out__msg[7] ), + .send_out__rdy( fu__send_out__rdy[7] ), + .send_out__val( fu__send_out__val[7] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[7] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[7] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[7] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[7] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[7] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[7] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[7] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[7] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[7] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[7] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[7] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[7] ) + ); + + SelRTL__45df3c5556ff02e3 fu__8 + ( + .clear( fu__clear[8] ), + .clk( fu__clk[8] ), + .reset( fu__reset[8] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[8] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[8] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[8] ), + .recv_const__msg( fu__recv_const__msg[8] ), + .recv_const__rdy( fu__recv_const__rdy[8] ), + .recv_const__val( fu__recv_const__val[8] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[8] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[8] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[8] ), + .recv_in__msg( fu__recv_in__msg[8] ), + .recv_in__rdy( fu__recv_in__rdy[8] ), + .recv_in__val( fu__recv_in__val[8] ), + .recv_opt__msg( fu__recv_opt__msg[8] ), + .recv_opt__rdy( fu__recv_opt__rdy[8] ), + .recv_opt__val( fu__recv_opt__val[8] ), + .send_out__msg( fu__send_out__msg[8] ), + .send_out__rdy( fu__send_out__rdy[8] ), + .send_out__val( fu__send_out__val[8] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[8] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[8] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[8] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[8] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[8] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[8] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[8] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[8] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[8] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[8] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[8] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[8] ) + ); + + RetRTL__45df3c5556ff02e3 fu__9 + ( + .clear( fu__clear[9] ), + .clk( fu__clk[9] ), + .reset( fu__reset[9] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[9] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[9] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[9] ), + .recv_const__msg( fu__recv_const__msg[9] ), + .recv_const__rdy( fu__recv_const__rdy[9] ), + .recv_const__val( fu__recv_const__val[9] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[9] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[9] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[9] ), + .recv_in__msg( fu__recv_in__msg[9] ), + .recv_in__rdy( fu__recv_in__rdy[9] ), + .recv_in__val( fu__recv_in__val[9] ), + .recv_opt__msg( fu__recv_opt__msg[9] ), + .recv_opt__rdy( fu__recv_opt__rdy[9] ), + .recv_opt__val( fu__recv_opt__val[9] ), + .send_out__msg( fu__send_out__msg[9] ), + .send_out__rdy( fu__send_out__rdy[9] ), + .send_out__val( fu__send_out__val[9] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[9] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[9] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[9] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[9] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[9] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[9] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[9] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[9] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[9] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[9] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[9] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[9] ) + ); + + SeqMulAdderRTL__b741248a3a1dca5f fu__10 + ( + .clear( fu__clear[10] ), + .clk( fu__clk[10] ), + .reset( fu__reset[10] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[10] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[10] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[10] ), + .recv_const__msg( fu__recv_const__msg[10] ), + .recv_const__rdy( fu__recv_const__rdy[10] ), + .recv_const__val( fu__recv_const__val[10] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[10] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[10] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[10] ), + .recv_in__msg( fu__recv_in__msg[10] ), + .recv_in__rdy( fu__recv_in__rdy[10] ), + .recv_in__val( fu__recv_in__val[10] ), + .recv_opt__msg( fu__recv_opt__msg[10] ), + .recv_opt__rdy( fu__recv_opt__rdy[10] ), + .recv_opt__val( fu__recv_opt__val[10] ), + .send_out__msg( fu__send_out__msg[10] ), + .send_out__rdy( fu__send_out__rdy[10] ), + .send_out__val( fu__send_out__val[10] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[10] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[10] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[10] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[10] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[10] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[10] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[10] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[10] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[10] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[10] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[10] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[10] ) + ); + + VectorMulComboRTL__e2d25a29972e2033 fu__11 + ( + .clear( fu__clear[11] ), + .clk( fu__clk[11] ), + .reset( fu__reset[11] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[11] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[11] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[11] ), + .recv_const__msg( fu__recv_const__msg[11] ), + .recv_const__rdy( fu__recv_const__rdy[11] ), + .recv_const__val( fu__recv_const__val[11] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[11] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[11] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[11] ), + .recv_in__msg( fu__recv_in__msg[11] ), + .recv_in__rdy( fu__recv_in__rdy[11] ), + .recv_in__val( fu__recv_in__val[11] ), + .recv_opt__msg( fu__recv_opt__msg[11] ), + .recv_opt__rdy( fu__recv_opt__rdy[11] ), + .recv_opt__val( fu__recv_opt__val[11] ), + .send_out__msg( fu__send_out__msg[11] ), + .send_out__rdy( fu__send_out__rdy[11] ), + .send_out__val( fu__send_out__val[11] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[11] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[11] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[11] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[11] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[11] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[11] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[11] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[11] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[11] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[11] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[11] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[11] ) + ); + + VectorAdderComboRTL__e2d25a29972e2033 fu__12 + ( + .clear( fu__clear[12] ), + .clk( fu__clk[12] ), + .reset( fu__reset[12] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[12] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[12] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[12] ), + .recv_const__msg( fu__recv_const__msg[12] ), + .recv_const__rdy( fu__recv_const__rdy[12] ), + .recv_const__val( fu__recv_const__val[12] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[12] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[12] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[12] ), + .recv_in__msg( fu__recv_in__msg[12] ), + .recv_in__rdy( fu__recv_in__rdy[12] ), + .recv_in__val( fu__recv_in__val[12] ), + .recv_opt__msg( fu__recv_opt__msg[12] ), + .recv_opt__rdy( fu__recv_opt__rdy[12] ), + .recv_opt__val( fu__recv_opt__val[12] ), + .send_out__msg( fu__send_out__msg[12] ), + .send_out__rdy( fu__send_out__rdy[12] ), + .send_out__val( fu__send_out__val[12] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[12] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[12] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[12] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[12] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[12] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[12] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[12] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[12] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[12] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[12] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[12] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[12] ) + ); + + VectorAllReduceRTL__e2d25a29972e2033 fu__13 + ( + .clear( fu__clear[13] ), + .clk( fu__clk[13] ), + .reset( fu__reset[13] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[13] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[13] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[13] ), + .recv_const__msg( fu__recv_const__msg[13] ), + .recv_const__rdy( fu__recv_const__rdy[13] ), + .recv_const__val( fu__recv_const__val[13] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[13] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[13] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[13] ), + .recv_in__msg( fu__recv_in__msg[13] ), + .recv_in__rdy( fu__recv_in__rdy[13] ), + .recv_in__val( fu__recv_in__val[13] ), + .recv_opt__msg( fu__recv_opt__msg[13] ), + .recv_opt__rdy( fu__recv_opt__rdy[13] ), + .recv_opt__val( fu__recv_opt__val[13] ), + .send_out__msg( fu__send_out__msg[13] ), + .send_out__rdy( fu__send_out__rdy[13] ), + .send_out__val( fu__send_out__val[13] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[13] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[13] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[13] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[13] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[13] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[13] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[13] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[13] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[13] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[13] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[13] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[13] ) + ); + + NahRTL__45df3c5556ff02e3 fu__14 + ( + .clear( fu__clear[14] ), + .clk( fu__clk[14] ), + .reset( fu__reset[14] ), + .from_mem_rdata__msg( fu__from_mem_rdata__msg[14] ), + .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[14] ), + .from_mem_rdata__val( fu__from_mem_rdata__val[14] ), + .recv_const__msg( fu__recv_const__msg[14] ), + .recv_const__rdy( fu__recv_const__rdy[14] ), + .recv_const__val( fu__recv_const__val[14] ), + .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[14] ), + .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[14] ), + .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[14] ), + .recv_in__msg( fu__recv_in__msg[14] ), + .recv_in__rdy( fu__recv_in__rdy[14] ), + .recv_in__val( fu__recv_in__val[14] ), + .recv_opt__msg( fu__recv_opt__msg[14] ), + .recv_opt__rdy( fu__recv_opt__rdy[14] ), + .recv_opt__val( fu__recv_opt__val[14] ), + .send_out__msg( fu__send_out__msg[14] ), + .send_out__rdy( fu__send_out__rdy[14] ), + .send_out__val( fu__send_out__val[14] ), + .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[14] ), + .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[14] ), + .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[14] ), + .to_mem_raddr__msg( fu__to_mem_raddr__msg[14] ), + .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[14] ), + .to_mem_raddr__val( fu__to_mem_raddr__val[14] ), + .to_mem_waddr__msg( fu__to_mem_waddr__msg[14] ), + .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[14] ), + .to_mem_waddr__val( fu__to_mem_waddr__val[14] ), + .to_mem_wdata__msg( fu__to_mem_wdata__msg[14] ), + .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[14] ), + .to_mem_wdata__val( fu__to_mem_wdata__val[14] ) + ); + + //------------------------------------------------------------- + // End of component fu[0:14] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py:107 + // @update + // def comb_logic(): + // for j in range(num_outports): + // s.send_out[j].val @= b1(0) + // s.send_out[j].msg @= DataType() + // + // for i in range(s.fu_list_size): + // # const connection. + // s.fu[i].recv_const.msg @= s.recv_const.msg + // s.fu[i].recv_const.val @= s.recv_const.val + // s.fu_recv_const_rdy_vector[i] @= s.fu[i].recv_const.rdy + // + // # opt connection. + // s.fu[i].recv_opt.msg @= s.recv_opt.msg + // # Sets each FU's op code as NAH when prologue execution is not completed. + // # As they are supposed to do nothing during that prologue cycles. + // if s.prologue_count_inport != 0: + // s.fu[i].recv_opt.msg.operation @= OPT_NAH + // s.fu[i].recv_opt.val @= s.recv_opt.val + // s.fu_recv_opt_rdy_vector[i] @= s.fu[i].recv_opt.rdy + // + // # send_out connection. + // for j in range(num_outports): + // # FIXME: need reduce_or here: https://github.com/tancheng/VectorCGRA/issues/51. + // if s.fu[i].send_out[j].val: + // s.send_out[j].msg @= s.fu[i].send_out[j].msg + // s.send_out[j].val @= s.fu[i].send_out[j].val + // s.fu[i].send_out[j].rdy @= s.send_out[j].rdy + // + // s.recv_const.rdy @= reduce_or(s.fu_recv_const_rdy_vector) + // # Operation (especially mem access) won't perform more than once, because once the + // # operation is performance (i.e., the recv_opt.rdy would be set), the `element_done` + // # register would be set and be respected. + // s.recv_opt.rdy @= reduce_or(s.fu_recv_opt_rdy_vector) | (s.prologue_count_inport != 0) + // + // for j in range(num_inports): + // s.recv_in[j].rdy @= b1(0) + // + // # recv_in connection. + // for port in range(num_inports): + // for i in range(s.fu_list_size): + // s.fu[i].recv_in[port].msg @= s.recv_in[port].msg + // s.fu[i].recv_in[port].val @= s.recv_in[port].val + // # s.recv_in[j].rdy @= s.fu[i].recv_in[j].rdy | s.recv_in[j].rdy + // s.fu_recv_in_rdy_vector[port][i] @= s.fu[i].recv_in[port].rdy + // s.recv_in[port].rdy @= reduce_or(s.fu_recv_in_rdy_vector[port]) + + always_comb begin : comb_logic + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin + send_out__val[1'(j)] = 1'd0; + send_out__msg[1'(j)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin + fu__recv_const__msg[4'(i)] = recv_const__msg; + fu__recv_const__val[4'(i)] = recv_const__val; + fu_recv_const_rdy_vector[4'(i)] = fu__recv_const__rdy[4'(i)]; + fu__recv_opt__msg[4'(i)] = recv_opt__msg; + if ( prologue_count_inport != 3'd0 ) begin + fu__recv_opt__msg[4'(i)].operation = 7'( __const__OPT_NAH ); + end + fu__recv_opt__val[4'(i)] = recv_opt__val; + fu_recv_opt_rdy_vector[4'(i)] = fu__recv_opt__rdy[4'(i)]; + for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin + if ( fu__send_out__val[4'(i)][1'(j)] ) begin + send_out__msg[1'(j)] = fu__send_out__msg[4'(i)][1'(j)]; + send_out__val[1'(j)] = fu__send_out__val[4'(i)][1'(j)]; + end + fu__send_out__rdy[4'(i)][1'(j)] = send_out__rdy[1'(j)]; + end + end + recv_const__rdy = ( | fu_recv_const_rdy_vector ); + recv_opt__rdy = ( | fu_recv_opt_rdy_vector ) | ( prologue_count_inport != 3'd0 ); + for ( int unsigned j = 1'd0; j < 3'( __const__num_inports_at_comb_logic ); j += 1'd1 ) + recv_in__rdy[2'(j)] = 1'd0; + for ( int unsigned port = 1'd0; port < 3'( __const__num_inports_at_comb_logic ); port += 1'd1 ) begin + for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin + fu__recv_in__msg[4'(i)][2'(port)] = recv_in__msg[2'(port)]; + fu__recv_in__val[4'(i)][2'(port)] = recv_in__val[2'(port)]; + fu_recv_in_rdy_vector[2'(port)][4'(i)] = fu__recv_in__rdy[4'(i)][2'(port)]; + end + recv_in__rdy[2'(port)] = ( | fu_recv_in_rdy_vector[2'(port)] ); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py:90 + // @update + // def connect_to_controller(): + // for i in range(s.fu_list_size): + // # const connection. + // s.fu[i].recv_from_ctrl_mem.msg @= s.recv_from_ctrl_mem.msg + // s.fu[i].recv_from_ctrl_mem.val @= s.recv_from_ctrl_mem.val + // s.recv_from_controller_rdy_vector[i] @= s.fu[i].recv_from_ctrl_mem.rdy + // s.recv_from_ctrl_mem.rdy @= reduce_or(s.recv_from_controller_rdy_vector) + // + // s.send_to_ctrl_mem.msg @= CgraPayloadType(0, 0, 0, 0, 0) + // s.send_to_ctrl_mem.val @= 0 + // for i in range(s.fu_list_size): + // if s.fu[i].send_to_ctrl_mem.val: + // s.send_to_ctrl_mem.msg @= s.fu[i].send_to_ctrl_mem.msg + // s.send_to_ctrl_mem.val @= s.fu[i].send_to_ctrl_mem.val + // s.fu[i].send_to_ctrl_mem.rdy @= s.send_to_ctrl_mem.rdy + + always_comb begin : connect_to_controller + for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin + fu__recv_from_ctrl_mem__msg[4'(i)] = recv_from_ctrl_mem__msg; + fu__recv_from_ctrl_mem__val[4'(i)] = recv_from_ctrl_mem__val; + recv_from_controller_rdy_vector[4'(i)] = fu__recv_from_ctrl_mem__rdy[4'(i)]; + end + recv_from_ctrl_mem__rdy = ( | recv_from_controller_rdy_vector ); + send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; + send_to_ctrl_mem__val = 1'd0; + for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin + if ( fu__send_to_ctrl_mem__val[4'(i)] ) begin + send_to_ctrl_mem__msg = fu__send_to_ctrl_mem__msg[4'(i)]; + send_to_ctrl_mem__val = fu__send_to_ctrl_mem__val[4'(i)]; + end + fu__send_to_ctrl_mem__rdy[4'(i)] = send_to_ctrl_mem__rdy; + end + end + + assign fu__clk[0] = clk; + assign fu__reset[0] = reset; + assign fu__clk[1] = clk; + assign fu__reset[1] = reset; + assign fu__clk[2] = clk; + assign fu__reset[2] = reset; + assign fu__clk[3] = clk; + assign fu__reset[3] = reset; + assign fu__clk[4] = clk; + assign fu__reset[4] = reset; + assign fu__clk[5] = clk; + assign fu__reset[5] = reset; + assign fu__clk[6] = clk; + assign fu__reset[6] = reset; + assign fu__clk[7] = clk; + assign fu__reset[7] = reset; + assign fu__clk[8] = clk; + assign fu__reset[8] = reset; + assign fu__clk[9] = clk; + assign fu__reset[9] = reset; + assign fu__clk[10] = clk; + assign fu__reset[10] = reset; + assign fu__clk[11] = clk; + assign fu__reset[11] = reset; + assign fu__clk[12] = clk; + assign fu__reset[12] = reset; + assign fu__clk[13] = clk; + assign fu__reset[13] = reset; + assign fu__clk[14] = clk; + assign fu__reset[14] = reset; + assign to_mem_raddr__msg[0] = fu__to_mem_raddr__msg[0]; + assign fu__to_mem_raddr__rdy[0] = to_mem_raddr__rdy[0]; + assign to_mem_raddr__val[0] = fu__to_mem_raddr__val[0]; + assign fu__from_mem_rdata__msg[0] = from_mem_rdata__msg[0]; + assign from_mem_rdata__rdy[0] = fu__from_mem_rdata__rdy[0]; + assign fu__from_mem_rdata__val[0] = from_mem_rdata__val[0]; + assign to_mem_waddr__msg[0] = fu__to_mem_waddr__msg[0]; + assign fu__to_mem_waddr__rdy[0] = to_mem_waddr__rdy[0]; + assign to_mem_waddr__val[0] = fu__to_mem_waddr__val[0]; + assign to_mem_wdata__msg[0] = fu__to_mem_wdata__msg[0]; + assign fu__to_mem_wdata__rdy[0] = to_mem_wdata__rdy[0]; + assign to_mem_wdata__val[0] = fu__to_mem_wdata__val[0]; + assign fu__clear[0] = clear[0]; + assign to_mem_raddr__msg[1] = fu__to_mem_raddr__msg[1]; + assign fu__to_mem_raddr__rdy[1] = to_mem_raddr__rdy[1]; + assign to_mem_raddr__val[1] = fu__to_mem_raddr__val[1]; + assign fu__from_mem_rdata__msg[1] = from_mem_rdata__msg[1]; + assign from_mem_rdata__rdy[1] = fu__from_mem_rdata__rdy[1]; + assign fu__from_mem_rdata__val[1] = from_mem_rdata__val[1]; + assign to_mem_waddr__msg[1] = fu__to_mem_waddr__msg[1]; + assign fu__to_mem_waddr__rdy[1] = to_mem_waddr__rdy[1]; + assign to_mem_waddr__val[1] = fu__to_mem_waddr__val[1]; + assign to_mem_wdata__msg[1] = fu__to_mem_wdata__msg[1]; + assign fu__to_mem_wdata__rdy[1] = to_mem_wdata__rdy[1]; + assign to_mem_wdata__val[1] = fu__to_mem_wdata__val[1]; + assign fu__clear[1] = clear[1]; + assign to_mem_raddr__msg[2] = fu__to_mem_raddr__msg[2]; + assign fu__to_mem_raddr__rdy[2] = to_mem_raddr__rdy[2]; + assign to_mem_raddr__val[2] = fu__to_mem_raddr__val[2]; + assign fu__from_mem_rdata__msg[2] = from_mem_rdata__msg[2]; + assign from_mem_rdata__rdy[2] = fu__from_mem_rdata__rdy[2]; + assign fu__from_mem_rdata__val[2] = from_mem_rdata__val[2]; + assign to_mem_waddr__msg[2] = fu__to_mem_waddr__msg[2]; + assign fu__to_mem_waddr__rdy[2] = to_mem_waddr__rdy[2]; + assign to_mem_waddr__val[2] = fu__to_mem_waddr__val[2]; + assign to_mem_wdata__msg[2] = fu__to_mem_wdata__msg[2]; + assign fu__to_mem_wdata__rdy[2] = to_mem_wdata__rdy[2]; + assign to_mem_wdata__val[2] = fu__to_mem_wdata__val[2]; + assign fu__clear[2] = clear[2]; + assign to_mem_raddr__msg[3] = fu__to_mem_raddr__msg[3]; + assign fu__to_mem_raddr__rdy[3] = to_mem_raddr__rdy[3]; + assign to_mem_raddr__val[3] = fu__to_mem_raddr__val[3]; + assign fu__from_mem_rdata__msg[3] = from_mem_rdata__msg[3]; + assign from_mem_rdata__rdy[3] = fu__from_mem_rdata__rdy[3]; + assign fu__from_mem_rdata__val[3] = from_mem_rdata__val[3]; + assign to_mem_waddr__msg[3] = fu__to_mem_waddr__msg[3]; + assign fu__to_mem_waddr__rdy[3] = to_mem_waddr__rdy[3]; + assign to_mem_waddr__val[3] = fu__to_mem_waddr__val[3]; + assign to_mem_wdata__msg[3] = fu__to_mem_wdata__msg[3]; + assign fu__to_mem_wdata__rdy[3] = to_mem_wdata__rdy[3]; + assign to_mem_wdata__val[3] = fu__to_mem_wdata__val[3]; + assign fu__clear[3] = clear[3]; + assign to_mem_raddr__msg[4] = fu__to_mem_raddr__msg[4]; + assign fu__to_mem_raddr__rdy[4] = to_mem_raddr__rdy[4]; + assign to_mem_raddr__val[4] = fu__to_mem_raddr__val[4]; + assign fu__from_mem_rdata__msg[4] = from_mem_rdata__msg[4]; + assign from_mem_rdata__rdy[4] = fu__from_mem_rdata__rdy[4]; + assign fu__from_mem_rdata__val[4] = from_mem_rdata__val[4]; + assign to_mem_waddr__msg[4] = fu__to_mem_waddr__msg[4]; + assign fu__to_mem_waddr__rdy[4] = to_mem_waddr__rdy[4]; + assign to_mem_waddr__val[4] = fu__to_mem_waddr__val[4]; + assign to_mem_wdata__msg[4] = fu__to_mem_wdata__msg[4]; + assign fu__to_mem_wdata__rdy[4] = to_mem_wdata__rdy[4]; + assign to_mem_wdata__val[4] = fu__to_mem_wdata__val[4]; + assign fu__clear[4] = clear[4]; + assign to_mem_raddr__msg[5] = fu__to_mem_raddr__msg[5]; + assign fu__to_mem_raddr__rdy[5] = to_mem_raddr__rdy[5]; + assign to_mem_raddr__val[5] = fu__to_mem_raddr__val[5]; + assign fu__from_mem_rdata__msg[5] = from_mem_rdata__msg[5]; + assign from_mem_rdata__rdy[5] = fu__from_mem_rdata__rdy[5]; + assign fu__from_mem_rdata__val[5] = from_mem_rdata__val[5]; + assign to_mem_waddr__msg[5] = fu__to_mem_waddr__msg[5]; + assign fu__to_mem_waddr__rdy[5] = to_mem_waddr__rdy[5]; + assign to_mem_waddr__val[5] = fu__to_mem_waddr__val[5]; + assign to_mem_wdata__msg[5] = fu__to_mem_wdata__msg[5]; + assign fu__to_mem_wdata__rdy[5] = to_mem_wdata__rdy[5]; + assign to_mem_wdata__val[5] = fu__to_mem_wdata__val[5]; + assign fu__clear[5] = clear[5]; + assign to_mem_raddr__msg[6] = fu__to_mem_raddr__msg[6]; + assign fu__to_mem_raddr__rdy[6] = to_mem_raddr__rdy[6]; + assign to_mem_raddr__val[6] = fu__to_mem_raddr__val[6]; + assign fu__from_mem_rdata__msg[6] = from_mem_rdata__msg[6]; + assign from_mem_rdata__rdy[6] = fu__from_mem_rdata__rdy[6]; + assign fu__from_mem_rdata__val[6] = from_mem_rdata__val[6]; + assign to_mem_waddr__msg[6] = fu__to_mem_waddr__msg[6]; + assign fu__to_mem_waddr__rdy[6] = to_mem_waddr__rdy[6]; + assign to_mem_waddr__val[6] = fu__to_mem_waddr__val[6]; + assign to_mem_wdata__msg[6] = fu__to_mem_wdata__msg[6]; + assign fu__to_mem_wdata__rdy[6] = to_mem_wdata__rdy[6]; + assign to_mem_wdata__val[6] = fu__to_mem_wdata__val[6]; + assign fu__clear[6] = clear[6]; + assign to_mem_raddr__msg[7] = fu__to_mem_raddr__msg[7]; + assign fu__to_mem_raddr__rdy[7] = to_mem_raddr__rdy[7]; + assign to_mem_raddr__val[7] = fu__to_mem_raddr__val[7]; + assign fu__from_mem_rdata__msg[7] = from_mem_rdata__msg[7]; + assign from_mem_rdata__rdy[7] = fu__from_mem_rdata__rdy[7]; + assign fu__from_mem_rdata__val[7] = from_mem_rdata__val[7]; + assign to_mem_waddr__msg[7] = fu__to_mem_waddr__msg[7]; + assign fu__to_mem_waddr__rdy[7] = to_mem_waddr__rdy[7]; + assign to_mem_waddr__val[7] = fu__to_mem_waddr__val[7]; + assign to_mem_wdata__msg[7] = fu__to_mem_wdata__msg[7]; + assign fu__to_mem_wdata__rdy[7] = to_mem_wdata__rdy[7]; + assign to_mem_wdata__val[7] = fu__to_mem_wdata__val[7]; + assign fu__clear[7] = clear[7]; + assign to_mem_raddr__msg[8] = fu__to_mem_raddr__msg[8]; + assign fu__to_mem_raddr__rdy[8] = to_mem_raddr__rdy[8]; + assign to_mem_raddr__val[8] = fu__to_mem_raddr__val[8]; + assign fu__from_mem_rdata__msg[8] = from_mem_rdata__msg[8]; + assign from_mem_rdata__rdy[8] = fu__from_mem_rdata__rdy[8]; + assign fu__from_mem_rdata__val[8] = from_mem_rdata__val[8]; + assign to_mem_waddr__msg[8] = fu__to_mem_waddr__msg[8]; + assign fu__to_mem_waddr__rdy[8] = to_mem_waddr__rdy[8]; + assign to_mem_waddr__val[8] = fu__to_mem_waddr__val[8]; + assign to_mem_wdata__msg[8] = fu__to_mem_wdata__msg[8]; + assign fu__to_mem_wdata__rdy[8] = to_mem_wdata__rdy[8]; + assign to_mem_wdata__val[8] = fu__to_mem_wdata__val[8]; + assign fu__clear[8] = clear[8]; + assign to_mem_raddr__msg[9] = fu__to_mem_raddr__msg[9]; + assign fu__to_mem_raddr__rdy[9] = to_mem_raddr__rdy[9]; + assign to_mem_raddr__val[9] = fu__to_mem_raddr__val[9]; + assign fu__from_mem_rdata__msg[9] = from_mem_rdata__msg[9]; + assign from_mem_rdata__rdy[9] = fu__from_mem_rdata__rdy[9]; + assign fu__from_mem_rdata__val[9] = from_mem_rdata__val[9]; + assign to_mem_waddr__msg[9] = fu__to_mem_waddr__msg[9]; + assign fu__to_mem_waddr__rdy[9] = to_mem_waddr__rdy[9]; + assign to_mem_waddr__val[9] = fu__to_mem_waddr__val[9]; + assign to_mem_wdata__msg[9] = fu__to_mem_wdata__msg[9]; + assign fu__to_mem_wdata__rdy[9] = to_mem_wdata__rdy[9]; + assign to_mem_wdata__val[9] = fu__to_mem_wdata__val[9]; + assign fu__clear[9] = clear[9]; + assign to_mem_raddr__msg[10] = fu__to_mem_raddr__msg[10]; + assign fu__to_mem_raddr__rdy[10] = to_mem_raddr__rdy[10]; + assign to_mem_raddr__val[10] = fu__to_mem_raddr__val[10]; + assign fu__from_mem_rdata__msg[10] = from_mem_rdata__msg[10]; + assign from_mem_rdata__rdy[10] = fu__from_mem_rdata__rdy[10]; + assign fu__from_mem_rdata__val[10] = from_mem_rdata__val[10]; + assign to_mem_waddr__msg[10] = fu__to_mem_waddr__msg[10]; + assign fu__to_mem_waddr__rdy[10] = to_mem_waddr__rdy[10]; + assign to_mem_waddr__val[10] = fu__to_mem_waddr__val[10]; + assign to_mem_wdata__msg[10] = fu__to_mem_wdata__msg[10]; + assign fu__to_mem_wdata__rdy[10] = to_mem_wdata__rdy[10]; + assign to_mem_wdata__val[10] = fu__to_mem_wdata__val[10]; + assign fu__clear[10] = clear[10]; + assign to_mem_raddr__msg[11] = fu__to_mem_raddr__msg[11]; + assign fu__to_mem_raddr__rdy[11] = to_mem_raddr__rdy[11]; + assign to_mem_raddr__val[11] = fu__to_mem_raddr__val[11]; + assign fu__from_mem_rdata__msg[11] = from_mem_rdata__msg[11]; + assign from_mem_rdata__rdy[11] = fu__from_mem_rdata__rdy[11]; + assign fu__from_mem_rdata__val[11] = from_mem_rdata__val[11]; + assign to_mem_waddr__msg[11] = fu__to_mem_waddr__msg[11]; + assign fu__to_mem_waddr__rdy[11] = to_mem_waddr__rdy[11]; + assign to_mem_waddr__val[11] = fu__to_mem_waddr__val[11]; + assign to_mem_wdata__msg[11] = fu__to_mem_wdata__msg[11]; + assign fu__to_mem_wdata__rdy[11] = to_mem_wdata__rdy[11]; + assign to_mem_wdata__val[11] = fu__to_mem_wdata__val[11]; + assign fu__clear[11] = clear[11]; + assign to_mem_raddr__msg[12] = fu__to_mem_raddr__msg[12]; + assign fu__to_mem_raddr__rdy[12] = to_mem_raddr__rdy[12]; + assign to_mem_raddr__val[12] = fu__to_mem_raddr__val[12]; + assign fu__from_mem_rdata__msg[12] = from_mem_rdata__msg[12]; + assign from_mem_rdata__rdy[12] = fu__from_mem_rdata__rdy[12]; + assign fu__from_mem_rdata__val[12] = from_mem_rdata__val[12]; + assign to_mem_waddr__msg[12] = fu__to_mem_waddr__msg[12]; + assign fu__to_mem_waddr__rdy[12] = to_mem_waddr__rdy[12]; + assign to_mem_waddr__val[12] = fu__to_mem_waddr__val[12]; + assign to_mem_wdata__msg[12] = fu__to_mem_wdata__msg[12]; + assign fu__to_mem_wdata__rdy[12] = to_mem_wdata__rdy[12]; + assign to_mem_wdata__val[12] = fu__to_mem_wdata__val[12]; + assign fu__clear[12] = clear[12]; + assign to_mem_raddr__msg[13] = fu__to_mem_raddr__msg[13]; + assign fu__to_mem_raddr__rdy[13] = to_mem_raddr__rdy[13]; + assign to_mem_raddr__val[13] = fu__to_mem_raddr__val[13]; + assign fu__from_mem_rdata__msg[13] = from_mem_rdata__msg[13]; + assign from_mem_rdata__rdy[13] = fu__from_mem_rdata__rdy[13]; + assign fu__from_mem_rdata__val[13] = from_mem_rdata__val[13]; + assign to_mem_waddr__msg[13] = fu__to_mem_waddr__msg[13]; + assign fu__to_mem_waddr__rdy[13] = to_mem_waddr__rdy[13]; + assign to_mem_waddr__val[13] = fu__to_mem_waddr__val[13]; + assign to_mem_wdata__msg[13] = fu__to_mem_wdata__msg[13]; + assign fu__to_mem_wdata__rdy[13] = to_mem_wdata__rdy[13]; + assign to_mem_wdata__val[13] = fu__to_mem_wdata__val[13]; + assign fu__clear[13] = clear[13]; + assign to_mem_raddr__msg[14] = fu__to_mem_raddr__msg[14]; + assign fu__to_mem_raddr__rdy[14] = to_mem_raddr__rdy[14]; + assign to_mem_raddr__val[14] = fu__to_mem_raddr__val[14]; + assign fu__from_mem_rdata__msg[14] = from_mem_rdata__msg[14]; + assign from_mem_rdata__rdy[14] = fu__from_mem_rdata__rdy[14]; + assign fu__from_mem_rdata__val[14] = from_mem_rdata__val[14]; + assign to_mem_waddr__msg[14] = fu__to_mem_waddr__msg[14]; + assign fu__to_mem_waddr__rdy[14] = to_mem_waddr__rdy[14]; + assign to_mem_waddr__val[14] = fu__to_mem_waddr__val[14]; + assign to_mem_wdata__msg[14] = fu__to_mem_wdata__msg[14]; + assign fu__to_mem_wdata__rdy[14] = to_mem_wdata__rdy[14]; + assign to_mem_wdata__val[14] = fu__to_mem_wdata__val[14]; + assign fu__clear[14] = clear[14]; + +endmodule + + +// PyMTL Component CrossbarRTL Definition +// Full name: CrossbarRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_2__num_outports_8__num_cgras_4__num_tiles_16__ctrl_mem_size_16__outport_towards_local_base_id_4 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py + +module CrossbarRTL__45ee026205c61975 +( + input logic [1:0] cgra_id , + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] compute_done , + input logic [0:0] crossbar_id , + input logic [1:0] crossbar_outport [0:7], + input logic [3:0] ctrl_addr_inport , + input logic [2:0] prologue_count_inport [0:15][0:1], + input logic [0:0] reset , + input logic [4:0] tile_id , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:1] , + output logic [0:0] recv_data__rdy [0:1] , + input logic [0:0] recv_data__val [0:1] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:7] , + input logic [0:0] send_data__rdy [0:7] , + output logic [0:0] send_data__val [0:7] +); + localparam logic [1:0] __const__num_inports_at_update_signal = 2'd2; + localparam logic [3:0] __const__num_outports_at_update_signal = 4'd8; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter = 5'd16; + localparam logic [1:0] __const__num_inports_at_update_prologue_counter = 2'd2; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter_next = 5'd16; + localparam logic [1:0] __const__num_inports_at_update_prologue_counter_next = 2'd2; + localparam logic [3:0] __const__num_outports_at_update_prologue_counter_next = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_prologue_allowing_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_prologue_or_valid_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_in_dir_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_rdy_vector = 4'd8; + localparam logic [2:0] __const__outport_towards_local_base_id_at_update_rdy_vector = 3'd4; + localparam logic [3:0] __const__num_outports_at_update_valid_vector = 4'd8; + localparam logic [1:0] __const__num_inports_at_update_recv_required_vector = 2'd2; + localparam logic [3:0] __const__num_outports_at_update_recv_required_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_send_required_vector = 4'd8; + logic [1:0] in_dir [0:7]; + logic [0:0] in_dir_local [0:7]; + logic [7:0] prologue_allowing_vector; + logic [2:0] prologue_count_wire [0:15][0:1]; + logic [2:0] prologue_counter [0:15][0:1]; + logic [2:0] prologue_counter_next [0:15][0:1]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_msg [0:1]; + logic [0:0] recv_data_val [0:1]; + logic [1:0] recv_required_vector; + logic [7:0] recv_valid_or_prologue_allowing_vector; + logic [7:0] recv_valid_vector; + logic [7:0] send_rdy_vector; + logic [7:0] send_required_vector; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:153 + // @update + // def update_in_dir_vector(): + // + // for i in range(num_outports): + // s.in_dir[i] @= 0 + // s.in_dir_local[i] @= 0 + // + // for i in range(num_outports): + // s.in_dir[i] @= s.crossbar_outport[i] + // if s.in_dir[i] > 0: + // s.in_dir_local[i] @= trunc(s.in_dir[i] - 1, NumInportType) + + always_comb begin : update_in_dir_vector + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin + in_dir[3'(i)] = 2'd0; + in_dir_local[3'(i)] = 1'd0; + end + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin + in_dir[3'(i)] = crossbar_outport[3'(i)]; + if ( in_dir[3'(i)] > 2'd0 ) begin + in_dir_local[3'(i)] = 1'(in_dir[3'(i)] - 2'd1); + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:134 + // @update + // def update_prologue_allowing_vector(): + // s.prologue_allowing_vector @= 0 + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // # Records whether the prologue steps have already been satisfied. + // s.prologue_allowing_vector[i] @= \ + // (s.prologue_counter[s.ctrl_addr_inport][s.in_dir_local[i]] < \ + // s.prologue_count_wire[s.ctrl_addr_inport][s.in_dir_local[i]]) + // else: + // s.prologue_allowing_vector[i] @= 1 + + always_comb begin : update_prologue_allowing_vector + prologue_allowing_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_allowing_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 2'd0 ) begin + prologue_allowing_vector[3'(i)] = prologue_counter[ctrl_addr_inport][in_dir_local[3'(i)]] < prologue_count_wire[ctrl_addr_inport][in_dir_local[3'(i)]]; + end + else + prologue_allowing_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:119 + // @update + // def update_prologue_counter_next(): + // # Nested-loop to update the prologue counter, to avoid dynamic indexing to + // # work-around Yosys issue: https://github.com/tancheng/VectorCGRA/issues/148 + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + // for j in range(num_outports): + // if s.recv_opt.rdy & \ + // (s.in_dir[j] > 0) & \ + // (s.in_dir_local[j] == i) & \ + // (addr == s.ctrl_addr_inport) & \ + // (s.prologue_counter[addr][i] < s.prologue_count_wire[addr][i]): + // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + 1 + + always_comb begin : update_prologue_counter_next + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter_next ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter_next ); i += 1'd1 ) begin + prologue_counter_next[4'(addr)][1'(i)] = prologue_counter[4'(addr)][1'(i)]; + for ( int unsigned j = 1'd0; j < 4'( __const__num_outports_at_update_prologue_counter_next ); j += 1'd1 ) + if ( ( ( ( recv_opt__rdy & ( in_dir[3'(j)] > 2'd0 ) ) & ( in_dir_local[3'(j)] == 1'(i) ) ) & ( 4'(addr) == ctrl_addr_inport ) ) & ( prologue_counter[4'(addr)][1'(i)] < prologue_count_wire[4'(addr)][1'(i)] ) ) begin + prologue_counter_next[4'(addr)][1'(i)] = prologue_counter[4'(addr)][1'(i)] + 3'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:146 + // @update + // def update_prologue_or_valid_vector(): + // s.recv_valid_or_prologue_allowing_vector @= 0 + // for i in range(num_outports): + // s.recv_valid_or_prologue_allowing_vector[i] @= \ + // s.recv_valid_vector[i] | s.prologue_allowing_vector[i] + + always_comb begin : update_prologue_or_valid_vector + recv_valid_or_prologue_allowing_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_or_valid_vector ); i += 1'd1 ) + recv_valid_or_prologue_allowing_vector[3'(i)] = recv_valid_vector[3'(i)] | prologue_allowing_vector[3'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:165 + // @update + // def update_rdy_vector(): + // s.send_rdy_vector @= 0 + // for i in range(num_outports): + // # The `num_inports` indicates the number of outports that go to other tiles. + // # Specifically, if the compute already done, we shouldn't care the ones + // # (i.e., i >= num_inports) go to the FU's inports. In other words, we skip + // # the rdy checking on the FU's inports (connecting from crossbar_outport) if + // # the compute is already completed. + // if (s.in_dir[i] > 0) & \ + // (~s.compute_done | (i < outport_towards_local_base_id)): + // s.send_rdy_vector[i] @= s.send_data[i].rdy + // else: + // s.send_rdy_vector[i] @= 1 + + always_comb begin : update_rdy_vector + send_rdy_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_rdy_vector ); i += 1'd1 ) + if ( ( in_dir[3'(i)] > 2'd0 ) & ( ( ~compute_done ) | ( 3'(i) < 3'( __const__outport_towards_local_base_id_at_update_rdy_vector ) ) ) ) begin + send_rdy_vector[3'(i)] = send_data__rdy[3'(i)]; + end + else + send_rdy_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:189 + // @update + // def update_recv_required_vector(): + // for i in range(num_inports): + // s.recv_required_vector[i] @= 0 + // + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.recv_required_vector[s.in_dir_local[i]] @= 1 + + always_comb begin : update_recv_required_vector + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_recv_required_vector ); i += 1'd1 ) + recv_required_vector[1'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_recv_required_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 2'd0 ) begin + recv_required_vector[in_dir_local[3'(i)]] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:198 + // @update + // def update_send_required_vector(): + // + // for i in range(num_outports): + // s.send_required_vector[i] @= 0 + // + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.send_required_vector[i] @= 1 + + always_comb begin : update_send_required_vector + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) + send_required_vector[3'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 2'd0 ) begin + send_required_vector[3'(i)] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:82 + // @update + // def update_signal(): + // for i in range(num_inports): + // s.recv_data[i].rdy @= 0 + // for i in range(num_outports): + // s.send_data[i].val @= 0 + // s.send_data[i].msg @= DataType() + // s.recv_opt.rdy @= 0 + // + // if s.recv_opt.val & (s.recv_opt.msg.operation != OPT_START): + // for i in range(num_inports): + // s.recv_data[i].rdy @= reduce_and(s.recv_valid_vector) & \ + // reduce_and(s.send_rdy_vector) & \ + // s.recv_required_vector[i] + // + // for i in range(num_outports): + // s.send_data[i].val @= reduce_and(s.recv_valid_vector) & \ + // s.send_required_vector[i] + // if reduce_and(s.recv_valid_vector) & \ + // s.send_required_vector[i]: + // s.send_data[i].msg.payload @= s.recv_data_msg[s.in_dir_local[i]].payload + // s.send_data[i].msg.predicate @= s.recv_data_msg[s.in_dir_local[i]].predicate + // + // s.recv_opt.rdy @= reduce_and(s.send_rdy_vector) & \ + // reduce_and(s.recv_valid_or_prologue_allowing_vector) + + always_comb begin : update_signal + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_signal ); i += 1'd1 ) + recv_data__rdy[1'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin + send_data__val[3'(i)] = 1'd0; + send_data__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_opt__rdy = 1'd0; + if ( recv_opt__val & ( recv_opt__msg.operation != 7'( __const__OPT_START ) ) ) begin + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_signal ); i += 1'd1 ) + recv_data__rdy[1'(i)] = ( ( & recv_valid_vector ) & ( & send_rdy_vector ) ) & recv_required_vector[1'(i)]; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin + send_data__val[3'(i)] = ( & recv_valid_vector ) & send_required_vector[3'(i)]; + if ( ( & recv_valid_vector ) & send_required_vector[3'(i)] ) begin + send_data__msg[3'(i)].payload = recv_data_msg[in_dir_local[3'(i)]].payload; + send_data__msg[3'(i)].predicate = recv_data_msg[in_dir_local[3'(i)]].predicate; + end + end + recv_opt__rdy = ( & send_rdy_vector ) & ( & recv_valid_or_prologue_allowing_vector ); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:180 + // @update + // def update_valid_vector(): + // s.recv_valid_vector @= 0 + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.recv_valid_vector[i] @= s.recv_data_val[s.in_dir_local[i]] + // else: + // s.recv_valid_vector[i] @= 1 + + always_comb begin : update_valid_vector + recv_valid_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_valid_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 2'd0 ) begin + recv_valid_vector[3'(i)] = recv_data_val[in_dir_local[3'(i)]]; + end + else + recv_valid_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:108 + // @update_ff + // def update_prologue_counter(): + // if s.reset | s.clear: + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter[addr][i] <<= 0 + // else: + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter[addr][i] <<= s.prologue_counter_next[addr][i] + + always_ff @(posedge clk) begin : update_prologue_counter + if ( reset | clear ) begin + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) + prologue_counter[4'(addr)][1'(i)] <= 3'd0; + end + else + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) + prologue_counter[4'(addr)][1'(i)] <= prologue_counter_next[4'(addr)][1'(i)]; + end + + assign recv_data_msg[0] = recv_data__msg[0]; + assign recv_data_val[0] = recv_data__val[0]; + assign recv_data_msg[1] = recv_data__msg[1]; + assign recv_data_val[1] = recv_data__val[1]; + assign prologue_count_wire[0][0] = prologue_count_inport[0][0]; + assign prologue_count_wire[0][1] = prologue_count_inport[0][1]; + assign prologue_count_wire[1][0] = prologue_count_inport[1][0]; + assign prologue_count_wire[1][1] = prologue_count_inport[1][1]; + assign prologue_count_wire[2][0] = prologue_count_inport[2][0]; + assign prologue_count_wire[2][1] = prologue_count_inport[2][1]; + assign prologue_count_wire[3][0] = prologue_count_inport[3][0]; + assign prologue_count_wire[3][1] = prologue_count_inport[3][1]; + assign prologue_count_wire[4][0] = prologue_count_inport[4][0]; + assign prologue_count_wire[4][1] = prologue_count_inport[4][1]; + assign prologue_count_wire[5][0] = prologue_count_inport[5][0]; + assign prologue_count_wire[5][1] = prologue_count_inport[5][1]; + assign prologue_count_wire[6][0] = prologue_count_inport[6][0]; + assign prologue_count_wire[6][1] = prologue_count_inport[6][1]; + assign prologue_count_wire[7][0] = prologue_count_inport[7][0]; + assign prologue_count_wire[7][1] = prologue_count_inport[7][1]; + assign prologue_count_wire[8][0] = prologue_count_inport[8][0]; + assign prologue_count_wire[8][1] = prologue_count_inport[8][1]; + assign prologue_count_wire[9][0] = prologue_count_inport[9][0]; + assign prologue_count_wire[9][1] = prologue_count_inport[9][1]; + assign prologue_count_wire[10][0] = prologue_count_inport[10][0]; + assign prologue_count_wire[10][1] = prologue_count_inport[10][1]; + assign prologue_count_wire[11][0] = prologue_count_inport[11][0]; + assign prologue_count_wire[11][1] = prologue_count_inport[11][1]; + assign prologue_count_wire[12][0] = prologue_count_inport[12][0]; + assign prologue_count_wire[12][1] = prologue_count_inport[12][1]; + assign prologue_count_wire[13][0] = prologue_count_inport[13][0]; + assign prologue_count_wire[13][1] = prologue_count_inport[13][1]; + assign prologue_count_wire[14][0] = prologue_count_inport[14][0]; + assign prologue_count_wire[14][1] = prologue_count_inport[14][1]; + assign prologue_count_wire[15][0] = prologue_count_inport[15][0]; + assign prologue_count_wire[15][1] = prologue_count_inport[15][1]; + +endmodule + + +// PyMTL Component RegisterBankRTL Definition +// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_0__num_registers_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py + +module RegisterBankRTL__649561e613f42979 +( + input logic [0:0] clk , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , + input logic [0:0] inport_valid [0:2], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], + input logic [0:0] reset , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , + input logic [0:0] send_data_to_fu__rdy , + output logic [0:0] send_data_to_fu__val +); + localparam logic [0:0] __const__reg_bank_id_at_access_registers = 1'd0; + localparam logic [0:0] __const__reg_bank_id_at_update_send_val = 1'd0; + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__bd22936ec5812d0d reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [1:0] __tmpvar__access_registers_write_reg_from; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 + // @update + // def access_registers(): + // # Initializes signals. + // s.reg_file.raddr[0] @= AddrType() + // s.send_data_to_fu.msg @= DataType() + // s.reg_file.waddr[0] @= AddrType() + // s.reg_file.wdata[0] @= DataType() + // s.reg_file.wen[0] @= 0 + // + // if s.inport_opt.read_reg_from[reg_bank_id]: + // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] + // s.send_data_to_fu.msg @= s.reg_file.rdata[0] + // + // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] + // if ~s.reset & (write_reg_from > 0): + // if s.inport_valid[write_reg_from - 1]: + // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] + // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] + // s.reg_file.wen[0] @= 1 + + always_comb begin : access_registers + reg_file__raddr[1'd0] = 4'd0; + send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__waddr[1'd0] = 4'd0; + reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__wen[1'd0] = 1'd0; + if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin + reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + send_data_to_fu__msg = reg_file__rdata[1'd0]; + end + __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; + if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin + if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin + reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; + reg_file__wen[1'd0] = 1'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 + // @update + // def update_send_val(): + // s.send_data_to_fu.val @= 0 + // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: + // s.send_data_to_fu.val @= 1 + + always_comb begin : update_send_val + send_data_to_fu__val = 1'd0; + if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin + send_data_to_fu__val = 1'd1; + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + +endmodule + + +// PyMTL Component RegisterBankRTL Definition +// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_1__num_registers_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py + +module RegisterBankRTL__0a5bdf408d921386 +( + input logic [0:0] clk , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , + input logic [0:0] inport_valid [0:2], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], + input logic [0:0] reset , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , + input logic [0:0] send_data_to_fu__rdy , + output logic [0:0] send_data_to_fu__val +); + localparam logic [0:0] __const__reg_bank_id_at_access_registers = 1'd1; + localparam logic [0:0] __const__reg_bank_id_at_update_send_val = 1'd1; + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__bd22936ec5812d0d reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [1:0] __tmpvar__access_registers_write_reg_from; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 + // @update + // def access_registers(): + // # Initializes signals. + // s.reg_file.raddr[0] @= AddrType() + // s.send_data_to_fu.msg @= DataType() + // s.reg_file.waddr[0] @= AddrType() + // s.reg_file.wdata[0] @= DataType() + // s.reg_file.wen[0] @= 0 + // + // if s.inport_opt.read_reg_from[reg_bank_id]: + // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] + // s.send_data_to_fu.msg @= s.reg_file.rdata[0] + // + // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] + // if ~s.reset & (write_reg_from > 0): + // if s.inport_valid[write_reg_from - 1]: + // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] + // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] + // s.reg_file.wen[0] @= 1 + + always_comb begin : access_registers + reg_file__raddr[1'd0] = 4'd0; + send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__waddr[1'd0] = 4'd0; + reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__wen[1'd0] = 1'd0; + if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin + reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + send_data_to_fu__msg = reg_file__rdata[1'd0]; + end + __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; + if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin + if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin + reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; + reg_file__wen[1'd0] = 1'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 + // @update + // def update_send_val(): + // s.send_data_to_fu.val @= 0 + // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: + // s.send_data_to_fu.val @= 1 + + always_comb begin : update_send_val + send_data_to_fu__val = 1'd0; + if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin + send_data_to_fu__val = 1'd1; + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + +endmodule + + +// PyMTL Component RegisterBankRTL Definition +// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_2__num_registers_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py + +module RegisterBankRTL__ddae41891d80e575 +( + input logic [0:0] clk , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , + input logic [0:0] inport_valid [0:2], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], + input logic [0:0] reset , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , + input logic [0:0] send_data_to_fu__rdy , + output logic [0:0] send_data_to_fu__val +); + localparam logic [1:0] __const__reg_bank_id_at_access_registers = 2'd2; + localparam logic [1:0] __const__reg_bank_id_at_update_send_val = 2'd2; + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__bd22936ec5812d0d reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [1:0] __tmpvar__access_registers_write_reg_from; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 + // @update + // def access_registers(): + // # Initializes signals. + // s.reg_file.raddr[0] @= AddrType() + // s.send_data_to_fu.msg @= DataType() + // s.reg_file.waddr[0] @= AddrType() + // s.reg_file.wdata[0] @= DataType() + // s.reg_file.wen[0] @= 0 + // + // if s.inport_opt.read_reg_from[reg_bank_id]: + // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] + // s.send_data_to_fu.msg @= s.reg_file.rdata[0] + // + // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] + // if ~s.reset & (write_reg_from > 0): + // if s.inport_valid[write_reg_from - 1]: + // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] + // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] + // s.reg_file.wen[0] @= 1 + + always_comb begin : access_registers + reg_file__raddr[1'd0] = 4'd0; + send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__waddr[1'd0] = 4'd0; + reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__wen[1'd0] = 1'd0; + if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin + reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + send_data_to_fu__msg = reg_file__rdata[1'd0]; + end + __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; + if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin + if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin + reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; + reg_file__wen[1'd0] = 1'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 + // @update + // def update_send_val(): + // s.send_data_to_fu.val @= 0 + // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: + // s.send_data_to_fu.val @= 1 + + always_comb begin : update_send_val + send_data_to_fu__val = 1'd0; + if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin + send_data_to_fu__val = 1'd1; + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + +endmodule + + +// PyMTL Component RegisterBankRTL Definition +// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_3__num_registers_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py + +module RegisterBankRTL__ff0588d25abf2ed3 +( + input logic [0:0] clk , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , + input logic [0:0] inport_valid [0:2], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], + input logic [0:0] reset , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , + input logic [0:0] send_data_to_fu__rdy , + output logic [0:0] send_data_to_fu__val +); + localparam logic [1:0] __const__reg_bank_id_at_access_registers = 2'd3; + localparam logic [1:0] __const__reg_bank_id_at_update_send_val = 2'd3; + //------------------------------------------------------------- + // Component reg_file + //------------------------------------------------------------- + + logic [0:0] reg_file__clk; + logic [3:0] reg_file__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; + logic [0:0] reg_file__reset; + logic [3:0] reg_file__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; + logic [0:0] reg_file__wen [0:0]; + + RegisterFile__bd22936ec5812d0d reg_file + ( + .clk( reg_file__clk ), + .raddr( reg_file__raddr ), + .rdata( reg_file__rdata ), + .reset( reg_file__reset ), + .waddr( reg_file__waddr ), + .wdata( reg_file__wdata ), + .wen( reg_file__wen ) + ); + + //------------------------------------------------------------- + // End of component reg_file + //------------------------------------------------------------- + logic [1:0] __tmpvar__access_registers_write_reg_from; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 + // @update + // def access_registers(): + // # Initializes signals. + // s.reg_file.raddr[0] @= AddrType() + // s.send_data_to_fu.msg @= DataType() + // s.reg_file.waddr[0] @= AddrType() + // s.reg_file.wdata[0] @= DataType() + // s.reg_file.wen[0] @= 0 + // + // if s.inport_opt.read_reg_from[reg_bank_id]: + // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] + // s.send_data_to_fu.msg @= s.reg_file.rdata[0] + // + // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] + // if ~s.reset & (write_reg_from > 0): + // if s.inport_valid[write_reg_from - 1]: + // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] + // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] + // s.reg_file.wen[0] @= 1 + + always_comb begin : access_registers + reg_file__raddr[1'd0] = 4'd0; + send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__waddr[1'd0] = 4'd0; + reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + reg_file__wen[1'd0] = 1'd0; + if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin + reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + send_data_to_fu__msg = reg_file__rdata[1'd0]; + end + __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; + if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin + if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin + reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; + reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; + reg_file__wen[1'd0] = 1'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 + // @update + // def update_send_val(): + // s.send_data_to_fu.val @= 0 + // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: + // s.send_data_to_fu.val @= 1 + + always_comb begin : update_send_val + send_data_to_fu__val = 1'd0; + if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin + send_data_to_fu__val = 1'd1; + end + end + + assign reg_file__clk = clk; + assign reg_file__reset = reset; + +endmodule + + +// PyMTL Component RegisterClusterRTL Definition +// Full name: RegisterClusterRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_reg_banks_4__num_registers_per_reg_bank_16 +// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterClusterRTL.py + +module RegisterClusterRTL__7f2febb613462546 +( + input logic [0:0] clk , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_const__msg [0:3] , + output logic [0:0] recv_data_from_const__rdy [0:3] , + input logic [0:0] recv_data_from_const__val [0:3] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_fu_crossbar__msg [0:3] , + output logic [0:0] recv_data_from_fu_crossbar__rdy [0:3] , + input logic [0:0] recv_data_from_fu_crossbar__val [0:3] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_routing_crossbar__msg [0:3] , + output logic [0:0] recv_data_from_routing_crossbar__rdy [0:3] , + input logic [0:0] recv_data_from_routing_crossbar__val [0:3] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg [0:3] , + input logic [0:0] send_data_to_fu__rdy [0:3] , + output logic [0:0] send_data_to_fu__val [0:3] +); + localparam logic [2:0] __const__num_reg_banks_at_update_msgs_signals = 3'd4; + //------------------------------------------------------------- + // Component reg_bank[0:3] + //------------------------------------------------------------- + + logic [0:0] reg_bank__clk [0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_bank__inport_opt [0:3]; + logic [0:0] reg_bank__inport_valid [0:3][0:2]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_bank__inport_wdata [0:3][0:2]; + logic [0:0] reg_bank__reset [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_bank__send_data_to_fu__msg [0:3]; + logic [0:0] reg_bank__send_data_to_fu__rdy [0:3]; + logic [0:0] reg_bank__send_data_to_fu__val [0:3]; + + RegisterBankRTL__649561e613f42979 reg_bank__0 + ( + .clk( reg_bank__clk[0] ), + .inport_opt( reg_bank__inport_opt[0] ), + .inport_valid( reg_bank__inport_valid[0] ), + .inport_wdata( reg_bank__inport_wdata[0] ), + .reset( reg_bank__reset[0] ), + .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[0] ), + .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[0] ), + .send_data_to_fu__val( reg_bank__send_data_to_fu__val[0] ) + ); + + RegisterBankRTL__0a5bdf408d921386 reg_bank__1 + ( + .clk( reg_bank__clk[1] ), + .inport_opt( reg_bank__inport_opt[1] ), + .inport_valid( reg_bank__inport_valid[1] ), + .inport_wdata( reg_bank__inport_wdata[1] ), + .reset( reg_bank__reset[1] ), + .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[1] ), + .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[1] ), + .send_data_to_fu__val( reg_bank__send_data_to_fu__val[1] ) + ); + + RegisterBankRTL__ddae41891d80e575 reg_bank__2 + ( + .clk( reg_bank__clk[2] ), + .inport_opt( reg_bank__inport_opt[2] ), + .inport_valid( reg_bank__inport_valid[2] ), + .inport_wdata( reg_bank__inport_wdata[2] ), + .reset( reg_bank__reset[2] ), + .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[2] ), + .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[2] ), + .send_data_to_fu__val( reg_bank__send_data_to_fu__val[2] ) + ); + + RegisterBankRTL__ff0588d25abf2ed3 reg_bank__3 + ( + .clk( reg_bank__clk[3] ), + .inport_opt( reg_bank__inport_opt[3] ), + .inport_valid( reg_bank__inport_valid[3] ), + .inport_wdata( reg_bank__inport_wdata[3] ), + .reset( reg_bank__reset[3] ), + .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[3] ), + .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[3] ), + .send_data_to_fu__val( reg_bank__send_data_to_fu__val[3] ) + ); + + //------------------------------------------------------------- + // End of component reg_bank[0:3] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterClusterRTL.py:45 + // @update + // def update_msgs_signals(): + // # Initializes signals. + // for i in range(num_reg_banks): + // s.send_data_to_fu[i].msg @= DataType() + // s.recv_data_from_routing_crossbar[i].rdy @= 0 + // s.recv_data_from_fu_crossbar[i].rdy @= 0 + // s.recv_data_from_const[i].rdy @= 0 + // s.send_data_to_fu[i].val @= 0 + // + // for i in range(num_reg_banks): + // if s.recv_data_from_routing_crossbar[i].val: + // s.send_data_to_fu[i].msg @= \ + // s.recv_data_from_routing_crossbar[i].msg + // else: + // s.send_data_to_fu[i].msg @= \ + // s.reg_bank[i].send_data_to_fu.msg + // + // s.send_data_to_fu[i].val @= \ + // s.recv_data_from_routing_crossbar[i].val | \ + // s.reg_bank[i].send_data_to_fu.val + // s.reg_bank[i].send_data_to_fu.rdy @= s.send_data_to_fu[i].rdy + // + // s.recv_data_from_routing_crossbar[i].rdy @= s.send_data_to_fu[i].rdy + // s.recv_data_from_fu_crossbar[i].rdy @= 1 + // s.recv_data_from_const[i].rdy @= 1 + + always_comb begin : update_msgs_signals + for ( int unsigned i = 1'd0; i < 3'( __const__num_reg_banks_at_update_msgs_signals ); i += 1'd1 ) begin + send_data_to_fu__msg[2'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + recv_data_from_routing_crossbar__rdy[2'(i)] = 1'd0; + recv_data_from_fu_crossbar__rdy[2'(i)] = 1'd0; + recv_data_from_const__rdy[2'(i)] = 1'd0; + send_data_to_fu__val[2'(i)] = 1'd0; + end + for ( int unsigned i = 1'd0; i < 3'( __const__num_reg_banks_at_update_msgs_signals ); i += 1'd1 ) begin + if ( recv_data_from_routing_crossbar__val[2'(i)] ) begin + send_data_to_fu__msg[2'(i)] = recv_data_from_routing_crossbar__msg[2'(i)]; + end + else + send_data_to_fu__msg[2'(i)] = reg_bank__send_data_to_fu__msg[2'(i)]; + send_data_to_fu__val[2'(i)] = recv_data_from_routing_crossbar__val[2'(i)] | reg_bank__send_data_to_fu__val[2'(i)]; + reg_bank__send_data_to_fu__rdy[2'(i)] = send_data_to_fu__rdy[2'(i)]; + recv_data_from_routing_crossbar__rdy[2'(i)] = send_data_to_fu__rdy[2'(i)]; + recv_data_from_fu_crossbar__rdy[2'(i)] = 1'd1; + recv_data_from_const__rdy[2'(i)] = 1'd1; + end + end + + assign reg_bank__clk[0] = clk; + assign reg_bank__reset[0] = reset; + assign reg_bank__clk[1] = clk; + assign reg_bank__reset[1] = reset; + assign reg_bank__clk[2] = clk; + assign reg_bank__reset[2] = reset; + assign reg_bank__clk[3] = clk; + assign reg_bank__reset[3] = reset; + assign reg_bank__inport_opt[0] = inport_opt; + assign reg_bank__inport_wdata[0][0] = recv_data_from_routing_crossbar__msg[0]; + assign reg_bank__inport_wdata[0][1] = recv_data_from_fu_crossbar__msg[0]; + assign reg_bank__inport_wdata[0][2] = recv_data_from_const__msg[0]; + assign reg_bank__inport_valid[0][0] = recv_data_from_routing_crossbar__val[0]; + assign reg_bank__inport_valid[0][1] = recv_data_from_fu_crossbar__val[0]; + assign reg_bank__inport_valid[0][2] = recv_data_from_const__val[0]; + assign reg_bank__inport_opt[1] = inport_opt; + assign reg_bank__inport_wdata[1][0] = recv_data_from_routing_crossbar__msg[1]; + assign reg_bank__inport_wdata[1][1] = recv_data_from_fu_crossbar__msg[1]; + assign reg_bank__inport_wdata[1][2] = recv_data_from_const__msg[1]; + assign reg_bank__inport_valid[1][0] = recv_data_from_routing_crossbar__val[1]; + assign reg_bank__inport_valid[1][1] = recv_data_from_fu_crossbar__val[1]; + assign reg_bank__inport_valid[1][2] = recv_data_from_const__val[1]; + assign reg_bank__inport_opt[2] = inport_opt; + assign reg_bank__inport_wdata[2][0] = recv_data_from_routing_crossbar__msg[2]; + assign reg_bank__inport_wdata[2][1] = recv_data_from_fu_crossbar__msg[2]; + assign reg_bank__inport_wdata[2][2] = recv_data_from_const__msg[2]; + assign reg_bank__inport_valid[2][0] = recv_data_from_routing_crossbar__val[2]; + assign reg_bank__inport_valid[2][1] = recv_data_from_fu_crossbar__val[2]; + assign reg_bank__inport_valid[2][2] = recv_data_from_const__val[2]; + assign reg_bank__inport_opt[3] = inport_opt; + assign reg_bank__inport_wdata[3][0] = recv_data_from_routing_crossbar__msg[3]; + assign reg_bank__inport_wdata[3][1] = recv_data_from_fu_crossbar__msg[3]; + assign reg_bank__inport_wdata[3][2] = recv_data_from_const__msg[3]; + assign reg_bank__inport_valid[3][0] = recv_data_from_routing_crossbar__val[3]; + assign reg_bank__inport_valid[3][1] = recv_data_from_fu_crossbar__val[3]; + assign reg_bank__inport_valid[3][2] = recv_data_from_const__val[3]; + +endmodule + + +// PyMTL Component CrossbarRTL Definition +// Full name: CrossbarRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_8__num_cgras_4__num_tiles_16__ctrl_mem_size_16__outport_towards_local_base_id_4 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py + +module CrossbarRTL__cad4150dfdc32fbd +( + input logic [1:0] cgra_id , + input logic [0:0] clear , + input logic [0:0] clk , + input logic [0:0] compute_done , + input logic [0:0] crossbar_id , + input logic [2:0] crossbar_outport [0:7], + input logic [3:0] ctrl_addr_inport , + input logic [2:0] prologue_count_inport [0:15][0:3], + input logic [0:0] reset , + input logic [4:0] tile_id , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:3] , + output logic [0:0] recv_data__rdy [0:3] , + input logic [0:0] recv_data__val [0:3] , + input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , + output logic [0:0] recv_opt__rdy , + input logic [0:0] recv_opt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:7] , + input logic [0:0] send_data__rdy [0:7] , + output logic [0:0] send_data__val [0:7] +); + localparam logic [2:0] __const__num_inports_at_update_signal = 3'd4; + localparam logic [3:0] __const__num_outports_at_update_signal = 4'd8; + localparam logic [6:0] __const__OPT_START = 7'd0; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter = 5'd16; + localparam logic [2:0] __const__num_inports_at_update_prologue_counter = 3'd4; + localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter_next = 5'd16; + localparam logic [2:0] __const__num_inports_at_update_prologue_counter_next = 3'd4; + localparam logic [3:0] __const__num_outports_at_update_prologue_counter_next = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_prologue_allowing_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_prologue_or_valid_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_in_dir_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_rdy_vector = 4'd8; + localparam logic [2:0] __const__outport_towards_local_base_id_at_update_rdy_vector = 3'd4; + localparam logic [3:0] __const__num_outports_at_update_valid_vector = 4'd8; + localparam logic [2:0] __const__num_inports_at_update_recv_required_vector = 3'd4; + localparam logic [3:0] __const__num_outports_at_update_recv_required_vector = 4'd8; + localparam logic [3:0] __const__num_outports_at_update_send_required_vector = 4'd8; + logic [2:0] in_dir [0:7]; + logic [1:0] in_dir_local [0:7]; + logic [7:0] prologue_allowing_vector; + logic [2:0] prologue_count_wire [0:15][0:3]; + logic [2:0] prologue_counter [0:15][0:3]; + logic [2:0] prologue_counter_next [0:15][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_msg [0:3]; + logic [0:0] recv_data_val [0:3]; + logic [3:0] recv_required_vector; + logic [7:0] recv_valid_or_prologue_allowing_vector; + logic [7:0] recv_valid_vector; + logic [7:0] send_rdy_vector; + logic [7:0] send_required_vector; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:153 + // @update + // def update_in_dir_vector(): + // + // for i in range(num_outports): + // s.in_dir[i] @= 0 + // s.in_dir_local[i] @= 0 + // + // for i in range(num_outports): + // s.in_dir[i] @= s.crossbar_outport[i] + // if s.in_dir[i] > 0: + // s.in_dir_local[i] @= trunc(s.in_dir[i] - 1, NumInportType) + + always_comb begin : update_in_dir_vector + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin + in_dir[3'(i)] = 3'd0; + in_dir_local[3'(i)] = 2'd0; + end + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin + in_dir[3'(i)] = crossbar_outport[3'(i)]; + if ( in_dir[3'(i)] > 3'd0 ) begin + in_dir_local[3'(i)] = 2'(in_dir[3'(i)] - 3'd1); + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:134 + // @update + // def update_prologue_allowing_vector(): + // s.prologue_allowing_vector @= 0 + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // # Records whether the prologue steps have already been satisfied. + // s.prologue_allowing_vector[i] @= \ + // (s.prologue_counter[s.ctrl_addr_inport][s.in_dir_local[i]] < \ + // s.prologue_count_wire[s.ctrl_addr_inport][s.in_dir_local[i]]) + // else: + // s.prologue_allowing_vector[i] @= 1 + + always_comb begin : update_prologue_allowing_vector + prologue_allowing_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_allowing_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 3'd0 ) begin + prologue_allowing_vector[3'(i)] = prologue_counter[ctrl_addr_inport][in_dir_local[3'(i)]] < prologue_count_wire[ctrl_addr_inport][in_dir_local[3'(i)]]; + end + else + prologue_allowing_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:119 + // @update + // def update_prologue_counter_next(): + // # Nested-loop to update the prologue counter, to avoid dynamic indexing to + // # work-around Yosys issue: https://github.com/tancheng/VectorCGRA/issues/148 + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + // for j in range(num_outports): + // if s.recv_opt.rdy & \ + // (s.in_dir[j] > 0) & \ + // (s.in_dir_local[j] == i) & \ + // (addr == s.ctrl_addr_inport) & \ + // (s.prologue_counter[addr][i] < s.prologue_count_wire[addr][i]): + // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + 1 + + always_comb begin : update_prologue_counter_next + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter_next ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter_next ); i += 1'd1 ) begin + prologue_counter_next[4'(addr)][2'(i)] = prologue_counter[4'(addr)][2'(i)]; + for ( int unsigned j = 1'd0; j < 4'( __const__num_outports_at_update_prologue_counter_next ); j += 1'd1 ) + if ( ( ( ( recv_opt__rdy & ( in_dir[3'(j)] > 3'd0 ) ) & ( in_dir_local[3'(j)] == 2'(i) ) ) & ( 4'(addr) == ctrl_addr_inport ) ) & ( prologue_counter[4'(addr)][2'(i)] < prologue_count_wire[4'(addr)][2'(i)] ) ) begin + prologue_counter_next[4'(addr)][2'(i)] = prologue_counter[4'(addr)][2'(i)] + 3'd1; + end + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:146 + // @update + // def update_prologue_or_valid_vector(): + // s.recv_valid_or_prologue_allowing_vector @= 0 + // for i in range(num_outports): + // s.recv_valid_or_prologue_allowing_vector[i] @= \ + // s.recv_valid_vector[i] | s.prologue_allowing_vector[i] + + always_comb begin : update_prologue_or_valid_vector + recv_valid_or_prologue_allowing_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_or_valid_vector ); i += 1'd1 ) + recv_valid_or_prologue_allowing_vector[3'(i)] = recv_valid_vector[3'(i)] | prologue_allowing_vector[3'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:165 + // @update + // def update_rdy_vector(): + // s.send_rdy_vector @= 0 + // for i in range(num_outports): + // # The `num_inports` indicates the number of outports that go to other tiles. + // # Specifically, if the compute already done, we shouldn't care the ones + // # (i.e., i >= num_inports) go to the FU's inports. In other words, we skip + // # the rdy checking on the FU's inports (connecting from crossbar_outport) if + // # the compute is already completed. + // if (s.in_dir[i] > 0) & \ + // (~s.compute_done | (i < outport_towards_local_base_id)): + // s.send_rdy_vector[i] @= s.send_data[i].rdy + // else: + // s.send_rdy_vector[i] @= 1 + + always_comb begin : update_rdy_vector + send_rdy_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_rdy_vector ); i += 1'd1 ) + if ( ( in_dir[3'(i)] > 3'd0 ) & ( ( ~compute_done ) | ( 3'(i) < 3'( __const__outport_towards_local_base_id_at_update_rdy_vector ) ) ) ) begin + send_rdy_vector[3'(i)] = send_data__rdy[3'(i)]; + end + else + send_rdy_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:189 + // @update + // def update_recv_required_vector(): + // for i in range(num_inports): + // s.recv_required_vector[i] @= 0 + // + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.recv_required_vector[s.in_dir_local[i]] @= 1 + + always_comb begin : update_recv_required_vector + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_recv_required_vector ); i += 1'd1 ) + recv_required_vector[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_recv_required_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 3'd0 ) begin + recv_required_vector[in_dir_local[3'(i)]] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:198 + // @update + // def update_send_required_vector(): + // + // for i in range(num_outports): + // s.send_required_vector[i] @= 0 + // + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.send_required_vector[i] @= 1 + + always_comb begin : update_send_required_vector + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) + send_required_vector[3'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 3'd0 ) begin + send_required_vector[3'(i)] = 1'd1; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:82 + // @update + // def update_signal(): + // for i in range(num_inports): + // s.recv_data[i].rdy @= 0 + // for i in range(num_outports): + // s.send_data[i].val @= 0 + // s.send_data[i].msg @= DataType() + // s.recv_opt.rdy @= 0 + // + // if s.recv_opt.val & (s.recv_opt.msg.operation != OPT_START): + // for i in range(num_inports): + // s.recv_data[i].rdy @= reduce_and(s.recv_valid_vector) & \ + // reduce_and(s.send_rdy_vector) & \ + // s.recv_required_vector[i] + // + // for i in range(num_outports): + // s.send_data[i].val @= reduce_and(s.recv_valid_vector) & \ + // s.send_required_vector[i] + // if reduce_and(s.recv_valid_vector) & \ + // s.send_required_vector[i]: + // s.send_data[i].msg.payload @= s.recv_data_msg[s.in_dir_local[i]].payload + // s.send_data[i].msg.predicate @= s.recv_data_msg[s.in_dir_local[i]].predicate + // + // s.recv_opt.rdy @= reduce_and(s.send_rdy_vector) & \ + // reduce_and(s.recv_valid_or_prologue_allowing_vector) + + always_comb begin : update_signal + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) + recv_data__rdy[2'(i)] = 1'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin + send_data__val[3'(i)] = 1'd0; + send_data__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + end + recv_opt__rdy = 1'd0; + if ( recv_opt__val & ( recv_opt__msg.operation != 7'( __const__OPT_START ) ) ) begin + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) + recv_data__rdy[2'(i)] = ( ( & recv_valid_vector ) & ( & send_rdy_vector ) ) & recv_required_vector[2'(i)]; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin + send_data__val[3'(i)] = ( & recv_valid_vector ) & send_required_vector[3'(i)]; + if ( ( & recv_valid_vector ) & send_required_vector[3'(i)] ) begin + send_data__msg[3'(i)].payload = recv_data_msg[in_dir_local[3'(i)]].payload; + send_data__msg[3'(i)].predicate = recv_data_msg[in_dir_local[3'(i)]].predicate; + end + end + recv_opt__rdy = ( & send_rdy_vector ) & ( & recv_valid_or_prologue_allowing_vector ); + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:180 + // @update + // def update_valid_vector(): + // s.recv_valid_vector @= 0 + // for i in range(num_outports): + // if s.in_dir[i] > 0: + // s.recv_valid_vector[i] @= s.recv_data_val[s.in_dir_local[i]] + // else: + // s.recv_valid_vector[i] @= 1 + + always_comb begin : update_valid_vector + recv_valid_vector = 8'd0; + for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_valid_vector ); i += 1'd1 ) + if ( in_dir[3'(i)] > 3'd0 ) begin + recv_valid_vector[3'(i)] = recv_data_val[in_dir_local[3'(i)]]; + end + else + recv_valid_vector[3'(i)] = 1'd1; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:108 + // @update_ff + // def update_prologue_counter(): + // if s.reset | s.clear: + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter[addr][i] <<= 0 + // else: + // for addr in range(ctrl_mem_size): + // for i in range(num_inports): + // s.prologue_counter[addr][i] <<= s.prologue_counter_next[addr][i] + + always_ff @(posedge clk) begin : update_prologue_counter + if ( reset | clear ) begin + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) + prologue_counter[4'(addr)][2'(i)] <= 3'd0; + end + else + for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) + prologue_counter[4'(addr)][2'(i)] <= prologue_counter_next[4'(addr)][2'(i)]; + end + + assign recv_data_msg[0] = recv_data__msg[0]; + assign recv_data_val[0] = recv_data__val[0]; + assign recv_data_msg[1] = recv_data__msg[1]; + assign recv_data_val[1] = recv_data__val[1]; + assign recv_data_msg[2] = recv_data__msg[2]; + assign recv_data_val[2] = recv_data__val[2]; + assign recv_data_msg[3] = recv_data__msg[3]; + assign recv_data_val[3] = recv_data__val[3]; + assign prologue_count_wire[0][0] = prologue_count_inport[0][0]; + assign prologue_count_wire[0][1] = prologue_count_inport[0][1]; + assign prologue_count_wire[0][2] = prologue_count_inport[0][2]; + assign prologue_count_wire[0][3] = prologue_count_inport[0][3]; + assign prologue_count_wire[1][0] = prologue_count_inport[1][0]; + assign prologue_count_wire[1][1] = prologue_count_inport[1][1]; + assign prologue_count_wire[1][2] = prologue_count_inport[1][2]; + assign prologue_count_wire[1][3] = prologue_count_inport[1][3]; + assign prologue_count_wire[2][0] = prologue_count_inport[2][0]; + assign prologue_count_wire[2][1] = prologue_count_inport[2][1]; + assign prologue_count_wire[2][2] = prologue_count_inport[2][2]; + assign prologue_count_wire[2][3] = prologue_count_inport[2][3]; + assign prologue_count_wire[3][0] = prologue_count_inport[3][0]; + assign prologue_count_wire[3][1] = prologue_count_inport[3][1]; + assign prologue_count_wire[3][2] = prologue_count_inport[3][2]; + assign prologue_count_wire[3][3] = prologue_count_inport[3][3]; + assign prologue_count_wire[4][0] = prologue_count_inport[4][0]; + assign prologue_count_wire[4][1] = prologue_count_inport[4][1]; + assign prologue_count_wire[4][2] = prologue_count_inport[4][2]; + assign prologue_count_wire[4][3] = prologue_count_inport[4][3]; + assign prologue_count_wire[5][0] = prologue_count_inport[5][0]; + assign prologue_count_wire[5][1] = prologue_count_inport[5][1]; + assign prologue_count_wire[5][2] = prologue_count_inport[5][2]; + assign prologue_count_wire[5][3] = prologue_count_inport[5][3]; + assign prologue_count_wire[6][0] = prologue_count_inport[6][0]; + assign prologue_count_wire[6][1] = prologue_count_inport[6][1]; + assign prologue_count_wire[6][2] = prologue_count_inport[6][2]; + assign prologue_count_wire[6][3] = prologue_count_inport[6][3]; + assign prologue_count_wire[7][0] = prologue_count_inport[7][0]; + assign prologue_count_wire[7][1] = prologue_count_inport[7][1]; + assign prologue_count_wire[7][2] = prologue_count_inport[7][2]; + assign prologue_count_wire[7][3] = prologue_count_inport[7][3]; + assign prologue_count_wire[8][0] = prologue_count_inport[8][0]; + assign prologue_count_wire[8][1] = prologue_count_inport[8][1]; + assign prologue_count_wire[8][2] = prologue_count_inport[8][2]; + assign prologue_count_wire[8][3] = prologue_count_inport[8][3]; + assign prologue_count_wire[9][0] = prologue_count_inport[9][0]; + assign prologue_count_wire[9][1] = prologue_count_inport[9][1]; + assign prologue_count_wire[9][2] = prologue_count_inport[9][2]; + assign prologue_count_wire[9][3] = prologue_count_inport[9][3]; + assign prologue_count_wire[10][0] = prologue_count_inport[10][0]; + assign prologue_count_wire[10][1] = prologue_count_inport[10][1]; + assign prologue_count_wire[10][2] = prologue_count_inport[10][2]; + assign prologue_count_wire[10][3] = prologue_count_inport[10][3]; + assign prologue_count_wire[11][0] = prologue_count_inport[11][0]; + assign prologue_count_wire[11][1] = prologue_count_inport[11][1]; + assign prologue_count_wire[11][2] = prologue_count_inport[11][2]; + assign prologue_count_wire[11][3] = prologue_count_inport[11][3]; + assign prologue_count_wire[12][0] = prologue_count_inport[12][0]; + assign prologue_count_wire[12][1] = prologue_count_inport[12][1]; + assign prologue_count_wire[12][2] = prologue_count_inport[12][2]; + assign prologue_count_wire[12][3] = prologue_count_inport[12][3]; + assign prologue_count_wire[13][0] = prologue_count_inport[13][0]; + assign prologue_count_wire[13][1] = prologue_count_inport[13][1]; + assign prologue_count_wire[13][2] = prologue_count_inport[13][2]; + assign prologue_count_wire[13][3] = prologue_count_inport[13][3]; + assign prologue_count_wire[14][0] = prologue_count_inport[14][0]; + assign prologue_count_wire[14][1] = prologue_count_inport[14][1]; + assign prologue_count_wire[14][2] = prologue_count_inport[14][2]; + assign prologue_count_wire[14][3] = prologue_count_inport[14][3]; + assign prologue_count_wire[15][0] = prologue_count_inport[15][0]; + assign prologue_count_wire[15][1] = prologue_count_inport[15][1]; + assign prologue_count_wire[15][2] = prologue_count_inport[15][2]; + assign prologue_count_wire[15][3] = prologue_count_inport[15][3]; + +endmodule + + +// PyMTL Component RegisterFile Definition +// Full name: RegisterFile__Type_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__nregs_2__rd_ports_1__wr_ports_1__const_zero_False +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py + +module RegisterFile__684a25db9dbebdb9 +( + input logic [0:0] clk , + input logic [0:0] raddr [0:0], + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rdata [0:0], + input logic [0:0] reset , + input logic [0:0] waddr [0:0], + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 wdata [0:0], + input logic [0:0] wen [0:0] +); + localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; + localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 regs [0:1]; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 + // @update + // def up_rf_read(): + // for i in range( rd_ports ): + // s.rdata[i] @= s.regs[ s.raddr[i] ] + + always_comb begin : up_rf_read + for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) + rdata[1'(i)] = regs[raddr[1'(i)]]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 + // @update_ff + // def up_rf_write(): + // for i in range( wr_ports ): + // if s.wen[i]: + // s.regs[ s.waddr[i] ] <<= s.wdata[i] + + always_ff @(posedge clk) begin : up_rf_write + for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) + if ( wen[1'(i)] ) begin + regs[waddr[1'(i)]] <= wdata[1'(i)]; + end + end + +endmodule + + +// PyMTL Component NormalQueueDpathRTL Definition +// Full name: NormalQueueDpathRTL__EntryType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueDpathRTL__43c9394e24dc368f +( + input logic [0:0] clk , + input logic [0:0] raddr , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_msg , + input logic [0:0] reset , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_msg , + input logic [0:0] waddr , + input logic [0:0] wen +); + //------------------------------------------------------------- + // Component rf + //------------------------------------------------------------- + + logic [0:0] rf__clk; + logic [0:0] rf__raddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rf__rdata [0:0]; + logic [0:0] rf__reset; + logic [0:0] rf__waddr [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rf__wdata [0:0]; + logic [0:0] rf__wen [0:0]; + + RegisterFile__684a25db9dbebdb9 rf + ( + .clk( rf__clk ), + .raddr( rf__raddr ), + .rdata( rf__rdata ), + .reset( rf__reset ), + .waddr( rf__waddr ), + .wdata( rf__wdata ), + .wen( rf__wen ) + ); + + //------------------------------------------------------------- + // End of component rf + //------------------------------------------------------------- + + assign rf__clk = clk; + assign rf__reset = reset; + assign rf__raddr[0] = raddr; + assign send_msg = rf__rdata[0]; + assign rf__wen[0] = wen; + assign rf__waddr[0] = waddr; + assign rf__wdata[0] = recv_msg; + +endmodule + + +// PyMTL Component NormalQueueRTL Definition +// Full name: NormalQueueRTL__EntryType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__num_entries_2 +// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py + +module NormalQueueRTL__43c9394e24dc368f +( + input logic [0:0] clk , + output logic [1:0] count , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component ctrl + //------------------------------------------------------------- + + logic [0:0] ctrl__clk; + logic [1:0] ctrl__count; + logic [0:0] ctrl__raddr; + logic [0:0] ctrl__recv_rdy; + logic [0:0] ctrl__recv_val; + logic [0:0] ctrl__reset; + logic [0:0] ctrl__send_rdy; + logic [0:0] ctrl__send_val; + logic [0:0] ctrl__waddr; + logic [0:0] ctrl__wen; + + NormalQueueCtrlRTL__num_entries_2 ctrl + ( + .clk( ctrl__clk ), + .count( ctrl__count ), + .raddr( ctrl__raddr ), + .recv_rdy( ctrl__recv_rdy ), + .recv_val( ctrl__recv_val ), + .reset( ctrl__reset ), + .send_rdy( ctrl__send_rdy ), + .send_val( ctrl__send_val ), + .waddr( ctrl__waddr ), + .wen( ctrl__wen ) + ); + + //------------------------------------------------------------- + // End of component ctrl + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component dpath + //------------------------------------------------------------- + + logic [0:0] dpath__clk; + logic [0:0] dpath__raddr; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 dpath__recv_msg; + logic [0:0] dpath__reset; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 dpath__send_msg; + logic [0:0] dpath__waddr; + logic [0:0] dpath__wen; + + NormalQueueDpathRTL__43c9394e24dc368f dpath + ( + .clk( dpath__clk ), + .raddr( dpath__raddr ), + .recv_msg( dpath__recv_msg ), + .reset( dpath__reset ), + .send_msg( dpath__send_msg ), + .waddr( dpath__waddr ), + .wen( dpath__wen ) + ); + + //------------------------------------------------------------- + // End of component dpath + //------------------------------------------------------------- + + assign ctrl__clk = clk; + assign ctrl__reset = reset; + assign dpath__clk = clk; + assign dpath__reset = reset; + assign dpath__wen = ctrl__wen; + assign dpath__waddr = ctrl__waddr; + assign dpath__raddr = ctrl__raddr; + assign ctrl__recv_val = recv__val; + assign recv__rdy = ctrl__recv_rdy; + assign dpath__recv_msg = recv__msg; + assign send__val = ctrl__send_val; + assign ctrl__send_rdy = send__rdy; + assign send__msg = dpath__send_msg; + assign count = ctrl__count; + +endmodule + + +// PyMTL Component ChannelRTL Definition +// Full name: ChannelRTL__PacketType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__QueueType_NormalQueueRTL__latency_1 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py + +module ChannelRTL__694d252f21ac798b +( + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queues[0:0] + //------------------------------------------------------------- + + logic [0:0] queues__clk [0:0]; + logic [1:0] queues__count [0:0]; + logic [0:0] queues__reset [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 queues__recv__msg [0:0]; + logic [0:0] queues__recv__rdy [0:0]; + logic [0:0] queues__recv__val [0:0]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 queues__send__msg [0:0]; + logic [0:0] queues__send__rdy [0:0]; + logic [0:0] queues__send__val [0:0]; + + NormalQueueRTL__43c9394e24dc368f queues__0 + ( + .clk( queues__clk[0] ), + .count( queues__count[0] ), + .reset( queues__reset[0] ), + .recv__msg( queues__recv__msg[0] ), + .recv__rdy( queues__recv__rdy[0] ), + .recv__val( queues__recv__val[0] ), + .send__msg( queues__send__msg[0] ), + .send__rdy( queues__send__rdy[0] ), + .send__val( queues__send__val[0] ) + ); + + //------------------------------------------------------------- + // End of component queues[0:0] + //------------------------------------------------------------- + + assign queues__clk[0] = clk; + assign queues__reset[0] = reset; + assign queues__recv__msg[0] = recv__msg; + assign recv__rdy = queues__recv__rdy[0]; + assign queues__recv__val[0] = recv__val; + assign send__msg = queues__send__msg[0]; + assign queues__send__rdy[0] = send__rdy; + assign send__val = queues__send__val[0]; + +endmodule + + +// PyMTL Component LinkOrRTL Definition +// Full name: LinkOrRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/LinkOrRTL.py + +module LinkOrRTL__0fce34ff986f61fe +( + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_fu__msg , + output logic [0:0] recv_fu__rdy , + input logic [0:0] recv_fu__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_xbar__msg , + output logic [0:0] recv_xbar__rdy , + input logic [0:0] recv_xbar__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/LinkOrRTL.py:28 + // @update + // def process(): + // # Initializes the delivered message. + // s.send.msg @= DataType() + // + // # The messages from two sources (i.e., xbar and FU) won't be valid + // # simultaneously (confliction would be caused if they both are valid), + // # which is guaranteed by the compiler/software. + // s.send.msg.predicate @= s.recv_fu.msg.predicate | s.recv_xbar.msg.predicate + // s.send.msg.payload @= s.recv_xbar.msg.payload | s.recv_fu.msg.payload + // + // # FIXME: bypass won't be necessary any more with separate xbar design. + // # s.send.msg.bypass @= 0 + // # s.send.msg.delay @= s.recv_fu.msg.delay | s.recv_xbar.msg.delay + // + // # s.send.val @= s.send.rdy & (s.recv_fu.val | s.recv_xbar.val) + // s.send.val @= s.recv_fu.val | s.recv_xbar.val + // s.recv_fu.rdy @= s.send.rdy + // s.recv_xbar.rdy @= s.send.rdy + + always_comb begin : process + send__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + send__msg.predicate = recv_fu__msg.predicate | recv_xbar__msg.predicate; + send__msg.payload = recv_xbar__msg.payload | recv_fu__msg.payload; + send__val = recv_fu__val | recv_xbar__val; + recv_fu__rdy = send__rdy; + recv_xbar__rdy = send__rdy; + end + +endmodule + + +// PyMTL Component TileRTL Definition +// Full name: TileRTL__IntraCgraPktType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ctrl_mem_size_16__data_mem_size_128__num_ctrl_4__total_steps_38__num_fu_inports_4__num_fu_outports_2__num_tile_inports_4__num_tile_outports_4__num_cgras_4__num_tiles_16__num_registers_per_reg_bank_16__Fu_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ] +// At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py + +module TileRTL__78da5e3970e1cd1d +( + input logic [1:0] cgra_id , + input logic [0:0] clk , + input logic [0:0] reset , + input logic [4:0] tile_id , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , + output logic [0:0] from_mem_rdata__rdy , + input logic [0:0] from_mem_rdata__val , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:3] , + output logic [0:0] recv_data__rdy [0:3] , + input logic [0:0] recv_data__val [0:3] , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_controller_pkt__msg , + output logic [0:0] recv_from_controller_pkt__rdy , + input logic [0:0] recv_from_controller_pkt__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:3] , + input logic [0:0] send_data__rdy [0:3] , + output logic [0:0] send_data__val [0:3] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_controller_pkt__msg , + input logic [0:0] send_to_controller_pkt__rdy , + output logic [0:0] send_to_controller_pkt__val , + output logic [6:0] to_mem_raddr__msg , + input logic [0:0] to_mem_raddr__rdy , + output logic [0:0] to_mem_raddr__val , + output logic [6:0] to_mem_waddr__msg , + input logic [0:0] to_mem_waddr__rdy , + output logic [0:0] to_mem_waddr__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , + input logic [0:0] to_mem_wdata__rdy , + output logic [0:0] to_mem_wdata__val +); + localparam logic [1:0] __const__CMD_CONFIG = 2'd3; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; + localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; + localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; + localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; + localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; + localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; + localparam logic [3:0] __const__CMD_CONST = 4'd13; + logic [0:0] element_done; + logic [0:0] fu_crossbar_done; + logic [0:0] routing_crossbar_done; + //------------------------------------------------------------- + // Component const_mem + //------------------------------------------------------------- + + logic [0:0] const_mem__clear; + logic [0:0] const_mem__clk; + logic [0:0] const_mem__ctrl_proceed; + logic [0:0] const_mem__reset; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_mem__recv_const__msg; + logic [0:0] const_mem__recv_const__rdy; + logic [0:0] const_mem__recv_const__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_mem__send_const__msg; + logic [0:0] const_mem__send_const__rdy; + logic [0:0] const_mem__send_const__val; + + ConstQueueDynamicRTL__9d3397f72f19af52 const_mem + ( + .clear( const_mem__clear ), + .clk( const_mem__clk ), + .ctrl_proceed( const_mem__ctrl_proceed ), + .reset( const_mem__reset ), + .recv_const__msg( const_mem__recv_const__msg ), + .recv_const__rdy( const_mem__recv_const__rdy ), + .recv_const__val( const_mem__recv_const__val ), + .send_const__msg( const_mem__send_const__msg ), + .send_const__rdy( const_mem__send_const__rdy ), + .send_const__val( const_mem__send_const__val ) + ); + + //------------------------------------------------------------- + // End of component const_mem + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component ctrl_mem + //------------------------------------------------------------- + + logic [1:0] ctrl_mem__cgra_id; + logic [0:0] ctrl_mem__clk; + logic [3:0] ctrl_mem__ctrl_addr_outport; + logic [2:0] ctrl_mem__prologue_count_outport_fu; + logic [2:0] ctrl_mem__prologue_count_outport_fu_crossbar [0:15][0:1]; + logic [2:0] ctrl_mem__prologue_count_outport_routing_crossbar [0:15][0:3]; + logic [0:0] ctrl_mem__reset; + logic [4:0] ctrl_mem__tile_id; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a ctrl_mem__recv_from_element__msg; + logic [0:0] ctrl_mem__recv_from_element__rdy; + logic [0:0] ctrl_mem__recv_from_element__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_mem__recv_pkt_from_controller__msg; + logic [0:0] ctrl_mem__recv_pkt_from_controller__rdy; + logic [0:0] ctrl_mem__recv_pkt_from_controller__val; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 ctrl_mem__send_ctrl__msg; + logic [0:0] ctrl_mem__send_ctrl__rdy; + logic [0:0] ctrl_mem__send_ctrl__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_mem__send_pkt_to_controller__msg; + logic [0:0] ctrl_mem__send_pkt_to_controller__rdy; + logic [0:0] ctrl_mem__send_pkt_to_controller__val; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a ctrl_mem__send_to_element__msg; + logic [0:0] ctrl_mem__send_to_element__rdy; + logic [0:0] ctrl_mem__send_to_element__val; + + CtrlMemDynamicRTL__427d547b7d58aa8e ctrl_mem + ( + .cgra_id( ctrl_mem__cgra_id ), + .clk( ctrl_mem__clk ), + .ctrl_addr_outport( ctrl_mem__ctrl_addr_outport ), + .prologue_count_outport_fu( ctrl_mem__prologue_count_outport_fu ), + .prologue_count_outport_fu_crossbar( ctrl_mem__prologue_count_outport_fu_crossbar ), + .prologue_count_outport_routing_crossbar( ctrl_mem__prologue_count_outport_routing_crossbar ), + .reset( ctrl_mem__reset ), + .tile_id( ctrl_mem__tile_id ), + .recv_from_element__msg( ctrl_mem__recv_from_element__msg ), + .recv_from_element__rdy( ctrl_mem__recv_from_element__rdy ), + .recv_from_element__val( ctrl_mem__recv_from_element__val ), + .recv_pkt_from_controller__msg( ctrl_mem__recv_pkt_from_controller__msg ), + .recv_pkt_from_controller__rdy( ctrl_mem__recv_pkt_from_controller__rdy ), + .recv_pkt_from_controller__val( ctrl_mem__recv_pkt_from_controller__val ), + .send_ctrl__msg( ctrl_mem__send_ctrl__msg ), + .send_ctrl__rdy( ctrl_mem__send_ctrl__rdy ), + .send_ctrl__val( ctrl_mem__send_ctrl__val ), + .send_pkt_to_controller__msg( ctrl_mem__send_pkt_to_controller__msg ), + .send_pkt_to_controller__rdy( ctrl_mem__send_pkt_to_controller__rdy ), + .send_pkt_to_controller__val( ctrl_mem__send_pkt_to_controller__val ), + .send_to_element__msg( ctrl_mem__send_to_element__msg ), + .send_to_element__rdy( ctrl_mem__send_to_element__rdy ), + .send_to_element__val( ctrl_mem__send_to_element__val ) + ); + + //------------------------------------------------------------- + // End of component ctrl_mem + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component element + //------------------------------------------------------------- + + logic [0:0] element__clear [0:14]; + logic [0:0] element__clk; + logic [2:0] element__prologue_count_inport; + logic [0:0] element__reset; + logic [4:0] element__tile_id; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__from_mem_rdata__msg [0:14]; + logic [0:0] element__from_mem_rdata__rdy [0:14]; + logic [0:0] element__from_mem_rdata__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__recv_const__msg; + logic [0:0] element__recv_const__rdy; + logic [0:0] element__recv_const__val; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a element__recv_from_ctrl_mem__msg; + logic [0:0] element__recv_from_ctrl_mem__rdy; + logic [0:0] element__recv_from_ctrl_mem__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__recv_in__msg [0:3]; + logic [0:0] element__recv_in__rdy [0:3]; + logic [0:0] element__recv_in__val [0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 element__recv_opt__msg; + logic [0:0] element__recv_opt__rdy; + logic [0:0] element__recv_opt__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__send_out__msg [0:1]; + logic [0:0] element__send_out__rdy [0:1]; + logic [0:0] element__send_out__val [0:1]; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a element__send_to_ctrl_mem__msg; + logic [0:0] element__send_to_ctrl_mem__rdy; + logic [0:0] element__send_to_ctrl_mem__val; + logic [6:0] element__to_mem_raddr__msg [0:14]; + logic [0:0] element__to_mem_raddr__rdy [0:14]; + logic [0:0] element__to_mem_raddr__val [0:14]; + logic [6:0] element__to_mem_waddr__msg [0:14]; + logic [0:0] element__to_mem_waddr__rdy [0:14]; + logic [0:0] element__to_mem_waddr__val [0:14]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__to_mem_wdata__msg [0:14]; + logic [0:0] element__to_mem_wdata__rdy [0:14]; + logic [0:0] element__to_mem_wdata__val [0:14]; + + FlexibleFuRTL__07217382918d0fc2 element + ( + .clear( element__clear ), + .clk( element__clk ), + .prologue_count_inport( element__prologue_count_inport ), + .reset( element__reset ), + .tile_id( element__tile_id ), + .from_mem_rdata__msg( element__from_mem_rdata__msg ), + .from_mem_rdata__rdy( element__from_mem_rdata__rdy ), + .from_mem_rdata__val( element__from_mem_rdata__val ), + .recv_const__msg( element__recv_const__msg ), + .recv_const__rdy( element__recv_const__rdy ), + .recv_const__val( element__recv_const__val ), + .recv_from_ctrl_mem__msg( element__recv_from_ctrl_mem__msg ), + .recv_from_ctrl_mem__rdy( element__recv_from_ctrl_mem__rdy ), + .recv_from_ctrl_mem__val( element__recv_from_ctrl_mem__val ), + .recv_in__msg( element__recv_in__msg ), + .recv_in__rdy( element__recv_in__rdy ), + .recv_in__val( element__recv_in__val ), + .recv_opt__msg( element__recv_opt__msg ), + .recv_opt__rdy( element__recv_opt__rdy ), + .recv_opt__val( element__recv_opt__val ), + .send_out__msg( element__send_out__msg ), + .send_out__rdy( element__send_out__rdy ), + .send_out__val( element__send_out__val ), + .send_to_ctrl_mem__msg( element__send_to_ctrl_mem__msg ), + .send_to_ctrl_mem__rdy( element__send_to_ctrl_mem__rdy ), + .send_to_ctrl_mem__val( element__send_to_ctrl_mem__val ), + .to_mem_raddr__msg( element__to_mem_raddr__msg ), + .to_mem_raddr__rdy( element__to_mem_raddr__rdy ), + .to_mem_raddr__val( element__to_mem_raddr__val ), + .to_mem_waddr__msg( element__to_mem_waddr__msg ), + .to_mem_waddr__rdy( element__to_mem_waddr__rdy ), + .to_mem_waddr__val( element__to_mem_waddr__val ), + .to_mem_wdata__msg( element__to_mem_wdata__msg ), + .to_mem_wdata__rdy( element__to_mem_wdata__rdy ), + .to_mem_wdata__val( element__to_mem_wdata__val ) + ); + + //------------------------------------------------------------- + // End of component element + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component fu_crossbar + //------------------------------------------------------------- + + logic [1:0] fu_crossbar__cgra_id; + logic [0:0] fu_crossbar__clear; + logic [0:0] fu_crossbar__clk; + logic [0:0] fu_crossbar__compute_done; + logic [0:0] fu_crossbar__crossbar_id; + logic [1:0] fu_crossbar__crossbar_outport [0:7]; + logic [3:0] fu_crossbar__ctrl_addr_inport; + logic [2:0] fu_crossbar__prologue_count_inport [0:15][0:1]; + logic [0:0] fu_crossbar__reset; + logic [4:0] fu_crossbar__tile_id; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu_crossbar__recv_data__msg [0:1]; + logic [0:0] fu_crossbar__recv_data__rdy [0:1]; + logic [0:0] fu_crossbar__recv_data__val [0:1]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 fu_crossbar__recv_opt__msg; + logic [0:0] fu_crossbar__recv_opt__rdy; + logic [0:0] fu_crossbar__recv_opt__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu_crossbar__send_data__msg [0:7]; + logic [0:0] fu_crossbar__send_data__rdy [0:7]; + logic [0:0] fu_crossbar__send_data__val [0:7]; + + CrossbarRTL__45ee026205c61975 fu_crossbar + ( + .cgra_id( fu_crossbar__cgra_id ), + .clear( fu_crossbar__clear ), + .clk( fu_crossbar__clk ), + .compute_done( fu_crossbar__compute_done ), + .crossbar_id( fu_crossbar__crossbar_id ), + .crossbar_outport( fu_crossbar__crossbar_outport ), + .ctrl_addr_inport( fu_crossbar__ctrl_addr_inport ), + .prologue_count_inport( fu_crossbar__prologue_count_inport ), + .reset( fu_crossbar__reset ), + .tile_id( fu_crossbar__tile_id ), + .recv_data__msg( fu_crossbar__recv_data__msg ), + .recv_data__rdy( fu_crossbar__recv_data__rdy ), + .recv_data__val( fu_crossbar__recv_data__val ), + .recv_opt__msg( fu_crossbar__recv_opt__msg ), + .recv_opt__rdy( fu_crossbar__recv_opt__rdy ), + .recv_opt__val( fu_crossbar__recv_opt__val ), + .send_data__msg( fu_crossbar__send_data__msg ), + .send_data__rdy( fu_crossbar__send_data__rdy ), + .send_data__val( fu_crossbar__send_data__val ) + ); + + //------------------------------------------------------------- + // End of component fu_crossbar + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component register_cluster + //------------------------------------------------------------- + + logic [0:0] register_cluster__clk; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 register_cluster__inport_opt; + logic [0:0] register_cluster__reset; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_const__msg [0:3]; + logic [0:0] register_cluster__recv_data_from_const__rdy [0:3]; + logic [0:0] register_cluster__recv_data_from_const__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_fu_crossbar__msg [0:3]; + logic [0:0] register_cluster__recv_data_from_fu_crossbar__rdy [0:3]; + logic [0:0] register_cluster__recv_data_from_fu_crossbar__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_routing_crossbar__msg [0:3]; + logic [0:0] register_cluster__recv_data_from_routing_crossbar__rdy [0:3]; + logic [0:0] register_cluster__recv_data_from_routing_crossbar__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__send_data_to_fu__msg [0:3]; + logic [0:0] register_cluster__send_data_to_fu__rdy [0:3]; + logic [0:0] register_cluster__send_data_to_fu__val [0:3]; + + RegisterClusterRTL__7f2febb613462546 register_cluster + ( + .clk( register_cluster__clk ), + .inport_opt( register_cluster__inport_opt ), + .reset( register_cluster__reset ), + .recv_data_from_const__msg( register_cluster__recv_data_from_const__msg ), + .recv_data_from_const__rdy( register_cluster__recv_data_from_const__rdy ), + .recv_data_from_const__val( register_cluster__recv_data_from_const__val ), + .recv_data_from_fu_crossbar__msg( register_cluster__recv_data_from_fu_crossbar__msg ), + .recv_data_from_fu_crossbar__rdy( register_cluster__recv_data_from_fu_crossbar__rdy ), + .recv_data_from_fu_crossbar__val( register_cluster__recv_data_from_fu_crossbar__val ), + .recv_data_from_routing_crossbar__msg( register_cluster__recv_data_from_routing_crossbar__msg ), + .recv_data_from_routing_crossbar__rdy( register_cluster__recv_data_from_routing_crossbar__rdy ), + .recv_data_from_routing_crossbar__val( register_cluster__recv_data_from_routing_crossbar__val ), + .send_data_to_fu__msg( register_cluster__send_data_to_fu__msg ), + .send_data_to_fu__rdy( register_cluster__send_data_to_fu__rdy ), + .send_data_to_fu__val( register_cluster__send_data_to_fu__val ) + ); + + //------------------------------------------------------------- + // End of component register_cluster + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component routing_crossbar + //------------------------------------------------------------- + + logic [1:0] routing_crossbar__cgra_id; + logic [0:0] routing_crossbar__clear; + logic [0:0] routing_crossbar__clk; + logic [0:0] routing_crossbar__compute_done; + logic [0:0] routing_crossbar__crossbar_id; + logic [2:0] routing_crossbar__crossbar_outport [0:7]; + logic [3:0] routing_crossbar__ctrl_addr_inport; + logic [2:0] routing_crossbar__prologue_count_inport [0:15][0:3]; + logic [0:0] routing_crossbar__reset; + logic [4:0] routing_crossbar__tile_id; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 routing_crossbar__recv_data__msg [0:3]; + logic [0:0] routing_crossbar__recv_data__rdy [0:3]; + logic [0:0] routing_crossbar__recv_data__val [0:3]; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 routing_crossbar__recv_opt__msg; + logic [0:0] routing_crossbar__recv_opt__rdy; + logic [0:0] routing_crossbar__recv_opt__val; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 routing_crossbar__send_data__msg [0:7]; + logic [0:0] routing_crossbar__send_data__rdy [0:7]; + logic [0:0] routing_crossbar__send_data__val [0:7]; + + CrossbarRTL__cad4150dfdc32fbd routing_crossbar + ( + .cgra_id( routing_crossbar__cgra_id ), + .clear( routing_crossbar__clear ), + .clk( routing_crossbar__clk ), + .compute_done( routing_crossbar__compute_done ), + .crossbar_id( routing_crossbar__crossbar_id ), + .crossbar_outport( routing_crossbar__crossbar_outport ), + .ctrl_addr_inport( routing_crossbar__ctrl_addr_inport ), + .prologue_count_inport( routing_crossbar__prologue_count_inport ), + .reset( routing_crossbar__reset ), + .tile_id( routing_crossbar__tile_id ), + .recv_data__msg( routing_crossbar__recv_data__msg ), + .recv_data__rdy( routing_crossbar__recv_data__rdy ), + .recv_data__val( routing_crossbar__recv_data__val ), + .recv_opt__msg( routing_crossbar__recv_opt__msg ), + .recv_opt__rdy( routing_crossbar__recv_opt__rdy ), + .recv_opt__val( routing_crossbar__recv_opt__val ), + .send_data__msg( routing_crossbar__send_data__msg ), + .send_data__rdy( routing_crossbar__send_data__rdy ), + .send_data__val( routing_crossbar__send_data__val ) + ); + + //------------------------------------------------------------- + // End of component routing_crossbar + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component tile_in_channel[0:3] + //------------------------------------------------------------- + + logic [0:0] tile_in_channel__clk [0:3]; + logic [0:0] tile_in_channel__reset [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_in_channel__recv__msg [0:3]; + logic [0:0] tile_in_channel__recv__rdy [0:3]; + logic [0:0] tile_in_channel__recv__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_in_channel__send__msg [0:3]; + logic [0:0] tile_in_channel__send__rdy [0:3]; + logic [0:0] tile_in_channel__send__val [0:3]; + + ChannelRTL__694d252f21ac798b tile_in_channel__0 + ( + .clk( tile_in_channel__clk[0] ), + .reset( tile_in_channel__reset[0] ), + .recv__msg( tile_in_channel__recv__msg[0] ), + .recv__rdy( tile_in_channel__recv__rdy[0] ), + .recv__val( tile_in_channel__recv__val[0] ), + .send__msg( tile_in_channel__send__msg[0] ), + .send__rdy( tile_in_channel__send__rdy[0] ), + .send__val( tile_in_channel__send__val[0] ) + ); + + ChannelRTL__694d252f21ac798b tile_in_channel__1 + ( + .clk( tile_in_channel__clk[1] ), + .reset( tile_in_channel__reset[1] ), + .recv__msg( tile_in_channel__recv__msg[1] ), + .recv__rdy( tile_in_channel__recv__rdy[1] ), + .recv__val( tile_in_channel__recv__val[1] ), + .send__msg( tile_in_channel__send__msg[1] ), + .send__rdy( tile_in_channel__send__rdy[1] ), + .send__val( tile_in_channel__send__val[1] ) + ); + + ChannelRTL__694d252f21ac798b tile_in_channel__2 + ( + .clk( tile_in_channel__clk[2] ), + .reset( tile_in_channel__reset[2] ), + .recv__msg( tile_in_channel__recv__msg[2] ), + .recv__rdy( tile_in_channel__recv__rdy[2] ), + .recv__val( tile_in_channel__recv__val[2] ), + .send__msg( tile_in_channel__send__msg[2] ), + .send__rdy( tile_in_channel__send__rdy[2] ), + .send__val( tile_in_channel__send__val[2] ) + ); + + ChannelRTL__694d252f21ac798b tile_in_channel__3 + ( + .clk( tile_in_channel__clk[3] ), + .reset( tile_in_channel__reset[3] ), + .recv__msg( tile_in_channel__recv__msg[3] ), + .recv__rdy( tile_in_channel__recv__rdy[3] ), + .recv__val( tile_in_channel__recv__val[3] ), + .send__msg( tile_in_channel__send__msg[3] ), + .send__rdy( tile_in_channel__send__rdy[3] ), + .send__val( tile_in_channel__send__val[3] ) + ); + + //------------------------------------------------------------- + // End of component tile_in_channel[0:3] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component tile_out_or_link[0:3] + //------------------------------------------------------------- + + logic [0:0] tile_out_or_link__clk [0:3]; + logic [0:0] tile_out_or_link__reset [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__recv_fu__msg [0:3]; + logic [0:0] tile_out_or_link__recv_fu__rdy [0:3]; + logic [0:0] tile_out_or_link__recv_fu__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__recv_xbar__msg [0:3]; + logic [0:0] tile_out_or_link__recv_xbar__rdy [0:3]; + logic [0:0] tile_out_or_link__recv_xbar__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__send__msg [0:3]; + logic [0:0] tile_out_or_link__send__rdy [0:3]; + logic [0:0] tile_out_or_link__send__val [0:3]; + + LinkOrRTL__0fce34ff986f61fe tile_out_or_link__0 + ( + .clk( tile_out_or_link__clk[0] ), + .reset( tile_out_or_link__reset[0] ), + .recv_fu__msg( tile_out_or_link__recv_fu__msg[0] ), + .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[0] ), + .recv_fu__val( tile_out_or_link__recv_fu__val[0] ), + .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[0] ), + .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[0] ), + .recv_xbar__val( tile_out_or_link__recv_xbar__val[0] ), + .send__msg( tile_out_or_link__send__msg[0] ), + .send__rdy( tile_out_or_link__send__rdy[0] ), + .send__val( tile_out_or_link__send__val[0] ) + ); + + LinkOrRTL__0fce34ff986f61fe tile_out_or_link__1 + ( + .clk( tile_out_or_link__clk[1] ), + .reset( tile_out_or_link__reset[1] ), + .recv_fu__msg( tile_out_or_link__recv_fu__msg[1] ), + .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[1] ), + .recv_fu__val( tile_out_or_link__recv_fu__val[1] ), + .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[1] ), + .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[1] ), + .recv_xbar__val( tile_out_or_link__recv_xbar__val[1] ), + .send__msg( tile_out_or_link__send__msg[1] ), + .send__rdy( tile_out_or_link__send__rdy[1] ), + .send__val( tile_out_or_link__send__val[1] ) + ); + + LinkOrRTL__0fce34ff986f61fe tile_out_or_link__2 + ( + .clk( tile_out_or_link__clk[2] ), + .reset( tile_out_or_link__reset[2] ), + .recv_fu__msg( tile_out_or_link__recv_fu__msg[2] ), + .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[2] ), + .recv_fu__val( tile_out_or_link__recv_fu__val[2] ), + .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[2] ), + .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[2] ), + .recv_xbar__val( tile_out_or_link__recv_xbar__val[2] ), + .send__msg( tile_out_or_link__send__msg[2] ), + .send__rdy( tile_out_or_link__send__rdy[2] ), + .send__val( tile_out_or_link__send__val[2] ) + ); + + LinkOrRTL__0fce34ff986f61fe tile_out_or_link__3 + ( + .clk( tile_out_or_link__clk[3] ), + .reset( tile_out_or_link__reset[3] ), + .recv_fu__msg( tile_out_or_link__recv_fu__msg[3] ), + .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[3] ), + .recv_fu__val( tile_out_or_link__recv_fu__val[3] ), + .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[3] ), + .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[3] ), + .recv_xbar__val( tile_out_or_link__recv_xbar__val[3] ), + .send__msg( tile_out_or_link__send__msg[3] ), + .send__rdy( tile_out_or_link__send__rdy[3] ), + .send__val( tile_out_or_link__send__val[3] ) + ); + + //------------------------------------------------------------- + // End of component tile_out_or_link[0:3] + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:236 + // @update + // def feed_pkt(): + // s.ctrl_mem.recv_pkt_from_controller.msg @= CtrlPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) # , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // s.const_mem.recv_const.msg @= DataType(0, 0, 0, 0) + // s.ctrl_mem.recv_pkt_from_controller.val @= 0 + // s.const_mem.recv_const.val @= 0 + // s.recv_from_controller_pkt.rdy @= 0 + // + // if s.recv_from_controller_pkt.val & \ + // ((s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE) | \ + // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_LAUNCH)): + // s.ctrl_mem.recv_pkt_from_controller.val @= 1 + // s.ctrl_mem.recv_pkt_from_controller.msg @= s.recv_from_controller_pkt.msg + // s.recv_from_controller_pkt.rdy @= s.ctrl_mem.recv_pkt_from_controller.rdy + // elif s.recv_from_controller_pkt.val & (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONST): + // s.const_mem.recv_const.val @= 1 + // s.const_mem.recv_const.msg @= s.recv_from_controller_pkt.msg.payload.data + // s.recv_from_controller_pkt.rdy @= s.const_mem.recv_const.rdy + + always_comb begin : feed_pkt + ctrl_mem__recv_pkt_from_controller__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; + const_mem__recv_const__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; + ctrl_mem__recv_pkt_from_controller__val = 1'd0; + const_mem__recv_const__val = 1'd0; + recv_from_controller_pkt__rdy = 1'd0; + if ( recv_from_controller_pkt__val & ( ( ( ( ( ( ( ( ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) ) begin + ctrl_mem__recv_pkt_from_controller__val = 1'd1; + ctrl_mem__recv_pkt_from_controller__msg = recv_from_controller_pkt__msg; + recv_from_controller_pkt__rdy = ctrl_mem__recv_pkt_from_controller__rdy; + end + else if ( recv_from_controller_pkt__val & ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONST ) ) ) begin + const_mem__recv_const__val = 1'd1; + const_mem__recv_const__msg = recv_from_controller_pkt__msg.payload.data; + recv_from_controller_pkt__rdy = const_mem__recv_const__rdy; + end + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:292 + // @update + // def notify_const_mem(): + // s.const_mem.ctrl_proceed @= s.ctrl_mem.send_ctrl.rdy & s.ctrl_mem.send_ctrl.val + + always_comb begin : notify_const_mem + const_mem__ctrl_proceed = ctrl_mem__send_ctrl__rdy & ctrl_mem__send_ctrl__val; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:311 + // @update + // def notify_crossbars_compute_status(): + // s.routing_crossbar.compute_done @= s.element_done + // s.fu_crossbar.compute_done @= s.element_done + + always_comb begin : notify_crossbars_compute_status + routing_crossbar__compute_done = element_done; + fu_crossbar__compute_done = element_done; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:272 + // @update + // def update_opt(): + // s.element.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg + // s.routing_crossbar.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg + // s.fu_crossbar.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg + // + // # FIXME: Do we still need separate element and routing_xbar? + // # FIXME: Do we need to consider reg bank here? + // s.element.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.element_done + // s.routing_crossbar.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.routing_crossbar_done + // s.fu_crossbar.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.fu_crossbar_done + // + // # FIXME: yo96, rename ctrl.rdy to ctrl.proceed or sth similar. + // # Allows either the FU-related go out first or routing-xbar go out first. And only + // # allows the ctrl signal proceed till all the sub-modules done their own job (once). + // s.ctrl_mem.send_ctrl.rdy @= (s.element.recv_opt.rdy | s.element_done) & \ + // (s.routing_crossbar.recv_opt.rdy | s.routing_crossbar_done) & \ + // (s.fu_crossbar.recv_opt.rdy | s.fu_crossbar_done) + + always_comb begin : update_opt + element__recv_opt__msg = ctrl_mem__send_ctrl__msg; + routing_crossbar__recv_opt__msg = ctrl_mem__send_ctrl__msg; + fu_crossbar__recv_opt__msg = ctrl_mem__send_ctrl__msg; + element__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~element_done ); + routing_crossbar__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~routing_crossbar_done ); + fu_crossbar__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~fu_crossbar_done ); + ctrl_mem__send_ctrl__rdy = ( ( element__recv_opt__rdy | element_done ) & ( routing_crossbar__recv_opt__rdy | routing_crossbar_done ) ) & ( fu_crossbar__recv_opt__rdy | fu_crossbar_done ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:262 + // @update + // def update_send_out_signal(): + // s.send_to_controller_pkt.val @= 0 + // s.send_to_controller_pkt.msg @= CtrlPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) # , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + // if s.ctrl_mem.send_pkt_to_controller.val: + // s.send_to_controller_pkt.val @= 1 + // s.send_to_controller_pkt.msg @= s.ctrl_mem.send_pkt_to_controller.msg + // s.ctrl_mem.send_pkt_to_controller.rdy @= s.send_to_controller_pkt.rdy + + always_comb begin : update_send_out_signal + send_to_controller_pkt__val = 1'd0; + send_to_controller_pkt__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; + if ( ctrl_mem__send_pkt_to_controller__val ) begin + send_to_controller_pkt__val = 1'd1; + send_to_controller_pkt__msg = ctrl_mem__send_pkt_to_controller__msg; + end + ctrl_mem__send_pkt_to_controller__rdy = send_to_controller_pkt__rdy; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:297 + // @update_ff + // def already_done(): + // if s.reset | s.ctrl_mem.send_ctrl.rdy: + // s.element_done <<= 0 + // s.fu_crossbar_done <<= 0 + // s.routing_crossbar_done <<= 0 + // else: + // if s.element.recv_opt.rdy: + // s.element_done <<= 1 + // if s.fu_crossbar.recv_opt.rdy: + // s.fu_crossbar_done <<= 1 + // if s.routing_crossbar.recv_opt.rdy: + // s.routing_crossbar_done <<= 1 + + always_ff @(posedge clk) begin : already_done + if ( reset | ctrl_mem__send_ctrl__rdy ) begin + element_done <= 1'd0; + fu_crossbar_done <= 1'd0; + routing_crossbar_done <= 1'd0; + end + else begin + if ( element__recv_opt__rdy ) begin + element_done <= 1'd1; + end + if ( fu_crossbar__recv_opt__rdy ) begin + fu_crossbar_done <= 1'd1; + end + if ( routing_crossbar__recv_opt__rdy ) begin + routing_crossbar_done <= 1'd1; + end + end + end + + assign element__clk = clk; + assign element__reset = reset; + assign const_mem__clk = clk; + assign const_mem__reset = reset; + assign routing_crossbar__clk = clk; + assign routing_crossbar__reset = reset; + assign fu_crossbar__clk = clk; + assign fu_crossbar__reset = reset; + assign register_cluster__clk = clk; + assign register_cluster__reset = reset; + assign ctrl_mem__clk = clk; + assign ctrl_mem__reset = reset; + assign tile_in_channel__clk[0] = clk; + assign tile_in_channel__reset[0] = reset; + assign tile_in_channel__clk[1] = clk; + assign tile_in_channel__reset[1] = reset; + assign tile_in_channel__clk[2] = clk; + assign tile_in_channel__reset[2] = reset; + assign tile_in_channel__clk[3] = clk; + assign tile_in_channel__reset[3] = reset; + assign tile_out_or_link__clk[0] = clk; + assign tile_out_or_link__reset[0] = reset; + assign tile_out_or_link__clk[1] = clk; + assign tile_out_or_link__reset[1] = reset; + assign tile_out_or_link__clk[2] = clk; + assign tile_out_or_link__reset[2] = reset; + assign tile_out_or_link__clk[3] = clk; + assign tile_out_or_link__reset[3] = reset; + assign element__tile_id = tile_id; + assign ctrl_mem__cgra_id = cgra_id; + assign ctrl_mem__tile_id = tile_id; + assign fu_crossbar__cgra_id = cgra_id; + assign fu_crossbar__tile_id = tile_id; + assign routing_crossbar__cgra_id = cgra_id; + assign routing_crossbar__tile_id = tile_id; + assign routing_crossbar__crossbar_id = 1'd0; + assign fu_crossbar__crossbar_id = 1'd1; + assign element__recv_const__msg = const_mem__send_const__msg; + assign const_mem__send_const__rdy = element__recv_const__rdy; + assign element__recv_const__val = const_mem__send_const__val; + assign ctrl_mem__recv_from_element__msg = element__send_to_ctrl_mem__msg; + assign element__send_to_ctrl_mem__rdy = ctrl_mem__recv_from_element__rdy; + assign ctrl_mem__recv_from_element__val = element__send_to_ctrl_mem__val; + assign element__recv_from_ctrl_mem__msg = ctrl_mem__send_to_element__msg; + assign ctrl_mem__send_to_element__rdy = element__recv_from_ctrl_mem__rdy; + assign element__recv_from_ctrl_mem__val = ctrl_mem__send_to_element__val; + assign routing_crossbar__ctrl_addr_inport = ctrl_mem__ctrl_addr_outport; + assign fu_crossbar__ctrl_addr_inport = ctrl_mem__ctrl_addr_outport; + assign element__prologue_count_inport = ctrl_mem__prologue_count_outport_fu; + assign routing_crossbar__prologue_count_inport[0][0] = ctrl_mem__prologue_count_outport_routing_crossbar[0][0]; + assign routing_crossbar__prologue_count_inport[0][1] = ctrl_mem__prologue_count_outport_routing_crossbar[0][1]; + assign routing_crossbar__prologue_count_inport[0][2] = ctrl_mem__prologue_count_outport_routing_crossbar[0][2]; + assign routing_crossbar__prologue_count_inport[0][3] = ctrl_mem__prologue_count_outport_routing_crossbar[0][3]; + assign fu_crossbar__prologue_count_inport[0][0] = ctrl_mem__prologue_count_outport_fu_crossbar[0][0]; + assign fu_crossbar__prologue_count_inport[0][1] = ctrl_mem__prologue_count_outport_fu_crossbar[0][1]; + assign routing_crossbar__prologue_count_inport[1][0] = ctrl_mem__prologue_count_outport_routing_crossbar[1][0]; + assign routing_crossbar__prologue_count_inport[1][1] = ctrl_mem__prologue_count_outport_routing_crossbar[1][1]; + assign routing_crossbar__prologue_count_inport[1][2] = ctrl_mem__prologue_count_outport_routing_crossbar[1][2]; + assign routing_crossbar__prologue_count_inport[1][3] = ctrl_mem__prologue_count_outport_routing_crossbar[1][3]; + assign fu_crossbar__prologue_count_inport[1][0] = ctrl_mem__prologue_count_outport_fu_crossbar[1][0]; + assign fu_crossbar__prologue_count_inport[1][1] = ctrl_mem__prologue_count_outport_fu_crossbar[1][1]; + assign routing_crossbar__prologue_count_inport[2][0] = ctrl_mem__prologue_count_outport_routing_crossbar[2][0]; + assign routing_crossbar__prologue_count_inport[2][1] = ctrl_mem__prologue_count_outport_routing_crossbar[2][1]; + assign routing_crossbar__prologue_count_inport[2][2] = ctrl_mem__prologue_count_outport_routing_crossbar[2][2]; + assign routing_crossbar__prologue_count_inport[2][3] = ctrl_mem__prologue_count_outport_routing_crossbar[2][3]; + assign fu_crossbar__prologue_count_inport[2][0] = ctrl_mem__prologue_count_outport_fu_crossbar[2][0]; + assign fu_crossbar__prologue_count_inport[2][1] = ctrl_mem__prologue_count_outport_fu_crossbar[2][1]; + assign routing_crossbar__prologue_count_inport[3][0] = ctrl_mem__prologue_count_outport_routing_crossbar[3][0]; + assign routing_crossbar__prologue_count_inport[3][1] = ctrl_mem__prologue_count_outport_routing_crossbar[3][1]; + assign routing_crossbar__prologue_count_inport[3][2] = ctrl_mem__prologue_count_outport_routing_crossbar[3][2]; + assign routing_crossbar__prologue_count_inport[3][3] = ctrl_mem__prologue_count_outport_routing_crossbar[3][3]; + assign fu_crossbar__prologue_count_inport[3][0] = ctrl_mem__prologue_count_outport_fu_crossbar[3][0]; + assign fu_crossbar__prologue_count_inport[3][1] = ctrl_mem__prologue_count_outport_fu_crossbar[3][1]; + assign routing_crossbar__prologue_count_inport[4][0] = ctrl_mem__prologue_count_outport_routing_crossbar[4][0]; + assign routing_crossbar__prologue_count_inport[4][1] = ctrl_mem__prologue_count_outport_routing_crossbar[4][1]; + assign routing_crossbar__prologue_count_inport[4][2] = ctrl_mem__prologue_count_outport_routing_crossbar[4][2]; + assign routing_crossbar__prologue_count_inport[4][3] = ctrl_mem__prologue_count_outport_routing_crossbar[4][3]; + assign fu_crossbar__prologue_count_inport[4][0] = ctrl_mem__prologue_count_outport_fu_crossbar[4][0]; + assign fu_crossbar__prologue_count_inport[4][1] = ctrl_mem__prologue_count_outport_fu_crossbar[4][1]; + assign routing_crossbar__prologue_count_inport[5][0] = ctrl_mem__prologue_count_outport_routing_crossbar[5][0]; + assign routing_crossbar__prologue_count_inport[5][1] = ctrl_mem__prologue_count_outport_routing_crossbar[5][1]; + assign routing_crossbar__prologue_count_inport[5][2] = ctrl_mem__prologue_count_outport_routing_crossbar[5][2]; + assign routing_crossbar__prologue_count_inport[5][3] = ctrl_mem__prologue_count_outport_routing_crossbar[5][3]; + assign fu_crossbar__prologue_count_inport[5][0] = ctrl_mem__prologue_count_outport_fu_crossbar[5][0]; + assign fu_crossbar__prologue_count_inport[5][1] = ctrl_mem__prologue_count_outport_fu_crossbar[5][1]; + assign routing_crossbar__prologue_count_inport[6][0] = ctrl_mem__prologue_count_outport_routing_crossbar[6][0]; + assign routing_crossbar__prologue_count_inport[6][1] = ctrl_mem__prologue_count_outport_routing_crossbar[6][1]; + assign routing_crossbar__prologue_count_inport[6][2] = ctrl_mem__prologue_count_outport_routing_crossbar[6][2]; + assign routing_crossbar__prologue_count_inport[6][3] = ctrl_mem__prologue_count_outport_routing_crossbar[6][3]; + assign fu_crossbar__prologue_count_inport[6][0] = ctrl_mem__prologue_count_outport_fu_crossbar[6][0]; + assign fu_crossbar__prologue_count_inport[6][1] = ctrl_mem__prologue_count_outport_fu_crossbar[6][1]; + assign routing_crossbar__prologue_count_inport[7][0] = ctrl_mem__prologue_count_outport_routing_crossbar[7][0]; + assign routing_crossbar__prologue_count_inport[7][1] = ctrl_mem__prologue_count_outport_routing_crossbar[7][1]; + assign routing_crossbar__prologue_count_inport[7][2] = ctrl_mem__prologue_count_outport_routing_crossbar[7][2]; + assign routing_crossbar__prologue_count_inport[7][3] = ctrl_mem__prologue_count_outport_routing_crossbar[7][3]; + assign fu_crossbar__prologue_count_inport[7][0] = ctrl_mem__prologue_count_outport_fu_crossbar[7][0]; + assign fu_crossbar__prologue_count_inport[7][1] = ctrl_mem__prologue_count_outport_fu_crossbar[7][1]; + assign routing_crossbar__prologue_count_inport[8][0] = ctrl_mem__prologue_count_outport_routing_crossbar[8][0]; + assign routing_crossbar__prologue_count_inport[8][1] = ctrl_mem__prologue_count_outport_routing_crossbar[8][1]; + assign routing_crossbar__prologue_count_inport[8][2] = ctrl_mem__prologue_count_outport_routing_crossbar[8][2]; + assign routing_crossbar__prologue_count_inport[8][3] = ctrl_mem__prologue_count_outport_routing_crossbar[8][3]; + assign fu_crossbar__prologue_count_inport[8][0] = ctrl_mem__prologue_count_outport_fu_crossbar[8][0]; + assign fu_crossbar__prologue_count_inport[8][1] = ctrl_mem__prologue_count_outport_fu_crossbar[8][1]; + assign routing_crossbar__prologue_count_inport[9][0] = ctrl_mem__prologue_count_outport_routing_crossbar[9][0]; + assign routing_crossbar__prologue_count_inport[9][1] = ctrl_mem__prologue_count_outport_routing_crossbar[9][1]; + assign routing_crossbar__prologue_count_inport[9][2] = ctrl_mem__prologue_count_outport_routing_crossbar[9][2]; + assign routing_crossbar__prologue_count_inport[9][3] = ctrl_mem__prologue_count_outport_routing_crossbar[9][3]; + assign fu_crossbar__prologue_count_inport[9][0] = ctrl_mem__prologue_count_outport_fu_crossbar[9][0]; + assign fu_crossbar__prologue_count_inport[9][1] = ctrl_mem__prologue_count_outport_fu_crossbar[9][1]; + assign routing_crossbar__prologue_count_inport[10][0] = ctrl_mem__prologue_count_outport_routing_crossbar[10][0]; + assign routing_crossbar__prologue_count_inport[10][1] = ctrl_mem__prologue_count_outport_routing_crossbar[10][1]; + assign routing_crossbar__prologue_count_inport[10][2] = ctrl_mem__prologue_count_outport_routing_crossbar[10][2]; + assign routing_crossbar__prologue_count_inport[10][3] = ctrl_mem__prologue_count_outport_routing_crossbar[10][3]; + assign fu_crossbar__prologue_count_inport[10][0] = ctrl_mem__prologue_count_outport_fu_crossbar[10][0]; + assign fu_crossbar__prologue_count_inport[10][1] = ctrl_mem__prologue_count_outport_fu_crossbar[10][1]; + assign routing_crossbar__prologue_count_inport[11][0] = ctrl_mem__prologue_count_outport_routing_crossbar[11][0]; + assign routing_crossbar__prologue_count_inport[11][1] = ctrl_mem__prologue_count_outport_routing_crossbar[11][1]; + assign routing_crossbar__prologue_count_inport[11][2] = ctrl_mem__prologue_count_outport_routing_crossbar[11][2]; + assign routing_crossbar__prologue_count_inport[11][3] = ctrl_mem__prologue_count_outport_routing_crossbar[11][3]; + assign fu_crossbar__prologue_count_inport[11][0] = ctrl_mem__prologue_count_outport_fu_crossbar[11][0]; + assign fu_crossbar__prologue_count_inport[11][1] = ctrl_mem__prologue_count_outport_fu_crossbar[11][1]; + assign routing_crossbar__prologue_count_inport[12][0] = ctrl_mem__prologue_count_outport_routing_crossbar[12][0]; + assign routing_crossbar__prologue_count_inport[12][1] = ctrl_mem__prologue_count_outport_routing_crossbar[12][1]; + assign routing_crossbar__prologue_count_inport[12][2] = ctrl_mem__prologue_count_outport_routing_crossbar[12][2]; + assign routing_crossbar__prologue_count_inport[12][3] = ctrl_mem__prologue_count_outport_routing_crossbar[12][3]; + assign fu_crossbar__prologue_count_inport[12][0] = ctrl_mem__prologue_count_outport_fu_crossbar[12][0]; + assign fu_crossbar__prologue_count_inport[12][1] = ctrl_mem__prologue_count_outport_fu_crossbar[12][1]; + assign routing_crossbar__prologue_count_inport[13][0] = ctrl_mem__prologue_count_outport_routing_crossbar[13][0]; + assign routing_crossbar__prologue_count_inport[13][1] = ctrl_mem__prologue_count_outport_routing_crossbar[13][1]; + assign routing_crossbar__prologue_count_inport[13][2] = ctrl_mem__prologue_count_outport_routing_crossbar[13][2]; + assign routing_crossbar__prologue_count_inport[13][3] = ctrl_mem__prologue_count_outport_routing_crossbar[13][3]; + assign fu_crossbar__prologue_count_inport[13][0] = ctrl_mem__prologue_count_outport_fu_crossbar[13][0]; + assign fu_crossbar__prologue_count_inport[13][1] = ctrl_mem__prologue_count_outport_fu_crossbar[13][1]; + assign routing_crossbar__prologue_count_inport[14][0] = ctrl_mem__prologue_count_outport_routing_crossbar[14][0]; + assign routing_crossbar__prologue_count_inport[14][1] = ctrl_mem__prologue_count_outport_routing_crossbar[14][1]; + assign routing_crossbar__prologue_count_inport[14][2] = ctrl_mem__prologue_count_outport_routing_crossbar[14][2]; + assign routing_crossbar__prologue_count_inport[14][3] = ctrl_mem__prologue_count_outport_routing_crossbar[14][3]; + assign fu_crossbar__prologue_count_inport[14][0] = ctrl_mem__prologue_count_outport_fu_crossbar[14][0]; + assign fu_crossbar__prologue_count_inport[14][1] = ctrl_mem__prologue_count_outport_fu_crossbar[14][1]; + assign routing_crossbar__prologue_count_inport[15][0] = ctrl_mem__prologue_count_outport_routing_crossbar[15][0]; + assign routing_crossbar__prologue_count_inport[15][1] = ctrl_mem__prologue_count_outport_routing_crossbar[15][1]; + assign routing_crossbar__prologue_count_inport[15][2] = ctrl_mem__prologue_count_outport_routing_crossbar[15][2]; + assign routing_crossbar__prologue_count_inport[15][3] = ctrl_mem__prologue_count_outport_routing_crossbar[15][3]; + assign fu_crossbar__prologue_count_inport[15][0] = ctrl_mem__prologue_count_outport_fu_crossbar[15][0]; + assign fu_crossbar__prologue_count_inport[15][1] = ctrl_mem__prologue_count_outport_fu_crossbar[15][1]; + assign element__to_mem_raddr__rdy[0] = 1'd0; + assign element__from_mem_rdata__val[0] = 1'd0; + assign element__from_mem_rdata__msg[0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[0] = 1'd0; + assign element__to_mem_wdata__rdy[0] = 1'd0; + assign element__to_mem_raddr__rdy[1] = 1'd0; + assign element__from_mem_rdata__val[1] = 1'd0; + assign element__from_mem_rdata__msg[1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[1] = 1'd0; + assign element__to_mem_wdata__rdy[1] = 1'd0; + assign element__to_mem_raddr__rdy[2] = 1'd0; + assign element__from_mem_rdata__val[2] = 1'd0; + assign element__from_mem_rdata__msg[2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[2] = 1'd0; + assign element__to_mem_wdata__rdy[2] = 1'd0; + assign element__to_mem_raddr__rdy[3] = 1'd0; + assign element__from_mem_rdata__val[3] = 1'd0; + assign element__from_mem_rdata__msg[3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[3] = 1'd0; + assign element__to_mem_wdata__rdy[3] = 1'd0; + assign element__to_mem_raddr__rdy[4] = 1'd0; + assign element__from_mem_rdata__val[4] = 1'd0; + assign element__from_mem_rdata__msg[4] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[4] = 1'd0; + assign element__to_mem_wdata__rdy[4] = 1'd0; + assign element__to_mem_raddr__rdy[5] = 1'd0; + assign element__from_mem_rdata__val[5] = 1'd0; + assign element__from_mem_rdata__msg[5] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[5] = 1'd0; + assign element__to_mem_wdata__rdy[5] = 1'd0; + assign element__to_mem_raddr__rdy[6] = 1'd0; + assign element__from_mem_rdata__val[6] = 1'd0; + assign element__from_mem_rdata__msg[6] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[6] = 1'd0; + assign element__to_mem_wdata__rdy[6] = 1'd0; + assign to_mem_raddr__msg = element__to_mem_raddr__msg[7]; + assign element__to_mem_raddr__rdy[7] = to_mem_raddr__rdy; + assign to_mem_raddr__val = element__to_mem_raddr__val[7]; + assign element__from_mem_rdata__msg[7] = from_mem_rdata__msg; + assign from_mem_rdata__rdy = element__from_mem_rdata__rdy[7]; + assign element__from_mem_rdata__val[7] = from_mem_rdata__val; + assign to_mem_waddr__msg = element__to_mem_waddr__msg[7]; + assign element__to_mem_waddr__rdy[7] = to_mem_waddr__rdy; + assign to_mem_waddr__val = element__to_mem_waddr__val[7]; + assign to_mem_wdata__msg = element__to_mem_wdata__msg[7]; + assign element__to_mem_wdata__rdy[7] = to_mem_wdata__rdy; + assign to_mem_wdata__val = element__to_mem_wdata__val[7]; + assign element__to_mem_raddr__rdy[8] = 1'd0; + assign element__from_mem_rdata__val[8] = 1'd0; + assign element__from_mem_rdata__msg[8] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[8] = 1'd0; + assign element__to_mem_wdata__rdy[8] = 1'd0; + assign element__to_mem_raddr__rdy[9] = 1'd0; + assign element__from_mem_rdata__val[9] = 1'd0; + assign element__from_mem_rdata__msg[9] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[9] = 1'd0; + assign element__to_mem_wdata__rdy[9] = 1'd0; + assign element__to_mem_raddr__rdy[10] = 1'd0; + assign element__from_mem_rdata__val[10] = 1'd0; + assign element__from_mem_rdata__msg[10] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[10] = 1'd0; + assign element__to_mem_wdata__rdy[10] = 1'd0; + assign element__to_mem_raddr__rdy[11] = 1'd0; + assign element__from_mem_rdata__val[11] = 1'd0; + assign element__from_mem_rdata__msg[11] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[11] = 1'd0; + assign element__to_mem_wdata__rdy[11] = 1'd0; + assign element__to_mem_raddr__rdy[12] = 1'd0; + assign element__from_mem_rdata__val[12] = 1'd0; + assign element__from_mem_rdata__msg[12] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[12] = 1'd0; + assign element__to_mem_wdata__rdy[12] = 1'd0; + assign element__to_mem_raddr__rdy[13] = 1'd0; + assign element__from_mem_rdata__val[13] = 1'd0; + assign element__from_mem_rdata__msg[13] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[13] = 1'd0; + assign element__to_mem_wdata__rdy[13] = 1'd0; + assign element__to_mem_raddr__rdy[14] = 1'd0; + assign element__from_mem_rdata__val[14] = 1'd0; + assign element__from_mem_rdata__msg[14] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign element__to_mem_waddr__rdy[14] = 1'd0; + assign element__to_mem_wdata__rdy[14] = 1'd0; + assign tile_in_channel__recv__msg[0] = recv_data__msg[0]; + assign recv_data__rdy[0] = tile_in_channel__recv__rdy[0]; + assign tile_in_channel__recv__val[0] = recv_data__val[0]; + assign routing_crossbar__recv_data__msg[0] = tile_in_channel__send__msg[0]; + assign tile_in_channel__send__rdy[0] = routing_crossbar__recv_data__rdy[0]; + assign routing_crossbar__recv_data__val[0] = tile_in_channel__send__val[0]; + assign tile_in_channel__recv__msg[1] = recv_data__msg[1]; + assign recv_data__rdy[1] = tile_in_channel__recv__rdy[1]; + assign tile_in_channel__recv__val[1] = recv_data__val[1]; + assign routing_crossbar__recv_data__msg[1] = tile_in_channel__send__msg[1]; + assign tile_in_channel__send__rdy[1] = routing_crossbar__recv_data__rdy[1]; + assign routing_crossbar__recv_data__val[1] = tile_in_channel__send__val[1]; + assign tile_in_channel__recv__msg[2] = recv_data__msg[2]; + assign recv_data__rdy[2] = tile_in_channel__recv__rdy[2]; + assign tile_in_channel__recv__val[2] = recv_data__val[2]; + assign routing_crossbar__recv_data__msg[2] = tile_in_channel__send__msg[2]; + assign tile_in_channel__send__rdy[2] = routing_crossbar__recv_data__rdy[2]; + assign routing_crossbar__recv_data__val[2] = tile_in_channel__send__val[2]; + assign tile_in_channel__recv__msg[3] = recv_data__msg[3]; + assign recv_data__rdy[3] = tile_in_channel__recv__rdy[3]; + assign tile_in_channel__recv__val[3] = recv_data__val[3]; + assign routing_crossbar__recv_data__msg[3] = tile_in_channel__send__msg[3]; + assign tile_in_channel__send__rdy[3] = routing_crossbar__recv_data__rdy[3]; + assign routing_crossbar__recv_data__val[3] = tile_in_channel__send__val[3]; + assign routing_crossbar__crossbar_outport[0] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[0]; + assign fu_crossbar__crossbar_outport[0] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[0]; + assign routing_crossbar__crossbar_outport[1] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[1]; + assign fu_crossbar__crossbar_outport[1] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[1]; + assign routing_crossbar__crossbar_outport[2] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[2]; + assign fu_crossbar__crossbar_outport[2] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[2]; + assign routing_crossbar__crossbar_outport[3] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[3]; + assign fu_crossbar__crossbar_outport[3] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[3]; + assign routing_crossbar__crossbar_outport[4] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[4]; + assign fu_crossbar__crossbar_outport[4] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[4]; + assign routing_crossbar__crossbar_outport[5] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[5]; + assign fu_crossbar__crossbar_outport[5] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[5]; + assign routing_crossbar__crossbar_outport[6] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[6]; + assign fu_crossbar__crossbar_outport[6] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[6]; + assign routing_crossbar__crossbar_outport[7] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[7]; + assign fu_crossbar__crossbar_outport[7] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[7]; + assign fu_crossbar__recv_data__msg[0] = element__send_out__msg[0]; + assign element__send_out__rdy[0] = fu_crossbar__recv_data__rdy[0]; + assign fu_crossbar__recv_data__val[0] = element__send_out__val[0]; + assign fu_crossbar__recv_data__msg[1] = element__send_out__msg[1]; + assign element__send_out__rdy[1] = fu_crossbar__recv_data__rdy[1]; + assign fu_crossbar__recv_data__val[1] = element__send_out__val[1]; + assign tile_out_or_link__recv_fu__msg[0] = fu_crossbar__send_data__msg[0]; + assign fu_crossbar__send_data__rdy[0] = tile_out_or_link__recv_fu__rdy[0]; + assign tile_out_or_link__recv_fu__val[0] = fu_crossbar__send_data__val[0]; + assign tile_out_or_link__recv_xbar__msg[0] = routing_crossbar__send_data__msg[0]; + assign routing_crossbar__send_data__rdy[0] = tile_out_or_link__recv_xbar__rdy[0]; + assign tile_out_or_link__recv_xbar__val[0] = routing_crossbar__send_data__val[0]; + assign send_data__msg[0] = tile_out_or_link__send__msg[0]; + assign tile_out_or_link__send__rdy[0] = send_data__rdy[0]; + assign send_data__val[0] = tile_out_or_link__send__val[0]; + assign tile_out_or_link__recv_fu__msg[1] = fu_crossbar__send_data__msg[1]; + assign fu_crossbar__send_data__rdy[1] = tile_out_or_link__recv_fu__rdy[1]; + assign tile_out_or_link__recv_fu__val[1] = fu_crossbar__send_data__val[1]; + assign tile_out_or_link__recv_xbar__msg[1] = routing_crossbar__send_data__msg[1]; + assign routing_crossbar__send_data__rdy[1] = tile_out_or_link__recv_xbar__rdy[1]; + assign tile_out_or_link__recv_xbar__val[1] = routing_crossbar__send_data__val[1]; + assign send_data__msg[1] = tile_out_or_link__send__msg[1]; + assign tile_out_or_link__send__rdy[1] = send_data__rdy[1]; + assign send_data__val[1] = tile_out_or_link__send__val[1]; + assign tile_out_or_link__recv_fu__msg[2] = fu_crossbar__send_data__msg[2]; + assign fu_crossbar__send_data__rdy[2] = tile_out_or_link__recv_fu__rdy[2]; + assign tile_out_or_link__recv_fu__val[2] = fu_crossbar__send_data__val[2]; + assign tile_out_or_link__recv_xbar__msg[2] = routing_crossbar__send_data__msg[2]; + assign routing_crossbar__send_data__rdy[2] = tile_out_or_link__recv_xbar__rdy[2]; + assign tile_out_or_link__recv_xbar__val[2] = routing_crossbar__send_data__val[2]; + assign send_data__msg[2] = tile_out_or_link__send__msg[2]; + assign tile_out_or_link__send__rdy[2] = send_data__rdy[2]; + assign send_data__val[2] = tile_out_or_link__send__val[2]; + assign tile_out_or_link__recv_fu__msg[3] = fu_crossbar__send_data__msg[3]; + assign fu_crossbar__send_data__rdy[3] = tile_out_or_link__recv_fu__rdy[3]; + assign tile_out_or_link__recv_fu__val[3] = fu_crossbar__send_data__val[3]; + assign tile_out_or_link__recv_xbar__msg[3] = routing_crossbar__send_data__msg[3]; + assign routing_crossbar__send_data__rdy[3] = tile_out_or_link__recv_xbar__rdy[3]; + assign tile_out_or_link__recv_xbar__val[3] = routing_crossbar__send_data__val[3]; + assign send_data__msg[3] = tile_out_or_link__send__msg[3]; + assign tile_out_or_link__send__rdy[3] = send_data__rdy[3]; + assign send_data__val[3] = tile_out_or_link__send__val[3]; + assign register_cluster__recv_data_from_routing_crossbar__msg[0] = routing_crossbar__send_data__msg[4]; + assign routing_crossbar__send_data__rdy[4] = register_cluster__recv_data_from_routing_crossbar__rdy[0]; + assign register_cluster__recv_data_from_routing_crossbar__val[0] = routing_crossbar__send_data__val[4]; + assign register_cluster__recv_data_from_fu_crossbar__msg[0] = fu_crossbar__send_data__msg[4]; + assign fu_crossbar__send_data__rdy[4] = register_cluster__recv_data_from_fu_crossbar__rdy[0]; + assign register_cluster__recv_data_from_fu_crossbar__val[0] = fu_crossbar__send_data__val[4]; + assign register_cluster__recv_data_from_const__msg[0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign register_cluster__recv_data_from_const__val[0] = 1'd0; + assign element__recv_in__msg[0] = register_cluster__send_data_to_fu__msg[0]; + assign register_cluster__send_data_to_fu__rdy[0] = element__recv_in__rdy[0]; + assign element__recv_in__val[0] = register_cluster__send_data_to_fu__val[0]; + assign register_cluster__inport_opt = ctrl_mem__send_ctrl__msg; + assign register_cluster__recv_data_from_routing_crossbar__msg[1] = routing_crossbar__send_data__msg[5]; + assign routing_crossbar__send_data__rdy[5] = register_cluster__recv_data_from_routing_crossbar__rdy[1]; + assign register_cluster__recv_data_from_routing_crossbar__val[1] = routing_crossbar__send_data__val[5]; + assign register_cluster__recv_data_from_fu_crossbar__msg[1] = fu_crossbar__send_data__msg[5]; + assign fu_crossbar__send_data__rdy[5] = register_cluster__recv_data_from_fu_crossbar__rdy[1]; + assign register_cluster__recv_data_from_fu_crossbar__val[1] = fu_crossbar__send_data__val[5]; + assign register_cluster__recv_data_from_const__msg[1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign register_cluster__recv_data_from_const__val[1] = 1'd0; + assign element__recv_in__msg[1] = register_cluster__send_data_to_fu__msg[1]; + assign register_cluster__send_data_to_fu__rdy[1] = element__recv_in__rdy[1]; + assign element__recv_in__val[1] = register_cluster__send_data_to_fu__val[1]; + assign register_cluster__recv_data_from_routing_crossbar__msg[2] = routing_crossbar__send_data__msg[6]; + assign routing_crossbar__send_data__rdy[6] = register_cluster__recv_data_from_routing_crossbar__rdy[2]; + assign register_cluster__recv_data_from_routing_crossbar__val[2] = routing_crossbar__send_data__val[6]; + assign register_cluster__recv_data_from_fu_crossbar__msg[2] = fu_crossbar__send_data__msg[6]; + assign fu_crossbar__send_data__rdy[6] = register_cluster__recv_data_from_fu_crossbar__rdy[2]; + assign register_cluster__recv_data_from_fu_crossbar__val[2] = fu_crossbar__send_data__val[6]; + assign register_cluster__recv_data_from_const__msg[2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign register_cluster__recv_data_from_const__val[2] = 1'd0; + assign element__recv_in__msg[2] = register_cluster__send_data_to_fu__msg[2]; + assign register_cluster__send_data_to_fu__rdy[2] = element__recv_in__rdy[2]; + assign element__recv_in__val[2] = register_cluster__send_data_to_fu__val[2]; + assign register_cluster__recv_data_from_routing_crossbar__msg[3] = routing_crossbar__send_data__msg[7]; + assign routing_crossbar__send_data__rdy[7] = register_cluster__recv_data_from_routing_crossbar__rdy[3]; + assign register_cluster__recv_data_from_routing_crossbar__val[3] = routing_crossbar__send_data__val[7]; + assign register_cluster__recv_data_from_fu_crossbar__msg[3] = fu_crossbar__send_data__msg[7]; + assign fu_crossbar__send_data__rdy[7] = register_cluster__recv_data_from_fu_crossbar__rdy[3]; + assign register_cluster__recv_data_from_fu_crossbar__val[3] = fu_crossbar__send_data__val[7]; + assign register_cluster__recv_data_from_const__msg[3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign register_cluster__recv_data_from_const__val[3] = 1'd0; + assign element__recv_in__msg[3] = register_cluster__send_data_to_fu__msg[3]; + assign register_cluster__send_data_to_fu__rdy[3] = element__recv_in__rdy[3]; + assign element__recv_in__val[3] = register_cluster__send_data_to_fu__val[3]; + assign element__clear[0] = 1'd0; + assign element__clear[1] = 1'd0; + assign element__clear[2] = 1'd0; + assign element__clear[3] = 1'd0; + assign element__clear[4] = 1'd0; + assign element__clear[5] = 1'd0; + assign element__clear[6] = 1'd0; + assign element__clear[7] = 1'd0; + assign element__clear[8] = 1'd0; + assign element__clear[9] = 1'd0; + assign element__clear[10] = 1'd0; + assign element__clear[11] = 1'd0; + assign element__clear[12] = 1'd0; + assign element__clear[13] = 1'd0; + assign element__clear[14] = 1'd0; + assign fu_crossbar__clear = 1'd0; + assign routing_crossbar__clear = 1'd0; + +endmodule + + +// PyMTL Component CgraRTL Definition +// Full name: CgraRTL__CgraPayloadType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__multi_cgra_rows_2__multi_cgra_columns_2__width_4__height_4__ctrl_mem_size_16__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_registers_per_reg_bank_16__num_ctrl_4__total_steps_38__mem_access_is_combinational_True__FunctionUnit_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ]__cgra_topology_Mesh__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)}__is_multi_cgra_True__has_ctrl_ring_True +// At /home/ajokai/cgra/VectorCGRAfork0/cgra/CgraRTL.py + +module CgraRTL__72d915b46abe89cb +( + input logic [6:0] address_lower , + input logic [6:0] address_upper , + input logic [1:0] cgra_id , + input logic [0:0] clk , + input logic [0:0] reset , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_east__msg [0:3] , + output logic [0:0] recv_data_on_boundary_east__rdy [0:3] , + input logic [0:0] recv_data_on_boundary_east__val [0:3] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_north__msg [0:3] , + output logic [0:0] recv_data_on_boundary_north__rdy [0:3] , + input logic [0:0] recv_data_on_boundary_north__val [0:3] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_south__msg [0:3] , + output logic [0:0] recv_data_on_boundary_south__rdy [0:3] , + input logic [0:0] recv_data_on_boundary_south__val [0:3] , + input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_west__msg [0:3] , + output logic [0:0] recv_data_on_boundary_west__rdy [0:3] , + input logic [0:0] recv_data_on_boundary_west__val [0:3] , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , + output logic [0:0] recv_from_cpu_pkt__rdy , + input logic [0:0] recv_from_cpu_pkt__val , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_inter_cgra_noc__msg , + output logic [0:0] recv_from_inter_cgra_noc__rdy , + input logic [0:0] recv_from_inter_cgra_noc__val , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_east__msg [0:3] , + input logic [0:0] send_data_on_boundary_east__rdy [0:3] , + output logic [0:0] send_data_on_boundary_east__val [0:3] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_north__msg [0:3] , + input logic [0:0] send_data_on_boundary_north__rdy [0:3] , + output logic [0:0] send_data_on_boundary_north__val [0:3] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_south__msg [0:3] , + input logic [0:0] send_data_on_boundary_south__rdy [0:3] , + output logic [0:0] send_data_on_boundary_south__val [0:3] , + output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_west__msg [0:3] , + input logic [0:0] send_data_on_boundary_west__rdy [0:3] , + output logic [0:0] send_data_on_boundary_west__val [0:3] , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , + input logic [0:0] send_to_cpu_pkt__rdy , + output logic [0:0] send_to_cpu_pkt__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_inter_cgra_noc__msg , + input logic [0:0] send_to_inter_cgra_noc__rdy , + output logic [0:0] send_to_inter_cgra_noc__val +); + //------------------------------------------------------------- + // Component controller + //------------------------------------------------------------- + + logic [1:0] controller__cgra_id; + logic [0:0] controller__clk; + logic [0:0] controller__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__recv_from_cpu_pkt__msg; + logic [0:0] controller__recv_from_cpu_pkt__rdy; + logic [0:0] controller__recv_from_cpu_pkt__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__recv_from_ctrl_ring_pkt__msg; + logic [0:0] controller__recv_from_ctrl_ring_pkt__rdy; + logic [0:0] controller__recv_from_ctrl_ring_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_inter_cgra_noc__msg; + logic [0:0] controller__recv_from_inter_cgra_noc__rdy; + logic [0:0] controller__recv_from_inter_cgra_noc__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_load_request_pkt__msg; + logic [0:0] controller__recv_from_tile_load_request_pkt__rdy; + logic [0:0] controller__recv_from_tile_load_request_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_load_response_pkt__msg; + logic [0:0] controller__recv_from_tile_load_response_pkt__rdy; + logic [0:0] controller__recv_from_tile_load_response_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_store_request_pkt__msg; + logic [0:0] controller__recv_from_tile_store_request_pkt__rdy; + logic [0:0] controller__recv_from_tile_store_request_pkt__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__send_to_cpu_pkt__msg; + logic [0:0] controller__send_to_cpu_pkt__rdy; + logic [0:0] controller__send_to_cpu_pkt__val; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__send_to_ctrl_ring_pkt__msg; + logic [0:0] controller__send_to_ctrl_ring_pkt__rdy; + logic [0:0] controller__send_to_ctrl_ring_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_inter_cgra_noc__msg; + logic [0:0] controller__send_to_inter_cgra_noc__rdy; + logic [0:0] controller__send_to_inter_cgra_noc__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_mem_load_request__msg; + logic [0:0] controller__send_to_mem_load_request__rdy; + logic [0:0] controller__send_to_mem_load_request__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_mem_store_request__msg; + logic [0:0] controller__send_to_mem_store_request__rdy; + logic [0:0] controller__send_to_mem_store_request__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_tile_load_response__msg; + logic [0:0] controller__send_to_tile_load_response__rdy; + logic [0:0] controller__send_to_tile_load_response__val; + + ControllerRTL__e06602ce343fdc8d controller + ( + .cgra_id( controller__cgra_id ), + .clk( controller__clk ), + .reset( controller__reset ), + .recv_from_cpu_pkt__msg( controller__recv_from_cpu_pkt__msg ), + .recv_from_cpu_pkt__rdy( controller__recv_from_cpu_pkt__rdy ), + .recv_from_cpu_pkt__val( controller__recv_from_cpu_pkt__val ), + .recv_from_ctrl_ring_pkt__msg( controller__recv_from_ctrl_ring_pkt__msg ), + .recv_from_ctrl_ring_pkt__rdy( controller__recv_from_ctrl_ring_pkt__rdy ), + .recv_from_ctrl_ring_pkt__val( controller__recv_from_ctrl_ring_pkt__val ), + .recv_from_inter_cgra_noc__msg( controller__recv_from_inter_cgra_noc__msg ), + .recv_from_inter_cgra_noc__rdy( controller__recv_from_inter_cgra_noc__rdy ), + .recv_from_inter_cgra_noc__val( controller__recv_from_inter_cgra_noc__val ), + .recv_from_tile_load_request_pkt__msg( controller__recv_from_tile_load_request_pkt__msg ), + .recv_from_tile_load_request_pkt__rdy( controller__recv_from_tile_load_request_pkt__rdy ), + .recv_from_tile_load_request_pkt__val( controller__recv_from_tile_load_request_pkt__val ), + .recv_from_tile_load_response_pkt__msg( controller__recv_from_tile_load_response_pkt__msg ), + .recv_from_tile_load_response_pkt__rdy( controller__recv_from_tile_load_response_pkt__rdy ), + .recv_from_tile_load_response_pkt__val( controller__recv_from_tile_load_response_pkt__val ), + .recv_from_tile_store_request_pkt__msg( controller__recv_from_tile_store_request_pkt__msg ), + .recv_from_tile_store_request_pkt__rdy( controller__recv_from_tile_store_request_pkt__rdy ), + .recv_from_tile_store_request_pkt__val( controller__recv_from_tile_store_request_pkt__val ), + .send_to_cpu_pkt__msg( controller__send_to_cpu_pkt__msg ), + .send_to_cpu_pkt__rdy( controller__send_to_cpu_pkt__rdy ), + .send_to_cpu_pkt__val( controller__send_to_cpu_pkt__val ), + .send_to_ctrl_ring_pkt__msg( controller__send_to_ctrl_ring_pkt__msg ), + .send_to_ctrl_ring_pkt__rdy( controller__send_to_ctrl_ring_pkt__rdy ), + .send_to_ctrl_ring_pkt__val( controller__send_to_ctrl_ring_pkt__val ), + .send_to_inter_cgra_noc__msg( controller__send_to_inter_cgra_noc__msg ), + .send_to_inter_cgra_noc__rdy( controller__send_to_inter_cgra_noc__rdy ), + .send_to_inter_cgra_noc__val( controller__send_to_inter_cgra_noc__val ), + .send_to_mem_load_request__msg( controller__send_to_mem_load_request__msg ), + .send_to_mem_load_request__rdy( controller__send_to_mem_load_request__rdy ), + .send_to_mem_load_request__val( controller__send_to_mem_load_request__val ), + .send_to_mem_store_request__msg( controller__send_to_mem_store_request__msg ), + .send_to_mem_store_request__rdy( controller__send_to_mem_store_request__rdy ), + .send_to_mem_store_request__val( controller__send_to_mem_store_request__val ), + .send_to_tile_load_response__msg( controller__send_to_tile_load_response__msg ), + .send_to_tile_load_response__rdy( controller__send_to_tile_load_response__rdy ), + .send_to_tile_load_response__val( controller__send_to_tile_load_response__val ) + ); + + //------------------------------------------------------------- + // End of component controller + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component ctrl_ring + //------------------------------------------------------------- + + logic [0:0] ctrl_ring__clk; + logic [0:0] ctrl_ring__reset; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_ring__recv__msg [0:16]; + logic [0:0] ctrl_ring__recv__rdy [0:16]; + logic [0:0] ctrl_ring__recv__val [0:16]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_ring__send__msg [0:16]; + logic [0:0] ctrl_ring__send__rdy [0:16]; + logic [0:0] ctrl_ring__send__val [0:16]; + + RingNetworkRTL__8866f4e00dbc912a ctrl_ring + ( + .clk( ctrl_ring__clk ), + .reset( ctrl_ring__reset ), + .recv__msg( ctrl_ring__recv__msg ), + .recv__rdy( ctrl_ring__recv__rdy ), + .recv__val( ctrl_ring__recv__val ), + .send__msg( ctrl_ring__send__msg ), + .send__rdy( ctrl_ring__send__rdy ), + .send__val( ctrl_ring__send__val ) + ); + + //------------------------------------------------------------- + // End of component ctrl_ring + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component data_mem + //------------------------------------------------------------- + + logic [6:0] data_mem__address_lower; + logic [6:0] data_mem__address_upper; + logic [1:0] data_mem__cgra_id; + logic [0:0] data_mem__clk; + logic [0:0] data_mem__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_load_request__msg; + logic [0:0] data_mem__recv_from_noc_load_request__rdy; + logic [0:0] data_mem__recv_from_noc_load_request__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_load_response_pkt__msg; + logic [0:0] data_mem__recv_from_noc_load_response_pkt__rdy; + logic [0:0] data_mem__recv_from_noc_load_response_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_store_request__msg; + logic [0:0] data_mem__recv_from_noc_store_request__rdy; + logic [0:0] data_mem__recv_from_noc_store_request__val; + logic [6:0] data_mem__recv_raddr__msg [0:6]; + logic [0:0] data_mem__recv_raddr__rdy [0:6]; + logic [0:0] data_mem__recv_raddr__val [0:6]; + logic [6:0] data_mem__recv_waddr__msg [0:6]; + logic [0:0] data_mem__recv_waddr__rdy [0:6]; + logic [0:0] data_mem__recv_waddr__val [0:6]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data_mem__recv_wdata__msg [0:6]; + logic [0:0] data_mem__recv_wdata__rdy [0:6]; + logic [0:0] data_mem__recv_wdata__val [0:6]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data_mem__send_rdata__msg [0:6]; + logic [0:0] data_mem__send_rdata__rdy [0:6]; + logic [0:0] data_mem__send_rdata__val [0:6]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_load_request_pkt__msg; + logic [0:0] data_mem__send_to_noc_load_request_pkt__rdy; + logic [0:0] data_mem__send_to_noc_load_request_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_load_response_pkt__msg; + logic [0:0] data_mem__send_to_noc_load_response_pkt__rdy; + logic [0:0] data_mem__send_to_noc_load_response_pkt__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_store_pkt__msg; + logic [0:0] data_mem__send_to_noc_store_pkt__rdy; + logic [0:0] data_mem__send_to_noc_store_pkt__val; + + DataMemControllerRTL__20df9b544ed809f0 data_mem + ( + .address_lower( data_mem__address_lower ), + .address_upper( data_mem__address_upper ), + .cgra_id( data_mem__cgra_id ), + .clk( data_mem__clk ), + .reset( data_mem__reset ), + .recv_from_noc_load_request__msg( data_mem__recv_from_noc_load_request__msg ), + .recv_from_noc_load_request__rdy( data_mem__recv_from_noc_load_request__rdy ), + .recv_from_noc_load_request__val( data_mem__recv_from_noc_load_request__val ), + .recv_from_noc_load_response_pkt__msg( data_mem__recv_from_noc_load_response_pkt__msg ), + .recv_from_noc_load_response_pkt__rdy( data_mem__recv_from_noc_load_response_pkt__rdy ), + .recv_from_noc_load_response_pkt__val( data_mem__recv_from_noc_load_response_pkt__val ), + .recv_from_noc_store_request__msg( data_mem__recv_from_noc_store_request__msg ), + .recv_from_noc_store_request__rdy( data_mem__recv_from_noc_store_request__rdy ), + .recv_from_noc_store_request__val( data_mem__recv_from_noc_store_request__val ), + .recv_raddr__msg( data_mem__recv_raddr__msg ), + .recv_raddr__rdy( data_mem__recv_raddr__rdy ), + .recv_raddr__val( data_mem__recv_raddr__val ), + .recv_waddr__msg( data_mem__recv_waddr__msg ), + .recv_waddr__rdy( data_mem__recv_waddr__rdy ), + .recv_waddr__val( data_mem__recv_waddr__val ), + .recv_wdata__msg( data_mem__recv_wdata__msg ), + .recv_wdata__rdy( data_mem__recv_wdata__rdy ), + .recv_wdata__val( data_mem__recv_wdata__val ), + .send_rdata__msg( data_mem__send_rdata__msg ), + .send_rdata__rdy( data_mem__send_rdata__rdy ), + .send_rdata__val( data_mem__send_rdata__val ), + .send_to_noc_load_request_pkt__msg( data_mem__send_to_noc_load_request_pkt__msg ), + .send_to_noc_load_request_pkt__rdy( data_mem__send_to_noc_load_request_pkt__rdy ), + .send_to_noc_load_request_pkt__val( data_mem__send_to_noc_load_request_pkt__val ), + .send_to_noc_load_response_pkt__msg( data_mem__send_to_noc_load_response_pkt__msg ), + .send_to_noc_load_response_pkt__rdy( data_mem__send_to_noc_load_response_pkt__rdy ), + .send_to_noc_load_response_pkt__val( data_mem__send_to_noc_load_response_pkt__val ), + .send_to_noc_store_pkt__msg( data_mem__send_to_noc_store_pkt__msg ), + .send_to_noc_store_pkt__rdy( data_mem__send_to_noc_store_pkt__rdy ), + .send_to_noc_store_pkt__val( data_mem__send_to_noc_store_pkt__val ) + ); + + //------------------------------------------------------------- + // End of component data_mem + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component tile[0:15] + //------------------------------------------------------------- + + logic [1:0] tile__cgra_id [0:15]; + logic [0:0] tile__clk [0:15]; + logic [0:0] tile__reset [0:15]; + logic [4:0] tile__tile_id [0:15]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__from_mem_rdata__msg [0:15]; + logic [0:0] tile__from_mem_rdata__rdy [0:15]; + logic [0:0] tile__from_mem_rdata__val [0:15]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__recv_data__msg [0:15][0:3]; + logic [0:0] tile__recv_data__rdy [0:15][0:3]; + logic [0:0] tile__recv_data__val [0:15][0:3]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 tile__recv_from_controller_pkt__msg [0:15]; + logic [0:0] tile__recv_from_controller_pkt__rdy [0:15]; + logic [0:0] tile__recv_from_controller_pkt__val [0:15]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__send_data__msg [0:15][0:3]; + logic [0:0] tile__send_data__rdy [0:15][0:3]; + logic [0:0] tile__send_data__val [0:15][0:3]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 tile__send_to_controller_pkt__msg [0:15]; + logic [0:0] tile__send_to_controller_pkt__rdy [0:15]; + logic [0:0] tile__send_to_controller_pkt__val [0:15]; + logic [6:0] tile__to_mem_raddr__msg [0:15]; + logic [0:0] tile__to_mem_raddr__rdy [0:15]; + logic [0:0] tile__to_mem_raddr__val [0:15]; + logic [6:0] tile__to_mem_waddr__msg [0:15]; + logic [0:0] tile__to_mem_waddr__rdy [0:15]; + logic [0:0] tile__to_mem_waddr__val [0:15]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__to_mem_wdata__msg [0:15]; + logic [0:0] tile__to_mem_wdata__rdy [0:15]; + logic [0:0] tile__to_mem_wdata__val [0:15]; + + TileRTL__78da5e3970e1cd1d tile__0 + ( + .cgra_id( tile__cgra_id[0] ), + .clk( tile__clk[0] ), + .reset( tile__reset[0] ), + .tile_id( tile__tile_id[0] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[0] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[0] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[0] ), + .recv_data__msg( tile__recv_data__msg[0] ), + .recv_data__rdy( tile__recv_data__rdy[0] ), + .recv_data__val( tile__recv_data__val[0] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[0] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[0] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[0] ), + .send_data__msg( tile__send_data__msg[0] ), + .send_data__rdy( tile__send_data__rdy[0] ), + .send_data__val( tile__send_data__val[0] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[0] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[0] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[0] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[0] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[0] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[0] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[0] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[0] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[0] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[0] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[0] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[0] ) + ); + + TileRTL__78da5e3970e1cd1d tile__1 + ( + .cgra_id( tile__cgra_id[1] ), + .clk( tile__clk[1] ), + .reset( tile__reset[1] ), + .tile_id( tile__tile_id[1] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[1] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[1] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[1] ), + .recv_data__msg( tile__recv_data__msg[1] ), + .recv_data__rdy( tile__recv_data__rdy[1] ), + .recv_data__val( tile__recv_data__val[1] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[1] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[1] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[1] ), + .send_data__msg( tile__send_data__msg[1] ), + .send_data__rdy( tile__send_data__rdy[1] ), + .send_data__val( tile__send_data__val[1] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[1] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[1] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[1] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[1] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[1] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[1] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[1] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[1] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[1] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[1] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[1] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[1] ) + ); + + TileRTL__78da5e3970e1cd1d tile__2 + ( + .cgra_id( tile__cgra_id[2] ), + .clk( tile__clk[2] ), + .reset( tile__reset[2] ), + .tile_id( tile__tile_id[2] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[2] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[2] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[2] ), + .recv_data__msg( tile__recv_data__msg[2] ), + .recv_data__rdy( tile__recv_data__rdy[2] ), + .recv_data__val( tile__recv_data__val[2] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[2] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[2] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[2] ), + .send_data__msg( tile__send_data__msg[2] ), + .send_data__rdy( tile__send_data__rdy[2] ), + .send_data__val( tile__send_data__val[2] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[2] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[2] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[2] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[2] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[2] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[2] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[2] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[2] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[2] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[2] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[2] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[2] ) + ); + + TileRTL__78da5e3970e1cd1d tile__3 + ( + .cgra_id( tile__cgra_id[3] ), + .clk( tile__clk[3] ), + .reset( tile__reset[3] ), + .tile_id( tile__tile_id[3] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[3] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[3] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[3] ), + .recv_data__msg( tile__recv_data__msg[3] ), + .recv_data__rdy( tile__recv_data__rdy[3] ), + .recv_data__val( tile__recv_data__val[3] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[3] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[3] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[3] ), + .send_data__msg( tile__send_data__msg[3] ), + .send_data__rdy( tile__send_data__rdy[3] ), + .send_data__val( tile__send_data__val[3] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[3] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[3] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[3] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[3] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[3] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[3] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[3] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[3] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[3] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[3] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[3] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[3] ) + ); + + TileRTL__78da5e3970e1cd1d tile__4 + ( + .cgra_id( tile__cgra_id[4] ), + .clk( tile__clk[4] ), + .reset( tile__reset[4] ), + .tile_id( tile__tile_id[4] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[4] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[4] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[4] ), + .recv_data__msg( tile__recv_data__msg[4] ), + .recv_data__rdy( tile__recv_data__rdy[4] ), + .recv_data__val( tile__recv_data__val[4] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[4] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[4] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[4] ), + .send_data__msg( tile__send_data__msg[4] ), + .send_data__rdy( tile__send_data__rdy[4] ), + .send_data__val( tile__send_data__val[4] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[4] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[4] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[4] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[4] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[4] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[4] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[4] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[4] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[4] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[4] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[4] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[4] ) + ); + + TileRTL__78da5e3970e1cd1d tile__5 + ( + .cgra_id( tile__cgra_id[5] ), + .clk( tile__clk[5] ), + .reset( tile__reset[5] ), + .tile_id( tile__tile_id[5] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[5] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[5] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[5] ), + .recv_data__msg( tile__recv_data__msg[5] ), + .recv_data__rdy( tile__recv_data__rdy[5] ), + .recv_data__val( tile__recv_data__val[5] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[5] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[5] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[5] ), + .send_data__msg( tile__send_data__msg[5] ), + .send_data__rdy( tile__send_data__rdy[5] ), + .send_data__val( tile__send_data__val[5] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[5] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[5] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[5] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[5] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[5] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[5] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[5] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[5] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[5] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[5] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[5] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[5] ) + ); + + TileRTL__78da5e3970e1cd1d tile__6 + ( + .cgra_id( tile__cgra_id[6] ), + .clk( tile__clk[6] ), + .reset( tile__reset[6] ), + .tile_id( tile__tile_id[6] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[6] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[6] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[6] ), + .recv_data__msg( tile__recv_data__msg[6] ), + .recv_data__rdy( tile__recv_data__rdy[6] ), + .recv_data__val( tile__recv_data__val[6] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[6] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[6] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[6] ), + .send_data__msg( tile__send_data__msg[6] ), + .send_data__rdy( tile__send_data__rdy[6] ), + .send_data__val( tile__send_data__val[6] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[6] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[6] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[6] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[6] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[6] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[6] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[6] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[6] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[6] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[6] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[6] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[6] ) + ); + + TileRTL__78da5e3970e1cd1d tile__7 + ( + .cgra_id( tile__cgra_id[7] ), + .clk( tile__clk[7] ), + .reset( tile__reset[7] ), + .tile_id( tile__tile_id[7] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[7] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[7] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[7] ), + .recv_data__msg( tile__recv_data__msg[7] ), + .recv_data__rdy( tile__recv_data__rdy[7] ), + .recv_data__val( tile__recv_data__val[7] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[7] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[7] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[7] ), + .send_data__msg( tile__send_data__msg[7] ), + .send_data__rdy( tile__send_data__rdy[7] ), + .send_data__val( tile__send_data__val[7] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[7] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[7] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[7] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[7] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[7] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[7] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[7] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[7] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[7] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[7] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[7] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[7] ) + ); + + TileRTL__78da5e3970e1cd1d tile__8 + ( + .cgra_id( tile__cgra_id[8] ), + .clk( tile__clk[8] ), + .reset( tile__reset[8] ), + .tile_id( tile__tile_id[8] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[8] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[8] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[8] ), + .recv_data__msg( tile__recv_data__msg[8] ), + .recv_data__rdy( tile__recv_data__rdy[8] ), + .recv_data__val( tile__recv_data__val[8] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[8] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[8] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[8] ), + .send_data__msg( tile__send_data__msg[8] ), + .send_data__rdy( tile__send_data__rdy[8] ), + .send_data__val( tile__send_data__val[8] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[8] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[8] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[8] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[8] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[8] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[8] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[8] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[8] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[8] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[8] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[8] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[8] ) + ); + + TileRTL__78da5e3970e1cd1d tile__9 + ( + .cgra_id( tile__cgra_id[9] ), + .clk( tile__clk[9] ), + .reset( tile__reset[9] ), + .tile_id( tile__tile_id[9] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[9] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[9] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[9] ), + .recv_data__msg( tile__recv_data__msg[9] ), + .recv_data__rdy( tile__recv_data__rdy[9] ), + .recv_data__val( tile__recv_data__val[9] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[9] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[9] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[9] ), + .send_data__msg( tile__send_data__msg[9] ), + .send_data__rdy( tile__send_data__rdy[9] ), + .send_data__val( tile__send_data__val[9] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[9] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[9] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[9] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[9] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[9] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[9] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[9] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[9] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[9] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[9] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[9] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[9] ) + ); + + TileRTL__78da5e3970e1cd1d tile__10 + ( + .cgra_id( tile__cgra_id[10] ), + .clk( tile__clk[10] ), + .reset( tile__reset[10] ), + .tile_id( tile__tile_id[10] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[10] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[10] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[10] ), + .recv_data__msg( tile__recv_data__msg[10] ), + .recv_data__rdy( tile__recv_data__rdy[10] ), + .recv_data__val( tile__recv_data__val[10] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[10] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[10] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[10] ), + .send_data__msg( tile__send_data__msg[10] ), + .send_data__rdy( tile__send_data__rdy[10] ), + .send_data__val( tile__send_data__val[10] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[10] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[10] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[10] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[10] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[10] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[10] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[10] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[10] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[10] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[10] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[10] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[10] ) + ); + + TileRTL__78da5e3970e1cd1d tile__11 + ( + .cgra_id( tile__cgra_id[11] ), + .clk( tile__clk[11] ), + .reset( tile__reset[11] ), + .tile_id( tile__tile_id[11] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[11] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[11] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[11] ), + .recv_data__msg( tile__recv_data__msg[11] ), + .recv_data__rdy( tile__recv_data__rdy[11] ), + .recv_data__val( tile__recv_data__val[11] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[11] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[11] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[11] ), + .send_data__msg( tile__send_data__msg[11] ), + .send_data__rdy( tile__send_data__rdy[11] ), + .send_data__val( tile__send_data__val[11] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[11] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[11] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[11] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[11] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[11] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[11] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[11] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[11] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[11] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[11] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[11] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[11] ) + ); + + TileRTL__78da5e3970e1cd1d tile__12 + ( + .cgra_id( tile__cgra_id[12] ), + .clk( tile__clk[12] ), + .reset( tile__reset[12] ), + .tile_id( tile__tile_id[12] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[12] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[12] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[12] ), + .recv_data__msg( tile__recv_data__msg[12] ), + .recv_data__rdy( tile__recv_data__rdy[12] ), + .recv_data__val( tile__recv_data__val[12] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[12] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[12] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[12] ), + .send_data__msg( tile__send_data__msg[12] ), + .send_data__rdy( tile__send_data__rdy[12] ), + .send_data__val( tile__send_data__val[12] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[12] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[12] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[12] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[12] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[12] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[12] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[12] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[12] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[12] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[12] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[12] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[12] ) + ); + + TileRTL__78da5e3970e1cd1d tile__13 + ( + .cgra_id( tile__cgra_id[13] ), + .clk( tile__clk[13] ), + .reset( tile__reset[13] ), + .tile_id( tile__tile_id[13] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[13] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[13] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[13] ), + .recv_data__msg( tile__recv_data__msg[13] ), + .recv_data__rdy( tile__recv_data__rdy[13] ), + .recv_data__val( tile__recv_data__val[13] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[13] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[13] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[13] ), + .send_data__msg( tile__send_data__msg[13] ), + .send_data__rdy( tile__send_data__rdy[13] ), + .send_data__val( tile__send_data__val[13] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[13] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[13] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[13] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[13] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[13] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[13] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[13] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[13] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[13] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[13] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[13] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[13] ) + ); + + TileRTL__78da5e3970e1cd1d tile__14 + ( + .cgra_id( tile__cgra_id[14] ), + .clk( tile__clk[14] ), + .reset( tile__reset[14] ), + .tile_id( tile__tile_id[14] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[14] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[14] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[14] ), + .recv_data__msg( tile__recv_data__msg[14] ), + .recv_data__rdy( tile__recv_data__rdy[14] ), + .recv_data__val( tile__recv_data__val[14] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[14] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[14] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[14] ), + .send_data__msg( tile__send_data__msg[14] ), + .send_data__rdy( tile__send_data__rdy[14] ), + .send_data__val( tile__send_data__val[14] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[14] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[14] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[14] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[14] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[14] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[14] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[14] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[14] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[14] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[14] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[14] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[14] ) + ); + + TileRTL__78da5e3970e1cd1d tile__15 + ( + .cgra_id( tile__cgra_id[15] ), + .clk( tile__clk[15] ), + .reset( tile__reset[15] ), + .tile_id( tile__tile_id[15] ), + .from_mem_rdata__msg( tile__from_mem_rdata__msg[15] ), + .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[15] ), + .from_mem_rdata__val( tile__from_mem_rdata__val[15] ), + .recv_data__msg( tile__recv_data__msg[15] ), + .recv_data__rdy( tile__recv_data__rdy[15] ), + .recv_data__val( tile__recv_data__val[15] ), + .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[15] ), + .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[15] ), + .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[15] ), + .send_data__msg( tile__send_data__msg[15] ), + .send_data__rdy( tile__send_data__rdy[15] ), + .send_data__val( tile__send_data__val[15] ), + .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[15] ), + .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[15] ), + .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[15] ), + .to_mem_raddr__msg( tile__to_mem_raddr__msg[15] ), + .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[15] ), + .to_mem_raddr__val( tile__to_mem_raddr__val[15] ), + .to_mem_waddr__msg( tile__to_mem_waddr__msg[15] ), + .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[15] ), + .to_mem_waddr__val( tile__to_mem_waddr__val[15] ), + .to_mem_wdata__msg( tile__to_mem_wdata__msg[15] ), + .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[15] ), + .to_mem_wdata__val( tile__to_mem_wdata__val[15] ) + ); + + //------------------------------------------------------------- + // End of component tile[0:15] + //------------------------------------------------------------- + + assign tile__clk[0] = clk; + assign tile__reset[0] = reset; + assign tile__clk[1] = clk; + assign tile__reset[1] = reset; + assign tile__clk[2] = clk; + assign tile__reset[2] = reset; + assign tile__clk[3] = clk; + assign tile__reset[3] = reset; + assign tile__clk[4] = clk; + assign tile__reset[4] = reset; + assign tile__clk[5] = clk; + assign tile__reset[5] = reset; + assign tile__clk[6] = clk; + assign tile__reset[6] = reset; + assign tile__clk[7] = clk; + assign tile__reset[7] = reset; + assign tile__clk[8] = clk; + assign tile__reset[8] = reset; + assign tile__clk[9] = clk; + assign tile__reset[9] = reset; + assign tile__clk[10] = clk; + assign tile__reset[10] = reset; + assign tile__clk[11] = clk; + assign tile__reset[11] = reset; + assign tile__clk[12] = clk; + assign tile__reset[12] = reset; + assign tile__clk[13] = clk; + assign tile__reset[13] = reset; + assign tile__clk[14] = clk; + assign tile__reset[14] = reset; + assign tile__clk[15] = clk; + assign tile__reset[15] = reset; + assign data_mem__clk = clk; + assign data_mem__reset = reset; + assign controller__clk = clk; + assign controller__reset = reset; + assign ctrl_ring__clk = clk; + assign ctrl_ring__reset = reset; + assign controller__cgra_id = cgra_id; + assign data_mem__cgra_id = cgra_id; + assign data_mem__address_lower = address_lower; + assign data_mem__address_upper = address_upper; + assign data_mem__recv_from_noc_load_request__msg = controller__send_to_mem_load_request__msg; + assign controller__send_to_mem_load_request__rdy = data_mem__recv_from_noc_load_request__rdy; + assign data_mem__recv_from_noc_load_request__val = controller__send_to_mem_load_request__val; + assign data_mem__recv_from_noc_store_request__msg = controller__send_to_mem_store_request__msg; + assign controller__send_to_mem_store_request__rdy = data_mem__recv_from_noc_store_request__rdy; + assign data_mem__recv_from_noc_store_request__val = controller__send_to_mem_store_request__val; + assign data_mem__recv_from_noc_load_response_pkt__msg = controller__send_to_tile_load_response__msg; + assign controller__send_to_tile_load_response__rdy = data_mem__recv_from_noc_load_response_pkt__rdy; + assign data_mem__recv_from_noc_load_response_pkt__val = controller__send_to_tile_load_response__val; + assign controller__recv_from_tile_load_request_pkt__msg = data_mem__send_to_noc_load_request_pkt__msg; + assign data_mem__send_to_noc_load_request_pkt__rdy = controller__recv_from_tile_load_request_pkt__rdy; + assign controller__recv_from_tile_load_request_pkt__val = data_mem__send_to_noc_load_request_pkt__val; + assign controller__recv_from_tile_load_response_pkt__msg = data_mem__send_to_noc_load_response_pkt__msg; + assign data_mem__send_to_noc_load_response_pkt__rdy = controller__recv_from_tile_load_response_pkt__rdy; + assign controller__recv_from_tile_load_response_pkt__val = data_mem__send_to_noc_load_response_pkt__val; + assign controller__recv_from_tile_store_request_pkt__msg = data_mem__send_to_noc_store_pkt__msg; + assign data_mem__send_to_noc_store_pkt__rdy = controller__recv_from_tile_store_request_pkt__rdy; + assign controller__recv_from_tile_store_request_pkt__val = data_mem__send_to_noc_store_pkt__val; + assign controller__recv_from_inter_cgra_noc__msg = recv_from_inter_cgra_noc__msg; + assign recv_from_inter_cgra_noc__rdy = controller__recv_from_inter_cgra_noc__rdy; + assign controller__recv_from_inter_cgra_noc__val = recv_from_inter_cgra_noc__val; + assign send_to_inter_cgra_noc__msg = controller__send_to_inter_cgra_noc__msg; + assign controller__send_to_inter_cgra_noc__rdy = send_to_inter_cgra_noc__rdy; + assign send_to_inter_cgra_noc__val = controller__send_to_inter_cgra_noc__val; + assign controller__recv_from_cpu_pkt__msg = recv_from_cpu_pkt__msg; + assign recv_from_cpu_pkt__rdy = controller__recv_from_cpu_pkt__rdy; + assign controller__recv_from_cpu_pkt__val = recv_from_cpu_pkt__val; + assign send_to_cpu_pkt__msg = controller__send_to_cpu_pkt__msg; + assign controller__send_to_cpu_pkt__rdy = send_to_cpu_pkt__rdy; + assign send_to_cpu_pkt__val = controller__send_to_cpu_pkt__val; + assign tile__tile_id[0] = 5'd0; + assign tile__cgra_id[0] = cgra_id; + assign tile__tile_id[1] = 5'd1; + assign tile__cgra_id[1] = cgra_id; + assign tile__tile_id[2] = 5'd2; + assign tile__cgra_id[2] = cgra_id; + assign tile__tile_id[3] = 5'd3; + assign tile__cgra_id[3] = cgra_id; + assign tile__tile_id[4] = 5'd4; + assign tile__cgra_id[4] = cgra_id; + assign tile__tile_id[5] = 5'd5; + assign tile__cgra_id[5] = cgra_id; + assign tile__tile_id[6] = 5'd6; + assign tile__cgra_id[6] = cgra_id; + assign tile__tile_id[7] = 5'd7; + assign tile__cgra_id[7] = cgra_id; + assign tile__tile_id[8] = 5'd8; + assign tile__cgra_id[8] = cgra_id; + assign tile__tile_id[9] = 5'd9; + assign tile__cgra_id[9] = cgra_id; + assign tile__tile_id[10] = 5'd10; + assign tile__cgra_id[10] = cgra_id; + assign tile__tile_id[11] = 5'd11; + assign tile__cgra_id[11] = cgra_id; + assign tile__tile_id[12] = 5'd12; + assign tile__cgra_id[12] = cgra_id; + assign tile__tile_id[13] = 5'd13; + assign tile__cgra_id[13] = cgra_id; + assign tile__tile_id[14] = 5'd14; + assign tile__cgra_id[14] = cgra_id; + assign tile__tile_id[15] = 5'd15; + assign tile__cgra_id[15] = cgra_id; + assign tile__recv_from_controller_pkt__msg[0] = ctrl_ring__send__msg[0]; + assign ctrl_ring__send__rdy[0] = tile__recv_from_controller_pkt__rdy[0]; + assign tile__recv_from_controller_pkt__val[0] = ctrl_ring__send__val[0]; + assign ctrl_ring__recv__msg[0] = tile__send_to_controller_pkt__msg[0]; + assign tile__send_to_controller_pkt__rdy[0] = ctrl_ring__recv__rdy[0]; + assign ctrl_ring__recv__val[0] = tile__send_to_controller_pkt__val[0]; + assign tile__recv_from_controller_pkt__msg[1] = ctrl_ring__send__msg[1]; + assign ctrl_ring__send__rdy[1] = tile__recv_from_controller_pkt__rdy[1]; + assign tile__recv_from_controller_pkt__val[1] = ctrl_ring__send__val[1]; + assign ctrl_ring__recv__msg[1] = tile__send_to_controller_pkt__msg[1]; + assign tile__send_to_controller_pkt__rdy[1] = ctrl_ring__recv__rdy[1]; + assign ctrl_ring__recv__val[1] = tile__send_to_controller_pkt__val[1]; + assign tile__recv_from_controller_pkt__msg[2] = ctrl_ring__send__msg[2]; + assign ctrl_ring__send__rdy[2] = tile__recv_from_controller_pkt__rdy[2]; + assign tile__recv_from_controller_pkt__val[2] = ctrl_ring__send__val[2]; + assign ctrl_ring__recv__msg[2] = tile__send_to_controller_pkt__msg[2]; + assign tile__send_to_controller_pkt__rdy[2] = ctrl_ring__recv__rdy[2]; + assign ctrl_ring__recv__val[2] = tile__send_to_controller_pkt__val[2]; + assign tile__recv_from_controller_pkt__msg[3] = ctrl_ring__send__msg[3]; + assign ctrl_ring__send__rdy[3] = tile__recv_from_controller_pkt__rdy[3]; + assign tile__recv_from_controller_pkt__val[3] = ctrl_ring__send__val[3]; + assign ctrl_ring__recv__msg[3] = tile__send_to_controller_pkt__msg[3]; + assign tile__send_to_controller_pkt__rdy[3] = ctrl_ring__recv__rdy[3]; + assign ctrl_ring__recv__val[3] = tile__send_to_controller_pkt__val[3]; + assign tile__recv_from_controller_pkt__msg[4] = ctrl_ring__send__msg[4]; + assign ctrl_ring__send__rdy[4] = tile__recv_from_controller_pkt__rdy[4]; + assign tile__recv_from_controller_pkt__val[4] = ctrl_ring__send__val[4]; + assign ctrl_ring__recv__msg[4] = tile__send_to_controller_pkt__msg[4]; + assign tile__send_to_controller_pkt__rdy[4] = ctrl_ring__recv__rdy[4]; + assign ctrl_ring__recv__val[4] = tile__send_to_controller_pkt__val[4]; + assign tile__recv_from_controller_pkt__msg[5] = ctrl_ring__send__msg[5]; + assign ctrl_ring__send__rdy[5] = tile__recv_from_controller_pkt__rdy[5]; + assign tile__recv_from_controller_pkt__val[5] = ctrl_ring__send__val[5]; + assign ctrl_ring__recv__msg[5] = tile__send_to_controller_pkt__msg[5]; + assign tile__send_to_controller_pkt__rdy[5] = ctrl_ring__recv__rdy[5]; + assign ctrl_ring__recv__val[5] = tile__send_to_controller_pkt__val[5]; + assign tile__recv_from_controller_pkt__msg[6] = ctrl_ring__send__msg[6]; + assign ctrl_ring__send__rdy[6] = tile__recv_from_controller_pkt__rdy[6]; + assign tile__recv_from_controller_pkt__val[6] = ctrl_ring__send__val[6]; + assign ctrl_ring__recv__msg[6] = tile__send_to_controller_pkt__msg[6]; + assign tile__send_to_controller_pkt__rdy[6] = ctrl_ring__recv__rdy[6]; + assign ctrl_ring__recv__val[6] = tile__send_to_controller_pkt__val[6]; + assign tile__recv_from_controller_pkt__msg[7] = ctrl_ring__send__msg[7]; + assign ctrl_ring__send__rdy[7] = tile__recv_from_controller_pkt__rdy[7]; + assign tile__recv_from_controller_pkt__val[7] = ctrl_ring__send__val[7]; + assign ctrl_ring__recv__msg[7] = tile__send_to_controller_pkt__msg[7]; + assign tile__send_to_controller_pkt__rdy[7] = ctrl_ring__recv__rdy[7]; + assign ctrl_ring__recv__val[7] = tile__send_to_controller_pkt__val[7]; + assign tile__recv_from_controller_pkt__msg[8] = ctrl_ring__send__msg[8]; + assign ctrl_ring__send__rdy[8] = tile__recv_from_controller_pkt__rdy[8]; + assign tile__recv_from_controller_pkt__val[8] = ctrl_ring__send__val[8]; + assign ctrl_ring__recv__msg[8] = tile__send_to_controller_pkt__msg[8]; + assign tile__send_to_controller_pkt__rdy[8] = ctrl_ring__recv__rdy[8]; + assign ctrl_ring__recv__val[8] = tile__send_to_controller_pkt__val[8]; + assign tile__recv_from_controller_pkt__msg[9] = ctrl_ring__send__msg[9]; + assign ctrl_ring__send__rdy[9] = tile__recv_from_controller_pkt__rdy[9]; + assign tile__recv_from_controller_pkt__val[9] = ctrl_ring__send__val[9]; + assign ctrl_ring__recv__msg[9] = tile__send_to_controller_pkt__msg[9]; + assign tile__send_to_controller_pkt__rdy[9] = ctrl_ring__recv__rdy[9]; + assign ctrl_ring__recv__val[9] = tile__send_to_controller_pkt__val[9]; + assign tile__recv_from_controller_pkt__msg[10] = ctrl_ring__send__msg[10]; + assign ctrl_ring__send__rdy[10] = tile__recv_from_controller_pkt__rdy[10]; + assign tile__recv_from_controller_pkt__val[10] = ctrl_ring__send__val[10]; + assign ctrl_ring__recv__msg[10] = tile__send_to_controller_pkt__msg[10]; + assign tile__send_to_controller_pkt__rdy[10] = ctrl_ring__recv__rdy[10]; + assign ctrl_ring__recv__val[10] = tile__send_to_controller_pkt__val[10]; + assign tile__recv_from_controller_pkt__msg[11] = ctrl_ring__send__msg[11]; + assign ctrl_ring__send__rdy[11] = tile__recv_from_controller_pkt__rdy[11]; + assign tile__recv_from_controller_pkt__val[11] = ctrl_ring__send__val[11]; + assign ctrl_ring__recv__msg[11] = tile__send_to_controller_pkt__msg[11]; + assign tile__send_to_controller_pkt__rdy[11] = ctrl_ring__recv__rdy[11]; + assign ctrl_ring__recv__val[11] = tile__send_to_controller_pkt__val[11]; + assign tile__recv_from_controller_pkt__msg[12] = ctrl_ring__send__msg[12]; + assign ctrl_ring__send__rdy[12] = tile__recv_from_controller_pkt__rdy[12]; + assign tile__recv_from_controller_pkt__val[12] = ctrl_ring__send__val[12]; + assign ctrl_ring__recv__msg[12] = tile__send_to_controller_pkt__msg[12]; + assign tile__send_to_controller_pkt__rdy[12] = ctrl_ring__recv__rdy[12]; + assign ctrl_ring__recv__val[12] = tile__send_to_controller_pkt__val[12]; + assign tile__recv_from_controller_pkt__msg[13] = ctrl_ring__send__msg[13]; + assign ctrl_ring__send__rdy[13] = tile__recv_from_controller_pkt__rdy[13]; + assign tile__recv_from_controller_pkt__val[13] = ctrl_ring__send__val[13]; + assign ctrl_ring__recv__msg[13] = tile__send_to_controller_pkt__msg[13]; + assign tile__send_to_controller_pkt__rdy[13] = ctrl_ring__recv__rdy[13]; + assign ctrl_ring__recv__val[13] = tile__send_to_controller_pkt__val[13]; + assign tile__recv_from_controller_pkt__msg[14] = ctrl_ring__send__msg[14]; + assign ctrl_ring__send__rdy[14] = tile__recv_from_controller_pkt__rdy[14]; + assign tile__recv_from_controller_pkt__val[14] = ctrl_ring__send__val[14]; + assign ctrl_ring__recv__msg[14] = tile__send_to_controller_pkt__msg[14]; + assign tile__send_to_controller_pkt__rdy[14] = ctrl_ring__recv__rdy[14]; + assign ctrl_ring__recv__val[14] = tile__send_to_controller_pkt__val[14]; + assign tile__recv_from_controller_pkt__msg[15] = ctrl_ring__send__msg[15]; + assign ctrl_ring__send__rdy[15] = tile__recv_from_controller_pkt__rdy[15]; + assign tile__recv_from_controller_pkt__val[15] = ctrl_ring__send__val[15]; + assign ctrl_ring__recv__msg[15] = tile__send_to_controller_pkt__msg[15]; + assign tile__send_to_controller_pkt__rdy[15] = ctrl_ring__recv__rdy[15]; + assign ctrl_ring__recv__val[15] = tile__send_to_controller_pkt__val[15]; + assign ctrl_ring__recv__msg[16] = controller__send_to_ctrl_ring_pkt__msg; + assign controller__send_to_ctrl_ring_pkt__rdy = ctrl_ring__recv__rdy[16]; + assign ctrl_ring__recv__val[16] = controller__send_to_ctrl_ring_pkt__val; + assign controller__recv_from_ctrl_ring_pkt__msg = ctrl_ring__send__msg[16]; + assign ctrl_ring__send__rdy[16] = controller__recv_from_ctrl_ring_pkt__rdy; + assign controller__recv_from_ctrl_ring_pkt__val = ctrl_ring__send__val[16]; + assign tile__recv_data__msg[4][1] = tile__send_data__msg[0][0]; + assign tile__send_data__rdy[0][0] = tile__recv_data__rdy[4][1]; + assign tile__recv_data__val[4][1] = tile__send_data__val[0][0]; + assign tile__recv_data__msg[1][2] = tile__send_data__msg[0][3]; + assign tile__send_data__rdy[0][3] = tile__recv_data__rdy[1][2]; + assign tile__recv_data__val[1][2] = tile__send_data__val[0][3]; + assign send_data_on_boundary_south__msg[0] = tile__send_data__msg[0][1]; + assign tile__send_data__rdy[0][1] = send_data_on_boundary_south__rdy[0]; + assign send_data_on_boundary_south__val[0] = tile__send_data__val[0][1]; + assign tile__recv_data__msg[0][1] = recv_data_on_boundary_south__msg[0]; + assign recv_data_on_boundary_south__rdy[0] = tile__recv_data__rdy[0][1]; + assign tile__recv_data__val[0][1] = recv_data_on_boundary_south__val[0]; + assign send_data_on_boundary_west__msg[0] = tile__send_data__msg[0][2]; + assign tile__send_data__rdy[0][2] = send_data_on_boundary_west__rdy[0]; + assign send_data_on_boundary_west__val[0] = tile__send_data__val[0][2]; + assign tile__recv_data__msg[0][2] = recv_data_on_boundary_west__msg[0]; + assign recv_data_on_boundary_west__rdy[0] = tile__recv_data__rdy[0][2]; + assign tile__recv_data__val[0][2] = recv_data_on_boundary_west__val[0]; + assign data_mem__recv_raddr__msg[0] = tile__to_mem_raddr__msg[0]; + assign tile__to_mem_raddr__rdy[0] = data_mem__recv_raddr__rdy[0]; + assign data_mem__recv_raddr__val[0] = tile__to_mem_raddr__val[0]; + assign tile__from_mem_rdata__msg[0] = data_mem__send_rdata__msg[0]; + assign data_mem__send_rdata__rdy[0] = tile__from_mem_rdata__rdy[0]; + assign tile__from_mem_rdata__val[0] = data_mem__send_rdata__val[0]; + assign data_mem__recv_waddr__msg[0] = tile__to_mem_waddr__msg[0]; + assign tile__to_mem_waddr__rdy[0] = data_mem__recv_waddr__rdy[0]; + assign data_mem__recv_waddr__val[0] = tile__to_mem_waddr__val[0]; + assign data_mem__recv_wdata__msg[0] = tile__to_mem_wdata__msg[0]; + assign tile__to_mem_wdata__rdy[0] = data_mem__recv_wdata__rdy[0]; + assign data_mem__recv_wdata__val[0] = tile__to_mem_wdata__val[0]; + assign tile__recv_data__msg[5][1] = tile__send_data__msg[1][0]; + assign tile__send_data__rdy[1][0] = tile__recv_data__rdy[5][1]; + assign tile__recv_data__val[5][1] = tile__send_data__val[1][0]; + assign tile__recv_data__msg[0][3] = tile__send_data__msg[1][2]; + assign tile__send_data__rdy[1][2] = tile__recv_data__rdy[0][3]; + assign tile__recv_data__val[0][3] = tile__send_data__val[1][2]; + assign tile__recv_data__msg[2][2] = tile__send_data__msg[1][3]; + assign tile__send_data__rdy[1][3] = tile__recv_data__rdy[2][2]; + assign tile__recv_data__val[2][2] = tile__send_data__val[1][3]; + assign send_data_on_boundary_south__msg[1] = tile__send_data__msg[1][1]; + assign tile__send_data__rdy[1][1] = send_data_on_boundary_south__rdy[1]; + assign send_data_on_boundary_south__val[1] = tile__send_data__val[1][1]; + assign tile__recv_data__msg[1][1] = recv_data_on_boundary_south__msg[1]; + assign recv_data_on_boundary_south__rdy[1] = tile__recv_data__rdy[1][1]; + assign tile__recv_data__val[1][1] = recv_data_on_boundary_south__val[1]; + assign data_mem__recv_raddr__msg[1] = tile__to_mem_raddr__msg[1]; + assign tile__to_mem_raddr__rdy[1] = data_mem__recv_raddr__rdy[1]; + assign data_mem__recv_raddr__val[1] = tile__to_mem_raddr__val[1]; + assign tile__from_mem_rdata__msg[1] = data_mem__send_rdata__msg[1]; + assign data_mem__send_rdata__rdy[1] = tile__from_mem_rdata__rdy[1]; + assign tile__from_mem_rdata__val[1] = data_mem__send_rdata__val[1]; + assign data_mem__recv_waddr__msg[1] = tile__to_mem_waddr__msg[1]; + assign tile__to_mem_waddr__rdy[1] = data_mem__recv_waddr__rdy[1]; + assign data_mem__recv_waddr__val[1] = tile__to_mem_waddr__val[1]; + assign data_mem__recv_wdata__msg[1] = tile__to_mem_wdata__msg[1]; + assign tile__to_mem_wdata__rdy[1] = data_mem__recv_wdata__rdy[1]; + assign data_mem__recv_wdata__val[1] = tile__to_mem_wdata__val[1]; + assign tile__recv_data__msg[6][1] = tile__send_data__msg[2][0]; + assign tile__send_data__rdy[2][0] = tile__recv_data__rdy[6][1]; + assign tile__recv_data__val[6][1] = tile__send_data__val[2][0]; + assign tile__recv_data__msg[1][3] = tile__send_data__msg[2][2]; + assign tile__send_data__rdy[2][2] = tile__recv_data__rdy[1][3]; + assign tile__recv_data__val[1][3] = tile__send_data__val[2][2]; + assign tile__recv_data__msg[3][2] = tile__send_data__msg[2][3]; + assign tile__send_data__rdy[2][3] = tile__recv_data__rdy[3][2]; + assign tile__recv_data__val[3][2] = tile__send_data__val[2][3]; + assign send_data_on_boundary_south__msg[2] = tile__send_data__msg[2][1]; + assign tile__send_data__rdy[2][1] = send_data_on_boundary_south__rdy[2]; + assign send_data_on_boundary_south__val[2] = tile__send_data__val[2][1]; + assign tile__recv_data__msg[2][1] = recv_data_on_boundary_south__msg[2]; + assign recv_data_on_boundary_south__rdy[2] = tile__recv_data__rdy[2][1]; + assign tile__recv_data__val[2][1] = recv_data_on_boundary_south__val[2]; + assign data_mem__recv_raddr__msg[2] = tile__to_mem_raddr__msg[2]; + assign tile__to_mem_raddr__rdy[2] = data_mem__recv_raddr__rdy[2]; + assign data_mem__recv_raddr__val[2] = tile__to_mem_raddr__val[2]; + assign tile__from_mem_rdata__msg[2] = data_mem__send_rdata__msg[2]; + assign data_mem__send_rdata__rdy[2] = tile__from_mem_rdata__rdy[2]; + assign tile__from_mem_rdata__val[2] = data_mem__send_rdata__val[2]; + assign data_mem__recv_waddr__msg[2] = tile__to_mem_waddr__msg[2]; + assign tile__to_mem_waddr__rdy[2] = data_mem__recv_waddr__rdy[2]; + assign data_mem__recv_waddr__val[2] = tile__to_mem_waddr__val[2]; + assign data_mem__recv_wdata__msg[2] = tile__to_mem_wdata__msg[2]; + assign tile__to_mem_wdata__rdy[2] = data_mem__recv_wdata__rdy[2]; + assign data_mem__recv_wdata__val[2] = tile__to_mem_wdata__val[2]; + assign tile__recv_data__msg[7][1] = tile__send_data__msg[3][0]; + assign tile__send_data__rdy[3][0] = tile__recv_data__rdy[7][1]; + assign tile__recv_data__val[7][1] = tile__send_data__val[3][0]; + assign tile__recv_data__msg[2][3] = tile__send_data__msg[3][2]; + assign tile__send_data__rdy[3][2] = tile__recv_data__rdy[2][3]; + assign tile__recv_data__val[2][3] = tile__send_data__val[3][2]; + assign send_data_on_boundary_south__msg[3] = tile__send_data__msg[3][1]; + assign tile__send_data__rdy[3][1] = send_data_on_boundary_south__rdy[3]; + assign send_data_on_boundary_south__val[3] = tile__send_data__val[3][1]; + assign tile__recv_data__msg[3][1] = recv_data_on_boundary_south__msg[3]; + assign recv_data_on_boundary_south__rdy[3] = tile__recv_data__rdy[3][1]; + assign tile__recv_data__val[3][1] = recv_data_on_boundary_south__val[3]; + assign send_data_on_boundary_east__msg[0] = tile__send_data__msg[3][3]; + assign tile__send_data__rdy[3][3] = send_data_on_boundary_east__rdy[0]; + assign send_data_on_boundary_east__val[0] = tile__send_data__val[3][3]; + assign tile__recv_data__msg[3][3] = recv_data_on_boundary_east__msg[0]; + assign recv_data_on_boundary_east__rdy[0] = tile__recv_data__rdy[3][3]; + assign tile__recv_data__val[3][3] = recv_data_on_boundary_east__val[0]; + assign data_mem__recv_raddr__msg[3] = tile__to_mem_raddr__msg[3]; + assign tile__to_mem_raddr__rdy[3] = data_mem__recv_raddr__rdy[3]; + assign data_mem__recv_raddr__val[3] = tile__to_mem_raddr__val[3]; + assign tile__from_mem_rdata__msg[3] = data_mem__send_rdata__msg[3]; + assign data_mem__send_rdata__rdy[3] = tile__from_mem_rdata__rdy[3]; + assign tile__from_mem_rdata__val[3] = data_mem__send_rdata__val[3]; + assign data_mem__recv_waddr__msg[3] = tile__to_mem_waddr__msg[3]; + assign tile__to_mem_waddr__rdy[3] = data_mem__recv_waddr__rdy[3]; + assign data_mem__recv_waddr__val[3] = tile__to_mem_waddr__val[3]; + assign data_mem__recv_wdata__msg[3] = tile__to_mem_wdata__msg[3]; + assign tile__to_mem_wdata__rdy[3] = data_mem__recv_wdata__rdy[3]; + assign data_mem__recv_wdata__val[3] = tile__to_mem_wdata__val[3]; + assign tile__recv_data__msg[0][0] = tile__send_data__msg[4][1]; + assign tile__send_data__rdy[4][1] = tile__recv_data__rdy[0][0]; + assign tile__recv_data__val[0][0] = tile__send_data__val[4][1]; + assign tile__recv_data__msg[8][1] = tile__send_data__msg[4][0]; + assign tile__send_data__rdy[4][0] = tile__recv_data__rdy[8][1]; + assign tile__recv_data__val[8][1] = tile__send_data__val[4][0]; + assign tile__recv_data__msg[5][2] = tile__send_data__msg[4][3]; + assign tile__send_data__rdy[4][3] = tile__recv_data__rdy[5][2]; + assign tile__recv_data__val[5][2] = tile__send_data__val[4][3]; + assign send_data_on_boundary_west__msg[1] = tile__send_data__msg[4][2]; + assign tile__send_data__rdy[4][2] = send_data_on_boundary_west__rdy[1]; + assign send_data_on_boundary_west__val[1] = tile__send_data__val[4][2]; + assign tile__recv_data__msg[4][2] = recv_data_on_boundary_west__msg[1]; + assign recv_data_on_boundary_west__rdy[1] = tile__recv_data__rdy[4][2]; + assign tile__recv_data__val[4][2] = recv_data_on_boundary_west__val[1]; + assign data_mem__recv_raddr__msg[4] = tile__to_mem_raddr__msg[4]; + assign tile__to_mem_raddr__rdy[4] = data_mem__recv_raddr__rdy[4]; + assign data_mem__recv_raddr__val[4] = tile__to_mem_raddr__val[4]; + assign tile__from_mem_rdata__msg[4] = data_mem__send_rdata__msg[4]; + assign data_mem__send_rdata__rdy[4] = tile__from_mem_rdata__rdy[4]; + assign tile__from_mem_rdata__val[4] = data_mem__send_rdata__val[4]; + assign data_mem__recv_waddr__msg[4] = tile__to_mem_waddr__msg[4]; + assign tile__to_mem_waddr__rdy[4] = data_mem__recv_waddr__rdy[4]; + assign data_mem__recv_waddr__val[4] = tile__to_mem_waddr__val[4]; + assign data_mem__recv_wdata__msg[4] = tile__to_mem_wdata__msg[4]; + assign tile__to_mem_wdata__rdy[4] = data_mem__recv_wdata__rdy[4]; + assign data_mem__recv_wdata__val[4] = tile__to_mem_wdata__val[4]; + assign tile__recv_data__msg[1][0] = tile__send_data__msg[5][1]; + assign tile__send_data__rdy[5][1] = tile__recv_data__rdy[1][0]; + assign tile__recv_data__val[1][0] = tile__send_data__val[5][1]; + assign tile__recv_data__msg[9][1] = tile__send_data__msg[5][0]; + assign tile__send_data__rdy[5][0] = tile__recv_data__rdy[9][1]; + assign tile__recv_data__val[9][1] = tile__send_data__val[5][0]; + assign tile__recv_data__msg[4][3] = tile__send_data__msg[5][2]; + assign tile__send_data__rdy[5][2] = tile__recv_data__rdy[4][3]; + assign tile__recv_data__val[4][3] = tile__send_data__val[5][2]; + assign tile__recv_data__msg[6][2] = tile__send_data__msg[5][3]; + assign tile__send_data__rdy[5][3] = tile__recv_data__rdy[6][2]; + assign tile__recv_data__val[6][2] = tile__send_data__val[5][3]; + assign tile__to_mem_raddr__rdy[5] = 1'd0; + assign tile__from_mem_rdata__val[5] = 1'd0; + assign tile__from_mem_rdata__msg[5] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[5] = 1'd0; + assign tile__to_mem_wdata__rdy[5] = 1'd0; + assign tile__recv_data__msg[2][0] = tile__send_data__msg[6][1]; + assign tile__send_data__rdy[6][1] = tile__recv_data__rdy[2][0]; + assign tile__recv_data__val[2][0] = tile__send_data__val[6][1]; + assign tile__recv_data__msg[10][1] = tile__send_data__msg[6][0]; + assign tile__send_data__rdy[6][0] = tile__recv_data__rdy[10][1]; + assign tile__recv_data__val[10][1] = tile__send_data__val[6][0]; + assign tile__recv_data__msg[5][3] = tile__send_data__msg[6][2]; + assign tile__send_data__rdy[6][2] = tile__recv_data__rdy[5][3]; + assign tile__recv_data__val[5][3] = tile__send_data__val[6][2]; + assign tile__recv_data__msg[7][2] = tile__send_data__msg[6][3]; + assign tile__send_data__rdy[6][3] = tile__recv_data__rdy[7][2]; + assign tile__recv_data__val[7][2] = tile__send_data__val[6][3]; + assign tile__to_mem_raddr__rdy[6] = 1'd0; + assign tile__from_mem_rdata__val[6] = 1'd0; + assign tile__from_mem_rdata__msg[6] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[6] = 1'd0; + assign tile__to_mem_wdata__rdy[6] = 1'd0; + assign tile__recv_data__msg[3][0] = tile__send_data__msg[7][1]; + assign tile__send_data__rdy[7][1] = tile__recv_data__rdy[3][0]; + assign tile__recv_data__val[3][0] = tile__send_data__val[7][1]; + assign tile__recv_data__msg[11][1] = tile__send_data__msg[7][0]; + assign tile__send_data__rdy[7][0] = tile__recv_data__rdy[11][1]; + assign tile__recv_data__val[11][1] = tile__send_data__val[7][0]; + assign tile__recv_data__msg[6][3] = tile__send_data__msg[7][2]; + assign tile__send_data__rdy[7][2] = tile__recv_data__rdy[6][3]; + assign tile__recv_data__val[6][3] = tile__send_data__val[7][2]; + assign send_data_on_boundary_east__msg[1] = tile__send_data__msg[7][3]; + assign tile__send_data__rdy[7][3] = send_data_on_boundary_east__rdy[1]; + assign send_data_on_boundary_east__val[1] = tile__send_data__val[7][3]; + assign tile__recv_data__msg[7][3] = recv_data_on_boundary_east__msg[1]; + assign recv_data_on_boundary_east__rdy[1] = tile__recv_data__rdy[7][3]; + assign tile__recv_data__val[7][3] = recv_data_on_boundary_east__val[1]; + assign tile__to_mem_raddr__rdy[7] = 1'd0; + assign tile__from_mem_rdata__val[7] = 1'd0; + assign tile__from_mem_rdata__msg[7] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[7] = 1'd0; + assign tile__to_mem_wdata__rdy[7] = 1'd0; + assign tile__recv_data__msg[4][0] = tile__send_data__msg[8][1]; + assign tile__send_data__rdy[8][1] = tile__recv_data__rdy[4][0]; + assign tile__recv_data__val[4][0] = tile__send_data__val[8][1]; + assign tile__recv_data__msg[12][1] = tile__send_data__msg[8][0]; + assign tile__send_data__rdy[8][0] = tile__recv_data__rdy[12][1]; + assign tile__recv_data__val[12][1] = tile__send_data__val[8][0]; + assign tile__recv_data__msg[9][2] = tile__send_data__msg[8][3]; + assign tile__send_data__rdy[8][3] = tile__recv_data__rdy[9][2]; + assign tile__recv_data__val[9][2] = tile__send_data__val[8][3]; + assign send_data_on_boundary_west__msg[2] = tile__send_data__msg[8][2]; + assign tile__send_data__rdy[8][2] = send_data_on_boundary_west__rdy[2]; + assign send_data_on_boundary_west__val[2] = tile__send_data__val[8][2]; + assign tile__recv_data__msg[8][2] = recv_data_on_boundary_west__msg[2]; + assign recv_data_on_boundary_west__rdy[2] = tile__recv_data__rdy[8][2]; + assign tile__recv_data__val[8][2] = recv_data_on_boundary_west__val[2]; + assign data_mem__recv_raddr__msg[5] = tile__to_mem_raddr__msg[8]; + assign tile__to_mem_raddr__rdy[8] = data_mem__recv_raddr__rdy[5]; + assign data_mem__recv_raddr__val[5] = tile__to_mem_raddr__val[8]; + assign tile__from_mem_rdata__msg[8] = data_mem__send_rdata__msg[5]; + assign data_mem__send_rdata__rdy[5] = tile__from_mem_rdata__rdy[8]; + assign tile__from_mem_rdata__val[8] = data_mem__send_rdata__val[5]; + assign data_mem__recv_waddr__msg[5] = tile__to_mem_waddr__msg[8]; + assign tile__to_mem_waddr__rdy[8] = data_mem__recv_waddr__rdy[5]; + assign data_mem__recv_waddr__val[5] = tile__to_mem_waddr__val[8]; + assign data_mem__recv_wdata__msg[5] = tile__to_mem_wdata__msg[8]; + assign tile__to_mem_wdata__rdy[8] = data_mem__recv_wdata__rdy[5]; + assign data_mem__recv_wdata__val[5] = tile__to_mem_wdata__val[8]; + assign tile__recv_data__msg[5][0] = tile__send_data__msg[9][1]; + assign tile__send_data__rdy[9][1] = tile__recv_data__rdy[5][0]; + assign tile__recv_data__val[5][0] = tile__send_data__val[9][1]; + assign tile__recv_data__msg[13][1] = tile__send_data__msg[9][0]; + assign tile__send_data__rdy[9][0] = tile__recv_data__rdy[13][1]; + assign tile__recv_data__val[13][1] = tile__send_data__val[9][0]; + assign tile__recv_data__msg[8][3] = tile__send_data__msg[9][2]; + assign tile__send_data__rdy[9][2] = tile__recv_data__rdy[8][3]; + assign tile__recv_data__val[8][3] = tile__send_data__val[9][2]; + assign tile__recv_data__msg[10][2] = tile__send_data__msg[9][3]; + assign tile__send_data__rdy[9][3] = tile__recv_data__rdy[10][2]; + assign tile__recv_data__val[10][2] = tile__send_data__val[9][3]; + assign tile__to_mem_raddr__rdy[9] = 1'd0; + assign tile__from_mem_rdata__val[9] = 1'd0; + assign tile__from_mem_rdata__msg[9] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[9] = 1'd0; + assign tile__to_mem_wdata__rdy[9] = 1'd0; + assign tile__recv_data__msg[6][0] = tile__send_data__msg[10][1]; + assign tile__send_data__rdy[10][1] = tile__recv_data__rdy[6][0]; + assign tile__recv_data__val[6][0] = tile__send_data__val[10][1]; + assign tile__recv_data__msg[14][1] = tile__send_data__msg[10][0]; + assign tile__send_data__rdy[10][0] = tile__recv_data__rdy[14][1]; + assign tile__recv_data__val[14][1] = tile__send_data__val[10][0]; + assign tile__recv_data__msg[9][3] = tile__send_data__msg[10][2]; + assign tile__send_data__rdy[10][2] = tile__recv_data__rdy[9][3]; + assign tile__recv_data__val[9][3] = tile__send_data__val[10][2]; + assign tile__recv_data__msg[11][2] = tile__send_data__msg[10][3]; + assign tile__send_data__rdy[10][3] = tile__recv_data__rdy[11][2]; + assign tile__recv_data__val[11][2] = tile__send_data__val[10][3]; + assign tile__to_mem_raddr__rdy[10] = 1'd0; + assign tile__from_mem_rdata__val[10] = 1'd0; + assign tile__from_mem_rdata__msg[10] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[10] = 1'd0; + assign tile__to_mem_wdata__rdy[10] = 1'd0; + assign tile__recv_data__msg[7][0] = tile__send_data__msg[11][1]; + assign tile__send_data__rdy[11][1] = tile__recv_data__rdy[7][0]; + assign tile__recv_data__val[7][0] = tile__send_data__val[11][1]; + assign tile__recv_data__msg[15][1] = tile__send_data__msg[11][0]; + assign tile__send_data__rdy[11][0] = tile__recv_data__rdy[15][1]; + assign tile__recv_data__val[15][1] = tile__send_data__val[11][0]; + assign tile__recv_data__msg[10][3] = tile__send_data__msg[11][2]; + assign tile__send_data__rdy[11][2] = tile__recv_data__rdy[10][3]; + assign tile__recv_data__val[10][3] = tile__send_data__val[11][2]; + assign send_data_on_boundary_east__msg[2] = tile__send_data__msg[11][3]; + assign tile__send_data__rdy[11][3] = send_data_on_boundary_east__rdy[2]; + assign send_data_on_boundary_east__val[2] = tile__send_data__val[11][3]; + assign tile__recv_data__msg[11][3] = recv_data_on_boundary_east__msg[2]; + assign recv_data_on_boundary_east__rdy[2] = tile__recv_data__rdy[11][3]; + assign tile__recv_data__val[11][3] = recv_data_on_boundary_east__val[2]; + assign tile__to_mem_raddr__rdy[11] = 1'd0; + assign tile__from_mem_rdata__val[11] = 1'd0; + assign tile__from_mem_rdata__msg[11] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[11] = 1'd0; + assign tile__to_mem_wdata__rdy[11] = 1'd0; + assign tile__recv_data__msg[8][0] = tile__send_data__msg[12][1]; + assign tile__send_data__rdy[12][1] = tile__recv_data__rdy[8][0]; + assign tile__recv_data__val[8][0] = tile__send_data__val[12][1]; + assign tile__recv_data__msg[13][2] = tile__send_data__msg[12][3]; + assign tile__send_data__rdy[12][3] = tile__recv_data__rdy[13][2]; + assign tile__recv_data__val[13][2] = tile__send_data__val[12][3]; + assign send_data_on_boundary_north__msg[0] = tile__send_data__msg[12][0]; + assign tile__send_data__rdy[12][0] = send_data_on_boundary_north__rdy[0]; + assign send_data_on_boundary_north__val[0] = tile__send_data__val[12][0]; + assign tile__recv_data__msg[12][0] = recv_data_on_boundary_north__msg[0]; + assign recv_data_on_boundary_north__rdy[0] = tile__recv_data__rdy[12][0]; + assign tile__recv_data__val[12][0] = recv_data_on_boundary_north__val[0]; + assign send_data_on_boundary_west__msg[3] = tile__send_data__msg[12][2]; + assign tile__send_data__rdy[12][2] = send_data_on_boundary_west__rdy[3]; + assign send_data_on_boundary_west__val[3] = tile__send_data__val[12][2]; + assign tile__recv_data__msg[12][2] = recv_data_on_boundary_west__msg[3]; + assign recv_data_on_boundary_west__rdy[3] = tile__recv_data__rdy[12][2]; + assign tile__recv_data__val[12][2] = recv_data_on_boundary_west__val[3]; + assign data_mem__recv_raddr__msg[6] = tile__to_mem_raddr__msg[12]; + assign tile__to_mem_raddr__rdy[12] = data_mem__recv_raddr__rdy[6]; + assign data_mem__recv_raddr__val[6] = tile__to_mem_raddr__val[12]; + assign tile__from_mem_rdata__msg[12] = data_mem__send_rdata__msg[6]; + assign data_mem__send_rdata__rdy[6] = tile__from_mem_rdata__rdy[12]; + assign tile__from_mem_rdata__val[12] = data_mem__send_rdata__val[6]; + assign data_mem__recv_waddr__msg[6] = tile__to_mem_waddr__msg[12]; + assign tile__to_mem_waddr__rdy[12] = data_mem__recv_waddr__rdy[6]; + assign data_mem__recv_waddr__val[6] = tile__to_mem_waddr__val[12]; + assign data_mem__recv_wdata__msg[6] = tile__to_mem_wdata__msg[12]; + assign tile__to_mem_wdata__rdy[12] = data_mem__recv_wdata__rdy[6]; + assign data_mem__recv_wdata__val[6] = tile__to_mem_wdata__val[12]; + assign tile__recv_data__msg[9][0] = tile__send_data__msg[13][1]; + assign tile__send_data__rdy[13][1] = tile__recv_data__rdy[9][0]; + assign tile__recv_data__val[9][0] = tile__send_data__val[13][1]; + assign tile__recv_data__msg[12][3] = tile__send_data__msg[13][2]; + assign tile__send_data__rdy[13][2] = tile__recv_data__rdy[12][3]; + assign tile__recv_data__val[12][3] = tile__send_data__val[13][2]; + assign tile__recv_data__msg[14][2] = tile__send_data__msg[13][3]; + assign tile__send_data__rdy[13][3] = tile__recv_data__rdy[14][2]; + assign tile__recv_data__val[14][2] = tile__send_data__val[13][3]; + assign send_data_on_boundary_north__msg[1] = tile__send_data__msg[13][0]; + assign tile__send_data__rdy[13][0] = send_data_on_boundary_north__rdy[1]; + assign send_data_on_boundary_north__val[1] = tile__send_data__val[13][0]; + assign tile__recv_data__msg[13][0] = recv_data_on_boundary_north__msg[1]; + assign recv_data_on_boundary_north__rdy[1] = tile__recv_data__rdy[13][0]; + assign tile__recv_data__val[13][0] = recv_data_on_boundary_north__val[1]; + assign tile__to_mem_raddr__rdy[13] = 1'd0; + assign tile__from_mem_rdata__val[13] = 1'd0; + assign tile__from_mem_rdata__msg[13] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[13] = 1'd0; + assign tile__to_mem_wdata__rdy[13] = 1'd0; + assign tile__recv_data__msg[10][0] = tile__send_data__msg[14][1]; + assign tile__send_data__rdy[14][1] = tile__recv_data__rdy[10][0]; + assign tile__recv_data__val[10][0] = tile__send_data__val[14][1]; + assign tile__recv_data__msg[13][3] = tile__send_data__msg[14][2]; + assign tile__send_data__rdy[14][2] = tile__recv_data__rdy[13][3]; + assign tile__recv_data__val[13][3] = tile__send_data__val[14][2]; + assign tile__recv_data__msg[15][2] = tile__send_data__msg[14][3]; + assign tile__send_data__rdy[14][3] = tile__recv_data__rdy[15][2]; + assign tile__recv_data__val[15][2] = tile__send_data__val[14][3]; + assign send_data_on_boundary_north__msg[2] = tile__send_data__msg[14][0]; + assign tile__send_data__rdy[14][0] = send_data_on_boundary_north__rdy[2]; + assign send_data_on_boundary_north__val[2] = tile__send_data__val[14][0]; + assign tile__recv_data__msg[14][0] = recv_data_on_boundary_north__msg[2]; + assign recv_data_on_boundary_north__rdy[2] = tile__recv_data__rdy[14][0]; + assign tile__recv_data__val[14][0] = recv_data_on_boundary_north__val[2]; + assign tile__to_mem_raddr__rdy[14] = 1'd0; + assign tile__from_mem_rdata__val[14] = 1'd0; + assign tile__from_mem_rdata__msg[14] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[14] = 1'd0; + assign tile__to_mem_wdata__rdy[14] = 1'd0; + assign tile__recv_data__msg[11][0] = tile__send_data__msg[15][1]; + assign tile__send_data__rdy[15][1] = tile__recv_data__rdy[11][0]; + assign tile__recv_data__val[11][0] = tile__send_data__val[15][1]; + assign tile__recv_data__msg[14][3] = tile__send_data__msg[15][2]; + assign tile__send_data__rdy[15][2] = tile__recv_data__rdy[14][3]; + assign tile__recv_data__val[14][3] = tile__send_data__val[15][2]; + assign send_data_on_boundary_north__msg[3] = tile__send_data__msg[15][0]; + assign tile__send_data__rdy[15][0] = send_data_on_boundary_north__rdy[3]; + assign send_data_on_boundary_north__val[3] = tile__send_data__val[15][0]; + assign tile__recv_data__msg[15][0] = recv_data_on_boundary_north__msg[3]; + assign recv_data_on_boundary_north__rdy[3] = tile__recv_data__rdy[15][0]; + assign tile__recv_data__val[15][0] = recv_data_on_boundary_north__val[3]; + assign send_data_on_boundary_east__msg[3] = tile__send_data__msg[15][3]; + assign tile__send_data__rdy[15][3] = send_data_on_boundary_east__rdy[3]; + assign send_data_on_boundary_east__val[3] = tile__send_data__val[15][3]; + assign tile__recv_data__msg[15][3] = recv_data_on_boundary_east__msg[3]; + assign recv_data_on_boundary_east__rdy[3] = tile__recv_data__rdy[15][3]; + assign tile__recv_data__val[15][3] = recv_data_on_boundary_east__val[3]; + assign tile__to_mem_raddr__rdy[15] = 1'd0; + assign tile__from_mem_rdata__val[15] = 1'd0; + assign tile__from_mem_rdata__msg[15] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign tile__to_mem_waddr__rdy[15] = 1'd0; + assign tile__to_mem_wdata__rdy[15] = 1'd0; + +endmodule + + +// PyMTL Component InputUnitRTL Definition +// Full name: InputUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_NormalQueueRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py + +module InputUnitRTL__8ea2cb5fb7536c6c +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + //------------------------------------------------------------- + // Component queue + //------------------------------------------------------------- + + logic [0:0] queue__clk; + logic [1:0] queue__count; + logic [0:0] queue__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__recv__msg; + logic [0:0] queue__recv__rdy; + logic [0:0] queue__recv__val; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__send__msg; + logic [0:0] queue__send__rdy; + logic [0:0] queue__send__val; + + NormalQueueRTL__c7280ffb0786127e queue + ( + .clk( queue__clk ), + .count( queue__count ), + .reset( queue__reset ), + .recv__msg( queue__recv__msg ), + .recv__rdy( queue__recv__rdy ), + .recv__val( queue__recv__val ), + .send__msg( queue__send__msg ), + .send__rdy( queue__send__rdy ), + .send__val( queue__send__val ) + ); + + //------------------------------------------------------------- + // End of component queue + //------------------------------------------------------------- + + assign queue__clk = clk; + assign queue__reset = reset; + assign queue__recv__msg = recv__msg; + assign recv__rdy = queue__recv__rdy; + assign queue__recv__val = recv__val; + assign send__msg = queue__send__msg; + assign queue__send__rdy = send__rdy; + assign send__val = queue__send__val; + +endmodule + + +// PyMTL Component OutputUnitRTL Definition +// Full name: OutputUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_None +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py + +module OutputUnitRTL__e43ef936c3b236b0 +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + + assign send__msg = recv__msg; + assign recv__rdy = send__rdy; + assign send__val = recv__val; + +endmodule + + +// PyMTL Component DORYMeshRouteUnitRTL Definition +// Full name: DORYMeshRouteUnitRTL__MsgType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__num_outports_5 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py + +module DORYMeshRouteUnitRTL__cf2d804ed36fdf23 +( + input logic [0:0] clk , + input MeshPosition_2x2__pos_x_1__pos_y_1 pos , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , + output logic [0:0] recv__rdy , + input logic [0:0] recv__val , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:4] , + input logic [0:0] send__rdy [0:4] , + output logic [0:0] send__val [0:4] +); + localparam logic [2:0] __const__num_outports_at_up_ru_routing = 3'd5; + localparam logic [2:0] __const__SELF = 3'd4; + localparam logic [0:0] __const__SOUTH = 1'd1; + localparam logic [0:0] __const__NORTH = 1'd0; + localparam logic [1:0] __const__WEST = 2'd2; + localparam logic [1:0] __const__EAST = 2'd3; + logic [2:0] out_dir; + logic [4:0] send_rdy; + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py:57 + // @update + // def up_ru_recv_rdy(): + // s.recv.rdy @= s.send_rdy[ s.out_dir ] + + always_comb begin : up_ru_recv_rdy + recv__rdy = send_rdy[out_dir]; + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py:38 + // @update + // def up_ru_routing(): + // s.out_dir @= Bits3(0) + // for i in range( num_outports ): + // s.send[i].val @= Bits1(0) + // + // if s.recv.val: + // if (s.pos.pos_x == s.recv.msg.dst_x) & (s.pos.pos_y == s.recv.msg.dst_y): + // s.out_dir @= SELF + // elif s.recv.msg.dst_y < s.pos.pos_y: + // s.out_dir @= SOUTH + // elif s.recv.msg.dst_y > s.pos.pos_y: + // s.out_dir @= NORTH + // elif s.recv.msg.dst_x < s.pos.pos_x: + // s.out_dir @= WEST + // else: + // s.out_dir @= EAST + // s.send[ s.out_dir ].val @= Bits1(1) + + always_comb begin : up_ru_routing + out_dir = 3'd0; + for ( int unsigned i = 1'd0; i < 3'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) + send__val[3'(i)] = 1'd0; + if ( recv__val ) begin + if ( ( pos.pos_x == recv__msg.dst_x ) & ( pos.pos_y == recv__msg.dst_y ) ) begin + out_dir = 3'( __const__SELF ); + end + else if ( recv__msg.dst_y < pos.pos_y ) begin + out_dir = 3'( __const__SOUTH ); + end + else if ( recv__msg.dst_y > pos.pos_y ) begin + out_dir = 3'( __const__NORTH ); + end + else if ( recv__msg.dst_x < pos.pos_x ) begin + out_dir = 3'( __const__WEST ); + end + else + out_dir = 3'( __const__EAST ); + send__val[out_dir] = 1'd1; + end + end + + assign send__msg[0] = recv__msg; + assign send_rdy[0:0] = send__rdy[0]; + assign send__msg[1] = recv__msg; + assign send_rdy[1:1] = send__rdy[1]; + assign send__msg[2] = recv__msg; + assign send_rdy[2:2] = send__rdy[2]; + assign send__msg[3] = recv__msg; + assign send_rdy[3:3] = send__rdy[3]; + assign send__msg[4] = recv__msg; + assign send_rdy[4:4] = send__rdy[4]; + +endmodule + + +// PyMTL Component RegEnRst Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py + +module RegEnRst__Type_Bits5__reset_value_1 +( + input logic [0:0] clk , + input logic [0:0] en , + input logic [4:0] in_ , + output logic [4:0] out , + input logic [0:0] reset +); + localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 + // @update_ff + // def up_regenrst(): + // if s.reset: s.out <<= reset_value + // elif s.en: s.out <<= s.in_ + + always_ff @(posedge clk) begin : up_regenrst + if ( reset ) begin + out <= 5'( __const__reset_value_at_up_regenrst ); + end + else if ( en ) begin + out <= in_; + end + end + +endmodule + + +// PyMTL Component RoundRobinArbiterEn Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py + +module RoundRobinArbiterEn__nreqs_5 +( + input logic [0:0] clk , + input logic [0:0] en , + output logic [4:0] grants , + input logic [4:0] reqs , + input logic [0:0] reset +); + localparam logic [2:0] __const__nreqs_at_comb_reqs_int = 3'd5; + localparam logic [3:0] __const__nreqsX2_at_comb_reqs_int = 4'd10; + localparam logic [2:0] __const__nreqs_at_comb_grants = 3'd5; + localparam logic [2:0] __const__nreqs_at_comb_priority_int = 3'd5; + localparam logic [3:0] __const__nreqsX2_at_comb_priority_int = 4'd10; + localparam logic [3:0] __const__nreqsX2_at_comb_kills = 4'd10; + localparam logic [3:0] __const__nreqsX2_at_comb_grants_int = 4'd10; + logic [9:0] grants_int; + logic [10:0] kills; + logic [0:0] priority_en; + logic [9:0] priority_int; + logic [9:0] reqs_int; + //------------------------------------------------------------- + // Component priority_reg + //------------------------------------------------------------- + + logic [0:0] priority_reg__clk; + logic [0:0] priority_reg__en; + logic [4:0] priority_reg__in_; + logic [4:0] priority_reg__out; + logic [0:0] priority_reg__reset; + + RegEnRst__Type_Bits5__reset_value_1 priority_reg + ( + .clk( priority_reg__clk ), + .en( priority_reg__en ), + .in_( priority_reg__in_ ), + .out( priority_reg__out ), + .reset( priority_reg__reset ) + ); + + //------------------------------------------------------------- + // End of component priority_reg + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 + // @update + // def comb_grants(): + // for i in range( nreqs ): + // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] + + always_comb begin : comb_grants + for ( int unsigned i = 1'd0; i < 3'( __const__nreqs_at_comb_grants ); i += 1'd1 ) + grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 + // @update + // def comb_grants_int(): + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.grants_int[i] @= s.reqs_int[i] + // else: + // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] + + always_comb begin : comb_grants_int + for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + grants_int[4'(i)] = reqs_int[4'(i)]; + end + else + grants_int[4'(i)] = ( ~kills[4'(i)] ) & reqs_int[4'(i)]; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 + // @update + // def comb_kills(): + // s.kills[0] @= 1 + // for i in range( nreqsX2 ): + // if s.priority_int[i]: + // s.kills[i+1] @= s.reqs_int[i] + // else: + // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) + + always_comb begin : comb_kills + kills[4'd0] = 1'd1; + for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) + if ( priority_int[4'(i)] ) begin + kills[4'(i) + 4'd1] = reqs_int[4'(i)]; + end + else + kills[4'(i) + 4'd1] = kills[4'(i)] | ( ( ~kills[4'(i)] ) & reqs_int[4'(i)] ); + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 + // @update + // def comb_priority_en(): + // s.priority_en @= ( s.grants != 0 ) & s.en + + always_comb begin : comb_priority_en + priority_en = ( grants != 5'd0 ) & en; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 + // @update + // def comb_priority_int(): + // s.priority_int[ 0:nreqs ] @= s.priority_reg.out + // s.priority_int[nreqs:nreqsX2] @= 0 + + always_comb begin : comb_priority_int + priority_int[4'd4:4'd0] = priority_reg__out; + priority_int[4'd9:4'( __const__nreqs_at_comb_priority_int )] = 5'd0; + end + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 + // @update + // def comb_reqs_int(): + // s.reqs_int [ 0:nreqs ] @= s.reqs + // s.reqs_int [nreqs:nreqsX2] @= s.reqs + + always_comb begin : comb_reqs_int + reqs_int[4'd4:4'd0] = reqs; + reqs_int[4'd9:4'( __const__nreqs_at_comb_reqs_int )] = reqs; + end + + assign priority_reg__clk = clk; + assign priority_reg__reset = reset; + assign priority_reg__en = priority_en; + assign priority_reg__in_[4:1] = grants[3:0]; + assign priority_reg__in_[0:0] = grants[4:4]; + +endmodule + + +// PyMTL Component Encoder Definition +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py + +module Encoder__in_nbits_5__out_nbits_3 +( + input logic [0:0] clk , + input logic [4:0] in_ , + output logic [2:0] out , + input logic [0:0] reset +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 + // @update + // def encode(): + // s.out @= 0 + // for i in range( s.in_nbits ): + // if s.in_[i]: + // s.out @= i + + always_comb begin : encode + out = 3'd0; + for ( int unsigned i = 1'd0; i < 3'd5; i += 1'd1 ) + if ( in_[3'(i)] ) begin + out = 3'(i); + end + end + +endmodule + + +// PyMTL Component Mux Definition +// Full name: Mux__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__ninputs_5 +// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py + +module Mux__5c29509c868f9669 +( + input logic [0:0] clk , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d in_ [0:4], + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d out , + input logic [0:0] reset , + input logic [2:0] sel +); + + // PyMTL Update Block Source + // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 + // @update + // def up_mux(): + // s.out @= s.in_[ s.sel ] + + always_comb begin : up_mux + out = in_[sel]; + end + +endmodule + + +// PyMTL Component SwitchUnitRTL Definition +// Full name: SwitchUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_inports_5 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py + +module SwitchUnitRTL__1ccc072d8fcd170f +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:4] , + output logic [0:0] recv__rdy [0:4] , + input logic [0:0] recv__val [0:4] , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , + input logic [0:0] send__rdy , + output logic [0:0] send__val +); + localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd5; + //------------------------------------------------------------- + // Component arbiter + //------------------------------------------------------------- + + logic [0:0] arbiter__clk; + logic [0:0] arbiter__en; + logic [4:0] arbiter__grants; + logic [4:0] arbiter__reqs; + logic [0:0] arbiter__reset; + + RoundRobinArbiterEn__nreqs_5 arbiter + ( + .clk( arbiter__clk ), + .en( arbiter__en ), + .grants( arbiter__grants ), + .reqs( arbiter__reqs ), + .reset( arbiter__reset ) + ); + + //------------------------------------------------------------- + // End of component arbiter + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component encoder + //------------------------------------------------------------- + + logic [0:0] encoder__clk; + logic [4:0] encoder__in_; + logic [2:0] encoder__out; + logic [0:0] encoder__reset; + + Encoder__in_nbits_5__out_nbits_3 encoder + ( + .clk( encoder__clk ), + .in_( encoder__in_ ), + .out( encoder__out ), + .reset( encoder__reset ) + ); + + //------------------------------------------------------------- + // End of component encoder + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mux + //------------------------------------------------------------- + + logic [0:0] mux__clk; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mux__in_ [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mux__out; + logic [0:0] mux__reset; + logic [2:0] mux__sel; + + Mux__5c29509c868f9669 mux + ( + .clk( mux__clk ), + .in_( mux__in_ ), + .out( mux__out ), + .reset( mux__reset ), + .sel( mux__sel ) + ); + + //------------------------------------------------------------- + // End of component mux + //------------------------------------------------------------- + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 + // @update + // def up_get_en(): + // for i in range( num_inports ): + // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) + + always_comb begin : up_get_en + for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) + recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); + end + + // PyMTL Update Block Source + // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 + // @update + // def up_send_val(): + // s.send.val @= s.arbiter.grants > 0 + + always_comb begin : up_send_val + send__val = arbiter__grants > 5'd0; + end + + assign arbiter__clk = clk; + assign arbiter__reset = reset; + assign arbiter__en = 1'd1; + assign mux__clk = clk; + assign mux__reset = reset; + assign send__msg = mux__out; + assign encoder__clk = clk; + assign encoder__reset = reset; + assign encoder__in_ = arbiter__grants; + assign mux__sel = encoder__out; + assign arbiter__reqs[0:0] = recv__val[0]; + assign mux__in_[0] = recv__msg[0]; + assign arbiter__reqs[1:1] = recv__val[1]; + assign mux__in_[1] = recv__msg[1]; + assign arbiter__reqs[2:2] = recv__val[2]; + assign mux__in_[2] = recv__msg[2]; + assign arbiter__reqs[3:3] = recv__val[3]; + assign mux__in_[3] = recv__msg[3]; + assign arbiter__reqs[4:4] = recv__val[4]; + assign mux__in_[4] = recv__msg[4]; + +endmodule + + +// PyMTL Component MeshRouterRTL Definition +// Full name: MeshRouterRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__InputUnitType_InputUnitRTL__RouteUnitType_DORYMeshRouteUnitRTL__SwitchUnitType_SwitchUnitRTL +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/MeshRouterRTL.py + +module MeshRouterRTL__574f02d875fdbb92 +( + input logic [0:0] clk , + input MeshPosition_2x2__pos_x_1__pos_y_1 pos , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:4] , + output logic [0:0] recv__rdy [0:4] , + input logic [0:0] recv__val [0:4] , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:4] , + input logic [0:0] send__rdy [0:4] , + output logic [0:0] send__val [0:4] +); + //------------------------------------------------------------- + // Component input_units[0:4] + //------------------------------------------------------------- + + logic [0:0] input_units__clk [0:4]; + logic [0:0] input_units__reset [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d input_units__recv__msg [0:4]; + logic [0:0] input_units__recv__rdy [0:4]; + logic [0:0] input_units__recv__val [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d input_units__send__msg [0:4]; + logic [0:0] input_units__send__rdy [0:4]; + logic [0:0] input_units__send__val [0:4]; + + InputUnitRTL__8ea2cb5fb7536c6c input_units__0 + ( + .clk( input_units__clk[0] ), + .reset( input_units__reset[0] ), + .recv__msg( input_units__recv__msg[0] ), + .recv__rdy( input_units__recv__rdy[0] ), + .recv__val( input_units__recv__val[0] ), + .send__msg( input_units__send__msg[0] ), + .send__rdy( input_units__send__rdy[0] ), + .send__val( input_units__send__val[0] ) + ); + + InputUnitRTL__8ea2cb5fb7536c6c input_units__1 + ( + .clk( input_units__clk[1] ), + .reset( input_units__reset[1] ), + .recv__msg( input_units__recv__msg[1] ), + .recv__rdy( input_units__recv__rdy[1] ), + .recv__val( input_units__recv__val[1] ), + .send__msg( input_units__send__msg[1] ), + .send__rdy( input_units__send__rdy[1] ), + .send__val( input_units__send__val[1] ) + ); + + InputUnitRTL__8ea2cb5fb7536c6c input_units__2 + ( + .clk( input_units__clk[2] ), + .reset( input_units__reset[2] ), + .recv__msg( input_units__recv__msg[2] ), + .recv__rdy( input_units__recv__rdy[2] ), + .recv__val( input_units__recv__val[2] ), + .send__msg( input_units__send__msg[2] ), + .send__rdy( input_units__send__rdy[2] ), + .send__val( input_units__send__val[2] ) + ); + + InputUnitRTL__8ea2cb5fb7536c6c input_units__3 + ( + .clk( input_units__clk[3] ), + .reset( input_units__reset[3] ), + .recv__msg( input_units__recv__msg[3] ), + .recv__rdy( input_units__recv__rdy[3] ), + .recv__val( input_units__recv__val[3] ), + .send__msg( input_units__send__msg[3] ), + .send__rdy( input_units__send__rdy[3] ), + .send__val( input_units__send__val[3] ) + ); + + InputUnitRTL__8ea2cb5fb7536c6c input_units__4 + ( + .clk( input_units__clk[4] ), + .reset( input_units__reset[4] ), + .recv__msg( input_units__recv__msg[4] ), + .recv__rdy( input_units__recv__rdy[4] ), + .recv__val( input_units__recv__val[4] ), + .send__msg( input_units__send__msg[4] ), + .send__rdy( input_units__send__rdy[4] ), + .send__val( input_units__send__val[4] ) + ); + + //------------------------------------------------------------- + // End of component input_units[0:4] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component output_units[0:4] + //------------------------------------------------------------- + + logic [0:0] output_units__clk [0:4]; + logic [0:0] output_units__reset [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d output_units__recv__msg [0:4]; + logic [0:0] output_units__recv__rdy [0:4]; + logic [0:0] output_units__recv__val [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d output_units__send__msg [0:4]; + logic [0:0] output_units__send__rdy [0:4]; + logic [0:0] output_units__send__val [0:4]; + + OutputUnitRTL__e43ef936c3b236b0 output_units__0 + ( + .clk( output_units__clk[0] ), + .reset( output_units__reset[0] ), + .recv__msg( output_units__recv__msg[0] ), + .recv__rdy( output_units__recv__rdy[0] ), + .recv__val( output_units__recv__val[0] ), + .send__msg( output_units__send__msg[0] ), + .send__rdy( output_units__send__rdy[0] ), + .send__val( output_units__send__val[0] ) + ); + + OutputUnitRTL__e43ef936c3b236b0 output_units__1 + ( + .clk( output_units__clk[1] ), + .reset( output_units__reset[1] ), + .recv__msg( output_units__recv__msg[1] ), + .recv__rdy( output_units__recv__rdy[1] ), + .recv__val( output_units__recv__val[1] ), + .send__msg( output_units__send__msg[1] ), + .send__rdy( output_units__send__rdy[1] ), + .send__val( output_units__send__val[1] ) + ); + + OutputUnitRTL__e43ef936c3b236b0 output_units__2 + ( + .clk( output_units__clk[2] ), + .reset( output_units__reset[2] ), + .recv__msg( output_units__recv__msg[2] ), + .recv__rdy( output_units__recv__rdy[2] ), + .recv__val( output_units__recv__val[2] ), + .send__msg( output_units__send__msg[2] ), + .send__rdy( output_units__send__rdy[2] ), + .send__val( output_units__send__val[2] ) + ); + + OutputUnitRTL__e43ef936c3b236b0 output_units__3 + ( + .clk( output_units__clk[3] ), + .reset( output_units__reset[3] ), + .recv__msg( output_units__recv__msg[3] ), + .recv__rdy( output_units__recv__rdy[3] ), + .recv__val( output_units__recv__val[3] ), + .send__msg( output_units__send__msg[3] ), + .send__rdy( output_units__send__rdy[3] ), + .send__val( output_units__send__val[3] ) + ); + + OutputUnitRTL__e43ef936c3b236b0 output_units__4 + ( + .clk( output_units__clk[4] ), + .reset( output_units__reset[4] ), + .recv__msg( output_units__recv__msg[4] ), + .recv__rdy( output_units__recv__rdy[4] ), + .recv__val( output_units__recv__val[4] ), + .send__msg( output_units__send__msg[4] ), + .send__rdy( output_units__send__rdy[4] ), + .send__val( output_units__send__val[4] ) + ); + + //------------------------------------------------------------- + // End of component output_units[0:4] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component route_units[0:4] + //------------------------------------------------------------- + + logic [0:0] route_units__clk [0:4]; + MeshPosition_2x2__pos_x_1__pos_y_1 route_units__pos [0:4]; + logic [0:0] route_units__reset [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d route_units__recv__msg [0:4]; + logic [0:0] route_units__recv__rdy [0:4]; + logic [0:0] route_units__recv__val [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d route_units__send__msg [0:4][0:4]; + logic [0:0] route_units__send__rdy [0:4][0:4]; + logic [0:0] route_units__send__val [0:4][0:4]; + + DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__0 + ( + .clk( route_units__clk[0] ), + .pos( route_units__pos[0] ), + .reset( route_units__reset[0] ), + .recv__msg( route_units__recv__msg[0] ), + .recv__rdy( route_units__recv__rdy[0] ), + .recv__val( route_units__recv__val[0] ), + .send__msg( route_units__send__msg[0] ), + .send__rdy( route_units__send__rdy[0] ), + .send__val( route_units__send__val[0] ) + ); + + DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__1 + ( + .clk( route_units__clk[1] ), + .pos( route_units__pos[1] ), + .reset( route_units__reset[1] ), + .recv__msg( route_units__recv__msg[1] ), + .recv__rdy( route_units__recv__rdy[1] ), + .recv__val( route_units__recv__val[1] ), + .send__msg( route_units__send__msg[1] ), + .send__rdy( route_units__send__rdy[1] ), + .send__val( route_units__send__val[1] ) + ); + + DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__2 + ( + .clk( route_units__clk[2] ), + .pos( route_units__pos[2] ), + .reset( route_units__reset[2] ), + .recv__msg( route_units__recv__msg[2] ), + .recv__rdy( route_units__recv__rdy[2] ), + .recv__val( route_units__recv__val[2] ), + .send__msg( route_units__send__msg[2] ), + .send__rdy( route_units__send__rdy[2] ), + .send__val( route_units__send__val[2] ) + ); + + DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__3 + ( + .clk( route_units__clk[3] ), + .pos( route_units__pos[3] ), + .reset( route_units__reset[3] ), + .recv__msg( route_units__recv__msg[3] ), + .recv__rdy( route_units__recv__rdy[3] ), + .recv__val( route_units__recv__val[3] ), + .send__msg( route_units__send__msg[3] ), + .send__rdy( route_units__send__rdy[3] ), + .send__val( route_units__send__val[3] ) + ); + + DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__4 + ( + .clk( route_units__clk[4] ), + .pos( route_units__pos[4] ), + .reset( route_units__reset[4] ), + .recv__msg( route_units__recv__msg[4] ), + .recv__rdy( route_units__recv__rdy[4] ), + .recv__val( route_units__recv__val[4] ), + .send__msg( route_units__send__msg[4] ), + .send__rdy( route_units__send__rdy[4] ), + .send__val( route_units__send__val[4] ) + ); + + //------------------------------------------------------------- + // End of component route_units[0:4] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component switch_units[0:4] + //------------------------------------------------------------- + + logic [0:0] switch_units__clk [0:4]; + logic [0:0] switch_units__reset [0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d switch_units__recv__msg [0:4][0:4]; + logic [0:0] switch_units__recv__rdy [0:4][0:4]; + logic [0:0] switch_units__recv__val [0:4][0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d switch_units__send__msg [0:4]; + logic [0:0] switch_units__send__rdy [0:4]; + logic [0:0] switch_units__send__val [0:4]; + + SwitchUnitRTL__1ccc072d8fcd170f switch_units__0 + ( + .clk( switch_units__clk[0] ), + .reset( switch_units__reset[0] ), + .recv__msg( switch_units__recv__msg[0] ), + .recv__rdy( switch_units__recv__rdy[0] ), + .recv__val( switch_units__recv__val[0] ), + .send__msg( switch_units__send__msg[0] ), + .send__rdy( switch_units__send__rdy[0] ), + .send__val( switch_units__send__val[0] ) + ); + + SwitchUnitRTL__1ccc072d8fcd170f switch_units__1 + ( + .clk( switch_units__clk[1] ), + .reset( switch_units__reset[1] ), + .recv__msg( switch_units__recv__msg[1] ), + .recv__rdy( switch_units__recv__rdy[1] ), + .recv__val( switch_units__recv__val[1] ), + .send__msg( switch_units__send__msg[1] ), + .send__rdy( switch_units__send__rdy[1] ), + .send__val( switch_units__send__val[1] ) + ); + + SwitchUnitRTL__1ccc072d8fcd170f switch_units__2 + ( + .clk( switch_units__clk[2] ), + .reset( switch_units__reset[2] ), + .recv__msg( switch_units__recv__msg[2] ), + .recv__rdy( switch_units__recv__rdy[2] ), + .recv__val( switch_units__recv__val[2] ), + .send__msg( switch_units__send__msg[2] ), + .send__rdy( switch_units__send__rdy[2] ), + .send__val( switch_units__send__val[2] ) + ); + + SwitchUnitRTL__1ccc072d8fcd170f switch_units__3 + ( + .clk( switch_units__clk[3] ), + .reset( switch_units__reset[3] ), + .recv__msg( switch_units__recv__msg[3] ), + .recv__rdy( switch_units__recv__rdy[3] ), + .recv__val( switch_units__recv__val[3] ), + .send__msg( switch_units__send__msg[3] ), + .send__rdy( switch_units__send__rdy[3] ), + .send__val( switch_units__send__val[3] ) + ); + + SwitchUnitRTL__1ccc072d8fcd170f switch_units__4 + ( + .clk( switch_units__clk[4] ), + .reset( switch_units__reset[4] ), + .recv__msg( switch_units__recv__msg[4] ), + .recv__rdy( switch_units__recv__rdy[4] ), + .recv__val( switch_units__recv__val[4] ), + .send__msg( switch_units__send__msg[4] ), + .send__rdy( switch_units__send__rdy[4] ), + .send__val( switch_units__send__val[4] ) + ); + + //------------------------------------------------------------- + // End of component switch_units[0:4] + //------------------------------------------------------------- + + assign input_units__clk[0] = clk; + assign input_units__reset[0] = reset; + assign input_units__clk[1] = clk; + assign input_units__reset[1] = reset; + assign input_units__clk[2] = clk; + assign input_units__reset[2] = reset; + assign input_units__clk[3] = clk; + assign input_units__reset[3] = reset; + assign input_units__clk[4] = clk; + assign input_units__reset[4] = reset; + assign route_units__clk[0] = clk; + assign route_units__reset[0] = reset; + assign route_units__clk[1] = clk; + assign route_units__reset[1] = reset; + assign route_units__clk[2] = clk; + assign route_units__reset[2] = reset; + assign route_units__clk[3] = clk; + assign route_units__reset[3] = reset; + assign route_units__clk[4] = clk; + assign route_units__reset[4] = reset; + assign switch_units__clk[0] = clk; + assign switch_units__reset[0] = reset; + assign switch_units__clk[1] = clk; + assign switch_units__reset[1] = reset; + assign switch_units__clk[2] = clk; + assign switch_units__reset[2] = reset; + assign switch_units__clk[3] = clk; + assign switch_units__reset[3] = reset; + assign switch_units__clk[4] = clk; + assign switch_units__reset[4] = reset; + assign output_units__clk[0] = clk; + assign output_units__reset[0] = reset; + assign output_units__clk[1] = clk; + assign output_units__reset[1] = reset; + assign output_units__clk[2] = clk; + assign output_units__reset[2] = reset; + assign output_units__clk[3] = clk; + assign output_units__reset[3] = reset; + assign output_units__clk[4] = clk; + assign output_units__reset[4] = reset; + assign input_units__recv__msg[0] = recv__msg[0]; + assign recv__rdy[0] = input_units__recv__rdy[0]; + assign input_units__recv__val[0] = recv__val[0]; + assign route_units__recv__msg[0] = input_units__send__msg[0]; + assign input_units__send__rdy[0] = route_units__recv__rdy[0]; + assign route_units__recv__val[0] = input_units__send__val[0]; + assign route_units__pos[0] = pos; + assign input_units__recv__msg[1] = recv__msg[1]; + assign recv__rdy[1] = input_units__recv__rdy[1]; + assign input_units__recv__val[1] = recv__val[1]; + assign route_units__recv__msg[1] = input_units__send__msg[1]; + assign input_units__send__rdy[1] = route_units__recv__rdy[1]; + assign route_units__recv__val[1] = input_units__send__val[1]; + assign route_units__pos[1] = pos; + assign input_units__recv__msg[2] = recv__msg[2]; + assign recv__rdy[2] = input_units__recv__rdy[2]; + assign input_units__recv__val[2] = recv__val[2]; + assign route_units__recv__msg[2] = input_units__send__msg[2]; + assign input_units__send__rdy[2] = route_units__recv__rdy[2]; + assign route_units__recv__val[2] = input_units__send__val[2]; + assign route_units__pos[2] = pos; + assign input_units__recv__msg[3] = recv__msg[3]; + assign recv__rdy[3] = input_units__recv__rdy[3]; + assign input_units__recv__val[3] = recv__val[3]; + assign route_units__recv__msg[3] = input_units__send__msg[3]; + assign input_units__send__rdy[3] = route_units__recv__rdy[3]; + assign route_units__recv__val[3] = input_units__send__val[3]; + assign route_units__pos[3] = pos; + assign input_units__recv__msg[4] = recv__msg[4]; + assign recv__rdy[4] = input_units__recv__rdy[4]; + assign input_units__recv__val[4] = recv__val[4]; + assign route_units__recv__msg[4] = input_units__send__msg[4]; + assign input_units__send__rdy[4] = route_units__recv__rdy[4]; + assign route_units__recv__val[4] = input_units__send__val[4]; + assign route_units__pos[4] = pos; + assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; + assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; + assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; + assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; + assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; + assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; + assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; + assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; + assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; + assign switch_units__recv__msg[3][0] = route_units__send__msg[0][3]; + assign route_units__send__rdy[0][3] = switch_units__recv__rdy[3][0]; + assign switch_units__recv__val[3][0] = route_units__send__val[0][3]; + assign switch_units__recv__msg[4][0] = route_units__send__msg[0][4]; + assign route_units__send__rdy[0][4] = switch_units__recv__rdy[4][0]; + assign switch_units__recv__val[4][0] = route_units__send__val[0][4]; + assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; + assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; + assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; + assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; + assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; + assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; + assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; + assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; + assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; + assign switch_units__recv__msg[3][1] = route_units__send__msg[1][3]; + assign route_units__send__rdy[1][3] = switch_units__recv__rdy[3][1]; + assign switch_units__recv__val[3][1] = route_units__send__val[1][3]; + assign switch_units__recv__msg[4][1] = route_units__send__msg[1][4]; + assign route_units__send__rdy[1][4] = switch_units__recv__rdy[4][1]; + assign switch_units__recv__val[4][1] = route_units__send__val[1][4]; + assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; + assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; + assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; + assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; + assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; + assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; + assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; + assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; + assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; + assign switch_units__recv__msg[3][2] = route_units__send__msg[2][3]; + assign route_units__send__rdy[2][3] = switch_units__recv__rdy[3][2]; + assign switch_units__recv__val[3][2] = route_units__send__val[2][3]; + assign switch_units__recv__msg[4][2] = route_units__send__msg[2][4]; + assign route_units__send__rdy[2][4] = switch_units__recv__rdy[4][2]; + assign switch_units__recv__val[4][2] = route_units__send__val[2][4]; + assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; + assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; + assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; + assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; + assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; + assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; + assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; + assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; + assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; + assign switch_units__recv__msg[3][3] = route_units__send__msg[3][3]; + assign route_units__send__rdy[3][3] = switch_units__recv__rdy[3][3]; + assign switch_units__recv__val[3][3] = route_units__send__val[3][3]; + assign switch_units__recv__msg[4][3] = route_units__send__msg[3][4]; + assign route_units__send__rdy[3][4] = switch_units__recv__rdy[4][3]; + assign switch_units__recv__val[4][3] = route_units__send__val[3][4]; + assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; + assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; + assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; + assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; + assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; + assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; + assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; + assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; + assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; + assign switch_units__recv__msg[3][4] = route_units__send__msg[4][3]; + assign route_units__send__rdy[4][3] = switch_units__recv__rdy[3][4]; + assign switch_units__recv__val[3][4] = route_units__send__val[4][3]; + assign switch_units__recv__msg[4][4] = route_units__send__msg[4][4]; + assign route_units__send__rdy[4][4] = switch_units__recv__rdy[4][4]; + assign switch_units__recv__val[4][4] = route_units__send__val[4][4]; + assign output_units__recv__msg[0] = switch_units__send__msg[0]; + assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; + assign output_units__recv__val[0] = switch_units__send__val[0]; + assign send__msg[0] = output_units__send__msg[0]; + assign output_units__send__rdy[0] = send__rdy[0]; + assign send__val[0] = output_units__send__val[0]; + assign output_units__recv__msg[1] = switch_units__send__msg[1]; + assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; + assign output_units__recv__val[1] = switch_units__send__val[1]; + assign send__msg[1] = output_units__send__msg[1]; + assign output_units__send__rdy[1] = send__rdy[1]; + assign send__val[1] = output_units__send__val[1]; + assign output_units__recv__msg[2] = switch_units__send__msg[2]; + assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; + assign output_units__recv__val[2] = switch_units__send__val[2]; + assign send__msg[2] = output_units__send__msg[2]; + assign output_units__send__rdy[2] = send__rdy[2]; + assign send__val[2] = output_units__send__val[2]; + assign output_units__recv__msg[3] = switch_units__send__msg[3]; + assign switch_units__send__rdy[3] = output_units__recv__rdy[3]; + assign output_units__recv__val[3] = switch_units__send__val[3]; + assign send__msg[3] = output_units__send__msg[3]; + assign output_units__send__rdy[3] = send__rdy[3]; + assign send__val[3] = output_units__send__val[3]; + assign output_units__recv__msg[4] = switch_units__send__msg[4]; + assign switch_units__send__rdy[4] = output_units__recv__rdy[4]; + assign output_units__recv__val[4] = switch_units__send__val[4]; + assign send__msg[4] = output_units__send__msg[4]; + assign output_units__send__rdy[4] = send__rdy[4]; + assign send__val[4] = output_units__send__val[4]; + +endmodule + + +// PyMTL Component MeshNetworkRTL Definition +// Full name: MeshNetworkRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__ncols_2__nrows_2__chl_lat_1 +// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/MeshNetworkRTL.py + +module MeshNetworkRTL__4ca7f469967df194 +( + input logic [0:0] clk , + input logic [0:0] reset , + input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:3] , + output logic [0:0] recv__rdy [0:3] , + input logic [0:0] recv__val [0:3] , + output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:3] , + input logic [0:0] send__rdy [0:3] , + output logic [0:0] send__val [0:3] +); + //------------------------------------------------------------- + // Component channels[0:7] + //------------------------------------------------------------- + + logic [0:0] channels__clk [0:7]; + logic [0:0] channels__reset [0:7]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d channels__recv__msg [0:7]; + logic [0:0] channels__recv__rdy [0:7]; + logic [0:0] channels__recv__val [0:7]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d channels__send__msg [0:7]; + logic [0:0] channels__send__rdy [0:7]; + logic [0:0] channels__send__val [0:7]; + + ChannelRTL__551ecec02ed96ac9 channels__0 + ( + .clk( channels__clk[0] ), + .reset( channels__reset[0] ), + .recv__msg( channels__recv__msg[0] ), + .recv__rdy( channels__recv__rdy[0] ), + .recv__val( channels__recv__val[0] ), + .send__msg( channels__send__msg[0] ), + .send__rdy( channels__send__rdy[0] ), + .send__val( channels__send__val[0] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__1 + ( + .clk( channels__clk[1] ), + .reset( channels__reset[1] ), + .recv__msg( channels__recv__msg[1] ), + .recv__rdy( channels__recv__rdy[1] ), + .recv__val( channels__recv__val[1] ), + .send__msg( channels__send__msg[1] ), + .send__rdy( channels__send__rdy[1] ), + .send__val( channels__send__val[1] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__2 + ( + .clk( channels__clk[2] ), + .reset( channels__reset[2] ), + .recv__msg( channels__recv__msg[2] ), + .recv__rdy( channels__recv__rdy[2] ), + .recv__val( channels__recv__val[2] ), + .send__msg( channels__send__msg[2] ), + .send__rdy( channels__send__rdy[2] ), + .send__val( channels__send__val[2] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__3 + ( + .clk( channels__clk[3] ), + .reset( channels__reset[3] ), + .recv__msg( channels__recv__msg[3] ), + .recv__rdy( channels__recv__rdy[3] ), + .recv__val( channels__recv__val[3] ), + .send__msg( channels__send__msg[3] ), + .send__rdy( channels__send__rdy[3] ), + .send__val( channels__send__val[3] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__4 + ( + .clk( channels__clk[4] ), + .reset( channels__reset[4] ), + .recv__msg( channels__recv__msg[4] ), + .recv__rdy( channels__recv__rdy[4] ), + .recv__val( channels__recv__val[4] ), + .send__msg( channels__send__msg[4] ), + .send__rdy( channels__send__rdy[4] ), + .send__val( channels__send__val[4] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__5 + ( + .clk( channels__clk[5] ), + .reset( channels__reset[5] ), + .recv__msg( channels__recv__msg[5] ), + .recv__rdy( channels__recv__rdy[5] ), + .recv__val( channels__recv__val[5] ), + .send__msg( channels__send__msg[5] ), + .send__rdy( channels__send__rdy[5] ), + .send__val( channels__send__val[5] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__6 + ( + .clk( channels__clk[6] ), + .reset( channels__reset[6] ), + .recv__msg( channels__recv__msg[6] ), + .recv__rdy( channels__recv__rdy[6] ), + .recv__val( channels__recv__val[6] ), + .send__msg( channels__send__msg[6] ), + .send__rdy( channels__send__rdy[6] ), + .send__val( channels__send__val[6] ) + ); + + ChannelRTL__551ecec02ed96ac9 channels__7 + ( + .clk( channels__clk[7] ), + .reset( channels__reset[7] ), + .recv__msg( channels__recv__msg[7] ), + .recv__rdy( channels__recv__rdy[7] ), + .recv__val( channels__recv__val[7] ), + .send__msg( channels__send__msg[7] ), + .send__rdy( channels__send__rdy[7] ), + .send__val( channels__send__val[7] ) + ); + + //------------------------------------------------------------- + // End of component channels[0:7] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component routers[0:3] + //------------------------------------------------------------- + + logic [0:0] routers__clk [0:3]; + MeshPosition_2x2__pos_x_1__pos_y_1 routers__pos [0:3]; + logic [0:0] routers__reset [0:3]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d routers__recv__msg [0:3][0:4]; + logic [0:0] routers__recv__rdy [0:3][0:4]; + logic [0:0] routers__recv__val [0:3][0:4]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d routers__send__msg [0:3][0:4]; + logic [0:0] routers__send__rdy [0:3][0:4]; + logic [0:0] routers__send__val [0:3][0:4]; + + MeshRouterRTL__574f02d875fdbb92 routers__0 + ( + .clk( routers__clk[0] ), + .pos( routers__pos[0] ), + .reset( routers__reset[0] ), + .recv__msg( routers__recv__msg[0] ), + .recv__rdy( routers__recv__rdy[0] ), + .recv__val( routers__recv__val[0] ), + .send__msg( routers__send__msg[0] ), + .send__rdy( routers__send__rdy[0] ), + .send__val( routers__send__val[0] ) + ); + + MeshRouterRTL__574f02d875fdbb92 routers__1 + ( + .clk( routers__clk[1] ), + .pos( routers__pos[1] ), + .reset( routers__reset[1] ), + .recv__msg( routers__recv__msg[1] ), + .recv__rdy( routers__recv__rdy[1] ), + .recv__val( routers__recv__val[1] ), + .send__msg( routers__send__msg[1] ), + .send__rdy( routers__send__rdy[1] ), + .send__val( routers__send__val[1] ) + ); + + MeshRouterRTL__574f02d875fdbb92 routers__2 + ( + .clk( routers__clk[2] ), + .pos( routers__pos[2] ), + .reset( routers__reset[2] ), + .recv__msg( routers__recv__msg[2] ), + .recv__rdy( routers__recv__rdy[2] ), + .recv__val( routers__recv__val[2] ), + .send__msg( routers__send__msg[2] ), + .send__rdy( routers__send__rdy[2] ), + .send__val( routers__send__val[2] ) + ); + + MeshRouterRTL__574f02d875fdbb92 routers__3 + ( + .clk( routers__clk[3] ), + .pos( routers__pos[3] ), + .reset( routers__reset[3] ), + .recv__msg( routers__recv__msg[3] ), + .recv__rdy( routers__recv__rdy[3] ), + .recv__val( routers__recv__val[3] ), + .send__msg( routers__send__msg[3] ), + .send__rdy( routers__send__rdy[3] ), + .send__val( routers__send__val[3] ) + ); + + //------------------------------------------------------------- + // End of component routers[0:3] + //------------------------------------------------------------- + + assign routers__clk[0] = clk; + assign routers__reset[0] = reset; + assign routers__clk[1] = clk; + assign routers__reset[1] = reset; + assign routers__clk[2] = clk; + assign routers__reset[2] = reset; + assign routers__clk[3] = clk; + assign routers__reset[3] = reset; + assign channels__clk[0] = clk; + assign channels__reset[0] = reset; + assign channels__clk[1] = clk; + assign channels__reset[1] = reset; + assign channels__clk[2] = clk; + assign channels__reset[2] = reset; + assign channels__clk[3] = clk; + assign channels__reset[3] = reset; + assign channels__clk[4] = clk; + assign channels__reset[4] = reset; + assign channels__clk[5] = clk; + assign channels__reset[5] = reset; + assign channels__clk[6] = clk; + assign channels__reset[6] = reset; + assign channels__clk[7] = clk; + assign channels__reset[7] = reset; + assign routers__pos[0].pos_x = 1'd0; + assign routers__pos[0].pos_y = 1'd0; + assign routers__pos[1].pos_x = 1'd1; + assign routers__pos[1].pos_y = 1'd0; + assign routers__pos[2].pos_x = 1'd0; + assign routers__pos[2].pos_y = 1'd1; + assign routers__pos[3].pos_x = 1'd1; + assign routers__pos[3].pos_y = 1'd1; + assign channels__recv__msg[0] = routers__send__msg[0][0]; + assign routers__send__rdy[0][0] = channels__recv__rdy[0]; + assign channels__recv__val[0] = routers__send__val[0][0]; + assign routers__recv__msg[2][1] = channels__send__msg[0]; + assign channels__send__rdy[0] = routers__recv__rdy[2][1]; + assign routers__recv__val[2][1] = channels__send__val[0]; + assign channels__recv__msg[1] = routers__send__msg[0][3]; + assign routers__send__rdy[0][3] = channels__recv__rdy[1]; + assign channels__recv__val[1] = routers__send__val[0][3]; + assign routers__recv__msg[1][2] = channels__send__msg[1]; + assign channels__send__rdy[1] = routers__recv__rdy[1][2]; + assign routers__recv__val[1][2] = channels__send__val[1]; + assign routers__recv__msg[0][4] = recv__msg[0]; + assign recv__rdy[0] = routers__recv__rdy[0][4]; + assign routers__recv__val[0][4] = recv__val[0]; + assign send__msg[0] = routers__send__msg[0][4]; + assign routers__send__rdy[0][4] = send__rdy[0]; + assign send__val[0] = routers__send__val[0][4]; + assign routers__send__rdy[0][1] = 1'd0; + assign routers__recv__val[0][1] = 1'd0; + assign routers__recv__msg[0][1] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign routers__send__rdy[0][2] = 1'd0; + assign routers__recv__val[0][2] = 1'd0; + assign routers__recv__msg[0][2] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign channels__recv__msg[2] = routers__send__msg[1][0]; + assign routers__send__rdy[1][0] = channels__recv__rdy[2]; + assign channels__recv__val[2] = routers__send__val[1][0]; + assign routers__recv__msg[3][1] = channels__send__msg[2]; + assign channels__send__rdy[2] = routers__recv__rdy[3][1]; + assign routers__recv__val[3][1] = channels__send__val[2]; + assign channels__recv__msg[3] = routers__send__msg[1][2]; + assign routers__send__rdy[1][2] = channels__recv__rdy[3]; + assign channels__recv__val[3] = routers__send__val[1][2]; + assign routers__recv__msg[0][3] = channels__send__msg[3]; + assign channels__send__rdy[3] = routers__recv__rdy[0][3]; + assign routers__recv__val[0][3] = channels__send__val[3]; + assign routers__recv__msg[1][4] = recv__msg[1]; + assign recv__rdy[1] = routers__recv__rdy[1][4]; + assign routers__recv__val[1][4] = recv__val[1]; + assign send__msg[1] = routers__send__msg[1][4]; + assign routers__send__rdy[1][4] = send__rdy[1]; + assign send__val[1] = routers__send__val[1][4]; + assign routers__send__rdy[1][1] = 1'd0; + assign routers__recv__val[1][1] = 1'd0; + assign routers__recv__msg[1][1] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign routers__send__rdy[1][3] = 1'd0; + assign routers__recv__val[1][3] = 1'd0; + assign routers__recv__msg[1][3] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign channels__recv__msg[4] = routers__send__msg[2][1]; + assign routers__send__rdy[2][1] = channels__recv__rdy[4]; + assign channels__recv__val[4] = routers__send__val[2][1]; + assign routers__recv__msg[0][0] = channels__send__msg[4]; + assign channels__send__rdy[4] = routers__recv__rdy[0][0]; + assign routers__recv__val[0][0] = channels__send__val[4]; + assign channels__recv__msg[5] = routers__send__msg[2][3]; + assign routers__send__rdy[2][3] = channels__recv__rdy[5]; + assign channels__recv__val[5] = routers__send__val[2][3]; + assign routers__recv__msg[3][2] = channels__send__msg[5]; + assign channels__send__rdy[5] = routers__recv__rdy[3][2]; + assign routers__recv__val[3][2] = channels__send__val[5]; + assign routers__recv__msg[2][4] = recv__msg[2]; + assign recv__rdy[2] = routers__recv__rdy[2][4]; + assign routers__recv__val[2][4] = recv__val[2]; + assign send__msg[2] = routers__send__msg[2][4]; + assign routers__send__rdy[2][4] = send__rdy[2]; + assign send__val[2] = routers__send__val[2][4]; + assign routers__send__rdy[2][0] = 1'd0; + assign routers__recv__val[2][0] = 1'd0; + assign routers__recv__msg[2][0] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign routers__send__rdy[2][2] = 1'd0; + assign routers__recv__val[2][2] = 1'd0; + assign routers__recv__msg[2][2] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign channels__recv__msg[6] = routers__send__msg[3][1]; + assign routers__send__rdy[3][1] = channels__recv__rdy[6]; + assign channels__recv__val[6] = routers__send__val[3][1]; + assign routers__recv__msg[1][0] = channels__send__msg[6]; + assign channels__send__rdy[6] = routers__recv__rdy[1][0]; + assign routers__recv__val[1][0] = channels__send__val[6]; + assign channels__recv__msg[7] = routers__send__msg[3][2]; + assign routers__send__rdy[3][2] = channels__recv__rdy[7]; + assign channels__recv__val[7] = routers__send__val[3][2]; + assign routers__recv__msg[2][3] = channels__send__msg[7]; + assign channels__send__rdy[7] = routers__recv__rdy[2][3]; + assign routers__recv__val[2][3] = channels__send__val[7]; + assign routers__recv__msg[3][4] = recv__msg[3]; + assign recv__rdy[3] = routers__recv__rdy[3][4]; + assign routers__recv__val[3][4] = recv__val[3]; + assign send__msg[3] = routers__send__msg[3][4]; + assign routers__send__rdy[3][4] = send__rdy[3]; + assign send__val[3] = routers__send__val[3][4]; + assign routers__send__rdy[3][0] = 1'd0; + assign routers__recv__val[3][0] = 1'd0; + assign routers__recv__msg[3][0] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign routers__send__rdy[3][3] = 1'd0; + assign routers__recv__val[3][3] = 1'd0; + assign routers__recv__msg[3][3] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + +endmodule + + +// PyMTL Component MeshMultiCgraRTL Definition +// Full name: MeshMultiCgraRTL__CgraPayloadType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__cgra_rows_2__cgra_columns_2__tile_rows_4__tile_columns_4__ctrl_mem_size_16__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_registers_per_reg_bank_16__num_ctrl_4__total_steps_38__mem_access_is_combinational_True__FunctionUnit_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ]__per_cgra_topology_Mesh__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__support_task_switching_False +// At /home/ajokai/cgra/VectorCGRAfork0/multi_cgra/MeshMultiCgraRTL.py + +module MeshMultiCgraRTL__explicit_vector_global_reduce +( + input logic [0:0] clk , + input logic [0:0] reset , + input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , + output logic [0:0] recv_from_cpu_pkt__rdy , + input logic [0:0] recv_from_cpu_pkt__val , + output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , + input logic [0:0] send_to_cpu_pkt__rdy , + output logic [0:0] send_to_cpu_pkt__val +); + //------------------------------------------------------------- + // Component cgra[0:3] + //------------------------------------------------------------- + + logic [6:0] cgra__address_lower [0:3]; + logic [6:0] cgra__address_upper [0:3]; + logic [1:0] cgra__cgra_id [0:3]; + logic [0:0] cgra__clk [0:3]; + logic [0:0] cgra__reset [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_east__msg [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_east__rdy [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_east__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_north__msg [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_north__rdy [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_north__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_south__msg [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_south__rdy [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_south__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_west__msg [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_west__rdy [0:3][0:3]; + logic [0:0] cgra__recv_data_on_boundary_west__val [0:3][0:3]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 cgra__recv_from_cpu_pkt__msg [0:3]; + logic [0:0] cgra__recv_from_cpu_pkt__rdy [0:3]; + logic [0:0] cgra__recv_from_cpu_pkt__val [0:3]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d cgra__recv_from_inter_cgra_noc__msg [0:3]; + logic [0:0] cgra__recv_from_inter_cgra_noc__rdy [0:3]; + logic [0:0] cgra__recv_from_inter_cgra_noc__val [0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_east__msg [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_east__rdy [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_east__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_north__msg [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_north__rdy [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_north__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_south__msg [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_south__rdy [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_south__val [0:3][0:3]; + CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_west__msg [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_west__rdy [0:3][0:3]; + logic [0:0] cgra__send_data_on_boundary_west__val [0:3][0:3]; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 cgra__send_to_cpu_pkt__msg [0:3]; + logic [0:0] cgra__send_to_cpu_pkt__rdy [0:3]; + logic [0:0] cgra__send_to_cpu_pkt__val [0:3]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d cgra__send_to_inter_cgra_noc__msg [0:3]; + logic [0:0] cgra__send_to_inter_cgra_noc__rdy [0:3]; + logic [0:0] cgra__send_to_inter_cgra_noc__val [0:3]; + + CgraRTL__72d915b46abe89cb cgra__0 + ( + .address_lower( cgra__address_lower[0] ), + .address_upper( cgra__address_upper[0] ), + .cgra_id( cgra__cgra_id[0] ), + .clk( cgra__clk[0] ), + .reset( cgra__reset[0] ), + .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[0] ), + .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[0] ), + .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[0] ), + .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[0] ), + .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[0] ), + .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[0] ), + .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[0] ), + .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[0] ), + .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[0] ), + .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[0] ), + .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[0] ), + .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[0] ), + .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[0] ), + .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[0] ), + .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[0] ), + .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[0] ), + .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[0] ), + .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[0] ), + .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[0] ), + .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[0] ), + .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[0] ), + .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[0] ), + .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[0] ), + .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[0] ), + .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[0] ), + .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[0] ), + .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[0] ), + .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[0] ), + .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[0] ), + .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[0] ), + .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[0] ), + .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[0] ), + .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[0] ), + .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[0] ), + .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[0] ), + .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[0] ) + ); + + CgraRTL__72d915b46abe89cb cgra__1 + ( + .address_lower( cgra__address_lower[1] ), + .address_upper( cgra__address_upper[1] ), + .cgra_id( cgra__cgra_id[1] ), + .clk( cgra__clk[1] ), + .reset( cgra__reset[1] ), + .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[1] ), + .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[1] ), + .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[1] ), + .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[1] ), + .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[1] ), + .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[1] ), + .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[1] ), + .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[1] ), + .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[1] ), + .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[1] ), + .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[1] ), + .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[1] ), + .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[1] ), + .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[1] ), + .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[1] ), + .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[1] ), + .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[1] ), + .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[1] ), + .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[1] ), + .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[1] ), + .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[1] ), + .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[1] ), + .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[1] ), + .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[1] ), + .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[1] ), + .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[1] ), + .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[1] ), + .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[1] ), + .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[1] ), + .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[1] ), + .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[1] ), + .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[1] ), + .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[1] ), + .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[1] ), + .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[1] ), + .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[1] ) + ); + + CgraRTL__72d915b46abe89cb cgra__2 + ( + .address_lower( cgra__address_lower[2] ), + .address_upper( cgra__address_upper[2] ), + .cgra_id( cgra__cgra_id[2] ), + .clk( cgra__clk[2] ), + .reset( cgra__reset[2] ), + .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[2] ), + .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[2] ), + .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[2] ), + .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[2] ), + .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[2] ), + .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[2] ), + .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[2] ), + .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[2] ), + .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[2] ), + .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[2] ), + .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[2] ), + .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[2] ), + .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[2] ), + .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[2] ), + .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[2] ), + .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[2] ), + .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[2] ), + .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[2] ), + .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[2] ), + .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[2] ), + .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[2] ), + .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[2] ), + .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[2] ), + .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[2] ), + .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[2] ), + .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[2] ), + .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[2] ), + .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[2] ), + .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[2] ), + .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[2] ), + .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[2] ), + .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[2] ), + .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[2] ), + .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[2] ), + .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[2] ), + .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[2] ) + ); + + CgraRTL__72d915b46abe89cb cgra__3 + ( + .address_lower( cgra__address_lower[3] ), + .address_upper( cgra__address_upper[3] ), + .cgra_id( cgra__cgra_id[3] ), + .clk( cgra__clk[3] ), + .reset( cgra__reset[3] ), + .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[3] ), + .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[3] ), + .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[3] ), + .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[3] ), + .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[3] ), + .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[3] ), + .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[3] ), + .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[3] ), + .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[3] ), + .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[3] ), + .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[3] ), + .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[3] ), + .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[3] ), + .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[3] ), + .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[3] ), + .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[3] ), + .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[3] ), + .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[3] ), + .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[3] ), + .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[3] ), + .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[3] ), + .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[3] ), + .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[3] ), + .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[3] ), + .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[3] ), + .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[3] ), + .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[3] ), + .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[3] ), + .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[3] ), + .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[3] ), + .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[3] ), + .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[3] ), + .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[3] ), + .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[3] ), + .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[3] ), + .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[3] ) + ); + + //------------------------------------------------------------- + // End of component cgra[0:3] + //------------------------------------------------------------- + + //------------------------------------------------------------- + // Component mesh + //------------------------------------------------------------- + + logic [0:0] mesh__clk; + logic [0:0] mesh__reset; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mesh__recv__msg [0:3]; + logic [0:0] mesh__recv__rdy [0:3]; + logic [0:0] mesh__recv__val [0:3]; + InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mesh__send__msg [0:3]; + logic [0:0] mesh__send__rdy [0:3]; + logic [0:0] mesh__send__val [0:3]; + + MeshNetworkRTL__4ca7f469967df194 mesh + ( + .clk( mesh__clk ), + .reset( mesh__reset ), + .recv__msg( mesh__recv__msg ), + .recv__rdy( mesh__recv__rdy ), + .recv__val( mesh__recv__val ), + .send__msg( mesh__send__msg ), + .send__rdy( mesh__send__rdy ), + .send__val( mesh__send__val ) + ); + + //------------------------------------------------------------- + // End of component mesh + //------------------------------------------------------------- + + assign cgra__clk[0] = clk; + assign cgra__reset[0] = reset; + assign cgra__clk[1] = clk; + assign cgra__reset[1] = reset; + assign cgra__clk[2] = clk; + assign cgra__reset[2] = reset; + assign cgra__clk[3] = clk; + assign cgra__reset[3] = reset; + assign mesh__clk = clk; + assign mesh__reset = reset; + assign cgra__recv_from_inter_cgra_noc__msg[0] = mesh__send__msg[0]; + assign mesh__send__rdy[0] = cgra__recv_from_inter_cgra_noc__rdy[0]; + assign cgra__recv_from_inter_cgra_noc__val[0] = mesh__send__val[0]; + assign mesh__recv__msg[0] = cgra__send_to_inter_cgra_noc__msg[0]; + assign cgra__send_to_inter_cgra_noc__rdy[0] = mesh__recv__rdy[0]; + assign mesh__recv__val[0] = cgra__send_to_inter_cgra_noc__val[0]; + assign cgra__recv_from_inter_cgra_noc__msg[1] = mesh__send__msg[1]; + assign mesh__send__rdy[1] = cgra__recv_from_inter_cgra_noc__rdy[1]; + assign cgra__recv_from_inter_cgra_noc__val[1] = mesh__send__val[1]; + assign mesh__recv__msg[1] = cgra__send_to_inter_cgra_noc__msg[1]; + assign cgra__send_to_inter_cgra_noc__rdy[1] = mesh__recv__rdy[1]; + assign mesh__recv__val[1] = cgra__send_to_inter_cgra_noc__val[1]; + assign cgra__recv_from_inter_cgra_noc__msg[2] = mesh__send__msg[2]; + assign mesh__send__rdy[2] = cgra__recv_from_inter_cgra_noc__rdy[2]; + assign cgra__recv_from_inter_cgra_noc__val[2] = mesh__send__val[2]; + assign mesh__recv__msg[2] = cgra__send_to_inter_cgra_noc__msg[2]; + assign cgra__send_to_inter_cgra_noc__rdy[2] = mesh__recv__rdy[2]; + assign mesh__recv__val[2] = cgra__send_to_inter_cgra_noc__val[2]; + assign cgra__recv_from_inter_cgra_noc__msg[3] = mesh__send__msg[3]; + assign mesh__send__rdy[3] = cgra__recv_from_inter_cgra_noc__rdy[3]; + assign cgra__recv_from_inter_cgra_noc__val[3] = mesh__send__val[3]; + assign mesh__recv__msg[3] = cgra__send_to_inter_cgra_noc__msg[3]; + assign cgra__send_to_inter_cgra_noc__rdy[3] = mesh__recv__rdy[3]; + assign mesh__recv__val[3] = cgra__send_to_inter_cgra_noc__val[3]; + assign cgra__cgra_id[0] = 2'd0; + assign cgra__cgra_id[1] = 2'd1; + assign cgra__cgra_id[2] = 2'd2; + assign cgra__cgra_id[3] = 2'd3; + assign cgra__address_lower[0] = 7'd0; + assign cgra__address_upper[0] = 7'd31; + assign cgra__address_lower[1] = 7'd32; + assign cgra__address_upper[1] = 7'd63; + assign cgra__address_lower[2] = 7'd64; + assign cgra__address_upper[2] = 7'd95; + assign cgra__address_lower[3] = 7'd96; + assign cgra__address_upper[3] = 7'd127; + assign cgra__recv_from_cpu_pkt__msg[0] = recv_from_cpu_pkt__msg; + assign recv_from_cpu_pkt__rdy = cgra__recv_from_cpu_pkt__rdy[0]; + assign cgra__recv_from_cpu_pkt__val[0] = recv_from_cpu_pkt__val; + assign send_to_cpu_pkt__msg = cgra__send_to_cpu_pkt__msg[0]; + assign cgra__send_to_cpu_pkt__rdy[0] = send_to_cpu_pkt__rdy; + assign send_to_cpu_pkt__val = cgra__send_to_cpu_pkt__val[0]; + assign cgra__recv_from_cpu_pkt__val[1] = 1'd0; + assign cgra__recv_from_cpu_pkt__msg[1] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign cgra__send_to_cpu_pkt__rdy[1] = 1'd0; + assign cgra__recv_from_cpu_pkt__val[2] = 1'd0; + assign cgra__recv_from_cpu_pkt__msg[2] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign cgra__send_to_cpu_pkt__rdy[2] = 1'd0; + assign cgra__recv_from_cpu_pkt__val[3] = 1'd0; + assign cgra__recv_from_cpu_pkt__msg[3] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; + assign cgra__send_to_cpu_pkt__rdy[3] = 1'd0; + assign cgra__send_data_on_boundary_south__rdy[0][0] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[0][0] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[0][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[0][1] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[0][1] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[0][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[0][2] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[0][2] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[0][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[0][3] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[0][3] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[0][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[0][0] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[0][0] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[0][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[0][1] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[0][1] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[0][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[0][2] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[0][2] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[0][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[0][3] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[0][3] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[0][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[1][0] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[1][0] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[1][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[1][1] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[1][1] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[1][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[1][2] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[1][2] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[1][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_south__rdy[1][3] = 1'd0; + assign cgra__recv_data_on_boundary_south__val[1][3] = 1'd0; + assign cgra__recv_data_on_boundary_south__msg[1][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__recv_data_on_boundary_east__msg[0][0] = cgra__send_data_on_boundary_west__msg[1][0]; + assign cgra__send_data_on_boundary_west__rdy[1][0] = cgra__recv_data_on_boundary_east__rdy[0][0]; + assign cgra__recv_data_on_boundary_east__val[0][0] = cgra__send_data_on_boundary_west__val[1][0]; + assign cgra__recv_data_on_boundary_west__msg[1][0] = cgra__send_data_on_boundary_east__msg[0][0]; + assign cgra__send_data_on_boundary_east__rdy[0][0] = cgra__recv_data_on_boundary_west__rdy[1][0]; + assign cgra__recv_data_on_boundary_west__val[1][0] = cgra__send_data_on_boundary_east__val[0][0]; + assign cgra__recv_data_on_boundary_east__msg[0][1] = cgra__send_data_on_boundary_west__msg[1][1]; + assign cgra__send_data_on_boundary_west__rdy[1][1] = cgra__recv_data_on_boundary_east__rdy[0][1]; + assign cgra__recv_data_on_boundary_east__val[0][1] = cgra__send_data_on_boundary_west__val[1][1]; + assign cgra__recv_data_on_boundary_west__msg[1][1] = cgra__send_data_on_boundary_east__msg[0][1]; + assign cgra__send_data_on_boundary_east__rdy[0][1] = cgra__recv_data_on_boundary_west__rdy[1][1]; + assign cgra__recv_data_on_boundary_west__val[1][1] = cgra__send_data_on_boundary_east__val[0][1]; + assign cgra__recv_data_on_boundary_east__msg[0][2] = cgra__send_data_on_boundary_west__msg[1][2]; + assign cgra__send_data_on_boundary_west__rdy[1][2] = cgra__recv_data_on_boundary_east__rdy[0][2]; + assign cgra__recv_data_on_boundary_east__val[0][2] = cgra__send_data_on_boundary_west__val[1][2]; + assign cgra__recv_data_on_boundary_west__msg[1][2] = cgra__send_data_on_boundary_east__msg[0][2]; + assign cgra__send_data_on_boundary_east__rdy[0][2] = cgra__recv_data_on_boundary_west__rdy[1][2]; + assign cgra__recv_data_on_boundary_west__val[1][2] = cgra__send_data_on_boundary_east__val[0][2]; + assign cgra__recv_data_on_boundary_east__msg[0][3] = cgra__send_data_on_boundary_west__msg[1][3]; + assign cgra__send_data_on_boundary_west__rdy[1][3] = cgra__recv_data_on_boundary_east__rdy[0][3]; + assign cgra__recv_data_on_boundary_east__val[0][3] = cgra__send_data_on_boundary_west__val[1][3]; + assign cgra__recv_data_on_boundary_west__msg[1][3] = cgra__send_data_on_boundary_east__msg[0][3]; + assign cgra__send_data_on_boundary_east__rdy[0][3] = cgra__recv_data_on_boundary_west__rdy[1][3]; + assign cgra__recv_data_on_boundary_west__val[1][3] = cgra__send_data_on_boundary_east__val[0][3]; + assign cgra__send_data_on_boundary_east__rdy[1][0] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[1][0] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[1][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[1][1] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[1][1] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[1][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[1][2] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[1][2] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[1][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[1][3] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[1][3] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[1][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__recv_data_on_boundary_north__msg[0][0] = cgra__send_data_on_boundary_south__msg[2][0]; + assign cgra__send_data_on_boundary_south__rdy[2][0] = cgra__recv_data_on_boundary_north__rdy[0][0]; + assign cgra__recv_data_on_boundary_north__val[0][0] = cgra__send_data_on_boundary_south__val[2][0]; + assign cgra__recv_data_on_boundary_south__msg[2][0] = cgra__send_data_on_boundary_north__msg[0][0]; + assign cgra__send_data_on_boundary_north__rdy[0][0] = cgra__recv_data_on_boundary_south__rdy[2][0]; + assign cgra__recv_data_on_boundary_south__val[2][0] = cgra__send_data_on_boundary_north__val[0][0]; + assign cgra__recv_data_on_boundary_north__msg[0][1] = cgra__send_data_on_boundary_south__msg[2][1]; + assign cgra__send_data_on_boundary_south__rdy[2][1] = cgra__recv_data_on_boundary_north__rdy[0][1]; + assign cgra__recv_data_on_boundary_north__val[0][1] = cgra__send_data_on_boundary_south__val[2][1]; + assign cgra__recv_data_on_boundary_south__msg[2][1] = cgra__send_data_on_boundary_north__msg[0][1]; + assign cgra__send_data_on_boundary_north__rdy[0][1] = cgra__recv_data_on_boundary_south__rdy[2][1]; + assign cgra__recv_data_on_boundary_south__val[2][1] = cgra__send_data_on_boundary_north__val[0][1]; + assign cgra__recv_data_on_boundary_north__msg[0][2] = cgra__send_data_on_boundary_south__msg[2][2]; + assign cgra__send_data_on_boundary_south__rdy[2][2] = cgra__recv_data_on_boundary_north__rdy[0][2]; + assign cgra__recv_data_on_boundary_north__val[0][2] = cgra__send_data_on_boundary_south__val[2][2]; + assign cgra__recv_data_on_boundary_south__msg[2][2] = cgra__send_data_on_boundary_north__msg[0][2]; + assign cgra__send_data_on_boundary_north__rdy[0][2] = cgra__recv_data_on_boundary_south__rdy[2][2]; + assign cgra__recv_data_on_boundary_south__val[2][2] = cgra__send_data_on_boundary_north__val[0][2]; + assign cgra__recv_data_on_boundary_north__msg[0][3] = cgra__send_data_on_boundary_south__msg[2][3]; + assign cgra__send_data_on_boundary_south__rdy[2][3] = cgra__recv_data_on_boundary_north__rdy[0][3]; + assign cgra__recv_data_on_boundary_north__val[0][3] = cgra__send_data_on_boundary_south__val[2][3]; + assign cgra__recv_data_on_boundary_south__msg[2][3] = cgra__send_data_on_boundary_north__msg[0][3]; + assign cgra__send_data_on_boundary_north__rdy[0][3] = cgra__recv_data_on_boundary_south__rdy[2][3]; + assign cgra__recv_data_on_boundary_south__val[2][3] = cgra__send_data_on_boundary_north__val[0][3]; + assign cgra__send_data_on_boundary_north__rdy[2][0] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[2][0] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[2][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[2][1] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[2][1] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[2][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[2][2] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[2][2] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[2][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[2][3] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[2][3] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[2][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[2][0] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[2][0] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[2][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[2][1] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[2][1] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[2][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[2][2] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[2][2] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[2][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_west__rdy[2][3] = 1'd0; + assign cgra__recv_data_on_boundary_west__val[2][3] = 1'd0; + assign cgra__recv_data_on_boundary_west__msg[2][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__recv_data_on_boundary_north__msg[1][0] = cgra__send_data_on_boundary_south__msg[3][0]; + assign cgra__send_data_on_boundary_south__rdy[3][0] = cgra__recv_data_on_boundary_north__rdy[1][0]; + assign cgra__recv_data_on_boundary_north__val[1][0] = cgra__send_data_on_boundary_south__val[3][0]; + assign cgra__recv_data_on_boundary_south__msg[3][0] = cgra__send_data_on_boundary_north__msg[1][0]; + assign cgra__send_data_on_boundary_north__rdy[1][0] = cgra__recv_data_on_boundary_south__rdy[3][0]; + assign cgra__recv_data_on_boundary_south__val[3][0] = cgra__send_data_on_boundary_north__val[1][0]; + assign cgra__recv_data_on_boundary_north__msg[1][1] = cgra__send_data_on_boundary_south__msg[3][1]; + assign cgra__send_data_on_boundary_south__rdy[3][1] = cgra__recv_data_on_boundary_north__rdy[1][1]; + assign cgra__recv_data_on_boundary_north__val[1][1] = cgra__send_data_on_boundary_south__val[3][1]; + assign cgra__recv_data_on_boundary_south__msg[3][1] = cgra__send_data_on_boundary_north__msg[1][1]; + assign cgra__send_data_on_boundary_north__rdy[1][1] = cgra__recv_data_on_boundary_south__rdy[3][1]; + assign cgra__recv_data_on_boundary_south__val[3][1] = cgra__send_data_on_boundary_north__val[1][1]; + assign cgra__recv_data_on_boundary_north__msg[1][2] = cgra__send_data_on_boundary_south__msg[3][2]; + assign cgra__send_data_on_boundary_south__rdy[3][2] = cgra__recv_data_on_boundary_north__rdy[1][2]; + assign cgra__recv_data_on_boundary_north__val[1][2] = cgra__send_data_on_boundary_south__val[3][2]; + assign cgra__recv_data_on_boundary_south__msg[3][2] = cgra__send_data_on_boundary_north__msg[1][2]; + assign cgra__send_data_on_boundary_north__rdy[1][2] = cgra__recv_data_on_boundary_south__rdy[3][2]; + assign cgra__recv_data_on_boundary_south__val[3][2] = cgra__send_data_on_boundary_north__val[1][2]; + assign cgra__recv_data_on_boundary_north__msg[1][3] = cgra__send_data_on_boundary_south__msg[3][3]; + assign cgra__send_data_on_boundary_south__rdy[3][3] = cgra__recv_data_on_boundary_north__rdy[1][3]; + assign cgra__recv_data_on_boundary_north__val[1][3] = cgra__send_data_on_boundary_south__val[3][3]; + assign cgra__recv_data_on_boundary_south__msg[3][3] = cgra__send_data_on_boundary_north__msg[1][3]; + assign cgra__send_data_on_boundary_north__rdy[1][3] = cgra__recv_data_on_boundary_south__rdy[3][3]; + assign cgra__recv_data_on_boundary_south__val[3][3] = cgra__send_data_on_boundary_north__val[1][3]; + assign cgra__send_data_on_boundary_north__rdy[3][0] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[3][0] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[3][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[3][1] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[3][1] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[3][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[3][2] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[3][2] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[3][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_north__rdy[3][3] = 1'd0; + assign cgra__recv_data_on_boundary_north__val[3][3] = 1'd0; + assign cgra__recv_data_on_boundary_north__msg[3][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__recv_data_on_boundary_east__msg[2][0] = cgra__send_data_on_boundary_west__msg[3][0]; + assign cgra__send_data_on_boundary_west__rdy[3][0] = cgra__recv_data_on_boundary_east__rdy[2][0]; + assign cgra__recv_data_on_boundary_east__val[2][0] = cgra__send_data_on_boundary_west__val[3][0]; + assign cgra__recv_data_on_boundary_west__msg[3][0] = cgra__send_data_on_boundary_east__msg[2][0]; + assign cgra__send_data_on_boundary_east__rdy[2][0] = cgra__recv_data_on_boundary_west__rdy[3][0]; + assign cgra__recv_data_on_boundary_west__val[3][0] = cgra__send_data_on_boundary_east__val[2][0]; + assign cgra__recv_data_on_boundary_east__msg[2][1] = cgra__send_data_on_boundary_west__msg[3][1]; + assign cgra__send_data_on_boundary_west__rdy[3][1] = cgra__recv_data_on_boundary_east__rdy[2][1]; + assign cgra__recv_data_on_boundary_east__val[2][1] = cgra__send_data_on_boundary_west__val[3][1]; + assign cgra__recv_data_on_boundary_west__msg[3][1] = cgra__send_data_on_boundary_east__msg[2][1]; + assign cgra__send_data_on_boundary_east__rdy[2][1] = cgra__recv_data_on_boundary_west__rdy[3][1]; + assign cgra__recv_data_on_boundary_west__val[3][1] = cgra__send_data_on_boundary_east__val[2][1]; + assign cgra__recv_data_on_boundary_east__msg[2][2] = cgra__send_data_on_boundary_west__msg[3][2]; + assign cgra__send_data_on_boundary_west__rdy[3][2] = cgra__recv_data_on_boundary_east__rdy[2][2]; + assign cgra__recv_data_on_boundary_east__val[2][2] = cgra__send_data_on_boundary_west__val[3][2]; + assign cgra__recv_data_on_boundary_west__msg[3][2] = cgra__send_data_on_boundary_east__msg[2][2]; + assign cgra__send_data_on_boundary_east__rdy[2][2] = cgra__recv_data_on_boundary_west__rdy[3][2]; + assign cgra__recv_data_on_boundary_west__val[3][2] = cgra__send_data_on_boundary_east__val[2][2]; + assign cgra__recv_data_on_boundary_east__msg[2][3] = cgra__send_data_on_boundary_west__msg[3][3]; + assign cgra__send_data_on_boundary_west__rdy[3][3] = cgra__recv_data_on_boundary_east__rdy[2][3]; + assign cgra__recv_data_on_boundary_east__val[2][3] = cgra__send_data_on_boundary_west__val[3][3]; + assign cgra__recv_data_on_boundary_west__msg[3][3] = cgra__send_data_on_boundary_east__msg[2][3]; + assign cgra__send_data_on_boundary_east__rdy[2][3] = cgra__recv_data_on_boundary_west__rdy[3][3]; + assign cgra__recv_data_on_boundary_west__val[3][3] = cgra__send_data_on_boundary_east__val[2][3]; + assign cgra__send_data_on_boundary_east__rdy[3][0] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[3][0] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[3][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[3][1] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[3][1] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[3][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[3][2] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[3][2] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[3][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + assign cgra__send_data_on_boundary_east__rdy[3][3] = 1'd0; + assign cgra__recv_data_on_boundary_east__val[3][3] = 1'd0; + assign cgra__recv_data_on_boundary_east__msg[3][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; + +endmodule From 95b5edfd16f0eaa7b2236fc79c0dbfadb54166e8 Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Sat, 3 Jan 2026 02:02:01 -0600 Subject: [PATCH 04/12] [SV tb] Adding hand-coded tb. --- ...iCgraRTL_2x2_fir_vector_global_reduce_tb.v | 1315 +++++++++++++++++ 1 file changed, 1315 insertions(+) create mode 100644 multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v diff --git a/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v b/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v new file mode 100644 index 00000000..6d9c3a83 --- /dev/null +++ b/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v @@ -0,0 +1,1315 @@ +`timescale 1ps/1ps + +`include "header.sv" + +// vcs -sverilog -full64 -timescale=1ns/1ps ../MeshMultiCgraRTL__explicit__pickled.v MeshMultiCgraRTL_2x2_fir_scalar_tb.v -debug_access+all + +module cgra_test +( +); + + logic [0:0] clk; + logic [0:0] reset; + + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__432fde8bfb7da0ed recv_from_cpu_pkt__msg; + logic [0:0] recv_from_cpu_pkt__rdy; + logic [0:0] recv_from_cpu_pkt__val; + + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__432fde8bfb7da0ed send_to_cpu_pkt__msg; + logic [0:0] send_to_cpu_pkt__rdy; + logic [0:0] send_to_cpu_pkt__val; + + MeshMultiCgraRTL__explicit MultiCGRA (.*); + + int PASS = 'd0; + time pass_time_of = 'd0; + + initial + begin + $display("\nTEST begin\n"); + + clk = 1'b0; + recv_from_cpu_pkt__val = 1'b0; + send_to_cpu_pkt__rdy = 1'b1; + + reset = 1'b0; + #7 + reset = 1'b1; + #50 + reset = 1'b0; + #10 +/* +typedef struct packed { + logic [4:0] src; + logic [4:0] dst; + logic [1:0] src_cgra_id; + logic [1:0] dst_cgra_id; + logic [0:0] src_cgra_x; + logic [0:0] src_cgra_y; + logic [0:0] dst_cgra_x; + logic [0:0] dst_cgra_y; + logic [7:0] opaque; + logic [0:0] vc_id; + MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__d9140faa89010e06 payload; +} IntraCgraPacket_4_2x2_16_8_2_CgraPayload__432fde8bfb7da0ed; +*/ +/* +typedef struct packed { + logic [4:0] cmd; + CgraData_32_1_1_1__payload_32__predicate_1__bypass_1__delay_1 data; + logic [6:0] data_addr; + CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 ctrl; + logic [3:0] ctrl_addr; +} MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__d9140faa89010e06; +*/ +/* +typedef struct packed { + logic [31:0] payload; + logic [0:0] predicate; + logic [0:0] bypass; + logic [0:0] delay; +} CgraData_32_1_1_1__payload_32__predicate_1__bypass_1__delay_1; +*/ +/* +typedef struct packed { + logic [6:0] operation; + logic [3:0][2:0] fu_in; + logic [7:0][2:0] routing_xbar_outport; + logic [7:0][1:0] fu_xbar_outport; + logic [2:0] vector_factor_power; + logic [0:0] is_last_ctrl; + logic [3:0][1:0] write_reg_from; + logic [3:0][3:0] write_reg_idx; + logic [3:0][0:0] read_reg_from; + logic [3:0][3:0] read_reg_idx; +} CGRAConfig_7_4_2_4_4_3__49d22cda396bec88; +*/ + + // Preload data. + #10 // CMD_STORE_REQUEST/ + recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h0001000100010001, 1, 0, 0); + recv_from_cpu_pkt__val = 1'b1; + #10 + recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h0001000100010001, 1, 1, 0); + #10 + recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h000f000e000d000c, 1, 2, 0); + #10 + recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h0013001200110010, 1, 3, 0); + #10 + recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h00110010000f000e, 1, 4, 0); + #10 + recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h0015001400130012, 1, 5, 0); + #10 + recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h0001000100010001, 1, 6, 0); + + // Tile 0. + #10 // CMD_CONST. + recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 13, 3, 1, 0, 0); + #10 // CMD_CONFIG_COUNT_PER_ITER. + recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 8, 4, 1, 0, 0); + #10 // CMD_CONFIG_TOTAL_CTRL_COUNT + recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 7, 'd42, 1, 0, 0); + #10 // CMD_CONFIG - OPT_ADD. + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt(0, 0, 3, 2, + '{3'd4, 3'd3, 3'd2, 3'd1}, + '{3'd0, 3'd0, 3'd0, 3'd1, 3'd0, 3'd0, 3'd0, 3'd0}, + '{2'd0, 2'd0, 2'd0, 2'd1, 2'd1, 2'd0, 2'd0, 2'd0}, + '{2'd0, 2'd0, 2'd0, 2'd2}, + '{1'd0, 1'd0, 1'd1, 1'd0}, + '{4'd0, 4'd0, 4'd0, 4'd0}, + '{4'd0, 4'd0, 4'd0, 4'd0}, + 0); + #10 // CMD_CONFIG - OPT_PHI_CONST. + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt(0, 0, 3, 32, + '{3'd4, 3'd3, 3'd2, 3'd1}, + '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, // routing_xbar_outport (TileInType list) + '{2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, // fu_xbar_outport (FuOutType list) + '{2'd0, 2'd0, 2'd2, 2'd0}, // write_reg_from (b2(0), b2(2), ...) + '{1'd0, 1'd0, 1'd0, 1'd1}, // read_reg_from + '{ default: 4'd0 }, // write_reg_idx (not specified, zeroed) + '{ default: 4'd0 }, // read_reg_idx (not specified, zeroed) + 1); // ctrl_addr = 1 + #10 // CMD_CONFIG - OPT_NAH. + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt(0, 0, 3, 1, + '{3'd4, 3'd3, 3'd2, 3'd1}, + '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0}, + '{1'd0, 1'd0, 1'd0, 1'd0}, + '{ default: 4'd0 }, + '{ default: 4'd0 }, + 2); + #10 // CMD_CONFIG - OPT_NAH. + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt(0, 0, 3, 1, + '{3'd4, 3'd3, 3'd2, 3'd1}, + '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0}, + '{1'd0, 1'd0, 1'd0, 1'd0}, + '{ default: 4'd0 }, + '{ default: 4'd0 }, + 3); + #10 // CMD_CONFIG_PROLOGUE_FU. + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 4, 0, + '{3'd0, 3'd0, 3'd0, 3'd0}, + '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0}, + '{1'd0, 1'd0, 1'd0, 1'd0}, + '{ default: 4'd0 }, + '{ default: 4'd0 }, + 0, + 1, + 1, + 0); + //#10 // CMD_CONFIG_PROLOGUE_FU. + //recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 4, 0, + // '{3'd0, 3'd0, 3'd0, 3'd0}, + // '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, + // '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, + // '{2'd0, 2'd0, 2'd0, 2'd0}, + // '{1'd0, 1'd0, 1'd0, 1'd0}, + // '{ default: 4'd0 }, + // '{ default: 4'd0 }, + // 1, + // 1, + // 1, + // 0); + #10 // CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR. + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 6, 0, + '{3'd0, 3'd0, 3'd0, 3'd0}, + '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0}, + '{1'd0, 1'd0, 1'd0, 1'd0}, + '{ default: 4'd0 }, + '{ default: 4'd0 }, + 0, + 1, + 1, + 0); + #10 // CMD_CONFIG_PROLOGUE_FU_CROSSBAR. + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 5, 0, + '{3'd0, 3'd0, 3'd0, 3'd0}, + '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0}, + '{1'd0, 1'd0, 1'd0, 1'd0}, + '{ default: 4'd0 }, + '{ default: 4'd0 }, + 0, + 1, + 1, + 0); + //#10 // CMD_CONFIG_PROLOGUE_FU_CROSSBAR. + //recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 5, 0, + // '{3'd0, 3'd0, 3'd0, 3'd0}, + // '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, + // '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, + // '{2'd0, 2'd0, 2'd0, 2'd0}, + // '{1'd0, 1'd0, 1'd0, 1'd0}, + // '{ default: 4'd0 }, + // '{ default: 4'd0 }, + // 1, + // 1, + // 1, + // 0); + #10 // CMD_LAUNCH. + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 0, 0, + '{3'd0, 3'd0, 3'd0, 3'd0}, + '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, + '{2'd0, 2'd0, 2'd0, 2'd0}, + '{1'd0, 1'd0, 1'd0, 1'd0}, + '{ default: 4'd0 }, + '{ default: 4'd0 }, + 0, + 0, + 0, + 0); + + // Tile 1. + #10 //CMD_CONFIG_COUNT_PER_ITER + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd8), // CMD_CONFIG_COUNT_PER_ITER = 8 + .operation(7'd0), + .fu_in_code('{default:3'd0}), + .routing_xbar_outport('{default:3'd0}), + .fu_xbar_outport('{default:2'd0}), + .write_reg_from('{default:2'd0}), + .read_reg_from('{default:1'd0}), + .write_reg_idx('{default:4'd0}), + .read_reg_idx('{default:4'd0}), + .ctrl_addr(4'd0), + .data(32'd4), // kCtrlCountPerIter = 4 + .pred(1'd1), // predicate = 1 + .data_addr(7'd0) + ); + #10 + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd7), // CMD_CONFIG_TOTAL_CTRL_COUNT = 7 + .operation(7'd0), + .fu_in_code('{default:3'd0}), + .routing_xbar_outport('{default:3'd0}), + .fu_xbar_outport('{default:2'd0}), + .write_reg_from('{default:2'd0}), + .read_reg_from('{default:1'd0}), + .write_reg_idx('{default:4'd0}), + .read_reg_idx('{default:4'd0}), + .ctrl_addr(4'd0), + .data(32'd42), // kTotalCtrlSteps = 42 + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd3), // CMD_CONFIG = 3 + .operation(7'd1), // OPT_NAH 1 + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{default:3'd0}), + .fu_xbar_outport('{default:2'd0}), + .write_reg_from('{default:2'd0}), + .read_reg_from('{default:1'd0}), + .write_reg_idx('{default:4'd0}), + .read_reg_idx('{default:4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd3), + .operation(7'd16), // OPT_GRT_PRED = 16 + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd1, 3'd3, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd2}), + .read_reg_from('{default:1'd0}), + .write_reg_idx('{default:4'd0}), + .read_reg_idx('{default:4'd0}), + .ctrl_addr(4'd1), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // OPT_RET (OPT_RET = 35) + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd3), + .operation(7'd35), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}), + .fu_xbar_outport('{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}), + .write_reg_from('{2'd0,2'd0,2'd0,2'd0}), + .read_reg_from('{1'b0, 1'b0, 1'b0, 1'b1}), + .write_reg_idx('{4'd0,4'd0,4'd0,4'd0}), + .read_reg_idx('{4'd0,4'd0,4'd0,4'd0}), + .ctrl_addr(4'd2), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // NAH again (OPT_NAH = 1) + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd3), + .operation(7'd1), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}), + .fu_xbar_outport('{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}), + .write_reg_from('{2'd0,2'd0,2'd0,2'd0}), + .read_reg_from('{1'd0,1'd0,1'd0,1'd0}), + .write_reg_idx('{4'd0,4'd0,4'd0,4'd0}), + .read_reg_idx('{4'd0,4'd0,4'd0,4'd0}), + .ctrl_addr(4'd3), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CONFIG_PROLOGUE_FU (ctrl_addr = 1) + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd4), + .operation(7'd0), + .fu_in_code('{default:3'd0}), + .routing_xbar_outport('{default:3'd0}), + .fu_xbar_outport('{default:2'd0}), + .write_reg_from('{default:2'd0}), + .read_reg_from('{default:1'd0}), + .write_reg_idx('{default:4'd0}), + .read_reg_idx('{default:4'd0}), + .ctrl_addr(4'd1), + .data(32'd1), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CONFIG_PROLOGUE_FU (ctrl_addr = 2) + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd4), + .operation(7'd0), + .fu_in_code('{default:3'd0}), + .routing_xbar_outport('{default:3'd0}), + .fu_xbar_outport('{default:2'd0}), + .write_reg_from('{default:2'd0}), + .read_reg_from('{default:1'd0}), + .write_reg_idx('{default:4'd0}), + .read_reg_idx('{default:4'd0}), + .ctrl_addr(4'd2), + .data(32'd1), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CONFIG_PROLOGUE_ROUTING_CROSSBAR (all 0) + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd6), + .operation(7'd0), + .fu_in_code('{default:3'd0}), + .routing_xbar_outport('{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}), + .fu_xbar_outport('{default:2'd0}), + .write_reg_from('{default:2'd0}), + .read_reg_from('{default:1'd0}), + .write_reg_idx('{default:4'd0}), + .read_reg_idx('{default:4'd0}), + .ctrl_addr(4'd1), + .data(32'd1), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CONFIG_PROLOGUE_ROUTING_CROSSBAR (first routing = 2) + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd6), + .operation(7'd0), + .fu_in_code('{default:3'd0}), + .routing_xbar_outport('{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd2}), + .fu_xbar_outport('{default:2'd0}), + .write_reg_from('{default:2'd0}), + .read_reg_from('{default:1'd0}), + .write_reg_idx('{default:4'd0}), + .read_reg_idx('{default:4'd0}), + .ctrl_addr(4'd1), + .data(32'd1), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CONFIG_PROLOGUE_FU_CROSSBAR (ctrl_addr = 1) + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd5), + .operation(7'd0), + .fu_in_code('{default:3'd0}), + .routing_xbar_outport('{default:3'd0}), + .fu_xbar_outport('{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}), + .write_reg_from('{default:2'd0}), + .read_reg_from('{default:1'd0}), + .write_reg_idx('{default:4'd0}), + .read_reg_idx('{default:4'd0}), + .ctrl_addr(4'd1), + .data(32'd1), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_LAUNCH + recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd1), + .cmd(5'd0), + .operation(7'd0), + .fu_in_code('{default:3'd0}), + .routing_xbar_outport('{default:3'd0}), + .fu_xbar_outport('{default:2'd0}), + .write_reg_from('{default:2'd0}), + .read_reg_from('{default:1'd0}), + .write_reg_idx('{default:4'd0}), + .read_reg_idx('{default:4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + //////////// + // Tile 4 // + //////////// + #10 + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd4), + .cmd(5'd13), // CMD_CONST + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), // write_reg_from_code (do not reverse) + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), // read_reg_from_code (do not reverse) + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd2), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG_COUNT_PER_ITER + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd4), + .cmd(5'd8), // CMD_CONFIG_COUNT_PER_ITER + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd4), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG_TOTAL_CTRL_COUNT + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd4), + .cmd(5'd7), // CMD_CONFIG_TOTAL_CTRL_COUNT + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd42), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=0, OPT_NAH + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd4), + .cmd(5'd3), // CMD_CONFIG + .operation(7'd1), // OPT_NAH + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + // reverse of [0,0,0,0,0,0,0,0] is itself + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + // reverse of [0,0,0,0,0,0,0,0] is itself + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), // keep provided code + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), // keep provided code + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=1, OPT_ADD_CONST + // routing: reverse of [0,0,0,0,1,0,0,0] -> [0,0,0,1,0,0,0,0] + // fu_xbar : reverse of [0,0,0,0,1,0,0,0] -> [0,0,0,1,0,0,0,0] + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd4), + .cmd(5'd3), // CMD_CONFIG + .operation(7'd25), // OPT_ADD_CONST + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd1, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd2}), // write_reg_from_code (keep order) + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), // read_reg_from_code + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd1), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=2, OPT_LD + // fu_xbar : reverse of [0,0,0,0,0,1,0,0] -> [0,0,1,0,0,0,0,0] + // write_reg_from inline [0,2,0,0] -> reverse -> [0,0,2,0] + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd4), + .cmd(5'd3), // CMD_CONFIG + .operation(7'd12), // OPT_LD + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd2, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd1}), // read_reg_from_code + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd2), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=3, OPT_MUL + // routing: reverse of [0,0,0,0,1,0,0,0] -> [0,0,0,1,0,0,0,0] + // fu_xbar : reverse of [0,1,0,0,0,0,0,0] -> [0,0,0,0,0,0,1,0] + // read_reg_from inline [0,1,0,0] -> reverse -> [0,0,1,0] + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd4), + .cmd(5'd3), // CMD_CONFIG + .operation(7'd7), // OPT_MUL + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd1, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd1, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd1, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd3), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_LAUNCH + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd4), + .cmd(5'd0), // CMD_LAUNCH + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + //////////// + // Tile 5 // + //////////// + #10 + // CMD_CONST (kLoopUpperBound, pred=1) + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd5), + .cmd(5'd13), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd10), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG_COUNT_PER_ITER (kCtrlCountPerIter, pred=1) + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd5), + .cmd(5'd8), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd4), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG_TOTAL_CTRL_COUNT (kTotalCtrlSteps, pred=1) + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd5), + .cmd(5'd7), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd42), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=0, OPT_NAH + // (explicit arrays reversed; provided *_code arrays kept as-is) + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd5), + .cmd(5'd3), + .operation(7'd1), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=1, OPT_NAH + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd5), + .cmd(5'd3), + .operation(7'd1), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd1), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=2, OPT_NE_CONST (CMP) + // routing [0,0,0,0,1,0,0,0] -> reversed -> [0,0,0,1,0,0,0,0] + // fu_xbar [1,0,0,0,1,0,0,0] -> reversed -> [0,0,0,0,1,0,0,1] + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd5), + .cmd(5'd3), + .operation(7'd46), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd1, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd1}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd2}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd2), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=3, OPT_NOT + // routing [0,1,0,0,0,0,0,0] -> reversed -> [0,0,0,0,0,0,1,0] + // fu_xbar [0,1,0,0,0,0,0,0] -> reversed -> [0,0,0,0,0,0,1,0] + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd5), + .cmd(5'd3), + .operation(7'd11), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd1, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd1}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd3), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_LAUNCH + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd5), + .cmd(5'd0), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + //////////// + // Tile 8 // + //////////// + #10 + // CMD_CONST (kLoopLowerBound, pred=1) — for PHI_CONST + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd8), + .cmd(5'd13), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd2), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONST (kInputBaseAddress, pred=1) — for ADD_CONST + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd8), + .cmd(5'd13), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG_COUNT_PER_ITER (kCtrlCountPerIter, pred=1) + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd8), + .cmd(5'd8), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd4), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG_TOTAL_CTRL_COUNT (kTotalCtrlSteps, pred=1) + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd8), + .cmd(5'd7), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd42), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=0, OPT_PHI_CONST + // routing [0,0,0,0,4,0,0,0] -> reversed -> [0,0,0,4,0,0,0,0] + // fu_xbar [0,1,0,1,1,0,0,0] -> reversed -> [0,0,0,1,1,0,1,0] + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd8), + .cmd(5'd3), + .operation(7'd32), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd4, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd1, 2'd1, 2'd0, 2'd1, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd2}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=1, OPT_ADD_CONST + // fu_xbar [0,0,0,0,0,1,0,0] -> reversed -> [0,0,1,0,0,0,0,0] + // write_reg_from inline [0,2,0,0] -> reversed -> [0,0,2,0] + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd8), + .cmd(5'd3), + .operation(7'd25), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd2, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd1}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd1), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=2, OPT_LD + // fu_in_code inline [2,0,0,0] -> reversed -> [0,0,0,2] + // fu_xbar [0,1,0,0,0,0,0,0] -> reversed -> [0,0,0,0,0,0,1,0] + // read_reg_from inline [0,1,0,0] -> reversed -> [0,0,1,0] + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd8), + .cmd(5'd3), + .operation(7'd12), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd2}), // Hand-coded. + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd1, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd1, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd2), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=3, OPT_NAH + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd8), + .cmd(5'd3), + .operation(7'd1), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd3), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR @ ctrl_addr=0, data=1 (pred=1) + // routing [3,0,0,0,0,0,0,0] -> reversed -> [0,0,0,0,0,0,0,3] + // (unspecified args default to zeros) + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd8), + .cmd(5'd6), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd3}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd1), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_LAUNCH + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd8), + .cmd(5'd0), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + //////////// + // Tile 9 // + //////////// + #10 + // CMD_CONST (kLoopIncrement, pred=1) — for ADD_CONST + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd9), + .cmd(5'd13), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd1), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG_COUNT_PER_ITER (kCtrlCountPerIter, pred=1) + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd9), + .cmd(5'd8), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd4), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG_TOTAL_CTRL_COUNT (kTotalCtrlSteps, pred=1) + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd9), + .cmd(5'd7), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd42), + .pred(1'd1), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=0, OPT_NAH + // routing [0,0,0,0,0,0,0,0] -> reversed -> same + // fu_xbar [0,0,0,0,0,0,0,0] -> reversed -> same + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd9), + .cmd(5'd3), + .operation(7'd1), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=1, OPT_ADD_CONST + // routing [0,0,0,0,3,0,0,0] -> reversed -> [0,0,0,3,0,0,0,0] + // fu_xbar [0,1,0,0,0,1,0,0] -> reversed -> [0,0,1,0,0,0,1,0] + // write_reg_from inline [0,2,0,0] -> reversed -> [0,0,2,0] + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd9), + .cmd(5'd3), + .operation(7'd25), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd3, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd1, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd2, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd1), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=2, OPT_NAH + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd9), + .cmd(5'd3), + .operation(7'd1), + .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd2), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_CONFIG @ ctrl_addr=3, OPT_GRT_PRED + // fu_in [2,1,0,0] . -> reversed -> [0,0,1,2] + // routing [0,0,0,0,2,0,0,0] -> reversed -> [0,0,0,2,0,0,0,0] + // fu_xbar [0,0,1,0,0,0,0,0] -> reversed -> [0,0,0,0,0,1,0,0] + // read_reg_from [0,1,0,0] -> reversed -> [0,0,1,0] + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd9), + .cmd(5'd3), + .operation(7'd16), + .fu_in_code('{3'd0, 3'd0, 3'd1, 3'd2}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd2, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd1, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd1, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd3), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + #10 + // CMD_LAUNCH + recv_from_cpu_pkt__msg = + make_intra_cgra_config_pkt_w_data( + .src(5'd0), + .dst(5'd9), + .cmd(5'd0), + .operation(7'd0), + .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), + .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), + .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), + .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), + .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), + .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), + .ctrl_addr(4'd0), + .data(32'd0), + .pred(1'd0), + .data_addr(7'd0) + ); + + + #10 + recv_from_cpu_pkt__val = 0; + + #3000 + + if ('d1 == PASS) $display("TEST PASSED at %0t.", pass_time_of); + else $display("TEST FAILED at %0t.", $time); + + $display("#########cgra 0 tile 0 cnst mem#################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__0.const_mem.reg_file.regs[i]) ) + $display("cgra0tile0cnst %d %d %d (%d)", i, MultiCGRA.cgra__0.tile__0.const_mem.reg_file.regs[i].payload, MultiCGRA.cgra__0.tile__0.const_mem.reg_file.regs[i].predicate, MultiCGRA.cgra__0.tile__0.const_mem.reg_file.regs[i]); + end + $display("##########################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__1.const_mem.reg_file.regs[i]) ) + $display("cgra0tile1cnst %d %d", i, MultiCGRA.cgra__0.tile__1.const_mem.reg_file.regs[i]); + end + $display("##########################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__4.const_mem.reg_file.regs[i]) ) + $display("cgra0tile4cnst %d %d", i, MultiCGRA.cgra__0.tile__4.const_mem.reg_file.regs[i]); + end + $display("##########################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__5.const_mem.reg_file.regs[i]) ) + $display("cgra0tile5cnst %d %d", i, MultiCGRA.cgra__0.tile__5.const_mem.reg_file.regs[i]); + end + $display("##########################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__8.const_mem.reg_file.regs[i]) ) + $display("cgra0tile8cnst %d %d", i, MultiCGRA.cgra__0.tile__8.const_mem.reg_file.regs[i]); + end + $display("##########################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__9.const_mem.reg_file.regs[i]) ) + $display("cgra0tile9cnst %d %d", i, MultiCGRA.cgra__0.tile__9.const_mem.reg_file.regs[i]); + end + + $display("********cgra 0 ctrl mem******************"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__0.ctrl_mem.reg_file.regs[i]) ) + $display("cgra0tile0ctrl %d %d", i, MultiCGRA.cgra__0.tile__0.ctrl_mem.reg_file.regs[i]); + end + $display("##########################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__1.ctrl_mem.reg_file.regs[i]) ) + $display("cgra0tile1ctrl %d %d", i, MultiCGRA.cgra__0.tile__1.ctrl_mem.reg_file.regs[i]); + end + $display("##########################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__4.ctrl_mem.reg_file.regs[i]) ) + $display("cgra0tile4ctrl %d %d", i, MultiCGRA.cgra__0.tile__4.ctrl_mem.reg_file.regs[i]); + end + $display("##########################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__5.ctrl_mem.reg_file.regs[i]) ) + $display("cgra0tile5ctrl %d %d", i, MultiCGRA.cgra__0.tile__5.ctrl_mem.reg_file.regs[i]); + end + $display("##########################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__8.ctrl_mem.reg_file.regs[i]) ) + $display("cgra0tile8ctrl %d %d", i, MultiCGRA.cgra__0.tile__8.ctrl_mem.reg_file.regs[i]); + end + $display("##########################"); + for (int i = 0; i < 512; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.tile__9.ctrl_mem.reg_file.regs[i]) ) + $display("cgra0tile9ctrl %d %d", i, MultiCGRA.cgra__0.tile__9.ctrl_mem.reg_file.regs[i]); + end + + $display("*************cgra0 data mem 0*************"); + for (int i = 0; i < 16; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.data_mem.memory_wrapper__0.memory.regs[i]) ) + $display("cgra0regfile0 (addr 0 init) %d %d (%d)", i, MultiCGRA.cgra__0.data_mem.memory_wrapper__0.memory.regs[i].payload, MultiCGRA.cgra__0.data_mem.memory_wrapper__0.memory.regs[i]); + end + $display("#############cgra0 data mem 1#############"); + for (int i = 0; i < 16; i++) + begin + if ( !$isunknown(MultiCGRA.cgra__0.data_mem.memory_wrapper__1.memory.regs[i]) ) + $display("cgra0regfile1 (addr 0 init) %d %d", i, MultiCGRA.cgra__0.data_mem.memory_wrapper__1.memory.regs[i]); + end + + $finish(); + end + + initial + forever + begin + #5 + clk = ~clk; + end + + always @ (posedge clk or negedge clk) + begin + #1 + + if ( send_to_cpu_pkt__val && ( ('d2212 * 'd2 + 'd3) == send_to_cpu_pkt__msg.payload.data.payload ) ) + begin + PASS = 'd1; + pass_time_of = $time; + end + end + + /*initial + begin + $dumpfile("./output.vcd"); + $dumpvars (0, cgra_test); + end*/ + // The Verilator test fails on these $fsdb* functions; if pragmas do not work, add --bbox-sys to Verilator cmd. +`ifndef VERILATOR + initial + begin + $fsdbDumpfile("./output.fsdb"); + $fsdbDumpvars ("+all", "cgra_test"); + $fsdbDumpMDA; + $fsdbDumpSVA; + end +`endif + + +endmodule + From 730cb5eb0e42362feeb778c9b2cdaad0b64a5d34 Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Tue, 6 Jan 2026 15:37:04 -0600 Subject: [PATCH 05/12] [PyMTL SV tb] Remove x-chk fail. --- ...1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v index 3abd9dd5..4216cc64 100644 --- a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v +++ b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v @@ -27,7 +27,7 @@ cycle_count += 1; \ $fatal; -`define CHECK(lineno, out, ref, port_name) \ +`define CHECK2(lineno, out, ref, port_name) \ if ((|(out ^ out)) == 1'b0) ; \ else begin \ $display(""); \ @@ -42,6 +42,13 @@ `VTB_TEST_FAIL(lineno, out, ref, port_name) \ end +`define CHECK(lineno, out, ref, port_name) \ + if (out != ref) begin \ + $display(""); \ + $display("The test bench received an incorrect value!"); \ + `VTB_TEST_FAIL(lineno, out, ref, port_name) \ + end + module MeshMultiCgraRTL__975ce70dc1a0740a_tb; // convention logic clk; From 9cf56edb80f62839302dbf391e686d5632ae27b2 Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Tue, 6 Jan 2026 15:40:06 -0600 Subject: [PATCH 06/12] [SV tb] Add real cfg vectors and updated CGRA RTL instantiation, data types. --- ...iCgraRTL_2x2_fir_vector_global_reduce_tb.v | 1339 +++-------------- 1 file changed, 248 insertions(+), 1091 deletions(-) diff --git a/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v b/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v index 6d9c3a83..e8d80ccb 100644 --- a/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v +++ b/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v @@ -1,6 +1,6 @@ `timescale 1ps/1ps -`include "header.sv" +`include "header_fir_vector_global_reduce.sv" // vcs -sverilog -full64 -timescale=1ns/1ps ../MeshMultiCgraRTL__explicit__pickled.v MeshMultiCgraRTL_2x2_fir_scalar_tb.v -debug_access+all @@ -11,15 +11,15 @@ module cgra_test logic [0:0] clk; logic [0:0] reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__432fde8bfb7da0ed recv_from_cpu_pkt__msg; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg; logic [0:0] recv_from_cpu_pkt__rdy; logic [0:0] recv_from_cpu_pkt__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__432fde8bfb7da0ed send_to_cpu_pkt__msg; + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg; logic [0:0] send_to_cpu_pkt__rdy; logic [0:0] send_to_cpu_pkt__val; - MeshMultiCgraRTL__explicit MultiCGRA (.*); + MeshMultiCgraRTL__975ce70dc1a0740a MultiCGRA (.*); int PASS = 'd0; time pass_time_of = 'd0; @@ -85,1107 +85,264 @@ typedef struct packed { } CGRAConfig_7_4_2_4_4_3__49d22cda396bec88; */ - // Preload data. - #10 // CMD_STORE_REQUEST/ - recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h0001000100010001, 1, 0, 0); + #10 recv_from_cpu_pkt__val = 1'b1; + recv_from_cpu_pkt__msg = unpack_pkt('h0000000180002000200020003000000000000000000000000000000); #10 - recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h0001000100010001, 1, 1, 0); + recv_from_cpu_pkt__msg = unpack_pkt('h0000000180002000200020003008000000000000000000000000000); #10 - recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h000f000e000d000c, 1, 2, 0); + recv_from_cpu_pkt__msg = unpack_pkt('h000000018001e001c001a0019010000000000000000000000000000); #10 - recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h0013001200110010, 1, 3, 0); + recv_from_cpu_pkt__msg = unpack_pkt('h0000000180026002400220021018000000000000000000000000000); #10 - recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h00110010000f000e, 1, 4, 0); + recv_from_cpu_pkt__msg = unpack_pkt('h00000001800220020001e001d020000000000000000000000000000); #10 - recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h0015001400130012, 1, 5, 0); + recv_from_cpu_pkt__msg = unpack_pkt('h000000018002a002800260025028000000000000000000000000000); #10 - recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 12, 'h0001000100010001, 1, 6, 0); - - // Tile 0. - #10 // CMD_CONST. - recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 13, 3, 1, 0, 0); - #10 // CMD_CONFIG_COUNT_PER_ITER. - recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 8, 4, 1, 0, 0); - #10 // CMD_CONFIG_TOTAL_CTRL_COUNT - recv_from_cpu_pkt__msg = make_intra_cgra_pkt(0, 0, 7, 'd42, 1, 0, 0); - #10 // CMD_CONFIG - OPT_ADD. - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt(0, 0, 3, 2, - '{3'd4, 3'd3, 3'd2, 3'd1}, - '{3'd0, 3'd0, 3'd0, 3'd1, 3'd0, 3'd0, 3'd0, 3'd0}, - '{2'd0, 2'd0, 2'd0, 2'd1, 2'd1, 2'd0, 2'd0, 2'd0}, - '{2'd0, 2'd0, 2'd0, 2'd2}, - '{1'd0, 1'd0, 1'd1, 1'd0}, - '{4'd0, 4'd0, 4'd0, 4'd0}, - '{4'd0, 4'd0, 4'd0, 4'd0}, - 0); - #10 // CMD_CONFIG - OPT_PHI_CONST. - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt(0, 0, 3, 32, - '{3'd4, 3'd3, 3'd2, 3'd1}, - '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, // routing_xbar_outport (TileInType list) - '{2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, // fu_xbar_outport (FuOutType list) - '{2'd0, 2'd0, 2'd2, 2'd0}, // write_reg_from (b2(0), b2(2), ...) - '{1'd0, 1'd0, 1'd0, 1'd1}, // read_reg_from - '{ default: 4'd0 }, // write_reg_idx (not specified, zeroed) - '{ default: 4'd0 }, // read_reg_idx (not specified, zeroed) - 1); // ctrl_addr = 1 - #10 // CMD_CONFIG - OPT_NAH. - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt(0, 0, 3, 1, - '{3'd4, 3'd3, 3'd2, 3'd1}, - '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0}, - '{1'd0, 1'd0, 1'd0, 1'd0}, - '{ default: 4'd0 }, - '{ default: 4'd0 }, - 2); - #10 // CMD_CONFIG - OPT_NAH. - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt(0, 0, 3, 1, - '{3'd4, 3'd3, 3'd2, 3'd1}, - '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0}, - '{1'd0, 1'd0, 1'd0, 1'd0}, - '{ default: 4'd0 }, - '{ default: 4'd0 }, - 3); - #10 // CMD_CONFIG_PROLOGUE_FU. - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 4, 0, - '{3'd0, 3'd0, 3'd0, 3'd0}, - '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0}, - '{1'd0, 1'd0, 1'd0, 1'd0}, - '{ default: 4'd0 }, - '{ default: 4'd0 }, - 0, - 1, - 1, - 0); - //#10 // CMD_CONFIG_PROLOGUE_FU. - //recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 4, 0, - // '{3'd0, 3'd0, 3'd0, 3'd0}, - // '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, - // '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, - // '{2'd0, 2'd0, 2'd0, 2'd0}, - // '{1'd0, 1'd0, 1'd0, 1'd0}, - // '{ default: 4'd0 }, - // '{ default: 4'd0 }, - // 1, - // 1, - // 1, - // 0); - #10 // CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR. - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 6, 0, - '{3'd0, 3'd0, 3'd0, 3'd0}, - '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0}, - '{1'd0, 1'd0, 1'd0, 1'd0}, - '{ default: 4'd0 }, - '{ default: 4'd0 }, - 0, - 1, - 1, - 0); - #10 // CMD_CONFIG_PROLOGUE_FU_CROSSBAR. - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 5, 0, - '{3'd0, 3'd0, 3'd0, 3'd0}, - '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0}, - '{1'd0, 1'd0, 1'd0, 1'd0}, - '{ default: 4'd0 }, - '{ default: 4'd0 }, - 0, - 1, - 1, - 0); - //#10 // CMD_CONFIG_PROLOGUE_FU_CROSSBAR. - //recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 5, 0, - // '{3'd0, 3'd0, 3'd0, 3'd0}, - // '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, - // '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, - // '{2'd0, 2'd0, 2'd0, 2'd0}, - // '{1'd0, 1'd0, 1'd0, 1'd0}, - // '{ default: 4'd0 }, - // '{ default: 4'd0 }, - // 1, - // 1, - // 1, - // 0); - #10 // CMD_LAUNCH. - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data(0, 0, 0, 0, - '{3'd0, 3'd0, 3'd0, 3'd0}, - '{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}, - '{2'd0, 2'd0, 2'd0, 2'd0}, - '{1'd0, 1'd0, 1'd0, 1'd0}, - '{ default: 4'd0 }, - '{ default: 4'd0 }, - 0, - 0, - 0, - 0); - - // Tile 1. - #10 //CMD_CONFIG_COUNT_PER_ITER - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd8), // CMD_CONFIG_COUNT_PER_ITER = 8 - .operation(7'd0), - .fu_in_code('{default:3'd0}), - .routing_xbar_outport('{default:3'd0}), - .fu_xbar_outport('{default:2'd0}), - .write_reg_from('{default:2'd0}), - .read_reg_from('{default:1'd0}), - .write_reg_idx('{default:4'd0}), - .read_reg_idx('{default:4'd0}), - .ctrl_addr(4'd0), - .data(32'd4), // kCtrlCountPerIter = 4 - .pred(1'd1), // predicate = 1 - .data_addr(7'd0) - ); - #10 - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd7), // CMD_CONFIG_TOTAL_CTRL_COUNT = 7 - .operation(7'd0), - .fu_in_code('{default:3'd0}), - .routing_xbar_outport('{default:3'd0}), - .fu_xbar_outport('{default:2'd0}), - .write_reg_from('{default:2'd0}), - .read_reg_from('{default:1'd0}), - .write_reg_idx('{default:4'd0}), - .read_reg_idx('{default:4'd0}), - .ctrl_addr(4'd0), - .data(32'd42), // kTotalCtrlSteps = 42 - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd3), // CMD_CONFIG = 3 - .operation(7'd1), // OPT_NAH 1 - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{default:3'd0}), - .fu_xbar_outport('{default:2'd0}), - .write_reg_from('{default:2'd0}), - .read_reg_from('{default:1'd0}), - .write_reg_idx('{default:4'd0}), - .read_reg_idx('{default:4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd3), - .operation(7'd16), // OPT_GRT_PRED = 16 - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd1, 3'd3, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd2}), - .read_reg_from('{default:1'd0}), - .write_reg_idx('{default:4'd0}), - .read_reg_idx('{default:4'd0}), - .ctrl_addr(4'd1), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // OPT_RET (OPT_RET = 35) - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd3), - .operation(7'd35), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}), - .fu_xbar_outport('{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}), - .write_reg_from('{2'd0,2'd0,2'd0,2'd0}), - .read_reg_from('{1'b0, 1'b0, 1'b0, 1'b1}), - .write_reg_idx('{4'd0,4'd0,4'd0,4'd0}), - .read_reg_idx('{4'd0,4'd0,4'd0,4'd0}), - .ctrl_addr(4'd2), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // NAH again (OPT_NAH = 1) - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd3), - .operation(7'd1), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}), - .fu_xbar_outport('{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}), - .write_reg_from('{2'd0,2'd0,2'd0,2'd0}), - .read_reg_from('{1'd0,1'd0,1'd0,1'd0}), - .write_reg_idx('{4'd0,4'd0,4'd0,4'd0}), - .read_reg_idx('{4'd0,4'd0,4'd0,4'd0}), - .ctrl_addr(4'd3), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CONFIG_PROLOGUE_FU (ctrl_addr = 1) - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd4), - .operation(7'd0), - .fu_in_code('{default:3'd0}), - .routing_xbar_outport('{default:3'd0}), - .fu_xbar_outport('{default:2'd0}), - .write_reg_from('{default:2'd0}), - .read_reg_from('{default:1'd0}), - .write_reg_idx('{default:4'd0}), - .read_reg_idx('{default:4'd0}), - .ctrl_addr(4'd1), - .data(32'd1), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CONFIG_PROLOGUE_FU (ctrl_addr = 2) - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd4), - .operation(7'd0), - .fu_in_code('{default:3'd0}), - .routing_xbar_outport('{default:3'd0}), - .fu_xbar_outport('{default:2'd0}), - .write_reg_from('{default:2'd0}), - .read_reg_from('{default:1'd0}), - .write_reg_idx('{default:4'd0}), - .read_reg_idx('{default:4'd0}), - .ctrl_addr(4'd2), - .data(32'd1), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CONFIG_PROLOGUE_ROUTING_CROSSBAR (all 0) - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd6), - .operation(7'd0), - .fu_in_code('{default:3'd0}), - .routing_xbar_outport('{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0}), - .fu_xbar_outport('{default:2'd0}), - .write_reg_from('{default:2'd0}), - .read_reg_from('{default:1'd0}), - .write_reg_idx('{default:4'd0}), - .read_reg_idx('{default:4'd0}), - .ctrl_addr(4'd1), - .data(32'd1), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CONFIG_PROLOGUE_ROUTING_CROSSBAR (first routing = 2) - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd6), - .operation(7'd0), - .fu_in_code('{default:3'd0}), - .routing_xbar_outport('{3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd0,3'd2}), - .fu_xbar_outport('{default:2'd0}), - .write_reg_from('{default:2'd0}), - .read_reg_from('{default:1'd0}), - .write_reg_idx('{default:4'd0}), - .read_reg_idx('{default:4'd0}), - .ctrl_addr(4'd1), - .data(32'd1), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CONFIG_PROLOGUE_FU_CROSSBAR (ctrl_addr = 1) - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd5), - .operation(7'd0), - .fu_in_code('{default:3'd0}), - .routing_xbar_outport('{default:3'd0}), - .fu_xbar_outport('{2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0,2'd0}), - .write_reg_from('{default:2'd0}), - .read_reg_from('{default:1'd0}), - .write_reg_idx('{default:4'd0}), - .read_reg_idx('{default:4'd0}), - .ctrl_addr(4'd1), - .data(32'd1), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_LAUNCH - recv_from_cpu_pkt__msg = make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd1), - .cmd(5'd0), - .operation(7'd0), - .fu_in_code('{default:3'd0}), - .routing_xbar_outport('{default:3'd0}), - .fu_xbar_outport('{default:2'd0}), - .write_reg_from('{default:2'd0}), - .read_reg_from('{default:1'd0}), - .write_reg_idx('{default:4'd0}), - .read_reg_idx('{default:4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - //////////// - // Tile 4 // - //////////// - #10 - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd4), - .cmd(5'd13), // CMD_CONST - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), // write_reg_from_code (do not reverse) - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), // read_reg_from_code (do not reverse) - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd2), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG_COUNT_PER_ITER - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd4), - .cmd(5'd8), // CMD_CONFIG_COUNT_PER_ITER - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd4), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG_TOTAL_CTRL_COUNT - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd4), - .cmd(5'd7), // CMD_CONFIG_TOTAL_CTRL_COUNT - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd42), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=0, OPT_NAH - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd4), - .cmd(5'd3), // CMD_CONFIG - .operation(7'd1), // OPT_NAH - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - // reverse of [0,0,0,0,0,0,0,0] is itself - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - // reverse of [0,0,0,0,0,0,0,0] is itself - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), // keep provided code - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), // keep provided code - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=1, OPT_ADD_CONST - // routing: reverse of [0,0,0,0,1,0,0,0] -> [0,0,0,1,0,0,0,0] - // fu_xbar : reverse of [0,0,0,0,1,0,0,0] -> [0,0,0,1,0,0,0,0] - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd4), - .cmd(5'd3), // CMD_CONFIG - .operation(7'd25), // OPT_ADD_CONST - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd1, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd2}), // write_reg_from_code (keep order) - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), // read_reg_from_code - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd1), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=2, OPT_LD - // fu_xbar : reverse of [0,0,0,0,0,1,0,0] -> [0,0,1,0,0,0,0,0] - // write_reg_from inline [0,2,0,0] -> reverse -> [0,0,2,0] - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd4), - .cmd(5'd3), // CMD_CONFIG - .operation(7'd12), // OPT_LD - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd2, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd1}), // read_reg_from_code - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd2), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=3, OPT_MUL - // routing: reverse of [0,0,0,0,1,0,0,0] -> [0,0,0,1,0,0,0,0] - // fu_xbar : reverse of [0,1,0,0,0,0,0,0] -> [0,0,0,0,0,0,1,0] - // read_reg_from inline [0,1,0,0] -> reverse -> [0,0,1,0] - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd4), - .cmd(5'd3), // CMD_CONFIG - .operation(7'd7), // OPT_MUL - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd1, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd1, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd1, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd3), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_LAUNCH - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd4), - .cmd(5'd0), // CMD_LAUNCH - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - //////////// - // Tile 5 // - //////////// - #10 - // CMD_CONST (kLoopUpperBound, pred=1) - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd5), - .cmd(5'd13), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd10), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG_COUNT_PER_ITER (kCtrlCountPerIter, pred=1) - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd5), - .cmd(5'd8), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd4), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG_TOTAL_CTRL_COUNT (kTotalCtrlSteps, pred=1) - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd5), - .cmd(5'd7), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd42), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=0, OPT_NAH - // (explicit arrays reversed; provided *_code arrays kept as-is) - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd5), - .cmd(5'd3), - .operation(7'd1), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=1, OPT_NAH - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd5), - .cmd(5'd3), - .operation(7'd1), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd1), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=2, OPT_NE_CONST (CMP) - // routing [0,0,0,0,1,0,0,0] -> reversed -> [0,0,0,1,0,0,0,0] - // fu_xbar [1,0,0,0,1,0,0,0] -> reversed -> [0,0,0,0,1,0,0,1] - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd5), - .cmd(5'd3), - .operation(7'd46), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd1, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd1}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd2}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd2), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=3, OPT_NOT - // routing [0,1,0,0,0,0,0,0] -> reversed -> [0,0,0,0,0,0,1,0] - // fu_xbar [0,1,0,0,0,0,0,0] -> reversed -> [0,0,0,0,0,0,1,0] - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd5), - .cmd(5'd3), - .operation(7'd11), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd1, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd1}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd3), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_LAUNCH - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd5), - .cmd(5'd0), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - //////////// - // Tile 8 // - //////////// - #10 - // CMD_CONST (kLoopLowerBound, pred=1) — for PHI_CONST - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd8), - .cmd(5'd13), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd2), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONST (kInputBaseAddress, pred=1) — for ADD_CONST - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd8), - .cmd(5'd13), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG_COUNT_PER_ITER (kCtrlCountPerIter, pred=1) - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd8), - .cmd(5'd8), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd4), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG_TOTAL_CTRL_COUNT (kTotalCtrlSteps, pred=1) - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd8), - .cmd(5'd7), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd42), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=0, OPT_PHI_CONST - // routing [0,0,0,0,4,0,0,0] -> reversed -> [0,0,0,4,0,0,0,0] - // fu_xbar [0,1,0,1,1,0,0,0] -> reversed -> [0,0,0,1,1,0,1,0] - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd8), - .cmd(5'd3), - .operation(7'd32), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd4, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd1, 2'd1, 2'd0, 2'd1, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd2}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=1, OPT_ADD_CONST - // fu_xbar [0,0,0,0,0,1,0,0] -> reversed -> [0,0,1,0,0,0,0,0] - // write_reg_from inline [0,2,0,0] -> reversed -> [0,0,2,0] - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd8), - .cmd(5'd3), - .operation(7'd25), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd2, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd1}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd1), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=2, OPT_LD - // fu_in_code inline [2,0,0,0] -> reversed -> [0,0,0,2] - // fu_xbar [0,1,0,0,0,0,0,0] -> reversed -> [0,0,0,0,0,0,1,0] - // read_reg_from inline [0,1,0,0] -> reversed -> [0,0,1,0] - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd8), - .cmd(5'd3), - .operation(7'd12), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd2}), // Hand-coded. - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd1, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd1, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd2), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=3, OPT_NAH - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd8), - .cmd(5'd3), - .operation(7'd1), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd3), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR @ ctrl_addr=0, data=1 (pred=1) - // routing [3,0,0,0,0,0,0,0] -> reversed -> [0,0,0,0,0,0,0,3] - // (unspecified args default to zeros) - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd8), - .cmd(5'd6), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd3}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd1), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_LAUNCH - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd8), - .cmd(5'd0), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - //////////// - // Tile 9 // - //////////// - #10 - // CMD_CONST (kLoopIncrement, pred=1) — for ADD_CONST - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd9), - .cmd(5'd13), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd1), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG_COUNT_PER_ITER (kCtrlCountPerIter, pred=1) - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd9), - .cmd(5'd8), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd4), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG_TOTAL_CTRL_COUNT (kTotalCtrlSteps, pred=1) - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd9), - .cmd(5'd7), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd42), - .pred(1'd1), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=0, OPT_NAH - // routing [0,0,0,0,0,0,0,0] -> reversed -> same - // fu_xbar [0,0,0,0,0,0,0,0] -> reversed -> same - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd9), - .cmd(5'd3), - .operation(7'd1), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=1, OPT_ADD_CONST - // routing [0,0,0,0,3,0,0,0] -> reversed -> [0,0,0,3,0,0,0,0] - // fu_xbar [0,1,0,0,0,1,0,0] -> reversed -> [0,0,1,0,0,0,1,0] - // write_reg_from inline [0,2,0,0] -> reversed -> [0,0,2,0] - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd9), - .cmd(5'd3), - .operation(7'd25), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd3, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd1, 2'd0, 2'd0, 2'd0, 2'd1, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd2, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd1), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=2, OPT_NAH - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd9), - .cmd(5'd3), - .operation(7'd1), - .fu_in_code('{3'd4, 3'd3, 3'd2, 3'd1}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd2), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_CONFIG @ ctrl_addr=3, OPT_GRT_PRED - // fu_in [2,1,0,0] . -> reversed -> [0,0,1,2] - // routing [0,0,0,0,2,0,0,0] -> reversed -> [0,0,0,2,0,0,0,0] - // fu_xbar [0,0,1,0,0,0,0,0] -> reversed -> [0,0,0,0,0,1,0,0] - // read_reg_from [0,1,0,0] -> reversed -> [0,0,1,0] - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd9), - .cmd(5'd3), - .operation(7'd16), - .fu_in_code('{3'd0, 3'd0, 3'd1, 3'd2}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd2, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd1, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd1, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd3), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - #10 - // CMD_LAUNCH - recv_from_cpu_pkt__msg = - make_intra_cgra_config_pkt_w_data( - .src(5'd0), - .dst(5'd9), - .cmd(5'd0), - .operation(7'd0), - .fu_in_code('{3'd0, 3'd0, 3'd0, 3'd0}), - .routing_xbar_outport('{3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0}), - .fu_xbar_outport('{2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0}), - .write_reg_from('{2'd0, 2'd0, 2'd0, 2'd0}), - .read_reg_from('{1'd0, 1'd0, 1'd0, 1'd0}), - .write_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .read_reg_idx('{4'd0, 4'd0, 4'd0, 4'd0}), - .ctrl_addr(4'd0), - .data(32'd0), - .pred(1'd0), - .data_addr(7'd0) - ); - + recv_from_cpu_pkt__msg = unpack_pkt('h0000000180002000200020003030000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00000001a0000000000000007000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0000000100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00000000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0000000060000000000000000004e8d100100001400020000200000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000000006000000000000000000208d100000004000080000100001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000000006000000000000000000018d100000000000000000000002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000000006000000000000000000018d100000000000000000000003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0000000220000000000000005000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0000000080000000000000003000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00000000c0000000000000003000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00000000a0000000000000003000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0000000000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0008000100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00080000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000800006000000000000000000018d100000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000800006000000000000000000108d100b00001000020000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000800006000000000000000000238d100000000000000000100002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000800006000000000000000000018d100000000000000000000003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0008000080000000000000003000000000000000000000000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0008000080000000000000003000000000000000000000000000002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00080000c0000000000000003000000000000000000000000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00080000c0000000000000003000000000000200000000000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00080000a0000000000000003000000000000000000000000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0008000000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00200001a0000000000000005000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0020000100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00200000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h002000006000000000000000000018d100000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h002000006000000000000000000198d100100001000020000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0020000060000000000000000000c8d100000004000080000100002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h002000006000000000000000000378d100100000040000000200003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0020000000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00280001a0000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0028000100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00280000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h002800006000000000000000000018d100000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h002800006000000000000000000018d100000000000000000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0028000060000000000000000002e8d100100001010020000000002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0028000060000000000000000000b8d100000000040000000100003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0028000000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00400001a0000000000000005000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00400001a0000000000000001000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0040000100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00400000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004000006000000000000000000208d100400001440020000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004000006000000000000000000198d100000004000080000100001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0040000060000000000000000000c00200000000040000000200002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004000006000000000000000000018d100000000000000000000003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00400000c0000000000000003000000000000300000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0040000000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00480001a0000000000000003000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0048000100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00480000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004800006000000000000000000018d100000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004800006000000000000000000198d100300004040080000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004800006000000000000000000018d100000000000000000000002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0048000060000000000000000001000a00200000100000000200003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0048000000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00009001a0000000000000007000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0000900100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00009000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0000900060000000000000000004e8d100100001400020000200000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000090006000000000000000000208d100000004000080000100001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000090006000000000000000000018d100000000000000000000002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000090006000000000000000000018d100000000000000000000003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0000900080000000000000003000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00009000c0000000000000003000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00009000a0000000000000003000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0000900000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0008900100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00089000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000890006000000000000000000018d100000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000890006000000000000000000108d100b00001000020000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h000890006000000000000000000238d100000000000000000100002); + #10 // Might need to send this twice if CGRA is really not rdy. + recv_from_cpu_pkt__msg = unpack_pkt('h000890006000000000000000000018d100000000000000000000003); + #10 // Second send. + recv_from_cpu_pkt__msg = unpack_pkt('h000890006000000000000000000018d100000000000000000000003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0008900080000000000000003000000000000000000000000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0008900080000000000000003000000000000000000000000000002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00089000c0000000000000003000000000000000000000000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00089000c0000000000000003000000000000200000000000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00089000a0000000000000003000000000000000000000000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0008900000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00209001a0000000000000005000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0020900100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00209000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h002090006000000000000000000018d100000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h002090006000000000000000000198d100100001000020000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0020900060000000000000000000c8d100000004000080000100002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h002090006000000000000000000378d100100000040000000200003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0020900000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00289001a0000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0028900100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00289000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h002890006000000000000000000018d100000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h002890006000000000000000000018d100000000000000000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0028900060000000000000000002e8d100100001010020000000002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0028900060000000000000000000b8d100000000040000000100003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0028900000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00409001a0000000000000005000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00409001a0000000000000001000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0040900100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00409000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004090006000000000000000000208d100400001440020000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004090006000000000000000000198d100000004000080000100001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0040900060000000000000000000c00200000000040000000200002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004090006000000000000000000018d100000000000000000000003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00409000c0000000000000003000000000000300000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0040900000000000000000000000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00489001a0000000000000003000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0048900100000000000000009000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h00489000e000000000000004d000000000000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004890006000000000000000000018d100000000000000000000000); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004890006000000000000000000198d100300004040080000000001); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h004890006000000000000000000018d100000000000000000000002); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0048900060000000000000000001000a00200000100000000200003); + #10 + recv_from_cpu_pkt__msg = unpack_pkt('h0048900000000000000000000000000000000000000000000000000); #10 recv_from_cpu_pkt__val = 0; - #3000 + #10000 if ('d1 == PASS) $display("TEST PASSED at %0t.", pass_time_of); else $display("TEST FAILED at %0t.", $time); + $display("%d", unpack_pkt('h01800001c000000000000229700238d100000000000000000100000).payload.data.payload); + $display("#########cgra 0 tile 0 cnst mem#################"); for (int i = 0; i < 512; i++) begin @@ -1295,7 +452,7 @@ typedef struct packed { end /*initial - begin + begin $dumpfile("./output.vcd"); $dumpvars (0, cgra_test); end*/ From 8be2120b234c02ab7bbbe787b280a17b11cf0a42 Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Tue, 6 Jan 2026 15:54:03 -0600 Subject: [PATCH 07/12] [SV tb] Packing-function header for the new CGRA RTL. --- .../header_fir_vector_global_reduce.sv | 358 ++++++++++++++++++ 1 file changed, 358 insertions(+) create mode 100644 multi_cgra/test/sv_test/header_fir_vector_global_reduce.sv diff --git a/multi_cgra/test/sv_test/header_fir_vector_global_reduce.sv b/multi_cgra/test/sv_test/header_fir_vector_global_reduce.sv new file mode 100644 index 00000000..6a0e3247 --- /dev/null +++ b/multi_cgra/test/sv_test/header_fir_vector_global_reduce.sv @@ -0,0 +1,358 @@ +function automatic IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 make_intra_cgra_pkt +( + input logic [4:0] src, + input logic [4:0] dst, + input logic [4:0] cmd, + input logic [31:0] data_payload, + input logic data_predicate, + input logic [6:0] data_addr, + input logic [6:0] ctrl_operation +); + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 pkt; + integer file_handle; + + pkt.src = src; + pkt.dst = dst; + pkt.src_cgra_id = 2'd0; + pkt.dst_cgra_id = 2'd0; + pkt.src_cgra_x = 1'b0; + pkt.src_cgra_y = 1'b0; + pkt.dst_cgra_x = 1'b0; + pkt.dst_cgra_y = 1'b0; + pkt.opaque = 8'd0; + pkt.vc_id = 1'b0; + + + pkt.payload.cmd = cmd; + pkt.payload.data_addr = data_addr; + pkt.payload.ctrl_addr = 4'd0; + + pkt.payload.data.payload = data_payload; + pkt.payload.data.predicate = data_predicate; + pkt.payload.data.bypass = 1'b0; + pkt.payload.data.delay = 1'b0; + + + pkt.payload.ctrl.operation = ctrl_operation; + pkt.payload.ctrl.fu_in = '{default: 3'd0}; + pkt.payload.ctrl.routing_xbar_outport = '{default: 3'd0}; + pkt.payload.ctrl.fu_xbar_outport = '{default: 2'd0}; + pkt.payload.ctrl.vector_factor_power = 3'd0; + pkt.payload.ctrl.is_last_ctrl = 1'b0; + pkt.payload.ctrl.write_reg_from = '{default: 2'd0}; + pkt.payload.ctrl.write_reg_idx = '{default: 4'd0}; + pkt.payload.ctrl.read_reg_from = '{default: 1'd0}; + pkt.payload.ctrl.read_reg_idx = '{default: 4'd0}; + +/* +111103b7 lui x7 +00138393 ADDI x7 +01039393 slli x7, x7, 16 +01039393 slli x7, x7, 16 +lui 31 +addi 31 +ADD 7 7 31 +0070b023 sd x7, 0(x1) + +22220437 lui x8 +addi x8 +01041413 slli x8, x8, 16 +01041413 slli x8, x8, 16 +lui 31 +addi 31 +ADD 8 8 31 +0080b423 sd x8, 8(x1) + +33330537 lui x10 +ADDI x10 +01051513 slli x10, x10, 16 +01051513 slli x10, x10, 16 +lui 31 +addi 31 +ADD 10 10 31 +00a0b823 sd x10, 16(x1) + +01808093 Advance x1 += 24 (h1018) +*/ + + file_handle = $fopen("hexcode.txt", "a"); + //$fdisplay( file_handle, "%h", logic_pkt(pkt)[63:0] ); + $fdisplay( file_handle, "%h3b7", (logic_pkt(pkt)[63:44] + logic_pkt(pkt)[43]) ); + $fdisplay( file_handle, "%h38393", (logic_pkt(pkt)[43:32] + logic_pkt(pkt)[31]) ); + $fdisplay( file_handle, "01039393" ); + $fdisplay( file_handle, "01039393" ); + $fdisplay( file_handle, "%hfb7", (logic_pkt(pkt)[31:12] + logic_pkt(pkt)[11]) ); + $fdisplay( file_handle, "%hf8f93", logic_pkt(pkt)[11:0] ); + $fdisplay( file_handle, "01f383b3" ); + $fdisplay( file_handle, "0070b023" ); + //$fdisplay( file_handle, "%h", logic_pkt(pkt)[127:64] ); + $fdisplay( file_handle, "%h437", (logic_pkt(pkt)[127:108] + logic_pkt(pkt)[107]) ); + $fdisplay( file_handle, "%h40413", (logic_pkt(pkt)[107:96] + logic_pkt(pkt)[95]) ); + $fdisplay( file_handle, "01041413" ); + $fdisplay( file_handle, "01041413" ); + $fdisplay( file_handle, "%hfb7", (logic_pkt(pkt)[95:76] + logic_pkt(pkt)[75]) ); + $fdisplay( file_handle, "%hf8f93", logic_pkt(pkt)[75:64] ); + $fdisplay( file_handle, "01f40433" ); + $fdisplay( file_handle, "0080b423" ); + //$fdisplay( file_handle, "%h", logic_pkt(pkt)[184:128] ); + $fdisplay( file_handle, "%h537", ({ {7{1'b0}}, logic_pkt(pkt)[184:172] } + logic_pkt(pkt)[171]) ); + $fdisplay( file_handle, "%h50513", ( logic_pkt(pkt)[171:160] + logic_pkt(pkt)[159]) ); + $fdisplay( file_handle, "01051513" ); + $fdisplay( file_handle, "01051513" ); + $fdisplay( file_handle, "%hfb7", (logic_pkt(pkt)[159:140] + logic_pkt(pkt)[139]) ); + $fdisplay( file_handle, "%hf8f93", logic_pkt(pkt)[139:128] ); + $fdisplay( file_handle, "01f50533" ); + $fdisplay( file_handle, "00a0b823" ); + // Advance x1 += 24 (h1018) + $fdisplay( file_handle, "01808093" ); + $fclose(file_handle); + + return pkt; +endfunction + +function automatic IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 make_intra_cgra_config_pkt +( + input logic [4:0] src, + input logic [4:0] dst, + input logic [4:0] cmd, + input logic [6:0] operation, + input logic [3:0][2:0] fu_in_code, + input logic [7:0][2:0] routing_xbar_outport, + input logic [7:0][1:0] fu_xbar_outport, + input logic [3:0][1:0] write_reg_from, + input logic [3:0][0:0] read_reg_from, + input logic [3:0][3:0] write_reg_idx, + input logic [3:0][3:0] read_reg_idx, + input logic [3:0] ctrl_addr +); + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 pkt; + integer file_handle; + + pkt.src = src; + pkt.dst = dst; + pkt.src_cgra_id = 2'd0; + pkt.dst_cgra_id = 2'd0; + pkt.src_cgra_x = 1'b0; + pkt.src_cgra_y = 1'b0; + pkt.dst_cgra_x = 1'b0; + pkt.dst_cgra_y = 1'b0; + pkt.opaque = 8'd0; + pkt.vc_id = 1'b0; + + pkt.payload.cmd = cmd; // CMD_CONFIG + pkt.payload.data = '0; // Not used for config packets + pkt.payload.data_addr = 7'd0; + pkt.payload.ctrl_addr = ctrl_addr; + + pkt.payload.ctrl.operation = operation; + pkt.payload.ctrl.fu_in = fu_in_code; + pkt.payload.ctrl.routing_xbar_outport = routing_xbar_outport; + pkt.payload.ctrl.fu_xbar_outport = fu_xbar_outport; + pkt.payload.ctrl.vector_factor_power = 3'd0; + pkt.payload.ctrl.is_last_ctrl = 1'b0; + pkt.payload.ctrl.write_reg_from = write_reg_from; + pkt.payload.ctrl.write_reg_idx = write_reg_idx; + pkt.payload.ctrl.read_reg_from = read_reg_from; + pkt.payload.ctrl.read_reg_idx = read_reg_idx; + + file_handle = $fopen("hexcode.txt", "a"); + //$fdisplay( file_handle, "%h", logic_pkt(pkt)[63:0] ); + $fdisplay( file_handle, "%h3b7", (logic_pkt(pkt)[63:44] + logic_pkt(pkt)[43]) ); + $fdisplay( file_handle, "%h38393", (logic_pkt(pkt)[43:32] + logic_pkt(pkt)[31]) ); + $fdisplay( file_handle, "01039393" ); + $fdisplay( file_handle, "01039393" ); + $fdisplay( file_handle, "%hfb7", (logic_pkt(pkt)[31:12] + logic_pkt(pkt)[11]) ); + $fdisplay( file_handle, "%hf8f93", logic_pkt(pkt)[11:0] ); + $fdisplay( file_handle, "01f383b3" ); + $fdisplay( file_handle, "0070b023" ); + //$fdisplay( file_handle, "%h", logic_pkt(pkt)[127:64] ); + $fdisplay( file_handle, "%h437", (logic_pkt(pkt)[127:108] + logic_pkt(pkt)[107]) ); + $fdisplay( file_handle, "%h40413", (logic_pkt(pkt)[107:96] + logic_pkt(pkt)[95]) ); + $fdisplay( file_handle, "01041413" ); + $fdisplay( file_handle, "01041413" ); + $fdisplay( file_handle, "%hfb7", (logic_pkt(pkt)[95:76] + logic_pkt(pkt)[75]) ); + $fdisplay( file_handle, "%hf8f93", logic_pkt(pkt)[75:64] ); + $fdisplay( file_handle, "01f40433" ); + $fdisplay( file_handle, "0080b423" ); + //$fdisplay( file_handle, "%h", logic_pkt(pkt)[184:128] ); + $fdisplay( file_handle, "%h537", ({ {7{1'b0}}, logic_pkt(pkt)[184:172] } + logic_pkt(pkt)[171]) ); + $fdisplay( file_handle, "%h50513", ( logic_pkt(pkt)[171:160] + logic_pkt(pkt)[159]) ); + $fdisplay( file_handle, "01051513" ); + $fdisplay( file_handle, "01051513" ); + $fdisplay( file_handle, "%hfb7", (logic_pkt(pkt)[159:140] + logic_pkt(pkt)[139]) ); + $fdisplay( file_handle, "%hf8f93", logic_pkt(pkt)[139:128] ); + $fdisplay( file_handle, "01f50533" ); + $fdisplay( file_handle, "00a0b823" ); + // Advance x1 += 24 (h1018) + $fdisplay( file_handle, "01808093" ); + $fclose(file_handle); + + return pkt; +endfunction + +function automatic IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 make_intra_cgra_config_pkt_w_data +( + input logic [4:0] src, + input logic [4:0] dst, + input logic [4:0] cmd, + input logic [6:0] operation, + input logic [3:0][2:0] fu_in_code, + input logic [7:0][2:0] routing_xbar_outport, + input logic [7:0][1:0] fu_xbar_outport, + input logic [3:0][1:0] write_reg_from, + input logic [3:0][0:0] read_reg_from, + input logic [3:0][3:0] write_reg_idx, + input logic [3:0][3:0] read_reg_idx, + input logic [3:0] ctrl_addr, + input logic [31:0] data, + input logic [0:0] pred, + input logic [6:0] data_addr +); + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 pkt; + integer file_handle; + + pkt.src = src; + pkt.dst = dst; + pkt.src_cgra_id = 2'd0; + pkt.dst_cgra_id = 2'd0; + pkt.src_cgra_x = 1'b0; + pkt.src_cgra_y = 1'b0; + pkt.dst_cgra_x = 1'b0; + pkt.dst_cgra_y = 1'b0; + pkt.opaque = 8'd0; + pkt.vc_id = 1'b0; + + pkt.payload.cmd = cmd; + pkt.payload.data_addr = data_addr; + pkt.payload.ctrl_addr = ctrl_addr; + + pkt.payload.ctrl.operation = operation; + pkt.payload.ctrl.fu_in = fu_in_code; + pkt.payload.ctrl.routing_xbar_outport = routing_xbar_outport; + pkt.payload.ctrl.fu_xbar_outport = fu_xbar_outport; + pkt.payload.ctrl.vector_factor_power = 3'd0; + pkt.payload.ctrl.is_last_ctrl = 1'b0; + pkt.payload.ctrl.write_reg_from = write_reg_from; + pkt.payload.ctrl.write_reg_idx = write_reg_idx; + pkt.payload.ctrl.read_reg_from = read_reg_from; + pkt.payload.ctrl.read_reg_idx = read_reg_idx; + + pkt.payload.data.payload = data; + pkt.payload.data.predicate = pred; + pkt.payload.data.bypass = 1'b0; + pkt.payload.data.delay = 1'b0; + + file_handle = $fopen("hexcode.txt", "a"); + //$fdisplay( file_handle, "%h", logic_pkt(pkt)[63:0] ); + $fdisplay( file_handle, "%h3b7", (logic_pkt(pkt)[63:44] + logic_pkt(pkt)[43]) ); + $fdisplay( file_handle, "%h38393", (logic_pkt(pkt)[43:32] + logic_pkt(pkt)[31]) ); + $fdisplay( file_handle, "01039393" ); + $fdisplay( file_handle, "01039393" ); + $fdisplay( file_handle, "%hfb7", (logic_pkt(pkt)[31:12] + logic_pkt(pkt)[11]) ); + $fdisplay( file_handle, "%hf8f93", logic_pkt(pkt)[11:0] ); + $fdisplay( file_handle, "01f383b3" ); + $fdisplay( file_handle, "0070b023" ); + //$fdisplay( file_handle, "%h", logic_pkt(pkt)[127:64] ); + $fdisplay( file_handle, "%h437", (logic_pkt(pkt)[127:108] + logic_pkt(pkt)[107]) ); + $fdisplay( file_handle, "%h40413", (logic_pkt(pkt)[107:96] + logic_pkt(pkt)[95]) ); + $fdisplay( file_handle, "01041413" ); + $fdisplay( file_handle, "01041413" ); + $fdisplay( file_handle, "%hfb7", (logic_pkt(pkt)[95:76] + logic_pkt(pkt)[75]) ); + $fdisplay( file_handle, "%hf8f93", logic_pkt(pkt)[75:64] ); + $fdisplay( file_handle, "01f40433" ); + $fdisplay( file_handle, "0080b423" ); + //$fdisplay( file_handle, "%h", logic_pkt(pkt)[184:128] ); + $fdisplay( file_handle, "%h537", ({ {7{1'b0}}, logic_pkt(pkt)[184:172] } + logic_pkt(pkt)[171]) ); + $fdisplay( file_handle, "%h50513", ( logic_pkt(pkt)[171:160] + logic_pkt(pkt)[159]) ); + $fdisplay( file_handle, "01051513" ); + $fdisplay( file_handle, "01051513" ); + $fdisplay( file_handle, "%hfb7", (logic_pkt(pkt)[159:140] + logic_pkt(pkt)[139]) ); + $fdisplay( file_handle, "%hf8f93", logic_pkt(pkt)[139:128] ); + $fdisplay( file_handle, "01f50533" ); + $fdisplay( file_handle, "00a0b823" ); + // Advance x1 += 24 (h1018) + $fdisplay( file_handle, "01808093" ); + $fclose(file_handle); + + return pkt; +endfunction + +function automatic logic [185-1:0] logic_pkt (IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 p); + logic_pkt = { + // Header (MSB->LSB order) + p.src, + p.dst, + p.src_cgra_id, + p.dst_cgra_id, + p.src_cgra_x, + p.src_cgra_y, + p.dst_cgra_x, + p.dst_cgra_y, + p.opaque, + p.vc_id, + // Payload + p.payload.cmd, + p.payload.data.payload, + p.payload.data.predicate, + p.payload.data.bypass, + p.payload.data.delay, + p.payload.data_addr, + p.payload.ctrl.operation, + p.payload.ctrl.fu_in, + p.payload.ctrl.routing_xbar_outport, + p.payload.ctrl.fu_xbar_outport, + p.payload.ctrl.vector_factor_power, + p.payload.ctrl.is_last_ctrl, + p.payload.ctrl.write_reg_from, + p.payload.ctrl.write_reg_idx, + p.payload.ctrl.read_reg_from, + p.payload.ctrl.read_reg_idx, + p.payload.ctrl_addr + }; +endfunction + +function automatic IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 unpack_pkt (logic [217-1:0] v); + IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 p; + // Use a running index from LSB upward for clarity + int i = 0; + // ctrl_addr (4) + p.payload.ctrl_addr = v[i +: 4]; i += 4; + // ctrl (107) + p.payload.ctrl.read_reg_idx = v[i +: 16]; i += 16; + p.payload.ctrl.read_reg_from = v[i +: 4]; i += 4; + p.payload.ctrl.write_reg_idx = v[i +: 16]; i += 16; + p.payload.ctrl.write_reg_from = v[i +: 8]; i += 8; + p.payload.ctrl.is_last_ctrl = v[i +: 1]; i += 1; + p.payload.ctrl.vector_factor_power = v[i +: 3]; i += 3; + p.payload.ctrl.fu_xbar_outport = v[i +: 16]; i += 16; // 8*2 + p.payload.ctrl.routing_xbar_outport = v[i +: 24]; i += 24; // 8*3 + p.payload.ctrl.fu_in = v[i +: 12]; i += 12; // 4*3 + p.payload.ctrl.operation = v[i +: 7]; i += 7; + // data_addr (7) + p.payload.data_addr = v[i +: 7]; i += 7; + // data (67) + p.payload.data.delay = v[i +: 1]; i += 1; + p.payload.data.bypass = v[i +: 1]; i += 1; + p.payload.data.predicate = v[i +: 1]; i += 1; + p.payload.data.payload = v[i +: 64]; i += 64; + // cmd (5) + p.payload.cmd = v[i +: 5]; i += 5; + // header tail (27) + p.vc_id = v[i +: 1]; i += 1; + p.opaque = v[i +: 8]; i += 8; + p.dst_cgra_y = v[i +: 1]; i += 1; + p.dst_cgra_x = v[i +: 1]; i += 1; + p.src_cgra_y = v[i +: 1]; i += 1; + p.src_cgra_x = v[i +: 1]; i += 1; + p.dst_cgra_id = v[i +: 2]; i += 2; + p.src_cgra_id = v[i +: 2]; i += 2; + p.dst = v[i +: 5]; i += 5; + p.src = v[i +: 5]; i += 5; + + // Consistency check. + if (i != 217) + $error("unpack index mismatch: %0d != %0d", i, 217); + + return p; +endfunction + From 106824d58497c10d6d56809a6e38d480a8427e03 Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Tue, 6 Jan 2026 16:06:44 -0600 Subject: [PATCH 08/12] [SV tb] Update CGRA instance name. --- .../MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v b/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v index e8d80ccb..aa5ba572 100644 --- a/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v +++ b/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v @@ -2,7 +2,7 @@ `include "header_fir_vector_global_reduce.sv" -// vcs -sverilog -full64 -timescale=1ns/1ps ../MeshMultiCgraRTL__explicit__pickled.v MeshMultiCgraRTL_2x2_fir_scalar_tb.v -debug_access+all +// vcs -sverilog -full64 -timescale=1ns/1ps ../../MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v ../MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v -debug_access+all +incdir+.. module cgra_test ( @@ -19,7 +19,7 @@ module cgra_test logic [0:0] send_to_cpu_pkt__rdy; logic [0:0] send_to_cpu_pkt__val; - MeshMultiCgraRTL__975ce70dc1a0740a MultiCGRA (.*); + MeshMultiCgraRTL__explicit_vector_global_reduce MultiCGRA (.*); int PASS = 'd0; time pass_time_of = 'd0; From 3d274a9b4f9c23859e08b5ce0a3189d71b984fd5 Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Tue, 6 Jan 2026 16:07:34 -0600 Subject: [PATCH 09/12] [SV tb] Update run cmds. --- multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_scalar_tb.v | 1 + .../sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v | 1 + 2 files changed, 2 insertions(+) diff --git a/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_scalar_tb.v b/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_scalar_tb.v index 6f2063df..ac470ba4 100644 --- a/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_scalar_tb.v +++ b/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_scalar_tb.v @@ -3,6 +3,7 @@ `include "header.sv" // vcs -sverilog -full64 -timescale=1ns/1ps ../MeshMultiCgraRTL__explicit__pickled.v MeshMultiCgraRTL_2x2_fir_scalar_tb.v -debug_access+all +// vcs -sverilog -full64 -timescale=1ns/1ps ../../../../../coredec_acc_soc/accelerator_soc/MeshMultiCgraRTL__explicit__pickled.v ../MeshMultiCgraRTL_2x2_fir_scalar_tb.v -debug_access+all +incdir+.. module cgra_test ( diff --git a/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v b/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v index aa5ba572..a8356e3c 100644 --- a/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v +++ b/multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v @@ -3,6 +3,7 @@ `include "header_fir_vector_global_reduce.sv" // vcs -sverilog -full64 -timescale=1ns/1ps ../../MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v ../MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v -debug_access+all +incdir+.. +// vcs -sverilog -full64 -timescale=1ns/1ps ../../../../../coredec_acc_soc/accelerator_soc/MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v ../MeshMultiCgraRTL_2x2_fir_vector_global_reduce_tb.v -debug_access+all +incdir+.. module cgra_test ( From 6efba6be21b1633cb439490442ae033e88196e9e Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Tue, 6 Jan 2026 16:31:44 -0600 Subject: [PATCH 10/12] Revert "[PyMTL output] Adding generated RTL file with init fixes." This reverts commit a57fdfa9d481ee27dcf942673635a331fdbbd98e. --- ...__explicit_vector_global_reduce__pickled.v | 23496 ---------------- 1 file changed, 23496 deletions(-) delete mode 100644 multi_cgra/test/MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v diff --git a/multi_cgra/test/MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v b/multi_cgra/test/MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v deleted file mode 100644 index 8b2e5fa9..00000000 --- a/multi_cgra/test/MeshMultiCgraRTL__explicit_vector_global_reduce__pickled.v +++ /dev/null @@ -1,23496 +0,0 @@ -//------------------------------------------------------------------------- -// MeshMultiCgraRTL__explicit_vector_global_reduce.v -//------------------------------------------------------------------------- -// This file is generated by PyMTL SystemVerilog translation pass. - -// PyMTL BitStruct CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Definition -typedef struct packed { - logic [63:0] payload; - logic [0:0] predicate; - logic [0:0] bypass; - logic [0:0] delay; -} CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1; - -// PyMTL BitStruct CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Definition -typedef struct packed { - logic [6:0] operation; - logic [3:0][2:0] fu_in; - logic [7:0][2:0] routing_xbar_outport; - logic [7:0][1:0] fu_xbar_outport; - logic [2:0] vector_factor_power; - logic [0:0] is_last_ctrl; - logic [3:0][1:0] write_reg_from; - logic [3:0][3:0] write_reg_idx; - logic [3:0][0:0] read_reg_from; - logic [3:0][3:0] read_reg_idx; -} CGRAConfig_7_4_2_4_4_3__49d22cda396bec88; - -// PyMTL BitStruct MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Definition -typedef struct packed { - logic [4:0] cmd; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; - logic [6:0] data_addr; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 ctrl; - logic [3:0] ctrl_addr; -} MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a; - -// PyMTL BitStruct InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d Definition -typedef struct packed { - logic [1:0] src; - logic [1:0] dst; - logic [0:0] src_x; - logic [0:0] src_y; - logic [0:0] dst_x; - logic [0:0] dst_y; - logic [4:0] src_tile_id; - logic [4:0] dst_tile_id; - logic [2:0] remote_src_port; - logic [7:0] opaque; - logic [1:0] vc_id; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a payload; -} InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d; - -// PyMTL BitStruct IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 Definition -typedef struct packed { - logic [4:0] src; - logic [4:0] dst; - logic [1:0] src_cgra_id; - logic [1:0] dst_cgra_id; - logic [0:0] src_cgra_x; - logic [0:0] src_cgra_y; - logic [0:0] dst_cgra_x; - logic [0:0] dst_cgra_y; - logic [7:0] opaque; - logic [0:0] vc_id; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a payload; -} IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69; - -// PyMTL BitStruct ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad Definition -typedef struct packed { - logic [0:0] dst; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d inter_cgra_pkt; -} ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad; - -// PyMTL BitStruct MemAccessPacket_8_3_128__43c148781d2f2a57 Definition -typedef struct packed { - logic [2:0] src; - logic [1:0] dst; - logic [6:0] addr; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; - logic [1:0] src_cgra; - logic [4:0] src_tile; - logic [2:0] remote_src_port; - logic [0:0] streaming_rd; - logic [6:0] streaming_rd_stride; - logic [6:0] streaming_rd_end_addr; -} MemAccessPacket_8_3_128__43c148781d2f2a57; - -// PyMTL BitStruct MemAccessPacket_3_8_128__9f21b0bcdad2c061 Definition -typedef struct packed { - logic [1:0] src; - logic [2:0] dst; - logic [6:0] addr; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; - logic [1:0] src_cgra; - logic [4:0] src_tile; - logic [2:0] remote_src_port; - logic [0:0] streaming_rd; - logic [6:0] streaming_rd_stride; - logic [6:0] streaming_rd_end_addr; -} MemAccessPacket_3_8_128__9f21b0bcdad2c061; - -// PyMTL BitStruct MeshPosition_2x2__pos_x_1__pos_y_1 Definition -typedef struct packed { - logic [0:0] pos_x; - logic [0:0] pos_y; -} MeshPosition_2x2__pos_x_1__pos_y_1; - -// PyMTL Component NormalQueueCtrlRTL Definition -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueCtrlRTL__num_entries_2 -( - input logic [0:0] clk , - output logic [1:0] count , - output logic [0:0] raddr , - output logic [0:0] recv_rdy , - input logic [0:0] recv_val , - input logic [0:0] reset , - input logic [0:0] send_rdy , - output logic [0:0] send_val , - output logic [0:0] waddr , - output logic [0:0] wen -); - localparam logic [1:0] __const__num_entries_at__lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy = 2'd2; - localparam logic [1:0] __const__num_entries_at_up_reg = 2'd2; - logic [0:0] head; - logic [0:0] recv_xfer; - logic [0:0] send_xfer; - logic [0:0] tail; - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:121 - // s.recv_rdy //= lambda: s.count < num_entries - - always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy - recv_rdy = count < 2'( __const__num_entries_at__lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy ); - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:124 - // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy - - always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_xfer - recv_xfer = recv_val & recv_rdy; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:122 - // s.send_val //= lambda: s.count > 0 - - always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_send_val - send_val = count > 2'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:125 - // s.send_xfer //= lambda: s.send_val & s.send_rdy - - always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_send_xfer - send_xfer = send_val & send_rdy; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:127 - // @update_ff - // def up_reg(): - // - // if s.reset: - // s.head <<= 0 - // s.tail <<= 0 - // s.count <<= 0 - // - // else: - // if s.recv_xfer: - // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 - // - // if s.send_xfer: - // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 - // - // if s.recv_xfer & ~s.send_xfer: - // s.count <<= s.count + 1 - // elif ~s.recv_xfer & s.send_xfer: - // s.count <<= s.count - 1 - - always_ff @(posedge clk) begin : up_reg - if ( reset ) begin - head <= 1'd0; - tail <= 1'd0; - count <= 2'd0; - end - else begin - if ( recv_xfer ) begin - tail <= ( tail < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? tail + 1'd1 : 1'd0; - end - if ( send_xfer ) begin - head <= ( head < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? head + 1'd1 : 1'd0; - end - if ( recv_xfer & ( ~send_xfer ) ) begin - count <= count + 2'd1; - end - else if ( ( ~recv_xfer ) & send_xfer ) begin - count <= count - 2'd1; - end - end - end - - assign wen = recv_xfer; - assign waddr = tail; - assign raddr = head; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__a60a466e6e87778c -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__b5f6715511792c61 -( - input logic [0:0] clk , - input logic [0:0] raddr , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv_msg , - input logic [0:0] reset , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__a60a466e6e87778c rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__b5f6715511792c61 -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__raddr; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad dpath__recv_msg; - logic [0:0] dpath__reset; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__b5f6715511792c61 dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component InputUnitRTL Definition -// Full name: InputUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__QueueType_NormalQueueRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py - -module InputUnitRTL__d71c3d07db1f649e -( - input logic [0:0] clk , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queue - //------------------------------------------------------------- - - logic [0:0] queue__clk; - logic [1:0] queue__count; - logic [0:0] queue__reset; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad queue__recv__msg; - logic [0:0] queue__recv__rdy; - logic [0:0] queue__recv__val; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad queue__send__msg; - logic [0:0] queue__send__rdy; - logic [0:0] queue__send__val; - - NormalQueueRTL__b5f6715511792c61 queue - ( - .clk( queue__clk ), - .count( queue__count ), - .reset( queue__reset ), - .recv__msg( queue__recv__msg ), - .recv__rdy( queue__recv__rdy ), - .recv__val( queue__recv__val ), - .send__msg( queue__send__msg ), - .send__rdy( queue__send__rdy ), - .send__val( queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component queue - //------------------------------------------------------------- - - assign queue__clk = clk; - assign queue__reset = reset; - assign queue__recv__msg = recv__msg; - assign recv__rdy = queue__recv__rdy; - assign queue__recv__val = recv__val; - assign send__msg = queue__send__msg; - assign queue__send__rdy = send__rdy; - assign send__val = queue__send__val; - -endmodule - - -// PyMTL Component OutputUnitRTL Definition -// Full name: OutputUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__QueueType_None -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py - -module OutputUnitRTL__c199f9a52ff41678 -( - input logic [0:0] clk , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - assign send__msg = recv__msg; - assign recv__rdy = send__rdy; - assign send__val = recv__val; - -endmodule - - -// PyMTL Component XbarRouteUnitRTL Definition -// Full name: XbarRouteUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_outports_1 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py - -module XbarRouteUnitRTL__2110ed3935ab4c25 -( - input logic [0:0] clk , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg [0:0] , - input logic [0:0] send__rdy [0:0] , - output logic [0:0] send__val [0:0] -); - localparam logic [0:0] __const__num_outports_at_up_ru_routing = 1'd1; - logic [0:0] out_dir; - logic [0:0] send_val; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 - // @update - // def up_ru_recv_rdy(): - // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 - - always_comb begin : up_ru_recv_rdy - recv__rdy = send__rdy[out_dir] > 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 - // @update - // def up_ru_routing(): - // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) - // - // for i in range( num_outports ): - // s.send[i].val @= b1(0) - // - // if s.recv.val: - // s.send[ s.out_dir ].val @= b1(1) - - always_comb begin : up_ru_routing - out_dir = recv__msg.dst; - for ( int unsigned i = 1'd0; i < 1'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) - send__val[1'(i)] = 1'd0; - if ( recv__val ) begin - send__val[out_dir] = 1'd1; - end - end - - assign send__msg[0] = recv__msg; - assign send_val[0:0] = send__val[0]; - -endmodule - - -// PyMTL Component RegEnRst Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py - -module RegEnRst__Type_Bits6__reset_value_1 -( - input logic [0:0] clk , - input logic [0:0] en , - input logic [5:0] in_ , - output logic [5:0] out , - input logic [0:0] reset -); - localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 - // @update_ff - // def up_regenrst(): - // if s.reset: s.out <<= reset_value - // elif s.en: s.out <<= s.in_ - - always_ff @(posedge clk) begin : up_regenrst - if ( reset ) begin - out <= 6'( __const__reset_value_at_up_regenrst ); - end - else if ( en ) begin - out <= in_; - end - end - -endmodule - - -// PyMTL Component RoundRobinArbiterEn Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py - -module RoundRobinArbiterEn__nreqs_6 -( - input logic [0:0] clk , - input logic [0:0] en , - output logic [5:0] grants , - input logic [5:0] reqs , - input logic [0:0] reset -); - localparam logic [2:0] __const__nreqs_at_comb_reqs_int = 3'd6; - localparam logic [3:0] __const__nreqsX2_at_comb_reqs_int = 4'd12; - localparam logic [2:0] __const__nreqs_at_comb_grants = 3'd6; - localparam logic [2:0] __const__nreqs_at_comb_priority_int = 3'd6; - localparam logic [3:0] __const__nreqsX2_at_comb_priority_int = 4'd12; - localparam logic [3:0] __const__nreqsX2_at_comb_kills = 4'd12; - localparam logic [3:0] __const__nreqsX2_at_comb_grants_int = 4'd12; - logic [11:0] grants_int; - logic [12:0] kills; - logic [0:0] priority_en; - logic [11:0] priority_int; - logic [11:0] reqs_int; - //------------------------------------------------------------- - // Component priority_reg - //------------------------------------------------------------- - - logic [0:0] priority_reg__clk; - logic [0:0] priority_reg__en; - logic [5:0] priority_reg__in_; - logic [5:0] priority_reg__out; - logic [0:0] priority_reg__reset; - - RegEnRst__Type_Bits6__reset_value_1 priority_reg - ( - .clk( priority_reg__clk ), - .en( priority_reg__en ), - .in_( priority_reg__in_ ), - .out( priority_reg__out ), - .reset( priority_reg__reset ) - ); - - //------------------------------------------------------------- - // End of component priority_reg - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 - // @update - // def comb_grants(): - // for i in range( nreqs ): - // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] - - always_comb begin : comb_grants - for ( int unsigned i = 1'd0; i < 3'( __const__nreqs_at_comb_grants ); i += 1'd1 ) - grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 - // @update - // def comb_grants_int(): - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.grants_int[i] @= s.reqs_int[i] - // else: - // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] - - always_comb begin : comb_grants_int - for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - grants_int[4'(i)] = reqs_int[4'(i)]; - end - else - grants_int[4'(i)] = ( ~kills[4'(i)] ) & reqs_int[4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 - // @update - // def comb_kills(): - // s.kills[0] @= 1 - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.kills[i+1] @= s.reqs_int[i] - // else: - // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) - - always_comb begin : comb_kills - kills[4'd0] = 1'd1; - for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - kills[4'(i) + 4'd1] = reqs_int[4'(i)]; - end - else - kills[4'(i) + 4'd1] = kills[4'(i)] | ( ( ~kills[4'(i)] ) & reqs_int[4'(i)] ); - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 - // @update - // def comb_priority_en(): - // s.priority_en @= ( s.grants != 0 ) & s.en - - always_comb begin : comb_priority_en - priority_en = ( grants != 6'd0 ) & en; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 - // @update - // def comb_priority_int(): - // s.priority_int[ 0:nreqs ] @= s.priority_reg.out - // s.priority_int[nreqs:nreqsX2] @= 0 - - always_comb begin : comb_priority_int - priority_int[4'd5:4'd0] = priority_reg__out; - priority_int[4'd11:4'( __const__nreqs_at_comb_priority_int )] = 6'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 - // @update - // def comb_reqs_int(): - // s.reqs_int [ 0:nreqs ] @= s.reqs - // s.reqs_int [nreqs:nreqsX2] @= s.reqs - - always_comb begin : comb_reqs_int - reqs_int[4'd5:4'd0] = reqs; - reqs_int[4'd11:4'( __const__nreqs_at_comb_reqs_int )] = reqs; - end - - assign priority_reg__clk = clk; - assign priority_reg__reset = reset; - assign priority_reg__en = priority_en; - assign priority_reg__in_[5:1] = grants[4:0]; - assign priority_reg__in_[0:0] = grants[5:5]; - -endmodule - - -// PyMTL Component Encoder Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py - -module Encoder__in_nbits_6__out_nbits_3 -( - input logic [0:0] clk , - input logic [5:0] in_ , - output logic [2:0] out , - input logic [0:0] reset -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 - // @update - // def encode(): - // s.out @= 0 - // for i in range( s.in_nbits ): - // if s.in_[i]: - // s.out @= i - - always_comb begin : encode - out = 3'd0; - for ( int unsigned i = 1'd0; i < 3'd6; i += 1'd1 ) - if ( in_[3'(i)] ) begin - out = 3'(i); - end - end - -endmodule - - -// PyMTL Component Mux Definition -// Full name: Mux__Type_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__ninputs_6 -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__899292f481a8b227 -( - input logic [0:0] clk , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad in_ [0:5], - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad out , - input logic [0:0] reset , - input logic [2:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component SwitchUnitRTL Definition -// Full name: SwitchUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_inports_6 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py - -module SwitchUnitRTL__2dc7ee83ee1f485f -( - input logic [0:0] clk , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg [0:5] , - output logic [0:0] recv__rdy [0:5] , - input logic [0:0] recv__val [0:5] , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd6; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [5:0] arbiter__grants; - logic [5:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_6 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [5:0] encoder__in_; - logic [2:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_6__out_nbits_3 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad mux__in_ [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad mux__out; - logic [0:0] mux__reset; - logic [2:0] mux__sel; - - Mux__899292f481a8b227 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 - // @update - // def up_get_en(): - // for i in range( num_inports ): - // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) - - always_comb begin : up_get_en - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) - recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 - // @update - // def up_send_val(): - // s.send.val @= s.arbiter.grants > 0 - - always_comb begin : up_send_val - send__val = arbiter__grants > 6'd0; - end - - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign arbiter__en = 1'd1; - assign mux__clk = clk; - assign mux__reset = reset; - assign send__msg = mux__out; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign encoder__in_ = arbiter__grants; - assign mux__sel = encoder__out; - assign arbiter__reqs[0:0] = recv__val[0]; - assign mux__in_[0] = recv__msg[0]; - assign arbiter__reqs[1:1] = recv__val[1]; - assign mux__in_[1] = recv__msg[1]; - assign arbiter__reqs[2:2] = recv__val[2]; - assign mux__in_[2] = recv__msg[2]; - assign arbiter__reqs[3:3] = recv__val[3]; - assign mux__in_[3] = recv__msg[3]; - assign arbiter__reqs[4:4] = recv__val[4]; - assign mux__in_[4] = recv__msg[4]; - assign arbiter__reqs[5:5] = recv__val[5]; - assign mux__in_[5] = recv__msg[5]; - -endmodule - - -// PyMTL Component XbarRTL Definition -// Full name: XbarRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_inports_6__num_outports_1__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRTL.py - -module XbarRTL__51e7846dd37f4a41 -( - input logic [0:0] clk , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg [0:5] , - output logic [0:0] recv__rdy [0:5] , - input logic [0:0] recv__val [0:5] , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg [0:0] , - input logic [0:0] send__rdy [0:0] , - output logic [0:0] send__val [0:0] -); - //------------------------------------------------------------- - // Component input_units[0:5] - //------------------------------------------------------------- - - logic [0:0] input_units__clk [0:5]; - logic [0:0] input_units__reset [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad input_units__recv__msg [0:5]; - logic [0:0] input_units__recv__rdy [0:5]; - logic [0:0] input_units__recv__val [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad input_units__send__msg [0:5]; - logic [0:0] input_units__send__rdy [0:5]; - logic [0:0] input_units__send__val [0:5]; - - InputUnitRTL__d71c3d07db1f649e input_units__0 - ( - .clk( input_units__clk[0] ), - .reset( input_units__reset[0] ), - .recv__msg( input_units__recv__msg[0] ), - .recv__rdy( input_units__recv__rdy[0] ), - .recv__val( input_units__recv__val[0] ), - .send__msg( input_units__send__msg[0] ), - .send__rdy( input_units__send__rdy[0] ), - .send__val( input_units__send__val[0] ) - ); - - InputUnitRTL__d71c3d07db1f649e input_units__1 - ( - .clk( input_units__clk[1] ), - .reset( input_units__reset[1] ), - .recv__msg( input_units__recv__msg[1] ), - .recv__rdy( input_units__recv__rdy[1] ), - .recv__val( input_units__recv__val[1] ), - .send__msg( input_units__send__msg[1] ), - .send__rdy( input_units__send__rdy[1] ), - .send__val( input_units__send__val[1] ) - ); - - InputUnitRTL__d71c3d07db1f649e input_units__2 - ( - .clk( input_units__clk[2] ), - .reset( input_units__reset[2] ), - .recv__msg( input_units__recv__msg[2] ), - .recv__rdy( input_units__recv__rdy[2] ), - .recv__val( input_units__recv__val[2] ), - .send__msg( input_units__send__msg[2] ), - .send__rdy( input_units__send__rdy[2] ), - .send__val( input_units__send__val[2] ) - ); - - InputUnitRTL__d71c3d07db1f649e input_units__3 - ( - .clk( input_units__clk[3] ), - .reset( input_units__reset[3] ), - .recv__msg( input_units__recv__msg[3] ), - .recv__rdy( input_units__recv__rdy[3] ), - .recv__val( input_units__recv__val[3] ), - .send__msg( input_units__send__msg[3] ), - .send__rdy( input_units__send__rdy[3] ), - .send__val( input_units__send__val[3] ) - ); - - InputUnitRTL__d71c3d07db1f649e input_units__4 - ( - .clk( input_units__clk[4] ), - .reset( input_units__reset[4] ), - .recv__msg( input_units__recv__msg[4] ), - .recv__rdy( input_units__recv__rdy[4] ), - .recv__val( input_units__recv__val[4] ), - .send__msg( input_units__send__msg[4] ), - .send__rdy( input_units__send__rdy[4] ), - .send__val( input_units__send__val[4] ) - ); - - InputUnitRTL__d71c3d07db1f649e input_units__5 - ( - .clk( input_units__clk[5] ), - .reset( input_units__reset[5] ), - .recv__msg( input_units__recv__msg[5] ), - .recv__rdy( input_units__recv__rdy[5] ), - .recv__val( input_units__recv__val[5] ), - .send__msg( input_units__send__msg[5] ), - .send__rdy( input_units__send__rdy[5] ), - .send__val( input_units__send__val[5] ) - ); - - //------------------------------------------------------------- - // End of component input_units[0:5] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component output_units[0:0] - //------------------------------------------------------------- - - logic [0:0] output_units__clk [0:0]; - logic [0:0] output_units__reset [0:0]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad output_units__recv__msg [0:0]; - logic [0:0] output_units__recv__rdy [0:0]; - logic [0:0] output_units__recv__val [0:0]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad output_units__send__msg [0:0]; - logic [0:0] output_units__send__rdy [0:0]; - logic [0:0] output_units__send__val [0:0]; - - OutputUnitRTL__c199f9a52ff41678 output_units__0 - ( - .clk( output_units__clk[0] ), - .reset( output_units__reset[0] ), - .recv__msg( output_units__recv__msg[0] ), - .recv__rdy( output_units__recv__rdy[0] ), - .recv__val( output_units__recv__val[0] ), - .send__msg( output_units__send__msg[0] ), - .send__rdy( output_units__send__rdy[0] ), - .send__val( output_units__send__val[0] ) - ); - - //------------------------------------------------------------- - // End of component output_units[0:0] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component route_units[0:5] - //------------------------------------------------------------- - - logic [0:0] route_units__clk [0:5]; - logic [0:0] route_units__reset [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad route_units__recv__msg [0:5]; - logic [0:0] route_units__recv__rdy [0:5]; - logic [0:0] route_units__recv__val [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad route_units__send__msg [0:5][0:0]; - logic [0:0] route_units__send__rdy [0:5][0:0]; - logic [0:0] route_units__send__val [0:5][0:0]; - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__0 - ( - .clk( route_units__clk[0] ), - .reset( route_units__reset[0] ), - .recv__msg( route_units__recv__msg[0] ), - .recv__rdy( route_units__recv__rdy[0] ), - .recv__val( route_units__recv__val[0] ), - .send__msg( route_units__send__msg[0] ), - .send__rdy( route_units__send__rdy[0] ), - .send__val( route_units__send__val[0] ) - ); - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__1 - ( - .clk( route_units__clk[1] ), - .reset( route_units__reset[1] ), - .recv__msg( route_units__recv__msg[1] ), - .recv__rdy( route_units__recv__rdy[1] ), - .recv__val( route_units__recv__val[1] ), - .send__msg( route_units__send__msg[1] ), - .send__rdy( route_units__send__rdy[1] ), - .send__val( route_units__send__val[1] ) - ); - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__2 - ( - .clk( route_units__clk[2] ), - .reset( route_units__reset[2] ), - .recv__msg( route_units__recv__msg[2] ), - .recv__rdy( route_units__recv__rdy[2] ), - .recv__val( route_units__recv__val[2] ), - .send__msg( route_units__send__msg[2] ), - .send__rdy( route_units__send__rdy[2] ), - .send__val( route_units__send__val[2] ) - ); - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__3 - ( - .clk( route_units__clk[3] ), - .reset( route_units__reset[3] ), - .recv__msg( route_units__recv__msg[3] ), - .recv__rdy( route_units__recv__rdy[3] ), - .recv__val( route_units__recv__val[3] ), - .send__msg( route_units__send__msg[3] ), - .send__rdy( route_units__send__rdy[3] ), - .send__val( route_units__send__val[3] ) - ); - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__4 - ( - .clk( route_units__clk[4] ), - .reset( route_units__reset[4] ), - .recv__msg( route_units__recv__msg[4] ), - .recv__rdy( route_units__recv__rdy[4] ), - .recv__val( route_units__recv__val[4] ), - .send__msg( route_units__send__msg[4] ), - .send__rdy( route_units__send__rdy[4] ), - .send__val( route_units__send__val[4] ) - ); - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__5 - ( - .clk( route_units__clk[5] ), - .reset( route_units__reset[5] ), - .recv__msg( route_units__recv__msg[5] ), - .recv__rdy( route_units__recv__rdy[5] ), - .recv__val( route_units__recv__val[5] ), - .send__msg( route_units__send__msg[5] ), - .send__rdy( route_units__send__rdy[5] ), - .send__val( route_units__send__val[5] ) - ); - - //------------------------------------------------------------- - // End of component route_units[0:5] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component switch_units[0:0] - //------------------------------------------------------------- - - logic [0:0] switch_units__clk [0:0]; - logic [0:0] switch_units__reset [0:0]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad switch_units__recv__msg [0:0][0:5]; - logic [0:0] switch_units__recv__rdy [0:0][0:5]; - logic [0:0] switch_units__recv__val [0:0][0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad switch_units__send__msg [0:0]; - logic [0:0] switch_units__send__rdy [0:0]; - logic [0:0] switch_units__send__val [0:0]; - - SwitchUnitRTL__2dc7ee83ee1f485f switch_units__0 - ( - .clk( switch_units__clk[0] ), - .reset( switch_units__reset[0] ), - .recv__msg( switch_units__recv__msg[0] ), - .recv__rdy( switch_units__recv__rdy[0] ), - .recv__val( switch_units__recv__val[0] ), - .send__msg( switch_units__send__msg[0] ), - .send__rdy( switch_units__send__rdy[0] ), - .send__val( switch_units__send__val[0] ) - ); - - //------------------------------------------------------------- - // End of component switch_units[0:0] - //------------------------------------------------------------- - - assign input_units__clk[0] = clk; - assign input_units__reset[0] = reset; - assign input_units__clk[1] = clk; - assign input_units__reset[1] = reset; - assign input_units__clk[2] = clk; - assign input_units__reset[2] = reset; - assign input_units__clk[3] = clk; - assign input_units__reset[3] = reset; - assign input_units__clk[4] = clk; - assign input_units__reset[4] = reset; - assign input_units__clk[5] = clk; - assign input_units__reset[5] = reset; - assign route_units__clk[0] = clk; - assign route_units__reset[0] = reset; - assign route_units__clk[1] = clk; - assign route_units__reset[1] = reset; - assign route_units__clk[2] = clk; - assign route_units__reset[2] = reset; - assign route_units__clk[3] = clk; - assign route_units__reset[3] = reset; - assign route_units__clk[4] = clk; - assign route_units__reset[4] = reset; - assign route_units__clk[5] = clk; - assign route_units__reset[5] = reset; - assign switch_units__clk[0] = clk; - assign switch_units__reset[0] = reset; - assign output_units__clk[0] = clk; - assign output_units__reset[0] = reset; - assign input_units__recv__msg[0] = recv__msg[0]; - assign recv__rdy[0] = input_units__recv__rdy[0]; - assign input_units__recv__val[0] = recv__val[0]; - assign route_units__recv__msg[0] = input_units__send__msg[0]; - assign input_units__send__rdy[0] = route_units__recv__rdy[0]; - assign route_units__recv__val[0] = input_units__send__val[0]; - assign input_units__recv__msg[1] = recv__msg[1]; - assign recv__rdy[1] = input_units__recv__rdy[1]; - assign input_units__recv__val[1] = recv__val[1]; - assign route_units__recv__msg[1] = input_units__send__msg[1]; - assign input_units__send__rdy[1] = route_units__recv__rdy[1]; - assign route_units__recv__val[1] = input_units__send__val[1]; - assign input_units__recv__msg[2] = recv__msg[2]; - assign recv__rdy[2] = input_units__recv__rdy[2]; - assign input_units__recv__val[2] = recv__val[2]; - assign route_units__recv__msg[2] = input_units__send__msg[2]; - assign input_units__send__rdy[2] = route_units__recv__rdy[2]; - assign route_units__recv__val[2] = input_units__send__val[2]; - assign input_units__recv__msg[3] = recv__msg[3]; - assign recv__rdy[3] = input_units__recv__rdy[3]; - assign input_units__recv__val[3] = recv__val[3]; - assign route_units__recv__msg[3] = input_units__send__msg[3]; - assign input_units__send__rdy[3] = route_units__recv__rdy[3]; - assign route_units__recv__val[3] = input_units__send__val[3]; - assign input_units__recv__msg[4] = recv__msg[4]; - assign recv__rdy[4] = input_units__recv__rdy[4]; - assign input_units__recv__val[4] = recv__val[4]; - assign route_units__recv__msg[4] = input_units__send__msg[4]; - assign input_units__send__rdy[4] = route_units__recv__rdy[4]; - assign route_units__recv__val[4] = input_units__send__val[4]; - assign input_units__recv__msg[5] = recv__msg[5]; - assign recv__rdy[5] = input_units__recv__rdy[5]; - assign input_units__recv__val[5] = recv__val[5]; - assign route_units__recv__msg[5] = input_units__send__msg[5]; - assign input_units__send__rdy[5] = route_units__recv__rdy[5]; - assign route_units__recv__val[5] = input_units__send__val[5]; - assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; - assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; - assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; - assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; - assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; - assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; - assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; - assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; - assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; - assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; - assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; - assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; - assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; - assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; - assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; - assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; - assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; - assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; - assign output_units__recv__msg[0] = switch_units__send__msg[0]; - assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; - assign output_units__recv__val[0] = switch_units__send__val[0]; - assign send__msg[0] = output_units__send__msg[0]; - assign output_units__send__rdy[0] = send__rdy[0]; - assign send__val[0] = output_units__send__val[0]; - -endmodule - - -// PyMTL Component NormalQueueCtrlRTL Definition -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueCtrlRTL__num_entries_16 -( - input logic [0:0] clk , - output logic [4:0] count , - output logic [3:0] raddr , - output logic [0:0] recv_rdy , - input logic [0:0] recv_val , - input logic [0:0] reset , - input logic [0:0] send_rdy , - output logic [0:0] send_val , - output logic [3:0] waddr , - output logic [0:0] wen -); - localparam logic [4:0] __const__num_entries_at__lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy = 5'd16; - localparam logic [4:0] __const__num_entries_at_up_reg = 5'd16; - logic [3:0] head; - logic [0:0] recv_xfer; - logic [0:0] send_xfer; - logic [3:0] tail; - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:121 - // s.recv_rdy //= lambda: s.count < num_entries - - always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy - recv_rdy = count < 5'( __const__num_entries_at__lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy ); - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:124 - // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy - - always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_xfer - recv_xfer = recv_val & recv_rdy; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:122 - // s.send_val //= lambda: s.count > 0 - - always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_send_val - send_val = count > 5'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:125 - // s.send_xfer //= lambda: s.send_val & s.send_rdy - - always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_send_xfer - send_xfer = send_val & send_rdy; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:127 - // @update_ff - // def up_reg(): - // - // if s.reset: - // s.head <<= 0 - // s.tail <<= 0 - // s.count <<= 0 - // - // else: - // if s.recv_xfer: - // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 - // - // if s.send_xfer: - // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 - // - // if s.recv_xfer & ~s.send_xfer: - // s.count <<= s.count + 1 - // elif ~s.recv_xfer & s.send_xfer: - // s.count <<= s.count - 1 - - always_ff @(posedge clk) begin : up_reg - if ( reset ) begin - head <= 4'd0; - tail <= 4'd0; - count <= 5'd0; - end - else begin - if ( recv_xfer ) begin - tail <= ( tail < ( 4'( __const__num_entries_at_up_reg ) - 4'd1 ) ) ? tail + 4'd1 : 4'd0; - end - if ( send_xfer ) begin - head <= ( head < ( 4'( __const__num_entries_at_up_reg ) - 4'd1 ) ) ? head + 4'd1 : 4'd0; - end - if ( recv_xfer & ( ~send_xfer ) ) begin - count <= count + 5'd1; - end - else if ( ( ~recv_xfer ) & send_xfer ) begin - count <= count - 5'd1; - end - end - end - - assign wen = recv_xfer; - assign waddr = tail; - assign raddr = head; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__nregs_16__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__769ad531033521b3 -( - input logic [0:0] clk , - input logic [3:0] raddr [0:0], - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rdata [0:0], - input logic [0:0] reset , - input logic [3:0] waddr [0:0], - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d regs [0:15]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_16 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__a1611e9294891a09 -( - input logic [0:0] clk , - input logic [3:0] raddr , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_msg , - input logic [0:0] reset , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_msg , - input logic [3:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [3:0] rf__raddr [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [3:0] rf__waddr [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__769ad531033521b3 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_16 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__a1611e9294891a09 -( - input logic [0:0] clk , - output logic [4:0] count , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [4:0] ctrl__count; - logic [3:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [3:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_16 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [3:0] dpath__raddr; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__recv_msg; - logic [0:0] dpath__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__send_msg; - logic [3:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__a1611e9294891a09 dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component GlobalReduceUnitRTL Definition -// Full name: GlobalReduceUnitRTL__InterCgraPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d -// At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py - -module GlobalReduceUnitRTL__7c4d8effbf794a25 -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_count__msg , - output logic [0:0] recv_count__rdy , - input logic [0:0] recv_count__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_data__msg , - output logic [0:0] recv_data__rdy , - input logic [0:0] recv_data__val , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL = 5'd19; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 receiving_count; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reduce_add_value; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reduce_mul_value; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 sending_count; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 target_count; - //------------------------------------------------------------- - // Component queue - //------------------------------------------------------------- - - logic [0:0] queue__clk; - logic [4:0] queue__count; - logic [0:0] queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__recv__msg; - logic [0:0] queue__recv__rdy; - logic [0:0] queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__send__msg; - logic [0:0] queue__send__rdy; - logic [0:0] queue__send__val; - - NormalQueueRTL__a1611e9294891a09 queue - ( - .clk( queue__clk ), - .count( queue__count ), - .reset( queue__reset ), - .recv__msg( queue__recv__msg ), - .recv__rdy( queue__recv__rdy ), - .recv__val( queue__recv__val ), - .send__msg( queue__send__msg ), - .send__rdy( queue__send__rdy ), - .send__val( queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component queue - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:45 - // @update - // def set_recv_rdy(): - // s.recv_data.rdy @= 0 - // s.queue.recv.val @= 0 - // s.queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // if s.target_count.payload > s.receiving_count.payload: - // s.recv_data.rdy @= s.queue.recv.rdy - // s.queue.recv.msg @= s.recv_data.msg - // s.queue.recv.val @= s.recv_data.val - - always_comb begin : set_recv_rdy - recv_data__rdy = 1'd0; - queue__recv__val = 1'd0; - queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - if ( target_count.payload > receiving_count.payload ) begin - recv_data__rdy = queue__recv__rdy; - queue__recv__msg = recv_data__msg; - queue__recv__val = recv_data__val; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:74 - // @update - // def update_send(): - // s.send.msg @= ControllerXbarPktType(0, 0) - // s.send.val @= 0 - // s.queue.send.rdy @= 0 - // if (s.target_count.payload > 0) & (s.receiving_count.payload == s.target_count.payload): - // # Updates the cmd type, result value, and src/dst. - // if s.queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: - // s.send.msg.inter_cgra_pkt.payload.cmd @= CMD_GLOBAL_REDUCE_ADD_RESPONSE - // s.send.msg.inter_cgra_pkt.payload.data @= s.reduce_add_value - // elif s.queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL: - // s.send.msg.inter_cgra_pkt.payload.cmd @= CMD_GLOBAL_REDUCE_MUL_RESPONSE - // s.send.msg.inter_cgra_pkt.payload.data @= s.reduce_mul_value - // s.send.msg.inter_cgra_pkt.src @= s.queue.send.msg.dst - // s.send.msg.inter_cgra_pkt.dst @= s.queue.send.msg.src - // s.send.msg.inter_cgra_pkt.src_x @= s.queue.send.msg.dst_x - // s.send.msg.inter_cgra_pkt.src_y @= s.queue.send.msg.dst_y - // s.send.msg.inter_cgra_pkt.dst_x @= s.queue.send.msg.src_x - // s.send.msg.inter_cgra_pkt.dst_y @= s.queue.send.msg.src_y - // s.send.msg.inter_cgra_pkt.src_tile_id @= s.queue.send.msg.dst_tile_id - // s.send.msg.inter_cgra_pkt.dst_tile_id @= s.queue.send.msg.src_tile_id - // s.queue.send.rdy @= s.send.rdy - // s.send.val @= s.queue.send.val - - always_comb begin : update_send - send__msg = { 1'd0, 221'd0 }; - send__val = 1'd0; - queue__send__rdy = 1'd0; - if ( ( target_count.payload > 64'd0 ) & ( receiving_count.payload == target_count.payload ) ) begin - if ( queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin - send__msg.inter_cgra_pkt.payload.cmd = 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ); - send__msg.inter_cgra_pkt.payload.data = reduce_add_value; - end - else if ( queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL ) ) begin - send__msg.inter_cgra_pkt.payload.cmd = 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ); - send__msg.inter_cgra_pkt.payload.data = reduce_mul_value; - end - send__msg.inter_cgra_pkt.src = queue__send__msg.dst; - send__msg.inter_cgra_pkt.dst = queue__send__msg.src; - send__msg.inter_cgra_pkt.src_x = queue__send__msg.dst_x; - send__msg.inter_cgra_pkt.src_y = queue__send__msg.dst_y; - send__msg.inter_cgra_pkt.dst_x = queue__send__msg.src_x; - send__msg.inter_cgra_pkt.dst_y = queue__send__msg.src_y; - send__msg.inter_cgra_pkt.src_tile_id = queue__send__msg.dst_tile_id; - send__msg.inter_cgra_pkt.dst_tile_id = queue__send__msg.src_tile_id; - queue__send__rdy = send__rdy; - send__val = queue__send__val; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:98 - // @update_ff - // def accumulate_value(): - // if s.reset | (s.sending_count == s.target_count): - // s.reduce_add_value <<= DataType(0, 0, 0, 0) - // s.reduce_mul_value <<= DataType(1, 0, 0, 0) - // else: - // if s.recv_data.val & \ - // s.recv_data.rdy: - // if s.recv_data.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: - // s.reduce_add_value <<= DataType(s.reduce_add_value.payload + s.recv_data.msg.payload.data.payload, - // s.recv_data.msg.payload.data.predicate, - // 0, - // 0) - // elif s.recv_data.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL: - // s.reduce_mul_value <<= DataType(s.reduce_mul_value.payload * s.recv_data.msg.payload.data.payload, - // s.recv_data.msg.payload.data.predicate, - // 0, - // 0) - - always_ff @(posedge clk) begin : accumulate_value - if ( reset | ( sending_count == target_count ) ) begin - reduce_add_value <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - reduce_mul_value <= { 64'd1, 1'd0, 1'd0, 1'd0 }; - end - else if ( recv_data__val & recv_data__rdy ) begin - if ( recv_data__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin - reduce_add_value <= { reduce_add_value.payload + recv_data__msg.payload.data.payload, recv_data__msg.payload.data.predicate, 1'd0, 1'd0 }; - end - else if ( recv_data__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL ) ) begin - reduce_mul_value <= { reduce_mul_value.payload * recv_data__msg.payload.data.payload, recv_data__msg.payload.data.predicate, 1'd0, 1'd0 }; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:55 - // @update_ff - // def update_count(): - // if s.reset: - // s.target_count <<= DataType(0, 0, 0, 0) - // s.receiving_count <<= DataType(0, 0, 0, 0) - // s.sending_count <<= DataType(0, 0, 0, 0) - // else: - // if s.recv_count.val & s.recv_count.rdy: - // s.target_count <<= DataType(s.recv_count.msg.payload.data.payload, 0, 0, 0) - // if s.recv_data.val & s.recv_data.rdy: - // s.receiving_count <<= DataType(s.receiving_count.payload + 1, 0, 0, 0) - // if s.send.rdy & s.send.val: - // s.sending_count <<= DataType(s.sending_count.payload + 1, 0, 0, 0) - // elif (s.sending_count == s.receiving_count) & \ - // (s.sending_count == s.target_count) & \ - // (s.target_count.payload > 0): - // s.sending_count <<= DataType(0, 0, 0, 0) - // s.receiving_count <<= DataType(0, 0, 0, 0) - - always_ff @(posedge clk) begin : update_count - if ( reset ) begin - target_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - receiving_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - sending_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - else begin - if ( recv_count__val & recv_count__rdy ) begin - target_count <= { recv_count__msg.payload.data.payload, 1'd0, 1'd0, 1'd0 }; - end - if ( recv_data__val & recv_data__rdy ) begin - receiving_count <= { receiving_count.payload + 64'd1, 1'd0, 1'd0, 1'd0 }; - end - if ( send__rdy & send__val ) begin - sending_count <= { sending_count.payload + 64'd1, 1'd0, 1'd0, 1'd0 }; - end - else if ( ( ( sending_count == receiving_count ) & ( sending_count == target_count ) ) & ( target_count.payload > 64'd0 ) ) begin - sending_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - receiving_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - end - end - - assign queue__clk = clk; - assign queue__reset = reset; - assign recv_count__rdy = 1'd1; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__80167091524f71e4 -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__a1c7a5a18a302c36 -( - input logic [0:0] clk , - input logic [0:0] raddr , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_msg , - input logic [0:0] reset , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__80167091524f71e4 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__a1c7a5a18a302c36 -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__raddr; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__recv_msg; - logic [0:0] dpath__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__a1c7a5a18a302c36 dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__96d83eaf701da4cb -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__c7280ffb0786127e -( - input logic [0:0] clk , - input logic [0:0] raddr , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_msg , - input logic [0:0] reset , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__96d83eaf701da4cb rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__c7280ffb0786127e -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__raddr; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__recv_msg; - logic [0:0] dpath__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__c7280ffb0786127e dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component ChannelRTL Definition -// Full name: ChannelRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_NormalQueueRTL__latency_1 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py - -module ChannelRTL__551ecec02ed96ac9 -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queues[0:0] - //------------------------------------------------------------- - - logic [0:0] queues__clk [0:0]; - logic [1:0] queues__count [0:0]; - logic [0:0] queues__reset [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queues__recv__msg [0:0]; - logic [0:0] queues__recv__rdy [0:0]; - logic [0:0] queues__recv__val [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queues__send__msg [0:0]; - logic [0:0] queues__send__rdy [0:0]; - logic [0:0] queues__send__val [0:0]; - - NormalQueueRTL__c7280ffb0786127e queues__0 - ( - .clk( queues__clk[0] ), - .count( queues__count[0] ), - .reset( queues__reset[0] ), - .recv__msg( queues__recv__msg[0] ), - .recv__rdy( queues__recv__rdy[0] ), - .recv__val( queues__recv__val[0] ), - .send__msg( queues__send__msg[0] ), - .send__rdy( queues__send__rdy[0] ), - .send__val( queues__send__val[0] ) - ); - - //------------------------------------------------------------- - // End of component queues[0:0] - //------------------------------------------------------------- - - assign queues__clk[0] = clk; - assign queues__reset[0] = reset; - assign queues__recv__msg[0] = recv__msg; - assign recv__rdy = queues__recv__rdy[0]; - assign queues__recv__val[0] = recv__val; - assign send__msg = queues__send__msg[0]; - assign queues__send__rdy[0] = send__rdy; - assign send__val = queues__send__val[0]; - -endmodule - - -// PyMTL Component ControllerRTL Definition -// Full name: ControllerRTL__InterCgraPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__multi_cgra_rows_2__multi_cgra_columns_2__num_tiles_16__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)} -// At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py - -module ControllerRTL__e06602ce343fdc8d -( - input logic [1:0] cgra_id , - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , - output logic [0:0] recv_from_cpu_pkt__rdy , - input logic [0:0] recv_from_cpu_pkt__val , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_ctrl_ring_pkt__msg , - output logic [0:0] recv_from_ctrl_ring_pkt__rdy , - input logic [0:0] recv_from_ctrl_ring_pkt__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_inter_cgra_noc__msg , - output logic [0:0] recv_from_inter_cgra_noc__rdy , - input logic [0:0] recv_from_inter_cgra_noc__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt__msg , - output logic [0:0] recv_from_tile_load_request_pkt__rdy , - input logic [0:0] recv_from_tile_load_request_pkt__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt__msg , - output logic [0:0] recv_from_tile_load_response_pkt__rdy , - input logic [0:0] recv_from_tile_load_response_pkt__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt__msg , - output logic [0:0] recv_from_tile_store_request_pkt__rdy , - input logic [0:0] recv_from_tile_store_request_pkt__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , - input logic [0:0] send_to_cpu_pkt__rdy , - output logic [0:0] send_to_cpu_pkt__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_ctrl_ring_pkt__msg , - input logic [0:0] send_to_ctrl_ring_pkt__rdy , - output logic [0:0] send_to_ctrl_ring_pkt__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_inter_cgra_noc__msg , - input logic [0:0] send_to_inter_cgra_noc__rdy , - output logic [0:0] send_to_inter_cgra_noc__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request__msg , - input logic [0:0] send_to_mem_load_request__rdy , - output logic [0:0] send_to_mem_load_request__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request__msg , - input logic [0:0] send_to_mem_store_request__rdy , - output logic [0:0] send_to_mem_store_request__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response__msg , - input logic [0:0] send_to_tile_load_response__rdy , - output logic [0:0] send_to_tile_load_response__val -); - localparam logic [2:0] __const__CONTROLLER_CROSSBAR_INPORTS = 3'd6; - localparam logic [4:0] __const__num_tiles_at_update_received_msg = 5'd16; - localparam logic [3:0] __const__CMD_LOAD_REQUEST = 4'd10; - localparam logic [3:0] __const__CMD_STORE_REQUEST = 4'd12; - localparam logic [3:0] __const__CMD_LOAD_RESPONSE = 4'd11; - localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_COUNT = 5'd17; - localparam logic [1:0] __const__CMD_CONFIG = 2'd3; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; - localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; - localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; - localparam logic [3:0] __const__CMD_CONFIG_CTRL_LOWER_BOUND = 4'd9; - localparam logic [3:0] __const__CMD_CONST = 4'd13; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; - localparam logic [0:0] __const__CMD_PAUSE = 1'd1; - localparam logic [4:0] __const__CMD_PRESERVE = 5'd22; - localparam logic [3:0] __const__CMD_RESUME = 4'd15; - localparam logic [4:0] __const__CMD_RECORD_PHI_ADDR = 5'd16; - localparam logic [1:0] __const__CMD_TERMINATE = 2'd2; - localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; - localparam logic [2:0] __const__addr_offset_nbits_at_capture_addr_dst_id = 3'd5; - logic [1:0] addr2controller_lut [0:3]; - logic [1:0] addr_dst_id; - logic [0:0] idTo2d_x_lut [0:3]; - logic [0:0] idTo2d_y_lut [0:3]; - //------------------------------------------------------------- - // Component crossbar - //------------------------------------------------------------- - - logic [0:0] crossbar__clk; - logic [0:0] crossbar__reset; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad crossbar__recv__msg [0:5]; - logic [0:0] crossbar__recv__rdy [0:5]; - logic [0:0] crossbar__recv__val [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad crossbar__send__msg [0:0]; - logic [0:0] crossbar__send__rdy [0:0]; - logic [0:0] crossbar__send__val [0:0]; - - XbarRTL__51e7846dd37f4a41 crossbar - ( - .clk( crossbar__clk ), - .reset( crossbar__reset ), - .recv__msg( crossbar__recv__msg ), - .recv__rdy( crossbar__recv__rdy ), - .recv__val( crossbar__recv__val ), - .send__msg( crossbar__send__msg ), - .send__rdy( crossbar__send__rdy ), - .send__val( crossbar__send__val ) - ); - - //------------------------------------------------------------- - // End of component crossbar - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component global_reduce_unit - //------------------------------------------------------------- - - logic [0:0] global_reduce_unit__clk; - logic [0:0] global_reduce_unit__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d global_reduce_unit__recv_count__msg; - logic [0:0] global_reduce_unit__recv_count__rdy; - logic [0:0] global_reduce_unit__recv_count__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d global_reduce_unit__recv_data__msg; - logic [0:0] global_reduce_unit__recv_data__rdy; - logic [0:0] global_reduce_unit__recv_data__val; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad global_reduce_unit__send__msg; - logic [0:0] global_reduce_unit__send__rdy; - logic [0:0] global_reduce_unit__send__val; - - GlobalReduceUnitRTL__7c4d8effbf794a25 global_reduce_unit - ( - .clk( global_reduce_unit__clk ), - .reset( global_reduce_unit__reset ), - .recv_count__msg( global_reduce_unit__recv_count__msg ), - .recv_count__rdy( global_reduce_unit__recv_count__rdy ), - .recv_count__val( global_reduce_unit__recv_count__val ), - .recv_data__msg( global_reduce_unit__recv_data__msg ), - .recv_data__rdy( global_reduce_unit__recv_data__rdy ), - .recv_data__val( global_reduce_unit__recv_data__val ), - .send__msg( global_reduce_unit__send__msg ), - .send__rdy( global_reduce_unit__send__rdy ), - .send__val( global_reduce_unit__send__val ) - ); - - //------------------------------------------------------------- - // End of component global_reduce_unit - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component recv_from_cpu_pkt_queue - //------------------------------------------------------------- - - logic [0:0] recv_from_cpu_pkt_queue__clk; - logic [1:0] recv_from_cpu_pkt_queue__count; - logic [0:0] recv_from_cpu_pkt_queue__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt_queue__recv__msg; - logic [0:0] recv_from_cpu_pkt_queue__recv__rdy; - logic [0:0] recv_from_cpu_pkt_queue__recv__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt_queue__send__msg; - logic [0:0] recv_from_cpu_pkt_queue__send__rdy; - logic [0:0] recv_from_cpu_pkt_queue__send__val; - - NormalQueueRTL__a1c7a5a18a302c36 recv_from_cpu_pkt_queue - ( - .clk( recv_from_cpu_pkt_queue__clk ), - .count( recv_from_cpu_pkt_queue__count ), - .reset( recv_from_cpu_pkt_queue__reset ), - .recv__msg( recv_from_cpu_pkt_queue__recv__msg ), - .recv__rdy( recv_from_cpu_pkt_queue__recv__rdy ), - .recv__val( recv_from_cpu_pkt_queue__recv__val ), - .send__msg( recv_from_cpu_pkt_queue__send__msg ), - .send__rdy( recv_from_cpu_pkt_queue__send__rdy ), - .send__val( recv_from_cpu_pkt_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_from_cpu_pkt_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component recv_from_tile_load_request_pkt_queue - //------------------------------------------------------------- - - logic [0:0] recv_from_tile_load_request_pkt_queue__clk; - logic [0:0] recv_from_tile_load_request_pkt_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt_queue__recv__msg; - logic [0:0] recv_from_tile_load_request_pkt_queue__recv__rdy; - logic [0:0] recv_from_tile_load_request_pkt_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt_queue__send__msg; - logic [0:0] recv_from_tile_load_request_pkt_queue__send__rdy; - logic [0:0] recv_from_tile_load_request_pkt_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 recv_from_tile_load_request_pkt_queue - ( - .clk( recv_from_tile_load_request_pkt_queue__clk ), - .reset( recv_from_tile_load_request_pkt_queue__reset ), - .recv__msg( recv_from_tile_load_request_pkt_queue__recv__msg ), - .recv__rdy( recv_from_tile_load_request_pkt_queue__recv__rdy ), - .recv__val( recv_from_tile_load_request_pkt_queue__recv__val ), - .send__msg( recv_from_tile_load_request_pkt_queue__send__msg ), - .send__rdy( recv_from_tile_load_request_pkt_queue__send__rdy ), - .send__val( recv_from_tile_load_request_pkt_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_from_tile_load_request_pkt_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component recv_from_tile_load_response_pkt_queue - //------------------------------------------------------------- - - logic [0:0] recv_from_tile_load_response_pkt_queue__clk; - logic [0:0] recv_from_tile_load_response_pkt_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt_queue__recv__msg; - logic [0:0] recv_from_tile_load_response_pkt_queue__recv__rdy; - logic [0:0] recv_from_tile_load_response_pkt_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt_queue__send__msg; - logic [0:0] recv_from_tile_load_response_pkt_queue__send__rdy; - logic [0:0] recv_from_tile_load_response_pkt_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 recv_from_tile_load_response_pkt_queue - ( - .clk( recv_from_tile_load_response_pkt_queue__clk ), - .reset( recv_from_tile_load_response_pkt_queue__reset ), - .recv__msg( recv_from_tile_load_response_pkt_queue__recv__msg ), - .recv__rdy( recv_from_tile_load_response_pkt_queue__recv__rdy ), - .recv__val( recv_from_tile_load_response_pkt_queue__recv__val ), - .send__msg( recv_from_tile_load_response_pkt_queue__send__msg ), - .send__rdy( recv_from_tile_load_response_pkt_queue__send__rdy ), - .send__val( recv_from_tile_load_response_pkt_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_from_tile_load_response_pkt_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component recv_from_tile_store_request_pkt_queue - //------------------------------------------------------------- - - logic [0:0] recv_from_tile_store_request_pkt_queue__clk; - logic [0:0] recv_from_tile_store_request_pkt_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt_queue__recv__msg; - logic [0:0] recv_from_tile_store_request_pkt_queue__recv__rdy; - logic [0:0] recv_from_tile_store_request_pkt_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt_queue__send__msg; - logic [0:0] recv_from_tile_store_request_pkt_queue__send__rdy; - logic [0:0] recv_from_tile_store_request_pkt_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 recv_from_tile_store_request_pkt_queue - ( - .clk( recv_from_tile_store_request_pkt_queue__clk ), - .reset( recv_from_tile_store_request_pkt_queue__reset ), - .recv__msg( recv_from_tile_store_request_pkt_queue__recv__msg ), - .recv__rdy( recv_from_tile_store_request_pkt_queue__recv__rdy ), - .recv__val( recv_from_tile_store_request_pkt_queue__recv__val ), - .send__msg( recv_from_tile_store_request_pkt_queue__send__msg ), - .send__rdy( recv_from_tile_store_request_pkt_queue__send__rdy ), - .send__val( recv_from_tile_store_request_pkt_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_from_tile_store_request_pkt_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component send_to_cpu_pkt_queue - //------------------------------------------------------------- - - logic [0:0] send_to_cpu_pkt_queue__clk; - logic [1:0] send_to_cpu_pkt_queue__count; - logic [0:0] send_to_cpu_pkt_queue__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt_queue__recv__msg; - logic [0:0] send_to_cpu_pkt_queue__recv__rdy; - logic [0:0] send_to_cpu_pkt_queue__recv__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt_queue__send__msg; - logic [0:0] send_to_cpu_pkt_queue__send__rdy; - logic [0:0] send_to_cpu_pkt_queue__send__val; - - NormalQueueRTL__a1c7a5a18a302c36 send_to_cpu_pkt_queue - ( - .clk( send_to_cpu_pkt_queue__clk ), - .count( send_to_cpu_pkt_queue__count ), - .reset( send_to_cpu_pkt_queue__reset ), - .recv__msg( send_to_cpu_pkt_queue__recv__msg ), - .recv__rdy( send_to_cpu_pkt_queue__recv__rdy ), - .recv__val( send_to_cpu_pkt_queue__recv__val ), - .send__msg( send_to_cpu_pkt_queue__send__msg ), - .send__rdy( send_to_cpu_pkt_queue__send__rdy ), - .send__val( send_to_cpu_pkt_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component send_to_cpu_pkt_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component send_to_mem_load_request_queue - //------------------------------------------------------------- - - logic [0:0] send_to_mem_load_request_queue__clk; - logic [0:0] send_to_mem_load_request_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request_queue__recv__msg; - logic [0:0] send_to_mem_load_request_queue__recv__rdy; - logic [0:0] send_to_mem_load_request_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request_queue__send__msg; - logic [0:0] send_to_mem_load_request_queue__send__rdy; - logic [0:0] send_to_mem_load_request_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 send_to_mem_load_request_queue - ( - .clk( send_to_mem_load_request_queue__clk ), - .reset( send_to_mem_load_request_queue__reset ), - .recv__msg( send_to_mem_load_request_queue__recv__msg ), - .recv__rdy( send_to_mem_load_request_queue__recv__rdy ), - .recv__val( send_to_mem_load_request_queue__recv__val ), - .send__msg( send_to_mem_load_request_queue__send__msg ), - .send__rdy( send_to_mem_load_request_queue__send__rdy ), - .send__val( send_to_mem_load_request_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component send_to_mem_load_request_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component send_to_mem_store_request_queue - //------------------------------------------------------------- - - logic [0:0] send_to_mem_store_request_queue__clk; - logic [0:0] send_to_mem_store_request_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request_queue__recv__msg; - logic [0:0] send_to_mem_store_request_queue__recv__rdy; - logic [0:0] send_to_mem_store_request_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request_queue__send__msg; - logic [0:0] send_to_mem_store_request_queue__send__rdy; - logic [0:0] send_to_mem_store_request_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 send_to_mem_store_request_queue - ( - .clk( send_to_mem_store_request_queue__clk ), - .reset( send_to_mem_store_request_queue__reset ), - .recv__msg( send_to_mem_store_request_queue__recv__msg ), - .recv__rdy( send_to_mem_store_request_queue__recv__rdy ), - .recv__val( send_to_mem_store_request_queue__recv__val ), - .send__msg( send_to_mem_store_request_queue__send__msg ), - .send__rdy( send_to_mem_store_request_queue__send__rdy ), - .send__val( send_to_mem_store_request_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component send_to_mem_store_request_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component send_to_tile_load_response_queue - //------------------------------------------------------------- - - logic [0:0] send_to_tile_load_response_queue__clk; - logic [0:0] send_to_tile_load_response_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response_queue__recv__msg; - logic [0:0] send_to_tile_load_response_queue__recv__rdy; - logic [0:0] send_to_tile_load_response_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response_queue__send__msg; - logic [0:0] send_to_tile_load_response_queue__send__rdy; - logic [0:0] send_to_tile_load_response_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 send_to_tile_load_response_queue - ( - .clk( send_to_tile_load_response_queue__clk ), - .reset( send_to_tile_load_response_queue__reset ), - .recv__msg( send_to_tile_load_response_queue__recv__msg ), - .recv__rdy( send_to_tile_load_response_queue__recv__rdy ), - .recv__val( send_to_tile_load_response_queue__recv__val ), - .send__msg( send_to_tile_load_response_queue__send__msg ), - .send__rdy( send_to_tile_load_response_queue__send__rdy ), - .send__val( send_to_tile_load_response_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component send_to_tile_load_response_queue - //------------------------------------------------------------- - logic [0:0] __tmpvar__update_received_msg_kLoadRequestInportIdx; - logic [0:0] __tmpvar__update_received_msg_kLoadResponseInportIdx; - logic [1:0] __tmpvar__update_received_msg_kStoreRequestInportIdx; - logic [1:0] __tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx; - logic [2:0] __tmpvar__update_received_msg_kFromInterTileRingIdx; - logic [2:0] __tmpvar__update_received_msg_kFromReduceUnitIdx; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d __tmpvar__update_received_msg_received_pkt; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:362 - // @update - // def capture_addr_dst_id(): - // s.addr_dst_id @= s.addr2controller_lut[trunc(s.crossbar.send[0].msg.inter_cgra_pkt.payload.data_addr >> addr_offset_nbits, CgraIdType)] - - always_comb begin : capture_addr_dst_id - addr_dst_id = addr2controller_lut[2'(crossbar__send__msg[1'd0].inter_cgra_pkt.payload.data_addr >> 3'( __const__addr_offset_nbits_at_capture_addr_dst_id ))]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:141 - // @update - // def update_received_msg(): - // kLoadRequestInportIdx = 0 - // kLoadResponseInportIdx = 1 - // kStoreRequestInportIdx = 2 - // kFromCpuCtrlAndDataIdx = 3 - // kFromInterTileRingIdx = 4 - // kFromReduceUnitIdx = 5 - // - // s.send_to_cpu_pkt_queue.recv.val @= 0 - // s.send_to_cpu_pkt_queue.recv.msg @= IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.recv_from_ctrl_ring_pkt.rdy @= 0 - // - // for i in range(CONTROLLER_CROSSBAR_INPORTS): - // s.crossbar.recv[i].val @= 0 - // s.crossbar.recv[i].msg @= ControllerXbarPktType(0, 0) - // - // # For the command signal from inter-tile/intra-cgra control ring. - // s.crossbar.recv[kFromInterTileRingIdx].val @= s.recv_from_ctrl_ring_pkt.val - // s.recv_from_ctrl_ring_pkt.rdy @= s.crossbar.recv[kFromInterTileRingIdx].rdy - // s.crossbar.recv[kFromInterTileRingIdx].msg @= \ - // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) - // InterCgraPktType(s.cgra_id, - // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_id, - // s.idTo2d_x_lut[s.cgra_id], # src_x - // s.idTo2d_y_lut[s.cgra_id], # src_y - // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_x, # dst_x - // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_y, # dst_y - // s.recv_from_ctrl_ring_pkt.msg.src, # src_tile_id - // s.recv_from_ctrl_ring_pkt.msg.dst, # dst_tile_id - // 0, # remote_src_port, only used for inter-cgra remote load request/response. - // 0, # opaque - // 0, # vc_id. No need to specify vc_id for self produce-consume pkt thanks to the additional VC buffer. - // s.recv_from_ctrl_ring_pkt.msg.payload)) - // - // # For the load request from local tiles. - // s.crossbar.recv[kLoadRequestInportIdx].val @= s.recv_from_tile_load_request_pkt_queue.send.val - // s.recv_from_tile_load_request_pkt_queue.send.rdy @= s.crossbar.recv[kLoadRequestInportIdx].rdy - // s.crossbar.recv[kLoadRequestInportIdx].msg @= \ - // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) - // s.recv_from_tile_load_request_pkt_queue.send.msg) - // - // # For the store request from local tiles. - // s.crossbar.recv[kStoreRequestInportIdx].val @= s.recv_from_tile_store_request_pkt_queue.send.val - // s.recv_from_tile_store_request_pkt_queue.send.rdy @= s.crossbar.recv[kStoreRequestInportIdx].rdy - // s.crossbar.recv[kStoreRequestInportIdx].msg @= \ - // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) - // s.recv_from_tile_store_request_pkt_queue.send.msg) - // - // # For the load response (i.e., the data towards other) from local memory. - // s.crossbar.recv[kLoadResponseInportIdx].val @= \ - // s.recv_from_tile_load_response_pkt_queue.send.val - // s.recv_from_tile_load_response_pkt_queue.send.rdy @= s.crossbar.recv[kLoadResponseInportIdx].rdy - // s.crossbar.recv[kLoadResponseInportIdx].msg @= \ - // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) - // s.recv_from_tile_load_response_pkt_queue.send.msg) - // - // # For the load response (i.e., the data towards other) from local memory. - // s.crossbar.recv[kFromReduceUnitIdx].val @= \ - // s.global_reduce_unit.send.val - // s.global_reduce_unit.send.rdy @= s.crossbar.recv[kFromReduceUnitIdx].rdy - // s.crossbar.recv[kFromReduceUnitIdx].msg @= s.global_reduce_unit.send.msg - // - // # For the ctrl and data preloading. - // s.crossbar.recv[kFromCpuCtrlAndDataIdx].val @= \ - // s.recv_from_cpu_pkt_queue.send.val - // s.recv_from_cpu_pkt_queue.send.rdy @= s.crossbar.recv[kFromCpuCtrlAndDataIdx].rdy - // s.crossbar.recv[kFromCpuCtrlAndDataIdx].msg @= \ - // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) - // InterCgraPktType(s.cgra_id, # src - // s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id, # dst - // 0, # src_x - // 0, # src_y - // s.idTo2d_x_lut[s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id], # dst_x - // s.idTo2d_y_lut[s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id], # dst_y - // num_tiles, # src_tile_id, num_tiles is used to indicate the request is from CPU, so the LOAD response can come back. - // s.recv_from_cpu_pkt_queue.send.msg.dst, # dst_tile_id - // 0, # remote_src_port, only used for inter-cgra remote load request/response. - // 0, # opaque - // 0, # vc_id - // s.recv_from_cpu_pkt_queue.send.msg.payload)) - // - // # TODO: For the other cmd types. - // - // - // # @update - // # def update_received_msg_from_noc(): - // - // # Initiates the signals. - // s.send_to_mem_load_request_queue.recv.val @= 0 - // s.send_to_mem_store_request_queue.recv.val @= 0 - // s.send_to_tile_load_response_queue.recv.val @= 0 - // - // s.send_to_mem_load_request_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.send_to_mem_store_request_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.send_to_tile_load_response_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // - // s.recv_from_inter_cgra_noc.rdy @= 0 - // s.send_to_ctrl_ring_pkt.val @= 0 - // s.send_to_ctrl_ring_pkt.msg @= IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.global_reduce_unit.recv_count.val @= 0 - // s.global_reduce_unit.recv_count.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.global_reduce_unit.recv_data.val @= 0 - // s.global_reduce_unit.recv_data.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // - // # For the load request from NoC. - // received_pkt = s.recv_from_inter_cgra_noc.msg - // if s.recv_from_inter_cgra_noc.val: - // if s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LOAD_REQUEST: - // s.send_to_mem_load_request_queue.recv.val @= 1 - // - // if s.send_to_mem_load_request_queue.recv.rdy: - // s.recv_from_inter_cgra_noc.rdy @= 1 - // s.send_to_mem_load_request_queue.recv.msg @= received_pkt - // - // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_STORE_REQUEST: - // s.send_to_mem_store_request_queue.recv.msg @= received_pkt - // s.send_to_mem_store_request_queue.recv.val @= 1 - // - // if s.send_to_mem_store_request_queue.recv.rdy: - // s.recv_from_inter_cgra_noc.rdy @= 1 - // - // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LOAD_RESPONSE: - // # FIXME: This condition needs to check whether this controller is the - // # one connecting to CPU, and with the help from additional field indicating - // # whether the packet is originally from CPU. - // # https://github.com/tancheng/VectorCGRA/issues/116. - // if s.recv_from_inter_cgra_noc.msg.dst_tile_id == num_tiles: - // s.recv_from_inter_cgra_noc.rdy @= s.send_to_cpu_pkt_queue.recv.rdy - // s.send_to_cpu_pkt_queue.recv.val @= 1 - // s.send_to_cpu_pkt_queue.recv.msg @= \ - // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src - // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst - // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x - // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y - // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x - // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y - // 0, # opaque - // 0, # vc_id - // s.recv_from_inter_cgra_noc.msg.payload) - // - // else: - // s.recv_from_inter_cgra_noc.rdy @= s.send_to_tile_load_response_queue.recv.rdy - // s.send_to_tile_load_response_queue.recv.msg @= received_pkt - // s.send_to_tile_load_response_queue.recv.val @= 1 - // - // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_COMPLETE: - // s.recv_from_inter_cgra_noc.rdy @= s.send_to_cpu_pkt_queue.recv.rdy - // s.send_to_cpu_pkt_queue.recv.val @= 1 - // s.send_to_cpu_pkt_queue.recv.msg @= \ - // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src - // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst - // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x - // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y - // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x - // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y - // 0, # opaque - // 0, # vc_id - // s.recv_from_inter_cgra_noc.msg.payload) - // - // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: - // s.recv_from_inter_cgra_noc.rdy @= s.global_reduce_unit.recv_data.rdy - // s.global_reduce_unit.recv_data.val @= 1 - // s.global_reduce_unit.recv_data.msg @= s.recv_from_inter_cgra_noc.msg - // - // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_COUNT: - // s.recv_from_inter_cgra_noc.rdy @= s.global_reduce_unit.recv_count.rdy - // s.global_reduce_unit.recv_count.val @= 1 - // s.global_reduce_unit.recv_count.msg @= s.recv_from_inter_cgra_noc.msg - // - // elif (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONST) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_PAUSE) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_PRESERVE) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_RESUME) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_RECORD_PHI_ADDR) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_TERMINATE) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LAUNCH): - // s.recv_from_inter_cgra_noc.rdy @= s.send_to_ctrl_ring_pkt.rdy - // s.send_to_ctrl_ring_pkt.val @= s.recv_from_inter_cgra_noc.val - // s.send_to_ctrl_ring_pkt.msg @= \ - // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src - // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst - // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x - // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y - // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x - // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y - // 0, # opaque - // 0, # vc_id - // s.recv_from_inter_cgra_noc.msg.payload) - // - // # else: - // # # TODO: Handle other cmd types. - // # assert(False) - - always_comb begin : update_received_msg - __tmpvar__update_received_msg_kLoadRequestInportIdx = 1'd0; - __tmpvar__update_received_msg_kLoadResponseInportIdx = 1'd1; - __tmpvar__update_received_msg_kStoreRequestInportIdx = 2'd2; - __tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx = 2'd3; - __tmpvar__update_received_msg_kFromInterTileRingIdx = 3'd4; - __tmpvar__update_received_msg_kFromReduceUnitIdx = 3'd5; - send_to_cpu_pkt_queue__recv__val = 1'd0; - send_to_cpu_pkt_queue__recv__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; - recv_from_ctrl_ring_pkt__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__CONTROLLER_CROSSBAR_INPORTS ); i += 1'd1 ) begin - crossbar__recv__val[3'(i)] = 1'd0; - crossbar__recv__msg[3'(i)] = { 1'd0, 221'd0 }; - end - crossbar__recv__val[__tmpvar__update_received_msg_kFromInterTileRingIdx] = recv_from_ctrl_ring_pkt__val; - recv_from_ctrl_ring_pkt__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromInterTileRingIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kFromInterTileRingIdx] = { 1'd0, { cgra_id, recv_from_ctrl_ring_pkt__msg.dst_cgra_id, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], recv_from_ctrl_ring_pkt__msg.dst_cgra_x, recv_from_ctrl_ring_pkt__msg.dst_cgra_y, recv_from_ctrl_ring_pkt__msg.src, recv_from_ctrl_ring_pkt__msg.dst, 3'd0, 8'd0, 2'd0, recv_from_ctrl_ring_pkt__msg.payload } }; - crossbar__recv__val[__tmpvar__update_received_msg_kLoadRequestInportIdx] = recv_from_tile_load_request_pkt_queue__send__val; - recv_from_tile_load_request_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kLoadRequestInportIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kLoadRequestInportIdx] = { 1'd0, recv_from_tile_load_request_pkt_queue__send__msg }; - crossbar__recv__val[__tmpvar__update_received_msg_kStoreRequestInportIdx] = recv_from_tile_store_request_pkt_queue__send__val; - recv_from_tile_store_request_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kStoreRequestInportIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kStoreRequestInportIdx] = { 1'd0, recv_from_tile_store_request_pkt_queue__send__msg }; - crossbar__recv__val[__tmpvar__update_received_msg_kLoadResponseInportIdx] = recv_from_tile_load_response_pkt_queue__send__val; - recv_from_tile_load_response_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kLoadResponseInportIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kLoadResponseInportIdx] = { 1'd0, recv_from_tile_load_response_pkt_queue__send__msg }; - crossbar__recv__val[__tmpvar__update_received_msg_kFromReduceUnitIdx] = global_reduce_unit__send__val; - global_reduce_unit__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromReduceUnitIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kFromReduceUnitIdx] = global_reduce_unit__send__msg; - crossbar__recv__val[__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx] = recv_from_cpu_pkt_queue__send__val; - recv_from_cpu_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx] = { 1'd0, { cgra_id, recv_from_cpu_pkt_queue__send__msg.dst_cgra_id, 1'd0, 1'd0, idTo2d_x_lut[recv_from_cpu_pkt_queue__send__msg.dst_cgra_id], idTo2d_y_lut[recv_from_cpu_pkt_queue__send__msg.dst_cgra_id], 5'( __const__num_tiles_at_update_received_msg ), recv_from_cpu_pkt_queue__send__msg.dst, 3'd0, 8'd0, 2'd0, recv_from_cpu_pkt_queue__send__msg.payload } }; - send_to_mem_load_request_queue__recv__val = 1'd0; - send_to_mem_store_request_queue__recv__val = 1'd0; - send_to_tile_load_response_queue__recv__val = 1'd0; - send_to_mem_load_request_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - send_to_mem_store_request_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - send_to_tile_load_response_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - recv_from_inter_cgra_noc__rdy = 1'd0; - send_to_ctrl_ring_pkt__val = 1'd0; - send_to_ctrl_ring_pkt__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; - global_reduce_unit__recv_count__val = 1'd0; - global_reduce_unit__recv_count__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - global_reduce_unit__recv_data__val = 1'd0; - global_reduce_unit__recv_data__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - __tmpvar__update_received_msg_received_pkt = recv_from_inter_cgra_noc__msg; - if ( recv_from_inter_cgra_noc__val ) begin - if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LOAD_REQUEST ) ) begin - send_to_mem_load_request_queue__recv__val = 1'd1; - if ( send_to_mem_load_request_queue__recv__rdy ) begin - recv_from_inter_cgra_noc__rdy = 1'd1; - send_to_mem_load_request_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; - end - end - else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_STORE_REQUEST ) ) begin - send_to_mem_store_request_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; - send_to_mem_store_request_queue__recv__val = 1'd1; - if ( send_to_mem_store_request_queue__recv__rdy ) begin - recv_from_inter_cgra_noc__rdy = 1'd1; - end - end - else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LOAD_RESPONSE ) ) begin - if ( recv_from_inter_cgra_noc__msg.dst_tile_id == 5'( __const__num_tiles_at_update_received_msg ) ) begin - recv_from_inter_cgra_noc__rdy = send_to_cpu_pkt_queue__recv__rdy; - send_to_cpu_pkt_queue__recv__val = 1'd1; - send_to_cpu_pkt_queue__recv__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; - end - else begin - recv_from_inter_cgra_noc__rdy = send_to_tile_load_response_queue__recv__rdy; - send_to_tile_load_response_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; - send_to_tile_load_response_queue__recv__val = 1'd1; - end - end - else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_COMPLETE ) ) begin - recv_from_inter_cgra_noc__rdy = send_to_cpu_pkt_queue__recv__rdy; - send_to_cpu_pkt_queue__recv__val = 1'd1; - send_to_cpu_pkt_queue__recv__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; - end - else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin - recv_from_inter_cgra_noc__rdy = global_reduce_unit__recv_data__rdy; - global_reduce_unit__recv_data__val = 1'd1; - global_reduce_unit__recv_data__msg = recv_from_inter_cgra_noc__msg; - end - else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_COUNT ) ) begin - recv_from_inter_cgra_noc__rdy = global_reduce_unit__recv_count__rdy; - global_reduce_unit__recv_count__val = 1'd1; - global_reduce_unit__recv_count__msg = recv_from_inter_cgra_noc__msg; - end - else if ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONST ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_PAUSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_PRESERVE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_RECORD_PHI_ADDR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) begin - recv_from_inter_cgra_noc__rdy = send_to_ctrl_ring_pkt__rdy; - send_to_ctrl_ring_pkt__val = recv_from_inter_cgra_noc__val; - send_to_ctrl_ring_pkt__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:350 - // @update - // def update_sending_to_noc_msg(): - // s.send_to_inter_cgra_noc.val @= s.crossbar.send[0].val - // s.crossbar.send[0].rdy @= s.send_to_inter_cgra_noc.rdy - // s.send_to_inter_cgra_noc.msg @= s.crossbar.send[0].msg.inter_cgra_pkt - // # addr_dst_id = 0 - // if (s.crossbar.send[0].msg.inter_cgra_pkt.payload.cmd == CMD_LOAD_REQUEST) | \ - // (s.crossbar.send[0].msg.inter_cgra_pkt.payload.cmd == CMD_STORE_REQUEST): - // s.send_to_inter_cgra_noc.msg.dst @= s.addr_dst_id - // s.send_to_inter_cgra_noc.msg.dst_x @= s.idTo2d_x_lut[s.addr_dst_id] - // s.send_to_inter_cgra_noc.msg.dst_y @= s.idTo2d_y_lut[s.addr_dst_id] - - always_comb begin : update_sending_to_noc_msg - send_to_inter_cgra_noc__val = crossbar__send__val[1'd0]; - crossbar__send__rdy[1'd0] = send_to_inter_cgra_noc__rdy; - send_to_inter_cgra_noc__msg = crossbar__send__msg[1'd0].inter_cgra_pkt; - if ( ( crossbar__send__msg[1'd0].inter_cgra_pkt.payload.cmd == 5'( __const__CMD_LOAD_REQUEST ) ) | ( crossbar__send__msg[1'd0].inter_cgra_pkt.payload.cmd == 5'( __const__CMD_STORE_REQUEST ) ) ) begin - send_to_inter_cgra_noc__msg.dst = addr_dst_id; - send_to_inter_cgra_noc__msg.dst_x = idTo2d_x_lut[addr_dst_id]; - send_to_inter_cgra_noc__msg.dst_y = idTo2d_y_lut[addr_dst_id]; - end - end - - assign recv_from_tile_load_request_pkt_queue__clk = clk; - assign recv_from_tile_load_request_pkt_queue__reset = reset; - assign recv_from_tile_load_response_pkt_queue__clk = clk; - assign recv_from_tile_load_response_pkt_queue__reset = reset; - assign recv_from_tile_store_request_pkt_queue__clk = clk; - assign recv_from_tile_store_request_pkt_queue__reset = reset; - assign send_to_mem_load_request_queue__clk = clk; - assign send_to_mem_load_request_queue__reset = reset; - assign send_to_tile_load_response_queue__clk = clk; - assign send_to_tile_load_response_queue__reset = reset; - assign send_to_mem_store_request_queue__clk = clk; - assign send_to_mem_store_request_queue__reset = reset; - assign crossbar__clk = clk; - assign crossbar__reset = reset; - assign recv_from_cpu_pkt_queue__clk = clk; - assign recv_from_cpu_pkt_queue__reset = reset; - assign send_to_cpu_pkt_queue__clk = clk; - assign send_to_cpu_pkt_queue__reset = reset; - assign global_reduce_unit__clk = clk; - assign global_reduce_unit__reset = reset; - assign addr2controller_lut[0] = 2'd0; - assign addr2controller_lut[1] = 2'd1; - assign addr2controller_lut[2] = 2'd2; - assign addr2controller_lut[3] = 2'd3; - assign idTo2d_x_lut[0] = 1'd0; - assign idTo2d_y_lut[0] = 1'd0; - assign idTo2d_x_lut[1] = 1'd1; - assign idTo2d_y_lut[1] = 1'd0; - assign idTo2d_x_lut[2] = 1'd0; - assign idTo2d_y_lut[2] = 1'd1; - assign idTo2d_x_lut[3] = 1'd1; - assign idTo2d_y_lut[3] = 1'd1; - assign recv_from_tile_load_request_pkt_queue__recv__msg = recv_from_tile_load_request_pkt__msg; - assign recv_from_tile_load_request_pkt__rdy = recv_from_tile_load_request_pkt_queue__recv__rdy; - assign recv_from_tile_load_request_pkt_queue__recv__val = recv_from_tile_load_request_pkt__val; - assign recv_from_tile_load_response_pkt_queue__recv__msg = recv_from_tile_load_response_pkt__msg; - assign recv_from_tile_load_response_pkt__rdy = recv_from_tile_load_response_pkt_queue__recv__rdy; - assign recv_from_tile_load_response_pkt_queue__recv__val = recv_from_tile_load_response_pkt__val; - assign recv_from_tile_store_request_pkt_queue__recv__msg = recv_from_tile_store_request_pkt__msg; - assign recv_from_tile_store_request_pkt__rdy = recv_from_tile_store_request_pkt_queue__recv__rdy; - assign recv_from_tile_store_request_pkt_queue__recv__val = recv_from_tile_store_request_pkt__val; - assign send_to_mem_load_request__msg = send_to_mem_load_request_queue__send__msg; - assign send_to_mem_load_request_queue__send__rdy = send_to_mem_load_request__rdy; - assign send_to_mem_load_request__val = send_to_mem_load_request_queue__send__val; - assign send_to_tile_load_response__msg = send_to_tile_load_response_queue__send__msg; - assign send_to_tile_load_response_queue__send__rdy = send_to_tile_load_response__rdy; - assign send_to_tile_load_response__val = send_to_tile_load_response_queue__send__val; - assign send_to_mem_store_request__msg = send_to_mem_store_request_queue__send__msg; - assign send_to_mem_store_request_queue__send__rdy = send_to_mem_store_request__rdy; - assign send_to_mem_store_request__val = send_to_mem_store_request_queue__send__val; - assign recv_from_cpu_pkt_queue__recv__msg = recv_from_cpu_pkt__msg; - assign recv_from_cpu_pkt__rdy = recv_from_cpu_pkt_queue__recv__rdy; - assign recv_from_cpu_pkt_queue__recv__val = recv_from_cpu_pkt__val; - assign send_to_cpu_pkt__msg = send_to_cpu_pkt_queue__send__msg; - assign send_to_cpu_pkt_queue__send__rdy = send_to_cpu_pkt__rdy; - assign send_to_cpu_pkt__val = send_to_cpu_pkt_queue__send__val; - -endmodule - - -// PyMTL Component Counter Definition -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/rtl/Counter.py - -module Counter__Type_Bits2__reset_value_2 -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] decr , - input logic [0:0] incr , - input logic [0:0] load , - input logic [1:0] load_value , - input logic [0:0] reset -); - localparam logic [1:0] __const__reset_value_at_up_count = 2'd2; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/rtl/Counter.py:28 - // @update_ff - // def up_count(): - // - // if s.reset: - // s.count <<= reset_value - // - // elif s.load: - // s.count <<= s.load_value - // - // elif s.incr & ~s.decr: - // s.count <<= s.count + 1 - // - // elif ~s.incr & s.decr: - // s.count <<= s.count - 1 - - always_ff @(posedge clk) begin : up_count - if ( reset ) begin - count <= 2'( __const__reset_value_at_up_count ); - end - else if ( load ) begin - count <= load_value; - end - else if ( incr & ( ~decr ) ) begin - count <= count + 2'd1; - end - else if ( ( ~incr ) & decr ) begin - count <= count - 2'd1; - end - end - -endmodule - - -// PyMTL Component RecvRTL2CreditSendRTL Definition -// Full name: RecvRTL2CreditSendRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py - -module RecvRTL2CreditSendRTL__6d49e584a986d10c -( - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output logic [0:0] send__en , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__yum [0:1] -); - localparam logic [1:0] __const__vc_at_up_credit_send = 2'd2; - localparam logic [1:0] __const__vc_at_up_counter_decr = 2'd2; - //------------------------------------------------------------- - // Component credit[0:1] - //------------------------------------------------------------- - - logic [0:0] credit__clk [0:1]; - logic [1:0] credit__count [0:1]; - logic [0:0] credit__decr [0:1]; - logic [0:0] credit__incr [0:1]; - logic [0:0] credit__load [0:1]; - logic [1:0] credit__load_value [0:1]; - logic [0:0] credit__reset [0:1]; - - Counter__Type_Bits2__reset_value_2 credit__0 - ( - .clk( credit__clk[0] ), - .count( credit__count[0] ), - .decr( credit__decr[0] ), - .incr( credit__incr[0] ), - .load( credit__load[0] ), - .load_value( credit__load_value[0] ), - .reset( credit__reset[0] ) - ); - - Counter__Type_Bits2__reset_value_2 credit__1 - ( - .clk( credit__clk[1] ), - .count( credit__count[1] ), - .decr( credit__decr[1] ), - .incr( credit__incr[1] ), - .load( credit__load[1] ), - .load_value( credit__load_value[1] ), - .reset( credit__reset[1] ) - ); - - //------------------------------------------------------------- - // End of component credit[0:1] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:149 - // @update - // def up_counter_decr(): - // for i in range( vc ): - // s.credit[i].decr @= s.send.en & ( i == s.send.msg.vc_id ) - - always_comb begin : up_counter_decr - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_counter_decr ); i += 1'd1 ) - credit__decr[1'(i)] = send__en & ( 1'(i) == send__msg.vc_id ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:137 - // @update - // def up_credit_send(): - // s.send.en @= 0 - // s.recv.rdy @= 0 - // # NOTE: recv.rdy depends on recv.val. - // # Be careful about combinationl loop. - // if s.recv.val: - // for i in range( vc ): - // if ( i == s.recv.msg.vc_id ) & ( s.credit[i].count > 0 ): - // s.send.en @= 1 - // s.recv.rdy @= 1 - - always_comb begin : up_credit_send - send__en = 1'd0; - recv__rdy = 1'd0; - if ( recv__val ) begin - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_credit_send ); i += 1'd1 ) - if ( ( 1'(i) == recv__msg.vc_id ) & ( credit__count[1'(i)] > 2'd0 ) ) begin - send__en = 1'd1; - recv__rdy = 1'd1; - end - end - end - - assign credit__clk[0] = clk; - assign credit__reset[0] = reset; - assign credit__clk[1] = clk; - assign credit__reset[1] = reset; - assign send__msg = recv__msg; - assign credit__incr[0] = send__yum[0]; - assign credit__load[0] = 1'd0; - assign credit__load_value[0] = 2'd0; - assign credit__incr[1] = send__yum[1]; - assign credit__load[1] = 1'd0; - assign credit__load_value[1] = 2'd0; - -endmodule - - -// PyMTL Component InputUnitCreditRTL Definition -// Full name: InputUnitCreditRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__QueueType_NormalQueueRTL__vc_2__credit_line_2 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py - -module InputUnitCreditRTL__797fe657f4e9d44e -( - input logic [0:0] clk , - input logic [0:0] reset , - input logic [0:0] recv__en , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__yum [0:1] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:1] , - input logic [0:0] send__rdy [0:1] , - output logic [0:0] send__val [0:1] -); - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ = 1'd0; - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ = 1'd1; - localparam logic [1:0] __const__vc_at_up_enq = 2'd2; - //------------------------------------------------------------- - // Component buffers[0:1] - //------------------------------------------------------------- - - logic [0:0] buffers__clk [0:1]; - logic [1:0] buffers__count [0:1]; - logic [0:0] buffers__reset [0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__recv__msg [0:1]; - logic [0:0] buffers__recv__rdy [0:1]; - logic [0:0] buffers__recv__val [0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__send__msg [0:1]; - logic [0:0] buffers__send__rdy [0:1]; - logic [0:0] buffers__send__val [0:1]; - - NormalQueueRTL__a1c7a5a18a302c36 buffers__0 - ( - .clk( buffers__clk[0] ), - .count( buffers__count[0] ), - .reset( buffers__reset[0] ), - .recv__msg( buffers__recv__msg[0] ), - .recv__rdy( buffers__recv__rdy[0] ), - .recv__val( buffers__recv__val[0] ), - .send__msg( buffers__send__msg[0] ), - .send__rdy( buffers__send__rdy[0] ), - .send__val( buffers__send__val[0] ) - ); - - NormalQueueRTL__a1c7a5a18a302c36 buffers__1 - ( - .clk( buffers__clk[1] ), - .count( buffers__count[1] ), - .reset( buffers__reset[1] ), - .recv__msg( buffers__recv__msg[1] ), - .recv__rdy( buffers__recv__rdy[1] ), - .recv__val( buffers__recv__val[1] ), - .send__msg( buffers__send__msg[1] ), - .send__rdy( buffers__send__rdy[1] ), - .send__val( buffers__send__val[1] ) - ); - - //------------------------------------------------------------- - // End of component buffers[0:1] - //------------------------------------------------------------- - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:39 - // s.recv.yum[i] //= lambda: s.send[i].val & s.send[i].rdy - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ - recv__yum[1'd0] = send__val[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ )] & send__rdy[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ )]; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:39 - // s.recv.yum[i] //= lambda: s.send[i].val & s.send[i].rdy - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ - recv__yum[1'd1] = send__val[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ )] & send__rdy[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ )]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:41 - // @update - // def up_enq(): - // if s.recv.en: - // for i in range( vc ): - // s.buffers[i].recv.val @= ( s.recv.msg.vc_id == i ) - // else: - // for i in range( vc ): - // s.buffers[i].recv.val @= 0 - - always_comb begin : up_enq - if ( recv__en ) begin - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) - buffers__recv__val[1'(i)] = recv__msg.vc_id == 1'(i); - end - else - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) - buffers__recv__val[1'(i)] = 1'd0; - end - - assign buffers__clk[0] = clk; - assign buffers__reset[0] = reset; - assign buffers__clk[1] = clk; - assign buffers__reset[1] = reset; - assign buffers__recv__msg[0] = recv__msg; - assign send__msg[0] = buffers__send__msg[0]; - assign buffers__send__rdy[0] = send__rdy[0]; - assign send__val[0] = buffers__send__val[0]; - assign buffers__recv__msg[1] = recv__msg; - assign send__msg[1] = buffers__send__msg[1]; - assign buffers__send__rdy[1] = send__rdy[1]; - assign send__val[1] = buffers__send__val[1]; - -endmodule - - -// PyMTL Component OutputUnitCreditRTL Definition -// Full name: OutputUnitCreditRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py - -module OutputUnitCreditRTL__6d49e584a986d10c -( - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output logic [0:0] send__en , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__yum [0:1] -); - localparam logic [1:0] __const__vc_at_up_credit_send = 2'd2; - localparam logic [1:0] __const__vc_at_up_counter_decr = 2'd2; - //------------------------------------------------------------- - // Component credit[0:1] - //------------------------------------------------------------- - - logic [0:0] credit__clk [0:1]; - logic [1:0] credit__count [0:1]; - logic [0:0] credit__decr [0:1]; - logic [0:0] credit__incr [0:1]; - logic [0:0] credit__load [0:1]; - logic [1:0] credit__load_value [0:1]; - logic [0:0] credit__reset [0:1]; - - Counter__Type_Bits2__reset_value_2 credit__0 - ( - .clk( credit__clk[0] ), - .count( credit__count[0] ), - .decr( credit__decr[0] ), - .incr( credit__incr[0] ), - .load( credit__load[0] ), - .load_value( credit__load_value[0] ), - .reset( credit__reset[0] ) - ); - - Counter__Type_Bits2__reset_value_2 credit__1 - ( - .clk( credit__clk[1] ), - .count( credit__count[1] ), - .decr( credit__decr[1] ), - .incr( credit__incr[1] ), - .load( credit__load[1] ), - .load_value( credit__load_value[1] ), - .reset( credit__reset[1] ) - ); - - //------------------------------------------------------------- - // End of component credit[0:1] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py:47 - // @update - // def up_counter_decr(): - // for i in range( vc ): - // s.credit[i].decr @= s.send.en & ( i == s.send.msg.vc_id ) - - always_comb begin : up_counter_decr - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_counter_decr ); i += 1'd1 ) - credit__decr[1'(i)] = send__en & ( 1'(i) == send__msg.vc_id ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py:35 - // @update - // def up_credit_send(): - // s.send.en @= 0 - // s.recv.rdy @= 0 - // # NOTE: Here the recv.rdy depends on recv.val. - // # Be careful about combinational loop. - // if s.recv.val: - // for i in range( vc ): - // if (i == s.recv.msg.vc_id) & (s.credit[i].count > 0): - // s.send.en @= 1 - // s.recv.rdy @= 1 - - always_comb begin : up_credit_send - send__en = 1'd0; - recv__rdy = 1'd0; - if ( recv__val ) begin - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_credit_send ); i += 1'd1 ) - if ( ( 1'(i) == recv__msg.vc_id ) & ( credit__count[1'(i)] > 2'd0 ) ) begin - send__en = 1'd1; - recv__rdy = 1'd1; - end - end - end - - assign credit__clk[0] = clk; - assign credit__reset[0] = reset; - assign credit__clk[1] = clk; - assign credit__reset[1] = reset; - assign send__msg = recv__msg; - assign credit__incr[0] = send__yum[0]; - assign credit__load[0] = 1'd0; - assign credit__load_value[0] = 2'd0; - assign credit__incr[1] = send__yum[1]; - assign credit__load[1] = 1'd0; - assign credit__load_value[1] = 2'd0; - -endmodule - - -// PyMTL Component RingRouteUnitRTL Definition -// Full name: RingRouteUnitRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py - -module RingRouteUnitRTL__6d1cae73cf31e9a0 -( - input logic [0:0] clk , - input logic [4:0] pos , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:2] , - input logic [0:0] send__rdy [0:2] , - output logic [0:0] send__val [0:2] -); - localparam logic [1:0] __const__SELF = 2'd2; - localparam logic [0:0] __const__LEFT = 1'd0; - localparam logic [0:0] __const__RIGHT = 1'd1; - logic [4:0] left_dist; - logic [1:0] out_dir; - logic [4:0] right_dist; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg_wire; - logic [2:0] send_rdy; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:51 - // @update - // def up_left_right_dist(): - // if s.recv.msg.dst < s.pos: - // s.left_dist @= zext(s.pos, DistType) - zext(s.recv.msg.dst, DistType) - // s.right_dist @= zext(s.last_idx, DistType) - zext(s.pos, DistType) + zext(s.recv.msg.dst, DistType) + 1 - // else: - // s.left_dist @= 1 + zext(s.last_idx, DistType) + zext(s.pos, DistType) - zext(s.recv.msg.dst, DistType) - // s.right_dist @= zext(s.recv.msg.dst, DistType) - zext(s.pos, DistType) - - always_comb begin : up_left_right_dist - if ( recv__msg.dst < pos ) begin - left_dist = pos - recv__msg.dst; - right_dist = ( ( 5'd16 - pos ) + recv__msg.dst ) + 5'd1; - end - else begin - left_dist = ( ( 5'd1 + 5'd16 ) + pos ) - recv__msg.dst; - right_dist = recv__msg.dst - pos; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:85 - // @update - // def up_ru_recv_rdy(): - // s.recv.rdy @= s.send_rdy[ s.out_dir ] - - always_comb begin : up_ru_recv_rdy - recv__rdy = send_rdy[out_dir]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:60 - // @update - // def up_ru_routing(): - // - // s.out_dir @= 0 - // s.send_msg_wire @= s.recv.msg - // for i in range( s.num_outports ): - // s.send[i].val @= 0 - // s.send[i].msg @= s.recv.msg - // - // if s.recv.val: - // if s.pos == s.recv.msg.dst: - // s.out_dir @= SELF - // elif s.left_dist < s.right_dist: - // s.out_dir @= LEFT - // else: - // s.out_dir @= RIGHT - // - // if ( s.pos == s.last_idx ) & ( s.out_dir == RIGHT ): - // s.send_msg_wire.vc_id @= 1 - // elif ( s.pos == 0 ) & ( s.out_dir == LEFT ): - // s.send_msg_wire.vc_id @= 1 - // - // s.send[ s.out_dir ].val @= 1 - // s.send[ s.out_dir ].msg @= s.send_msg_wire - - always_comb begin : up_ru_routing - out_dir = 2'd0; - send_msg_wire = recv__msg; - for ( int unsigned i = 1'd0; i < 2'd3; i += 1'd1 ) begin - send__val[2'(i)] = 1'd0; - send__msg[2'(i)] = recv__msg; - end - if ( recv__val ) begin - if ( pos == recv__msg.dst ) begin - out_dir = 2'( __const__SELF ); - end - else if ( left_dist < right_dist ) begin - out_dir = 2'( __const__LEFT ); - end - else - out_dir = 2'( __const__RIGHT ); - if ( ( pos == 5'd16 ) & ( out_dir == 2'( __const__RIGHT ) ) ) begin - send_msg_wire.vc_id = 1'd1; - end - else if ( ( pos == 5'd0 ) & ( out_dir == 2'( __const__LEFT ) ) ) begin - send_msg_wire.vc_id = 1'd1; - end - send__val[out_dir] = 1'd1; - send__msg[out_dir] = send_msg_wire; - end - end - - assign send_rdy[0:0] = send__rdy[0]; - assign send_rdy[1:1] = send__rdy[1]; - assign send_rdy[2:2] = send__rdy[2]; - -endmodule - - -// PyMTL Component Mux Definition -// Full name: Mux__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ninputs_6 -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__1cc75bdfd067f505 -( - input logic [0:0] clk , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 in_ [0:5], - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 out , - input logic [0:0] reset , - input logic [2:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component SwitchUnitRTL Definition -// Full name: SwitchUnitRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_inports_6 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py - -module SwitchUnitRTL__ae7d6e1a8f952f91 -( - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:5] , - output logic [0:0] recv__rdy [0:5] , - input logic [0:0] recv__val [0:5] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd6; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [5:0] arbiter__grants; - logic [5:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_6 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [5:0] encoder__in_; - logic [2:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_6__out_nbits_3 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__in_ [0:5]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__out; - logic [0:0] mux__reset; - logic [2:0] mux__sel; - - Mux__1cc75bdfd067f505 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 - // @update - // def up_get_en(): - // for i in range( num_inports ): - // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) - - always_comb begin : up_get_en - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) - recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 - // @update - // def up_send_val(): - // s.send.val @= s.arbiter.grants > 0 - - always_comb begin : up_send_val - send__val = arbiter__grants > 6'd0; - end - - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign arbiter__en = 1'd1; - assign mux__clk = clk; - assign mux__reset = reset; - assign send__msg = mux__out; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign encoder__in_ = arbiter__grants; - assign mux__sel = encoder__out; - assign arbiter__reqs[0:0] = recv__val[0]; - assign mux__in_[0] = recv__msg[0]; - assign arbiter__reqs[1:1] = recv__val[1]; - assign mux__in_[1] = recv__msg[1]; - assign arbiter__reqs[2:2] = recv__val[2]; - assign mux__in_[2] = recv__msg[2]; - assign arbiter__reqs[3:3] = recv__val[3]; - assign mux__in_[3] = recv__msg[3]; - assign arbiter__reqs[4:4] = recv__val[4]; - assign mux__in_[4] = recv__msg[4]; - assign arbiter__reqs[5:5] = recv__val[5]; - assign mux__in_[5] = recv__msg[5]; - -endmodule - - -// PyMTL Component RingRouterRTL Definition -// Full name: RingRouterRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17__InputUnitType_InputUnitCreditRTL__RouteUnitType_RingRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitCreditRTL__vc_2__credit_line_2 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouterRTL.py - -module RingRouterRTL__6e670e447e1766e0 -( - input logic [0:0] clk , - input logic [4:0] pos , - input logic [0:0] reset , - input logic [0:0] recv__en [0:2] , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:2] , - output logic [0:0] recv__yum [0:2][0:1] , - output logic [0:0] send__en [0:2] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:2] , - input logic [0:0] send__yum [0:2][0:1] -); - //------------------------------------------------------------- - // Component input_units[0:2] - //------------------------------------------------------------- - - logic [0:0] input_units__clk [0:2]; - logic [0:0] input_units__reset [0:2]; - logic [0:0] input_units__recv__en [0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 input_units__recv__msg [0:2]; - logic [0:0] input_units__recv__yum [0:2][0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 input_units__send__msg [0:2][0:1]; - logic [0:0] input_units__send__rdy [0:2][0:1]; - logic [0:0] input_units__send__val [0:2][0:1]; - - InputUnitCreditRTL__797fe657f4e9d44e input_units__0 - ( - .clk( input_units__clk[0] ), - .reset( input_units__reset[0] ), - .recv__en( input_units__recv__en[0] ), - .recv__msg( input_units__recv__msg[0] ), - .recv__yum( input_units__recv__yum[0] ), - .send__msg( input_units__send__msg[0] ), - .send__rdy( input_units__send__rdy[0] ), - .send__val( input_units__send__val[0] ) - ); - - InputUnitCreditRTL__797fe657f4e9d44e input_units__1 - ( - .clk( input_units__clk[1] ), - .reset( input_units__reset[1] ), - .recv__en( input_units__recv__en[1] ), - .recv__msg( input_units__recv__msg[1] ), - .recv__yum( input_units__recv__yum[1] ), - .send__msg( input_units__send__msg[1] ), - .send__rdy( input_units__send__rdy[1] ), - .send__val( input_units__send__val[1] ) - ); - - InputUnitCreditRTL__797fe657f4e9d44e input_units__2 - ( - .clk( input_units__clk[2] ), - .reset( input_units__reset[2] ), - .recv__en( input_units__recv__en[2] ), - .recv__msg( input_units__recv__msg[2] ), - .recv__yum( input_units__recv__yum[2] ), - .send__msg( input_units__send__msg[2] ), - .send__rdy( input_units__send__rdy[2] ), - .send__val( input_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component input_units[0:2] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component output_units[0:2] - //------------------------------------------------------------- - - logic [0:0] output_units__clk [0:2]; - logic [0:0] output_units__reset [0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 output_units__recv__msg [0:2]; - logic [0:0] output_units__recv__rdy [0:2]; - logic [0:0] output_units__recv__val [0:2]; - logic [0:0] output_units__send__en [0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 output_units__send__msg [0:2]; - logic [0:0] output_units__send__yum [0:2][0:1]; - - OutputUnitCreditRTL__6d49e584a986d10c output_units__0 - ( - .clk( output_units__clk[0] ), - .reset( output_units__reset[0] ), - .recv__msg( output_units__recv__msg[0] ), - .recv__rdy( output_units__recv__rdy[0] ), - .recv__val( output_units__recv__val[0] ), - .send__en( output_units__send__en[0] ), - .send__msg( output_units__send__msg[0] ), - .send__yum( output_units__send__yum[0] ) - ); - - OutputUnitCreditRTL__6d49e584a986d10c output_units__1 - ( - .clk( output_units__clk[1] ), - .reset( output_units__reset[1] ), - .recv__msg( output_units__recv__msg[1] ), - .recv__rdy( output_units__recv__rdy[1] ), - .recv__val( output_units__recv__val[1] ), - .send__en( output_units__send__en[1] ), - .send__msg( output_units__send__msg[1] ), - .send__yum( output_units__send__yum[1] ) - ); - - OutputUnitCreditRTL__6d49e584a986d10c output_units__2 - ( - .clk( output_units__clk[2] ), - .reset( output_units__reset[2] ), - .recv__msg( output_units__recv__msg[2] ), - .recv__rdy( output_units__recv__rdy[2] ), - .recv__val( output_units__recv__val[2] ), - .send__en( output_units__send__en[2] ), - .send__msg( output_units__send__msg[2] ), - .send__yum( output_units__send__yum[2] ) - ); - - //------------------------------------------------------------- - // End of component output_units[0:2] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component route_units[0:5] - //------------------------------------------------------------- - - logic [0:0] route_units__clk [0:5]; - logic [4:0] route_units__pos [0:5]; - logic [0:0] route_units__reset [0:5]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 route_units__recv__msg [0:5]; - logic [0:0] route_units__recv__rdy [0:5]; - logic [0:0] route_units__recv__val [0:5]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 route_units__send__msg [0:5][0:2]; - logic [0:0] route_units__send__rdy [0:5][0:2]; - logic [0:0] route_units__send__val [0:5][0:2]; - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__0 - ( - .clk( route_units__clk[0] ), - .pos( route_units__pos[0] ), - .reset( route_units__reset[0] ), - .recv__msg( route_units__recv__msg[0] ), - .recv__rdy( route_units__recv__rdy[0] ), - .recv__val( route_units__recv__val[0] ), - .send__msg( route_units__send__msg[0] ), - .send__rdy( route_units__send__rdy[0] ), - .send__val( route_units__send__val[0] ) - ); - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__1 - ( - .clk( route_units__clk[1] ), - .pos( route_units__pos[1] ), - .reset( route_units__reset[1] ), - .recv__msg( route_units__recv__msg[1] ), - .recv__rdy( route_units__recv__rdy[1] ), - .recv__val( route_units__recv__val[1] ), - .send__msg( route_units__send__msg[1] ), - .send__rdy( route_units__send__rdy[1] ), - .send__val( route_units__send__val[1] ) - ); - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__2 - ( - .clk( route_units__clk[2] ), - .pos( route_units__pos[2] ), - .reset( route_units__reset[2] ), - .recv__msg( route_units__recv__msg[2] ), - .recv__rdy( route_units__recv__rdy[2] ), - .recv__val( route_units__recv__val[2] ), - .send__msg( route_units__send__msg[2] ), - .send__rdy( route_units__send__rdy[2] ), - .send__val( route_units__send__val[2] ) - ); - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__3 - ( - .clk( route_units__clk[3] ), - .pos( route_units__pos[3] ), - .reset( route_units__reset[3] ), - .recv__msg( route_units__recv__msg[3] ), - .recv__rdy( route_units__recv__rdy[3] ), - .recv__val( route_units__recv__val[3] ), - .send__msg( route_units__send__msg[3] ), - .send__rdy( route_units__send__rdy[3] ), - .send__val( route_units__send__val[3] ) - ); - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__4 - ( - .clk( route_units__clk[4] ), - .pos( route_units__pos[4] ), - .reset( route_units__reset[4] ), - .recv__msg( route_units__recv__msg[4] ), - .recv__rdy( route_units__recv__rdy[4] ), - .recv__val( route_units__recv__val[4] ), - .send__msg( route_units__send__msg[4] ), - .send__rdy( route_units__send__rdy[4] ), - .send__val( route_units__send__val[4] ) - ); - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__5 - ( - .clk( route_units__clk[5] ), - .pos( route_units__pos[5] ), - .reset( route_units__reset[5] ), - .recv__msg( route_units__recv__msg[5] ), - .recv__rdy( route_units__recv__rdy[5] ), - .recv__val( route_units__recv__val[5] ), - .send__msg( route_units__send__msg[5] ), - .send__rdy( route_units__send__rdy[5] ), - .send__val( route_units__send__val[5] ) - ); - - //------------------------------------------------------------- - // End of component route_units[0:5] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component switch_units[0:2] - //------------------------------------------------------------- - - logic [0:0] switch_units__clk [0:2]; - logic [0:0] switch_units__reset [0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 switch_units__recv__msg [0:2][0:5]; - logic [0:0] switch_units__recv__rdy [0:2][0:5]; - logic [0:0] switch_units__recv__val [0:2][0:5]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 switch_units__send__msg [0:2]; - logic [0:0] switch_units__send__rdy [0:2]; - logic [0:0] switch_units__send__val [0:2]; - - SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__0 - ( - .clk( switch_units__clk[0] ), - .reset( switch_units__reset[0] ), - .recv__msg( switch_units__recv__msg[0] ), - .recv__rdy( switch_units__recv__rdy[0] ), - .recv__val( switch_units__recv__val[0] ), - .send__msg( switch_units__send__msg[0] ), - .send__rdy( switch_units__send__rdy[0] ), - .send__val( switch_units__send__val[0] ) - ); - - SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__1 - ( - .clk( switch_units__clk[1] ), - .reset( switch_units__reset[1] ), - .recv__msg( switch_units__recv__msg[1] ), - .recv__rdy( switch_units__recv__rdy[1] ), - .recv__val( switch_units__recv__val[1] ), - .send__msg( switch_units__send__msg[1] ), - .send__rdy( switch_units__send__rdy[1] ), - .send__val( switch_units__send__val[1] ) - ); - - SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__2 - ( - .clk( switch_units__clk[2] ), - .reset( switch_units__reset[2] ), - .recv__msg( switch_units__recv__msg[2] ), - .recv__rdy( switch_units__recv__rdy[2] ), - .recv__val( switch_units__recv__val[2] ), - .send__msg( switch_units__send__msg[2] ), - .send__rdy( switch_units__send__rdy[2] ), - .send__val( switch_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component switch_units[0:2] - //------------------------------------------------------------- - - assign input_units__clk[0] = clk; - assign input_units__reset[0] = reset; - assign input_units__clk[1] = clk; - assign input_units__reset[1] = reset; - assign input_units__clk[2] = clk; - assign input_units__reset[2] = reset; - assign route_units__clk[0] = clk; - assign route_units__reset[0] = reset; - assign route_units__clk[1] = clk; - assign route_units__reset[1] = reset; - assign route_units__clk[2] = clk; - assign route_units__reset[2] = reset; - assign route_units__clk[3] = clk; - assign route_units__reset[3] = reset; - assign route_units__clk[4] = clk; - assign route_units__reset[4] = reset; - assign route_units__clk[5] = clk; - assign route_units__reset[5] = reset; - assign switch_units__clk[0] = clk; - assign switch_units__reset[0] = reset; - assign switch_units__clk[1] = clk; - assign switch_units__reset[1] = reset; - assign switch_units__clk[2] = clk; - assign switch_units__reset[2] = reset; - assign output_units__clk[0] = clk; - assign output_units__reset[0] = reset; - assign output_units__clk[1] = clk; - assign output_units__reset[1] = reset; - assign output_units__clk[2] = clk; - assign output_units__reset[2] = reset; - assign input_units__recv__en[0] = recv__en[0]; - assign input_units__recv__msg[0] = recv__msg[0]; - assign recv__yum[0][0] = input_units__recv__yum[0][0]; - assign recv__yum[0][1] = input_units__recv__yum[0][1]; - assign route_units__recv__msg[0] = input_units__send__msg[0][0]; - assign input_units__send__rdy[0][0] = route_units__recv__rdy[0]; - assign route_units__recv__val[0] = input_units__send__val[0][0]; - assign route_units__pos[0] = pos; - assign route_units__recv__msg[1] = input_units__send__msg[0][1]; - assign input_units__send__rdy[0][1] = route_units__recv__rdy[1]; - assign route_units__recv__val[1] = input_units__send__val[0][1]; - assign route_units__pos[1] = pos; - assign input_units__recv__en[1] = recv__en[1]; - assign input_units__recv__msg[1] = recv__msg[1]; - assign recv__yum[1][0] = input_units__recv__yum[1][0]; - assign recv__yum[1][1] = input_units__recv__yum[1][1]; - assign route_units__recv__msg[2] = input_units__send__msg[1][0]; - assign input_units__send__rdy[1][0] = route_units__recv__rdy[2]; - assign route_units__recv__val[2] = input_units__send__val[1][0]; - assign route_units__pos[2] = pos; - assign route_units__recv__msg[3] = input_units__send__msg[1][1]; - assign input_units__send__rdy[1][1] = route_units__recv__rdy[3]; - assign route_units__recv__val[3] = input_units__send__val[1][1]; - assign route_units__pos[3] = pos; - assign input_units__recv__en[2] = recv__en[2]; - assign input_units__recv__msg[2] = recv__msg[2]; - assign recv__yum[2][0] = input_units__recv__yum[2][0]; - assign recv__yum[2][1] = input_units__recv__yum[2][1]; - assign route_units__recv__msg[4] = input_units__send__msg[2][0]; - assign input_units__send__rdy[2][0] = route_units__recv__rdy[4]; - assign route_units__recv__val[4] = input_units__send__val[2][0]; - assign route_units__pos[4] = pos; - assign route_units__recv__msg[5] = input_units__send__msg[2][1]; - assign input_units__send__rdy[2][1] = route_units__recv__rdy[5]; - assign route_units__recv__val[5] = input_units__send__val[2][1]; - assign route_units__pos[5] = pos; - assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; - assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; - assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; - assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; - assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; - assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; - assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; - assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; - assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; - assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; - assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; - assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; - assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; - assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; - assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; - assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; - assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; - assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; - assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; - assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; - assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; - assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; - assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; - assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; - assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; - assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; - assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; - assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; - assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; - assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; - assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; - assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; - assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; - assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; - assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; - assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; - assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; - assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; - assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; - assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; - assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; - assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; - assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; - assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; - assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; - assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; - assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; - assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; - assign switch_units__recv__msg[1][5] = route_units__send__msg[5][1]; - assign route_units__send__rdy[5][1] = switch_units__recv__rdy[1][5]; - assign switch_units__recv__val[1][5] = route_units__send__val[5][1]; - assign switch_units__recv__msg[2][5] = route_units__send__msg[5][2]; - assign route_units__send__rdy[5][2] = switch_units__recv__rdy[2][5]; - assign switch_units__recv__val[2][5] = route_units__send__val[5][2]; - assign output_units__recv__msg[0] = switch_units__send__msg[0]; - assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; - assign output_units__recv__val[0] = switch_units__send__val[0]; - assign send__en[0] = output_units__send__en[0]; - assign send__msg[0] = output_units__send__msg[0]; - assign output_units__send__yum[0][0] = send__yum[0][0]; - assign output_units__send__yum[0][1] = send__yum[0][1]; - assign output_units__recv__msg[1] = switch_units__send__msg[1]; - assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; - assign output_units__recv__val[1] = switch_units__send__val[1]; - assign send__en[1] = output_units__send__en[1]; - assign send__msg[1] = output_units__send__msg[1]; - assign output_units__send__yum[1][0] = send__yum[1][0]; - assign output_units__send__yum[1][1] = send__yum[1][1]; - assign output_units__recv__msg[2] = switch_units__send__msg[2]; - assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; - assign output_units__recv__val[2] = switch_units__send__val[2]; - assign send__en[2] = output_units__send__en[2]; - assign send__msg[2] = output_units__send__msg[2]; - assign output_units__send__yum[2][0] = send__yum[2][0]; - assign output_units__send__yum[2][1] = send__yum[2][1]; - -endmodule - - -// PyMTL Component RegEnRst Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py - -module RegEnRst__Type_Bits2__reset_value_1 -( - input logic [0:0] clk , - input logic [0:0] en , - input logic [1:0] in_ , - output logic [1:0] out , - input logic [0:0] reset -); - localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 - // @update_ff - // def up_regenrst(): - // if s.reset: s.out <<= reset_value - // elif s.en: s.out <<= s.in_ - - always_ff @(posedge clk) begin : up_regenrst - if ( reset ) begin - out <= 2'( __const__reset_value_at_up_regenrst ); - end - else if ( en ) begin - out <= in_; - end - end - -endmodule - - -// PyMTL Component RoundRobinArbiterEn Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py - -module RoundRobinArbiterEn__nreqs_2 -( - input logic [0:0] clk , - input logic [0:0] en , - output logic [1:0] grants , - input logic [1:0] reqs , - input logic [0:0] reset -); - localparam logic [1:0] __const__nreqs_at_comb_reqs_int = 2'd2; - localparam logic [2:0] __const__nreqsX2_at_comb_reqs_int = 3'd4; - localparam logic [1:0] __const__nreqs_at_comb_grants = 2'd2; - localparam logic [1:0] __const__nreqs_at_comb_priority_int = 2'd2; - localparam logic [2:0] __const__nreqsX2_at_comb_priority_int = 3'd4; - localparam logic [2:0] __const__nreqsX2_at_comb_kills = 3'd4; - localparam logic [2:0] __const__nreqsX2_at_comb_grants_int = 3'd4; - logic [3:0] grants_int; - logic [4:0] kills; - logic [0:0] priority_en; - logic [3:0] priority_int; - logic [3:0] reqs_int; - //------------------------------------------------------------- - // Component priority_reg - //------------------------------------------------------------- - - logic [0:0] priority_reg__clk; - logic [0:0] priority_reg__en; - logic [1:0] priority_reg__in_; - logic [1:0] priority_reg__out; - logic [0:0] priority_reg__reset; - - RegEnRst__Type_Bits2__reset_value_1 priority_reg - ( - .clk( priority_reg__clk ), - .en( priority_reg__en ), - .in_( priority_reg__in_ ), - .out( priority_reg__out ), - .reset( priority_reg__reset ) - ); - - //------------------------------------------------------------- - // End of component priority_reg - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 - // @update - // def comb_grants(): - // for i in range( nreqs ): - // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] - - always_comb begin : comb_grants - for ( int unsigned i = 1'd0; i < 2'( __const__nreqs_at_comb_grants ); i += 1'd1 ) - grants[1'(i)] = grants_int[2'(i)] | grants_int[2'( __const__nreqs_at_comb_grants ) + 2'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 - // @update - // def comb_grants_int(): - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.grants_int[i] @= s.reqs_int[i] - // else: - // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] - - always_comb begin : comb_grants_int - for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) - if ( priority_int[2'(i)] ) begin - grants_int[2'(i)] = reqs_int[2'(i)]; - end - else - grants_int[2'(i)] = ( ~kills[3'(i)] ) & reqs_int[2'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 - // @update - // def comb_kills(): - // s.kills[0] @= 1 - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.kills[i+1] @= s.reqs_int[i] - // else: - // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) - - always_comb begin : comb_kills - kills[3'd0] = 1'd1; - for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) - if ( priority_int[2'(i)] ) begin - kills[3'(i) + 3'd1] = reqs_int[2'(i)]; - end - else - kills[3'(i) + 3'd1] = kills[3'(i)] | ( ( ~kills[3'(i)] ) & reqs_int[2'(i)] ); - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 - // @update - // def comb_priority_en(): - // s.priority_en @= ( s.grants != 0 ) & s.en - - always_comb begin : comb_priority_en - priority_en = ( grants != 2'd0 ) & en; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 - // @update - // def comb_priority_int(): - // s.priority_int[ 0:nreqs ] @= s.priority_reg.out - // s.priority_int[nreqs:nreqsX2] @= 0 - - always_comb begin : comb_priority_int - priority_int[2'd1:2'd0] = priority_reg__out; - priority_int[2'd3:2'( __const__nreqs_at_comb_priority_int )] = 2'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 - // @update - // def comb_reqs_int(): - // s.reqs_int [ 0:nreqs ] @= s.reqs - // s.reqs_int [nreqs:nreqsX2] @= s.reqs - - always_comb begin : comb_reqs_int - reqs_int[2'd1:2'd0] = reqs; - reqs_int[2'd3:2'( __const__nreqs_at_comb_reqs_int )] = reqs; - end - - assign priority_reg__clk = clk; - assign priority_reg__reset = reset; - assign priority_reg__en = priority_en; - assign priority_reg__in_[1:1] = grants[0:0]; - assign priority_reg__in_[0:0] = grants[1:1]; - -endmodule - - -// PyMTL Component BypassQueueCtrlRTL Definition -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueCtrlRTL__num_entries_2 -( - input logic [0:0] clk , - output logic [1:0] count , - output logic [0:0] mux_sel , - output logic [0:0] raddr , - output logic [0:0] recv_rdy , - input logic [0:0] recv_val , - input logic [0:0] reset , - input logic [0:0] send_rdy , - output logic [0:0] send_val , - output logic [0:0] waddr , - output logic [0:0] wen -); - localparam logic [1:0] __const__num_entries_at__lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy = 2'd2; - localparam logic [1:0] __const__num_entries_at_up_reg = 2'd2; - logic [0:0] head; - logic [0:0] recv_xfer; - logic [0:0] send_xfer; - logic [0:0] tail; - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:645 - // s.mux_sel //= lambda: s.count == 0 - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_mux_sel - mux_sel = count == 2'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:642 - // s.recv_rdy //= lambda: s.count < num_entries - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy - recv_rdy = count < 2'( __const__num_entries_at__lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy ); - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:647 - // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_xfer - recv_xfer = recv_val & recv_rdy; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:643 - // s.send_val //= lambda: (s.count > 0) | s.recv_val - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_send_val - send_val = ( count > 2'd0 ) | recv_val; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:648 - // s.send_xfer //= lambda: s.send_val & s.send_rdy - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_send_xfer - send_xfer = send_val & send_rdy; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:650 - // @update_ff - // def up_reg(): - // - // if s.reset: - // s.head <<= 0 - // s.tail <<= 0 - // s.count <<= 0 - // - // else: - // if s.recv_xfer: - // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 - // - // if s.send_xfer: - // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 - // - // if s.recv_xfer & ~s.send_xfer: - // s.count <<= s.count + 1 - // if ~s.recv_xfer & s.send_xfer: - // s.count <<= s.count - 1 - - always_ff @(posedge clk) begin : up_reg - if ( reset ) begin - head <= 1'd0; - tail <= 1'd0; - count <= 2'd0; - end - else begin - if ( recv_xfer ) begin - tail <= ( tail < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? tail + 1'd1 : 1'd0; - end - if ( send_xfer ) begin - head <= ( head < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? head + 1'd1 : 1'd0; - end - if ( recv_xfer & ( ~send_xfer ) ) begin - count <= count + 2'd1; - end - if ( ( ~recv_xfer ) & send_xfer ) begin - count <= count - 2'd1; - end - end - end - - assign wen = recv_xfer; - assign waddr = tail; - assign raddr = head; - -endmodule - - -// PyMTL Component Mux Definition -// Full name: Mux__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ninputs_2 -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__4754a371c6cda085 -( - input logic [0:0] clk , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 in_ [0:1], - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 out , - input logic [0:0] reset , - input logic [0:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component BypassQueueDpathRTL Definition -// Full name: BypassQueueDpathRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueDpathRTL__a1c7a5a18a302c36 -( - input logic [0:0] clk , - input logic [0:0] mux_sel , - input logic [0:0] raddr , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_msg , - input logic [0:0] reset , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__in_ [0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__out; - logic [0:0] mux__reset; - logic [0:0] mux__sel; - - Mux__4754a371c6cda085 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__80167091524f71e4 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - assign mux__clk = clk; - assign mux__reset = reset; - assign mux__sel = mux_sel; - assign mux__in_[0] = rf__rdata[0]; - assign mux__in_[1] = recv_msg; - assign send_msg = mux__out; - -endmodule - - -// PyMTL Component BypassQueueRTL Definition -// Full name: BypassQueueRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueRTL__a1c7a5a18a302c36 -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__mux_sel; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - BypassQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .mux_sel( ctrl__mux_sel ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__mux_sel; - logic [0:0] dpath__raddr; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__recv_msg; - logic [0:0] dpath__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - BypassQueueDpathRTL__a1c7a5a18a302c36 dpath - ( - .clk( dpath__clk ), - .mux_sel( dpath__mux_sel ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign dpath__mux_sel = ctrl__mux_sel; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign count = ctrl__count; - assign dpath__recv_msg = recv__msg; - assign send__msg = dpath__send_msg; - -endmodule - - -// PyMTL Component Encoder Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py - -module Encoder__in_nbits_2__out_nbits_1 -( - input logic [0:0] clk , - input logic [1:0] in_ , - output logic [0:0] out , - input logic [0:0] reset -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 - // @update - // def encode(): - // s.out @= 0 - // for i in range( s.in_nbits ): - // if s.in_[i]: - // s.out @= i - - always_comb begin : encode - out = 1'd0; - for ( int unsigned i = 1'd0; i < 2'd2; i += 1'd1 ) - if ( in_[1'(i)] ) begin - out = 1'(i); - end - end - -endmodule - - -// PyMTL Component CreditRecvRTL2SendRTL Definition -// Full name: CreditRecvRTL2SendRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2__QType_BypassQueueRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py - -module CreditRecvRTL2SendRTL__0d4276a185d5c616 -( - input logic [0:0] clk , - input logic [0:0] reset , - input logic [0:0] recv__en , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__yum [0:1] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [1:0] __const__vc_at_up_enq = 2'd2; - localparam logic [1:0] __const__vc_at_up_deq_and_send = 2'd2; - localparam logic [1:0] __const__vc_at_up_yummy = 2'd2; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [1:0] arbiter__grants; - logic [1:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_2 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component buffers[0:1] - //------------------------------------------------------------- - - logic [0:0] buffers__clk [0:1]; - logic [1:0] buffers__count [0:1]; - logic [0:0] buffers__reset [0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__recv__msg [0:1]; - logic [0:0] buffers__recv__rdy [0:1]; - logic [0:0] buffers__recv__val [0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__send__msg [0:1]; - logic [0:0] buffers__send__rdy [0:1]; - logic [0:0] buffers__send__val [0:1]; - - BypassQueueRTL__a1c7a5a18a302c36 buffers__0 - ( - .clk( buffers__clk[0] ), - .count( buffers__count[0] ), - .reset( buffers__reset[0] ), - .recv__msg( buffers__recv__msg[0] ), - .recv__rdy( buffers__recv__rdy[0] ), - .recv__val( buffers__recv__val[0] ), - .send__msg( buffers__send__msg[0] ), - .send__rdy( buffers__send__rdy[0] ), - .send__val( buffers__send__val[0] ) - ); - - BypassQueueRTL__a1c7a5a18a302c36 buffers__1 - ( - .clk( buffers__clk[1] ), - .count( buffers__count[1] ), - .reset( buffers__reset[1] ), - .recv__msg( buffers__recv__msg[1] ), - .recv__rdy( buffers__recv__rdy[1] ), - .recv__val( buffers__recv__val[1] ), - .send__msg( buffers__send__msg[1] ), - .send__rdy( buffers__send__rdy[1] ), - .send__val( buffers__send__val[1] ) - ); - - //------------------------------------------------------------- - // End of component buffers[0:1] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [1:0] encoder__in_; - logic [0:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_2__out_nbits_1 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:205 - // @update - // def up_deq_and_send(): - // for i in range( vc ): - // s.buffers[i].send.rdy @= 0 - // - // s.send.msg @= s.buffers[ s.encoder.out ].send.msg - // - // if s.arbiter.grants > 0: - // s.send.val @= 1 - // s.buffers[ s.encoder.out ].send.rdy @= s.send.rdy - // else: - // s.send.val @= 0 - - always_comb begin : up_deq_and_send - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_deq_and_send ); i += 1'd1 ) - buffers__send__rdy[1'(i)] = 1'd0; - send__msg = buffers__send__msg[encoder__out]; - if ( arbiter__grants > 2'd0 ) begin - send__val = 1'd1; - buffers__send__rdy[encoder__out] = send__rdy; - end - else - send__val = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:194 - // @update - // def up_enq(): - // if s.recv.en: - // for i in range( vc ): - // s.buffers[i].recv.val @= ( s.recv.msg.vc_id == i ) - // else: - // for i in range( vc ): - // s.buffers[i].recv.val @= 0 - - always_comb begin : up_enq - if ( recv__en ) begin - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) - buffers__recv__val[1'(i)] = recv__msg.vc_id == 1'(i); - end - else - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) - buffers__recv__val[1'(i)] = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:218 - // @update - // def up_yummy(): - // for i in range( vc ): - // s.recv.yum[i] @= s.buffers[i].send.val & s.buffers[i].send.rdy - - always_comb begin : up_yummy - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_yummy ); i += 1'd1 ) - recv__yum[1'(i)] = buffers__send__val[1'(i)] & buffers__send__rdy[1'(i)]; - end - - assign buffers__clk[0] = clk; - assign buffers__reset[0] = reset; - assign buffers__clk[1] = clk; - assign buffers__reset[1] = reset; - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign buffers__recv__msg[0] = recv__msg; - assign arbiter__reqs[0:0] = buffers__send__val[0]; - assign buffers__recv__msg[1] = recv__msg; - assign arbiter__reqs[1:1] = buffers__send__val[1]; - assign encoder__in_ = arbiter__grants; - assign arbiter__en = send__val; - -endmodule - - -// PyMTL Component RingNetworkRTL Definition -// Full name: RingNetworkRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17__chl_lat_1__vc_2__credit_line_2 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingNetworkRTL.py - -module RingNetworkRTL__8866f4e00dbc912a -( - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:16] , - output logic [0:0] recv__rdy [0:16] , - input logic [0:0] recv__val [0:16] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:16] , - input logic [0:0] send__rdy [0:16] , - output logic [0:0] send__val [0:16] -); - //------------------------------------------------------------- - // Component recv_adp[0:16] - //------------------------------------------------------------- - - logic [0:0] recv_adp__clk [0:16]; - logic [0:0] recv_adp__reset [0:16]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_adp__recv__msg [0:16]; - logic [0:0] recv_adp__recv__rdy [0:16]; - logic [0:0] recv_adp__recv__val [0:16]; - logic [0:0] recv_adp__send__en [0:16]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_adp__send__msg [0:16]; - logic [0:0] recv_adp__send__yum [0:16][0:1]; - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__0 - ( - .clk( recv_adp__clk[0] ), - .reset( recv_adp__reset[0] ), - .recv__msg( recv_adp__recv__msg[0] ), - .recv__rdy( recv_adp__recv__rdy[0] ), - .recv__val( recv_adp__recv__val[0] ), - .send__en( recv_adp__send__en[0] ), - .send__msg( recv_adp__send__msg[0] ), - .send__yum( recv_adp__send__yum[0] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__1 - ( - .clk( recv_adp__clk[1] ), - .reset( recv_adp__reset[1] ), - .recv__msg( recv_adp__recv__msg[1] ), - .recv__rdy( recv_adp__recv__rdy[1] ), - .recv__val( recv_adp__recv__val[1] ), - .send__en( recv_adp__send__en[1] ), - .send__msg( recv_adp__send__msg[1] ), - .send__yum( recv_adp__send__yum[1] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__2 - ( - .clk( recv_adp__clk[2] ), - .reset( recv_adp__reset[2] ), - .recv__msg( recv_adp__recv__msg[2] ), - .recv__rdy( recv_adp__recv__rdy[2] ), - .recv__val( recv_adp__recv__val[2] ), - .send__en( recv_adp__send__en[2] ), - .send__msg( recv_adp__send__msg[2] ), - .send__yum( recv_adp__send__yum[2] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__3 - ( - .clk( recv_adp__clk[3] ), - .reset( recv_adp__reset[3] ), - .recv__msg( recv_adp__recv__msg[3] ), - .recv__rdy( recv_adp__recv__rdy[3] ), - .recv__val( recv_adp__recv__val[3] ), - .send__en( recv_adp__send__en[3] ), - .send__msg( recv_adp__send__msg[3] ), - .send__yum( recv_adp__send__yum[3] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__4 - ( - .clk( recv_adp__clk[4] ), - .reset( recv_adp__reset[4] ), - .recv__msg( recv_adp__recv__msg[4] ), - .recv__rdy( recv_adp__recv__rdy[4] ), - .recv__val( recv_adp__recv__val[4] ), - .send__en( recv_adp__send__en[4] ), - .send__msg( recv_adp__send__msg[4] ), - .send__yum( recv_adp__send__yum[4] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__5 - ( - .clk( recv_adp__clk[5] ), - .reset( recv_adp__reset[5] ), - .recv__msg( recv_adp__recv__msg[5] ), - .recv__rdy( recv_adp__recv__rdy[5] ), - .recv__val( recv_adp__recv__val[5] ), - .send__en( recv_adp__send__en[5] ), - .send__msg( recv_adp__send__msg[5] ), - .send__yum( recv_adp__send__yum[5] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__6 - ( - .clk( recv_adp__clk[6] ), - .reset( recv_adp__reset[6] ), - .recv__msg( recv_adp__recv__msg[6] ), - .recv__rdy( recv_adp__recv__rdy[6] ), - .recv__val( recv_adp__recv__val[6] ), - .send__en( recv_adp__send__en[6] ), - .send__msg( recv_adp__send__msg[6] ), - .send__yum( recv_adp__send__yum[6] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__7 - ( - .clk( recv_adp__clk[7] ), - .reset( recv_adp__reset[7] ), - .recv__msg( recv_adp__recv__msg[7] ), - .recv__rdy( recv_adp__recv__rdy[7] ), - .recv__val( recv_adp__recv__val[7] ), - .send__en( recv_adp__send__en[7] ), - .send__msg( recv_adp__send__msg[7] ), - .send__yum( recv_adp__send__yum[7] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__8 - ( - .clk( recv_adp__clk[8] ), - .reset( recv_adp__reset[8] ), - .recv__msg( recv_adp__recv__msg[8] ), - .recv__rdy( recv_adp__recv__rdy[8] ), - .recv__val( recv_adp__recv__val[8] ), - .send__en( recv_adp__send__en[8] ), - .send__msg( recv_adp__send__msg[8] ), - .send__yum( recv_adp__send__yum[8] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__9 - ( - .clk( recv_adp__clk[9] ), - .reset( recv_adp__reset[9] ), - .recv__msg( recv_adp__recv__msg[9] ), - .recv__rdy( recv_adp__recv__rdy[9] ), - .recv__val( recv_adp__recv__val[9] ), - .send__en( recv_adp__send__en[9] ), - .send__msg( recv_adp__send__msg[9] ), - .send__yum( recv_adp__send__yum[9] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__10 - ( - .clk( recv_adp__clk[10] ), - .reset( recv_adp__reset[10] ), - .recv__msg( recv_adp__recv__msg[10] ), - .recv__rdy( recv_adp__recv__rdy[10] ), - .recv__val( recv_adp__recv__val[10] ), - .send__en( recv_adp__send__en[10] ), - .send__msg( recv_adp__send__msg[10] ), - .send__yum( recv_adp__send__yum[10] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__11 - ( - .clk( recv_adp__clk[11] ), - .reset( recv_adp__reset[11] ), - .recv__msg( recv_adp__recv__msg[11] ), - .recv__rdy( recv_adp__recv__rdy[11] ), - .recv__val( recv_adp__recv__val[11] ), - .send__en( recv_adp__send__en[11] ), - .send__msg( recv_adp__send__msg[11] ), - .send__yum( recv_adp__send__yum[11] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__12 - ( - .clk( recv_adp__clk[12] ), - .reset( recv_adp__reset[12] ), - .recv__msg( recv_adp__recv__msg[12] ), - .recv__rdy( recv_adp__recv__rdy[12] ), - .recv__val( recv_adp__recv__val[12] ), - .send__en( recv_adp__send__en[12] ), - .send__msg( recv_adp__send__msg[12] ), - .send__yum( recv_adp__send__yum[12] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__13 - ( - .clk( recv_adp__clk[13] ), - .reset( recv_adp__reset[13] ), - .recv__msg( recv_adp__recv__msg[13] ), - .recv__rdy( recv_adp__recv__rdy[13] ), - .recv__val( recv_adp__recv__val[13] ), - .send__en( recv_adp__send__en[13] ), - .send__msg( recv_adp__send__msg[13] ), - .send__yum( recv_adp__send__yum[13] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__14 - ( - .clk( recv_adp__clk[14] ), - .reset( recv_adp__reset[14] ), - .recv__msg( recv_adp__recv__msg[14] ), - .recv__rdy( recv_adp__recv__rdy[14] ), - .recv__val( recv_adp__recv__val[14] ), - .send__en( recv_adp__send__en[14] ), - .send__msg( recv_adp__send__msg[14] ), - .send__yum( recv_adp__send__yum[14] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__15 - ( - .clk( recv_adp__clk[15] ), - .reset( recv_adp__reset[15] ), - .recv__msg( recv_adp__recv__msg[15] ), - .recv__rdy( recv_adp__recv__rdy[15] ), - .recv__val( recv_adp__recv__val[15] ), - .send__en( recv_adp__send__en[15] ), - .send__msg( recv_adp__send__msg[15] ), - .send__yum( recv_adp__send__yum[15] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__16 - ( - .clk( recv_adp__clk[16] ), - .reset( recv_adp__reset[16] ), - .recv__msg( recv_adp__recv__msg[16] ), - .recv__rdy( recv_adp__recv__rdy[16] ), - .recv__val( recv_adp__recv__val[16] ), - .send__en( recv_adp__send__en[16] ), - .send__msg( recv_adp__send__msg[16] ), - .send__yum( recv_adp__send__yum[16] ) - ); - - //------------------------------------------------------------- - // End of component recv_adp[0:16] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component routers[0:16] - //------------------------------------------------------------- - - logic [0:0] routers__clk [0:16]; - logic [4:0] routers__pos [0:16]; - logic [0:0] routers__reset [0:16]; - logic [0:0] routers__recv__en [0:16][0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 routers__recv__msg [0:16][0:2]; - logic [0:0] routers__recv__yum [0:16][0:2][0:1]; - logic [0:0] routers__send__en [0:16][0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 routers__send__msg [0:16][0:2]; - logic [0:0] routers__send__yum [0:16][0:2][0:1]; - - RingRouterRTL__6e670e447e1766e0 routers__0 - ( - .clk( routers__clk[0] ), - .pos( routers__pos[0] ), - .reset( routers__reset[0] ), - .recv__en( routers__recv__en[0] ), - .recv__msg( routers__recv__msg[0] ), - .recv__yum( routers__recv__yum[0] ), - .send__en( routers__send__en[0] ), - .send__msg( routers__send__msg[0] ), - .send__yum( routers__send__yum[0] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__1 - ( - .clk( routers__clk[1] ), - .pos( routers__pos[1] ), - .reset( routers__reset[1] ), - .recv__en( routers__recv__en[1] ), - .recv__msg( routers__recv__msg[1] ), - .recv__yum( routers__recv__yum[1] ), - .send__en( routers__send__en[1] ), - .send__msg( routers__send__msg[1] ), - .send__yum( routers__send__yum[1] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__2 - ( - .clk( routers__clk[2] ), - .pos( routers__pos[2] ), - .reset( routers__reset[2] ), - .recv__en( routers__recv__en[2] ), - .recv__msg( routers__recv__msg[2] ), - .recv__yum( routers__recv__yum[2] ), - .send__en( routers__send__en[2] ), - .send__msg( routers__send__msg[2] ), - .send__yum( routers__send__yum[2] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__3 - ( - .clk( routers__clk[3] ), - .pos( routers__pos[3] ), - .reset( routers__reset[3] ), - .recv__en( routers__recv__en[3] ), - .recv__msg( routers__recv__msg[3] ), - .recv__yum( routers__recv__yum[3] ), - .send__en( routers__send__en[3] ), - .send__msg( routers__send__msg[3] ), - .send__yum( routers__send__yum[3] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__4 - ( - .clk( routers__clk[4] ), - .pos( routers__pos[4] ), - .reset( routers__reset[4] ), - .recv__en( routers__recv__en[4] ), - .recv__msg( routers__recv__msg[4] ), - .recv__yum( routers__recv__yum[4] ), - .send__en( routers__send__en[4] ), - .send__msg( routers__send__msg[4] ), - .send__yum( routers__send__yum[4] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__5 - ( - .clk( routers__clk[5] ), - .pos( routers__pos[5] ), - .reset( routers__reset[5] ), - .recv__en( routers__recv__en[5] ), - .recv__msg( routers__recv__msg[5] ), - .recv__yum( routers__recv__yum[5] ), - .send__en( routers__send__en[5] ), - .send__msg( routers__send__msg[5] ), - .send__yum( routers__send__yum[5] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__6 - ( - .clk( routers__clk[6] ), - .pos( routers__pos[6] ), - .reset( routers__reset[6] ), - .recv__en( routers__recv__en[6] ), - .recv__msg( routers__recv__msg[6] ), - .recv__yum( routers__recv__yum[6] ), - .send__en( routers__send__en[6] ), - .send__msg( routers__send__msg[6] ), - .send__yum( routers__send__yum[6] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__7 - ( - .clk( routers__clk[7] ), - .pos( routers__pos[7] ), - .reset( routers__reset[7] ), - .recv__en( routers__recv__en[7] ), - .recv__msg( routers__recv__msg[7] ), - .recv__yum( routers__recv__yum[7] ), - .send__en( routers__send__en[7] ), - .send__msg( routers__send__msg[7] ), - .send__yum( routers__send__yum[7] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__8 - ( - .clk( routers__clk[8] ), - .pos( routers__pos[8] ), - .reset( routers__reset[8] ), - .recv__en( routers__recv__en[8] ), - .recv__msg( routers__recv__msg[8] ), - .recv__yum( routers__recv__yum[8] ), - .send__en( routers__send__en[8] ), - .send__msg( routers__send__msg[8] ), - .send__yum( routers__send__yum[8] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__9 - ( - .clk( routers__clk[9] ), - .pos( routers__pos[9] ), - .reset( routers__reset[9] ), - .recv__en( routers__recv__en[9] ), - .recv__msg( routers__recv__msg[9] ), - .recv__yum( routers__recv__yum[9] ), - .send__en( routers__send__en[9] ), - .send__msg( routers__send__msg[9] ), - .send__yum( routers__send__yum[9] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__10 - ( - .clk( routers__clk[10] ), - .pos( routers__pos[10] ), - .reset( routers__reset[10] ), - .recv__en( routers__recv__en[10] ), - .recv__msg( routers__recv__msg[10] ), - .recv__yum( routers__recv__yum[10] ), - .send__en( routers__send__en[10] ), - .send__msg( routers__send__msg[10] ), - .send__yum( routers__send__yum[10] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__11 - ( - .clk( routers__clk[11] ), - .pos( routers__pos[11] ), - .reset( routers__reset[11] ), - .recv__en( routers__recv__en[11] ), - .recv__msg( routers__recv__msg[11] ), - .recv__yum( routers__recv__yum[11] ), - .send__en( routers__send__en[11] ), - .send__msg( routers__send__msg[11] ), - .send__yum( routers__send__yum[11] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__12 - ( - .clk( routers__clk[12] ), - .pos( routers__pos[12] ), - .reset( routers__reset[12] ), - .recv__en( routers__recv__en[12] ), - .recv__msg( routers__recv__msg[12] ), - .recv__yum( routers__recv__yum[12] ), - .send__en( routers__send__en[12] ), - .send__msg( routers__send__msg[12] ), - .send__yum( routers__send__yum[12] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__13 - ( - .clk( routers__clk[13] ), - .pos( routers__pos[13] ), - .reset( routers__reset[13] ), - .recv__en( routers__recv__en[13] ), - .recv__msg( routers__recv__msg[13] ), - .recv__yum( routers__recv__yum[13] ), - .send__en( routers__send__en[13] ), - .send__msg( routers__send__msg[13] ), - .send__yum( routers__send__yum[13] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__14 - ( - .clk( routers__clk[14] ), - .pos( routers__pos[14] ), - .reset( routers__reset[14] ), - .recv__en( routers__recv__en[14] ), - .recv__msg( routers__recv__msg[14] ), - .recv__yum( routers__recv__yum[14] ), - .send__en( routers__send__en[14] ), - .send__msg( routers__send__msg[14] ), - .send__yum( routers__send__yum[14] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__15 - ( - .clk( routers__clk[15] ), - .pos( routers__pos[15] ), - .reset( routers__reset[15] ), - .recv__en( routers__recv__en[15] ), - .recv__msg( routers__recv__msg[15] ), - .recv__yum( routers__recv__yum[15] ), - .send__en( routers__send__en[15] ), - .send__msg( routers__send__msg[15] ), - .send__yum( routers__send__yum[15] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__16 - ( - .clk( routers__clk[16] ), - .pos( routers__pos[16] ), - .reset( routers__reset[16] ), - .recv__en( routers__recv__en[16] ), - .recv__msg( routers__recv__msg[16] ), - .recv__yum( routers__recv__yum[16] ), - .send__en( routers__send__en[16] ), - .send__msg( routers__send__msg[16] ), - .send__yum( routers__send__yum[16] ) - ); - - //------------------------------------------------------------- - // End of component routers[0:16] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component send_adp[0:16] - //------------------------------------------------------------- - - logic [0:0] send_adp__clk [0:16]; - logic [0:0] send_adp__reset [0:16]; - logic [0:0] send_adp__recv__en [0:16]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_adp__recv__msg [0:16]; - logic [0:0] send_adp__recv__yum [0:16][0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_adp__send__msg [0:16]; - logic [0:0] send_adp__send__rdy [0:16]; - logic [0:0] send_adp__send__val [0:16]; - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__0 - ( - .clk( send_adp__clk[0] ), - .reset( send_adp__reset[0] ), - .recv__en( send_adp__recv__en[0] ), - .recv__msg( send_adp__recv__msg[0] ), - .recv__yum( send_adp__recv__yum[0] ), - .send__msg( send_adp__send__msg[0] ), - .send__rdy( send_adp__send__rdy[0] ), - .send__val( send_adp__send__val[0] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__1 - ( - .clk( send_adp__clk[1] ), - .reset( send_adp__reset[1] ), - .recv__en( send_adp__recv__en[1] ), - .recv__msg( send_adp__recv__msg[1] ), - .recv__yum( send_adp__recv__yum[1] ), - .send__msg( send_adp__send__msg[1] ), - .send__rdy( send_adp__send__rdy[1] ), - .send__val( send_adp__send__val[1] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__2 - ( - .clk( send_adp__clk[2] ), - .reset( send_adp__reset[2] ), - .recv__en( send_adp__recv__en[2] ), - .recv__msg( send_adp__recv__msg[2] ), - .recv__yum( send_adp__recv__yum[2] ), - .send__msg( send_adp__send__msg[2] ), - .send__rdy( send_adp__send__rdy[2] ), - .send__val( send_adp__send__val[2] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__3 - ( - .clk( send_adp__clk[3] ), - .reset( send_adp__reset[3] ), - .recv__en( send_adp__recv__en[3] ), - .recv__msg( send_adp__recv__msg[3] ), - .recv__yum( send_adp__recv__yum[3] ), - .send__msg( send_adp__send__msg[3] ), - .send__rdy( send_adp__send__rdy[3] ), - .send__val( send_adp__send__val[3] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__4 - ( - .clk( send_adp__clk[4] ), - .reset( send_adp__reset[4] ), - .recv__en( send_adp__recv__en[4] ), - .recv__msg( send_adp__recv__msg[4] ), - .recv__yum( send_adp__recv__yum[4] ), - .send__msg( send_adp__send__msg[4] ), - .send__rdy( send_adp__send__rdy[4] ), - .send__val( send_adp__send__val[4] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__5 - ( - .clk( send_adp__clk[5] ), - .reset( send_adp__reset[5] ), - .recv__en( send_adp__recv__en[5] ), - .recv__msg( send_adp__recv__msg[5] ), - .recv__yum( send_adp__recv__yum[5] ), - .send__msg( send_adp__send__msg[5] ), - .send__rdy( send_adp__send__rdy[5] ), - .send__val( send_adp__send__val[5] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__6 - ( - .clk( send_adp__clk[6] ), - .reset( send_adp__reset[6] ), - .recv__en( send_adp__recv__en[6] ), - .recv__msg( send_adp__recv__msg[6] ), - .recv__yum( send_adp__recv__yum[6] ), - .send__msg( send_adp__send__msg[6] ), - .send__rdy( send_adp__send__rdy[6] ), - .send__val( send_adp__send__val[6] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__7 - ( - .clk( send_adp__clk[7] ), - .reset( send_adp__reset[7] ), - .recv__en( send_adp__recv__en[7] ), - .recv__msg( send_adp__recv__msg[7] ), - .recv__yum( send_adp__recv__yum[7] ), - .send__msg( send_adp__send__msg[7] ), - .send__rdy( send_adp__send__rdy[7] ), - .send__val( send_adp__send__val[7] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__8 - ( - .clk( send_adp__clk[8] ), - .reset( send_adp__reset[8] ), - .recv__en( send_adp__recv__en[8] ), - .recv__msg( send_adp__recv__msg[8] ), - .recv__yum( send_adp__recv__yum[8] ), - .send__msg( send_adp__send__msg[8] ), - .send__rdy( send_adp__send__rdy[8] ), - .send__val( send_adp__send__val[8] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__9 - ( - .clk( send_adp__clk[9] ), - .reset( send_adp__reset[9] ), - .recv__en( send_adp__recv__en[9] ), - .recv__msg( send_adp__recv__msg[9] ), - .recv__yum( send_adp__recv__yum[9] ), - .send__msg( send_adp__send__msg[9] ), - .send__rdy( send_adp__send__rdy[9] ), - .send__val( send_adp__send__val[9] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__10 - ( - .clk( send_adp__clk[10] ), - .reset( send_adp__reset[10] ), - .recv__en( send_adp__recv__en[10] ), - .recv__msg( send_adp__recv__msg[10] ), - .recv__yum( send_adp__recv__yum[10] ), - .send__msg( send_adp__send__msg[10] ), - .send__rdy( send_adp__send__rdy[10] ), - .send__val( send_adp__send__val[10] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__11 - ( - .clk( send_adp__clk[11] ), - .reset( send_adp__reset[11] ), - .recv__en( send_adp__recv__en[11] ), - .recv__msg( send_adp__recv__msg[11] ), - .recv__yum( send_adp__recv__yum[11] ), - .send__msg( send_adp__send__msg[11] ), - .send__rdy( send_adp__send__rdy[11] ), - .send__val( send_adp__send__val[11] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__12 - ( - .clk( send_adp__clk[12] ), - .reset( send_adp__reset[12] ), - .recv__en( send_adp__recv__en[12] ), - .recv__msg( send_adp__recv__msg[12] ), - .recv__yum( send_adp__recv__yum[12] ), - .send__msg( send_adp__send__msg[12] ), - .send__rdy( send_adp__send__rdy[12] ), - .send__val( send_adp__send__val[12] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__13 - ( - .clk( send_adp__clk[13] ), - .reset( send_adp__reset[13] ), - .recv__en( send_adp__recv__en[13] ), - .recv__msg( send_adp__recv__msg[13] ), - .recv__yum( send_adp__recv__yum[13] ), - .send__msg( send_adp__send__msg[13] ), - .send__rdy( send_adp__send__rdy[13] ), - .send__val( send_adp__send__val[13] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__14 - ( - .clk( send_adp__clk[14] ), - .reset( send_adp__reset[14] ), - .recv__en( send_adp__recv__en[14] ), - .recv__msg( send_adp__recv__msg[14] ), - .recv__yum( send_adp__recv__yum[14] ), - .send__msg( send_adp__send__msg[14] ), - .send__rdy( send_adp__send__rdy[14] ), - .send__val( send_adp__send__val[14] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__15 - ( - .clk( send_adp__clk[15] ), - .reset( send_adp__reset[15] ), - .recv__en( send_adp__recv__en[15] ), - .recv__msg( send_adp__recv__msg[15] ), - .recv__yum( send_adp__recv__yum[15] ), - .send__msg( send_adp__send__msg[15] ), - .send__rdy( send_adp__send__rdy[15] ), - .send__val( send_adp__send__val[15] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__16 - ( - .clk( send_adp__clk[16] ), - .reset( send_adp__reset[16] ), - .recv__en( send_adp__recv__en[16] ), - .recv__msg( send_adp__recv__msg[16] ), - .recv__yum( send_adp__recv__yum[16] ), - .send__msg( send_adp__send__msg[16] ), - .send__rdy( send_adp__send__rdy[16] ), - .send__val( send_adp__send__val[16] ) - ); - - //------------------------------------------------------------- - // End of component send_adp[0:16] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingNetworkRTL.py:58 - // @update - // def up_pos(): - // for r in range( s.num_routers ): - // s.routers[r].pos @= r - - always_comb begin : up_pos - for ( int unsigned r = 1'd0; r < 5'd17; r += 1'd1 ) - routers__pos[5'(r)] = 5'(r); - end - - assign routers__clk[0] = clk; - assign routers__reset[0] = reset; - assign routers__clk[1] = clk; - assign routers__reset[1] = reset; - assign routers__clk[2] = clk; - assign routers__reset[2] = reset; - assign routers__clk[3] = clk; - assign routers__reset[3] = reset; - assign routers__clk[4] = clk; - assign routers__reset[4] = reset; - assign routers__clk[5] = clk; - assign routers__reset[5] = reset; - assign routers__clk[6] = clk; - assign routers__reset[6] = reset; - assign routers__clk[7] = clk; - assign routers__reset[7] = reset; - assign routers__clk[8] = clk; - assign routers__reset[8] = reset; - assign routers__clk[9] = clk; - assign routers__reset[9] = reset; - assign routers__clk[10] = clk; - assign routers__reset[10] = reset; - assign routers__clk[11] = clk; - assign routers__reset[11] = reset; - assign routers__clk[12] = clk; - assign routers__reset[12] = reset; - assign routers__clk[13] = clk; - assign routers__reset[13] = reset; - assign routers__clk[14] = clk; - assign routers__reset[14] = reset; - assign routers__clk[15] = clk; - assign routers__reset[15] = reset; - assign routers__clk[16] = clk; - assign routers__reset[16] = reset; - assign recv_adp__clk[0] = clk; - assign recv_adp__reset[0] = reset; - assign recv_adp__clk[1] = clk; - assign recv_adp__reset[1] = reset; - assign recv_adp__clk[2] = clk; - assign recv_adp__reset[2] = reset; - assign recv_adp__clk[3] = clk; - assign recv_adp__reset[3] = reset; - assign recv_adp__clk[4] = clk; - assign recv_adp__reset[4] = reset; - assign recv_adp__clk[5] = clk; - assign recv_adp__reset[5] = reset; - assign recv_adp__clk[6] = clk; - assign recv_adp__reset[6] = reset; - assign recv_adp__clk[7] = clk; - assign recv_adp__reset[7] = reset; - assign recv_adp__clk[8] = clk; - assign recv_adp__reset[8] = reset; - assign recv_adp__clk[9] = clk; - assign recv_adp__reset[9] = reset; - assign recv_adp__clk[10] = clk; - assign recv_adp__reset[10] = reset; - assign recv_adp__clk[11] = clk; - assign recv_adp__reset[11] = reset; - assign recv_adp__clk[12] = clk; - assign recv_adp__reset[12] = reset; - assign recv_adp__clk[13] = clk; - assign recv_adp__reset[13] = reset; - assign recv_adp__clk[14] = clk; - assign recv_adp__reset[14] = reset; - assign recv_adp__clk[15] = clk; - assign recv_adp__reset[15] = reset; - assign recv_adp__clk[16] = clk; - assign recv_adp__reset[16] = reset; - assign send_adp__clk[0] = clk; - assign send_adp__reset[0] = reset; - assign send_adp__clk[1] = clk; - assign send_adp__reset[1] = reset; - assign send_adp__clk[2] = clk; - assign send_adp__reset[2] = reset; - assign send_adp__clk[3] = clk; - assign send_adp__reset[3] = reset; - assign send_adp__clk[4] = clk; - assign send_adp__reset[4] = reset; - assign send_adp__clk[5] = clk; - assign send_adp__reset[5] = reset; - assign send_adp__clk[6] = clk; - assign send_adp__reset[6] = reset; - assign send_adp__clk[7] = clk; - assign send_adp__reset[7] = reset; - assign send_adp__clk[8] = clk; - assign send_adp__reset[8] = reset; - assign send_adp__clk[9] = clk; - assign send_adp__reset[9] = reset; - assign send_adp__clk[10] = clk; - assign send_adp__reset[10] = reset; - assign send_adp__clk[11] = clk; - assign send_adp__reset[11] = reset; - assign send_adp__clk[12] = clk; - assign send_adp__reset[12] = reset; - assign send_adp__clk[13] = clk; - assign send_adp__reset[13] = reset; - assign send_adp__clk[14] = clk; - assign send_adp__reset[14] = reset; - assign send_adp__clk[15] = clk; - assign send_adp__reset[15] = reset; - assign send_adp__clk[16] = clk; - assign send_adp__reset[16] = reset; - assign routers__recv__en[1][0] = routers__send__en[0][1]; - assign routers__recv__msg[1][0] = routers__send__msg[0][1]; - assign routers__send__yum[0][1][0] = routers__recv__yum[1][0][0]; - assign routers__send__yum[0][1][1] = routers__recv__yum[1][0][1]; - assign routers__recv__en[0][1] = routers__send__en[1][0]; - assign routers__recv__msg[0][1] = routers__send__msg[1][0]; - assign routers__send__yum[1][0][0] = routers__recv__yum[0][1][0]; - assign routers__send__yum[1][0][1] = routers__recv__yum[0][1][1]; - assign recv_adp__recv__msg[0] = recv__msg[0]; - assign recv__rdy[0] = recv_adp__recv__rdy[0]; - assign recv_adp__recv__val[0] = recv__val[0]; - assign routers__recv__en[0][2] = recv_adp__send__en[0]; - assign routers__recv__msg[0][2] = recv_adp__send__msg[0]; - assign recv_adp__send__yum[0][0] = routers__recv__yum[0][2][0]; - assign recv_adp__send__yum[0][1] = routers__recv__yum[0][2][1]; - assign send_adp__recv__en[0] = routers__send__en[0][2]; - assign send_adp__recv__msg[0] = routers__send__msg[0][2]; - assign routers__send__yum[0][2][0] = send_adp__recv__yum[0][0]; - assign routers__send__yum[0][2][1] = send_adp__recv__yum[0][1]; - assign send__msg[0] = send_adp__send__msg[0]; - assign send_adp__send__rdy[0] = send__rdy[0]; - assign send__val[0] = send_adp__send__val[0]; - assign routers__recv__en[2][0] = routers__send__en[1][1]; - assign routers__recv__msg[2][0] = routers__send__msg[1][1]; - assign routers__send__yum[1][1][0] = routers__recv__yum[2][0][0]; - assign routers__send__yum[1][1][1] = routers__recv__yum[2][0][1]; - assign routers__recv__en[1][1] = routers__send__en[2][0]; - assign routers__recv__msg[1][1] = routers__send__msg[2][0]; - assign routers__send__yum[2][0][0] = routers__recv__yum[1][1][0]; - assign routers__send__yum[2][0][1] = routers__recv__yum[1][1][1]; - assign recv_adp__recv__msg[1] = recv__msg[1]; - assign recv__rdy[1] = recv_adp__recv__rdy[1]; - assign recv_adp__recv__val[1] = recv__val[1]; - assign routers__recv__en[1][2] = recv_adp__send__en[1]; - assign routers__recv__msg[1][2] = recv_adp__send__msg[1]; - assign recv_adp__send__yum[1][0] = routers__recv__yum[1][2][0]; - assign recv_adp__send__yum[1][1] = routers__recv__yum[1][2][1]; - assign send_adp__recv__en[1] = routers__send__en[1][2]; - assign send_adp__recv__msg[1] = routers__send__msg[1][2]; - assign routers__send__yum[1][2][0] = send_adp__recv__yum[1][0]; - assign routers__send__yum[1][2][1] = send_adp__recv__yum[1][1]; - assign send__msg[1] = send_adp__send__msg[1]; - assign send_adp__send__rdy[1] = send__rdy[1]; - assign send__val[1] = send_adp__send__val[1]; - assign routers__recv__en[3][0] = routers__send__en[2][1]; - assign routers__recv__msg[3][0] = routers__send__msg[2][1]; - assign routers__send__yum[2][1][0] = routers__recv__yum[3][0][0]; - assign routers__send__yum[2][1][1] = routers__recv__yum[3][0][1]; - assign routers__recv__en[2][1] = routers__send__en[3][0]; - assign routers__recv__msg[2][1] = routers__send__msg[3][0]; - assign routers__send__yum[3][0][0] = routers__recv__yum[2][1][0]; - assign routers__send__yum[3][0][1] = routers__recv__yum[2][1][1]; - assign recv_adp__recv__msg[2] = recv__msg[2]; - assign recv__rdy[2] = recv_adp__recv__rdy[2]; - assign recv_adp__recv__val[2] = recv__val[2]; - assign routers__recv__en[2][2] = recv_adp__send__en[2]; - assign routers__recv__msg[2][2] = recv_adp__send__msg[2]; - assign recv_adp__send__yum[2][0] = routers__recv__yum[2][2][0]; - assign recv_adp__send__yum[2][1] = routers__recv__yum[2][2][1]; - assign send_adp__recv__en[2] = routers__send__en[2][2]; - assign send_adp__recv__msg[2] = routers__send__msg[2][2]; - assign routers__send__yum[2][2][0] = send_adp__recv__yum[2][0]; - assign routers__send__yum[2][2][1] = send_adp__recv__yum[2][1]; - assign send__msg[2] = send_adp__send__msg[2]; - assign send_adp__send__rdy[2] = send__rdy[2]; - assign send__val[2] = send_adp__send__val[2]; - assign routers__recv__en[4][0] = routers__send__en[3][1]; - assign routers__recv__msg[4][0] = routers__send__msg[3][1]; - assign routers__send__yum[3][1][0] = routers__recv__yum[4][0][0]; - assign routers__send__yum[3][1][1] = routers__recv__yum[4][0][1]; - assign routers__recv__en[3][1] = routers__send__en[4][0]; - assign routers__recv__msg[3][1] = routers__send__msg[4][0]; - assign routers__send__yum[4][0][0] = routers__recv__yum[3][1][0]; - assign routers__send__yum[4][0][1] = routers__recv__yum[3][1][1]; - assign recv_adp__recv__msg[3] = recv__msg[3]; - assign recv__rdy[3] = recv_adp__recv__rdy[3]; - assign recv_adp__recv__val[3] = recv__val[3]; - assign routers__recv__en[3][2] = recv_adp__send__en[3]; - assign routers__recv__msg[3][2] = recv_adp__send__msg[3]; - assign recv_adp__send__yum[3][0] = routers__recv__yum[3][2][0]; - assign recv_adp__send__yum[3][1] = routers__recv__yum[3][2][1]; - assign send_adp__recv__en[3] = routers__send__en[3][2]; - assign send_adp__recv__msg[3] = routers__send__msg[3][2]; - assign routers__send__yum[3][2][0] = send_adp__recv__yum[3][0]; - assign routers__send__yum[3][2][1] = send_adp__recv__yum[3][1]; - assign send__msg[3] = send_adp__send__msg[3]; - assign send_adp__send__rdy[3] = send__rdy[3]; - assign send__val[3] = send_adp__send__val[3]; - assign routers__recv__en[5][0] = routers__send__en[4][1]; - assign routers__recv__msg[5][0] = routers__send__msg[4][1]; - assign routers__send__yum[4][1][0] = routers__recv__yum[5][0][0]; - assign routers__send__yum[4][1][1] = routers__recv__yum[5][0][1]; - assign routers__recv__en[4][1] = routers__send__en[5][0]; - assign routers__recv__msg[4][1] = routers__send__msg[5][0]; - assign routers__send__yum[5][0][0] = routers__recv__yum[4][1][0]; - assign routers__send__yum[5][0][1] = routers__recv__yum[4][1][1]; - assign recv_adp__recv__msg[4] = recv__msg[4]; - assign recv__rdy[4] = recv_adp__recv__rdy[4]; - assign recv_adp__recv__val[4] = recv__val[4]; - assign routers__recv__en[4][2] = recv_adp__send__en[4]; - assign routers__recv__msg[4][2] = recv_adp__send__msg[4]; - assign recv_adp__send__yum[4][0] = routers__recv__yum[4][2][0]; - assign recv_adp__send__yum[4][1] = routers__recv__yum[4][2][1]; - assign send_adp__recv__en[4] = routers__send__en[4][2]; - assign send_adp__recv__msg[4] = routers__send__msg[4][2]; - assign routers__send__yum[4][2][0] = send_adp__recv__yum[4][0]; - assign routers__send__yum[4][2][1] = send_adp__recv__yum[4][1]; - assign send__msg[4] = send_adp__send__msg[4]; - assign send_adp__send__rdy[4] = send__rdy[4]; - assign send__val[4] = send_adp__send__val[4]; - assign routers__recv__en[6][0] = routers__send__en[5][1]; - assign routers__recv__msg[6][0] = routers__send__msg[5][1]; - assign routers__send__yum[5][1][0] = routers__recv__yum[6][0][0]; - assign routers__send__yum[5][1][1] = routers__recv__yum[6][0][1]; - assign routers__recv__en[5][1] = routers__send__en[6][0]; - assign routers__recv__msg[5][1] = routers__send__msg[6][0]; - assign routers__send__yum[6][0][0] = routers__recv__yum[5][1][0]; - assign routers__send__yum[6][0][1] = routers__recv__yum[5][1][1]; - assign recv_adp__recv__msg[5] = recv__msg[5]; - assign recv__rdy[5] = recv_adp__recv__rdy[5]; - assign recv_adp__recv__val[5] = recv__val[5]; - assign routers__recv__en[5][2] = recv_adp__send__en[5]; - assign routers__recv__msg[5][2] = recv_adp__send__msg[5]; - assign recv_adp__send__yum[5][0] = routers__recv__yum[5][2][0]; - assign recv_adp__send__yum[5][1] = routers__recv__yum[5][2][1]; - assign send_adp__recv__en[5] = routers__send__en[5][2]; - assign send_adp__recv__msg[5] = routers__send__msg[5][2]; - assign routers__send__yum[5][2][0] = send_adp__recv__yum[5][0]; - assign routers__send__yum[5][2][1] = send_adp__recv__yum[5][1]; - assign send__msg[5] = send_adp__send__msg[5]; - assign send_adp__send__rdy[5] = send__rdy[5]; - assign send__val[5] = send_adp__send__val[5]; - assign routers__recv__en[7][0] = routers__send__en[6][1]; - assign routers__recv__msg[7][0] = routers__send__msg[6][1]; - assign routers__send__yum[6][1][0] = routers__recv__yum[7][0][0]; - assign routers__send__yum[6][1][1] = routers__recv__yum[7][0][1]; - assign routers__recv__en[6][1] = routers__send__en[7][0]; - assign routers__recv__msg[6][1] = routers__send__msg[7][0]; - assign routers__send__yum[7][0][0] = routers__recv__yum[6][1][0]; - assign routers__send__yum[7][0][1] = routers__recv__yum[6][1][1]; - assign recv_adp__recv__msg[6] = recv__msg[6]; - assign recv__rdy[6] = recv_adp__recv__rdy[6]; - assign recv_adp__recv__val[6] = recv__val[6]; - assign routers__recv__en[6][2] = recv_adp__send__en[6]; - assign routers__recv__msg[6][2] = recv_adp__send__msg[6]; - assign recv_adp__send__yum[6][0] = routers__recv__yum[6][2][0]; - assign recv_adp__send__yum[6][1] = routers__recv__yum[6][2][1]; - assign send_adp__recv__en[6] = routers__send__en[6][2]; - assign send_adp__recv__msg[6] = routers__send__msg[6][2]; - assign routers__send__yum[6][2][0] = send_adp__recv__yum[6][0]; - assign routers__send__yum[6][2][1] = send_adp__recv__yum[6][1]; - assign send__msg[6] = send_adp__send__msg[6]; - assign send_adp__send__rdy[6] = send__rdy[6]; - assign send__val[6] = send_adp__send__val[6]; - assign routers__recv__en[8][0] = routers__send__en[7][1]; - assign routers__recv__msg[8][0] = routers__send__msg[7][1]; - assign routers__send__yum[7][1][0] = routers__recv__yum[8][0][0]; - assign routers__send__yum[7][1][1] = routers__recv__yum[8][0][1]; - assign routers__recv__en[7][1] = routers__send__en[8][0]; - assign routers__recv__msg[7][1] = routers__send__msg[8][0]; - assign routers__send__yum[8][0][0] = routers__recv__yum[7][1][0]; - assign routers__send__yum[8][0][1] = routers__recv__yum[7][1][1]; - assign recv_adp__recv__msg[7] = recv__msg[7]; - assign recv__rdy[7] = recv_adp__recv__rdy[7]; - assign recv_adp__recv__val[7] = recv__val[7]; - assign routers__recv__en[7][2] = recv_adp__send__en[7]; - assign routers__recv__msg[7][2] = recv_adp__send__msg[7]; - assign recv_adp__send__yum[7][0] = routers__recv__yum[7][2][0]; - assign recv_adp__send__yum[7][1] = routers__recv__yum[7][2][1]; - assign send_adp__recv__en[7] = routers__send__en[7][2]; - assign send_adp__recv__msg[7] = routers__send__msg[7][2]; - assign routers__send__yum[7][2][0] = send_adp__recv__yum[7][0]; - assign routers__send__yum[7][2][1] = send_adp__recv__yum[7][1]; - assign send__msg[7] = send_adp__send__msg[7]; - assign send_adp__send__rdy[7] = send__rdy[7]; - assign send__val[7] = send_adp__send__val[7]; - assign routers__recv__en[9][0] = routers__send__en[8][1]; - assign routers__recv__msg[9][0] = routers__send__msg[8][1]; - assign routers__send__yum[8][1][0] = routers__recv__yum[9][0][0]; - assign routers__send__yum[8][1][1] = routers__recv__yum[9][0][1]; - assign routers__recv__en[8][1] = routers__send__en[9][0]; - assign routers__recv__msg[8][1] = routers__send__msg[9][0]; - assign routers__send__yum[9][0][0] = routers__recv__yum[8][1][0]; - assign routers__send__yum[9][0][1] = routers__recv__yum[8][1][1]; - assign recv_adp__recv__msg[8] = recv__msg[8]; - assign recv__rdy[8] = recv_adp__recv__rdy[8]; - assign recv_adp__recv__val[8] = recv__val[8]; - assign routers__recv__en[8][2] = recv_adp__send__en[8]; - assign routers__recv__msg[8][2] = recv_adp__send__msg[8]; - assign recv_adp__send__yum[8][0] = routers__recv__yum[8][2][0]; - assign recv_adp__send__yum[8][1] = routers__recv__yum[8][2][1]; - assign send_adp__recv__en[8] = routers__send__en[8][2]; - assign send_adp__recv__msg[8] = routers__send__msg[8][2]; - assign routers__send__yum[8][2][0] = send_adp__recv__yum[8][0]; - assign routers__send__yum[8][2][1] = send_adp__recv__yum[8][1]; - assign send__msg[8] = send_adp__send__msg[8]; - assign send_adp__send__rdy[8] = send__rdy[8]; - assign send__val[8] = send_adp__send__val[8]; - assign routers__recv__en[10][0] = routers__send__en[9][1]; - assign routers__recv__msg[10][0] = routers__send__msg[9][1]; - assign routers__send__yum[9][1][0] = routers__recv__yum[10][0][0]; - assign routers__send__yum[9][1][1] = routers__recv__yum[10][0][1]; - assign routers__recv__en[9][1] = routers__send__en[10][0]; - assign routers__recv__msg[9][1] = routers__send__msg[10][0]; - assign routers__send__yum[10][0][0] = routers__recv__yum[9][1][0]; - assign routers__send__yum[10][0][1] = routers__recv__yum[9][1][1]; - assign recv_adp__recv__msg[9] = recv__msg[9]; - assign recv__rdy[9] = recv_adp__recv__rdy[9]; - assign recv_adp__recv__val[9] = recv__val[9]; - assign routers__recv__en[9][2] = recv_adp__send__en[9]; - assign routers__recv__msg[9][2] = recv_adp__send__msg[9]; - assign recv_adp__send__yum[9][0] = routers__recv__yum[9][2][0]; - assign recv_adp__send__yum[9][1] = routers__recv__yum[9][2][1]; - assign send_adp__recv__en[9] = routers__send__en[9][2]; - assign send_adp__recv__msg[9] = routers__send__msg[9][2]; - assign routers__send__yum[9][2][0] = send_adp__recv__yum[9][0]; - assign routers__send__yum[9][2][1] = send_adp__recv__yum[9][1]; - assign send__msg[9] = send_adp__send__msg[9]; - assign send_adp__send__rdy[9] = send__rdy[9]; - assign send__val[9] = send_adp__send__val[9]; - assign routers__recv__en[11][0] = routers__send__en[10][1]; - assign routers__recv__msg[11][0] = routers__send__msg[10][1]; - assign routers__send__yum[10][1][0] = routers__recv__yum[11][0][0]; - assign routers__send__yum[10][1][1] = routers__recv__yum[11][0][1]; - assign routers__recv__en[10][1] = routers__send__en[11][0]; - assign routers__recv__msg[10][1] = routers__send__msg[11][0]; - assign routers__send__yum[11][0][0] = routers__recv__yum[10][1][0]; - assign routers__send__yum[11][0][1] = routers__recv__yum[10][1][1]; - assign recv_adp__recv__msg[10] = recv__msg[10]; - assign recv__rdy[10] = recv_adp__recv__rdy[10]; - assign recv_adp__recv__val[10] = recv__val[10]; - assign routers__recv__en[10][2] = recv_adp__send__en[10]; - assign routers__recv__msg[10][2] = recv_adp__send__msg[10]; - assign recv_adp__send__yum[10][0] = routers__recv__yum[10][2][0]; - assign recv_adp__send__yum[10][1] = routers__recv__yum[10][2][1]; - assign send_adp__recv__en[10] = routers__send__en[10][2]; - assign send_adp__recv__msg[10] = routers__send__msg[10][2]; - assign routers__send__yum[10][2][0] = send_adp__recv__yum[10][0]; - assign routers__send__yum[10][2][1] = send_adp__recv__yum[10][1]; - assign send__msg[10] = send_adp__send__msg[10]; - assign send_adp__send__rdy[10] = send__rdy[10]; - assign send__val[10] = send_adp__send__val[10]; - assign routers__recv__en[12][0] = routers__send__en[11][1]; - assign routers__recv__msg[12][0] = routers__send__msg[11][1]; - assign routers__send__yum[11][1][0] = routers__recv__yum[12][0][0]; - assign routers__send__yum[11][1][1] = routers__recv__yum[12][0][1]; - assign routers__recv__en[11][1] = routers__send__en[12][0]; - assign routers__recv__msg[11][1] = routers__send__msg[12][0]; - assign routers__send__yum[12][0][0] = routers__recv__yum[11][1][0]; - assign routers__send__yum[12][0][1] = routers__recv__yum[11][1][1]; - assign recv_adp__recv__msg[11] = recv__msg[11]; - assign recv__rdy[11] = recv_adp__recv__rdy[11]; - assign recv_adp__recv__val[11] = recv__val[11]; - assign routers__recv__en[11][2] = recv_adp__send__en[11]; - assign routers__recv__msg[11][2] = recv_adp__send__msg[11]; - assign recv_adp__send__yum[11][0] = routers__recv__yum[11][2][0]; - assign recv_adp__send__yum[11][1] = routers__recv__yum[11][2][1]; - assign send_adp__recv__en[11] = routers__send__en[11][2]; - assign send_adp__recv__msg[11] = routers__send__msg[11][2]; - assign routers__send__yum[11][2][0] = send_adp__recv__yum[11][0]; - assign routers__send__yum[11][2][1] = send_adp__recv__yum[11][1]; - assign send__msg[11] = send_adp__send__msg[11]; - assign send_adp__send__rdy[11] = send__rdy[11]; - assign send__val[11] = send_adp__send__val[11]; - assign routers__recv__en[13][0] = routers__send__en[12][1]; - assign routers__recv__msg[13][0] = routers__send__msg[12][1]; - assign routers__send__yum[12][1][0] = routers__recv__yum[13][0][0]; - assign routers__send__yum[12][1][1] = routers__recv__yum[13][0][1]; - assign routers__recv__en[12][1] = routers__send__en[13][0]; - assign routers__recv__msg[12][1] = routers__send__msg[13][0]; - assign routers__send__yum[13][0][0] = routers__recv__yum[12][1][0]; - assign routers__send__yum[13][0][1] = routers__recv__yum[12][1][1]; - assign recv_adp__recv__msg[12] = recv__msg[12]; - assign recv__rdy[12] = recv_adp__recv__rdy[12]; - assign recv_adp__recv__val[12] = recv__val[12]; - assign routers__recv__en[12][2] = recv_adp__send__en[12]; - assign routers__recv__msg[12][2] = recv_adp__send__msg[12]; - assign recv_adp__send__yum[12][0] = routers__recv__yum[12][2][0]; - assign recv_adp__send__yum[12][1] = routers__recv__yum[12][2][1]; - assign send_adp__recv__en[12] = routers__send__en[12][2]; - assign send_adp__recv__msg[12] = routers__send__msg[12][2]; - assign routers__send__yum[12][2][0] = send_adp__recv__yum[12][0]; - assign routers__send__yum[12][2][1] = send_adp__recv__yum[12][1]; - assign send__msg[12] = send_adp__send__msg[12]; - assign send_adp__send__rdy[12] = send__rdy[12]; - assign send__val[12] = send_adp__send__val[12]; - assign routers__recv__en[14][0] = routers__send__en[13][1]; - assign routers__recv__msg[14][0] = routers__send__msg[13][1]; - assign routers__send__yum[13][1][0] = routers__recv__yum[14][0][0]; - assign routers__send__yum[13][1][1] = routers__recv__yum[14][0][1]; - assign routers__recv__en[13][1] = routers__send__en[14][0]; - assign routers__recv__msg[13][1] = routers__send__msg[14][0]; - assign routers__send__yum[14][0][0] = routers__recv__yum[13][1][0]; - assign routers__send__yum[14][0][1] = routers__recv__yum[13][1][1]; - assign recv_adp__recv__msg[13] = recv__msg[13]; - assign recv__rdy[13] = recv_adp__recv__rdy[13]; - assign recv_adp__recv__val[13] = recv__val[13]; - assign routers__recv__en[13][2] = recv_adp__send__en[13]; - assign routers__recv__msg[13][2] = recv_adp__send__msg[13]; - assign recv_adp__send__yum[13][0] = routers__recv__yum[13][2][0]; - assign recv_adp__send__yum[13][1] = routers__recv__yum[13][2][1]; - assign send_adp__recv__en[13] = routers__send__en[13][2]; - assign send_adp__recv__msg[13] = routers__send__msg[13][2]; - assign routers__send__yum[13][2][0] = send_adp__recv__yum[13][0]; - assign routers__send__yum[13][2][1] = send_adp__recv__yum[13][1]; - assign send__msg[13] = send_adp__send__msg[13]; - assign send_adp__send__rdy[13] = send__rdy[13]; - assign send__val[13] = send_adp__send__val[13]; - assign routers__recv__en[15][0] = routers__send__en[14][1]; - assign routers__recv__msg[15][0] = routers__send__msg[14][1]; - assign routers__send__yum[14][1][0] = routers__recv__yum[15][0][0]; - assign routers__send__yum[14][1][1] = routers__recv__yum[15][0][1]; - assign routers__recv__en[14][1] = routers__send__en[15][0]; - assign routers__recv__msg[14][1] = routers__send__msg[15][0]; - assign routers__send__yum[15][0][0] = routers__recv__yum[14][1][0]; - assign routers__send__yum[15][0][1] = routers__recv__yum[14][1][1]; - assign recv_adp__recv__msg[14] = recv__msg[14]; - assign recv__rdy[14] = recv_adp__recv__rdy[14]; - assign recv_adp__recv__val[14] = recv__val[14]; - assign routers__recv__en[14][2] = recv_adp__send__en[14]; - assign routers__recv__msg[14][2] = recv_adp__send__msg[14]; - assign recv_adp__send__yum[14][0] = routers__recv__yum[14][2][0]; - assign recv_adp__send__yum[14][1] = routers__recv__yum[14][2][1]; - assign send_adp__recv__en[14] = routers__send__en[14][2]; - assign send_adp__recv__msg[14] = routers__send__msg[14][2]; - assign routers__send__yum[14][2][0] = send_adp__recv__yum[14][0]; - assign routers__send__yum[14][2][1] = send_adp__recv__yum[14][1]; - assign send__msg[14] = send_adp__send__msg[14]; - assign send_adp__send__rdy[14] = send__rdy[14]; - assign send__val[14] = send_adp__send__val[14]; - assign routers__recv__en[16][0] = routers__send__en[15][1]; - assign routers__recv__msg[16][0] = routers__send__msg[15][1]; - assign routers__send__yum[15][1][0] = routers__recv__yum[16][0][0]; - assign routers__send__yum[15][1][1] = routers__recv__yum[16][0][1]; - assign routers__recv__en[15][1] = routers__send__en[16][0]; - assign routers__recv__msg[15][1] = routers__send__msg[16][0]; - assign routers__send__yum[16][0][0] = routers__recv__yum[15][1][0]; - assign routers__send__yum[16][0][1] = routers__recv__yum[15][1][1]; - assign recv_adp__recv__msg[15] = recv__msg[15]; - assign recv__rdy[15] = recv_adp__recv__rdy[15]; - assign recv_adp__recv__val[15] = recv__val[15]; - assign routers__recv__en[15][2] = recv_adp__send__en[15]; - assign routers__recv__msg[15][2] = recv_adp__send__msg[15]; - assign recv_adp__send__yum[15][0] = routers__recv__yum[15][2][0]; - assign recv_adp__send__yum[15][1] = routers__recv__yum[15][2][1]; - assign send_adp__recv__en[15] = routers__send__en[15][2]; - assign send_adp__recv__msg[15] = routers__send__msg[15][2]; - assign routers__send__yum[15][2][0] = send_adp__recv__yum[15][0]; - assign routers__send__yum[15][2][1] = send_adp__recv__yum[15][1]; - assign send__msg[15] = send_adp__send__msg[15]; - assign send_adp__send__rdy[15] = send__rdy[15]; - assign send__val[15] = send_adp__send__val[15]; - assign routers__recv__en[0][0] = routers__send__en[16][1]; - assign routers__recv__msg[0][0] = routers__send__msg[16][1]; - assign routers__send__yum[16][1][0] = routers__recv__yum[0][0][0]; - assign routers__send__yum[16][1][1] = routers__recv__yum[0][0][1]; - assign routers__recv__en[16][1] = routers__send__en[0][0]; - assign routers__recv__msg[16][1] = routers__send__msg[0][0]; - assign routers__send__yum[0][0][0] = routers__recv__yum[16][1][0]; - assign routers__send__yum[0][0][1] = routers__recv__yum[16][1][1]; - assign recv_adp__recv__msg[16] = recv__msg[16]; - assign recv__rdy[16] = recv_adp__recv__rdy[16]; - assign recv_adp__recv__val[16] = recv__val[16]; - assign routers__recv__en[16][2] = recv_adp__send__en[16]; - assign routers__recv__msg[16][2] = recv_adp__send__msg[16]; - assign recv_adp__send__yum[16][0] = routers__recv__yum[16][2][0]; - assign recv_adp__send__yum[16][1] = routers__recv__yum[16][2][1]; - assign send_adp__recv__en[16] = routers__send__en[16][2]; - assign send_adp__recv__msg[16] = routers__send__msg[16][2]; - assign routers__send__yum[16][2][0] = send_adp__recv__yum[16][0]; - assign routers__send__yum[16][2][1] = send_adp__recv__yum[16][1]; - assign send__msg[16] = send_adp__send__msg[16]; - assign send_adp__send__rdy[16] = send__rdy[16]; - assign send__val[16] = send_adp__send__val[16]; - -endmodule - - -// PyMTL Component ChannelRTL Definition -// Full name: ChannelRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_NormalQueueRTL__latency_0 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py - -module ChannelRTL__c31a2b1c86c6a129 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - assign send__msg = recv__msg; - assign recv__rdy = send__rdy; - assign send__val = recv__val; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__nregs_16__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__bd22936ec5812d0d -( - input logic [0:0] clk , - input logic [3:0] raddr [0:0], - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rdata [0:0], - input logic [0:0] reset , - input logic [3:0] waddr [0:0], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 regs [0:15]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component DataMemWrapperRTL Definition -// Full name: DataMemWrapperRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__MemReadType_MemAccessPacket_8_3_128__43c148781d2f2a57__MemWriteType_MemAccessPacket_8_3_128__43c148781d2f2a57__MemResponseType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__global_data_mem_size_128__per_bank_data_mem_size_16__is_combinational_True -// At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py - -module DataMemWrapperRTL__33e0a5b37976e571 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_rd__msg , - output logic [0:0] recv_rd__rdy , - input logic [0:0] recv_rd__val , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_wr__msg , - output logic [0:0] recv_wr__rdy , - input logic [0:0] recv_wr__val , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [4:0] __const__per_bank_data_mem_size_at_request_memory = 5'd16; - logic [6:0] streaming_rd_addr; - MemAccessPacket_8_3_128__43c148781d2f2a57 streaming_rd_read_reqeust; - logic [0:0] streaming_rd_status; - //------------------------------------------------------------- - // Component channel_rd - //------------------------------------------------------------- - - logic [0:0] channel_rd__clk; - logic [0:0] channel_rd__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 channel_rd__recv__msg; - logic [0:0] channel_rd__recv__rdy; - logic [0:0] channel_rd__recv__val; - MemAccessPacket_8_3_128__43c148781d2f2a57 channel_rd__send__msg; - logic [0:0] channel_rd__send__rdy; - logic [0:0] channel_rd__send__val; - - ChannelRTL__c31a2b1c86c6a129 channel_rd - ( - .clk( channel_rd__clk ), - .reset( channel_rd__reset ), - .recv__msg( channel_rd__recv__msg ), - .recv__rdy( channel_rd__recv__rdy ), - .recv__val( channel_rd__recv__val ), - .send__msg( channel_rd__send__msg ), - .send__rdy( channel_rd__send__rdy ), - .send__val( channel_rd__send__val ) - ); - - //------------------------------------------------------------- - // End of component channel_rd - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component channel_wr - //------------------------------------------------------------- - - logic [0:0] channel_wr__clk; - logic [0:0] channel_wr__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 channel_wr__recv__msg; - logic [0:0] channel_wr__recv__rdy; - logic [0:0] channel_wr__recv__val; - MemAccessPacket_8_3_128__43c148781d2f2a57 channel_wr__send__msg; - logic [0:0] channel_wr__send__rdy; - logic [0:0] channel_wr__send__val; - - ChannelRTL__c31a2b1c86c6a129 channel_wr - ( - .clk( channel_wr__clk ), - .reset( channel_wr__reset ), - .recv__msg( channel_wr__recv__msg ), - .recv__rdy( channel_wr__recv__rdy ), - .recv__val( channel_wr__recv__val ), - .send__msg( channel_wr__send__msg ), - .send__rdy( channel_wr__send__rdy ), - .send__val( channel_wr__send__val ) - ); - - //------------------------------------------------------------- - // End of component channel_wr - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component memory - //------------------------------------------------------------- - - logic [0:0] memory__clk; - logic [3:0] memory__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 memory__rdata [0:0]; - logic [0:0] memory__reset; - logic [3:0] memory__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 memory__wdata [0:0]; - logic [0:0] memory__wen [0:0]; - - RegisterFile__bd22936ec5812d0d memory - ( - .clk( memory__clk ), - .raddr( memory__raddr ), - .rdata( memory__rdata ), - .reset( memory__reset ), - .waddr( memory__waddr ), - .wdata( memory__wdata ), - .wen( memory__wen ) - ); - - //------------------------------------------------------------- - // End of component memory - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:76 - // @update - // def compose_send_msg(): - // s.send.msg @= MemResponseType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) - // # TODO: change to pipe's out's wen. - // # Streaming read example: - // # At cycle 0, s.channel_rd issues one single streaming read request (indicated by - // # s.channel_rd.send.msg.streaming_rd = 1) with s.channel_rd.send.msg.addr = 2, - // # s.channel_rd.send.msg.streaming_rd_stride = 2, and s.channel_rd.send.msg.streaming_rd_end_addr = 6. - // # Then s.send will return the multiple response data from addr=2, addr=4, and addr=6 - // # at cycle 0, cycle 1, and cycle 2, respectively. - // if s.streaming_rd_status: - // s.send.msg.src @= s.streaming_rd_read_reqeust.dst - // s.send.msg.dst @= s.streaming_rd_read_reqeust.src - // s.send.msg.addr @= s.streaming_rd_addr - // s.send.msg.data @= s.memory.rdata[0] - // s.send.msg.src_cgra @= s.streaming_rd_read_reqeust.src_cgra - // s.send.msg.src_tile @= s.streaming_rd_read_reqeust.src_tile - // s.send.msg.remote_src_port @= s.streaming_rd_read_reqeust.remote_src_port - // elif s.channel_rd.send.val: - // s.send.msg.src @= s.channel_rd.send.msg.dst - // s.send.msg.dst @= s.channel_rd.send.msg.src - // s.send.msg.addr @= s.channel_rd.send.msg.addr - // s.send.msg.data @= s.memory.rdata[0] - // s.send.msg.src_cgra @= s.channel_rd.send.msg.src_cgra - // s.send.msg.src_tile @= s.channel_rd.send.msg.src_tile - // s.send.msg.remote_src_port @= s.channel_rd.send.msg.remote_src_port - - always_comb begin : compose_send_msg - send__msg = { 2'd0, 3'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; - if ( streaming_rd_status ) begin - send__msg.src = streaming_rd_read_reqeust.dst; - send__msg.dst = streaming_rd_read_reqeust.src; - send__msg.addr = streaming_rd_addr; - send__msg.data = memory__rdata[1'd0]; - send__msg.src_cgra = streaming_rd_read_reqeust.src_cgra; - send__msg.src_tile = streaming_rd_read_reqeust.src_tile; - send__msg.remote_src_port = streaming_rd_read_reqeust.remote_src_port; - end - else if ( channel_rd__send__val ) begin - send__msg.src = channel_rd__send__msg.dst; - send__msg.dst = channel_rd__send__msg.src; - send__msg.addr = channel_rd__send__msg.addr; - send__msg.data = memory__rdata[1'd0]; - send__msg.src_cgra = channel_rd__send__msg.src_cgra; - send__msg.src_tile = channel_rd__send__msg.src_tile; - send__msg.remote_src_port = channel_rd__send__msg.remote_src_port; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:123 - // @update - // def notify_channel_rdy(): - // # TODO: change to SRAM's rdy when replacing register file - // # with SRAM. - // if s.streaming_rd_status: - // # Issue one streaming request at one time. - // s.channel_rd.send.rdy @= 0 - // else: - // s.channel_rd.send.rdy @= s.send.rdy - // s.channel_wr.send.rdy @= 1 - - always_comb begin : notify_channel_rdy - if ( streaming_rd_status ) begin - channel_rd__send__rdy = 1'd0; - end - else - channel_rd__send__rdy = send__rdy; - channel_wr__send__rdy = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:134 - // @update - // def notify_send_val(): - // # TODO: change to SRAM's valid when replacing register file - // # with SRAM. - // if s.streaming_rd_status: - // # Keep sending read data during streaming status. - // s.send.val @= 1 - // else: - // s.send.val @= s.channel_rd.send.val - - always_comb begin : notify_send_val - if ( streaming_rd_status ) begin - send__val = 1'd1; - end - else - send__val = channel_rd__send__val; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:103 - // @update - // def request_memory(): - // # Default values. - // s.memory.wen[0] @= 0 - // s.memory.raddr[0] @= PerBankAddrType(0) - // s.memory.waddr[0] @= PerBankAddrType(0) - // s.memory.wdata[0] @= DataType(0, 0, 0, 0) - // - // if s.streaming_rd_status: - // s.memory.raddr[0] @= \ - // trunc(s.streaming_rd_addr % per_bank_data_mem_size, PerBankAddrType) - // if s.channel_rd.send.val: - // s.memory.raddr[0] @= \ - // trunc(s.channel_rd.send.msg.addr % per_bank_data_mem_size, PerBankAddrType) - // if s.channel_wr.send.val: - // s.memory.waddr[0] @= \ - // trunc(s.channel_wr.send.msg.addr % per_bank_data_mem_size, PerBankAddrType) - // s.memory.wdata[0] @= s.channel_wr.send.msg.data - // s.memory.wen[0] @= 1 - - always_comb begin : request_memory - memory__wen[1'd0] = 1'd0; - memory__raddr[1'd0] = 4'd0; - memory__waddr[1'd0] = 4'd0; - memory__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - if ( streaming_rd_status ) begin - memory__raddr[1'd0] = 4'(streaming_rd_addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); - end - if ( channel_rd__send__val ) begin - memory__raddr[1'd0] = 4'(channel_rd__send__msg.addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); - end - if ( channel_wr__send__val ) begin - memory__waddr[1'd0] = 4'(channel_wr__send__msg.addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); - memory__wdata[1'd0] = channel_wr__send__msg.data; - memory__wen[1'd0] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:63 - // @update_ff - // def update_streaming_rd_regs(): - // if s.channel_rd.send.val & s.channel_rd.send.msg.streaming_rd: - // s.streaming_rd_status <<= 1 - // s.streaming_rd_addr <<= s.channel_rd.send.msg.addr + s.channel_rd.send.msg.streaming_rd_stride - // s.streaming_rd_read_reqeust <<= s.channel_rd.send.msg - // elif s.streaming_rd_addr == s.streaming_rd_read_reqeust.streaming_rd_end_addr: - // s.streaming_rd_status <<= 0 - // s.streaming_rd_addr <<= GlobalAddrType(0) - // s.streaming_rd_read_reqeust <<= MemReadType() - // else: - // s.streaming_rd_addr <<= s.streaming_rd_addr + s.streaming_rd_read_reqeust.streaming_rd_stride - - always_ff @(posedge clk) begin : update_streaming_rd_regs - if ( channel_rd__send__val & channel_rd__send__msg.streaming_rd ) begin - streaming_rd_status <= 1'd1; - streaming_rd_addr <= channel_rd__send__msg.addr + channel_rd__send__msg.streaming_rd_stride; - streaming_rd_read_reqeust <= channel_rd__send__msg; - end - else if ( streaming_rd_addr == streaming_rd_read_reqeust.streaming_rd_end_addr ) begin - streaming_rd_status <= 1'd0; - streaming_rd_addr <= 7'd0; - streaming_rd_read_reqeust <= { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; - end - else - streaming_rd_addr <= streaming_rd_addr + streaming_rd_read_reqeust.streaming_rd_stride; - end - - assign memory__clk = clk; - assign memory__reset = reset; - assign channel_rd__clk = clk; - assign channel_rd__reset = reset; - assign channel_wr__clk = clk; - assign channel_wr__reset = reset; - assign channel_rd__recv__msg = recv_rd__msg; - assign recv_rd__rdy = channel_rd__recv__rdy; - assign channel_rd__recv__val = recv_rd__val; - assign channel_wr__recv__msg = recv_wr__msg; - assign recv_wr__rdy = channel_wr__recv__rdy; - assign channel_wr__recv__val = recv_wr__val; - -endmodule - - -// PyMTL Component Mux Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_2 -( - input logic [0:0] clk , - input MemAccessPacket_8_3_128__43c148781d2f2a57 in_ [0:1], - output MemAccessPacket_8_3_128__43c148781d2f2a57 out , - input logic [0:0] reset , - input logic [0:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__7305dd76cfb05fd9 -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output MemAccessPacket_8_3_128__43c148781d2f2a57 rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input MemAccessPacket_8_3_128__43c148781d2f2a57 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - MemAccessPacket_8_3_128__43c148781d2f2a57 regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component BypassQueueDpathRTL Definition -// Full name: BypassQueueDpathRTL__EntryType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueDpathRTL__4eac613e5285098c -( - input logic [0:0] clk , - input logic [0:0] mux_sel , - input logic [0:0] raddr , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_msg , - input logic [0:0] reset , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - MemAccessPacket_8_3_128__43c148781d2f2a57 mux__in_ [0:1]; - MemAccessPacket_8_3_128__43c148781d2f2a57 mux__out; - logic [0:0] mux__reset; - logic [0:0] mux__sel; - - Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_2 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - MemAccessPacket_8_3_128__43c148781d2f2a57 rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - MemAccessPacket_8_3_128__43c148781d2f2a57 rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__7305dd76cfb05fd9 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - assign mux__clk = clk; - assign mux__reset = reset; - assign mux__sel = mux_sel; - assign mux__in_[0] = rf__rdata[0]; - assign mux__in_[1] = recv_msg; - assign send_msg = mux__out; - -endmodule - - -// PyMTL Component BypassQueueRTL Definition -// Full name: BypassQueueRTL__EntryType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueRTL__4eac613e5285098c -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__mux_sel; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - BypassQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .mux_sel( ctrl__mux_sel ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__mux_sel; - logic [0:0] dpath__raddr; - MemAccessPacket_8_3_128__43c148781d2f2a57 dpath__recv_msg; - logic [0:0] dpath__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - BypassQueueDpathRTL__4eac613e5285098c dpath - ( - .clk( dpath__clk ), - .mux_sel( dpath__mux_sel ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign dpath__mux_sel = ctrl__mux_sel; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign count = ctrl__count; - assign dpath__recv_msg = recv__msg; - assign send__msg = dpath__send_msg; - -endmodule - - -// PyMTL Component InputUnitRTL Definition -// Full name: InputUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_BypassQueueRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py - -module InputUnitRTL__1864e8652261553b -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queue - //------------------------------------------------------------- - - logic [0:0] queue__clk; - logic [1:0] queue__count; - logic [0:0] queue__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 queue__recv__msg; - logic [0:0] queue__recv__rdy; - logic [0:0] queue__recv__val; - MemAccessPacket_8_3_128__43c148781d2f2a57 queue__send__msg; - logic [0:0] queue__send__rdy; - logic [0:0] queue__send__val; - - BypassQueueRTL__4eac613e5285098c queue - ( - .clk( queue__clk ), - .count( queue__count ), - .reset( queue__reset ), - .recv__msg( queue__recv__msg ), - .recv__rdy( queue__recv__rdy ), - .recv__val( queue__recv__val ), - .send__msg( queue__send__msg ), - .send__rdy( queue__send__rdy ), - .send__val( queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component queue - //------------------------------------------------------------- - - assign queue__clk = clk; - assign queue__reset = reset; - assign queue__recv__msg = recv__msg; - assign recv__rdy = queue__recv__rdy; - assign queue__recv__val = recv__val; - assign send__msg = queue__send__msg; - assign queue__send__rdy = send__rdy; - assign send__val = queue__send__val; - -endmodule - - -// PyMTL Component OutputUnitRTL Definition -// Full name: OutputUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_None -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py - -module OutputUnitRTL__a3f8631b75bafad0 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - assign send__msg = recv__msg; - assign recv__rdy = send__rdy; - assign send__val = recv__val; - -endmodule - - -// PyMTL Component XbarRouteUnitRTL Definition -// Full name: XbarRouteUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_outports_3 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py - -module XbarRouteUnitRTL__32c7752a7c15587d -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg [0:2] , - input logic [0:0] send__rdy [0:2] , - output logic [0:0] send__val [0:2] -); - localparam logic [1:0] __const__num_outports_at_up_ru_routing = 2'd3; - logic [1:0] out_dir; - logic [2:0] send_val; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 - // @update - // def up_ru_recv_rdy(): - // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 - - always_comb begin : up_ru_recv_rdy - recv__rdy = send__rdy[out_dir] > 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 - // @update - // def up_ru_routing(): - // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) - // - // for i in range( num_outports ): - // s.send[i].val @= b1(0) - // - // if s.recv.val: - // s.send[ s.out_dir ].val @= b1(1) - - always_comb begin : up_ru_routing - out_dir = recv__msg.dst; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) - send__val[2'(i)] = 1'd0; - if ( recv__val ) begin - send__val[out_dir] = 1'd1; - end - end - - assign send__msg[0] = recv__msg; - assign send_val[0:0] = send__val[0]; - assign send__msg[1] = recv__msg; - assign send_val[1:1] = send__val[1]; - assign send__msg[2] = recv__msg; - assign send_val[2:2] = send__val[2]; - -endmodule - - -// PyMTL Component RegEnRst Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py - -module RegEnRst__Type_Bits8__reset_value_1 -( - input logic [0:0] clk , - input logic [0:0] en , - input logic [7:0] in_ , - output logic [7:0] out , - input logic [0:0] reset -); - localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 - // @update_ff - // def up_regenrst(): - // if s.reset: s.out <<= reset_value - // elif s.en: s.out <<= s.in_ - - always_ff @(posedge clk) begin : up_regenrst - if ( reset ) begin - out <= 8'( __const__reset_value_at_up_regenrst ); - end - else if ( en ) begin - out <= in_; - end - end - -endmodule - - -// PyMTL Component RoundRobinArbiterEn Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py - -module RoundRobinArbiterEn__nreqs_8 -( - input logic [0:0] clk , - input logic [0:0] en , - output logic [7:0] grants , - input logic [7:0] reqs , - input logic [0:0] reset -); - localparam logic [3:0] __const__nreqs_at_comb_reqs_int = 4'd8; - localparam logic [4:0] __const__nreqsX2_at_comb_reqs_int = 5'd16; - localparam logic [3:0] __const__nreqs_at_comb_grants = 4'd8; - localparam logic [3:0] __const__nreqs_at_comb_priority_int = 4'd8; - localparam logic [4:0] __const__nreqsX2_at_comb_priority_int = 5'd16; - localparam logic [4:0] __const__nreqsX2_at_comb_kills = 5'd16; - localparam logic [4:0] __const__nreqsX2_at_comb_grants_int = 5'd16; - logic [15:0] grants_int; - logic [16:0] kills; - logic [0:0] priority_en; - logic [15:0] priority_int; - logic [15:0] reqs_int; - //------------------------------------------------------------- - // Component priority_reg - //------------------------------------------------------------- - - logic [0:0] priority_reg__clk; - logic [0:0] priority_reg__en; - logic [7:0] priority_reg__in_; - logic [7:0] priority_reg__out; - logic [0:0] priority_reg__reset; - - RegEnRst__Type_Bits8__reset_value_1 priority_reg - ( - .clk( priority_reg__clk ), - .en( priority_reg__en ), - .in_( priority_reg__in_ ), - .out( priority_reg__out ), - .reset( priority_reg__reset ) - ); - - //------------------------------------------------------------- - // End of component priority_reg - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 - // @update - // def comb_grants(): - // for i in range( nreqs ): - // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] - - always_comb begin : comb_grants - for ( int unsigned i = 1'd0; i < 4'( __const__nreqs_at_comb_grants ); i += 1'd1 ) - grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 - // @update - // def comb_grants_int(): - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.grants_int[i] @= s.reqs_int[i] - // else: - // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] - - always_comb begin : comb_grants_int - for ( int unsigned i = 1'd0; i < 5'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - grants_int[4'(i)] = reqs_int[4'(i)]; - end - else - grants_int[4'(i)] = ( ~kills[5'(i)] ) & reqs_int[4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 - // @update - // def comb_kills(): - // s.kills[0] @= 1 - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.kills[i+1] @= s.reqs_int[i] - // else: - // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) - - always_comb begin : comb_kills - kills[5'd0] = 1'd1; - for ( int unsigned i = 1'd0; i < 5'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - kills[5'(i) + 5'd1] = reqs_int[4'(i)]; - end - else - kills[5'(i) + 5'd1] = kills[5'(i)] | ( ( ~kills[5'(i)] ) & reqs_int[4'(i)] ); - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 - // @update - // def comb_priority_en(): - // s.priority_en @= ( s.grants != 0 ) & s.en - - always_comb begin : comb_priority_en - priority_en = ( grants != 8'd0 ) & en; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 - // @update - // def comb_priority_int(): - // s.priority_int[ 0:nreqs ] @= s.priority_reg.out - // s.priority_int[nreqs:nreqsX2] @= 0 - - always_comb begin : comb_priority_int - priority_int[4'd7:4'd0] = priority_reg__out; - priority_int[4'd15:4'( __const__nreqs_at_comb_priority_int )] = 8'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 - // @update - // def comb_reqs_int(): - // s.reqs_int [ 0:nreqs ] @= s.reqs - // s.reqs_int [nreqs:nreqsX2] @= s.reqs - - always_comb begin : comb_reqs_int - reqs_int[4'd7:4'd0] = reqs; - reqs_int[4'd15:4'( __const__nreqs_at_comb_reqs_int )] = reqs; - end - - assign priority_reg__clk = clk; - assign priority_reg__reset = reset; - assign priority_reg__en = priority_en; - assign priority_reg__in_[7:1] = grants[6:0]; - assign priority_reg__in_[0:0] = grants[7:7]; - -endmodule - - -// PyMTL Component Encoder Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py - -module Encoder__in_nbits_8__out_nbits_3 -( - input logic [0:0] clk , - input logic [7:0] in_ , - output logic [2:0] out , - input logic [0:0] reset -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 - // @update - // def encode(): - // s.out @= 0 - // for i in range( s.in_nbits ): - // if s.in_[i]: - // s.out @= i - - always_comb begin : encode - out = 3'd0; - for ( int unsigned i = 1'd0; i < 4'd8; i += 1'd1 ) - if ( in_[3'(i)] ) begin - out = 3'(i); - end - end - -endmodule - - -// PyMTL Component Mux Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_8 -( - input logic [0:0] clk , - input MemAccessPacket_8_3_128__43c148781d2f2a57 in_ [0:7], - output MemAccessPacket_8_3_128__43c148781d2f2a57 out , - input logic [0:0] reset , - input logic [2:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component SwitchUnitRTL Definition -// Full name: SwitchUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_inports_8 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py - -module SwitchUnitRTL__10097976fa423359 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg [0:7] , - output logic [0:0] recv__rdy [0:7] , - input logic [0:0] recv__val [0:7] , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [3:0] __const__num_inports_at_up_get_en = 4'd8; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [7:0] arbiter__grants; - logic [7:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_8 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [7:0] encoder__in_; - logic [2:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_8__out_nbits_3 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - MemAccessPacket_8_3_128__43c148781d2f2a57 mux__in_ [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 mux__out; - logic [0:0] mux__reset; - logic [2:0] mux__sel; - - Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_8 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 - // @update - // def up_get_en(): - // for i in range( num_inports ): - // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) - - always_comb begin : up_get_en - for ( int unsigned i = 1'd0; i < 4'( __const__num_inports_at_up_get_en ); i += 1'd1 ) - recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 - // @update - // def up_send_val(): - // s.send.val @= s.arbiter.grants > 0 - - always_comb begin : up_send_val - send__val = arbiter__grants > 8'd0; - end - - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign arbiter__en = 1'd1; - assign mux__clk = clk; - assign mux__reset = reset; - assign send__msg = mux__out; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign encoder__in_ = arbiter__grants; - assign mux__sel = encoder__out; - assign arbiter__reqs[0:0] = recv__val[0]; - assign mux__in_[0] = recv__msg[0]; - assign arbiter__reqs[1:1] = recv__val[1]; - assign mux__in_[1] = recv__msg[1]; - assign arbiter__reqs[2:2] = recv__val[2]; - assign mux__in_[2] = recv__msg[2]; - assign arbiter__reqs[3:3] = recv__val[3]; - assign mux__in_[3] = recv__msg[3]; - assign arbiter__reqs[4:4] = recv__val[4]; - assign mux__in_[4] = recv__msg[4]; - assign arbiter__reqs[5:5] = recv__val[5]; - assign mux__in_[5] = recv__msg[5]; - assign arbiter__reqs[6:6] = recv__val[6]; - assign mux__in_[6] = recv__msg[6]; - assign arbiter__reqs[7:7] = recv__val[7]; - assign mux__in_[7] = recv__msg[7]; - -endmodule - - -// PyMTL Component XbarBypassQueueRTL Definition -// Full name: XbarBypassQueueRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_inports_8__num_outports_3__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarBypassQueueRTL.py - -module XbarBypassQueueRTL__045133ee283ca701 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg [0:7] , - output logic [0:0] recv__rdy [0:7] , - input logic [0:0] recv__val [0:7] , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg [0:2] , - input logic [0:0] send__rdy [0:2] , - output logic [0:0] send__val [0:2] -); - //------------------------------------------------------------- - // Component input_units[0:7] - //------------------------------------------------------------- - - logic [0:0] input_units__clk [0:7]; - logic [0:0] input_units__reset [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 input_units__recv__msg [0:7]; - logic [0:0] input_units__recv__rdy [0:7]; - logic [0:0] input_units__recv__val [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 input_units__send__msg [0:7]; - logic [0:0] input_units__send__rdy [0:7]; - logic [0:0] input_units__send__val [0:7]; - - InputUnitRTL__1864e8652261553b input_units__0 - ( - .clk( input_units__clk[0] ), - .reset( input_units__reset[0] ), - .recv__msg( input_units__recv__msg[0] ), - .recv__rdy( input_units__recv__rdy[0] ), - .recv__val( input_units__recv__val[0] ), - .send__msg( input_units__send__msg[0] ), - .send__rdy( input_units__send__rdy[0] ), - .send__val( input_units__send__val[0] ) - ); - - InputUnitRTL__1864e8652261553b input_units__1 - ( - .clk( input_units__clk[1] ), - .reset( input_units__reset[1] ), - .recv__msg( input_units__recv__msg[1] ), - .recv__rdy( input_units__recv__rdy[1] ), - .recv__val( input_units__recv__val[1] ), - .send__msg( input_units__send__msg[1] ), - .send__rdy( input_units__send__rdy[1] ), - .send__val( input_units__send__val[1] ) - ); - - InputUnitRTL__1864e8652261553b input_units__2 - ( - .clk( input_units__clk[2] ), - .reset( input_units__reset[2] ), - .recv__msg( input_units__recv__msg[2] ), - .recv__rdy( input_units__recv__rdy[2] ), - .recv__val( input_units__recv__val[2] ), - .send__msg( input_units__send__msg[2] ), - .send__rdy( input_units__send__rdy[2] ), - .send__val( input_units__send__val[2] ) - ); - - InputUnitRTL__1864e8652261553b input_units__3 - ( - .clk( input_units__clk[3] ), - .reset( input_units__reset[3] ), - .recv__msg( input_units__recv__msg[3] ), - .recv__rdy( input_units__recv__rdy[3] ), - .recv__val( input_units__recv__val[3] ), - .send__msg( input_units__send__msg[3] ), - .send__rdy( input_units__send__rdy[3] ), - .send__val( input_units__send__val[3] ) - ); - - InputUnitRTL__1864e8652261553b input_units__4 - ( - .clk( input_units__clk[4] ), - .reset( input_units__reset[4] ), - .recv__msg( input_units__recv__msg[4] ), - .recv__rdy( input_units__recv__rdy[4] ), - .recv__val( input_units__recv__val[4] ), - .send__msg( input_units__send__msg[4] ), - .send__rdy( input_units__send__rdy[4] ), - .send__val( input_units__send__val[4] ) - ); - - InputUnitRTL__1864e8652261553b input_units__5 - ( - .clk( input_units__clk[5] ), - .reset( input_units__reset[5] ), - .recv__msg( input_units__recv__msg[5] ), - .recv__rdy( input_units__recv__rdy[5] ), - .recv__val( input_units__recv__val[5] ), - .send__msg( input_units__send__msg[5] ), - .send__rdy( input_units__send__rdy[5] ), - .send__val( input_units__send__val[5] ) - ); - - InputUnitRTL__1864e8652261553b input_units__6 - ( - .clk( input_units__clk[6] ), - .reset( input_units__reset[6] ), - .recv__msg( input_units__recv__msg[6] ), - .recv__rdy( input_units__recv__rdy[6] ), - .recv__val( input_units__recv__val[6] ), - .send__msg( input_units__send__msg[6] ), - .send__rdy( input_units__send__rdy[6] ), - .send__val( input_units__send__val[6] ) - ); - - InputUnitRTL__1864e8652261553b input_units__7 - ( - .clk( input_units__clk[7] ), - .reset( input_units__reset[7] ), - .recv__msg( input_units__recv__msg[7] ), - .recv__rdy( input_units__recv__rdy[7] ), - .recv__val( input_units__recv__val[7] ), - .send__msg( input_units__send__msg[7] ), - .send__rdy( input_units__send__rdy[7] ), - .send__val( input_units__send__val[7] ) - ); - - //------------------------------------------------------------- - // End of component input_units[0:7] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component output_units[0:2] - //------------------------------------------------------------- - - logic [0:0] output_units__clk [0:2]; - logic [0:0] output_units__reset [0:2]; - MemAccessPacket_8_3_128__43c148781d2f2a57 output_units__recv__msg [0:2]; - logic [0:0] output_units__recv__rdy [0:2]; - logic [0:0] output_units__recv__val [0:2]; - MemAccessPacket_8_3_128__43c148781d2f2a57 output_units__send__msg [0:2]; - logic [0:0] output_units__send__rdy [0:2]; - logic [0:0] output_units__send__val [0:2]; - - OutputUnitRTL__a3f8631b75bafad0 output_units__0 - ( - .clk( output_units__clk[0] ), - .reset( output_units__reset[0] ), - .recv__msg( output_units__recv__msg[0] ), - .recv__rdy( output_units__recv__rdy[0] ), - .recv__val( output_units__recv__val[0] ), - .send__msg( output_units__send__msg[0] ), - .send__rdy( output_units__send__rdy[0] ), - .send__val( output_units__send__val[0] ) - ); - - OutputUnitRTL__a3f8631b75bafad0 output_units__1 - ( - .clk( output_units__clk[1] ), - .reset( output_units__reset[1] ), - .recv__msg( output_units__recv__msg[1] ), - .recv__rdy( output_units__recv__rdy[1] ), - .recv__val( output_units__recv__val[1] ), - .send__msg( output_units__send__msg[1] ), - .send__rdy( output_units__send__rdy[1] ), - .send__val( output_units__send__val[1] ) - ); - - OutputUnitRTL__a3f8631b75bafad0 output_units__2 - ( - .clk( output_units__clk[2] ), - .reset( output_units__reset[2] ), - .recv__msg( output_units__recv__msg[2] ), - .recv__rdy( output_units__recv__rdy[2] ), - .recv__val( output_units__recv__val[2] ), - .send__msg( output_units__send__msg[2] ), - .send__rdy( output_units__send__rdy[2] ), - .send__val( output_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component output_units[0:2] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component route_units[0:7] - //------------------------------------------------------------- - - logic [0:0] route_units__clk [0:7]; - logic [0:0] route_units__reset [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 route_units__recv__msg [0:7]; - logic [0:0] route_units__recv__rdy [0:7]; - logic [0:0] route_units__recv__val [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 route_units__send__msg [0:7][0:2]; - logic [0:0] route_units__send__rdy [0:7][0:2]; - logic [0:0] route_units__send__val [0:7][0:2]; - - XbarRouteUnitRTL__32c7752a7c15587d route_units__0 - ( - .clk( route_units__clk[0] ), - .reset( route_units__reset[0] ), - .recv__msg( route_units__recv__msg[0] ), - .recv__rdy( route_units__recv__rdy[0] ), - .recv__val( route_units__recv__val[0] ), - .send__msg( route_units__send__msg[0] ), - .send__rdy( route_units__send__rdy[0] ), - .send__val( route_units__send__val[0] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__1 - ( - .clk( route_units__clk[1] ), - .reset( route_units__reset[1] ), - .recv__msg( route_units__recv__msg[1] ), - .recv__rdy( route_units__recv__rdy[1] ), - .recv__val( route_units__recv__val[1] ), - .send__msg( route_units__send__msg[1] ), - .send__rdy( route_units__send__rdy[1] ), - .send__val( route_units__send__val[1] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__2 - ( - .clk( route_units__clk[2] ), - .reset( route_units__reset[2] ), - .recv__msg( route_units__recv__msg[2] ), - .recv__rdy( route_units__recv__rdy[2] ), - .recv__val( route_units__recv__val[2] ), - .send__msg( route_units__send__msg[2] ), - .send__rdy( route_units__send__rdy[2] ), - .send__val( route_units__send__val[2] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__3 - ( - .clk( route_units__clk[3] ), - .reset( route_units__reset[3] ), - .recv__msg( route_units__recv__msg[3] ), - .recv__rdy( route_units__recv__rdy[3] ), - .recv__val( route_units__recv__val[3] ), - .send__msg( route_units__send__msg[3] ), - .send__rdy( route_units__send__rdy[3] ), - .send__val( route_units__send__val[3] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__4 - ( - .clk( route_units__clk[4] ), - .reset( route_units__reset[4] ), - .recv__msg( route_units__recv__msg[4] ), - .recv__rdy( route_units__recv__rdy[4] ), - .recv__val( route_units__recv__val[4] ), - .send__msg( route_units__send__msg[4] ), - .send__rdy( route_units__send__rdy[4] ), - .send__val( route_units__send__val[4] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__5 - ( - .clk( route_units__clk[5] ), - .reset( route_units__reset[5] ), - .recv__msg( route_units__recv__msg[5] ), - .recv__rdy( route_units__recv__rdy[5] ), - .recv__val( route_units__recv__val[5] ), - .send__msg( route_units__send__msg[5] ), - .send__rdy( route_units__send__rdy[5] ), - .send__val( route_units__send__val[5] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__6 - ( - .clk( route_units__clk[6] ), - .reset( route_units__reset[6] ), - .recv__msg( route_units__recv__msg[6] ), - .recv__rdy( route_units__recv__rdy[6] ), - .recv__val( route_units__recv__val[6] ), - .send__msg( route_units__send__msg[6] ), - .send__rdy( route_units__send__rdy[6] ), - .send__val( route_units__send__val[6] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__7 - ( - .clk( route_units__clk[7] ), - .reset( route_units__reset[7] ), - .recv__msg( route_units__recv__msg[7] ), - .recv__rdy( route_units__recv__rdy[7] ), - .recv__val( route_units__recv__val[7] ), - .send__msg( route_units__send__msg[7] ), - .send__rdy( route_units__send__rdy[7] ), - .send__val( route_units__send__val[7] ) - ); - - //------------------------------------------------------------- - // End of component route_units[0:7] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component switch_units[0:2] - //------------------------------------------------------------- - - logic [0:0] switch_units__clk [0:2]; - logic [0:0] switch_units__reset [0:2]; - MemAccessPacket_8_3_128__43c148781d2f2a57 switch_units__recv__msg [0:2][0:7]; - logic [0:0] switch_units__recv__rdy [0:2][0:7]; - logic [0:0] switch_units__recv__val [0:2][0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 switch_units__send__msg [0:2]; - logic [0:0] switch_units__send__rdy [0:2]; - logic [0:0] switch_units__send__val [0:2]; - - SwitchUnitRTL__10097976fa423359 switch_units__0 - ( - .clk( switch_units__clk[0] ), - .reset( switch_units__reset[0] ), - .recv__msg( switch_units__recv__msg[0] ), - .recv__rdy( switch_units__recv__rdy[0] ), - .recv__val( switch_units__recv__val[0] ), - .send__msg( switch_units__send__msg[0] ), - .send__rdy( switch_units__send__rdy[0] ), - .send__val( switch_units__send__val[0] ) - ); - - SwitchUnitRTL__10097976fa423359 switch_units__1 - ( - .clk( switch_units__clk[1] ), - .reset( switch_units__reset[1] ), - .recv__msg( switch_units__recv__msg[1] ), - .recv__rdy( switch_units__recv__rdy[1] ), - .recv__val( switch_units__recv__val[1] ), - .send__msg( switch_units__send__msg[1] ), - .send__rdy( switch_units__send__rdy[1] ), - .send__val( switch_units__send__val[1] ) - ); - - SwitchUnitRTL__10097976fa423359 switch_units__2 - ( - .clk( switch_units__clk[2] ), - .reset( switch_units__reset[2] ), - .recv__msg( switch_units__recv__msg[2] ), - .recv__rdy( switch_units__recv__rdy[2] ), - .recv__val( switch_units__recv__val[2] ), - .send__msg( switch_units__send__msg[2] ), - .send__rdy( switch_units__send__rdy[2] ), - .send__val( switch_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component switch_units[0:2] - //------------------------------------------------------------- - - assign input_units__clk[0] = clk; - assign input_units__reset[0] = reset; - assign input_units__clk[1] = clk; - assign input_units__reset[1] = reset; - assign input_units__clk[2] = clk; - assign input_units__reset[2] = reset; - assign input_units__clk[3] = clk; - assign input_units__reset[3] = reset; - assign input_units__clk[4] = clk; - assign input_units__reset[4] = reset; - assign input_units__clk[5] = clk; - assign input_units__reset[5] = reset; - assign input_units__clk[6] = clk; - assign input_units__reset[6] = reset; - assign input_units__clk[7] = clk; - assign input_units__reset[7] = reset; - assign route_units__clk[0] = clk; - assign route_units__reset[0] = reset; - assign route_units__clk[1] = clk; - assign route_units__reset[1] = reset; - assign route_units__clk[2] = clk; - assign route_units__reset[2] = reset; - assign route_units__clk[3] = clk; - assign route_units__reset[3] = reset; - assign route_units__clk[4] = clk; - assign route_units__reset[4] = reset; - assign route_units__clk[5] = clk; - assign route_units__reset[5] = reset; - assign route_units__clk[6] = clk; - assign route_units__reset[6] = reset; - assign route_units__clk[7] = clk; - assign route_units__reset[7] = reset; - assign switch_units__clk[0] = clk; - assign switch_units__reset[0] = reset; - assign switch_units__clk[1] = clk; - assign switch_units__reset[1] = reset; - assign switch_units__clk[2] = clk; - assign switch_units__reset[2] = reset; - assign output_units__clk[0] = clk; - assign output_units__reset[0] = reset; - assign output_units__clk[1] = clk; - assign output_units__reset[1] = reset; - assign output_units__clk[2] = clk; - assign output_units__reset[2] = reset; - assign input_units__recv__msg[0] = recv__msg[0]; - assign recv__rdy[0] = input_units__recv__rdy[0]; - assign input_units__recv__val[0] = recv__val[0]; - assign route_units__recv__msg[0] = input_units__send__msg[0]; - assign input_units__send__rdy[0] = route_units__recv__rdy[0]; - assign route_units__recv__val[0] = input_units__send__val[0]; - assign input_units__recv__msg[1] = recv__msg[1]; - assign recv__rdy[1] = input_units__recv__rdy[1]; - assign input_units__recv__val[1] = recv__val[1]; - assign route_units__recv__msg[1] = input_units__send__msg[1]; - assign input_units__send__rdy[1] = route_units__recv__rdy[1]; - assign route_units__recv__val[1] = input_units__send__val[1]; - assign input_units__recv__msg[2] = recv__msg[2]; - assign recv__rdy[2] = input_units__recv__rdy[2]; - assign input_units__recv__val[2] = recv__val[2]; - assign route_units__recv__msg[2] = input_units__send__msg[2]; - assign input_units__send__rdy[2] = route_units__recv__rdy[2]; - assign route_units__recv__val[2] = input_units__send__val[2]; - assign input_units__recv__msg[3] = recv__msg[3]; - assign recv__rdy[3] = input_units__recv__rdy[3]; - assign input_units__recv__val[3] = recv__val[3]; - assign route_units__recv__msg[3] = input_units__send__msg[3]; - assign input_units__send__rdy[3] = route_units__recv__rdy[3]; - assign route_units__recv__val[3] = input_units__send__val[3]; - assign input_units__recv__msg[4] = recv__msg[4]; - assign recv__rdy[4] = input_units__recv__rdy[4]; - assign input_units__recv__val[4] = recv__val[4]; - assign route_units__recv__msg[4] = input_units__send__msg[4]; - assign input_units__send__rdy[4] = route_units__recv__rdy[4]; - assign route_units__recv__val[4] = input_units__send__val[4]; - assign input_units__recv__msg[5] = recv__msg[5]; - assign recv__rdy[5] = input_units__recv__rdy[5]; - assign input_units__recv__val[5] = recv__val[5]; - assign route_units__recv__msg[5] = input_units__send__msg[5]; - assign input_units__send__rdy[5] = route_units__recv__rdy[5]; - assign route_units__recv__val[5] = input_units__send__val[5]; - assign input_units__recv__msg[6] = recv__msg[6]; - assign recv__rdy[6] = input_units__recv__rdy[6]; - assign input_units__recv__val[6] = recv__val[6]; - assign route_units__recv__msg[6] = input_units__send__msg[6]; - assign input_units__send__rdy[6] = route_units__recv__rdy[6]; - assign route_units__recv__val[6] = input_units__send__val[6]; - assign input_units__recv__msg[7] = recv__msg[7]; - assign recv__rdy[7] = input_units__recv__rdy[7]; - assign input_units__recv__val[7] = recv__val[7]; - assign route_units__recv__msg[7] = input_units__send__msg[7]; - assign input_units__send__rdy[7] = route_units__recv__rdy[7]; - assign route_units__recv__val[7] = input_units__send__val[7]; - assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; - assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; - assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; - assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; - assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; - assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; - assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; - assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; - assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; - assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; - assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; - assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; - assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; - assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; - assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; - assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; - assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; - assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; - assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; - assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; - assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; - assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; - assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; - assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; - assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; - assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; - assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; - assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; - assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; - assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; - assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; - assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; - assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; - assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; - assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; - assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; - assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; - assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; - assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; - assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; - assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; - assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; - assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; - assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; - assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; - assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; - assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; - assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; - assign switch_units__recv__msg[1][5] = route_units__send__msg[5][1]; - assign route_units__send__rdy[5][1] = switch_units__recv__rdy[1][5]; - assign switch_units__recv__val[1][5] = route_units__send__val[5][1]; - assign switch_units__recv__msg[2][5] = route_units__send__msg[5][2]; - assign route_units__send__rdy[5][2] = switch_units__recv__rdy[2][5]; - assign switch_units__recv__val[2][5] = route_units__send__val[5][2]; - assign switch_units__recv__msg[0][6] = route_units__send__msg[6][0]; - assign route_units__send__rdy[6][0] = switch_units__recv__rdy[0][6]; - assign switch_units__recv__val[0][6] = route_units__send__val[6][0]; - assign switch_units__recv__msg[1][6] = route_units__send__msg[6][1]; - assign route_units__send__rdy[6][1] = switch_units__recv__rdy[1][6]; - assign switch_units__recv__val[1][6] = route_units__send__val[6][1]; - assign switch_units__recv__msg[2][6] = route_units__send__msg[6][2]; - assign route_units__send__rdy[6][2] = switch_units__recv__rdy[2][6]; - assign switch_units__recv__val[2][6] = route_units__send__val[6][2]; - assign switch_units__recv__msg[0][7] = route_units__send__msg[7][0]; - assign route_units__send__rdy[7][0] = switch_units__recv__rdy[0][7]; - assign switch_units__recv__val[0][7] = route_units__send__val[7][0]; - assign switch_units__recv__msg[1][7] = route_units__send__msg[7][1]; - assign route_units__send__rdy[7][1] = switch_units__recv__rdy[1][7]; - assign switch_units__recv__val[1][7] = route_units__send__val[7][1]; - assign switch_units__recv__msg[2][7] = route_units__send__msg[7][2]; - assign route_units__send__rdy[7][2] = switch_units__recv__rdy[2][7]; - assign switch_units__recv__val[2][7] = route_units__send__val[7][2]; - assign output_units__recv__msg[0] = switch_units__send__msg[0]; - assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; - assign output_units__recv__val[0] = switch_units__send__val[0]; - assign send__msg[0] = output_units__send__msg[0]; - assign output_units__send__rdy[0] = send__rdy[0]; - assign send__val[0] = output_units__send__val[0]; - assign output_units__recv__msg[1] = switch_units__send__msg[1]; - assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; - assign output_units__recv__val[1] = switch_units__send__val[1]; - assign send__msg[1] = output_units__send__msg[1]; - assign output_units__send__rdy[1] = send__rdy[1]; - assign send__val[1] = output_units__send__val[1]; - assign output_units__recv__msg[2] = switch_units__send__msg[2]; - assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; - assign output_units__recv__val[2] = switch_units__send__val[2]; - assign send__msg[2] = output_units__send__msg[2]; - assign output_units__send__rdy[2] = send__rdy[2]; - assign send__val[2] = output_units__send__val[2]; - -endmodule - - -// PyMTL Component Mux Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_2 -( - input logic [0:0] clk , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 in_ [0:1], - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 out , - input logic [0:0] reset , - input logic [0:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__3969b2773d1d2f8e -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component BypassQueueDpathRTL Definition -// Full name: BypassQueueDpathRTL__EntryType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueDpathRTL__60d0395b9f70f062 -( - input logic [0:0] clk , - input logic [0:0] mux_sel , - input logic [0:0] raddr , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv_msg , - input logic [0:0] reset , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__in_ [0:1]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__out; - logic [0:0] mux__reset; - logic [0:0] mux__sel; - - Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_2 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__3969b2773d1d2f8e rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - assign mux__clk = clk; - assign mux__reset = reset; - assign mux__sel = mux_sel; - assign mux__in_[0] = rf__rdata[0]; - assign mux__in_[1] = recv_msg; - assign send_msg = mux__out; - -endmodule - - -// PyMTL Component BypassQueueRTL Definition -// Full name: BypassQueueRTL__EntryType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueRTL__60d0395b9f70f062 -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__mux_sel; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - BypassQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .mux_sel( ctrl__mux_sel ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__mux_sel; - logic [0:0] dpath__raddr; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 dpath__recv_msg; - logic [0:0] dpath__reset; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - BypassQueueDpathRTL__60d0395b9f70f062 dpath - ( - .clk( dpath__clk ), - .mux_sel( dpath__mux_sel ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign dpath__mux_sel = ctrl__mux_sel; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign count = ctrl__count; - assign dpath__recv_msg = recv__msg; - assign send__msg = dpath__send_msg; - -endmodule - - -// PyMTL Component InputUnitRTL Definition -// Full name: InputUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__QueueType_BypassQueueRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py - -module InputUnitRTL__cff279ef5009e7c6 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queue - //------------------------------------------------------------- - - logic [0:0] queue__clk; - logic [1:0] queue__count; - logic [0:0] queue__reset; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 queue__recv__msg; - logic [0:0] queue__recv__rdy; - logic [0:0] queue__recv__val; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 queue__send__msg; - logic [0:0] queue__send__rdy; - logic [0:0] queue__send__val; - - BypassQueueRTL__60d0395b9f70f062 queue - ( - .clk( queue__clk ), - .count( queue__count ), - .reset( queue__reset ), - .recv__msg( queue__recv__msg ), - .recv__rdy( queue__recv__rdy ), - .recv__val( queue__recv__val ), - .send__msg( queue__send__msg ), - .send__rdy( queue__send__rdy ), - .send__val( queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component queue - //------------------------------------------------------------- - - assign queue__clk = clk; - assign queue__reset = reset; - assign queue__recv__msg = recv__msg; - assign recv__rdy = queue__recv__rdy; - assign queue__recv__val = recv__val; - assign send__msg = queue__send__msg; - assign queue__send__rdy = send__rdy; - assign send__val = queue__send__val; - -endmodule - - -// PyMTL Component OutputUnitRTL Definition -// Full name: OutputUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__QueueType_None -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py - -module OutputUnitRTL__e96d78a3d0126314 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - assign send__msg = recv__msg; - assign recv__rdy = send__rdy; - assign send__val = recv__val; - -endmodule - - -// PyMTL Component XbarRouteUnitRTL Definition -// Full name: XbarRouteUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_outports_8 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py - -module XbarRouteUnitRTL__c063f4910bbc0b50 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg [0:7] , - input logic [0:0] send__rdy [0:7] , - output logic [0:0] send__val [0:7] -); - localparam logic [3:0] __const__num_outports_at_up_ru_routing = 4'd8; - logic [2:0] out_dir; - logic [7:0] send_val; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 - // @update - // def up_ru_recv_rdy(): - // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 - - always_comb begin : up_ru_recv_rdy - recv__rdy = send__rdy[out_dir] > 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 - // @update - // def up_ru_routing(): - // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) - // - // for i in range( num_outports ): - // s.send[i].val @= b1(0) - // - // if s.recv.val: - // s.send[ s.out_dir ].val @= b1(1) - - always_comb begin : up_ru_routing - out_dir = recv__msg.dst; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) - send__val[3'(i)] = 1'd0; - if ( recv__val ) begin - send__val[out_dir] = 1'd1; - end - end - - assign send__msg[0] = recv__msg; - assign send_val[0:0] = send__val[0]; - assign send__msg[1] = recv__msg; - assign send_val[1:1] = send__val[1]; - assign send__msg[2] = recv__msg; - assign send_val[2:2] = send__val[2]; - assign send__msg[3] = recv__msg; - assign send_val[3:3] = send__val[3]; - assign send__msg[4] = recv__msg; - assign send_val[4:4] = send__val[4]; - assign send__msg[5] = recv__msg; - assign send_val[5:5] = send__val[5]; - assign send__msg[6] = recv__msg; - assign send_val[6:6] = send__val[6]; - assign send__msg[7] = recv__msg; - assign send_val[7:7] = send__val[7]; - -endmodule - - -// PyMTL Component RegEnRst Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py - -module RegEnRst__Type_Bits3__reset_value_1 -( - input logic [0:0] clk , - input logic [0:0] en , - input logic [2:0] in_ , - output logic [2:0] out , - input logic [0:0] reset -); - localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 - // @update_ff - // def up_regenrst(): - // if s.reset: s.out <<= reset_value - // elif s.en: s.out <<= s.in_ - - always_ff @(posedge clk) begin : up_regenrst - if ( reset ) begin - out <= 3'( __const__reset_value_at_up_regenrst ); - end - else if ( en ) begin - out <= in_; - end - end - -endmodule - - -// PyMTL Component RoundRobinArbiterEn Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py - -module RoundRobinArbiterEn__nreqs_3 -( - input logic [0:0] clk , - input logic [0:0] en , - output logic [2:0] grants , - input logic [2:0] reqs , - input logic [0:0] reset -); - localparam logic [1:0] __const__nreqs_at_comb_reqs_int = 2'd3; - localparam logic [2:0] __const__nreqsX2_at_comb_reqs_int = 3'd6; - localparam logic [1:0] __const__nreqs_at_comb_grants = 2'd3; - localparam logic [1:0] __const__nreqs_at_comb_priority_int = 2'd3; - localparam logic [2:0] __const__nreqsX2_at_comb_priority_int = 3'd6; - localparam logic [2:0] __const__nreqsX2_at_comb_kills = 3'd6; - localparam logic [2:0] __const__nreqsX2_at_comb_grants_int = 3'd6; - logic [5:0] grants_int; - logic [6:0] kills; - logic [0:0] priority_en; - logic [5:0] priority_int; - logic [5:0] reqs_int; - //------------------------------------------------------------- - // Component priority_reg - //------------------------------------------------------------- - - logic [0:0] priority_reg__clk; - logic [0:0] priority_reg__en; - logic [2:0] priority_reg__in_; - logic [2:0] priority_reg__out; - logic [0:0] priority_reg__reset; - - RegEnRst__Type_Bits3__reset_value_1 priority_reg - ( - .clk( priority_reg__clk ), - .en( priority_reg__en ), - .in_( priority_reg__in_ ), - .out( priority_reg__out ), - .reset( priority_reg__reset ) - ); - - //------------------------------------------------------------- - // End of component priority_reg - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 - // @update - // def comb_grants(): - // for i in range( nreqs ): - // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] - - always_comb begin : comb_grants - for ( int unsigned i = 1'd0; i < 2'( __const__nreqs_at_comb_grants ); i += 1'd1 ) - grants[2'(i)] = grants_int[3'(i)] | grants_int[3'( __const__nreqs_at_comb_grants ) + 3'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 - // @update - // def comb_grants_int(): - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.grants_int[i] @= s.reqs_int[i] - // else: - // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] - - always_comb begin : comb_grants_int - for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) - if ( priority_int[3'(i)] ) begin - grants_int[3'(i)] = reqs_int[3'(i)]; - end - else - grants_int[3'(i)] = ( ~kills[3'(i)] ) & reqs_int[3'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 - // @update - // def comb_kills(): - // s.kills[0] @= 1 - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.kills[i+1] @= s.reqs_int[i] - // else: - // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) - - always_comb begin : comb_kills - kills[3'd0] = 1'd1; - for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) - if ( priority_int[3'(i)] ) begin - kills[3'(i) + 3'd1] = reqs_int[3'(i)]; - end - else - kills[3'(i) + 3'd1] = kills[3'(i)] | ( ( ~kills[3'(i)] ) & reqs_int[3'(i)] ); - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 - // @update - // def comb_priority_en(): - // s.priority_en @= ( s.grants != 0 ) & s.en - - always_comb begin : comb_priority_en - priority_en = ( grants != 3'd0 ) & en; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 - // @update - // def comb_priority_int(): - // s.priority_int[ 0:nreqs ] @= s.priority_reg.out - // s.priority_int[nreqs:nreqsX2] @= 0 - - always_comb begin : comb_priority_int - priority_int[3'd2:3'd0] = priority_reg__out; - priority_int[3'd5:3'( __const__nreqs_at_comb_priority_int )] = 3'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 - // @update - // def comb_reqs_int(): - // s.reqs_int [ 0:nreqs ] @= s.reqs - // s.reqs_int [nreqs:nreqsX2] @= s.reqs - - always_comb begin : comb_reqs_int - reqs_int[3'd2:3'd0] = reqs; - reqs_int[3'd5:3'( __const__nreqs_at_comb_reqs_int )] = reqs; - end - - assign priority_reg__clk = clk; - assign priority_reg__reset = reset; - assign priority_reg__en = priority_en; - assign priority_reg__in_[2:1] = grants[1:0]; - assign priority_reg__in_[0:0] = grants[2:2]; - -endmodule - - -// PyMTL Component Encoder Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py - -module Encoder__in_nbits_3__out_nbits_2 -( - input logic [0:0] clk , - input logic [2:0] in_ , - output logic [1:0] out , - input logic [0:0] reset -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 - // @update - // def encode(): - // s.out @= 0 - // for i in range( s.in_nbits ): - // if s.in_[i]: - // s.out @= i - - always_comb begin : encode - out = 2'd0; - for ( int unsigned i = 1'd0; i < 2'd3; i += 1'd1 ) - if ( in_[2'(i)] ) begin - out = 2'(i); - end - end - -endmodule - - -// PyMTL Component Mux Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_3 -( - input logic [0:0] clk , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 in_ [0:2], - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 out , - input logic [0:0] reset , - input logic [1:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component SwitchUnitRTL Definition -// Full name: SwitchUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_inports_3 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py - -module SwitchUnitRTL__4cc70db240bb572a -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg [0:2] , - output logic [0:0] recv__rdy [0:2] , - input logic [0:0] recv__val [0:2] , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [1:0] __const__num_inports_at_up_get_en = 2'd3; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [2:0] arbiter__grants; - logic [2:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_3 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [2:0] encoder__in_; - logic [1:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_3__out_nbits_2 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__in_ [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__out; - logic [0:0] mux__reset; - logic [1:0] mux__sel; - - Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_3 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 - // @update - // def up_get_en(): - // for i in range( num_inports ): - // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) - - always_comb begin : up_get_en - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_up_get_en ); i += 1'd1 ) - recv__rdy[2'(i)] = send__rdy & ( mux__sel == 2'(i) ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 - // @update - // def up_send_val(): - // s.send.val @= s.arbiter.grants > 0 - - always_comb begin : up_send_val - send__val = arbiter__grants > 3'd0; - end - - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign arbiter__en = 1'd1; - assign mux__clk = clk; - assign mux__reset = reset; - assign send__msg = mux__out; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign encoder__in_ = arbiter__grants; - assign mux__sel = encoder__out; - assign arbiter__reqs[0:0] = recv__val[0]; - assign mux__in_[0] = recv__msg[0]; - assign arbiter__reqs[1:1] = recv__val[1]; - assign mux__in_[1] = recv__msg[1]; - assign arbiter__reqs[2:2] = recv__val[2]; - assign mux__in_[2] = recv__msg[2]; - -endmodule - - -// PyMTL Component XbarBypassQueueRTL Definition -// Full name: XbarBypassQueueRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_inports_3__num_outports_8__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarBypassQueueRTL.py - -module XbarBypassQueueRTL__510da12df6787984 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg [0:2] , - output logic [0:0] recv__rdy [0:2] , - input logic [0:0] recv__val [0:2] , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg [0:7] , - input logic [0:0] send__rdy [0:7] , - output logic [0:0] send__val [0:7] -); - //------------------------------------------------------------- - // Component input_units[0:2] - //------------------------------------------------------------- - - logic [0:0] input_units__clk [0:2]; - logic [0:0] input_units__reset [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 input_units__recv__msg [0:2]; - logic [0:0] input_units__recv__rdy [0:2]; - logic [0:0] input_units__recv__val [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 input_units__send__msg [0:2]; - logic [0:0] input_units__send__rdy [0:2]; - logic [0:0] input_units__send__val [0:2]; - - InputUnitRTL__cff279ef5009e7c6 input_units__0 - ( - .clk( input_units__clk[0] ), - .reset( input_units__reset[0] ), - .recv__msg( input_units__recv__msg[0] ), - .recv__rdy( input_units__recv__rdy[0] ), - .recv__val( input_units__recv__val[0] ), - .send__msg( input_units__send__msg[0] ), - .send__rdy( input_units__send__rdy[0] ), - .send__val( input_units__send__val[0] ) - ); - - InputUnitRTL__cff279ef5009e7c6 input_units__1 - ( - .clk( input_units__clk[1] ), - .reset( input_units__reset[1] ), - .recv__msg( input_units__recv__msg[1] ), - .recv__rdy( input_units__recv__rdy[1] ), - .recv__val( input_units__recv__val[1] ), - .send__msg( input_units__send__msg[1] ), - .send__rdy( input_units__send__rdy[1] ), - .send__val( input_units__send__val[1] ) - ); - - InputUnitRTL__cff279ef5009e7c6 input_units__2 - ( - .clk( input_units__clk[2] ), - .reset( input_units__reset[2] ), - .recv__msg( input_units__recv__msg[2] ), - .recv__rdy( input_units__recv__rdy[2] ), - .recv__val( input_units__recv__val[2] ), - .send__msg( input_units__send__msg[2] ), - .send__rdy( input_units__send__rdy[2] ), - .send__val( input_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component input_units[0:2] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component output_units[0:7] - //------------------------------------------------------------- - - logic [0:0] output_units__clk [0:7]; - logic [0:0] output_units__reset [0:7]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 output_units__recv__msg [0:7]; - logic [0:0] output_units__recv__rdy [0:7]; - logic [0:0] output_units__recv__val [0:7]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 output_units__send__msg [0:7]; - logic [0:0] output_units__send__rdy [0:7]; - logic [0:0] output_units__send__val [0:7]; - - OutputUnitRTL__e96d78a3d0126314 output_units__0 - ( - .clk( output_units__clk[0] ), - .reset( output_units__reset[0] ), - .recv__msg( output_units__recv__msg[0] ), - .recv__rdy( output_units__recv__rdy[0] ), - .recv__val( output_units__recv__val[0] ), - .send__msg( output_units__send__msg[0] ), - .send__rdy( output_units__send__rdy[0] ), - .send__val( output_units__send__val[0] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__1 - ( - .clk( output_units__clk[1] ), - .reset( output_units__reset[1] ), - .recv__msg( output_units__recv__msg[1] ), - .recv__rdy( output_units__recv__rdy[1] ), - .recv__val( output_units__recv__val[1] ), - .send__msg( output_units__send__msg[1] ), - .send__rdy( output_units__send__rdy[1] ), - .send__val( output_units__send__val[1] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__2 - ( - .clk( output_units__clk[2] ), - .reset( output_units__reset[2] ), - .recv__msg( output_units__recv__msg[2] ), - .recv__rdy( output_units__recv__rdy[2] ), - .recv__val( output_units__recv__val[2] ), - .send__msg( output_units__send__msg[2] ), - .send__rdy( output_units__send__rdy[2] ), - .send__val( output_units__send__val[2] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__3 - ( - .clk( output_units__clk[3] ), - .reset( output_units__reset[3] ), - .recv__msg( output_units__recv__msg[3] ), - .recv__rdy( output_units__recv__rdy[3] ), - .recv__val( output_units__recv__val[3] ), - .send__msg( output_units__send__msg[3] ), - .send__rdy( output_units__send__rdy[3] ), - .send__val( output_units__send__val[3] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__4 - ( - .clk( output_units__clk[4] ), - .reset( output_units__reset[4] ), - .recv__msg( output_units__recv__msg[4] ), - .recv__rdy( output_units__recv__rdy[4] ), - .recv__val( output_units__recv__val[4] ), - .send__msg( output_units__send__msg[4] ), - .send__rdy( output_units__send__rdy[4] ), - .send__val( output_units__send__val[4] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__5 - ( - .clk( output_units__clk[5] ), - .reset( output_units__reset[5] ), - .recv__msg( output_units__recv__msg[5] ), - .recv__rdy( output_units__recv__rdy[5] ), - .recv__val( output_units__recv__val[5] ), - .send__msg( output_units__send__msg[5] ), - .send__rdy( output_units__send__rdy[5] ), - .send__val( output_units__send__val[5] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__6 - ( - .clk( output_units__clk[6] ), - .reset( output_units__reset[6] ), - .recv__msg( output_units__recv__msg[6] ), - .recv__rdy( output_units__recv__rdy[6] ), - .recv__val( output_units__recv__val[6] ), - .send__msg( output_units__send__msg[6] ), - .send__rdy( output_units__send__rdy[6] ), - .send__val( output_units__send__val[6] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__7 - ( - .clk( output_units__clk[7] ), - .reset( output_units__reset[7] ), - .recv__msg( output_units__recv__msg[7] ), - .recv__rdy( output_units__recv__rdy[7] ), - .recv__val( output_units__recv__val[7] ), - .send__msg( output_units__send__msg[7] ), - .send__rdy( output_units__send__rdy[7] ), - .send__val( output_units__send__val[7] ) - ); - - //------------------------------------------------------------- - // End of component output_units[0:7] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component route_units[0:2] - //------------------------------------------------------------- - - logic [0:0] route_units__clk [0:2]; - logic [0:0] route_units__reset [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 route_units__recv__msg [0:2]; - logic [0:0] route_units__recv__rdy [0:2]; - logic [0:0] route_units__recv__val [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 route_units__send__msg [0:2][0:7]; - logic [0:0] route_units__send__rdy [0:2][0:7]; - logic [0:0] route_units__send__val [0:2][0:7]; - - XbarRouteUnitRTL__c063f4910bbc0b50 route_units__0 - ( - .clk( route_units__clk[0] ), - .reset( route_units__reset[0] ), - .recv__msg( route_units__recv__msg[0] ), - .recv__rdy( route_units__recv__rdy[0] ), - .recv__val( route_units__recv__val[0] ), - .send__msg( route_units__send__msg[0] ), - .send__rdy( route_units__send__rdy[0] ), - .send__val( route_units__send__val[0] ) - ); - - XbarRouteUnitRTL__c063f4910bbc0b50 route_units__1 - ( - .clk( route_units__clk[1] ), - .reset( route_units__reset[1] ), - .recv__msg( route_units__recv__msg[1] ), - .recv__rdy( route_units__recv__rdy[1] ), - .recv__val( route_units__recv__val[1] ), - .send__msg( route_units__send__msg[1] ), - .send__rdy( route_units__send__rdy[1] ), - .send__val( route_units__send__val[1] ) - ); - - XbarRouteUnitRTL__c063f4910bbc0b50 route_units__2 - ( - .clk( route_units__clk[2] ), - .reset( route_units__reset[2] ), - .recv__msg( route_units__recv__msg[2] ), - .recv__rdy( route_units__recv__rdy[2] ), - .recv__val( route_units__recv__val[2] ), - .send__msg( route_units__send__msg[2] ), - .send__rdy( route_units__send__rdy[2] ), - .send__val( route_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component route_units[0:2] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component switch_units[0:7] - //------------------------------------------------------------- - - logic [0:0] switch_units__clk [0:7]; - logic [0:0] switch_units__reset [0:7]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 switch_units__recv__msg [0:7][0:2]; - logic [0:0] switch_units__recv__rdy [0:7][0:2]; - logic [0:0] switch_units__recv__val [0:7][0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 switch_units__send__msg [0:7]; - logic [0:0] switch_units__send__rdy [0:7]; - logic [0:0] switch_units__send__val [0:7]; - - SwitchUnitRTL__4cc70db240bb572a switch_units__0 - ( - .clk( switch_units__clk[0] ), - .reset( switch_units__reset[0] ), - .recv__msg( switch_units__recv__msg[0] ), - .recv__rdy( switch_units__recv__rdy[0] ), - .recv__val( switch_units__recv__val[0] ), - .send__msg( switch_units__send__msg[0] ), - .send__rdy( switch_units__send__rdy[0] ), - .send__val( switch_units__send__val[0] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__1 - ( - .clk( switch_units__clk[1] ), - .reset( switch_units__reset[1] ), - .recv__msg( switch_units__recv__msg[1] ), - .recv__rdy( switch_units__recv__rdy[1] ), - .recv__val( switch_units__recv__val[1] ), - .send__msg( switch_units__send__msg[1] ), - .send__rdy( switch_units__send__rdy[1] ), - .send__val( switch_units__send__val[1] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__2 - ( - .clk( switch_units__clk[2] ), - .reset( switch_units__reset[2] ), - .recv__msg( switch_units__recv__msg[2] ), - .recv__rdy( switch_units__recv__rdy[2] ), - .recv__val( switch_units__recv__val[2] ), - .send__msg( switch_units__send__msg[2] ), - .send__rdy( switch_units__send__rdy[2] ), - .send__val( switch_units__send__val[2] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__3 - ( - .clk( switch_units__clk[3] ), - .reset( switch_units__reset[3] ), - .recv__msg( switch_units__recv__msg[3] ), - .recv__rdy( switch_units__recv__rdy[3] ), - .recv__val( switch_units__recv__val[3] ), - .send__msg( switch_units__send__msg[3] ), - .send__rdy( switch_units__send__rdy[3] ), - .send__val( switch_units__send__val[3] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__4 - ( - .clk( switch_units__clk[4] ), - .reset( switch_units__reset[4] ), - .recv__msg( switch_units__recv__msg[4] ), - .recv__rdy( switch_units__recv__rdy[4] ), - .recv__val( switch_units__recv__val[4] ), - .send__msg( switch_units__send__msg[4] ), - .send__rdy( switch_units__send__rdy[4] ), - .send__val( switch_units__send__val[4] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__5 - ( - .clk( switch_units__clk[5] ), - .reset( switch_units__reset[5] ), - .recv__msg( switch_units__recv__msg[5] ), - .recv__rdy( switch_units__recv__rdy[5] ), - .recv__val( switch_units__recv__val[5] ), - .send__msg( switch_units__send__msg[5] ), - .send__rdy( switch_units__send__rdy[5] ), - .send__val( switch_units__send__val[5] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__6 - ( - .clk( switch_units__clk[6] ), - .reset( switch_units__reset[6] ), - .recv__msg( switch_units__recv__msg[6] ), - .recv__rdy( switch_units__recv__rdy[6] ), - .recv__val( switch_units__recv__val[6] ), - .send__msg( switch_units__send__msg[6] ), - .send__rdy( switch_units__send__rdy[6] ), - .send__val( switch_units__send__val[6] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__7 - ( - .clk( switch_units__clk[7] ), - .reset( switch_units__reset[7] ), - .recv__msg( switch_units__recv__msg[7] ), - .recv__rdy( switch_units__recv__rdy[7] ), - .recv__val( switch_units__recv__val[7] ), - .send__msg( switch_units__send__msg[7] ), - .send__rdy( switch_units__send__rdy[7] ), - .send__val( switch_units__send__val[7] ) - ); - - //------------------------------------------------------------- - // End of component switch_units[0:7] - //------------------------------------------------------------- - - assign input_units__clk[0] = clk; - assign input_units__reset[0] = reset; - assign input_units__clk[1] = clk; - assign input_units__reset[1] = reset; - assign input_units__clk[2] = clk; - assign input_units__reset[2] = reset; - assign route_units__clk[0] = clk; - assign route_units__reset[0] = reset; - assign route_units__clk[1] = clk; - assign route_units__reset[1] = reset; - assign route_units__clk[2] = clk; - assign route_units__reset[2] = reset; - assign switch_units__clk[0] = clk; - assign switch_units__reset[0] = reset; - assign switch_units__clk[1] = clk; - assign switch_units__reset[1] = reset; - assign switch_units__clk[2] = clk; - assign switch_units__reset[2] = reset; - assign switch_units__clk[3] = clk; - assign switch_units__reset[3] = reset; - assign switch_units__clk[4] = clk; - assign switch_units__reset[4] = reset; - assign switch_units__clk[5] = clk; - assign switch_units__reset[5] = reset; - assign switch_units__clk[6] = clk; - assign switch_units__reset[6] = reset; - assign switch_units__clk[7] = clk; - assign switch_units__reset[7] = reset; - assign output_units__clk[0] = clk; - assign output_units__reset[0] = reset; - assign output_units__clk[1] = clk; - assign output_units__reset[1] = reset; - assign output_units__clk[2] = clk; - assign output_units__reset[2] = reset; - assign output_units__clk[3] = clk; - assign output_units__reset[3] = reset; - assign output_units__clk[4] = clk; - assign output_units__reset[4] = reset; - assign output_units__clk[5] = clk; - assign output_units__reset[5] = reset; - assign output_units__clk[6] = clk; - assign output_units__reset[6] = reset; - assign output_units__clk[7] = clk; - assign output_units__reset[7] = reset; - assign input_units__recv__msg[0] = recv__msg[0]; - assign recv__rdy[0] = input_units__recv__rdy[0]; - assign input_units__recv__val[0] = recv__val[0]; - assign route_units__recv__msg[0] = input_units__send__msg[0]; - assign input_units__send__rdy[0] = route_units__recv__rdy[0]; - assign route_units__recv__val[0] = input_units__send__val[0]; - assign input_units__recv__msg[1] = recv__msg[1]; - assign recv__rdy[1] = input_units__recv__rdy[1]; - assign input_units__recv__val[1] = recv__val[1]; - assign route_units__recv__msg[1] = input_units__send__msg[1]; - assign input_units__send__rdy[1] = route_units__recv__rdy[1]; - assign route_units__recv__val[1] = input_units__send__val[1]; - assign input_units__recv__msg[2] = recv__msg[2]; - assign recv__rdy[2] = input_units__recv__rdy[2]; - assign input_units__recv__val[2] = recv__val[2]; - assign route_units__recv__msg[2] = input_units__send__msg[2]; - assign input_units__send__rdy[2] = route_units__recv__rdy[2]; - assign route_units__recv__val[2] = input_units__send__val[2]; - assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; - assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; - assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; - assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; - assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; - assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; - assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; - assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; - assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; - assign switch_units__recv__msg[3][0] = route_units__send__msg[0][3]; - assign route_units__send__rdy[0][3] = switch_units__recv__rdy[3][0]; - assign switch_units__recv__val[3][0] = route_units__send__val[0][3]; - assign switch_units__recv__msg[4][0] = route_units__send__msg[0][4]; - assign route_units__send__rdy[0][4] = switch_units__recv__rdy[4][0]; - assign switch_units__recv__val[4][0] = route_units__send__val[0][4]; - assign switch_units__recv__msg[5][0] = route_units__send__msg[0][5]; - assign route_units__send__rdy[0][5] = switch_units__recv__rdy[5][0]; - assign switch_units__recv__val[5][0] = route_units__send__val[0][5]; - assign switch_units__recv__msg[6][0] = route_units__send__msg[0][6]; - assign route_units__send__rdy[0][6] = switch_units__recv__rdy[6][0]; - assign switch_units__recv__val[6][0] = route_units__send__val[0][6]; - assign switch_units__recv__msg[7][0] = route_units__send__msg[0][7]; - assign route_units__send__rdy[0][7] = switch_units__recv__rdy[7][0]; - assign switch_units__recv__val[7][0] = route_units__send__val[0][7]; - assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; - assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; - assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; - assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; - assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; - assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; - assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; - assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; - assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; - assign switch_units__recv__msg[3][1] = route_units__send__msg[1][3]; - assign route_units__send__rdy[1][3] = switch_units__recv__rdy[3][1]; - assign switch_units__recv__val[3][1] = route_units__send__val[1][3]; - assign switch_units__recv__msg[4][1] = route_units__send__msg[1][4]; - assign route_units__send__rdy[1][4] = switch_units__recv__rdy[4][1]; - assign switch_units__recv__val[4][1] = route_units__send__val[1][4]; - assign switch_units__recv__msg[5][1] = route_units__send__msg[1][5]; - assign route_units__send__rdy[1][5] = switch_units__recv__rdy[5][1]; - assign switch_units__recv__val[5][1] = route_units__send__val[1][5]; - assign switch_units__recv__msg[6][1] = route_units__send__msg[1][6]; - assign route_units__send__rdy[1][6] = switch_units__recv__rdy[6][1]; - assign switch_units__recv__val[6][1] = route_units__send__val[1][6]; - assign switch_units__recv__msg[7][1] = route_units__send__msg[1][7]; - assign route_units__send__rdy[1][7] = switch_units__recv__rdy[7][1]; - assign switch_units__recv__val[7][1] = route_units__send__val[1][7]; - assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; - assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; - assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; - assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; - assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; - assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; - assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; - assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; - assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; - assign switch_units__recv__msg[3][2] = route_units__send__msg[2][3]; - assign route_units__send__rdy[2][3] = switch_units__recv__rdy[3][2]; - assign switch_units__recv__val[3][2] = route_units__send__val[2][3]; - assign switch_units__recv__msg[4][2] = route_units__send__msg[2][4]; - assign route_units__send__rdy[2][4] = switch_units__recv__rdy[4][2]; - assign switch_units__recv__val[4][2] = route_units__send__val[2][4]; - assign switch_units__recv__msg[5][2] = route_units__send__msg[2][5]; - assign route_units__send__rdy[2][5] = switch_units__recv__rdy[5][2]; - assign switch_units__recv__val[5][2] = route_units__send__val[2][5]; - assign switch_units__recv__msg[6][2] = route_units__send__msg[2][6]; - assign route_units__send__rdy[2][6] = switch_units__recv__rdy[6][2]; - assign switch_units__recv__val[6][2] = route_units__send__val[2][6]; - assign switch_units__recv__msg[7][2] = route_units__send__msg[2][7]; - assign route_units__send__rdy[2][7] = switch_units__recv__rdy[7][2]; - assign switch_units__recv__val[7][2] = route_units__send__val[2][7]; - assign output_units__recv__msg[0] = switch_units__send__msg[0]; - assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; - assign output_units__recv__val[0] = switch_units__send__val[0]; - assign send__msg[0] = output_units__send__msg[0]; - assign output_units__send__rdy[0] = send__rdy[0]; - assign send__val[0] = output_units__send__val[0]; - assign output_units__recv__msg[1] = switch_units__send__msg[1]; - assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; - assign output_units__recv__val[1] = switch_units__send__val[1]; - assign send__msg[1] = output_units__send__msg[1]; - assign output_units__send__rdy[1] = send__rdy[1]; - assign send__val[1] = output_units__send__val[1]; - assign output_units__recv__msg[2] = switch_units__send__msg[2]; - assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; - assign output_units__recv__val[2] = switch_units__send__val[2]; - assign send__msg[2] = output_units__send__msg[2]; - assign output_units__send__rdy[2] = send__rdy[2]; - assign send__val[2] = output_units__send__val[2]; - assign output_units__recv__msg[3] = switch_units__send__msg[3]; - assign switch_units__send__rdy[3] = output_units__recv__rdy[3]; - assign output_units__recv__val[3] = switch_units__send__val[3]; - assign send__msg[3] = output_units__send__msg[3]; - assign output_units__send__rdy[3] = send__rdy[3]; - assign send__val[3] = output_units__send__val[3]; - assign output_units__recv__msg[4] = switch_units__send__msg[4]; - assign switch_units__send__rdy[4] = output_units__recv__rdy[4]; - assign output_units__recv__val[4] = switch_units__send__val[4]; - assign send__msg[4] = output_units__send__msg[4]; - assign output_units__send__rdy[4] = send__rdy[4]; - assign send__val[4] = output_units__send__val[4]; - assign output_units__recv__msg[5] = switch_units__send__msg[5]; - assign switch_units__send__rdy[5] = output_units__recv__rdy[5]; - assign output_units__recv__val[5] = switch_units__send__val[5]; - assign send__msg[5] = output_units__send__msg[5]; - assign output_units__send__rdy[5] = send__rdy[5]; - assign send__val[5] = output_units__send__val[5]; - assign output_units__recv__msg[6] = switch_units__send__msg[6]; - assign switch_units__send__rdy[6] = output_units__recv__rdy[6]; - assign output_units__recv__val[6] = switch_units__send__val[6]; - assign send__msg[6] = output_units__send__msg[6]; - assign output_units__send__rdy[6] = send__rdy[6]; - assign send__val[6] = output_units__send__val[6]; - assign output_units__recv__msg[7] = switch_units__send__msg[7]; - assign switch_units__send__rdy[7] = output_units__recv__rdy[7]; - assign output_units__recv__val[7] = switch_units__send__val[7]; - assign send__msg[7] = output_units__send__msg[7]; - assign output_units__send__rdy[7] = send__rdy[7]; - assign send__val[7] = output_units__send__val[7]; - -endmodule - - -// PyMTL Component DataMemControllerRTL Definition -// Full name: DataMemControllerRTL__NocPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_rd_tiles_7__num_wr_tiles_7__multi_cgra_rows_2__multi_cgra_columns_2__num_tiles_16__mem_access_is_combinational_True__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)} -// At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py - -module DataMemControllerRTL__20df9b544ed809f0 -( - input logic [6:0] address_lower , - input logic [6:0] address_upper , - input logic [1:0] cgra_id , - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_load_request__msg , - output logic [0:0] recv_from_noc_load_request__rdy , - input logic [0:0] recv_from_noc_load_request__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_load_response_pkt__msg , - output logic [0:0] recv_from_noc_load_response_pkt__rdy , - input logic [0:0] recv_from_noc_load_response_pkt__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_store_request__msg , - output logic [0:0] recv_from_noc_store_request__rdy , - input logic [0:0] recv_from_noc_store_request__val , - input logic [6:0] recv_raddr__msg [0:6] , - output logic [0:0] recv_raddr__rdy [0:6] , - input logic [0:0] recv_raddr__val [0:6] , - input logic [6:0] recv_waddr__msg [0:6] , - output logic [0:0] recv_waddr__rdy [0:6] , - input logic [0:0] recv_waddr__val [0:6] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_wdata__msg [0:6] , - output logic [0:0] recv_wdata__rdy [0:6] , - input logic [0:0] recv_wdata__val [0:6] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_rdata__msg [0:6] , - input logic [0:0] send_rdata__rdy [0:6] , - output logic [0:0] send_rdata__val [0:6] , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_load_request_pkt__msg , - input logic [0:0] send_to_noc_load_request_pkt__rdy , - output logic [0:0] send_to_noc_load_request_pkt__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_load_response_pkt__msg , - input logic [0:0] send_to_noc_load_response_pkt__rdy , - output logic [0:0] send_to_noc_load_response_pkt__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_store_pkt__msg , - input logic [0:0] send_to_noc_store_pkt__rdy , - output logic [0:0] send_to_noc_store_pkt__val -); - localparam logic [3:0] __const__num_xbar_in_rd_ports_at_assemble_xbar_pkt = 4'd8; - localparam logic [3:0] __const__num_xbar_in_wr_ports_at_assemble_xbar_pkt = 4'd8; - localparam logic [2:0] __const__num_rd_tiles_at_assemble_xbar_pkt = 3'd7; - localparam logic [2:0] __const__per_bank_addr_nbits_at_assemble_xbar_pkt = 3'd4; - localparam logic [1:0] __const__num_banks_per_cgra_at_assemble_xbar_pkt = 2'd2; - localparam logic [2:0] __const__num_wr_tiles_at_assemble_xbar_pkt = 3'd7; - localparam logic [2:0] __const__num_rd_tiles_at_update_all = 3'd7; - localparam logic [2:0] __const__num_wr_tiles_at_update_all = 3'd7; - localparam logic [3:0] __const__num_xbar_in_rd_ports_at_update_all = 4'd8; - localparam logic [3:0] __const__num_xbar_in_wr_ports_at_update_all = 4'd8; - localparam logic [3:0] __const__CMD_LOAD_RESPONSE = 4'd11; - localparam logic [1:0] __const__num_banks_per_cgra_at_update_all = 2'd2; - localparam logic [3:0] __const__CMD_LOAD_REQUEST = 4'd10; - localparam logic [3:0] __const__CMD_STORE_REQUEST = 4'd12; - logic [0:0] idTo2d_x_lut [0:3]; - logic [0:0] idTo2d_y_lut [0:3]; - MemAccessPacket_8_3_128__43c148781d2f2a57 rd_pkt [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 wr_pkt [0:7]; - //------------------------------------------------------------- - // Component memory_wrapper[0:1] - //------------------------------------------------------------- - - logic [0:0] memory_wrapper__clk [0:1]; - logic [0:0] memory_wrapper__reset [0:1]; - MemAccessPacket_8_3_128__43c148781d2f2a57 memory_wrapper__recv_rd__msg [0:1]; - logic [0:0] memory_wrapper__recv_rd__rdy [0:1]; - logic [0:0] memory_wrapper__recv_rd__val [0:1]; - MemAccessPacket_8_3_128__43c148781d2f2a57 memory_wrapper__recv_wr__msg [0:1]; - logic [0:0] memory_wrapper__recv_wr__rdy [0:1]; - logic [0:0] memory_wrapper__recv_wr__val [0:1]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 memory_wrapper__send__msg [0:1]; - logic [0:0] memory_wrapper__send__rdy [0:1]; - logic [0:0] memory_wrapper__send__val [0:1]; - - DataMemWrapperRTL__33e0a5b37976e571 memory_wrapper__0 - ( - .clk( memory_wrapper__clk[0] ), - .reset( memory_wrapper__reset[0] ), - .recv_rd__msg( memory_wrapper__recv_rd__msg[0] ), - .recv_rd__rdy( memory_wrapper__recv_rd__rdy[0] ), - .recv_rd__val( memory_wrapper__recv_rd__val[0] ), - .recv_wr__msg( memory_wrapper__recv_wr__msg[0] ), - .recv_wr__rdy( memory_wrapper__recv_wr__rdy[0] ), - .recv_wr__val( memory_wrapper__recv_wr__val[0] ), - .send__msg( memory_wrapper__send__msg[0] ), - .send__rdy( memory_wrapper__send__rdy[0] ), - .send__val( memory_wrapper__send__val[0] ) - ); - - DataMemWrapperRTL__33e0a5b37976e571 memory_wrapper__1 - ( - .clk( memory_wrapper__clk[1] ), - .reset( memory_wrapper__reset[1] ), - .recv_rd__msg( memory_wrapper__recv_rd__msg[1] ), - .recv_rd__rdy( memory_wrapper__recv_rd__rdy[1] ), - .recv_rd__val( memory_wrapper__recv_rd__val[1] ), - .recv_wr__msg( memory_wrapper__recv_wr__msg[1] ), - .recv_wr__rdy( memory_wrapper__recv_wr__rdy[1] ), - .recv_wr__val( memory_wrapper__recv_wr__val[1] ), - .send__msg( memory_wrapper__send__msg[1] ), - .send__rdy( memory_wrapper__send__rdy[1] ), - .send__val( memory_wrapper__send__val[1] ) - ); - - //------------------------------------------------------------- - // End of component memory_wrapper[0:1] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component read_crossbar - //------------------------------------------------------------- - - logic [0:0] read_crossbar__clk; - logic [0:0] read_crossbar__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 read_crossbar__recv__msg [0:7]; - logic [0:0] read_crossbar__recv__rdy [0:7]; - logic [0:0] read_crossbar__recv__val [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 read_crossbar__send__msg [0:2]; - logic [0:0] read_crossbar__send__rdy [0:2]; - logic [0:0] read_crossbar__send__val [0:2]; - - XbarBypassQueueRTL__045133ee283ca701 read_crossbar - ( - .clk( read_crossbar__clk ), - .reset( read_crossbar__reset ), - .recv__msg( read_crossbar__recv__msg ), - .recv__rdy( read_crossbar__recv__rdy ), - .recv__val( read_crossbar__recv__val ), - .send__msg( read_crossbar__send__msg ), - .send__rdy( read_crossbar__send__rdy ), - .send__val( read_crossbar__send__val ) - ); - - //------------------------------------------------------------- - // End of component read_crossbar - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component response_crossbar - //------------------------------------------------------------- - - logic [0:0] response_crossbar__clk; - logic [0:0] response_crossbar__reset; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 response_crossbar__recv__msg [0:2]; - logic [0:0] response_crossbar__recv__rdy [0:2]; - logic [0:0] response_crossbar__recv__val [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 response_crossbar__send__msg [0:7]; - logic [0:0] response_crossbar__send__rdy [0:7]; - logic [0:0] response_crossbar__send__val [0:7]; - - XbarBypassQueueRTL__510da12df6787984 response_crossbar - ( - .clk( response_crossbar__clk ), - .reset( response_crossbar__reset ), - .recv__msg( response_crossbar__recv__msg ), - .recv__rdy( response_crossbar__recv__rdy ), - .recv__val( response_crossbar__recv__val ), - .send__msg( response_crossbar__send__msg ), - .send__rdy( response_crossbar__send__rdy ), - .send__val( response_crossbar__send__val ) - ); - - //------------------------------------------------------------- - // End of component response_crossbar - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component write_crossbar - //------------------------------------------------------------- - - logic [0:0] write_crossbar__clk; - logic [0:0] write_crossbar__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 write_crossbar__recv__msg [0:7]; - logic [0:0] write_crossbar__recv__rdy [0:7]; - logic [0:0] write_crossbar__recv__val [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 write_crossbar__send__msg [0:2]; - logic [0:0] write_crossbar__send__rdy [0:2]; - logic [0:0] write_crossbar__send__val [0:2]; - - XbarBypassQueueRTL__045133ee283ca701 write_crossbar - ( - .clk( write_crossbar__clk ), - .reset( write_crossbar__reset ), - .recv__msg( write_crossbar__recv__msg ), - .recv__rdy( write_crossbar__recv__rdy ), - .recv__val( write_crossbar__recv__val ), - .send__msg( write_crossbar__send__msg ), - .send__rdy( write_crossbar__send__rdy ), - .send__val( write_crossbar__send__val ) - ); - - //------------------------------------------------------------- - // End of component write_crossbar - //------------------------------------------------------------- - logic [6:0] __tmpvar__assemble_xbar_pkt_recv_raddr; - logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_load_local; - logic [6:0] __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc; - logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc; - logic [6:0] __tmpvar__assemble_xbar_pkt_recv_waddr; - logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_store_local; - logic [6:0] __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc; - logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc; - logic [1:0] __tmpvar__update_all_from_cgra_id; - logic [4:0] __tmpvar__update_all_from_tile_id; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py:159 - // @update - // def assemble_xbar_pkt(): - // for i in range(num_xbar_in_rd_ports): - // s.rd_pkt[i] @= MemReadPktType(i, 0, 0, DataType(0, 0, 0, 0), 0, 0, i, 0, 0, 0) - // - // for i in range(num_xbar_in_wr_ports): - // s.wr_pkt[i] @= MemWritePktType(i, 0, 0, DataType(0, 0, 0, 0), 0, 0, i, 0, 0, 0) - // - // for i in range(num_rd_tiles): - // recv_raddr = s.recv_raddr[i].msg - // # Calculates the target bank index for load. - // if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper): - // bank_index_load_local = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType) - // else: - // bank_index_load_local = XbarOutRdType(num_banks_per_cgra) - // # FIXME: change to exact tile id. - // s.rd_pkt[i] @= MemReadPktType(i, # src - // bank_index_load_local, # dst - // recv_raddr, # addr - // DataType(0, 0, 0, 0), # data - // s.cgra_id, # src_cgra - // 0, # src_tile - // i, # remote_src_port - // 0, # streaming_rd - // 0, # streaming_rd_stride - // 0) # streaming_rd_end_addr - // - // recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr - // # Calculates the target bank index. - // if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper): - // bank_index_load_from_noc = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType) - // else: - // bank_index_load_from_noc = XbarOutRdType(num_banks_per_cgra) - // s.rd_pkt[num_rd_tiles] @= MemReadPktType(num_rd_tiles, # src - // bank_index_load_from_noc, # dst - // recv_raddr_from_noc, # addr - // DataType(0, 0, 0, 0), # data - // s.recv_from_noc_load_request.msg.src, # src_cgra - // s.recv_from_noc_load_request.msg.src_tile_id, # src_tile - // s.recv_from_noc_load_request.msg.remote_src_port, # remote_src_port - // 0, # streaming_rd - // 0, # streaming_rd_stride - // 0) # streaming_rd_end_addr - // - // - // for i in range(num_wr_tiles): - // recv_waddr = s.recv_waddr[i].msg - // # Calculates the target bank index for store. - // if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper): - // bank_index_store_local = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType) - // else: - // bank_index_store_local = XbarOutWrType(num_banks_per_cgra) - // s.wr_pkt[i] @= MemWritePktType(i, # src - // bank_index_store_local, # dst - // recv_waddr, # addr - // s.recv_wdata[i].msg, # data - // 0, # src_cgra - // 0, # src_tile - // i, # remote_src_port - // 0, # streaming_rd - // 0, # streaming_rd_stride - // 0) # streaming_rd_end_addr - // - // - // recv_waddr_from_noc = s.recv_from_noc_store_request.msg.payload.data_addr - // recv_wdata_from_noc = s.recv_from_noc_store_request.msg.payload.data - // if (recv_waddr_from_noc >= s.address_lower) & (recv_waddr_from_noc <= s.address_upper): - // bank_index_store_from_noc = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType) - // else: - // bank_index_store_from_noc = XbarOutWrType(num_banks_per_cgra) - // s.wr_pkt[num_wr_tiles] @= MemWritePktType(num_wr_tiles, # src - // bank_index_store_from_noc, # dst - // recv_waddr_from_noc, # addr - // recv_wdata_from_noc, # data - // 0, # src_cgra - // 0, # src_tile - // num_wr_tiles, # remote_src_port - // 0, # streaming_rd - // 0, # streaming_rd_stride - // 0) # streaming_rd_end_addr - - always_comb begin : assemble_xbar_pkt - for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_assemble_xbar_pkt ); i += 1'd1 ) - rd_pkt[3'(i)] = { 3'(i), 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; - for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_wr_ports_at_assemble_xbar_pkt ); i += 1'd1 ) - wr_pkt[3'(i)] = { 3'(i), 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; - for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_assemble_xbar_pkt ); i += 1'd1 ) begin - __tmpvar__assemble_xbar_pkt_recv_raddr = recv_raddr__msg[3'(i)]; - if ( ( __tmpvar__assemble_xbar_pkt_recv_raddr >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_raddr <= address_upper ) ) begin - __tmpvar__assemble_xbar_pkt_bank_index_load_local = 2'(( __tmpvar__assemble_xbar_pkt_recv_raddr - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); - end - else - __tmpvar__assemble_xbar_pkt_bank_index_load_local = 2'd2; - rd_pkt[3'(i)] = { 3'(i), __tmpvar__assemble_xbar_pkt_bank_index_load_local, __tmpvar__assemble_xbar_pkt_recv_raddr, { 64'd0, 1'd0, 1'd0, 1'd0 }, cgra_id, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; - end - __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc = recv_from_noc_load_request__msg.payload.data_addr; - if ( ( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc <= address_upper ) ) begin - __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc = 2'(( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); - end - else - __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc = 2'd2; - rd_pkt[3'( __const__num_rd_tiles_at_assemble_xbar_pkt )] = { 3'( __const__num_rd_tiles_at_assemble_xbar_pkt ), __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc, __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc, { 64'd0, 1'd0, 1'd0, 1'd0 }, recv_from_noc_load_request__msg.src, recv_from_noc_load_request__msg.src_tile_id, recv_from_noc_load_request__msg.remote_src_port, 1'd0, 7'd0, 7'd0 }; - for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ); i += 1'd1 ) begin - __tmpvar__assemble_xbar_pkt_recv_waddr = recv_waddr__msg[3'(i)]; - if ( ( __tmpvar__assemble_xbar_pkt_recv_waddr >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_waddr <= address_upper ) ) begin - __tmpvar__assemble_xbar_pkt_bank_index_store_local = 2'(( __tmpvar__assemble_xbar_pkt_recv_waddr - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); - end - else - __tmpvar__assemble_xbar_pkt_bank_index_store_local = 2'd2; - wr_pkt[3'(i)] = { 3'(i), __tmpvar__assemble_xbar_pkt_bank_index_store_local, __tmpvar__assemble_xbar_pkt_recv_waddr, recv_wdata__msg[3'(i)], 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; - end - __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc = recv_from_noc_store_request__msg.payload.data_addr; - __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc = recv_from_noc_store_request__msg.payload.data; - if ( ( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc <= address_upper ) ) begin - __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc = 2'(( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); - end - else - __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc = 2'd2; - wr_pkt[3'( __const__num_wr_tiles_at_assemble_xbar_pkt )] = { 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ), __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc, __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc, __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc, 2'd0, 5'd0, 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ), 1'd0, 7'd0, 7'd0 }; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py:242 - // @update - // def update_all(): - // # Initializes the signals. - // for i in range(num_rd_tiles): - // s.recv_raddr[i].rdy @= 0 - // s.recv_from_noc_load_request.rdy @= 0 - // - // for i in range(num_wr_tiles): - // s.recv_waddr[i].rdy @= 0 - // # s.recv_wdata_bypass_q[i].send.rdy @= 0 - // s.recv_from_noc_store_request.rdy @= 0 - // # s.recv_wdata_bypass_q[num_wr_tiles].send.rdy @= 0 - // - // for i in range(num_rd_tiles): - // s.send_rdata[i].val @= 0 - // s.send_rdata[i].msg @= DataType() - // s.send_to_noc_load_response_pkt.val @= 0 - // - // s.send_to_noc_load_response_pkt.msg @= \ - // NocPktType(0, # src - // 0, # dst - // 0, # src_x - // 0, # src_y - // 0, # dst_x - // 0, # dst_y - // 0, # src_tile_id - // 0, # dst_tile_id - // 0, # remote_src_port - // 0, # opaque - // 0, # vc_id - // CgraPayloadType(0, 0, 0, 0, 0)) - // - // - // for i in range(num_wr_tiles): - // s.recv_wdata[i].rdy @= 0 - // - // s.send_to_noc_store_pkt.msg @= \ - // NocPktType(0, # src - // 0, # dst - // 0, # src_x - // 0, # src_y - // 0, # dst_x - // 0, # dst_y - // 0, # src_tile_id - // 0, # dst_tile_id - // 0, # remote_src_port - // 0, # opaque - // 0, # vc_id - // CgraPayloadType(0, 0, 0, 0, 0)) - // - // s.send_to_noc_store_pkt.val @= 0 - // - // for i in range(num_xbar_in_rd_ports): - // s.read_crossbar.recv[i].val @= 0 - // s.read_crossbar.recv[i].msg @= MemReadPktType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) - // - // s.recv_from_noc_load_response_pkt.rdy @= 0 - // - // for i in range(num_xbar_in_wr_ports): - // s.write_crossbar.recv[i].val @= 0 - // s.write_crossbar.recv[i].msg @= MemWritePktType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) - // - // s.send_to_noc_load_request_pkt.msg @= \ - // NocPktType(0, # src - // 0, # dst - // 0, # src_x - // 0, # src_y - // 0, # dst_x - // 0, # dst_y - // 0, # src_tile_id - // 0, # dst_tile_id - // 0, # remote_src_port - // 0, # opaque - // 0, # vc_id - // CgraPayloadType(0, 0, 0, 0, 0)) - // - // s.send_to_noc_load_request_pkt.val @= 0 - // - // # Connects the load request ports (from tiles and NoC) to the xbar targetting memory and NoC. - // for i in range(num_rd_tiles): - // s.read_crossbar.recv[i].val @= s.recv_raddr[i].val - // s.read_crossbar.recv[i].msg @= s.rd_pkt[i] - // s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy - // s.read_crossbar.recv[num_rd_tiles].val @= s.recv_from_noc_load_request.val - // s.read_crossbar.recv[num_rd_tiles].msg @= s.rd_pkt[num_rd_tiles] - // s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[num_rd_tiles].rdy - // - // # Connects the store request ports (from tiles and NoC) to the xbar targetting memory and NoC. - // for i in range(num_wr_tiles): - // s.write_crossbar.recv[i].val @= s.recv_waddr[i].val - // s.write_crossbar.recv[i].msg @= s.wr_pkt[i] - // s.recv_waddr[i].rdy @= s.write_crossbar.recv[i].rdy - // s.recv_wdata[i].rdy @= s.write_crossbar.recv[i].rdy - // s.write_crossbar.recv[num_wr_tiles].val @= s.recv_from_noc_store_request.val - // s.write_crossbar.recv[num_wr_tiles].msg @= s.wr_pkt[num_wr_tiles] - // s.recv_from_noc_store_request.rdy @= s.write_crossbar.recv[num_wr_tiles].rdy - // - // # Connects the response ports to tiles and NoC from the xbar. - // # Number of load responses is expected to be the same as the number of load requests. - // for i in range(num_xbar_in_rd_ports): - // if i < num_rd_tiles: - // s.send_rdata[RdTileIdType(i)].msg @= s.response_crossbar.send[i].msg.data - // s.send_rdata[RdTileIdType(i)].val @= s.response_crossbar.send[i].val - // s.response_crossbar.send[i].rdy @= s.send_rdata[RdTileIdType(i)].rdy - // else: - // from_cgra_id = s.response_crossbar.send[i].msg.src_cgra - // from_tile_id = s.response_crossbar.send[i].msg.src_tile - // s.send_to_noc_load_response_pkt.msg @= \ - // NocPktType( - // s.cgra_id, # src_cgra_id - // from_cgra_id, # dst_cgra_id - // s.idTo2d_x_lut[s.cgra_id], # src_cgra_x - // s.idTo2d_y_lut[s.cgra_id], # src_cgra_y - // s.idTo2d_x_lut[from_cgra_id], # dst_cgra_x - // s.idTo2d_y_lut[from_cgra_id], # dst_cgra_y - // 0, # src_tile_id set as 0 as it is from memory rather than a specific tile. - // from_tile_id, # dst_tile_id - // s.response_crossbar.send[i].msg.remote_src_port, # remote_src_port, carries the original source port id towards the src. - // 0, # opaque - // 0, # vc_id - // CgraPayloadType( - // CMD_LOAD_RESPONSE, - // s.response_crossbar.send[i].msg.data, - // s.response_crossbar.send[i].msg.addr, 0, 0)) - // - // s.send_to_noc_load_response_pkt.val @= s.response_crossbar.send[i].val - // s.response_crossbar.send[i].rdy @= s.send_to_noc_load_response_pkt.rdy - // - // # Handles the request (not response) towards the others via the NoC. The dst would be - // # updated in the controller. - // s.send_to_noc_load_request_pkt.msg @= \ - // NocPktType(s.cgra_id, # src - // 0, # dst - // s.idTo2d_x_lut[s.cgra_id], # src_x - // s.idTo2d_y_lut[s.cgra_id], # src_y - // 0, # dst_x - // 0, # dst_y - // 0, # src_tile_id - // 0, # dst_tile_id - // s.read_crossbar.send[num_banks_per_cgra].msg.src, # remote_src_port - // 0, # opaque - // 0, # vc_id - // CgraPayloadType( - // CMD_LOAD_REQUEST, - // 0, - // s.read_crossbar.send[num_banks_per_cgra].msg.addr, 0, 0)) - // - // s.send_to_noc_load_request_pkt.val @= s.read_crossbar.send[num_banks_per_cgra].val - // # TODO: https://github.com/tancheng/VectorCGRA/issues/26 -- Modify this part for non-blocking access. - // # 'val` indicates the data is arbitrated successfully. - // s.recv_from_noc_load_response_pkt.rdy @= s.response_crossbar.recv[num_banks_per_cgra].rdy - // s.response_crossbar.recv[num_banks_per_cgra].val @= s.recv_from_noc_load_response_pkt.val - // s.response_crossbar.recv[num_banks_per_cgra].msg @= \ - // MemResponsePktType(num_banks_per_cgra, - // s.recv_from_noc_load_response_pkt.msg.remote_src_port, - // s.recv_from_noc_load_response_pkt.msg.payload.data_addr, - // s.recv_from_noc_load_response_pkt.msg.payload.data, - // s.recv_from_noc_load_response_pkt.msg.src, - // s.recv_from_noc_load_response_pkt.msg.src_tile_id, - // 0, - // 0, # streaming_rd - // 0, # streaming_rd_stride - // 0) # streaming_rd_end_addr - // - // # Allows other load request towards NoC when the previous one is not responded. There - // # could be out-of-order load response, i.e., potential consistency issue. - // s.read_crossbar.send[num_banks_per_cgra].rdy @= s.send_to_noc_load_request_pkt.rdy - // - // # Handles the write port towards the NoC. - // s.send_to_noc_store_pkt.msg @= \ - // NocPktType(s.cgra_id, # src - // 0, # dst - // s.idTo2d_x_lut[s.cgra_id], # src_x - // s.idTo2d_y_lut[s.cgra_id], # src_y - // 0, # dst_x - // 0, # dst_y - // 0, # src_tile_id - // 0, # dst_tile_id - // s.write_crossbar.send[num_banks_per_cgra].msg.src, # remote_src_port - // 0, # opaque - // 0, # vc_id - // CgraPayloadType( - // CMD_STORE_REQUEST, - // s.write_crossbar.send[num_banks_per_cgra].msg.data, - // s.write_crossbar.send[num_banks_per_cgra].msg.addr, 0, 0)) - // - // s.send_to_noc_store_pkt.val @= s.write_crossbar.send[num_banks_per_cgra].val - // s.write_crossbar.send[num_banks_per_cgra].rdy @= s.send_to_noc_store_pkt.rdy - - always_comb begin : update_all - for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) - recv_raddr__rdy[3'(i)] = 1'd0; - recv_from_noc_load_request__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) - recv_waddr__rdy[3'(i)] = 1'd0; - recv_from_noc_store_request__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) begin - send_rdata__val[3'(i)] = 1'd0; - send_rdata__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - send_to_noc_load_response_pkt__val = 1'd0; - send_to_noc_load_response_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; - for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) - recv_wdata__rdy[3'(i)] = 1'd0; - send_to_noc_store_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; - send_to_noc_store_pkt__val = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_update_all ); i += 1'd1 ) begin - read_crossbar__recv__val[3'(i)] = 1'd0; - read_crossbar__recv__msg[3'(i)] = { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; - end - recv_from_noc_load_response_pkt__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_wr_ports_at_update_all ); i += 1'd1 ) begin - write_crossbar__recv__val[3'(i)] = 1'd0; - write_crossbar__recv__msg[3'(i)] = { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; - end - send_to_noc_load_request_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; - send_to_noc_load_request_pkt__val = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) begin - read_crossbar__recv__val[3'(i)] = recv_raddr__val[3'(i)]; - read_crossbar__recv__msg[3'(i)] = rd_pkt[3'(i)]; - recv_raddr__rdy[3'(i)] = read_crossbar__recv__rdy[3'(i)]; - end - read_crossbar__recv__val[3'( __const__num_rd_tiles_at_update_all )] = recv_from_noc_load_request__val; - read_crossbar__recv__msg[3'( __const__num_rd_tiles_at_update_all )] = rd_pkt[3'( __const__num_rd_tiles_at_update_all )]; - recv_from_noc_load_request__rdy = read_crossbar__recv__rdy[3'( __const__num_rd_tiles_at_update_all )]; - for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) begin - write_crossbar__recv__val[3'(i)] = recv_waddr__val[3'(i)]; - write_crossbar__recv__msg[3'(i)] = wr_pkt[3'(i)]; - recv_waddr__rdy[3'(i)] = write_crossbar__recv__rdy[3'(i)]; - recv_wdata__rdy[3'(i)] = write_crossbar__recv__rdy[3'(i)]; - end - write_crossbar__recv__val[3'( __const__num_wr_tiles_at_update_all )] = recv_from_noc_store_request__val; - write_crossbar__recv__msg[3'( __const__num_wr_tiles_at_update_all )] = wr_pkt[3'( __const__num_wr_tiles_at_update_all )]; - recv_from_noc_store_request__rdy = write_crossbar__recv__rdy[3'( __const__num_wr_tiles_at_update_all )]; - for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_update_all ); i += 1'd1 ) - if ( 3'(i) < 3'( __const__num_rd_tiles_at_update_all ) ) begin - send_rdata__msg[3'( 3'(i) )] = response_crossbar__send__msg[3'(i)].data; - send_rdata__val[3'( 3'(i) )] = response_crossbar__send__val[3'(i)]; - response_crossbar__send__rdy[3'(i)] = send_rdata__rdy[3'( 3'(i) )]; - end - else begin - __tmpvar__update_all_from_cgra_id = response_crossbar__send__msg[3'(i)].src_cgra; - __tmpvar__update_all_from_tile_id = response_crossbar__send__msg[3'(i)].src_tile; - send_to_noc_load_response_pkt__msg = { cgra_id, __tmpvar__update_all_from_cgra_id, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], idTo2d_x_lut[__tmpvar__update_all_from_cgra_id], idTo2d_y_lut[__tmpvar__update_all_from_cgra_id], 5'd0, __tmpvar__update_all_from_tile_id, response_crossbar__send__msg[3'(i)].remote_src_port, 8'd0, 2'd0, { 5'( __const__CMD_LOAD_RESPONSE ), response_crossbar__send__msg[3'(i)].data, response_crossbar__send__msg[3'(i)].addr, 107'd0, 4'd0 } }; - send_to_noc_load_response_pkt__val = response_crossbar__send__val[3'(i)]; - response_crossbar__send__rdy[3'(i)] = send_to_noc_load_response_pkt__rdy; - end - send_to_noc_load_request_pkt__msg = { cgra_id, 2'd0, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], 1'd0, 1'd0, 5'd0, 5'd0, read_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].src, 8'd0, 2'd0, { 5'( __const__CMD_LOAD_REQUEST ), 67'd0, read_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].addr, 107'd0, 4'd0 } }; - send_to_noc_load_request_pkt__val = read_crossbar__send__val[2'( __const__num_banks_per_cgra_at_update_all )]; - recv_from_noc_load_response_pkt__rdy = response_crossbar__recv__rdy[2'( __const__num_banks_per_cgra_at_update_all )]; - response_crossbar__recv__val[2'( __const__num_banks_per_cgra_at_update_all )] = recv_from_noc_load_response_pkt__val; - response_crossbar__recv__msg[2'( __const__num_banks_per_cgra_at_update_all )] = { 2'( __const__num_banks_per_cgra_at_update_all ), recv_from_noc_load_response_pkt__msg.remote_src_port, recv_from_noc_load_response_pkt__msg.payload.data_addr, recv_from_noc_load_response_pkt__msg.payload.data, recv_from_noc_load_response_pkt__msg.src, recv_from_noc_load_response_pkt__msg.src_tile_id, 3'd0, 1'd0, 7'd0, 7'd0 }; - read_crossbar__send__rdy[2'( __const__num_banks_per_cgra_at_update_all )] = send_to_noc_load_request_pkt__rdy; - send_to_noc_store_pkt__msg = { cgra_id, 2'd0, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], 1'd0, 1'd0, 5'd0, 5'd0, write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].src, 8'd0, 2'd0, { 5'( __const__CMD_STORE_REQUEST ), write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].data, write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].addr, 107'd0, 4'd0 } }; - send_to_noc_store_pkt__val = write_crossbar__send__val[2'( __const__num_banks_per_cgra_at_update_all )]; - write_crossbar__send__rdy[2'( __const__num_banks_per_cgra_at_update_all )] = send_to_noc_store_pkt__rdy; - end - - assign memory_wrapper__clk[0] = clk; - assign memory_wrapper__reset[0] = reset; - assign memory_wrapper__clk[1] = clk; - assign memory_wrapper__reset[1] = reset; - assign read_crossbar__clk = clk; - assign read_crossbar__reset = reset; - assign write_crossbar__clk = clk; - assign write_crossbar__reset = reset; - assign response_crossbar__clk = clk; - assign response_crossbar__reset = reset; - assign idTo2d_x_lut[0] = 1'd0; - assign idTo2d_y_lut[0] = 1'd0; - assign idTo2d_x_lut[1] = 1'd1; - assign idTo2d_y_lut[1] = 1'd0; - assign idTo2d_x_lut[2] = 1'd0; - assign idTo2d_y_lut[2] = 1'd1; - assign idTo2d_x_lut[3] = 1'd1; - assign idTo2d_y_lut[3] = 1'd1; - assign memory_wrapper__recv_rd__msg[0] = read_crossbar__send__msg[0]; - assign read_crossbar__send__rdy[0] = memory_wrapper__recv_rd__rdy[0]; - assign memory_wrapper__recv_rd__val[0] = read_crossbar__send__val[0]; - assign memory_wrapper__recv_wr__msg[0] = write_crossbar__send__msg[0]; - assign write_crossbar__send__rdy[0] = memory_wrapper__recv_wr__rdy[0]; - assign memory_wrapper__recv_wr__val[0] = write_crossbar__send__val[0]; - assign response_crossbar__recv__msg[0] = memory_wrapper__send__msg[0]; - assign memory_wrapper__send__rdy[0] = response_crossbar__recv__rdy[0]; - assign response_crossbar__recv__val[0] = memory_wrapper__send__val[0]; - assign memory_wrapper__recv_rd__msg[1] = read_crossbar__send__msg[1]; - assign read_crossbar__send__rdy[1] = memory_wrapper__recv_rd__rdy[1]; - assign memory_wrapper__recv_rd__val[1] = read_crossbar__send__val[1]; - assign memory_wrapper__recv_wr__msg[1] = write_crossbar__send__msg[1]; - assign write_crossbar__send__rdy[1] = memory_wrapper__recv_wr__rdy[1]; - assign memory_wrapper__recv_wr__val[1] = write_crossbar__send__val[1]; - assign response_crossbar__recv__msg[1] = memory_wrapper__send__msg[1]; - assign memory_wrapper__send__rdy[1] = response_crossbar__recv__rdy[1]; - assign response_crossbar__recv__val[1] = memory_wrapper__send__val[1]; - -endmodule - - -// PyMTL Component ConstQueueDynamicRTL Definition -// Full name: ConstQueueDynamicRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__const_mem_size_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py - -module ConstQueueDynamicRTL__9d3397f72f19af52 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] ctrl_proceed , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_const__msg , - input logic [0:0] send_const__rdy , - output logic [0:0] send_const__val -); - localparam logic [4:0] __const__const_mem_size_at_load_const = 5'd16; - localparam logic [4:0] __const__const_mem_size_at_update_wr_cur = 5'd16; - logic [3:0] rd_cur; - logic [4:0] wr_cur; - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__bd22936ec5812d0d reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [0:0] __tmpvar__load_const_not_full; - logic [0:0] __tmpvar__update_wr_cur_not_full; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:56 - // @update - // def load_const(): - // # Initializes signals. - // s.reg_file.waddr[0] @= AddrType() - // s.reg_file.wdata[0] @= DataType() - // s.reg_file.wen[0] @= 0 - // - // not_full = s.wr_cur < const_mem_size - // s.recv_const.rdy @= not_full - // - // if s.recv_const.val & not_full: - // s.reg_file.waddr[0] @= trunc(s.wr_cur, AddrType) - // s.reg_file.wdata[0] @= s.recv_const.msg - // s.reg_file.wen[0] @= 1 - - always_comb begin : load_const - reg_file__waddr[1'd0] = 4'd0; - reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__wen[1'd0] = 1'd0; - __tmpvar__load_const_not_full = wr_cur < 5'( __const__const_mem_size_at_load_const ); - recv_const__rdy = __tmpvar__load_const_not_full; - if ( recv_const__val & __tmpvar__load_const_not_full ) begin - reg_file__waddr[1'd0] = 4'(wr_cur); - reg_file__wdata[1'd0] = recv_const__msg; - reg_file__wen[1'd0] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:83 - // @update - // def update_send_val(): - // # Checks if read cursor is in front of write cursor. - // if (zext(s.rd_cur, WrCurType) < s.wr_cur): - // s.send_const.val @= 1 - // else: - // s.send_const.val @= 0 - - always_comb begin : update_send_val - if ( { { 1 { 1'b0 } }, rd_cur } < wr_cur ) begin - send_const__val = 1'd1; - end - else - send_const__val = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:92 - // @update_ff - // def update_rd_cur(): - // if s.reset | s.clear: - // s.rd_cur <<= 0 - // else: - // # Checks whether the "reader" successfully read the data at rd_cur, - // # and proceed rd_cur accordingly. - // if s.send_const.rdy & s.ctrl_proceed: - // if zext((s.rd_cur), WrCurType) < (s.wr_cur - 1): - // s.rd_cur <<= s.rd_cur + 1 - // else: - // s.rd_cur <<= 0 - - always_ff @(posedge clk) begin : update_rd_cur - if ( reset | clear ) begin - rd_cur <= 4'd0; - end - else if ( send_const__rdy & ctrl_proceed ) begin - if ( { { 1 { 1'b0 } }, rd_cur } < ( wr_cur - 5'd1 ) ) begin - rd_cur <= rd_cur + 4'd1; - end - else - rd_cur <= 4'd0; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:72 - // @update_ff - // def update_wr_cur(): - // not_full = (s.wr_cur < const_mem_size) - // if s.reset | s.clear: - // s.wr_cur <<= 0 - // # Checks if there's a valid const (from producer) to be written. - // else: - // if s.recv_const.val & not_full: - // s.wr_cur <<= s.wr_cur + 1 - - always_ff @(posedge clk) begin : update_wr_cur - __tmpvar__update_wr_cur_not_full = wr_cur < 5'( __const__const_mem_size_at_update_wr_cur ); - if ( reset | clear ) begin - wr_cur <= 5'd0; - end - else if ( recv_const__val & __tmpvar__update_wr_cur_not_full ) begin - wr_cur <= wr_cur + 5'd1; - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - assign send_const__msg = reg_file__rdata[0]; - assign reg_file__raddr[0] = rd_cur; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__736a0143e1873b49 -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__66f570731410737c -( - input logic [0:0] clk , - input logic [0:0] raddr , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_msg , - input logic [0:0] reset , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__736a0143e1873b49 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__66f570731410737c -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__raddr; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a dpath__recv_msg; - logic [0:0] dpath__reset; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__66f570731410737c dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__nregs_16__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__46d8b36a7a21259f -( - input logic [0:0] clk , - input logic [3:0] raddr [0:0], - output CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 rdata [0:0], - input logic [0:0] reset , - input logic [3:0] waddr [0:0], - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 regs [0:15]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component CtrlMemDynamicRTL Definition -// Full name: CtrlMemDynamicRTL__IntraCgraPktType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ctrl_mem_size_16__num_fu_inports_4__num_fu_outports_2__num_tile_inports_4__num_tile_outports_4__num_cgras_4__num_tiles_16__ctrl_count_per_iter_4__total_ctrl_steps_38 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py - -module CtrlMemDynamicRTL__427d547b7d58aa8e -( - input logic [1:0] cgra_id , - input logic [0:0] clk , - output logic [3:0] ctrl_addr_outport , - output logic [2:0] prologue_count_outport_fu , - output logic [2:0] prologue_count_outport_fu_crossbar [0:15][0:1], - output logic [2:0] prologue_count_outport_routing_crossbar [0:15][0:3], - input logic [0:0] reset , - input logic [4:0] tile_id , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element__msg , - output logic [0:0] recv_from_element__rdy , - input logic [0:0] recv_from_element__val , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller__msg , - output logic [0:0] recv_pkt_from_controller__rdy , - input logic [0:0] recv_pkt_from_controller__val , - output CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 send_ctrl__msg , - input logic [0:0] send_ctrl__rdy , - output logic [0:0] send_ctrl__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_pkt_to_controller__msg , - input logic [0:0] send_pkt_to_controller__rdy , - output logic [0:0] send_pkt_to_controller__val , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_element__msg , - input logic [0:0] send_to_element__rdy , - output logic [0:0] send_to_element__val -); - localparam logic [2:0] __const__num_fu_inports_at_update_msg = 3'd4; - localparam logic [3:0] __const__num_routing_outports_at_update_msg = 4'd8; - localparam logic [1:0] __const__CMD_CONFIG = 2'd3; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; - localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; - localparam logic [1:0] __const__CMD_TERMINATE = 2'd2; - localparam logic [0:0] __const__CMD_PAUSE = 1'd1; - localparam logic [4:0] __const__CMD_PRESERVE = 5'd22; - localparam logic [3:0] __const__CMD_RESUME = 4'd15; - localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; - localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; - localparam logic [3:0] __const__CMD_CONFIG_CTRL_LOWER_BOUND = 4'd9; - localparam logic [4:0] __const__CMD_RECORD_PHI_ADDR = 5'd16; - localparam logic [4:0] __const__num_tiles_at_update_send_pkt_to_controller = 5'd16; - localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [4:0] __const__ctrl_mem_size_at_update_raddr_and_fu_prologue = 5'd16; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_outport = 5'd16; - localparam logic [2:0] __const__num_tile_inports_at_update_prologue_outport = 3'd4; - localparam logic [1:0] __const__num_fu_outports_at_update_prologue_outport = 2'd2; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_reg = 5'd16; - localparam logic [2:0] __const__num_tile_inports_at_update_prologue_reg = 3'd4; - localparam logic [1:0] __const__num_fu_outports_at_update_prologue_reg = 2'd2; - localparam logic [2:0] __const__ctrl_count_per_iter_at_update_ctrl_count_per_iter = 3'd4; - localparam logic [5:0] __const__total_ctrl_steps_at_update_total_ctrl_steps = 6'd38; - logic [3:0] ctrl_count_lower_bound; - logic [2:0] ctrl_count_per_iter_val; - logic [4:0] ctrl_count_upper_bound; - logic [2:0] prologue_count_reg_fu [0:15]; - logic [2:0] prologue_count_reg_fu_crossbar [0:15][0:1]; - logic [2:0] prologue_count_reg_routing_crossbar [0:15][0:3]; - logic [0:0] sent_complete; - logic [0:0] start_iterate_ctrl; - logic [10:0] times; - logic [10:0] total_ctrl_steps_val; - //------------------------------------------------------------- - // Component recv_from_element_queue - //------------------------------------------------------------- - - logic [0:0] recv_from_element_queue__clk; - logic [1:0] recv_from_element_queue__count; - logic [0:0] recv_from_element_queue__reset; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element_queue__recv__msg; - logic [0:0] recv_from_element_queue__recv__rdy; - logic [0:0] recv_from_element_queue__recv__val; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element_queue__send__msg; - logic [0:0] recv_from_element_queue__send__rdy; - logic [0:0] recv_from_element_queue__send__val; - - NormalQueueRTL__66f570731410737c recv_from_element_queue - ( - .clk( recv_from_element_queue__clk ), - .count( recv_from_element_queue__count ), - .reset( recv_from_element_queue__reset ), - .recv__msg( recv_from_element_queue__recv__msg ), - .recv__rdy( recv_from_element_queue__recv__rdy ), - .recv__val( recv_from_element_queue__recv__val ), - .send__msg( recv_from_element_queue__send__msg ), - .send__rdy( recv_from_element_queue__send__rdy ), - .send__val( recv_from_element_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_from_element_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component recv_pkt_from_controller_queue - //------------------------------------------------------------- - - logic [0:0] recv_pkt_from_controller_queue__clk; - logic [1:0] recv_pkt_from_controller_queue__count; - logic [0:0] recv_pkt_from_controller_queue__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller_queue__recv__msg; - logic [0:0] recv_pkt_from_controller_queue__recv__rdy; - logic [0:0] recv_pkt_from_controller_queue__recv__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller_queue__send__msg; - logic [0:0] recv_pkt_from_controller_queue__send__rdy; - logic [0:0] recv_pkt_from_controller_queue__send__val; - - NormalQueueRTL__a1c7a5a18a302c36 recv_pkt_from_controller_queue - ( - .clk( recv_pkt_from_controller_queue__clk ), - .count( recv_pkt_from_controller_queue__count ), - .reset( recv_pkt_from_controller_queue__reset ), - .recv__msg( recv_pkt_from_controller_queue__recv__msg ), - .recv__rdy( recv_pkt_from_controller_queue__recv__rdy ), - .recv__val( recv_pkt_from_controller_queue__recv__val ), - .send__msg( recv_pkt_from_controller_queue__send__msg ), - .send__rdy( recv_pkt_from_controller_queue__send__rdy ), - .send__val( recv_pkt_from_controller_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_pkt_from_controller_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__46d8b36a7a21259f reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [2:0] __tmpvar__update_prologue_reg_temp_routing_crossbar_in; - logic [1:0] __tmpvar__update_prologue_reg_temp_fu_crossbar_in; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:157 - // @update - // def update_ctrl_addr_outport(): - // s.ctrl_addr_outport @= s.reg_file.raddr[0] - - always_comb begin : update_ctrl_addr_outport - ctrl_addr_outport = reg_file__raddr[1'd0]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:94 - // @update - // def update_msg(): - // s.recv_pkt_from_controller_queue.send.rdy @= 0 - // s.send_to_element.msg @= CgraPayloadType(0, 0, 0, 0, 0) - // s.send_to_element.val @= 0 - // s.reg_file.wen[0] @= 0 - // s.reg_file.waddr[0] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr - // # Initializes the fields of the control signal. - // s.reg_file.wdata[0].operation @= 0 - // for i in range(num_fu_inports): - // s.reg_file.wdata[0].fu_in[i] @= 0 - // s.reg_file.wdata[0].write_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_from[i] - // s.reg_file.wdata[0].write_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_idx[i] - // s.reg_file.wdata[0].read_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_from[i] - // s.reg_file.wdata[0].read_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_idx[i] - // for i in range(num_routing_outports): - // s.reg_file.wdata[0].routing_xbar_outport[i] @= 0 - // s.reg_file.wdata[0].fu_xbar_outport[i] @= 0 - // s.reg_file.wdata[0].vector_factor_power @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.vector_factor_power - // s.reg_file.wdata[0].is_last_ctrl @= 0 - // - // if s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG): - // s.reg_file.wen[0] @= 1 - // s.reg_file.waddr[0] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr - // # Fills the fields of the control signal. - // s.reg_file.wdata[0].operation @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.operation - // for i in range(num_fu_inports): - // s.reg_file.wdata[0].fu_in[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_in[i] - // s.reg_file.wdata[0].write_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_from[i] - // s.reg_file.wdata[0].write_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_idx[i] - // s.reg_file.wdata[0].read_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_from[i] - // s.reg_file.wdata[0].read_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_idx[i] - // for i in range(num_routing_outports): - // s.reg_file.wdata[0].routing_xbar_outport[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.routing_xbar_outport[i] - // s.reg_file.wdata[0].fu_xbar_outport[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_xbar_outport[i] - // s.reg_file.wdata[0].vector_factor_power @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.vector_factor_power - // s.reg_file.wdata[0].is_last_ctrl @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.is_last_ctrl - // elif s.recv_pkt_from_controller_queue.send.val & \ - // ((s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE)): - // s.send_to_element.msg @= s.recv_pkt_from_controller_queue.send.msg.payload - // s.send_to_element.val @= 1 - // - // if (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_PAUSE) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_PRESERVE) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RECORD_PHI_ADDR) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE): - // s.recv_pkt_from_controller_queue.send.rdy @= 1 - // # TODO: Extend for the other commands. Maybe another queue to - // # handle complicated actions. - // # else: - - always_comb begin : update_msg - recv_pkt_from_controller_queue__send__rdy = 1'd0; - send_to_element__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - send_to_element__val = 1'd0; - reg_file__wen[1'd0] = 1'd0; - reg_file__waddr[1'd0] = recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr; - reg_file__wdata[1'd0].operation = 7'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_fu_inports_at_update_msg ); i += 1'd1 ) begin - reg_file__wdata[1'd0].fu_in[2'(i)] = 3'd0; - reg_file__wdata[1'd0].write_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_from[2'(i)]; - reg_file__wdata[1'd0].write_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_idx[2'(i)]; - reg_file__wdata[1'd0].read_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_from[2'(i)]; - reg_file__wdata[1'd0].read_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_idx[2'(i)]; - end - for ( int unsigned i = 1'd0; i < 4'( __const__num_routing_outports_at_update_msg ); i += 1'd1 ) begin - reg_file__wdata[1'd0].routing_xbar_outport[3'(i)] = 3'd0; - reg_file__wdata[1'd0].fu_xbar_outport[3'(i)] = 2'd0; - end - reg_file__wdata[1'd0].vector_factor_power = recv_pkt_from_controller_queue__send__msg.payload.ctrl.vector_factor_power; - reg_file__wdata[1'd0].is_last_ctrl = 1'd0; - if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) ) begin - reg_file__wen[1'd0] = 1'd1; - reg_file__waddr[1'd0] = recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr; - reg_file__wdata[1'd0].operation = recv_pkt_from_controller_queue__send__msg.payload.ctrl.operation; - for ( int unsigned i = 1'd0; i < 3'( __const__num_fu_inports_at_update_msg ); i += 1'd1 ) begin - reg_file__wdata[1'd0].fu_in[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_in[2'(i)]; - reg_file__wdata[1'd0].write_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_from[2'(i)]; - reg_file__wdata[1'd0].write_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_idx[2'(i)]; - reg_file__wdata[1'd0].read_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_from[2'(i)]; - reg_file__wdata[1'd0].read_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_idx[2'(i)]; - end - for ( int unsigned i = 1'd0; i < 4'( __const__num_routing_outports_at_update_msg ); i += 1'd1 ) begin - reg_file__wdata[1'd0].routing_xbar_outport[3'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.routing_xbar_outport[3'(i)]; - reg_file__wdata[1'd0].fu_xbar_outport[3'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_xbar_outport[3'(i)]; - end - reg_file__wdata[1'd0].vector_factor_power = recv_pkt_from_controller_queue__send__msg.payload.ctrl.vector_factor_power; - reg_file__wdata[1'd0].is_last_ctrl = recv_pkt_from_controller_queue__send__msg.payload.ctrl.is_last_ctrl; - end - else if ( recv_pkt_from_controller_queue__send__val & ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) ) begin - send_to_element__msg = recv_pkt_from_controller_queue__send__msg.payload; - send_to_element__val = 1'd1; - end - if ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_PAUSE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_PRESERVE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RECORD_PHI_ADDR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) begin - recv_pkt_from_controller_queue__send__rdy = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:255 - // @update - // def update_prologue_outport(): - // s.prologue_count_outport_fu @= s.prologue_count_reg_fu[s.reg_file.raddr[0]] - // for addr in range(ctrl_mem_size): - // for i in range(num_tile_inports): - // s.prologue_count_outport_routing_crossbar[addr][i] @= \ - // s.prologue_count_reg_routing_crossbar[addr][i] - // for i in range(num_fu_outports): - // s.prologue_count_outport_fu_crossbar[addr][i] @= \ - // s.prologue_count_reg_fu_crossbar[addr][i] - - always_comb begin : update_prologue_outport - prologue_count_outport_fu = prologue_count_reg_fu[reg_file__raddr[1'd0]]; - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_outport ); addr += 1'd1 ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_tile_inports_at_update_prologue_outport ); i += 1'd1 ) - prologue_count_outport_routing_crossbar[4'(addr)][2'(i)] = prologue_count_reg_routing_crossbar[4'(addr)][2'(i)]; - for ( int unsigned i = 1'd0; i < 2'( __const__num_fu_outports_at_update_prologue_outport ); i += 1'd1 ) - prologue_count_outport_fu_crossbar[4'(addr)][1'(i)] = prologue_count_reg_fu_crossbar[4'(addr)][1'(i)]; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:181 - // @update - // def update_send_ctrl(): - // s.send_ctrl.val @= 0 - // if s.start_iterate_ctrl == b1(1): - // if s.sent_complete: - // s.send_ctrl.val @= 0 - // elif ((s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val)) | \ - // (s.reg_file.rdata[0].operation == OPT_START): - // s.send_ctrl.val @= b1(0) - // else: - // s.send_ctrl.val @= 1 - // if s.recv_pkt_from_controller_queue.send.val & \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE): - // s.send_ctrl.val @= b1(0) - - always_comb begin : update_send_ctrl - send_ctrl__val = 1'd0; - if ( start_iterate_ctrl == 1'd1 ) begin - if ( sent_complete ) begin - send_ctrl__val = 1'd0; - end - else if ( ( ( total_ctrl_steps_val > 11'd0 ) & ( times == total_ctrl_steps_val ) ) | ( reg_file__rdata[1'd0].operation == 7'( __const__OPT_START ) ) ) begin - send_ctrl__val = 1'd0; - end - else - send_ctrl__val = 1'd1; - end - if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) begin - send_ctrl__val = 1'd0; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:161 - // @update - // def update_send_pkt_to_controller(): - // s.send_pkt_to_controller.val @= 0 - // s.send_pkt_to_controller.msg @= IntraCgraPktType(0, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, CgraPayloadType(CMD_COMPLETE, 0, 0, 0, 0)) - // s.recv_from_element_queue.send.rdy @= 0 - // if s.start_iterate_ctrl == b1(1): - // if s.recv_from_element_queue.send.val & (~s.sent_complete): - // s.send_pkt_to_controller.msg @= \ - // IntraCgraPktType(s.tile_id, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, - // s.recv_from_element_queue.send.msg) - // s.send_pkt_to_controller.val @= 1 - // s.recv_from_element_queue.send.rdy @= s.send_pkt_to_controller.rdy - // elif ((s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val)) | \ - // (s.reg_file.rdata[0].operation == OPT_START): - // # Sends COMPLETE signal to Controller when the last ctrl signal is done. - // if ~s.sent_complete & (s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val) & s.start_iterate_ctrl: - // s.send_pkt_to_controller.msg @= \ - // IntraCgraPktType(s.tile_id, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, CgraPayloadType(CMD_COMPLETE, 0, 0, 0, 0)) - // s.send_pkt_to_controller.val @= 1 - - always_comb begin : update_send_pkt_to_controller - send_pkt_to_controller__val = 1'd0; - send_pkt_to_controller__msg = { 5'd0, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'( __const__CMD_COMPLETE ), 67'd0, 7'd0, 107'd0, 4'd0 } }; - recv_from_element_queue__send__rdy = 1'd0; - if ( start_iterate_ctrl == 1'd1 ) begin - if ( recv_from_element_queue__send__val & ( ~sent_complete ) ) begin - send_pkt_to_controller__msg = { tile_id, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, recv_from_element_queue__send__msg }; - send_pkt_to_controller__val = 1'd1; - recv_from_element_queue__send__rdy = send_pkt_to_controller__rdy; - end - else if ( ( ( total_ctrl_steps_val > 11'd0 ) & ( times == total_ctrl_steps_val ) ) | ( reg_file__rdata[1'd0].operation == 7'( __const__OPT_START ) ) ) begin - if ( ( ( ( ~sent_complete ) & ( total_ctrl_steps_val > 11'd0 ) ) & ( times == total_ctrl_steps_val ) ) & start_iterate_ctrl ) begin - send_pkt_to_controller__msg = { tile_id, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'( __const__CMD_COMPLETE ), 67'd0, 7'd0, 107'd0, 4'd0 } }; - send_pkt_to_controller__val = 1'd1; - end - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:298 - // @update - // def update_upper_bound(): - // s.ctrl_count_upper_bound @= zext(s.ctrl_count_lower_bound, UpperBoundType) + zext(s.ctrl_count_per_iter_val, UpperBoundType) - - always_comb begin : update_upper_bound - ctrl_count_upper_bound = { { 1 { 1'b0 } }, ctrl_count_lower_bound } + { { 2 { 1'b0 } }, ctrl_count_per_iter_val }; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:210 - // @update_ff - // def issue_complete(): - // if s.reset: - // s.sent_complete <<= 0 - // else: - // if s.send_pkt_to_controller.val & \ - // s.send_pkt_to_controller.rdy & \ - // (s.send_pkt_to_controller.msg.payload.cmd == CMD_COMPLETE): - // s.sent_complete <<= 1 - // elif s.recv_pkt_from_controller_queue.send.val & ( (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME) ): - // s.sent_complete <<= 0 - - always_ff @(posedge clk) begin : issue_complete - if ( reset ) begin - sent_complete <= 1'd0; - end - else if ( ( send_pkt_to_controller__val & send_pkt_to_controller__rdy ) & ( send_pkt_to_controller__msg.payload.cmd == 5'( __const__CMD_COMPLETE ) ) ) begin - sent_complete <= 1'd1; - end - else if ( recv_pkt_from_controller_queue__send__val & ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) ) begin - sent_complete <= 1'd0; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:284 - // @update_ff - // def update_ctrl_count_per_iter(): - // if s.reset: - // s.ctrl_count_per_iter_val <<= PCType(ctrl_count_per_iter) - // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER): - // s.ctrl_count_per_iter_val <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PCType) - - always_ff @(posedge clk) begin : update_ctrl_count_per_iter - if ( reset ) begin - ctrl_count_per_iter_val <= 3'd4; - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) begin - ctrl_count_per_iter_val <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:291 - // @update_ff - // def update_lower_bound(): - // if s.reset: - // s.ctrl_count_lower_bound <<= CtrlAddrType(0) - // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND): - // s.ctrl_count_lower_bound <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, CtrlAddrType) - - always_ff @(posedge clk) begin : update_lower_bound - if ( reset ) begin - ctrl_count_lower_bound <= 4'd0; - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) begin - ctrl_count_lower_bound <= 4'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:266 - // @update_ff - // def update_prologue_reg(): - // if s.reset: - // for addr in range(ctrl_mem_size): - // for i in range(num_tile_inports): - // s.prologue_count_reg_routing_crossbar[addr][i] <<= 0 - // for i in range(num_fu_outports): - // s.prologue_count_reg_fu_crossbar[addr][i] <<= 0 - // else: - // if s.recv_pkt_from_controller_queue.send.val & \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR): - // temp_routing_crossbar_in = s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.routing_xbar_outport[0] - // s.prologue_count_reg_routing_crossbar[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr][trunc(temp_routing_crossbar_in, TileInPortType)] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) - // elif s.recv_pkt_from_controller_queue.send.val & \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR): - // temp_fu_crossbar_in = s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_xbar_outport[0] - // s.prologue_count_reg_fu_crossbar[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr][trunc(temp_fu_crossbar_in, FuOutPortType)] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) - - always_ff @(posedge clk) begin : update_prologue_reg - if ( reset ) begin - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_reg ); addr += 1'd1 ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_tile_inports_at_update_prologue_reg ); i += 1'd1 ) - prologue_count_reg_routing_crossbar[4'(addr)][2'(i)] <= 3'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_fu_outports_at_update_prologue_reg ); i += 1'd1 ) - prologue_count_reg_fu_crossbar[4'(addr)][1'(i)] <= 3'd0; - end - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) begin - __tmpvar__update_prologue_reg_temp_routing_crossbar_in = recv_pkt_from_controller_queue__send__msg.payload.ctrl.routing_xbar_outport[3'd0]; - prologue_count_reg_routing_crossbar[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr][2'(__tmpvar__update_prologue_reg_temp_routing_crossbar_in)] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) begin - __tmpvar__update_prologue_reg_temp_fu_crossbar_in = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_xbar_outport[3'd0]; - prologue_count_reg_fu_crossbar[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr][1'(__tmpvar__update_prologue_reg_temp_fu_crossbar_in)] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:223 - // @update_ff - // def update_raddr_and_fu_prologue(): - // if s.reset: - // s.times <<= 0 - // s.reg_file.raddr[0] <<= 0 - // for i in range(ctrl_mem_size): - // s.prologue_count_reg_fu[i] <<= 0 - // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND): - // s.reg_file.raddr[0] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, CtrlAddrType) - // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE): - // s.times <<= TimeType(0) - // else: - // if s.recv_pkt_from_controller_queue.send.val & \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU): - // s.prologue_count_reg_fu[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr] <<= \ - // trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) - // - // if s.start_iterate_ctrl == b1(1): - // if ((s.total_ctrl_steps_val == 0) | \ - // (s.times < s.total_ctrl_steps_val)) & \ - // s.send_ctrl.rdy & s.send_ctrl.val: - // s.times <<= s.times + TimeType(1) - // - // # Reads the next ctrl signal only when the current one is done. - // if s.send_ctrl.rdy & s.send_ctrl.val: - // if zext(s.reg_file.raddr[0], UpperBoundType) == s.ctrl_count_upper_bound - UpperBoundType(1): - // s.reg_file.raddr[0] <<= s.ctrl_count_lower_bound - // else: - // s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + CtrlAddrType(1) - // if s.prologue_count_reg_fu[s.reg_file.raddr[0]] > 0: - // s.prologue_count_reg_fu[s.reg_file.raddr[0]] <<= s.prologue_count_reg_fu[s.reg_file.raddr[0]] - 1 - - always_ff @(posedge clk) begin : update_raddr_and_fu_prologue - if ( reset ) begin - times <= 11'd0; - reg_file__raddr[1'd0] <= 4'd0; - for ( int unsigned i = 1'd0; i < 5'( __const__ctrl_mem_size_at_update_raddr_and_fu_prologue ); i += 1'd1 ) - prologue_count_reg_fu[4'(i)] <= 3'd0; - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) begin - reg_file__raddr[1'd0] <= 4'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) begin - times <= 11'd0; - end - else begin - if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) begin - prologue_count_reg_fu[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - if ( start_iterate_ctrl == 1'd1 ) begin - if ( ( ( ( total_ctrl_steps_val == 11'd0 ) | ( times < total_ctrl_steps_val ) ) & send_ctrl__rdy ) & send_ctrl__val ) begin - times <= times + 11'd1; - end - if ( send_ctrl__rdy & send_ctrl__val ) begin - if ( { { 1 { 1'b0 } }, reg_file__raddr[1'd0] } == ( ctrl_count_upper_bound - 5'd1 ) ) begin - reg_file__raddr[1'd0] <= ctrl_count_lower_bound; - end - else - reg_file__raddr[1'd0] <= reg_file__raddr[1'd0] + 4'd1; - if ( prologue_count_reg_fu[reg_file__raddr[1'd0]] > 3'd0 ) begin - prologue_count_reg_fu[reg_file__raddr[1'd0]] <= prologue_count_reg_fu[reg_file__raddr[1'd0]] - 3'd1; - end - end - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:302 - // @update_ff - // def update_total_ctrl_steps(): - // if s.reset: - // s.total_ctrl_steps_val <<= TimeType(total_ctrl_steps) - // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT): - // s.total_ctrl_steps_val <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, TimeType) - - always_ff @(posedge clk) begin : update_total_ctrl_steps - if ( reset ) begin - total_ctrl_steps_val <= 11'd38; - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) begin - total_ctrl_steps_val <= 11'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:196 - // @update_ff - // def update_whether_we_can_iterate_ctrl(): - // if s.reset: - // s.start_iterate_ctrl <<= 0 - // else: - // if s.recv_pkt_from_controller_queue.send.val: - // if (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME): - // s.start_iterate_ctrl <<= 1 - // # TODO: issue #191, stop iterate ctrl after 10 cycels during pausing status, - // # so as to clear channels safely. - // elif s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE: - // s.start_iterate_ctrl <<= 0 - - always_ff @(posedge clk) begin : update_whether_we_can_iterate_ctrl - if ( reset ) begin - start_iterate_ctrl <= 1'd0; - end - else if ( recv_pkt_from_controller_queue__send__val ) begin - if ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) begin - start_iterate_ctrl <= 1'd1; - end - else if ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) begin - start_iterate_ctrl <= 1'd0; - end - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - assign recv_pkt_from_controller_queue__clk = clk; - assign recv_pkt_from_controller_queue__reset = reset; - assign recv_from_element_queue__clk = clk; - assign recv_from_element_queue__reset = reset; - assign send_ctrl__msg = reg_file__rdata[0]; - assign recv_pkt_from_controller_queue__recv__msg = recv_pkt_from_controller__msg; - assign recv_pkt_from_controller__rdy = recv_pkt_from_controller_queue__recv__rdy; - assign recv_pkt_from_controller_queue__recv__val = recv_pkt_from_controller__val; - assign recv_from_element_queue__recv__msg = recv_from_element__msg; - assign recv_from_element__rdy = recv_from_element_queue__recv__rdy; - assign recv_from_element_queue__recv__val = recv_from_element__val; - -endmodule - - -// PyMTL Component AdderRTL Definition -// Full name: AdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py - -module AdderRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_ADD = 7'd2; - localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; - localparam logic [6:0] __const__OPT_INC = 7'd3; - localparam logic [6:0] __const__OPT_SUB = 7'd4; - localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; - localparam logic [6:0] __const__OPT_PAS = 7'd31; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py:45 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // s.in0 @= 0 - // s.in1 @= 0 - // # For pick input register - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // # Though different operations might not need to consume - // # all the operands, as long as the opcode indicating it - // # is an operand, the data would disappear from the register. - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != 0: - // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) - // if s.recv_opt.msg.fu_in[1] != 0: - // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_ADD: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_ADD_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // s.recv_const.rdy @= s.send_out[0].rdy - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_INC: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.const_one.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_PAS: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_const__msg.payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; - recv_const__rdy = send_out__rdy[1'd0]; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + 64'd1; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_const__msg.payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component MulRTL Definition -// Full name: MulRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_32 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py - -module MulRTL__903abe7e5de73fa1 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_MUL = 7'd7; - localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py:44 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != 0: - // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) - // if s.recv_opt.msg.fu_in[1] != 0: - // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_MUL: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_MUL_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_const__msg.payload; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component AdderRTL Definition -// Full name: AdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_32 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py - -module AdderRTL__903abe7e5de73fa1 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_ADD = 7'd2; - localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; - localparam logic [6:0] __const__OPT_INC = 7'd3; - localparam logic [6:0] __const__OPT_SUB = 7'd4; - localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; - localparam logic [6:0] __const__OPT_PAS = 7'd31; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py:45 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // s.in0 @= 0 - // s.in1 @= 0 - // # For pick input register - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // # Though different operations might not need to consume - // # all the operands, as long as the opcode indicating it - // # is an operand, the data would disappear from the register. - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != 0: - // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) - // if s.recv_opt.msg.fu_in[1] != 0: - // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_ADD: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_ADD_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // s.recv_const.rdy @= s.send_out[0].rdy - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_INC: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.const_one.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_PAS: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_const__msg.payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; - recv_const__rdy = send_out__rdy[1'd0]; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + 64'd1; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_const__msg.payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component SeqMulAdderRTL Definition -// Full name: SeqMulAdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/double/SeqMulAdderRTL.py - -module SeqMulAdderRTL__b741248a3a1dca5f -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_MUL_ADD = 7'd18; - localparam logic [6:0] __const__OPT_MUL = 7'd7; - localparam logic [6:0] __const__OPT_ADD = 7'd2; - localparam logic [6:0] __const__OPT_MUL_CONST_ADD = 7'd30; - localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; - localparam logic [6:0] __const__OPT_PAS = 7'd31; - localparam logic [6:0] __const__OPT_MUL_SUB = 7'd19; - localparam logic [6:0] __const__OPT_SUB = 7'd4; - localparam logic [6:0] __const__OPT_START = 7'd0; - //------------------------------------------------------------- - // Component Fu0 - //------------------------------------------------------------- - - logic [0:0] Fu0__clear; - logic [0:0] Fu0__clk; - logic [0:0] Fu0__reset; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__from_mem_rdata__msg; - logic [0:0] Fu0__from_mem_rdata__rdy; - logic [0:0] Fu0__from_mem_rdata__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__recv_const__msg; - logic [0:0] Fu0__recv_const__rdy; - logic [0:0] Fu0__recv_const__val; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu0__recv_from_ctrl_mem__msg; - logic [0:0] Fu0__recv_from_ctrl_mem__rdy; - logic [0:0] Fu0__recv_from_ctrl_mem__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__recv_in__msg [0:3]; - logic [0:0] Fu0__recv_in__rdy [0:3]; - logic [0:0] Fu0__recv_in__val [0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu0__recv_opt__msg; - logic [0:0] Fu0__recv_opt__rdy; - logic [0:0] Fu0__recv_opt__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__send_out__msg [0:1]; - logic [0:0] Fu0__send_out__rdy [0:1]; - logic [0:0] Fu0__send_out__val [0:1]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu0__send_to_ctrl_mem__msg; - logic [0:0] Fu0__send_to_ctrl_mem__rdy; - logic [0:0] Fu0__send_to_ctrl_mem__val; - logic [6:0] Fu0__to_mem_raddr__msg; - logic [0:0] Fu0__to_mem_raddr__rdy; - logic [0:0] Fu0__to_mem_raddr__val; - logic [6:0] Fu0__to_mem_waddr__msg; - logic [0:0] Fu0__to_mem_waddr__rdy; - logic [0:0] Fu0__to_mem_waddr__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__to_mem_wdata__msg; - logic [0:0] Fu0__to_mem_wdata__rdy; - logic [0:0] Fu0__to_mem_wdata__val; - - MulRTL__903abe7e5de73fa1 Fu0 - ( - .clear( Fu0__clear ), - .clk( Fu0__clk ), - .reset( Fu0__reset ), - .from_mem_rdata__msg( Fu0__from_mem_rdata__msg ), - .from_mem_rdata__rdy( Fu0__from_mem_rdata__rdy ), - .from_mem_rdata__val( Fu0__from_mem_rdata__val ), - .recv_const__msg( Fu0__recv_const__msg ), - .recv_const__rdy( Fu0__recv_const__rdy ), - .recv_const__val( Fu0__recv_const__val ), - .recv_from_ctrl_mem__msg( Fu0__recv_from_ctrl_mem__msg ), - .recv_from_ctrl_mem__rdy( Fu0__recv_from_ctrl_mem__rdy ), - .recv_from_ctrl_mem__val( Fu0__recv_from_ctrl_mem__val ), - .recv_in__msg( Fu0__recv_in__msg ), - .recv_in__rdy( Fu0__recv_in__rdy ), - .recv_in__val( Fu0__recv_in__val ), - .recv_opt__msg( Fu0__recv_opt__msg ), - .recv_opt__rdy( Fu0__recv_opt__rdy ), - .recv_opt__val( Fu0__recv_opt__val ), - .send_out__msg( Fu0__send_out__msg ), - .send_out__rdy( Fu0__send_out__rdy ), - .send_out__val( Fu0__send_out__val ), - .send_to_ctrl_mem__msg( Fu0__send_to_ctrl_mem__msg ), - .send_to_ctrl_mem__rdy( Fu0__send_to_ctrl_mem__rdy ), - .send_to_ctrl_mem__val( Fu0__send_to_ctrl_mem__val ), - .to_mem_raddr__msg( Fu0__to_mem_raddr__msg ), - .to_mem_raddr__rdy( Fu0__to_mem_raddr__rdy ), - .to_mem_raddr__val( Fu0__to_mem_raddr__val ), - .to_mem_waddr__msg( Fu0__to_mem_waddr__msg ), - .to_mem_waddr__rdy( Fu0__to_mem_waddr__rdy ), - .to_mem_waddr__val( Fu0__to_mem_waddr__val ), - .to_mem_wdata__msg( Fu0__to_mem_wdata__msg ), - .to_mem_wdata__rdy( Fu0__to_mem_wdata__rdy ), - .to_mem_wdata__val( Fu0__to_mem_wdata__val ) - ); - - //------------------------------------------------------------- - // End of component Fu0 - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component Fu1 - //------------------------------------------------------------- - - logic [0:0] Fu1__clear; - logic [0:0] Fu1__clk; - logic [0:0] Fu1__reset; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__from_mem_rdata__msg; - logic [0:0] Fu1__from_mem_rdata__rdy; - logic [0:0] Fu1__from_mem_rdata__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__recv_const__msg; - logic [0:0] Fu1__recv_const__rdy; - logic [0:0] Fu1__recv_const__val; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu1__recv_from_ctrl_mem__msg; - logic [0:0] Fu1__recv_from_ctrl_mem__rdy; - logic [0:0] Fu1__recv_from_ctrl_mem__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__recv_in__msg [0:3]; - logic [0:0] Fu1__recv_in__rdy [0:3]; - logic [0:0] Fu1__recv_in__val [0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu1__recv_opt__msg; - logic [0:0] Fu1__recv_opt__rdy; - logic [0:0] Fu1__recv_opt__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__send_out__msg [0:1]; - logic [0:0] Fu1__send_out__rdy [0:1]; - logic [0:0] Fu1__send_out__val [0:1]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu1__send_to_ctrl_mem__msg; - logic [0:0] Fu1__send_to_ctrl_mem__rdy; - logic [0:0] Fu1__send_to_ctrl_mem__val; - logic [6:0] Fu1__to_mem_raddr__msg; - logic [0:0] Fu1__to_mem_raddr__rdy; - logic [0:0] Fu1__to_mem_raddr__val; - logic [6:0] Fu1__to_mem_waddr__msg; - logic [0:0] Fu1__to_mem_waddr__rdy; - logic [0:0] Fu1__to_mem_waddr__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__to_mem_wdata__msg; - logic [0:0] Fu1__to_mem_wdata__rdy; - logic [0:0] Fu1__to_mem_wdata__val; - - AdderRTL__903abe7e5de73fa1 Fu1 - ( - .clear( Fu1__clear ), - .clk( Fu1__clk ), - .reset( Fu1__reset ), - .from_mem_rdata__msg( Fu1__from_mem_rdata__msg ), - .from_mem_rdata__rdy( Fu1__from_mem_rdata__rdy ), - .from_mem_rdata__val( Fu1__from_mem_rdata__val ), - .recv_const__msg( Fu1__recv_const__msg ), - .recv_const__rdy( Fu1__recv_const__rdy ), - .recv_const__val( Fu1__recv_const__val ), - .recv_from_ctrl_mem__msg( Fu1__recv_from_ctrl_mem__msg ), - .recv_from_ctrl_mem__rdy( Fu1__recv_from_ctrl_mem__rdy ), - .recv_from_ctrl_mem__val( Fu1__recv_from_ctrl_mem__val ), - .recv_in__msg( Fu1__recv_in__msg ), - .recv_in__rdy( Fu1__recv_in__rdy ), - .recv_in__val( Fu1__recv_in__val ), - .recv_opt__msg( Fu1__recv_opt__msg ), - .recv_opt__rdy( Fu1__recv_opt__rdy ), - .recv_opt__val( Fu1__recv_opt__val ), - .send_out__msg( Fu1__send_out__msg ), - .send_out__rdy( Fu1__send_out__rdy ), - .send_out__val( Fu1__send_out__val ), - .send_to_ctrl_mem__msg( Fu1__send_to_ctrl_mem__msg ), - .send_to_ctrl_mem__rdy( Fu1__send_to_ctrl_mem__rdy ), - .send_to_ctrl_mem__val( Fu1__send_to_ctrl_mem__val ), - .to_mem_raddr__msg( Fu1__to_mem_raddr__msg ), - .to_mem_raddr__rdy( Fu1__to_mem_raddr__rdy ), - .to_mem_raddr__val( Fu1__to_mem_raddr__val ), - .to_mem_waddr__msg( Fu1__to_mem_waddr__msg ), - .to_mem_waddr__rdy( Fu1__to_mem_waddr__rdy ), - .to_mem_waddr__val( Fu1__to_mem_waddr__val ), - .to_mem_wdata__msg( Fu1__to_mem_wdata__msg ), - .to_mem_wdata__rdy( Fu1__to_mem_wdata__rdy ), - .to_mem_wdata__val( Fu1__to_mem_wdata__val ) - ); - - //------------------------------------------------------------- - // End of component Fu1 - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:90 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= AddrType(0) - // s.to_mem_raddr.msg @= AddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/double/SeqMulAdderRTL.py:32 - // @update - // def update_opt(): - // - // s.Fu0.recv_opt.msg @= s.recv_opt.msg - // s.Fu1.recv_opt.msg @= s.recv_opt.msg - // - // s.Fu0.recv_opt.msg.fu_in[0] @= 1 - // s.Fu0.recv_opt.msg.fu_in[1] @= 2 - // s.Fu1.recv_opt.msg.fu_in[0] @= 1 - // s.Fu1.recv_opt.msg.fu_in[1] @= 2 - // - // if s.recv_opt.msg.operation == OPT_MUL_ADD: - // s.Fu0.recv_opt.msg.operation @= OPT_MUL - // s.Fu1.recv_opt.msg.operation @= OPT_ADD - // elif s.recv_opt.msg.operation == OPT_MUL_CONST_ADD: - // s.Fu0.recv_opt.msg.operation @= OPT_MUL_CONST - // s.Fu1.recv_opt.msg.operation @= OPT_ADD - // elif s.recv_opt.msg.operation == OPT_MUL_CONST: - // s.Fu0.recv_opt.msg.operation @= OPT_MUL_CONST - // s.Fu1.recv_opt.msg.operation @= OPT_PAS - // elif s.recv_opt.msg.operation == OPT_MUL_SUB: - // s.Fu0.recv_opt.msg.operation @= OPT_MUL - // s.Fu1.recv_opt.msg.operation @= OPT_SUB - // else: - // # Indicates no computation should happen no this fused FU. - // # This is necessary to avoid the OPT_MUL_CONST be executed - // # by both Mul and MulAdder. - // s.Fu0.recv_opt.msg.operation @= OPT_START - // s.Fu1.recv_opt.msg.operation @= OPT_START - // - // # TODO: need to handle the other cases - - always_comb begin : update_opt - Fu0__recv_opt__msg = recv_opt__msg; - Fu1__recv_opt__msg = recv_opt__msg; - Fu0__recv_opt__msg.fu_in[2'd0] = 3'd1; - Fu0__recv_opt__msg.fu_in[2'd1] = 3'd2; - Fu1__recv_opt__msg.fu_in[2'd0] = 3'd1; - Fu1__recv_opt__msg.fu_in[2'd1] = 3'd2; - if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_ADD ) ) begin - Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL ); - Fu1__recv_opt__msg.operation = 7'( __const__OPT_ADD ); - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST_ADD ) ) begin - Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL_CONST ); - Fu1__recv_opt__msg.operation = 7'( __const__OPT_ADD ); - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin - Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL_CONST ); - Fu1__recv_opt__msg.operation = 7'( __const__OPT_PAS ); - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_SUB ) ) begin - Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL ); - Fu1__recv_opt__msg.operation = 7'( __const__OPT_SUB ); - end - else begin - Fu0__recv_opt__msg.operation = 7'( __const__OPT_START ); - Fu1__recv_opt__msg.operation = 7'( __const__OPT_START ); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:100 - // @update - // def update_send_to_controller(): - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - - always_comb begin : update_send_to_controller - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:68 - // @update - // def update_signal(): - // - // s.recv_in[0].rdy @= s.Fu0.recv_in[0].rdy - // s.recv_in[1].rdy @= s.Fu0.recv_in[1].rdy - // s.recv_in[2].rdy @= s.Fu1.recv_in[1].rdy - // - // s.Fu0.recv_in[0].val @= s.recv_in[0].val - // s.Fu0.recv_in[1].val @= s.recv_in[1].val - // s.Fu1.recv_in[0].val @= s.Fu0.send_out[0].val - // s.Fu1.recv_in[1].val @= s.recv_in[2].val - // - // s.Fu0.recv_opt.val @= s.recv_opt.val - // s.Fu1.recv_opt.val @= s.recv_opt.val - // - // s.recv_opt.rdy @= s.Fu0.recv_opt.rdy & s.Fu1.recv_opt.rdy - // - // s.send_out[0].val @= s.Fu1.send_out[0].val - // - // s.Fu0.send_out[0].rdy @= s.Fu1.recv_in[0].rdy - // s.Fu1.send_out[0].rdy @= s.send_out[0].rdy - - always_comb begin : update_signal - recv_in__rdy[2'd0] = Fu0__recv_in__rdy[2'd0]; - recv_in__rdy[2'd1] = Fu0__recv_in__rdy[2'd1]; - recv_in__rdy[2'd2] = Fu1__recv_in__rdy[2'd1]; - Fu0__recv_in__val[2'd0] = recv_in__val[2'd0]; - Fu0__recv_in__val[2'd1] = recv_in__val[2'd1]; - Fu1__recv_in__val[2'd0] = Fu0__send_out__val[1'd0]; - Fu1__recv_in__val[2'd1] = recv_in__val[2'd2]; - Fu0__recv_opt__val = recv_opt__val; - Fu1__recv_opt__val = recv_opt__val; - recv_opt__rdy = Fu0__recv_opt__rdy & Fu1__recv_opt__rdy; - send_out__val[1'd0] = Fu1__send_out__val[1'd0]; - Fu0__send_out__rdy[1'd0] = Fu1__recv_in__rdy[2'd0]; - Fu1__send_out__rdy[1'd0] = send_out__rdy[1'd0]; - end - - assign Fu0__clk = clk; - assign Fu0__reset = reset; - assign Fu1__clk = clk; - assign Fu1__reset = reset; - assign Fu0__recv_in__msg[0] = recv_in__msg[0]; - assign Fu0__recv_in__msg[1] = recv_in__msg[1]; - assign Fu1__recv_in__msg[1] = recv_in__msg[2]; - assign Fu1__recv_in__msg[0] = Fu0__send_out__msg[0]; - assign send_out__msg[0] = Fu1__send_out__msg[0]; - assign Fu0__recv_const__msg = recv_const__msg; - assign recv_const__rdy = Fu0__recv_const__rdy; - assign Fu0__recv_const__val = recv_const__val; - -endmodule - - -// PyMTL Component VectorMulRTL Definition -// Full name: VectorMulRTL__bw_16__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulRTL.py - -module VectorMulRTL__848c3e0c53bb478c -( - input logic [0:0] clk , - input logic [0:0] reset , - input logic [31:0] recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input logic [31:0] recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output logic [31:0] send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] -); - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_MUL = 7'd7; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] recv_all_val; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulRTL.py:55 - // @update - // def comb_logic(): - // s.recv_all_val @= 0 - // # Picks input register. - // s.in0 @= FuInType(0) - // s.in1 @= FuInType(0) - // - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range( num_outports ): - // s.send_out[i].val @= b1(0) - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_MUL: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg * s.recv_in[s.in1_idx].msg - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = 32'd0; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin - send_out__msg[1'd0] = recv_in__msg[in0_idx] * recv_in__msg[in1_idx]; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component VectorMulComboRTL Definition -// Full name: VectorMulComboRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py - -module VectorMulComboRTL__e2d25a29972e2033 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [1:0] __const__num_outports_at_update_input_output = 2'd2; - localparam logic [2:0] __const__num_lanes_at_update_input_output = 3'd4; - localparam logic [6:0] __const__OPT_VEC_MUL = 7'd55; - localparam logic [4:0] __const__sub_bw_at_update_input_output = 5'd16; - localparam logic [5:0] __const__sub_bw_2_at_update_input_output = 6'd32; - localparam logic [5:0] __const__sub_bw_3_at_update_input_output = 6'd48; - localparam logic [6:0] __const__sub_bw_4_at_update_input_output = 7'd64; - localparam logic [6:0] __const__data_bitwidth_at_update_input_output = 7'd64; - localparam logic [6:0] __const__OPT_VEC_MUL_COMBINED = 7'd75; - localparam logic [2:0] __const__num_lanes_at_update_signal = 3'd4; - localparam logic [1:0] __const__num_outports_at_update_signal = 2'd2; - localparam logic [2:0] __const__num_lanes_at_update_opt = 3'd4; - localparam logic [6:0] __const__OPT_NAH = 7'd1; - localparam logic [6:0] __const__OPT_MUL = 7'd7; - logic [63:0] temp_result [0:3]; - //------------------------------------------------------------- - // Component Fu[0:3] - //------------------------------------------------------------- - - logic [0:0] Fu__clk [0:3]; - logic [0:0] Fu__reset [0:3]; - logic [31:0] Fu__recv_const__msg [0:3]; - logic [0:0] Fu__recv_const__rdy [0:3]; - logic [0:0] Fu__recv_const__val [0:3]; - logic [31:0] Fu__recv_in__msg [0:3][0:3]; - logic [0:0] Fu__recv_in__rdy [0:3][0:3]; - logic [0:0] Fu__recv_in__val [0:3][0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu__recv_opt__msg [0:3]; - logic [0:0] Fu__recv_opt__rdy [0:3]; - logic [0:0] Fu__recv_opt__val [0:3]; - logic [31:0] Fu__send_out__msg [0:3][0:1]; - logic [0:0] Fu__send_out__rdy [0:3][0:1]; - logic [0:0] Fu__send_out__val [0:3][0:1]; - - VectorMulRTL__848c3e0c53bb478c Fu__0 - ( - .clk( Fu__clk[0] ), - .reset( Fu__reset[0] ), - .recv_const__msg( Fu__recv_const__msg[0] ), - .recv_const__rdy( Fu__recv_const__rdy[0] ), - .recv_const__val( Fu__recv_const__val[0] ), - .recv_in__msg( Fu__recv_in__msg[0] ), - .recv_in__rdy( Fu__recv_in__rdy[0] ), - .recv_in__val( Fu__recv_in__val[0] ), - .recv_opt__msg( Fu__recv_opt__msg[0] ), - .recv_opt__rdy( Fu__recv_opt__rdy[0] ), - .recv_opt__val( Fu__recv_opt__val[0] ), - .send_out__msg( Fu__send_out__msg[0] ), - .send_out__rdy( Fu__send_out__rdy[0] ), - .send_out__val( Fu__send_out__val[0] ) - ); - - VectorMulRTL__848c3e0c53bb478c Fu__1 - ( - .clk( Fu__clk[1] ), - .reset( Fu__reset[1] ), - .recv_const__msg( Fu__recv_const__msg[1] ), - .recv_const__rdy( Fu__recv_const__rdy[1] ), - .recv_const__val( Fu__recv_const__val[1] ), - .recv_in__msg( Fu__recv_in__msg[1] ), - .recv_in__rdy( Fu__recv_in__rdy[1] ), - .recv_in__val( Fu__recv_in__val[1] ), - .recv_opt__msg( Fu__recv_opt__msg[1] ), - .recv_opt__rdy( Fu__recv_opt__rdy[1] ), - .recv_opt__val( Fu__recv_opt__val[1] ), - .send_out__msg( Fu__send_out__msg[1] ), - .send_out__rdy( Fu__send_out__rdy[1] ), - .send_out__val( Fu__send_out__val[1] ) - ); - - VectorMulRTL__848c3e0c53bb478c Fu__2 - ( - .clk( Fu__clk[2] ), - .reset( Fu__reset[2] ), - .recv_const__msg( Fu__recv_const__msg[2] ), - .recv_const__rdy( Fu__recv_const__rdy[2] ), - .recv_const__val( Fu__recv_const__val[2] ), - .recv_in__msg( Fu__recv_in__msg[2] ), - .recv_in__rdy( Fu__recv_in__rdy[2] ), - .recv_in__val( Fu__recv_in__val[2] ), - .recv_opt__msg( Fu__recv_opt__msg[2] ), - .recv_opt__rdy( Fu__recv_opt__rdy[2] ), - .recv_opt__val( Fu__recv_opt__val[2] ), - .send_out__msg( Fu__send_out__msg[2] ), - .send_out__rdy( Fu__send_out__rdy[2] ), - .send_out__val( Fu__send_out__val[2] ) - ); - - VectorMulRTL__848c3e0c53bb478c Fu__3 - ( - .clk( Fu__clk[3] ), - .reset( Fu__reset[3] ), - .recv_const__msg( Fu__recv_const__msg[3] ), - .recv_const__rdy( Fu__recv_const__rdy[3] ), - .recv_const__val( Fu__recv_const__val[3] ), - .recv_in__msg( Fu__recv_in__msg[3] ), - .recv_in__rdy( Fu__recv_in__rdy[3] ), - .recv_in__val( Fu__recv_in__val[3] ), - .recv_opt__msg( Fu__recv_opt__msg[3] ), - .recv_opt__rdy( Fu__recv_opt__rdy[3] ), - .recv_opt__val( Fu__recv_opt__val[3] ), - .send_out__msg( Fu__send_out__msg[3] ), - .send_out__rdy( Fu__send_out__rdy[3] ), - .send_out__val( Fu__send_out__val[3] ) - ); - - //------------------------------------------------------------- - // End of component Fu[0:3] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:80 - // @update - // def update_input_output(): - // - // # Initialization to avoid latches - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // - // s.send_out[0].val @= s.Fu[0].send_out[0].val & \ - // s.recv_opt.val - // s.send_out[0].msg.payload @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // - // s.recv_from_ctrl_mem.rdy @= 0 - // - // for i in range(num_lanes): - // s.temp_result[i] @= TempDataType(0) - // s.Fu[i].recv_in[0].msg @= 0 - // s.Fu[i].recv_in[1].msg @= 0 - // - // if s.recv_opt.msg.operation == OPT_VEC_MUL: - // # Connection: split into vectorized FUs - // s.Fu[0].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] - // s.Fu[0].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] - // s.Fu[1].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] - // s.Fu[1].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] - // s.Fu[2].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw_2:sub_bw_3] - // s.Fu[2].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw_2:sub_bw_3] - // s.Fu[3].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw_3:sub_bw_4] - // s.Fu[3].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw_3:sub_bw_4] - // - // for i in range(num_lanes): - // s.temp_result[i] @= TempDataType(0) - // s.temp_result[i][0:sub_bw_2] @= s.Fu[i].send_out[0].msg[0:sub_bw_2] - // - // s.send_out[0].msg.payload[0:data_bitwidth] @= \ - // (s.temp_result[3] << (sub_bw * 3)) + \ - // (s.temp_result[2] << (sub_bw * 2)) + \ - // (s.temp_result[1] << sub_bw) + \ - // s.temp_result[0] - // - // elif s.recv_opt.msg.operation == OPT_VEC_MUL_COMBINED: # with highest precision - // s.Fu[0].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] - // s.Fu[0].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] - // s.Fu[1].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] - // s.Fu[1].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] - // s.Fu[2].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] - // s.Fu[2].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] - // s.Fu[3].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] - // s.Fu[3].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] - // - // for i in range(num_lanes): - // s.temp_result[i] @= TempDataType(0) - // s.temp_result[i][0:sub_bw_2] @= s.Fu[i].send_out[0].msg[0:sub_bw_2] - // - // s.send_out[0].msg.payload[0:data_bitwidth] @= \ - // s.temp_result[0] + \ - // (s.temp_result[1] << sub_bw) + \ - // (s.temp_result[2] << sub_bw) + \ - // (s.temp_result[3] << (sub_bw * 2)) - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - - always_comb begin : update_input_output - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_input_output ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - send_out__val[1'd0] = Fu__send_out__val[2'd0][1'd0] & recv_opt__val; - send_out__msg[1'd0].payload = 64'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin - temp_result[2'(i)] = 64'd0; - Fu__recv_in__msg[2'(i)][2'd0] = 32'd0; - Fu__recv_in__msg[2'(i)][2'd1] = 32'd0; - end - if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL ) ) begin - Fu__recv_in__msg[2'd0][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd0][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd1][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - Fu__recv_in__msg[2'd1][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - Fu__recv_in__msg[2'd2][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd47:6'( __const__sub_bw_2_at_update_input_output )]; - Fu__recv_in__msg[2'd2][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd47:6'( __const__sub_bw_2_at_update_input_output )]; - Fu__recv_in__msg[2'd3][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd63:6'( __const__sub_bw_3_at_update_input_output )]; - Fu__recv_in__msg[2'd3][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd63:6'( __const__sub_bw_3_at_update_input_output )]; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin - temp_result[2'(i)] = 64'd0; - temp_result[2'(i)][6'd31:6'd0] = Fu__send_out__msg[2'(i)][1'd0][5'd31:5'd0]; - end - send_out__msg[1'd0].payload[6'd63:6'd0] = ( ( ( temp_result[2'd3] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd3 ) ) + ( temp_result[2'd2] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd2 ) ) ) + ( temp_result[2'd1] << 5'( __const__sub_bw_at_update_input_output ) ) ) + temp_result[2'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL_COMBINED ) ) begin - Fu__recv_in__msg[2'd0][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd0][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd1][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd1][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - Fu__recv_in__msg[2'd2][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - Fu__recv_in__msg[2'd2][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd3][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - Fu__recv_in__msg[2'd3][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin - temp_result[2'(i)] = 64'd0; - temp_result[2'(i)][6'd31:6'd0] = Fu__send_out__msg[2'(i)][1'd0][5'd31:5'd0]; - end - send_out__msg[1'd0].payload[6'd63:6'd0] = ( ( temp_result[2'd0] + ( temp_result[2'd1] << 5'( __const__sub_bw_at_update_input_output ) ) ) + ( temp_result[2'd2] << 5'( __const__sub_bw_at_update_input_output ) ) ) + ( temp_result[2'd3] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd2 ) ); - end - else - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_input_output ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:183 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= AddrType(0) - // s.to_mem_raddr.msg @= AddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:168 - // @update - // def update_opt(): - // s.send_out[0].msg.predicate @= b1(0) - // - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.fu_in[0] @= 1 - // s.Fu[i].recv_opt.msg.fu_in[1] @= 2 - // s.Fu[i].recv_opt.msg.operation @= OPT_NAH - // - // if (s.recv_opt.msg.operation == OPT_VEC_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_MUL_COMBINED): - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.operation @= OPT_MUL - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate - - always_comb begin : update_opt - send_out__msg[1'd0].predicate = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].fu_in[2'd0] = 3'd1; - Fu__recv_opt__msg[2'(i)].fu_in[2'd1] = 3'd2; - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_NAH ); - end - if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL_COMBINED ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_MUL ); - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:146 - // @update - // def update_signal(): - // s.recv_in[0].rdy @= s.Fu[0].recv_in[0].rdy - // s.recv_in[1].rdy @= s.Fu[0].recv_in[1].rdy - // - // for i in range(num_lanes): - // s.Fu[i].recv_opt.val @= s.recv_opt.val - // - // # Note that the predication for a combined FU should be identical/shareable, - // # which means the computation in different basic block cannot be combined. - // # s.Fu[i].recv_opt.msg.predicate = s.recv_opt.msg.predicate - // - // s.Fu[i].recv_in[0].val @= s.recv_in[0].val - // s.Fu[i].recv_in[1].val @= s.recv_in[1].val - // s.Fu[i].recv_const.val @= s.recv_const.val - // - // for j in range(num_outports): - // s.Fu[i].send_out[j].rdy @= s.send_out[j].rdy - // - // s.recv_const.rdy @= s.Fu[0].recv_const.rdy - // s.recv_opt.rdy @= s.send_out[0].rdy - - always_comb begin : update_signal - recv_in__rdy[2'd0] = Fu__recv_in__rdy[2'd0][2'd0]; - recv_in__rdy[2'd1] = Fu__recv_in__rdy[2'd0][2'd1]; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_signal ); i += 1'd1 ) begin - Fu__recv_opt__val[2'(i)] = recv_opt__val; - Fu__recv_in__val[2'(i)][2'd0] = recv_in__val[2'd0]; - Fu__recv_in__val[2'(i)][2'd1] = recv_in__val[2'd1]; - Fu__recv_const__val[2'(i)] = recv_const__val; - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_signal ); j += 1'd1 ) - Fu__send_out__rdy[2'(i)][1'(j)] = send_out__rdy[1'(j)]; - end - recv_const__rdy = Fu__recv_const__rdy[2'd0]; - recv_opt__rdy = send_out__rdy[1'd0]; - end - - assign Fu__clk[0] = clk; - assign Fu__reset[0] = reset; - assign Fu__clk[1] = clk; - assign Fu__reset[1] = reset; - assign Fu__clk[2] = clk; - assign Fu__reset[2] = reset; - assign Fu__clk[3] = clk; - assign Fu__reset[3] = reset; - -endmodule - - -// PyMTL Component VectorAdderRTL Definition -// Full name: VectorAdderRTL__bw_16__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderRTL.py - -module VectorAdderRTL__848c3e0c53bb478c -( - input logic [0:0] carry_in , - output logic [0:0] carry_out , - input logic [0:0] clk , - input logic [0:0] combine_adder , - input logic [0:0] reset , - input logic [16:0] recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input logic [16:0] recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output logic [16:0] send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] -); - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_ADD = 7'd2; - localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; - localparam logic [6:0] __const__OPT_INC = 7'd3; - localparam logic [6:0] __const__OPT_SUB = 7'd4; - localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; - localparam logic [6:0] __const__OPT_PAS = 7'd31; - localparam logic [4:0] __const__bw_at_comb_logic = 5'd16; - logic [16:0] carry_in_temp; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] recv_all_val; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderRTL.py:58 - // @update - // def comb_logic(): - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= b1(0) - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.carry_in_temp[0] @= s.carry_in & s.combine_adder - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_ADD: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.recv_in[s.in1_idx].msg + s.carry_in_temp - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_ADD_CONST: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.recv_const.msg + s.carry_in_temp - // s.recv_const.rdy @= s.send_out[0].rdy - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_INC: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.const_one - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - s.recv_in[s.in1_idx].msg - s.carry_in_temp - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB_CONST: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - s.recv_const.msg - s.carry_in_temp - // s.recv_const.rdy @= s.send_out[0].rdy - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_PAS: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - // - // s.carry_out @= s.send_out[0].msg[bw:bw+1] - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = 17'd0; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - carry_in_temp[5'd0] = carry_in & combine_adder; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin - send_out__msg[1'd0] = ( recv_in__msg[in0_idx] + recv_in__msg[in1_idx] ) + carry_in_temp; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin - send_out__msg[1'd0] = ( recv_in__msg[in0_idx] + recv_const__msg ) + carry_in_temp; - recv_const__rdy = send_out__rdy[1'd0]; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin - send_out__msg[1'd0] = recv_in__msg[in0_idx] + 17'd1; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin - send_out__msg[1'd0] = ( recv_in__msg[in0_idx] - recv_in__msg[in1_idx] ) - carry_in_temp; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin - send_out__msg[1'd0] = ( recv_in__msg[in0_idx] - recv_const__msg ) - carry_in_temp; - recv_const__rdy = send_out__rdy[1'd0]; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin - send_out__msg[1'd0] = recv_in__msg[in0_idx]; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - carry_out = send_out__msg[1'd0][5'd16:5'( __const__bw_at_comb_logic )]; - end - - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component VectorAdderComboRTL Definition -// Full name: VectorAdderComboRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py - -module VectorAdderComboRTL__e2d25a29972e2033 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [2:0] __const__num_lanes_at_update_signal = 3'd4; - localparam logic [1:0] __const__num_outports_at_update_signal = 2'd2; - localparam logic [1:0] __const__num_outports_at_update_opt = 2'd2; - localparam logic [2:0] __const__num_lanes_at_update_opt = 3'd4; - localparam logic [6:0] __const__OPT_NAH = 7'd1; - localparam logic [6:0] __const__OPT_VEC_ADD = 7'd51; - localparam logic [6:0] __const__OPT_VEC_ADD_COMBINED = 7'd71; - localparam logic [6:0] __const__OPT_ADD = 7'd2; - localparam logic [6:0] __const__OPT_VEC_SUB = 7'd53; - localparam logic [6:0] __const__OPT_VEC_SUB_COMBINED = 7'd73; - localparam logic [6:0] __const__OPT_SUB = 7'd4; - localparam logic [6:0] __const__OPT_VEC_ADD_CONST = 7'd52; - localparam logic [6:0] __const__OPT_VEC_ADD_CONST_COMBINED = 7'd72; - localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; - localparam logic [6:0] __const__OPT_VEC_SUB_CONST = 7'd54; - localparam logic [6:0] __const__OPT_VEC_SUB_CONST_COMBINED = 7'd74; - localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; - //------------------------------------------------------------- - // Component Fu[0:3] - //------------------------------------------------------------- - - logic [0:0] Fu__carry_in [0:3]; - logic [0:0] Fu__carry_out [0:3]; - logic [0:0] Fu__clk [0:3]; - logic [0:0] Fu__combine_adder [0:3]; - logic [0:0] Fu__reset [0:3]; - logic [16:0] Fu__recv_const__msg [0:3]; - logic [0:0] Fu__recv_const__rdy [0:3]; - logic [0:0] Fu__recv_const__val [0:3]; - logic [16:0] Fu__recv_in__msg [0:3][0:3]; - logic [0:0] Fu__recv_in__rdy [0:3][0:3]; - logic [0:0] Fu__recv_in__val [0:3][0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu__recv_opt__msg [0:3]; - logic [0:0] Fu__recv_opt__rdy [0:3]; - logic [0:0] Fu__recv_opt__val [0:3]; - logic [16:0] Fu__send_out__msg [0:3][0:1]; - logic [0:0] Fu__send_out__rdy [0:3][0:1]; - logic [0:0] Fu__send_out__val [0:3][0:1]; - - VectorAdderRTL__848c3e0c53bb478c Fu__0 - ( - .carry_in( Fu__carry_in[0] ), - .carry_out( Fu__carry_out[0] ), - .clk( Fu__clk[0] ), - .combine_adder( Fu__combine_adder[0] ), - .reset( Fu__reset[0] ), - .recv_const__msg( Fu__recv_const__msg[0] ), - .recv_const__rdy( Fu__recv_const__rdy[0] ), - .recv_const__val( Fu__recv_const__val[0] ), - .recv_in__msg( Fu__recv_in__msg[0] ), - .recv_in__rdy( Fu__recv_in__rdy[0] ), - .recv_in__val( Fu__recv_in__val[0] ), - .recv_opt__msg( Fu__recv_opt__msg[0] ), - .recv_opt__rdy( Fu__recv_opt__rdy[0] ), - .recv_opt__val( Fu__recv_opt__val[0] ), - .send_out__msg( Fu__send_out__msg[0] ), - .send_out__rdy( Fu__send_out__rdy[0] ), - .send_out__val( Fu__send_out__val[0] ) - ); - - VectorAdderRTL__848c3e0c53bb478c Fu__1 - ( - .carry_in( Fu__carry_in[1] ), - .carry_out( Fu__carry_out[1] ), - .clk( Fu__clk[1] ), - .combine_adder( Fu__combine_adder[1] ), - .reset( Fu__reset[1] ), - .recv_const__msg( Fu__recv_const__msg[1] ), - .recv_const__rdy( Fu__recv_const__rdy[1] ), - .recv_const__val( Fu__recv_const__val[1] ), - .recv_in__msg( Fu__recv_in__msg[1] ), - .recv_in__rdy( Fu__recv_in__rdy[1] ), - .recv_in__val( Fu__recv_in__val[1] ), - .recv_opt__msg( Fu__recv_opt__msg[1] ), - .recv_opt__rdy( Fu__recv_opt__rdy[1] ), - .recv_opt__val( Fu__recv_opt__val[1] ), - .send_out__msg( Fu__send_out__msg[1] ), - .send_out__rdy( Fu__send_out__rdy[1] ), - .send_out__val( Fu__send_out__val[1] ) - ); - - VectorAdderRTL__848c3e0c53bb478c Fu__2 - ( - .carry_in( Fu__carry_in[2] ), - .carry_out( Fu__carry_out[2] ), - .clk( Fu__clk[2] ), - .combine_adder( Fu__combine_adder[2] ), - .reset( Fu__reset[2] ), - .recv_const__msg( Fu__recv_const__msg[2] ), - .recv_const__rdy( Fu__recv_const__rdy[2] ), - .recv_const__val( Fu__recv_const__val[2] ), - .recv_in__msg( Fu__recv_in__msg[2] ), - .recv_in__rdy( Fu__recv_in__rdy[2] ), - .recv_in__val( Fu__recv_in__val[2] ), - .recv_opt__msg( Fu__recv_opt__msg[2] ), - .recv_opt__rdy( Fu__recv_opt__rdy[2] ), - .recv_opt__val( Fu__recv_opt__val[2] ), - .send_out__msg( Fu__send_out__msg[2] ), - .send_out__rdy( Fu__send_out__rdy[2] ), - .send_out__val( Fu__send_out__val[2] ) - ); - - VectorAdderRTL__848c3e0c53bb478c Fu__3 - ( - .carry_in( Fu__carry_in[3] ), - .carry_out( Fu__carry_out[3] ), - .clk( Fu__clk[3] ), - .combine_adder( Fu__combine_adder[3] ), - .reset( Fu__reset[3] ), - .recv_const__msg( Fu__recv_const__msg[3] ), - .recv_const__rdy( Fu__recv_const__rdy[3] ), - .recv_const__val( Fu__recv_const__val[3] ), - .recv_in__msg( Fu__recv_in__msg[3] ), - .recv_in__rdy( Fu__recv_in__rdy[3] ), - .recv_in__val( Fu__recv_in__val[3] ), - .recv_opt__msg( Fu__recv_opt__msg[3] ), - .recv_opt__rdy( Fu__recv_opt__rdy[3] ), - .recv_opt__val( Fu__recv_opt__val[3] ), - .send_out__msg( Fu__send_out__msg[3] ), - .send_out__rdy( Fu__send_out__rdy[3] ), - .send_out__val( Fu__send_out__val[3] ) - ); - - //------------------------------------------------------------- - // End of component Fu[0:3] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:158 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= AddrType(0) - // s.to_mem_raddr.msg @= AddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:108 - // @update - // def update_opt(): - // - // for j in range( num_outports ): - // s.send_out[j].val @= b1(0) - // s.send_out[j].msg.predicate @= b1(0) - // - // s.send_out[0].val @= s.Fu[0].send_out[0].val & \ - // s.recv_opt.val - // - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.fu_in[0] @= 1 - // s.Fu[i].recv_opt.msg.fu_in[1] @= 2 - // s.Fu[i].recv_opt.msg.operation @= OPT_NAH - // s.Fu[i].combine_adder @= 0 - // - // if ( s.recv_opt.msg.operation == OPT_VEC_ADD ) | \ - // ( s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED ): - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.operation @= OPT_ADD - // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED) - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate - // - // elif ( s.recv_opt.msg.operation == OPT_VEC_SUB ) | \ - // ( s.recv_opt.msg.operation == OPT_VEC_SUB_COMBINED ): - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.operation @= OPT_SUB - // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_SUB_COMBINED) - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate - // - // # elif ( s.recv_opt.msg.operation == OPT_VEC_ADD_CONST ) | \ - // # ( s.recv_opt.msg.operation == OPT_ADD_CONST ): - // elif (s.recv_opt.msg.operation == OPT_VEC_ADD_CONST) | \ - // (s.recv_opt.msg.operation == OPT_VEC_ADD_CONST_COMBINED): - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.operation @= OPT_ADD_CONST - // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED) - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate - // - // elif (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST ) | \ - // (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST_COMBINED ): - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.operation @= OPT_SUB_CONST - // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST_COMBINED) - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - - always_comb begin : update_opt - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_opt ); j += 1'd1 ) begin - send_out__val[1'(j)] = 1'd0; - send_out__msg[1'(j)].predicate = 1'd0; - end - send_out__val[1'd0] = Fu__send_out__val[2'd0][1'd0] & recv_opt__val; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].fu_in[2'd0] = 3'd1; - Fu__recv_opt__msg[2'(i)].fu_in[2'd1] = 3'd2; - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_NAH ); - Fu__combine_adder[2'(i)] = 1'd0; - end - if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_ADD ); - Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ); - end - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_COMBINED ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_SUB ); - Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_COMBINED ); - end - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_CONST_COMBINED ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_ADD_CONST ); - Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ); - end - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST_COMBINED ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_SUB_CONST ); - Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST_COMBINED ); - end - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; - end - else - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_opt ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:82 - // @update - // def update_signal(): - // s.recv_in[0].rdy @= s.Fu[0].recv_in[0].rdy - // s.recv_in[1].rdy @= s.Fu[0].recv_in[1].rdy - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // - // s.recv_from_ctrl_mem.rdy @= 0 - // - // for i in range(num_lanes): - // s.Fu[i].recv_opt.val @= s.recv_opt.val - // - // for j in range(num_outports): - // s.Fu[i].send_out[j].rdy @= s.send_out[j].rdy - // - // s.Fu[i].recv_in[0].val @= s.recv_in[0].val - // s.Fu[i].recv_in[1].val @= s.recv_in[1].val - // s.Fu[i].recv_const.val @= s.recv_const.val - // - // # Note that the predication for a combined FU should be identical/shareable, - // # which means the computation in different basic block cannot be combined. - // # s.Fu[i].recv_opt.msg.predicate = s.recv_opt.msg.predicate - // s.recv_const.rdy @= s.Fu[0].recv_const.rdy - // s.recv_opt.rdy @= s.Fu[0].recv_opt.rdy - - always_comb begin : update_signal - recv_in__rdy[2'd0] = Fu__recv_in__rdy[2'd0][2'd0]; - recv_in__rdy[2'd1] = Fu__recv_in__rdy[2'd0][2'd1]; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_signal ); i += 1'd1 ) begin - Fu__recv_opt__val[2'(i)] = recv_opt__val; - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_signal ); j += 1'd1 ) - Fu__send_out__rdy[2'(i)][1'(j)] = send_out__rdy[1'(j)]; - Fu__recv_in__val[2'(i)][2'd0] = recv_in__val[2'd0]; - Fu__recv_in__val[2'(i)][2'd1] = recv_in__val[2'd1]; - Fu__recv_const__val[2'(i)] = recv_const__val; - end - recv_const__rdy = Fu__recv_const__rdy[2'd0]; - recv_opt__rdy = Fu__recv_opt__rdy[2'd0]; - end - - assign Fu__clk[0] = clk; - assign Fu__reset[0] = reset; - assign Fu__clk[1] = clk; - assign Fu__reset[1] = reset; - assign Fu__clk[2] = clk; - assign Fu__reset[2] = reset; - assign Fu__clk[3] = clk; - assign Fu__reset[3] = reset; - assign Fu__carry_in[0] = 1'd0; - assign Fu__carry_in[1] = Fu__carry_out[0]; - assign Fu__carry_in[2] = Fu__carry_out[1]; - assign Fu__carry_in[3] = Fu__carry_out[2]; - assign Fu__recv_in__msg[0][0][15:0] = recv_in__msg[0].payload[15:0]; - assign Fu__recv_in__msg[0][1][15:0] = recv_in__msg[1].payload[15:0]; - assign Fu__recv_const__msg[0][15:0] = recv_const__msg.payload[15:0]; - assign send_out__msg[0].payload[15:0] = Fu__send_out__msg[0][0][15:0]; - assign Fu__recv_in__msg[1][0][15:0] = recv_in__msg[0].payload[31:16]; - assign Fu__recv_in__msg[1][1][15:0] = recv_in__msg[1].payload[31:16]; - assign Fu__recv_const__msg[1][15:0] = recv_const__msg.payload[31:16]; - assign send_out__msg[0].payload[31:16] = Fu__send_out__msg[1][0][15:0]; - assign Fu__recv_in__msg[2][0][15:0] = recv_in__msg[0].payload[47:32]; - assign Fu__recv_in__msg[2][1][15:0] = recv_in__msg[1].payload[47:32]; - assign Fu__recv_const__msg[2][15:0] = recv_const__msg.payload[47:32]; - assign send_out__msg[0].payload[47:32] = Fu__send_out__msg[2][0][15:0]; - assign Fu__recv_in__msg[3][0][15:0] = recv_in__msg[0].payload[63:48]; - assign Fu__recv_in__msg[3][1][15:0] = recv_in__msg[1].payload[63:48]; - assign Fu__recv_const__msg[3][15:0] = recv_const__msg.payload[63:48]; - assign send_out__msg[0].payload[63:48] = Fu__send_out__msg[3][0][15:0]; - -endmodule - - -// PyMTL Component SumUnit Definition -// At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py - -module SumUnit__DataType_Bits64__num_inputs_4 -( - input logic [0:0] clk , - input logic [63:0] in_ [0:3], - output logic [63:0] out , - input logic [0:0] reset -); - logic [63:0] partial_sum [0:3]; - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py:37 - // s.out //= lambda: s.partial_sum[s.num_inputs-1] - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_out - out = partial_sum[3'd4 - 3'd1]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py:31 - // @update - // def up_sum(): - // s.partial_sum[0] @= s.in_[0] - // for i in range( 1, s.num_inputs ): - // s.partial_sum[i] @= s.partial_sum[i-1] + s.in_[i] - - always_comb begin : up_sum - partial_sum[2'd0] = in_[2'd0]; - for ( int unsigned i = 1'd1; i < 3'd4; i += 1'd1 ) - partial_sum[2'(i)] = partial_sum[2'(i) - 2'd1] + in_[2'(i)]; - end - -endmodule - - -// PyMTL Component ReduceMulUnit Definition -// At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/ReduceMulUnit.py - -module ReduceMulUnit__DataType_Bits64__num_inputs_4 -( - input logic [0:0] clk , - input logic [63:0] in_ [0:3], - output logic [63:0] out , - input logic [0:0] reset -); - logic [63:0] partial_sum [0:3]; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/ReduceMulUnit.py:32 - // @update - // def up_sum(): - // s.partial_sum[0] @= s.in_[0] - // for i in range( 1, s.num_inputs ): - // s.partial_sum[i] @= s.partial_sum[i-1] * s.in_[i] - - always_comb begin : up_sum - partial_sum[2'd0] = in_[2'd0]; - for ( int unsigned i = 1'd1; i < 3'd4; i += 1'd1 ) - partial_sum[2'(i)] = partial_sum[2'(i) - 2'd1] * in_[2'(i)]; - end - - assign out = partial_sum[3]; - -endmodule - - -// PyMTL Component VectorAllReduceRTL Definition -// Full name: VectorAllReduceRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py - -module VectorAllReduceRTL__e2d25a29972e2033 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD = 7'd56; - localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_BASE = 7'd68; - localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_GLOBAL = 7'd76; - localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL = 7'd78; - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ = 1'd0; - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ = 1'd1; - localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ = 2'd2; - localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ = 2'd3; - localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL = 7'd57; - localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_BASE = 7'd69; - localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_GLOBAL = 7'd77; - localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL = 7'd79; - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ = 1'd0; - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ = 1'd1; - localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ = 2'd2; - localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ = 2'd3; - localparam logic [6:0] __const__data_bitwidth_at_update_result = 7'd64; - localparam logic [2:0] __const__num_inports_at_update_signal = 3'd4; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL = 5'd19; - logic [0:0] already_sent_to_controller; - logic [63:0] temp_result [0:3]; - //------------------------------------------------------------- - // Component reduce_add - //------------------------------------------------------------- - - logic [0:0] reduce_add__clk; - logic [63:0] reduce_add__in_ [0:3]; - logic [63:0] reduce_add__out; - logic [0:0] reduce_add__reset; - - SumUnit__DataType_Bits64__num_inputs_4 reduce_add - ( - .clk( reduce_add__clk ), - .in_( reduce_add__in_ ), - .out( reduce_add__out ), - .reset( reduce_add__reset ) - ); - - //------------------------------------------------------------- - // End of component reduce_add - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component reduce_mul - //------------------------------------------------------------- - - logic [0:0] reduce_mul__clk; - logic [63:0] reduce_mul__in_ [0:3]; - logic [63:0] reduce_mul__out; - logic [0:0] reduce_mul__reset; - - ReduceMulUnit__DataType_Bits64__num_inputs_4 reduce_mul - ( - .clk( reduce_mul__clk ), - .in_( reduce_mul__in_ ), - .out( reduce_mul__out ), - .reset( reduce_mul__reset ) - ); - - //------------------------------------------------------------- - // End of component reduce_mul - //------------------------------------------------------------- - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 - // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ - reduce_add__in_[2'd0] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 - // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ - reduce_add__in_[2'd1] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 - // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ - reduce_add__in_[2'd2] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 - // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ - reduce_add__in_[2'd3] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 - // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ - reduce_mul__in_[2'd0] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 - // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ - reduce_mul__in_[2'd1] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 - // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ - reduce_mul__in_[2'd2] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 - // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ - reduce_mul__in_[2'd3] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ )] : 64'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:234 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:195 - // @update - // def update_predicate(): - // s.send_out[0].msg.predicate @= 0 - // if ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL)): - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate - // elif ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)): - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & \ - // s.recv_in[1].msg.predicate - // elif ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)): - // s.send_out[0].msg.predicate @= s.recv_from_ctrl_mem.msg.data.predicate & \ - // s.recv_in[1].msg.predicate - - always_comb begin : update_predicate - send_out__msg[1'd0].predicate = 1'd0; - if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) begin - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) begin - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) begin - send_out__msg[1'd0].predicate = recv_from_ctrl_mem__msg.data.predicate & recv_in__msg[2'd1].predicate; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:95 - // @update - // def update_result(): - // # Connection: splits data into vectorized wires. - // s.send_out[0].msg.payload @= 0 - // - // if s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_add.out - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_add.out + s.recv_in[1].msg.payload - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_mul.out - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_mul.out * s.recv_in[1].msg.payload - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] + s.recv_in[1].msg.payload - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] * s.recv_in[1].msg.payload - - always_comb begin : update_result - send_out__msg[1'd0].payload = 64'd0; - if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_add__out; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_add__out + recv_in__msg[2'd1].payload; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_mul__out; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_mul__out * recv_in__msg[2'd1].payload; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0] + recv_in__msg[2'd1].payload; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0] * recv_in__msg[2'd1].payload; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:117 - // @update - // def update_signal(): - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // - // s.recv_from_ctrl_mem.rdy @= 0 - // - // s.recv_in[0].rdy @= (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)) & \ - // s.send_out[0].rdy) | \ - // (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ - // s.send_to_ctrl_mem.rdy) - // s.recv_opt.rdy @= s.send_out[0].rdy - // s.recv_in[1].rdy @= (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)) & \ - // s.send_out[0].rdy) | \ - // (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ - // s.send_to_ctrl_mem.rdy) - // s.send_out[0].val @= (s.recv_in[0].val & \ - // s.recv_opt.val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL))) | \ - // (s.recv_in[0].val & \ - // s.recv_in[1].val & \ - // s.recv_opt.val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE))) | \ - // (s.recv_opt.val & \ - // s.recv_from_ctrl_mem.val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL))) | \ - // (s.recv_opt.val & \ - // s.recv_from_ctrl_mem.val & \ - // s.recv_in[1].val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL))) - // - // if s.recv_opt.val & \ - // ~s.already_sent_to_controller & \ - // (s.recv_in[0].val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL))) | \ - // (s.recv_in[0].val & \ - // s.recv_in[1].val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL))): - // s.send_to_ctrl_mem.val @= 1 - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL): - // s.send_to_ctrl_mem.msg @= \ - // s.CgraPayloadType(CMD_GLOBAL_REDUCE_ADD, - // DataType(s.reduce_add.out, - // s.recv_in[0].msg.predicate, 0, 0), - // 0, - // s.recv_opt.msg, - // 0) - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL): - // s.send_to_ctrl_mem.msg @= \ - // s.CgraPayloadType(CMD_GLOBAL_REDUCE_MUL, - // DataType(s.reduce_add.out, - // s.recv_in[0].msg.predicate, 0, 0), - // 0, - // s.recv_opt.msg, - // 0) - // - // if s.recv_opt.val & s.already_sent_to_controller: - // s.recv_from_ctrl_mem.rdy @= 1 - - always_comb begin : update_signal - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - recv_in__rdy[2'd0] = ( ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) & send_out__rdy[1'd0] ) | ( ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) & send_to_ctrl_mem__rdy ); - recv_opt__rdy = send_out__rdy[1'd0]; - recv_in__rdy[2'd1] = ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) & send_out__rdy[1'd0] ) | ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) & send_to_ctrl_mem__rdy ); - send_out__val[1'd0] = ( ( ( ( recv_in__val[2'd0] & recv_opt__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) ) | ( ( ( recv_in__val[2'd0] & recv_in__val[2'd1] ) & recv_opt__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) ) ) | ( ( recv_opt__val & recv_from_ctrl_mem__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) ) ) | ( ( ( recv_opt__val & recv_from_ctrl_mem__val ) & recv_in__val[2'd1] ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ); - if ( ( ( recv_opt__val & ( ~already_sent_to_controller ) ) & ( recv_in__val[2'd0] & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) ) ) | ( ( recv_in__val[2'd0] & recv_in__val[2'd1] ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) ) begin - send_to_ctrl_mem__val = 1'd1; - if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) begin - send_to_ctrl_mem__msg = { 5'( __const__CMD_GLOBAL_REDUCE_ADD ), { reduce_add__out, recv_in__msg[2'd0].predicate, 1'd0, 1'd0 }, 7'd0, recv_opt__msg, 4'd0 }; - end - if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) begin - send_to_ctrl_mem__msg = { 5'( __const__CMD_GLOBAL_REDUCE_MUL ), { reduce_add__out, recv_in__msg[2'd0].predicate, 1'd0, 1'd0 }, 7'd0, recv_opt__msg, 4'd0 }; - end - end - if ( recv_opt__val & already_sent_to_controller ) begin - recv_from_ctrl_mem__rdy = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:210 - // @update_ff - // def update_already_sent_to_controller(): - // if s.reset: - // s.already_sent_to_controller <<= 0 - // else: - // if s.recv_opt.val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ - // ~s.already_sent_to_controller & \ - // s.send_to_ctrl_mem.val & \ - // s.send_to_ctrl_mem.rdy: - // s.already_sent_to_controller <<= 1 - // # Recovers already_sent_to_controller once the ctrl proceeds to the next one. - // elif s.recv_opt.val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ - // s.already_sent_to_controller & \ - // s.recv_opt.rdy: - // s.already_sent_to_controller <<= 0 - - always_ff @(posedge clk) begin : update_already_sent_to_controller - if ( reset ) begin - already_sent_to_controller <= 1'd0; - end - else if ( ( ( ( recv_opt__val & ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) & ( ~already_sent_to_controller ) ) & send_to_ctrl_mem__val ) & send_to_ctrl_mem__rdy ) begin - already_sent_to_controller <= 1'd1; - end - else if ( ( ( recv_opt__val & ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) & already_sent_to_controller ) & recv_opt__rdy ) begin - already_sent_to_controller <= 1'd0; - end - end - - assign reduce_add__clk = clk; - assign reduce_add__reset = reset; - assign reduce_mul__clk = clk; - assign reduce_mul__reset = reset; - assign temp_result[0][15:0] = recv_in__msg[0].payload[15:0]; - assign temp_result[0][63:16] = 48'd0; - assign temp_result[1][15:0] = recv_in__msg[0].payload[31:16]; - assign temp_result[1][63:16] = 48'd0; - assign temp_result[2][15:0] = recv_in__msg[0].payload[47:32]; - assign temp_result[2][63:16] = 48'd0; - assign temp_result[3][15:0] = recv_in__msg[0].payload[63:48]; - assign temp_result[3][63:16] = 48'd0; - -endmodule - - -// PyMTL Component NahRTL Definition -// Full name: NahRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/NahRTL.py - -module NahRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_NAH = 7'd1; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/NahRTL.py:28 - // @update - // def comb_logic(): - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // # For pick input register - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // - // for i in range( num_outports ): - // # s.send_out[i].val @= s.recv_opt.val - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val & (s.recv_opt.msg.operation == OPT_NAH): - // s.recv_opt.rdy @= 1 - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - - always_comb begin : comb_logic - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val & ( recv_opt__msg.operation == 7'( __const__OPT_NAH ) ) ) begin - recv_opt__rdy = 1'd1; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - -endmodule - - -// PyMTL Component MulRTL Definition -// Full name: MulRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py - -module MulRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_MUL = 7'd7; - localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py:44 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != 0: - // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) - // if s.recv_opt.msg.fu_in[1] != 0: - // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_MUL: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_MUL_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_const__msg.payload; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component LogicRTL Definition -// Full name: LogicRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/LogicRTL.py - -module LogicRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_OR = 7'd8; - localparam logic [6:0] __const__OPT_AND = 7'd10; - localparam logic [6:0] __const__OPT_BIT_NOT = 7'd43; - localparam logic [6:0] __const__OPT_NOT = 7'd11; - localparam logic [6:0] __const__OPT_XOR = 7'd9; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/LogicRTL.py:44 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range( num_outports ): - // s.send_out[i].val @= b1(0) - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_OR: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload | s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_AND: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload & s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_BIT_NOT: - // s.send_out[0].msg.payload @= ~ s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_NOT: - // if s.recv_in[s.in0_idx].msg.payload == 0: - // s.send_out[0].msg.payload @= 1 - // else: - // s.send_out[0].msg.payload @= 0 - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_XOR: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload ^ s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_OR ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload | recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_AND ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload & recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_BIT_NOT ) ) begin - send_out__msg[1'd0].payload = ~recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_NOT ) ) begin - if ( recv_in__msg[in0_idx].payload == 64'd0 ) begin - send_out__msg[1'd0].payload = 64'd1; - end - else - send_out__msg[1'd0].payload = 64'd0; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_XOR ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload ^ recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component ShifterRTL Definition -// Full name: ShifterRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/ShifterRTL.py - -module ShifterRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_LLS = 7'd5; - localparam logic [6:0] __const__OPT_LRS = 7'd6; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/ShifterRTL.py:44 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= FuInType(0) - // s.in1 @= FuInType(0) - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_LLS: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload << s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_LRS: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload >> s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_LLS ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload << recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_LRS ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload >> recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component PhiRTL Definition -// Full name: PhiRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py - -module PhiRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_PHI = 7'd17; - localparam logic [6:0] __const__OPT_PHI_START = 7'd84; - localparam logic [6:0] __const__OPT_PHI_CONST = 7'd32; - logic [0:0] first; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py:48 - // @update - // def comb_logic(): - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // # TODO: decision needs to be made. Adder could be in FU vector width. Or only effective once on the boundary. - // # if s.recv_opt.val: - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_PHI: - // if s.recv_in[s.in0_idx].msg.predicate == Bits1(1): - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // elif s.recv_in[s.in1_idx].msg.predicate == Bits1(1): - // s.send_out[0].msg.payload @= s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // else: # No predecessor is active. - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= 0 - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_PHI_START: - // if s.first: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // elif s.recv_in[s.in0_idx].msg.predicate == Bits1(1): - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // elif s.recv_in[s.in1_idx].msg.predicate == Bits1(1): - // s.send_out[0].msg.payload @= s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // else: # No predecessor is active. - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= 0 - // s.recv_all_val @= ((s.first & s.recv_in[s.in0_idx].val) | \ - // (~s.first & s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val)) - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= ~s.first & s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_PHI_CONST: - // if s.first: - // s.send_out[0].msg.payload @= s.recv_const.msg.payload - // else: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // - // s.recv_all_val @= ((s.first & s.recv_const.val) | \ - // (~s.first & s.recv_in[s.in0_idx].val)) - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // if s.first: - // s.send_out[0].msg.predicate @= s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // else: - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_PHI ) ) begin - if ( recv_in__msg[in0_idx].predicate == 1'd1 ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = reached_vector_factor; - end - else if ( recv_in__msg[in1_idx].predicate == 1'd1 ) begin - send_out__msg[1'd0].payload = recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = reached_vector_factor; - end - else begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = 1'd0; - end - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_PHI_START ) ) begin - if ( first ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = reached_vector_factor; - end - else if ( recv_in__msg[in0_idx].predicate == 1'd1 ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = reached_vector_factor; - end - else if ( recv_in__msg[in1_idx].predicate == 1'd1 ) begin - send_out__msg[1'd0].payload = recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = reached_vector_factor; - end - else begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = 1'd0; - end - recv_all_val = ( first & recv_in__val[in0_idx] ) | ( ( ( ~first ) & recv_in__val[in0_idx] ) & recv_in__val[in1_idx] ); - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = ( ( ~first ) & recv_all_val ) & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_PHI_CONST ) ) begin - if ( first ) begin - send_out__msg[1'd0].payload = recv_const__msg.payload; - end - else - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - recv_all_val = ( first & recv_const__val ) | ( ( ~first ) & recv_in__val[in0_idx] ); - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - if ( first ) begin - send_out__msg[1'd0].predicate = recv_const__msg.predicate & reached_vector_factor; - end - else - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py:141 - // @update_ff - // def br_start_once(): - // if s.reset | s.clear: - // s.first <<= b1(1) - // if ((s.recv_opt.msg.operation == OPT_PHI_CONST) | (s.recv_opt.msg.operation == OPT_PHI_START)) & s.reached_vector_factor: - // s.first <<= b1(0) - - always_ff @(posedge clk) begin : br_start_once - if ( reset | clear ) begin - first <= 1'd1; - end - if ( ( ( recv_opt__msg.operation == 7'( __const__OPT_PHI_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_PHI_START ) ) ) & reached_vector_factor ) begin - first <= 1'd0; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component CompRTL Definition -// Full name: CompRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/CompRTL.py - -module CompRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_one = { 64'd1, 1'd0, 1'd0, 1'd0 }; - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_read_reg = 3'd4; - localparam logic [1:0] __const__num_outports_at_read_reg = 2'd2; - localparam logic [6:0] __const__OPT_EQ = 7'd14; - localparam logic [6:0] __const__OPT_NE = 7'd45; - localparam logic [6:0] __const__OPT_EQ_CONST = 7'd33; - localparam logic [6:0] __const__OPT_NE_CONST = 7'd46; - localparam logic [6:0] __const__OPT_LT = 7'd60; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/CompRTL.py:48 - // @update - // def read_reg(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= FuInType(0) - // s.in1 @= FuInType(0) - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType( 0 ): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if (s.recv_opt.msg.operation == OPT_EQ) | (s.recv_opt.msg.operation == OPT_NE): - // if (s.recv_opt.msg.operation == OPT_EQ) & \ - // (s.recv_in[s.in0_idx].msg.payload == s.recv_in[s.in1_idx].msg.payload): - // s.send_out[0].msg @= s.const_one - // elif (s.recv_opt.msg.operation == OPT_NE) & \ - // (s.recv_in[s.in0_idx].msg.payload != s.recv_in[s.in1_idx].msg.payload): - // s.send_out[0].msg @= s.const_one - // else: - // s.send_out[0].msg @= s.const_zero - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif (s.recv_opt.msg.operation == OPT_EQ_CONST) | (s.recv_opt.msg.operation == OPT_NE_CONST): - // if (s.recv_opt.msg.operation == OPT_EQ_CONST) & \ - // (s.recv_in[s.in0_idx].msg.payload == s.recv_const.msg.payload): - // s.send_out[0].msg @= s.const_one - // elif (s.recv_opt.msg.operation == OPT_NE_CONST) & \ - // (s.recv_in[s.in0_idx].msg.payload != s.recv_const.msg.payload): - // s.send_out[0].msg @= s.const_one - // else: - // s.send_out[0].msg @= s.const_zero - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_LT: - // if s.recv_in[s.in0_idx].msg.payload < s.recv_in[s.in1_idx].msg.payload: - // s.send_out[0].msg @= s.const_one - // else: - // s.send_out[0].msg @= s.const_zero - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : read_reg - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_read_reg ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_read_reg ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_NE ) ) ) begin - if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ ) ) & ( recv_in__msg[in0_idx].payload == recv_in__msg[in1_idx].payload ) ) begin - send_out__msg[1'd0] = const_one; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_NE ) ) & ( recv_in__msg[in0_idx].payload != recv_in__msg[in1_idx].payload ) ) begin - send_out__msg[1'd0] = const_one; - end - else - send_out__msg[1'd0] = const_zero; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_NE_CONST ) ) ) begin - if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ_CONST ) ) & ( recv_in__msg[in0_idx].payload == recv_const__msg.payload ) ) begin - send_out__msg[1'd0] = const_one; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_NE_CONST ) ) & ( recv_in__msg[in0_idx].payload != recv_const__msg.payload ) ) begin - send_out__msg[1'd0] = const_one; - end - else - send_out__msg[1'd0] = const_zero; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_LT ) ) begin - if ( recv_in__msg[in0_idx].payload < recv_in__msg[in1_idx].payload ) begin - send_out__msg[1'd0] = const_one; - end - else - send_out__msg[1'd0] = const_zero; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_read_reg ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component GrantRTL Definition -// Full name: GrantRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py - -module GrantRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_GRT_PRED = 7'd16; - localparam logic [6:0] __const__OPT_GRT_ALWAYS = 7'd34; - localparam logic [6:0] __const__OPT_GRT_ONCE = 7'd47; - logic [0:0] already_grt_once; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py:46 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= b1(0) - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_GRT_PRED: - // # GRANT_PREDICATE is used to apply (`and` operation) predicate onto a value. - // # The second operand would be used/treated as the predicate condition that - // # is usually coming from a `cmp` operation. - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // # Only updates predicate if the condition is true. Note that we respect - // # condition's (operand_1's) both value and predicate. - // if s.recv_in[s.in1_idx].msg.payload != s.const_zero.payload: - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // elif s.recv_opt.msg.operation == OPT_GRT_ALWAYS: - // # GRANT_ALWAYS is used to apply `true` predicate onto a value regardless - // # its original predicate value. This is usually used for the constant declared - // # in the entry block of a function, and then being used as a bound variable - // # in some streaming loop. Note that if we fuse the constant and the grant_always, - // # we may not need this operation, as the constant is usually preloaded into the - // # ConstQueue with `true` predicate. - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - // # Always updates predicate as true. - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // elif s.recv_opt.msg.operation == OPT_GRT_ONCE: - // # GRANT_ONCE is used to apply `true` predicate onto a value only once. This - // # is usually used for the constant declared in the entry block of a function. - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - // # Only updates predicate as true for the first time. - // s.send_out[0].msg.predicate @= s.reached_vector_factor & ~s.already_grt_once - // - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range( num_outports ): - // s.send_out[j].val @= b1( 0 ) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_PRED ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - if ( recv_in__msg[in1_idx].payload != 64'd0 ) begin - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - end - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ALWAYS ) ) begin - send_out__msg[1'd0] = recv_in__msg[in0_idx]; - send_out__msg[1'd0].predicate = reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ONCE ) ) begin - send_out__msg[1'd0] = recv_in__msg[in0_idx]; - send_out__msg[1'd0].predicate = reached_vector_factor & ( ~already_grt_once ); - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py:123 - // @update_ff - // def record_grt_once(): - // if s.reset | s.clear: - // s.already_grt_once <<= 0 - // else: - // if ~s.already_grt_once & s.send_out[0].val & s.send_out[0].rdy & (s.recv_opt.msg.operation == OPT_GRT_ONCE): - // s.already_grt_once <<= 1 - // else: - // s.already_grt_once <<= s.already_grt_once - - always_ff @(posedge clk) begin : record_grt_once - if ( reset | clear ) begin - already_grt_once <= 1'd0; - end - else if ( ( ( ( ~already_grt_once ) & send_out__val[1'd0] ) & send_out__rdy[1'd0] ) & ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ONCE ) ) ) begin - already_grt_once <= 1'd1; - end - else - already_grt_once <= already_grt_once; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component MemUnitRTL Definition -// Full name: MemUnitRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py - -module MemUnitRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_LD = 7'd12; - localparam logic [6:0] __const__OPT_ADD_CONST_LD = 7'd81; - localparam logic [6:0] __const__OPT_LD_CONST = 7'd28; - localparam logic [6:0] __const__OPT_STR = 7'd13; - localparam logic [6:0] __const__OPT_STR_CONST = 7'd58; - logic [0:0] already_sent_raddr; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [3:0] recv_in_val_vector; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:81 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= FuInType(0) - // s.in1 @= FuInType(0) - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != 0: - // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) - // if s.recv_opt.msg.fu_in[1] != 0: - // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - // - // s.to_mem_waddr.val @= 0 - // s.to_mem_waddr.msg @= AddrType() - // s.to_mem_wdata.val @= 0 - // s.to_mem_wdata.msg @= DataType() - // s.to_mem_raddr.val @= 0 - // s.to_mem_raddr.msg @= AddrType() - // s.from_mem_rdata.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_LD: - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_raddr.rdy - // s.to_mem_raddr.msg @= AddrType(s.recv_in[s.in0_idx].msg.payload[0:AddrType.nbits]) - // # Do not access memory by setting raddr.val=0 if the raddr has predicate=0. - // # Note that this only happends "once" when all the required inputs are arrived. - // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): - // s.to_mem_raddr.val @= 0 - // else: - // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr - // s.from_mem_rdata.rdy @= s.send_out[0].rdy - // # Although we do not access memory when raddr has predicate=0, - // # we still need to simulate that memory returns a fake data with predicate=0, - // # so that the consumer will not block due to the lack of data. - // # Then all initiated iterations can be normally drained. - // # Note that this only happends "after" all the required inputs are arrived. - // # Otherwise, the recv_opt's opcode would be consumed at the wrong timing. - // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): - // s.send_out[0].val @= s.recv_all_val - // s.send_out[0].msg.predicate @= 0 - // s.recv_opt.rdy @= s.send_out[0].rdy - // else: - // s.send_out[0].val @= s.from_mem_rdata.val - // s.send_out[0].msg @= s.from_mem_rdata.msg - // # Predicate of 0 is already handled and returned with fake data. So just - // # use the from_mem_rdata's predicate here. - // s.send_out[0].msg.predicate @= s.from_mem_rdata.msg.predicate & \ - // s.reached_vector_factor - // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val - // - // # ADD_CONST_LD indicates the address is added on a const, then perform load. - // elif s.recv_opt.msg.operation == OPT_ADD_CONST_LD: - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_raddr.rdy - // # It is okay to always set recv_const.rdy=1 here, because the const queue - // # would only proceed once the operation is done executing. - // s.recv_const.rdy @= 1 - // s.to_mem_raddr.msg @= AddrType(s.recv_in[s.in0_idx].msg.payload[0:AddrType.nbits] + - // s.recv_const.msg.payload[0:AddrType.nbits]) - // # Do not access memory by setting raddr.val=0 if the raddr has predicate=0. - // # Note that this only happends "once" when all the required inputs are arrived. - // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): - // s.to_mem_raddr.val @= 0 - // else: - // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr - // s.from_mem_rdata.rdy @= s.send_out[0].rdy - // # Although we do not access memory when raddr has predicate=0, - // # we still need to simulate that memory returns a fake data with predicate=0, - // # so that the consumer will not block due to the lack of data. - // # Then all initiated iterations can be normally drained. - // # Note that this only happends "after" all the required inputs are arrived. - // # Otherwise, the recv_opt's opcode would be consumed at the wrong timing. - // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): - // s.send_out[0].val @= s.recv_all_val - // s.send_out[0].msg.predicate @= 0 - // s.recv_opt.rdy @= s.send_out[0].rdy - // else: - // s.send_out[0].val @= s.from_mem_rdata.val - // s.send_out[0].msg @= s.from_mem_rdata.msg - // # Predicate of 0 is already handled and returned with fake data. So just - // # use the from_mem_rdata's predicate here. - // s.send_out[0].msg.predicate @= s.from_mem_rdata.msg.predicate & \ - // s.reached_vector_factor - // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val - // - // # LD_CONST indicates the address is a const. - // elif s.recv_opt.msg.operation == OPT_LD_CONST: - // s.recv_all_val @= s.recv_const.val - // # It is okay to always set recv_const.rdy=1 here, because the const queue - // # would only proceed once the operation is done executing. - // s.recv_const.rdy @= 1 - // s.to_mem_raddr.msg @= AddrType(s.recv_const.msg.payload[0:AddrType.nbits]) - // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr - // s.from_mem_rdata.rdy @= s.send_out[0].rdy - // s.send_out[0].val @= s.from_mem_rdata.val - // s.send_out[0].msg @= s.from_mem_rdata.msg - // s.send_out[0].msg.predicate @= s.recv_const.msg.predicate & \ - // s.from_mem_rdata.msg.predicate & \ - // s.reached_vector_factor - // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val - // - // elif s.recv_opt.msg.operation == OPT_STR: - // s.recv_all_val @= s.recv_in[s.in0_idx].val & \ - // s.recv_in[s.in1_idx].val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // s.to_mem_waddr.msg @= AddrType(s.recv_in[0].msg.payload[0:AddrType.nbits]) - // s.to_mem_waddr.val @= s.recv_all_val - // s.to_mem_wdata.msg @= s.recv_in[s.in1_idx].msg - // s.to_mem_wdata.msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.to_mem_wdata.val @= s.recv_all_val - // - // # `send_out` is meaningless for store operation. - // s.send_out[0].val @= b1(0) - // - // s.recv_opt.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // - // # STR_CONST indicates the address is a const. - // elif s.recv_opt.msg.operation == OPT_STR_CONST: - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.recv_const.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // # Only needs one input register to indicate the storing data. - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // s.to_mem_waddr.msg @= AddrType(s.recv_const.msg.payload[0:AddrType.nbits]) - // s.to_mem_waddr.val @= s.recv_all_val & \ - // s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate - // s.to_mem_wdata.msg @= s.recv_in[s.in0_idx].msg - // s.to_mem_wdata.msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // s.to_mem_wdata.val @= s.recv_all_val & \ - // s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate - // - // # `send_out` is meaningless for store operation. - // s.send_out[0].val @= b1(0) - // - // s.recv_opt.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - to_mem_waddr__val = 1'd0; - to_mem_waddr__msg = 7'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - to_mem_raddr__val = 1'd0; - to_mem_raddr__msg = 7'd0; - from_mem_rdata__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_LD ) ) begin - recv_all_val = recv_in__val[in0_idx]; - recv_in__rdy[in0_idx] = recv_all_val & to_mem_raddr__rdy; - to_mem_raddr__msg = 7'( recv_in__msg[in0_idx].payload[6'd6:6'd0] ); - if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin - to_mem_raddr__val = 1'd0; - end - else - to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); - from_mem_rdata__rdy = send_out__rdy[1'd0]; - if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin - send_out__val[1'd0] = recv_all_val; - send_out__msg[1'd0].predicate = 1'd0; - recv_opt__rdy = send_out__rdy[1'd0]; - end - else begin - send_out__val[1'd0] = from_mem_rdata__val; - send_out__msg[1'd0] = from_mem_rdata__msg; - send_out__msg[1'd0].predicate = from_mem_rdata__msg.predicate & reached_vector_factor; - recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; - end - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST_LD ) ) begin - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - recv_in__rdy[in0_idx] = recv_all_val & to_mem_raddr__rdy; - recv_const__rdy = 1'd1; - to_mem_raddr__msg = 7'( recv_in__msg[in0_idx].payload[6'd6:6'd0] + recv_const__msg.payload[6'd6:6'd0] ); - if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin - to_mem_raddr__val = 1'd0; - end - else - to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); - from_mem_rdata__rdy = send_out__rdy[1'd0]; - if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin - send_out__val[1'd0] = recv_all_val; - send_out__msg[1'd0].predicate = 1'd0; - recv_opt__rdy = send_out__rdy[1'd0]; - end - else begin - send_out__val[1'd0] = from_mem_rdata__val; - send_out__msg[1'd0] = from_mem_rdata__msg; - send_out__msg[1'd0].predicate = from_mem_rdata__msg.predicate & reached_vector_factor; - recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; - end - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_LD_CONST ) ) begin - recv_all_val = recv_const__val; - recv_const__rdy = 1'd1; - to_mem_raddr__msg = 7'( recv_const__msg.payload[6'd6:6'd0] ); - to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); - from_mem_rdata__rdy = send_out__rdy[1'd0]; - send_out__val[1'd0] = from_mem_rdata__val; - send_out__msg[1'd0] = from_mem_rdata__msg; - send_out__msg[1'd0].predicate = ( recv_const__msg.predicate & from_mem_rdata__msg.predicate ) & reached_vector_factor; - recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_STR ) ) begin - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - recv_in__rdy[in0_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - recv_in__rdy[in1_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - to_mem_waddr__msg = 7'( recv_in__msg[2'd0].payload[6'd6:6'd0] ); - to_mem_waddr__val = recv_all_val; - to_mem_wdata__msg = recv_in__msg[in1_idx]; - to_mem_wdata__msg.predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - to_mem_wdata__val = recv_all_val; - send_out__val[1'd0] = 1'd0; - recv_opt__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_STR_CONST ) ) begin - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - recv_const__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - recv_in__rdy[in0_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - to_mem_waddr__msg = 7'( recv_const__msg.payload[6'd6:6'd0] ); - to_mem_waddr__val = ( recv_all_val & recv_in__msg[in0_idx].predicate ) & recv_const__msg.predicate; - to_mem_wdata__msg = recv_in__msg[in0_idx]; - to_mem_wdata__msg.predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; - to_mem_wdata__val = ( recv_all_val & recv_in__msg[in0_idx].predicate ) & recv_const__msg.predicate; - send_out__val[1'd0] = 1'd0; - recv_opt__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:245 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:269 - // @update_ff - // def update_already_sent_raddr(): - // if s.reset: - // s.already_sent_raddr <<= 0 - // else: - // if ~s.recv_opt.val: - // s.already_sent_raddr <<= 0 - // elif s.from_mem_rdata.val & s.from_mem_rdata.rdy: - // # Clears the flag when the data has returned (s.from_mem_rdata.val) - // # and successfully delivered to the destination (s.from_mem_rdata.rdy). - // s.already_sent_raddr <<= 0 - // elif s.to_mem_raddr.val & \ - // s.to_mem_raddr.rdy & \ - // ~s.already_sent_raddr: - // s.already_sent_raddr <<= 1 - // else: - // s.already_sent_raddr <<= s.already_sent_raddr - - always_ff @(posedge clk) begin : update_already_sent_raddr - if ( reset ) begin - already_sent_raddr <= 1'd0; - end - else if ( ~recv_opt__val ) begin - already_sent_raddr <= 1'd0; - end - else if ( from_mem_rdata__val & from_mem_rdata__rdy ) begin - already_sent_raddr <= 1'd0; - end - else if ( ( to_mem_raddr__val & to_mem_raddr__rdy ) & ( ~already_sent_raddr ) ) begin - already_sent_raddr <= 1'd1; - end - else - already_sent_raddr <= already_sent_raddr; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:253 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - assign vector_factor_power = 3'd0; - -endmodule - - -// PyMTL Component SelRTL Definition -// Full name: SelRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py - -module SelRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_SEL = 7'd27; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [2:0] in2; - logic [1:0] in2_idx; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:88 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register, Selector needs at least 3 inputs - // s.in0 @= FuInType(0) - // s.in1 @= FuInType(0) - // s.in2 @= FuInType(0) - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= s.send_out[0].rdy - // - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // if s.recv_opt.msg.fu_in[2] != FuInType(0): - // s.in2 @= s.recv_opt.msg.fu_in[2] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_SEL: - // if s.recv_in[s.in0_idx].msg.payload == s.true.payload: - // s.send_out[0].msg @= s.recv_in[s.in1_idx].msg - // else: - // s.send_out[0].msg @= s.recv_in[s.in2_idx].msg - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.recv_in[s.in2_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & \ - // s.recv_in[s.in1_idx].val & \ - // s.recv_in[s.in2_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in2_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - // s.recv_in[s.in2_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - in2 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - recv_const__rdy = 1'd0; - recv_opt__rdy = send_out__rdy[1'd0]; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd2] != 3'd0 ) begin - in2 = recv_opt__msg.fu_in[2'd2] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_SEL ) ) begin - if ( recv_in__msg[in0_idx].payload == 64'd1 ) begin - send_out__msg[1'd0] = recv_in__msg[in1_idx]; - end - else - send_out__msg[1'd0] = recv_in__msg[in2_idx]; - send_out__msg[1'd0].predicate = ( ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & recv_in__msg[in2_idx].predicate ) & reached_vector_factor; - recv_all_val = ( recv_in__val[in0_idx] & recv_in__val[in1_idx] ) & recv_in__val[in2_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in2_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - recv_in__rdy[in2_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:78 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= AddrType(0) - // s.to_mem_raddr.msg @= AddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:144 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:152 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - assign in2_idx = in2[1:0]; - assign vector_factor_power = 3'd0; - -endmodule - - -// PyMTL Component RetRTL Definition -// Full name: RetRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py - -module RetRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_RET = 7'd35; - localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; - logic [0:0] already_done; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py:48 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register. - // s.in0 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // - // for j in range(num_outports): - // s.send_out[j].val @= 0 - // s.send_out[j].msg @= DataType() - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_RET: - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // # Value to be returned is usually granted with a predicate: - // # https://github.com/coredac/dataflow/blob/b9ffc097d67429017323e3d50d3984655f756b91/test/neura/ctrl/branch_for.mlir#L150. - // if s.already_done: - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val - // s.recv_opt.rdy @= s.recv_all_val - // elif s.recv_in[s.in0_idx].msg.predicate: - // # Only when the predicate is true, the value will be sent back to CPU. - // s.send_to_ctrl_mem.val @= s.recv_all_val & s.reached_vector_factor - // # s.send_to_ctrl_mem.msg @= s.recv_in[s.in0_idx].msg - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(CMD_COMPLETE, s.recv_in[s.in0_idx].msg, 0, s.recv_opt.msg, 0) - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.reached_vector_factor & s.send_to_ctrl_mem.rdy - // s.recv_opt.rdy @= s.recv_all_val & s.reached_vector_factor & s.send_to_ctrl_mem.rdy - // else: - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.reached_vector_factor - // s.recv_opt.rdy @= s.recv_all_val & s.reached_vector_factor - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin - send_out__val[1'(j)] = 1'd0; - send_out__msg[1'(j)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_RET ) ) begin - recv_all_val = recv_in__val[in0_idx]; - if ( already_done ) begin - recv_in__rdy[in0_idx] = recv_all_val; - recv_opt__rdy = recv_all_val; - end - else if ( recv_in__msg[in0_idx].predicate ) begin - send_to_ctrl_mem__val = recv_all_val & reached_vector_factor; - send_to_ctrl_mem__msg = { 5'( __const__CMD_COMPLETE ), recv_in__msg[in0_idx], 7'd0, recv_opt__msg, 4'd0 }; - recv_in__rdy[in0_idx] = ( recv_all_val & reached_vector_factor ) & send_to_ctrl_mem__rdy; - recv_opt__rdy = ( recv_all_val & reached_vector_factor ) & send_to_ctrl_mem__rdy; - end - else begin - recv_in__rdy[in0_idx] = recv_all_val & reached_vector_factor; - recv_opt__rdy = recv_all_val & reached_vector_factor; - end - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py:91 - // @update_ff - // def update_already_done(): - // if s.reset | s.clear: - // s.already_done <<= 0 - // else: - // if s.recv_opt.val & \ - // (s.recv_opt.msg.operation == OPT_RET) & \ - // ~s.already_done & \ - // s.recv_all_val & \ - // s.send_to_ctrl_mem.val & \ - // s.send_to_ctrl_mem.rdy: - // s.already_done <<= 1 - // else: - // s.already_done <<= s.already_done - - always_ff @(posedge clk) begin : update_already_done - if ( reset | clear ) begin - already_done <= 1'd0; - end - else if ( ( ( ( ( recv_opt__val & ( recv_opt__msg.operation == 7'( __const__OPT_RET ) ) ) & ( ~already_done ) ) & recv_all_val ) & send_to_ctrl_mem__val ) & send_to_ctrl_mem__rdy ) begin - already_done <= 1'd1; - end - else - already_done <= already_done; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - -endmodule - - -// PyMTL Component FlexibleFuRTL Definition -// Full name: FlexibleFuRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__num_tiles_16__FuList_[, , , , , , , , , , , , , , ]__exec_lantency_{} -// At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py - -module FlexibleFuRTL__07217382918d0fc2 -( - input logic [0:0] clear [0:14], - input logic [0:0] clk , - input logic [2:0] prologue_count_inport , - input logic [0:0] reset , - input logic [4:0] tile_id , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg [0:14] , - output logic [0:0] from_mem_rdata__rdy [0:14] , - input logic [0:0] from_mem_rdata__val [0:14] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg [0:14] , - input logic [0:0] to_mem_raddr__rdy [0:14] , - output logic [0:0] to_mem_raddr__val [0:14] , - output logic [6:0] to_mem_waddr__msg [0:14] , - input logic [0:0] to_mem_waddr__rdy [0:14] , - output logic [0:0] to_mem_waddr__val [0:14] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg [0:14] , - input logic [0:0] to_mem_wdata__rdy [0:14] , - output logic [0:0] to_mem_wdata__val [0:14] -); - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_NAH = 7'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - logic [14:0] fu_recv_const_rdy_vector; - logic [14:0] fu_recv_in_rdy_vector [0:3]; - logic [14:0] fu_recv_opt_rdy_vector; - logic [14:0] recv_from_controller_rdy_vector; - //------------------------------------------------------------- - // Component fu[0:14] - //------------------------------------------------------------- - - logic [0:0] fu__clear [0:14]; - logic [0:0] fu__clk [0:14]; - logic [0:0] fu__reset [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__from_mem_rdata__msg [0:14]; - logic [0:0] fu__from_mem_rdata__rdy [0:14]; - logic [0:0] fu__from_mem_rdata__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__recv_const__msg [0:14]; - logic [0:0] fu__recv_const__rdy [0:14]; - logic [0:0] fu__recv_const__val [0:14]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a fu__recv_from_ctrl_mem__msg [0:14]; - logic [0:0] fu__recv_from_ctrl_mem__rdy [0:14]; - logic [0:0] fu__recv_from_ctrl_mem__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__recv_in__msg [0:14][0:3]; - logic [0:0] fu__recv_in__rdy [0:14][0:3]; - logic [0:0] fu__recv_in__val [0:14][0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 fu__recv_opt__msg [0:14]; - logic [0:0] fu__recv_opt__rdy [0:14]; - logic [0:0] fu__recv_opt__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__send_out__msg [0:14][0:1]; - logic [0:0] fu__send_out__rdy [0:14][0:1]; - logic [0:0] fu__send_out__val [0:14][0:1]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a fu__send_to_ctrl_mem__msg [0:14]; - logic [0:0] fu__send_to_ctrl_mem__rdy [0:14]; - logic [0:0] fu__send_to_ctrl_mem__val [0:14]; - logic [6:0] fu__to_mem_raddr__msg [0:14]; - logic [0:0] fu__to_mem_raddr__rdy [0:14]; - logic [0:0] fu__to_mem_raddr__val [0:14]; - logic [6:0] fu__to_mem_waddr__msg [0:14]; - logic [0:0] fu__to_mem_waddr__rdy [0:14]; - logic [0:0] fu__to_mem_waddr__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__to_mem_wdata__msg [0:14]; - logic [0:0] fu__to_mem_wdata__rdy [0:14]; - logic [0:0] fu__to_mem_wdata__val [0:14]; - - AdderRTL__45df3c5556ff02e3 fu__0 - ( - .clear( fu__clear[0] ), - .clk( fu__clk[0] ), - .reset( fu__reset[0] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[0] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[0] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[0] ), - .recv_const__msg( fu__recv_const__msg[0] ), - .recv_const__rdy( fu__recv_const__rdy[0] ), - .recv_const__val( fu__recv_const__val[0] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[0] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[0] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[0] ), - .recv_in__msg( fu__recv_in__msg[0] ), - .recv_in__rdy( fu__recv_in__rdy[0] ), - .recv_in__val( fu__recv_in__val[0] ), - .recv_opt__msg( fu__recv_opt__msg[0] ), - .recv_opt__rdy( fu__recv_opt__rdy[0] ), - .recv_opt__val( fu__recv_opt__val[0] ), - .send_out__msg( fu__send_out__msg[0] ), - .send_out__rdy( fu__send_out__rdy[0] ), - .send_out__val( fu__send_out__val[0] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[0] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[0] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[0] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[0] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[0] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[0] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[0] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[0] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[0] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[0] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[0] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[0] ) - ); - - MulRTL__45df3c5556ff02e3 fu__1 - ( - .clear( fu__clear[1] ), - .clk( fu__clk[1] ), - .reset( fu__reset[1] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[1] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[1] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[1] ), - .recv_const__msg( fu__recv_const__msg[1] ), - .recv_const__rdy( fu__recv_const__rdy[1] ), - .recv_const__val( fu__recv_const__val[1] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[1] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[1] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[1] ), - .recv_in__msg( fu__recv_in__msg[1] ), - .recv_in__rdy( fu__recv_in__rdy[1] ), - .recv_in__val( fu__recv_in__val[1] ), - .recv_opt__msg( fu__recv_opt__msg[1] ), - .recv_opt__rdy( fu__recv_opt__rdy[1] ), - .recv_opt__val( fu__recv_opt__val[1] ), - .send_out__msg( fu__send_out__msg[1] ), - .send_out__rdy( fu__send_out__rdy[1] ), - .send_out__val( fu__send_out__val[1] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[1] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[1] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[1] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[1] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[1] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[1] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[1] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[1] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[1] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[1] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[1] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[1] ) - ); - - LogicRTL__45df3c5556ff02e3 fu__2 - ( - .clear( fu__clear[2] ), - .clk( fu__clk[2] ), - .reset( fu__reset[2] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[2] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[2] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[2] ), - .recv_const__msg( fu__recv_const__msg[2] ), - .recv_const__rdy( fu__recv_const__rdy[2] ), - .recv_const__val( fu__recv_const__val[2] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[2] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[2] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[2] ), - .recv_in__msg( fu__recv_in__msg[2] ), - .recv_in__rdy( fu__recv_in__rdy[2] ), - .recv_in__val( fu__recv_in__val[2] ), - .recv_opt__msg( fu__recv_opt__msg[2] ), - .recv_opt__rdy( fu__recv_opt__rdy[2] ), - .recv_opt__val( fu__recv_opt__val[2] ), - .send_out__msg( fu__send_out__msg[2] ), - .send_out__rdy( fu__send_out__rdy[2] ), - .send_out__val( fu__send_out__val[2] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[2] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[2] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[2] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[2] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[2] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[2] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[2] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[2] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[2] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[2] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[2] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[2] ) - ); - - ShifterRTL__45df3c5556ff02e3 fu__3 - ( - .clear( fu__clear[3] ), - .clk( fu__clk[3] ), - .reset( fu__reset[3] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[3] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[3] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[3] ), - .recv_const__msg( fu__recv_const__msg[3] ), - .recv_const__rdy( fu__recv_const__rdy[3] ), - .recv_const__val( fu__recv_const__val[3] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[3] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[3] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[3] ), - .recv_in__msg( fu__recv_in__msg[3] ), - .recv_in__rdy( fu__recv_in__rdy[3] ), - .recv_in__val( fu__recv_in__val[3] ), - .recv_opt__msg( fu__recv_opt__msg[3] ), - .recv_opt__rdy( fu__recv_opt__rdy[3] ), - .recv_opt__val( fu__recv_opt__val[3] ), - .send_out__msg( fu__send_out__msg[3] ), - .send_out__rdy( fu__send_out__rdy[3] ), - .send_out__val( fu__send_out__val[3] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[3] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[3] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[3] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[3] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[3] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[3] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[3] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[3] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[3] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[3] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[3] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[3] ) - ); - - PhiRTL__45df3c5556ff02e3 fu__4 - ( - .clear( fu__clear[4] ), - .clk( fu__clk[4] ), - .reset( fu__reset[4] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[4] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[4] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[4] ), - .recv_const__msg( fu__recv_const__msg[4] ), - .recv_const__rdy( fu__recv_const__rdy[4] ), - .recv_const__val( fu__recv_const__val[4] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[4] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[4] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[4] ), - .recv_in__msg( fu__recv_in__msg[4] ), - .recv_in__rdy( fu__recv_in__rdy[4] ), - .recv_in__val( fu__recv_in__val[4] ), - .recv_opt__msg( fu__recv_opt__msg[4] ), - .recv_opt__rdy( fu__recv_opt__rdy[4] ), - .recv_opt__val( fu__recv_opt__val[4] ), - .send_out__msg( fu__send_out__msg[4] ), - .send_out__rdy( fu__send_out__rdy[4] ), - .send_out__val( fu__send_out__val[4] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[4] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[4] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[4] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[4] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[4] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[4] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[4] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[4] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[4] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[4] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[4] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[4] ) - ); - - CompRTL__45df3c5556ff02e3 fu__5 - ( - .clear( fu__clear[5] ), - .clk( fu__clk[5] ), - .reset( fu__reset[5] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[5] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[5] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[5] ), - .recv_const__msg( fu__recv_const__msg[5] ), - .recv_const__rdy( fu__recv_const__rdy[5] ), - .recv_const__val( fu__recv_const__val[5] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[5] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[5] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[5] ), - .recv_in__msg( fu__recv_in__msg[5] ), - .recv_in__rdy( fu__recv_in__rdy[5] ), - .recv_in__val( fu__recv_in__val[5] ), - .recv_opt__msg( fu__recv_opt__msg[5] ), - .recv_opt__rdy( fu__recv_opt__rdy[5] ), - .recv_opt__val( fu__recv_opt__val[5] ), - .send_out__msg( fu__send_out__msg[5] ), - .send_out__rdy( fu__send_out__rdy[5] ), - .send_out__val( fu__send_out__val[5] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[5] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[5] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[5] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[5] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[5] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[5] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[5] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[5] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[5] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[5] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[5] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[5] ) - ); - - GrantRTL__45df3c5556ff02e3 fu__6 - ( - .clear( fu__clear[6] ), - .clk( fu__clk[6] ), - .reset( fu__reset[6] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[6] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[6] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[6] ), - .recv_const__msg( fu__recv_const__msg[6] ), - .recv_const__rdy( fu__recv_const__rdy[6] ), - .recv_const__val( fu__recv_const__val[6] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[6] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[6] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[6] ), - .recv_in__msg( fu__recv_in__msg[6] ), - .recv_in__rdy( fu__recv_in__rdy[6] ), - .recv_in__val( fu__recv_in__val[6] ), - .recv_opt__msg( fu__recv_opt__msg[6] ), - .recv_opt__rdy( fu__recv_opt__rdy[6] ), - .recv_opt__val( fu__recv_opt__val[6] ), - .send_out__msg( fu__send_out__msg[6] ), - .send_out__rdy( fu__send_out__rdy[6] ), - .send_out__val( fu__send_out__val[6] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[6] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[6] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[6] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[6] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[6] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[6] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[6] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[6] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[6] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[6] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[6] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[6] ) - ); - - MemUnitRTL__45df3c5556ff02e3 fu__7 - ( - .clear( fu__clear[7] ), - .clk( fu__clk[7] ), - .reset( fu__reset[7] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[7] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[7] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[7] ), - .recv_const__msg( fu__recv_const__msg[7] ), - .recv_const__rdy( fu__recv_const__rdy[7] ), - .recv_const__val( fu__recv_const__val[7] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[7] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[7] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[7] ), - .recv_in__msg( fu__recv_in__msg[7] ), - .recv_in__rdy( fu__recv_in__rdy[7] ), - .recv_in__val( fu__recv_in__val[7] ), - .recv_opt__msg( fu__recv_opt__msg[7] ), - .recv_opt__rdy( fu__recv_opt__rdy[7] ), - .recv_opt__val( fu__recv_opt__val[7] ), - .send_out__msg( fu__send_out__msg[7] ), - .send_out__rdy( fu__send_out__rdy[7] ), - .send_out__val( fu__send_out__val[7] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[7] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[7] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[7] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[7] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[7] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[7] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[7] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[7] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[7] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[7] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[7] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[7] ) - ); - - SelRTL__45df3c5556ff02e3 fu__8 - ( - .clear( fu__clear[8] ), - .clk( fu__clk[8] ), - .reset( fu__reset[8] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[8] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[8] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[8] ), - .recv_const__msg( fu__recv_const__msg[8] ), - .recv_const__rdy( fu__recv_const__rdy[8] ), - .recv_const__val( fu__recv_const__val[8] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[8] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[8] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[8] ), - .recv_in__msg( fu__recv_in__msg[8] ), - .recv_in__rdy( fu__recv_in__rdy[8] ), - .recv_in__val( fu__recv_in__val[8] ), - .recv_opt__msg( fu__recv_opt__msg[8] ), - .recv_opt__rdy( fu__recv_opt__rdy[8] ), - .recv_opt__val( fu__recv_opt__val[8] ), - .send_out__msg( fu__send_out__msg[8] ), - .send_out__rdy( fu__send_out__rdy[8] ), - .send_out__val( fu__send_out__val[8] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[8] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[8] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[8] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[8] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[8] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[8] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[8] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[8] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[8] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[8] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[8] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[8] ) - ); - - RetRTL__45df3c5556ff02e3 fu__9 - ( - .clear( fu__clear[9] ), - .clk( fu__clk[9] ), - .reset( fu__reset[9] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[9] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[9] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[9] ), - .recv_const__msg( fu__recv_const__msg[9] ), - .recv_const__rdy( fu__recv_const__rdy[9] ), - .recv_const__val( fu__recv_const__val[9] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[9] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[9] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[9] ), - .recv_in__msg( fu__recv_in__msg[9] ), - .recv_in__rdy( fu__recv_in__rdy[9] ), - .recv_in__val( fu__recv_in__val[9] ), - .recv_opt__msg( fu__recv_opt__msg[9] ), - .recv_opt__rdy( fu__recv_opt__rdy[9] ), - .recv_opt__val( fu__recv_opt__val[9] ), - .send_out__msg( fu__send_out__msg[9] ), - .send_out__rdy( fu__send_out__rdy[9] ), - .send_out__val( fu__send_out__val[9] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[9] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[9] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[9] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[9] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[9] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[9] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[9] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[9] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[9] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[9] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[9] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[9] ) - ); - - SeqMulAdderRTL__b741248a3a1dca5f fu__10 - ( - .clear( fu__clear[10] ), - .clk( fu__clk[10] ), - .reset( fu__reset[10] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[10] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[10] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[10] ), - .recv_const__msg( fu__recv_const__msg[10] ), - .recv_const__rdy( fu__recv_const__rdy[10] ), - .recv_const__val( fu__recv_const__val[10] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[10] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[10] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[10] ), - .recv_in__msg( fu__recv_in__msg[10] ), - .recv_in__rdy( fu__recv_in__rdy[10] ), - .recv_in__val( fu__recv_in__val[10] ), - .recv_opt__msg( fu__recv_opt__msg[10] ), - .recv_opt__rdy( fu__recv_opt__rdy[10] ), - .recv_opt__val( fu__recv_opt__val[10] ), - .send_out__msg( fu__send_out__msg[10] ), - .send_out__rdy( fu__send_out__rdy[10] ), - .send_out__val( fu__send_out__val[10] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[10] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[10] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[10] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[10] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[10] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[10] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[10] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[10] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[10] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[10] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[10] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[10] ) - ); - - VectorMulComboRTL__e2d25a29972e2033 fu__11 - ( - .clear( fu__clear[11] ), - .clk( fu__clk[11] ), - .reset( fu__reset[11] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[11] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[11] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[11] ), - .recv_const__msg( fu__recv_const__msg[11] ), - .recv_const__rdy( fu__recv_const__rdy[11] ), - .recv_const__val( fu__recv_const__val[11] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[11] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[11] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[11] ), - .recv_in__msg( fu__recv_in__msg[11] ), - .recv_in__rdy( fu__recv_in__rdy[11] ), - .recv_in__val( fu__recv_in__val[11] ), - .recv_opt__msg( fu__recv_opt__msg[11] ), - .recv_opt__rdy( fu__recv_opt__rdy[11] ), - .recv_opt__val( fu__recv_opt__val[11] ), - .send_out__msg( fu__send_out__msg[11] ), - .send_out__rdy( fu__send_out__rdy[11] ), - .send_out__val( fu__send_out__val[11] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[11] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[11] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[11] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[11] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[11] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[11] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[11] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[11] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[11] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[11] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[11] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[11] ) - ); - - VectorAdderComboRTL__e2d25a29972e2033 fu__12 - ( - .clear( fu__clear[12] ), - .clk( fu__clk[12] ), - .reset( fu__reset[12] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[12] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[12] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[12] ), - .recv_const__msg( fu__recv_const__msg[12] ), - .recv_const__rdy( fu__recv_const__rdy[12] ), - .recv_const__val( fu__recv_const__val[12] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[12] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[12] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[12] ), - .recv_in__msg( fu__recv_in__msg[12] ), - .recv_in__rdy( fu__recv_in__rdy[12] ), - .recv_in__val( fu__recv_in__val[12] ), - .recv_opt__msg( fu__recv_opt__msg[12] ), - .recv_opt__rdy( fu__recv_opt__rdy[12] ), - .recv_opt__val( fu__recv_opt__val[12] ), - .send_out__msg( fu__send_out__msg[12] ), - .send_out__rdy( fu__send_out__rdy[12] ), - .send_out__val( fu__send_out__val[12] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[12] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[12] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[12] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[12] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[12] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[12] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[12] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[12] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[12] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[12] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[12] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[12] ) - ); - - VectorAllReduceRTL__e2d25a29972e2033 fu__13 - ( - .clear( fu__clear[13] ), - .clk( fu__clk[13] ), - .reset( fu__reset[13] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[13] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[13] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[13] ), - .recv_const__msg( fu__recv_const__msg[13] ), - .recv_const__rdy( fu__recv_const__rdy[13] ), - .recv_const__val( fu__recv_const__val[13] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[13] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[13] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[13] ), - .recv_in__msg( fu__recv_in__msg[13] ), - .recv_in__rdy( fu__recv_in__rdy[13] ), - .recv_in__val( fu__recv_in__val[13] ), - .recv_opt__msg( fu__recv_opt__msg[13] ), - .recv_opt__rdy( fu__recv_opt__rdy[13] ), - .recv_opt__val( fu__recv_opt__val[13] ), - .send_out__msg( fu__send_out__msg[13] ), - .send_out__rdy( fu__send_out__rdy[13] ), - .send_out__val( fu__send_out__val[13] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[13] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[13] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[13] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[13] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[13] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[13] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[13] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[13] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[13] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[13] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[13] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[13] ) - ); - - NahRTL__45df3c5556ff02e3 fu__14 - ( - .clear( fu__clear[14] ), - .clk( fu__clk[14] ), - .reset( fu__reset[14] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[14] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[14] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[14] ), - .recv_const__msg( fu__recv_const__msg[14] ), - .recv_const__rdy( fu__recv_const__rdy[14] ), - .recv_const__val( fu__recv_const__val[14] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[14] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[14] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[14] ), - .recv_in__msg( fu__recv_in__msg[14] ), - .recv_in__rdy( fu__recv_in__rdy[14] ), - .recv_in__val( fu__recv_in__val[14] ), - .recv_opt__msg( fu__recv_opt__msg[14] ), - .recv_opt__rdy( fu__recv_opt__rdy[14] ), - .recv_opt__val( fu__recv_opt__val[14] ), - .send_out__msg( fu__send_out__msg[14] ), - .send_out__rdy( fu__send_out__rdy[14] ), - .send_out__val( fu__send_out__val[14] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[14] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[14] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[14] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[14] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[14] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[14] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[14] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[14] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[14] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[14] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[14] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[14] ) - ); - - //------------------------------------------------------------- - // End of component fu[0:14] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py:107 - // @update - // def comb_logic(): - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.send_out[j].msg @= DataType() - // - // for i in range(s.fu_list_size): - // # const connection. - // s.fu[i].recv_const.msg @= s.recv_const.msg - // s.fu[i].recv_const.val @= s.recv_const.val - // s.fu_recv_const_rdy_vector[i] @= s.fu[i].recv_const.rdy - // - // # opt connection. - // s.fu[i].recv_opt.msg @= s.recv_opt.msg - // # Sets each FU's op code as NAH when prologue execution is not completed. - // # As they are supposed to do nothing during that prologue cycles. - // if s.prologue_count_inport != 0: - // s.fu[i].recv_opt.msg.operation @= OPT_NAH - // s.fu[i].recv_opt.val @= s.recv_opt.val - // s.fu_recv_opt_rdy_vector[i] @= s.fu[i].recv_opt.rdy - // - // # send_out connection. - // for j in range(num_outports): - // # FIXME: need reduce_or here: https://github.com/tancheng/VectorCGRA/issues/51. - // if s.fu[i].send_out[j].val: - // s.send_out[j].msg @= s.fu[i].send_out[j].msg - // s.send_out[j].val @= s.fu[i].send_out[j].val - // s.fu[i].send_out[j].rdy @= s.send_out[j].rdy - // - // s.recv_const.rdy @= reduce_or(s.fu_recv_const_rdy_vector) - // # Operation (especially mem access) won't perform more than once, because once the - // # operation is performance (i.e., the recv_opt.rdy would be set), the `element_done` - // # register would be set and be respected. - // s.recv_opt.rdy @= reduce_or(s.fu_recv_opt_rdy_vector) | (s.prologue_count_inport != 0) - // - // for j in range(num_inports): - // s.recv_in[j].rdy @= b1(0) - // - // # recv_in connection. - // for port in range(num_inports): - // for i in range(s.fu_list_size): - // s.fu[i].recv_in[port].msg @= s.recv_in[port].msg - // s.fu[i].recv_in[port].val @= s.recv_in[port].val - // # s.recv_in[j].rdy @= s.fu[i].recv_in[j].rdy | s.recv_in[j].rdy - // s.fu_recv_in_rdy_vector[port][i] @= s.fu[i].recv_in[port].rdy - // s.recv_in[port].rdy @= reduce_or(s.fu_recv_in_rdy_vector[port]) - - always_comb begin : comb_logic - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin - send_out__val[1'(j)] = 1'd0; - send_out__msg[1'(j)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin - fu__recv_const__msg[4'(i)] = recv_const__msg; - fu__recv_const__val[4'(i)] = recv_const__val; - fu_recv_const_rdy_vector[4'(i)] = fu__recv_const__rdy[4'(i)]; - fu__recv_opt__msg[4'(i)] = recv_opt__msg; - if ( prologue_count_inport != 3'd0 ) begin - fu__recv_opt__msg[4'(i)].operation = 7'( __const__OPT_NAH ); - end - fu__recv_opt__val[4'(i)] = recv_opt__val; - fu_recv_opt_rdy_vector[4'(i)] = fu__recv_opt__rdy[4'(i)]; - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin - if ( fu__send_out__val[4'(i)][1'(j)] ) begin - send_out__msg[1'(j)] = fu__send_out__msg[4'(i)][1'(j)]; - send_out__val[1'(j)] = fu__send_out__val[4'(i)][1'(j)]; - end - fu__send_out__rdy[4'(i)][1'(j)] = send_out__rdy[1'(j)]; - end - end - recv_const__rdy = ( | fu_recv_const_rdy_vector ); - recv_opt__rdy = ( | fu_recv_opt_rdy_vector ) | ( prologue_count_inport != 3'd0 ); - for ( int unsigned j = 1'd0; j < 3'( __const__num_inports_at_comb_logic ); j += 1'd1 ) - recv_in__rdy[2'(j)] = 1'd0; - for ( int unsigned port = 1'd0; port < 3'( __const__num_inports_at_comb_logic ); port += 1'd1 ) begin - for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin - fu__recv_in__msg[4'(i)][2'(port)] = recv_in__msg[2'(port)]; - fu__recv_in__val[4'(i)][2'(port)] = recv_in__val[2'(port)]; - fu_recv_in_rdy_vector[2'(port)][4'(i)] = fu__recv_in__rdy[4'(i)][2'(port)]; - end - recv_in__rdy[2'(port)] = ( | fu_recv_in_rdy_vector[2'(port)] ); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py:90 - // @update - // def connect_to_controller(): - // for i in range(s.fu_list_size): - // # const connection. - // s.fu[i].recv_from_ctrl_mem.msg @= s.recv_from_ctrl_mem.msg - // s.fu[i].recv_from_ctrl_mem.val @= s.recv_from_ctrl_mem.val - // s.recv_from_controller_rdy_vector[i] @= s.fu[i].recv_from_ctrl_mem.rdy - // s.recv_from_ctrl_mem.rdy @= reduce_or(s.recv_from_controller_rdy_vector) - // - // s.send_to_ctrl_mem.msg @= CgraPayloadType(0, 0, 0, 0, 0) - // s.send_to_ctrl_mem.val @= 0 - // for i in range(s.fu_list_size): - // if s.fu[i].send_to_ctrl_mem.val: - // s.send_to_ctrl_mem.msg @= s.fu[i].send_to_ctrl_mem.msg - // s.send_to_ctrl_mem.val @= s.fu[i].send_to_ctrl_mem.val - // s.fu[i].send_to_ctrl_mem.rdy @= s.send_to_ctrl_mem.rdy - - always_comb begin : connect_to_controller - for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin - fu__recv_from_ctrl_mem__msg[4'(i)] = recv_from_ctrl_mem__msg; - fu__recv_from_ctrl_mem__val[4'(i)] = recv_from_ctrl_mem__val; - recv_from_controller_rdy_vector[4'(i)] = fu__recv_from_ctrl_mem__rdy[4'(i)]; - end - recv_from_ctrl_mem__rdy = ( | recv_from_controller_rdy_vector ); - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - send_to_ctrl_mem__val = 1'd0; - for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin - if ( fu__send_to_ctrl_mem__val[4'(i)] ) begin - send_to_ctrl_mem__msg = fu__send_to_ctrl_mem__msg[4'(i)]; - send_to_ctrl_mem__val = fu__send_to_ctrl_mem__val[4'(i)]; - end - fu__send_to_ctrl_mem__rdy[4'(i)] = send_to_ctrl_mem__rdy; - end - end - - assign fu__clk[0] = clk; - assign fu__reset[0] = reset; - assign fu__clk[1] = clk; - assign fu__reset[1] = reset; - assign fu__clk[2] = clk; - assign fu__reset[2] = reset; - assign fu__clk[3] = clk; - assign fu__reset[3] = reset; - assign fu__clk[4] = clk; - assign fu__reset[4] = reset; - assign fu__clk[5] = clk; - assign fu__reset[5] = reset; - assign fu__clk[6] = clk; - assign fu__reset[6] = reset; - assign fu__clk[7] = clk; - assign fu__reset[7] = reset; - assign fu__clk[8] = clk; - assign fu__reset[8] = reset; - assign fu__clk[9] = clk; - assign fu__reset[9] = reset; - assign fu__clk[10] = clk; - assign fu__reset[10] = reset; - assign fu__clk[11] = clk; - assign fu__reset[11] = reset; - assign fu__clk[12] = clk; - assign fu__reset[12] = reset; - assign fu__clk[13] = clk; - assign fu__reset[13] = reset; - assign fu__clk[14] = clk; - assign fu__reset[14] = reset; - assign to_mem_raddr__msg[0] = fu__to_mem_raddr__msg[0]; - assign fu__to_mem_raddr__rdy[0] = to_mem_raddr__rdy[0]; - assign to_mem_raddr__val[0] = fu__to_mem_raddr__val[0]; - assign fu__from_mem_rdata__msg[0] = from_mem_rdata__msg[0]; - assign from_mem_rdata__rdy[0] = fu__from_mem_rdata__rdy[0]; - assign fu__from_mem_rdata__val[0] = from_mem_rdata__val[0]; - assign to_mem_waddr__msg[0] = fu__to_mem_waddr__msg[0]; - assign fu__to_mem_waddr__rdy[0] = to_mem_waddr__rdy[0]; - assign to_mem_waddr__val[0] = fu__to_mem_waddr__val[0]; - assign to_mem_wdata__msg[0] = fu__to_mem_wdata__msg[0]; - assign fu__to_mem_wdata__rdy[0] = to_mem_wdata__rdy[0]; - assign to_mem_wdata__val[0] = fu__to_mem_wdata__val[0]; - assign fu__clear[0] = clear[0]; - assign to_mem_raddr__msg[1] = fu__to_mem_raddr__msg[1]; - assign fu__to_mem_raddr__rdy[1] = to_mem_raddr__rdy[1]; - assign to_mem_raddr__val[1] = fu__to_mem_raddr__val[1]; - assign fu__from_mem_rdata__msg[1] = from_mem_rdata__msg[1]; - assign from_mem_rdata__rdy[1] = fu__from_mem_rdata__rdy[1]; - assign fu__from_mem_rdata__val[1] = from_mem_rdata__val[1]; - assign to_mem_waddr__msg[1] = fu__to_mem_waddr__msg[1]; - assign fu__to_mem_waddr__rdy[1] = to_mem_waddr__rdy[1]; - assign to_mem_waddr__val[1] = fu__to_mem_waddr__val[1]; - assign to_mem_wdata__msg[1] = fu__to_mem_wdata__msg[1]; - assign fu__to_mem_wdata__rdy[1] = to_mem_wdata__rdy[1]; - assign to_mem_wdata__val[1] = fu__to_mem_wdata__val[1]; - assign fu__clear[1] = clear[1]; - assign to_mem_raddr__msg[2] = fu__to_mem_raddr__msg[2]; - assign fu__to_mem_raddr__rdy[2] = to_mem_raddr__rdy[2]; - assign to_mem_raddr__val[2] = fu__to_mem_raddr__val[2]; - assign fu__from_mem_rdata__msg[2] = from_mem_rdata__msg[2]; - assign from_mem_rdata__rdy[2] = fu__from_mem_rdata__rdy[2]; - assign fu__from_mem_rdata__val[2] = from_mem_rdata__val[2]; - assign to_mem_waddr__msg[2] = fu__to_mem_waddr__msg[2]; - assign fu__to_mem_waddr__rdy[2] = to_mem_waddr__rdy[2]; - assign to_mem_waddr__val[2] = fu__to_mem_waddr__val[2]; - assign to_mem_wdata__msg[2] = fu__to_mem_wdata__msg[2]; - assign fu__to_mem_wdata__rdy[2] = to_mem_wdata__rdy[2]; - assign to_mem_wdata__val[2] = fu__to_mem_wdata__val[2]; - assign fu__clear[2] = clear[2]; - assign to_mem_raddr__msg[3] = fu__to_mem_raddr__msg[3]; - assign fu__to_mem_raddr__rdy[3] = to_mem_raddr__rdy[3]; - assign to_mem_raddr__val[3] = fu__to_mem_raddr__val[3]; - assign fu__from_mem_rdata__msg[3] = from_mem_rdata__msg[3]; - assign from_mem_rdata__rdy[3] = fu__from_mem_rdata__rdy[3]; - assign fu__from_mem_rdata__val[3] = from_mem_rdata__val[3]; - assign to_mem_waddr__msg[3] = fu__to_mem_waddr__msg[3]; - assign fu__to_mem_waddr__rdy[3] = to_mem_waddr__rdy[3]; - assign to_mem_waddr__val[3] = fu__to_mem_waddr__val[3]; - assign to_mem_wdata__msg[3] = fu__to_mem_wdata__msg[3]; - assign fu__to_mem_wdata__rdy[3] = to_mem_wdata__rdy[3]; - assign to_mem_wdata__val[3] = fu__to_mem_wdata__val[3]; - assign fu__clear[3] = clear[3]; - assign to_mem_raddr__msg[4] = fu__to_mem_raddr__msg[4]; - assign fu__to_mem_raddr__rdy[4] = to_mem_raddr__rdy[4]; - assign to_mem_raddr__val[4] = fu__to_mem_raddr__val[4]; - assign fu__from_mem_rdata__msg[4] = from_mem_rdata__msg[4]; - assign from_mem_rdata__rdy[4] = fu__from_mem_rdata__rdy[4]; - assign fu__from_mem_rdata__val[4] = from_mem_rdata__val[4]; - assign to_mem_waddr__msg[4] = fu__to_mem_waddr__msg[4]; - assign fu__to_mem_waddr__rdy[4] = to_mem_waddr__rdy[4]; - assign to_mem_waddr__val[4] = fu__to_mem_waddr__val[4]; - assign to_mem_wdata__msg[4] = fu__to_mem_wdata__msg[4]; - assign fu__to_mem_wdata__rdy[4] = to_mem_wdata__rdy[4]; - assign to_mem_wdata__val[4] = fu__to_mem_wdata__val[4]; - assign fu__clear[4] = clear[4]; - assign to_mem_raddr__msg[5] = fu__to_mem_raddr__msg[5]; - assign fu__to_mem_raddr__rdy[5] = to_mem_raddr__rdy[5]; - assign to_mem_raddr__val[5] = fu__to_mem_raddr__val[5]; - assign fu__from_mem_rdata__msg[5] = from_mem_rdata__msg[5]; - assign from_mem_rdata__rdy[5] = fu__from_mem_rdata__rdy[5]; - assign fu__from_mem_rdata__val[5] = from_mem_rdata__val[5]; - assign to_mem_waddr__msg[5] = fu__to_mem_waddr__msg[5]; - assign fu__to_mem_waddr__rdy[5] = to_mem_waddr__rdy[5]; - assign to_mem_waddr__val[5] = fu__to_mem_waddr__val[5]; - assign to_mem_wdata__msg[5] = fu__to_mem_wdata__msg[5]; - assign fu__to_mem_wdata__rdy[5] = to_mem_wdata__rdy[5]; - assign to_mem_wdata__val[5] = fu__to_mem_wdata__val[5]; - assign fu__clear[5] = clear[5]; - assign to_mem_raddr__msg[6] = fu__to_mem_raddr__msg[6]; - assign fu__to_mem_raddr__rdy[6] = to_mem_raddr__rdy[6]; - assign to_mem_raddr__val[6] = fu__to_mem_raddr__val[6]; - assign fu__from_mem_rdata__msg[6] = from_mem_rdata__msg[6]; - assign from_mem_rdata__rdy[6] = fu__from_mem_rdata__rdy[6]; - assign fu__from_mem_rdata__val[6] = from_mem_rdata__val[6]; - assign to_mem_waddr__msg[6] = fu__to_mem_waddr__msg[6]; - assign fu__to_mem_waddr__rdy[6] = to_mem_waddr__rdy[6]; - assign to_mem_waddr__val[6] = fu__to_mem_waddr__val[6]; - assign to_mem_wdata__msg[6] = fu__to_mem_wdata__msg[6]; - assign fu__to_mem_wdata__rdy[6] = to_mem_wdata__rdy[6]; - assign to_mem_wdata__val[6] = fu__to_mem_wdata__val[6]; - assign fu__clear[6] = clear[6]; - assign to_mem_raddr__msg[7] = fu__to_mem_raddr__msg[7]; - assign fu__to_mem_raddr__rdy[7] = to_mem_raddr__rdy[7]; - assign to_mem_raddr__val[7] = fu__to_mem_raddr__val[7]; - assign fu__from_mem_rdata__msg[7] = from_mem_rdata__msg[7]; - assign from_mem_rdata__rdy[7] = fu__from_mem_rdata__rdy[7]; - assign fu__from_mem_rdata__val[7] = from_mem_rdata__val[7]; - assign to_mem_waddr__msg[7] = fu__to_mem_waddr__msg[7]; - assign fu__to_mem_waddr__rdy[7] = to_mem_waddr__rdy[7]; - assign to_mem_waddr__val[7] = fu__to_mem_waddr__val[7]; - assign to_mem_wdata__msg[7] = fu__to_mem_wdata__msg[7]; - assign fu__to_mem_wdata__rdy[7] = to_mem_wdata__rdy[7]; - assign to_mem_wdata__val[7] = fu__to_mem_wdata__val[7]; - assign fu__clear[7] = clear[7]; - assign to_mem_raddr__msg[8] = fu__to_mem_raddr__msg[8]; - assign fu__to_mem_raddr__rdy[8] = to_mem_raddr__rdy[8]; - assign to_mem_raddr__val[8] = fu__to_mem_raddr__val[8]; - assign fu__from_mem_rdata__msg[8] = from_mem_rdata__msg[8]; - assign from_mem_rdata__rdy[8] = fu__from_mem_rdata__rdy[8]; - assign fu__from_mem_rdata__val[8] = from_mem_rdata__val[8]; - assign to_mem_waddr__msg[8] = fu__to_mem_waddr__msg[8]; - assign fu__to_mem_waddr__rdy[8] = to_mem_waddr__rdy[8]; - assign to_mem_waddr__val[8] = fu__to_mem_waddr__val[8]; - assign to_mem_wdata__msg[8] = fu__to_mem_wdata__msg[8]; - assign fu__to_mem_wdata__rdy[8] = to_mem_wdata__rdy[8]; - assign to_mem_wdata__val[8] = fu__to_mem_wdata__val[8]; - assign fu__clear[8] = clear[8]; - assign to_mem_raddr__msg[9] = fu__to_mem_raddr__msg[9]; - assign fu__to_mem_raddr__rdy[9] = to_mem_raddr__rdy[9]; - assign to_mem_raddr__val[9] = fu__to_mem_raddr__val[9]; - assign fu__from_mem_rdata__msg[9] = from_mem_rdata__msg[9]; - assign from_mem_rdata__rdy[9] = fu__from_mem_rdata__rdy[9]; - assign fu__from_mem_rdata__val[9] = from_mem_rdata__val[9]; - assign to_mem_waddr__msg[9] = fu__to_mem_waddr__msg[9]; - assign fu__to_mem_waddr__rdy[9] = to_mem_waddr__rdy[9]; - assign to_mem_waddr__val[9] = fu__to_mem_waddr__val[9]; - assign to_mem_wdata__msg[9] = fu__to_mem_wdata__msg[9]; - assign fu__to_mem_wdata__rdy[9] = to_mem_wdata__rdy[9]; - assign to_mem_wdata__val[9] = fu__to_mem_wdata__val[9]; - assign fu__clear[9] = clear[9]; - assign to_mem_raddr__msg[10] = fu__to_mem_raddr__msg[10]; - assign fu__to_mem_raddr__rdy[10] = to_mem_raddr__rdy[10]; - assign to_mem_raddr__val[10] = fu__to_mem_raddr__val[10]; - assign fu__from_mem_rdata__msg[10] = from_mem_rdata__msg[10]; - assign from_mem_rdata__rdy[10] = fu__from_mem_rdata__rdy[10]; - assign fu__from_mem_rdata__val[10] = from_mem_rdata__val[10]; - assign to_mem_waddr__msg[10] = fu__to_mem_waddr__msg[10]; - assign fu__to_mem_waddr__rdy[10] = to_mem_waddr__rdy[10]; - assign to_mem_waddr__val[10] = fu__to_mem_waddr__val[10]; - assign to_mem_wdata__msg[10] = fu__to_mem_wdata__msg[10]; - assign fu__to_mem_wdata__rdy[10] = to_mem_wdata__rdy[10]; - assign to_mem_wdata__val[10] = fu__to_mem_wdata__val[10]; - assign fu__clear[10] = clear[10]; - assign to_mem_raddr__msg[11] = fu__to_mem_raddr__msg[11]; - assign fu__to_mem_raddr__rdy[11] = to_mem_raddr__rdy[11]; - assign to_mem_raddr__val[11] = fu__to_mem_raddr__val[11]; - assign fu__from_mem_rdata__msg[11] = from_mem_rdata__msg[11]; - assign from_mem_rdata__rdy[11] = fu__from_mem_rdata__rdy[11]; - assign fu__from_mem_rdata__val[11] = from_mem_rdata__val[11]; - assign to_mem_waddr__msg[11] = fu__to_mem_waddr__msg[11]; - assign fu__to_mem_waddr__rdy[11] = to_mem_waddr__rdy[11]; - assign to_mem_waddr__val[11] = fu__to_mem_waddr__val[11]; - assign to_mem_wdata__msg[11] = fu__to_mem_wdata__msg[11]; - assign fu__to_mem_wdata__rdy[11] = to_mem_wdata__rdy[11]; - assign to_mem_wdata__val[11] = fu__to_mem_wdata__val[11]; - assign fu__clear[11] = clear[11]; - assign to_mem_raddr__msg[12] = fu__to_mem_raddr__msg[12]; - assign fu__to_mem_raddr__rdy[12] = to_mem_raddr__rdy[12]; - assign to_mem_raddr__val[12] = fu__to_mem_raddr__val[12]; - assign fu__from_mem_rdata__msg[12] = from_mem_rdata__msg[12]; - assign from_mem_rdata__rdy[12] = fu__from_mem_rdata__rdy[12]; - assign fu__from_mem_rdata__val[12] = from_mem_rdata__val[12]; - assign to_mem_waddr__msg[12] = fu__to_mem_waddr__msg[12]; - assign fu__to_mem_waddr__rdy[12] = to_mem_waddr__rdy[12]; - assign to_mem_waddr__val[12] = fu__to_mem_waddr__val[12]; - assign to_mem_wdata__msg[12] = fu__to_mem_wdata__msg[12]; - assign fu__to_mem_wdata__rdy[12] = to_mem_wdata__rdy[12]; - assign to_mem_wdata__val[12] = fu__to_mem_wdata__val[12]; - assign fu__clear[12] = clear[12]; - assign to_mem_raddr__msg[13] = fu__to_mem_raddr__msg[13]; - assign fu__to_mem_raddr__rdy[13] = to_mem_raddr__rdy[13]; - assign to_mem_raddr__val[13] = fu__to_mem_raddr__val[13]; - assign fu__from_mem_rdata__msg[13] = from_mem_rdata__msg[13]; - assign from_mem_rdata__rdy[13] = fu__from_mem_rdata__rdy[13]; - assign fu__from_mem_rdata__val[13] = from_mem_rdata__val[13]; - assign to_mem_waddr__msg[13] = fu__to_mem_waddr__msg[13]; - assign fu__to_mem_waddr__rdy[13] = to_mem_waddr__rdy[13]; - assign to_mem_waddr__val[13] = fu__to_mem_waddr__val[13]; - assign to_mem_wdata__msg[13] = fu__to_mem_wdata__msg[13]; - assign fu__to_mem_wdata__rdy[13] = to_mem_wdata__rdy[13]; - assign to_mem_wdata__val[13] = fu__to_mem_wdata__val[13]; - assign fu__clear[13] = clear[13]; - assign to_mem_raddr__msg[14] = fu__to_mem_raddr__msg[14]; - assign fu__to_mem_raddr__rdy[14] = to_mem_raddr__rdy[14]; - assign to_mem_raddr__val[14] = fu__to_mem_raddr__val[14]; - assign fu__from_mem_rdata__msg[14] = from_mem_rdata__msg[14]; - assign from_mem_rdata__rdy[14] = fu__from_mem_rdata__rdy[14]; - assign fu__from_mem_rdata__val[14] = from_mem_rdata__val[14]; - assign to_mem_waddr__msg[14] = fu__to_mem_waddr__msg[14]; - assign fu__to_mem_waddr__rdy[14] = to_mem_waddr__rdy[14]; - assign to_mem_waddr__val[14] = fu__to_mem_waddr__val[14]; - assign to_mem_wdata__msg[14] = fu__to_mem_wdata__msg[14]; - assign fu__to_mem_wdata__rdy[14] = to_mem_wdata__rdy[14]; - assign to_mem_wdata__val[14] = fu__to_mem_wdata__val[14]; - assign fu__clear[14] = clear[14]; - -endmodule - - -// PyMTL Component CrossbarRTL Definition -// Full name: CrossbarRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_2__num_outports_8__num_cgras_4__num_tiles_16__ctrl_mem_size_16__outport_towards_local_base_id_4 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py - -module CrossbarRTL__45ee026205c61975 -( - input logic [1:0] cgra_id , - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] compute_done , - input logic [0:0] crossbar_id , - input logic [1:0] crossbar_outport [0:7], - input logic [3:0] ctrl_addr_inport , - input logic [2:0] prologue_count_inport [0:15][0:1], - input logic [0:0] reset , - input logic [4:0] tile_id , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:1] , - output logic [0:0] recv_data__rdy [0:1] , - input logic [0:0] recv_data__val [0:1] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:7] , - input logic [0:0] send_data__rdy [0:7] , - output logic [0:0] send_data__val [0:7] -); - localparam logic [1:0] __const__num_inports_at_update_signal = 2'd2; - localparam logic [3:0] __const__num_outports_at_update_signal = 4'd8; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter = 5'd16; - localparam logic [1:0] __const__num_inports_at_update_prologue_counter = 2'd2; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter_next = 5'd16; - localparam logic [1:0] __const__num_inports_at_update_prologue_counter_next = 2'd2; - localparam logic [3:0] __const__num_outports_at_update_prologue_counter_next = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_prologue_allowing_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_prologue_or_valid_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_in_dir_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_rdy_vector = 4'd8; - localparam logic [2:0] __const__outport_towards_local_base_id_at_update_rdy_vector = 3'd4; - localparam logic [3:0] __const__num_outports_at_update_valid_vector = 4'd8; - localparam logic [1:0] __const__num_inports_at_update_recv_required_vector = 2'd2; - localparam logic [3:0] __const__num_outports_at_update_recv_required_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_send_required_vector = 4'd8; - logic [1:0] in_dir [0:7]; - logic [0:0] in_dir_local [0:7]; - logic [7:0] prologue_allowing_vector; - logic [2:0] prologue_count_wire [0:15][0:1]; - logic [2:0] prologue_counter [0:15][0:1]; - logic [2:0] prologue_counter_next [0:15][0:1]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_msg [0:1]; - logic [0:0] recv_data_val [0:1]; - logic [1:0] recv_required_vector; - logic [7:0] recv_valid_or_prologue_allowing_vector; - logic [7:0] recv_valid_vector; - logic [7:0] send_rdy_vector; - logic [7:0] send_required_vector; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:153 - // @update - // def update_in_dir_vector(): - // - // for i in range(num_outports): - // s.in_dir[i] @= 0 - // s.in_dir_local[i] @= 0 - // - // for i in range(num_outports): - // s.in_dir[i] @= s.crossbar_outport[i] - // if s.in_dir[i] > 0: - // s.in_dir_local[i] @= trunc(s.in_dir[i] - 1, NumInportType) - - always_comb begin : update_in_dir_vector - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin - in_dir[3'(i)] = 2'd0; - in_dir_local[3'(i)] = 1'd0; - end - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin - in_dir[3'(i)] = crossbar_outport[3'(i)]; - if ( in_dir[3'(i)] > 2'd0 ) begin - in_dir_local[3'(i)] = 1'(in_dir[3'(i)] - 2'd1); - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:134 - // @update - // def update_prologue_allowing_vector(): - // s.prologue_allowing_vector @= 0 - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // # Records whether the prologue steps have already been satisfied. - // s.prologue_allowing_vector[i] @= \ - // (s.prologue_counter[s.ctrl_addr_inport][s.in_dir_local[i]] < \ - // s.prologue_count_wire[s.ctrl_addr_inport][s.in_dir_local[i]]) - // else: - // s.prologue_allowing_vector[i] @= 1 - - always_comb begin : update_prologue_allowing_vector - prologue_allowing_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_allowing_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 2'd0 ) begin - prologue_allowing_vector[3'(i)] = prologue_counter[ctrl_addr_inport][in_dir_local[3'(i)]] < prologue_count_wire[ctrl_addr_inport][in_dir_local[3'(i)]]; - end - else - prologue_allowing_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:119 - // @update - // def update_prologue_counter_next(): - // # Nested-loop to update the prologue counter, to avoid dynamic indexing to - // # work-around Yosys issue: https://github.com/tancheng/VectorCGRA/issues/148 - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] - // for j in range(num_outports): - // if s.recv_opt.rdy & \ - // (s.in_dir[j] > 0) & \ - // (s.in_dir_local[j] == i) & \ - // (addr == s.ctrl_addr_inport) & \ - // (s.prologue_counter[addr][i] < s.prologue_count_wire[addr][i]): - // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + 1 - - always_comb begin : update_prologue_counter_next - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter_next ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter_next ); i += 1'd1 ) begin - prologue_counter_next[4'(addr)][1'(i)] = prologue_counter[4'(addr)][1'(i)]; - for ( int unsigned j = 1'd0; j < 4'( __const__num_outports_at_update_prologue_counter_next ); j += 1'd1 ) - if ( ( ( ( recv_opt__rdy & ( in_dir[3'(j)] > 2'd0 ) ) & ( in_dir_local[3'(j)] == 1'(i) ) ) & ( 4'(addr) == ctrl_addr_inport ) ) & ( prologue_counter[4'(addr)][1'(i)] < prologue_count_wire[4'(addr)][1'(i)] ) ) begin - prologue_counter_next[4'(addr)][1'(i)] = prologue_counter[4'(addr)][1'(i)] + 3'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:146 - // @update - // def update_prologue_or_valid_vector(): - // s.recv_valid_or_prologue_allowing_vector @= 0 - // for i in range(num_outports): - // s.recv_valid_or_prologue_allowing_vector[i] @= \ - // s.recv_valid_vector[i] | s.prologue_allowing_vector[i] - - always_comb begin : update_prologue_or_valid_vector - recv_valid_or_prologue_allowing_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_or_valid_vector ); i += 1'd1 ) - recv_valid_or_prologue_allowing_vector[3'(i)] = recv_valid_vector[3'(i)] | prologue_allowing_vector[3'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:165 - // @update - // def update_rdy_vector(): - // s.send_rdy_vector @= 0 - // for i in range(num_outports): - // # The `num_inports` indicates the number of outports that go to other tiles. - // # Specifically, if the compute already done, we shouldn't care the ones - // # (i.e., i >= num_inports) go to the FU's inports. In other words, we skip - // # the rdy checking on the FU's inports (connecting from crossbar_outport) if - // # the compute is already completed. - // if (s.in_dir[i] > 0) & \ - // (~s.compute_done | (i < outport_towards_local_base_id)): - // s.send_rdy_vector[i] @= s.send_data[i].rdy - // else: - // s.send_rdy_vector[i] @= 1 - - always_comb begin : update_rdy_vector - send_rdy_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_rdy_vector ); i += 1'd1 ) - if ( ( in_dir[3'(i)] > 2'd0 ) & ( ( ~compute_done ) | ( 3'(i) < 3'( __const__outport_towards_local_base_id_at_update_rdy_vector ) ) ) ) begin - send_rdy_vector[3'(i)] = send_data__rdy[3'(i)]; - end - else - send_rdy_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:189 - // @update - // def update_recv_required_vector(): - // for i in range(num_inports): - // s.recv_required_vector[i] @= 0 - // - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.recv_required_vector[s.in_dir_local[i]] @= 1 - - always_comb begin : update_recv_required_vector - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_recv_required_vector ); i += 1'd1 ) - recv_required_vector[1'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_recv_required_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 2'd0 ) begin - recv_required_vector[in_dir_local[3'(i)]] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:198 - // @update - // def update_send_required_vector(): - // - // for i in range(num_outports): - // s.send_required_vector[i] @= 0 - // - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.send_required_vector[i] @= 1 - - always_comb begin : update_send_required_vector - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) - send_required_vector[3'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 2'd0 ) begin - send_required_vector[3'(i)] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:82 - // @update - // def update_signal(): - // for i in range(num_inports): - // s.recv_data[i].rdy @= 0 - // for i in range(num_outports): - // s.send_data[i].val @= 0 - // s.send_data[i].msg @= DataType() - // s.recv_opt.rdy @= 0 - // - // if s.recv_opt.val & (s.recv_opt.msg.operation != OPT_START): - // for i in range(num_inports): - // s.recv_data[i].rdy @= reduce_and(s.recv_valid_vector) & \ - // reduce_and(s.send_rdy_vector) & \ - // s.recv_required_vector[i] - // - // for i in range(num_outports): - // s.send_data[i].val @= reduce_and(s.recv_valid_vector) & \ - // s.send_required_vector[i] - // if reduce_and(s.recv_valid_vector) & \ - // s.send_required_vector[i]: - // s.send_data[i].msg.payload @= s.recv_data_msg[s.in_dir_local[i]].payload - // s.send_data[i].msg.predicate @= s.recv_data_msg[s.in_dir_local[i]].predicate - // - // s.recv_opt.rdy @= reduce_and(s.send_rdy_vector) & \ - // reduce_and(s.recv_valid_or_prologue_allowing_vector) - - always_comb begin : update_signal - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_signal ); i += 1'd1 ) - recv_data__rdy[1'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin - send_data__val[3'(i)] = 1'd0; - send_data__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_opt__rdy = 1'd0; - if ( recv_opt__val & ( recv_opt__msg.operation != 7'( __const__OPT_START ) ) ) begin - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_signal ); i += 1'd1 ) - recv_data__rdy[1'(i)] = ( ( & recv_valid_vector ) & ( & send_rdy_vector ) ) & recv_required_vector[1'(i)]; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin - send_data__val[3'(i)] = ( & recv_valid_vector ) & send_required_vector[3'(i)]; - if ( ( & recv_valid_vector ) & send_required_vector[3'(i)] ) begin - send_data__msg[3'(i)].payload = recv_data_msg[in_dir_local[3'(i)]].payload; - send_data__msg[3'(i)].predicate = recv_data_msg[in_dir_local[3'(i)]].predicate; - end - end - recv_opt__rdy = ( & send_rdy_vector ) & ( & recv_valid_or_prologue_allowing_vector ); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:180 - // @update - // def update_valid_vector(): - // s.recv_valid_vector @= 0 - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.recv_valid_vector[i] @= s.recv_data_val[s.in_dir_local[i]] - // else: - // s.recv_valid_vector[i] @= 1 - - always_comb begin : update_valid_vector - recv_valid_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_valid_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 2'd0 ) begin - recv_valid_vector[3'(i)] = recv_data_val[in_dir_local[3'(i)]]; - end - else - recv_valid_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:108 - // @update_ff - // def update_prologue_counter(): - // if s.reset | s.clear: - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter[addr][i] <<= 0 - // else: - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter[addr][i] <<= s.prologue_counter_next[addr][i] - - always_ff @(posedge clk) begin : update_prologue_counter - if ( reset | clear ) begin - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) - prologue_counter[4'(addr)][1'(i)] <= 3'd0; - end - else - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) - prologue_counter[4'(addr)][1'(i)] <= prologue_counter_next[4'(addr)][1'(i)]; - end - - assign recv_data_msg[0] = recv_data__msg[0]; - assign recv_data_val[0] = recv_data__val[0]; - assign recv_data_msg[1] = recv_data__msg[1]; - assign recv_data_val[1] = recv_data__val[1]; - assign prologue_count_wire[0][0] = prologue_count_inport[0][0]; - assign prologue_count_wire[0][1] = prologue_count_inport[0][1]; - assign prologue_count_wire[1][0] = prologue_count_inport[1][0]; - assign prologue_count_wire[1][1] = prologue_count_inport[1][1]; - assign prologue_count_wire[2][0] = prologue_count_inport[2][0]; - assign prologue_count_wire[2][1] = prologue_count_inport[2][1]; - assign prologue_count_wire[3][0] = prologue_count_inport[3][0]; - assign prologue_count_wire[3][1] = prologue_count_inport[3][1]; - assign prologue_count_wire[4][0] = prologue_count_inport[4][0]; - assign prologue_count_wire[4][1] = prologue_count_inport[4][1]; - assign prologue_count_wire[5][0] = prologue_count_inport[5][0]; - assign prologue_count_wire[5][1] = prologue_count_inport[5][1]; - assign prologue_count_wire[6][0] = prologue_count_inport[6][0]; - assign prologue_count_wire[6][1] = prologue_count_inport[6][1]; - assign prologue_count_wire[7][0] = prologue_count_inport[7][0]; - assign prologue_count_wire[7][1] = prologue_count_inport[7][1]; - assign prologue_count_wire[8][0] = prologue_count_inport[8][0]; - assign prologue_count_wire[8][1] = prologue_count_inport[8][1]; - assign prologue_count_wire[9][0] = prologue_count_inport[9][0]; - assign prologue_count_wire[9][1] = prologue_count_inport[9][1]; - assign prologue_count_wire[10][0] = prologue_count_inport[10][0]; - assign prologue_count_wire[10][1] = prologue_count_inport[10][1]; - assign prologue_count_wire[11][0] = prologue_count_inport[11][0]; - assign prologue_count_wire[11][1] = prologue_count_inport[11][1]; - assign prologue_count_wire[12][0] = prologue_count_inport[12][0]; - assign prologue_count_wire[12][1] = prologue_count_inport[12][1]; - assign prologue_count_wire[13][0] = prologue_count_inport[13][0]; - assign prologue_count_wire[13][1] = prologue_count_inport[13][1]; - assign prologue_count_wire[14][0] = prologue_count_inport[14][0]; - assign prologue_count_wire[14][1] = prologue_count_inport[14][1]; - assign prologue_count_wire[15][0] = prologue_count_inport[15][0]; - assign prologue_count_wire[15][1] = prologue_count_inport[15][1]; - -endmodule - - -// PyMTL Component RegisterBankRTL Definition -// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_0__num_registers_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py - -module RegisterBankRTL__649561e613f42979 -( - input logic [0:0] clk , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , - input logic [0:0] inport_valid [0:2], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], - input logic [0:0] reset , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , - input logic [0:0] send_data_to_fu__rdy , - output logic [0:0] send_data_to_fu__val -); - localparam logic [0:0] __const__reg_bank_id_at_access_registers = 1'd0; - localparam logic [0:0] __const__reg_bank_id_at_update_send_val = 1'd0; - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__bd22936ec5812d0d reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [1:0] __tmpvar__access_registers_write_reg_from; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 - // @update - // def access_registers(): - // # Initializes signals. - // s.reg_file.raddr[0] @= AddrType() - // s.send_data_to_fu.msg @= DataType() - // s.reg_file.waddr[0] @= AddrType() - // s.reg_file.wdata[0] @= DataType() - // s.reg_file.wen[0] @= 0 - // - // if s.inport_opt.read_reg_from[reg_bank_id]: - // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] - // s.send_data_to_fu.msg @= s.reg_file.rdata[0] - // - // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] - // if ~s.reset & (write_reg_from > 0): - // if s.inport_valid[write_reg_from - 1]: - // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] - // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] - // s.reg_file.wen[0] @= 1 - - always_comb begin : access_registers - reg_file__raddr[1'd0] = 4'd0; - send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__waddr[1'd0] = 4'd0; - reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__wen[1'd0] = 1'd0; - if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin - reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - send_data_to_fu__msg = reg_file__rdata[1'd0]; - end - __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; - if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin - if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin - reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; - reg_file__wen[1'd0] = 1'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 - // @update - // def update_send_val(): - // s.send_data_to_fu.val @= 0 - // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: - // s.send_data_to_fu.val @= 1 - - always_comb begin : update_send_val - send_data_to_fu__val = 1'd0; - if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin - send_data_to_fu__val = 1'd1; - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - -endmodule - - -// PyMTL Component RegisterBankRTL Definition -// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_1__num_registers_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py - -module RegisterBankRTL__0a5bdf408d921386 -( - input logic [0:0] clk , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , - input logic [0:0] inport_valid [0:2], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], - input logic [0:0] reset , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , - input logic [0:0] send_data_to_fu__rdy , - output logic [0:0] send_data_to_fu__val -); - localparam logic [0:0] __const__reg_bank_id_at_access_registers = 1'd1; - localparam logic [0:0] __const__reg_bank_id_at_update_send_val = 1'd1; - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__bd22936ec5812d0d reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [1:0] __tmpvar__access_registers_write_reg_from; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 - // @update - // def access_registers(): - // # Initializes signals. - // s.reg_file.raddr[0] @= AddrType() - // s.send_data_to_fu.msg @= DataType() - // s.reg_file.waddr[0] @= AddrType() - // s.reg_file.wdata[0] @= DataType() - // s.reg_file.wen[0] @= 0 - // - // if s.inport_opt.read_reg_from[reg_bank_id]: - // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] - // s.send_data_to_fu.msg @= s.reg_file.rdata[0] - // - // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] - // if ~s.reset & (write_reg_from > 0): - // if s.inport_valid[write_reg_from - 1]: - // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] - // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] - // s.reg_file.wen[0] @= 1 - - always_comb begin : access_registers - reg_file__raddr[1'd0] = 4'd0; - send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__waddr[1'd0] = 4'd0; - reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__wen[1'd0] = 1'd0; - if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin - reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - send_data_to_fu__msg = reg_file__rdata[1'd0]; - end - __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; - if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin - if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin - reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; - reg_file__wen[1'd0] = 1'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 - // @update - // def update_send_val(): - // s.send_data_to_fu.val @= 0 - // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: - // s.send_data_to_fu.val @= 1 - - always_comb begin : update_send_val - send_data_to_fu__val = 1'd0; - if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin - send_data_to_fu__val = 1'd1; - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - -endmodule - - -// PyMTL Component RegisterBankRTL Definition -// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_2__num_registers_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py - -module RegisterBankRTL__ddae41891d80e575 -( - input logic [0:0] clk , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , - input logic [0:0] inport_valid [0:2], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], - input logic [0:0] reset , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , - input logic [0:0] send_data_to_fu__rdy , - output logic [0:0] send_data_to_fu__val -); - localparam logic [1:0] __const__reg_bank_id_at_access_registers = 2'd2; - localparam logic [1:0] __const__reg_bank_id_at_update_send_val = 2'd2; - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__bd22936ec5812d0d reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [1:0] __tmpvar__access_registers_write_reg_from; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 - // @update - // def access_registers(): - // # Initializes signals. - // s.reg_file.raddr[0] @= AddrType() - // s.send_data_to_fu.msg @= DataType() - // s.reg_file.waddr[0] @= AddrType() - // s.reg_file.wdata[0] @= DataType() - // s.reg_file.wen[0] @= 0 - // - // if s.inport_opt.read_reg_from[reg_bank_id]: - // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] - // s.send_data_to_fu.msg @= s.reg_file.rdata[0] - // - // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] - // if ~s.reset & (write_reg_from > 0): - // if s.inport_valid[write_reg_from - 1]: - // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] - // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] - // s.reg_file.wen[0] @= 1 - - always_comb begin : access_registers - reg_file__raddr[1'd0] = 4'd0; - send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__waddr[1'd0] = 4'd0; - reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__wen[1'd0] = 1'd0; - if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin - reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - send_data_to_fu__msg = reg_file__rdata[1'd0]; - end - __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; - if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin - if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin - reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; - reg_file__wen[1'd0] = 1'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 - // @update - // def update_send_val(): - // s.send_data_to_fu.val @= 0 - // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: - // s.send_data_to_fu.val @= 1 - - always_comb begin : update_send_val - send_data_to_fu__val = 1'd0; - if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin - send_data_to_fu__val = 1'd1; - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - -endmodule - - -// PyMTL Component RegisterBankRTL Definition -// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_3__num_registers_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py - -module RegisterBankRTL__ff0588d25abf2ed3 -( - input logic [0:0] clk , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , - input logic [0:0] inport_valid [0:2], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], - input logic [0:0] reset , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , - input logic [0:0] send_data_to_fu__rdy , - output logic [0:0] send_data_to_fu__val -); - localparam logic [1:0] __const__reg_bank_id_at_access_registers = 2'd3; - localparam logic [1:0] __const__reg_bank_id_at_update_send_val = 2'd3; - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__bd22936ec5812d0d reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [1:0] __tmpvar__access_registers_write_reg_from; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 - // @update - // def access_registers(): - // # Initializes signals. - // s.reg_file.raddr[0] @= AddrType() - // s.send_data_to_fu.msg @= DataType() - // s.reg_file.waddr[0] @= AddrType() - // s.reg_file.wdata[0] @= DataType() - // s.reg_file.wen[0] @= 0 - // - // if s.inport_opt.read_reg_from[reg_bank_id]: - // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] - // s.send_data_to_fu.msg @= s.reg_file.rdata[0] - // - // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] - // if ~s.reset & (write_reg_from > 0): - // if s.inport_valid[write_reg_from - 1]: - // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] - // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] - // s.reg_file.wen[0] @= 1 - - always_comb begin : access_registers - reg_file__raddr[1'd0] = 4'd0; - send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__waddr[1'd0] = 4'd0; - reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__wen[1'd0] = 1'd0; - if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin - reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - send_data_to_fu__msg = reg_file__rdata[1'd0]; - end - __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; - if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin - if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin - reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; - reg_file__wen[1'd0] = 1'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 - // @update - // def update_send_val(): - // s.send_data_to_fu.val @= 0 - // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: - // s.send_data_to_fu.val @= 1 - - always_comb begin : update_send_val - send_data_to_fu__val = 1'd0; - if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin - send_data_to_fu__val = 1'd1; - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - -endmodule - - -// PyMTL Component RegisterClusterRTL Definition -// Full name: RegisterClusterRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_reg_banks_4__num_registers_per_reg_bank_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterClusterRTL.py - -module RegisterClusterRTL__7f2febb613462546 -( - input logic [0:0] clk , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_const__msg [0:3] , - output logic [0:0] recv_data_from_const__rdy [0:3] , - input logic [0:0] recv_data_from_const__val [0:3] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_fu_crossbar__msg [0:3] , - output logic [0:0] recv_data_from_fu_crossbar__rdy [0:3] , - input logic [0:0] recv_data_from_fu_crossbar__val [0:3] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_routing_crossbar__msg [0:3] , - output logic [0:0] recv_data_from_routing_crossbar__rdy [0:3] , - input logic [0:0] recv_data_from_routing_crossbar__val [0:3] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg [0:3] , - input logic [0:0] send_data_to_fu__rdy [0:3] , - output logic [0:0] send_data_to_fu__val [0:3] -); - localparam logic [2:0] __const__num_reg_banks_at_update_msgs_signals = 3'd4; - //------------------------------------------------------------- - // Component reg_bank[0:3] - //------------------------------------------------------------- - - logic [0:0] reg_bank__clk [0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_bank__inport_opt [0:3]; - logic [0:0] reg_bank__inport_valid [0:3][0:2]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_bank__inport_wdata [0:3][0:2]; - logic [0:0] reg_bank__reset [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_bank__send_data_to_fu__msg [0:3]; - logic [0:0] reg_bank__send_data_to_fu__rdy [0:3]; - logic [0:0] reg_bank__send_data_to_fu__val [0:3]; - - RegisterBankRTL__649561e613f42979 reg_bank__0 - ( - .clk( reg_bank__clk[0] ), - .inport_opt( reg_bank__inport_opt[0] ), - .inport_valid( reg_bank__inport_valid[0] ), - .inport_wdata( reg_bank__inport_wdata[0] ), - .reset( reg_bank__reset[0] ), - .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[0] ), - .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[0] ), - .send_data_to_fu__val( reg_bank__send_data_to_fu__val[0] ) - ); - - RegisterBankRTL__0a5bdf408d921386 reg_bank__1 - ( - .clk( reg_bank__clk[1] ), - .inport_opt( reg_bank__inport_opt[1] ), - .inport_valid( reg_bank__inport_valid[1] ), - .inport_wdata( reg_bank__inport_wdata[1] ), - .reset( reg_bank__reset[1] ), - .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[1] ), - .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[1] ), - .send_data_to_fu__val( reg_bank__send_data_to_fu__val[1] ) - ); - - RegisterBankRTL__ddae41891d80e575 reg_bank__2 - ( - .clk( reg_bank__clk[2] ), - .inport_opt( reg_bank__inport_opt[2] ), - .inport_valid( reg_bank__inport_valid[2] ), - .inport_wdata( reg_bank__inport_wdata[2] ), - .reset( reg_bank__reset[2] ), - .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[2] ), - .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[2] ), - .send_data_to_fu__val( reg_bank__send_data_to_fu__val[2] ) - ); - - RegisterBankRTL__ff0588d25abf2ed3 reg_bank__3 - ( - .clk( reg_bank__clk[3] ), - .inport_opt( reg_bank__inport_opt[3] ), - .inport_valid( reg_bank__inport_valid[3] ), - .inport_wdata( reg_bank__inport_wdata[3] ), - .reset( reg_bank__reset[3] ), - .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[3] ), - .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[3] ), - .send_data_to_fu__val( reg_bank__send_data_to_fu__val[3] ) - ); - - //------------------------------------------------------------- - // End of component reg_bank[0:3] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterClusterRTL.py:45 - // @update - // def update_msgs_signals(): - // # Initializes signals. - // for i in range(num_reg_banks): - // s.send_data_to_fu[i].msg @= DataType() - // s.recv_data_from_routing_crossbar[i].rdy @= 0 - // s.recv_data_from_fu_crossbar[i].rdy @= 0 - // s.recv_data_from_const[i].rdy @= 0 - // s.send_data_to_fu[i].val @= 0 - // - // for i in range(num_reg_banks): - // if s.recv_data_from_routing_crossbar[i].val: - // s.send_data_to_fu[i].msg @= \ - // s.recv_data_from_routing_crossbar[i].msg - // else: - // s.send_data_to_fu[i].msg @= \ - // s.reg_bank[i].send_data_to_fu.msg - // - // s.send_data_to_fu[i].val @= \ - // s.recv_data_from_routing_crossbar[i].val | \ - // s.reg_bank[i].send_data_to_fu.val - // s.reg_bank[i].send_data_to_fu.rdy @= s.send_data_to_fu[i].rdy - // - // s.recv_data_from_routing_crossbar[i].rdy @= s.send_data_to_fu[i].rdy - // s.recv_data_from_fu_crossbar[i].rdy @= 1 - // s.recv_data_from_const[i].rdy @= 1 - - always_comb begin : update_msgs_signals - for ( int unsigned i = 1'd0; i < 3'( __const__num_reg_banks_at_update_msgs_signals ); i += 1'd1 ) begin - send_data_to_fu__msg[2'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - recv_data_from_routing_crossbar__rdy[2'(i)] = 1'd0; - recv_data_from_fu_crossbar__rdy[2'(i)] = 1'd0; - recv_data_from_const__rdy[2'(i)] = 1'd0; - send_data_to_fu__val[2'(i)] = 1'd0; - end - for ( int unsigned i = 1'd0; i < 3'( __const__num_reg_banks_at_update_msgs_signals ); i += 1'd1 ) begin - if ( recv_data_from_routing_crossbar__val[2'(i)] ) begin - send_data_to_fu__msg[2'(i)] = recv_data_from_routing_crossbar__msg[2'(i)]; - end - else - send_data_to_fu__msg[2'(i)] = reg_bank__send_data_to_fu__msg[2'(i)]; - send_data_to_fu__val[2'(i)] = recv_data_from_routing_crossbar__val[2'(i)] | reg_bank__send_data_to_fu__val[2'(i)]; - reg_bank__send_data_to_fu__rdy[2'(i)] = send_data_to_fu__rdy[2'(i)]; - recv_data_from_routing_crossbar__rdy[2'(i)] = send_data_to_fu__rdy[2'(i)]; - recv_data_from_fu_crossbar__rdy[2'(i)] = 1'd1; - recv_data_from_const__rdy[2'(i)] = 1'd1; - end - end - - assign reg_bank__clk[0] = clk; - assign reg_bank__reset[0] = reset; - assign reg_bank__clk[1] = clk; - assign reg_bank__reset[1] = reset; - assign reg_bank__clk[2] = clk; - assign reg_bank__reset[2] = reset; - assign reg_bank__clk[3] = clk; - assign reg_bank__reset[3] = reset; - assign reg_bank__inport_opt[0] = inport_opt; - assign reg_bank__inport_wdata[0][0] = recv_data_from_routing_crossbar__msg[0]; - assign reg_bank__inport_wdata[0][1] = recv_data_from_fu_crossbar__msg[0]; - assign reg_bank__inport_wdata[0][2] = recv_data_from_const__msg[0]; - assign reg_bank__inport_valid[0][0] = recv_data_from_routing_crossbar__val[0]; - assign reg_bank__inport_valid[0][1] = recv_data_from_fu_crossbar__val[0]; - assign reg_bank__inport_valid[0][2] = recv_data_from_const__val[0]; - assign reg_bank__inport_opt[1] = inport_opt; - assign reg_bank__inport_wdata[1][0] = recv_data_from_routing_crossbar__msg[1]; - assign reg_bank__inport_wdata[1][1] = recv_data_from_fu_crossbar__msg[1]; - assign reg_bank__inport_wdata[1][2] = recv_data_from_const__msg[1]; - assign reg_bank__inport_valid[1][0] = recv_data_from_routing_crossbar__val[1]; - assign reg_bank__inport_valid[1][1] = recv_data_from_fu_crossbar__val[1]; - assign reg_bank__inport_valid[1][2] = recv_data_from_const__val[1]; - assign reg_bank__inport_opt[2] = inport_opt; - assign reg_bank__inport_wdata[2][0] = recv_data_from_routing_crossbar__msg[2]; - assign reg_bank__inport_wdata[2][1] = recv_data_from_fu_crossbar__msg[2]; - assign reg_bank__inport_wdata[2][2] = recv_data_from_const__msg[2]; - assign reg_bank__inport_valid[2][0] = recv_data_from_routing_crossbar__val[2]; - assign reg_bank__inport_valid[2][1] = recv_data_from_fu_crossbar__val[2]; - assign reg_bank__inport_valid[2][2] = recv_data_from_const__val[2]; - assign reg_bank__inport_opt[3] = inport_opt; - assign reg_bank__inport_wdata[3][0] = recv_data_from_routing_crossbar__msg[3]; - assign reg_bank__inport_wdata[3][1] = recv_data_from_fu_crossbar__msg[3]; - assign reg_bank__inport_wdata[3][2] = recv_data_from_const__msg[3]; - assign reg_bank__inport_valid[3][0] = recv_data_from_routing_crossbar__val[3]; - assign reg_bank__inport_valid[3][1] = recv_data_from_fu_crossbar__val[3]; - assign reg_bank__inport_valid[3][2] = recv_data_from_const__val[3]; - -endmodule - - -// PyMTL Component CrossbarRTL Definition -// Full name: CrossbarRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_8__num_cgras_4__num_tiles_16__ctrl_mem_size_16__outport_towards_local_base_id_4 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py - -module CrossbarRTL__cad4150dfdc32fbd -( - input logic [1:0] cgra_id , - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] compute_done , - input logic [0:0] crossbar_id , - input logic [2:0] crossbar_outport [0:7], - input logic [3:0] ctrl_addr_inport , - input logic [2:0] prologue_count_inport [0:15][0:3], - input logic [0:0] reset , - input logic [4:0] tile_id , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:3] , - output logic [0:0] recv_data__rdy [0:3] , - input logic [0:0] recv_data__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:7] , - input logic [0:0] send_data__rdy [0:7] , - output logic [0:0] send_data__val [0:7] -); - localparam logic [2:0] __const__num_inports_at_update_signal = 3'd4; - localparam logic [3:0] __const__num_outports_at_update_signal = 4'd8; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter = 5'd16; - localparam logic [2:0] __const__num_inports_at_update_prologue_counter = 3'd4; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter_next = 5'd16; - localparam logic [2:0] __const__num_inports_at_update_prologue_counter_next = 3'd4; - localparam logic [3:0] __const__num_outports_at_update_prologue_counter_next = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_prologue_allowing_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_prologue_or_valid_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_in_dir_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_rdy_vector = 4'd8; - localparam logic [2:0] __const__outport_towards_local_base_id_at_update_rdy_vector = 3'd4; - localparam logic [3:0] __const__num_outports_at_update_valid_vector = 4'd8; - localparam logic [2:0] __const__num_inports_at_update_recv_required_vector = 3'd4; - localparam logic [3:0] __const__num_outports_at_update_recv_required_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_send_required_vector = 4'd8; - logic [2:0] in_dir [0:7]; - logic [1:0] in_dir_local [0:7]; - logic [7:0] prologue_allowing_vector; - logic [2:0] prologue_count_wire [0:15][0:3]; - logic [2:0] prologue_counter [0:15][0:3]; - logic [2:0] prologue_counter_next [0:15][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_msg [0:3]; - logic [0:0] recv_data_val [0:3]; - logic [3:0] recv_required_vector; - logic [7:0] recv_valid_or_prologue_allowing_vector; - logic [7:0] recv_valid_vector; - logic [7:0] send_rdy_vector; - logic [7:0] send_required_vector; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:153 - // @update - // def update_in_dir_vector(): - // - // for i in range(num_outports): - // s.in_dir[i] @= 0 - // s.in_dir_local[i] @= 0 - // - // for i in range(num_outports): - // s.in_dir[i] @= s.crossbar_outport[i] - // if s.in_dir[i] > 0: - // s.in_dir_local[i] @= trunc(s.in_dir[i] - 1, NumInportType) - - always_comb begin : update_in_dir_vector - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin - in_dir[3'(i)] = 3'd0; - in_dir_local[3'(i)] = 2'd0; - end - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin - in_dir[3'(i)] = crossbar_outport[3'(i)]; - if ( in_dir[3'(i)] > 3'd0 ) begin - in_dir_local[3'(i)] = 2'(in_dir[3'(i)] - 3'd1); - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:134 - // @update - // def update_prologue_allowing_vector(): - // s.prologue_allowing_vector @= 0 - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // # Records whether the prologue steps have already been satisfied. - // s.prologue_allowing_vector[i] @= \ - // (s.prologue_counter[s.ctrl_addr_inport][s.in_dir_local[i]] < \ - // s.prologue_count_wire[s.ctrl_addr_inport][s.in_dir_local[i]]) - // else: - // s.prologue_allowing_vector[i] @= 1 - - always_comb begin : update_prologue_allowing_vector - prologue_allowing_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_allowing_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 3'd0 ) begin - prologue_allowing_vector[3'(i)] = prologue_counter[ctrl_addr_inport][in_dir_local[3'(i)]] < prologue_count_wire[ctrl_addr_inport][in_dir_local[3'(i)]]; - end - else - prologue_allowing_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:119 - // @update - // def update_prologue_counter_next(): - // # Nested-loop to update the prologue counter, to avoid dynamic indexing to - // # work-around Yosys issue: https://github.com/tancheng/VectorCGRA/issues/148 - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] - // for j in range(num_outports): - // if s.recv_opt.rdy & \ - // (s.in_dir[j] > 0) & \ - // (s.in_dir_local[j] == i) & \ - // (addr == s.ctrl_addr_inport) & \ - // (s.prologue_counter[addr][i] < s.prologue_count_wire[addr][i]): - // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + 1 - - always_comb begin : update_prologue_counter_next - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter_next ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter_next ); i += 1'd1 ) begin - prologue_counter_next[4'(addr)][2'(i)] = prologue_counter[4'(addr)][2'(i)]; - for ( int unsigned j = 1'd0; j < 4'( __const__num_outports_at_update_prologue_counter_next ); j += 1'd1 ) - if ( ( ( ( recv_opt__rdy & ( in_dir[3'(j)] > 3'd0 ) ) & ( in_dir_local[3'(j)] == 2'(i) ) ) & ( 4'(addr) == ctrl_addr_inport ) ) & ( prologue_counter[4'(addr)][2'(i)] < prologue_count_wire[4'(addr)][2'(i)] ) ) begin - prologue_counter_next[4'(addr)][2'(i)] = prologue_counter[4'(addr)][2'(i)] + 3'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:146 - // @update - // def update_prologue_or_valid_vector(): - // s.recv_valid_or_prologue_allowing_vector @= 0 - // for i in range(num_outports): - // s.recv_valid_or_prologue_allowing_vector[i] @= \ - // s.recv_valid_vector[i] | s.prologue_allowing_vector[i] - - always_comb begin : update_prologue_or_valid_vector - recv_valid_or_prologue_allowing_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_or_valid_vector ); i += 1'd1 ) - recv_valid_or_prologue_allowing_vector[3'(i)] = recv_valid_vector[3'(i)] | prologue_allowing_vector[3'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:165 - // @update - // def update_rdy_vector(): - // s.send_rdy_vector @= 0 - // for i in range(num_outports): - // # The `num_inports` indicates the number of outports that go to other tiles. - // # Specifically, if the compute already done, we shouldn't care the ones - // # (i.e., i >= num_inports) go to the FU's inports. In other words, we skip - // # the rdy checking on the FU's inports (connecting from crossbar_outport) if - // # the compute is already completed. - // if (s.in_dir[i] > 0) & \ - // (~s.compute_done | (i < outport_towards_local_base_id)): - // s.send_rdy_vector[i] @= s.send_data[i].rdy - // else: - // s.send_rdy_vector[i] @= 1 - - always_comb begin : update_rdy_vector - send_rdy_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_rdy_vector ); i += 1'd1 ) - if ( ( in_dir[3'(i)] > 3'd0 ) & ( ( ~compute_done ) | ( 3'(i) < 3'( __const__outport_towards_local_base_id_at_update_rdy_vector ) ) ) ) begin - send_rdy_vector[3'(i)] = send_data__rdy[3'(i)]; - end - else - send_rdy_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:189 - // @update - // def update_recv_required_vector(): - // for i in range(num_inports): - // s.recv_required_vector[i] @= 0 - // - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.recv_required_vector[s.in_dir_local[i]] @= 1 - - always_comb begin : update_recv_required_vector - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_recv_required_vector ); i += 1'd1 ) - recv_required_vector[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_recv_required_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 3'd0 ) begin - recv_required_vector[in_dir_local[3'(i)]] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:198 - // @update - // def update_send_required_vector(): - // - // for i in range(num_outports): - // s.send_required_vector[i] @= 0 - // - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.send_required_vector[i] @= 1 - - always_comb begin : update_send_required_vector - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) - send_required_vector[3'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 3'd0 ) begin - send_required_vector[3'(i)] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:82 - // @update - // def update_signal(): - // for i in range(num_inports): - // s.recv_data[i].rdy @= 0 - // for i in range(num_outports): - // s.send_data[i].val @= 0 - // s.send_data[i].msg @= DataType() - // s.recv_opt.rdy @= 0 - // - // if s.recv_opt.val & (s.recv_opt.msg.operation != OPT_START): - // for i in range(num_inports): - // s.recv_data[i].rdy @= reduce_and(s.recv_valid_vector) & \ - // reduce_and(s.send_rdy_vector) & \ - // s.recv_required_vector[i] - // - // for i in range(num_outports): - // s.send_data[i].val @= reduce_and(s.recv_valid_vector) & \ - // s.send_required_vector[i] - // if reduce_and(s.recv_valid_vector) & \ - // s.send_required_vector[i]: - // s.send_data[i].msg.payload @= s.recv_data_msg[s.in_dir_local[i]].payload - // s.send_data[i].msg.predicate @= s.recv_data_msg[s.in_dir_local[i]].predicate - // - // s.recv_opt.rdy @= reduce_and(s.send_rdy_vector) & \ - // reduce_and(s.recv_valid_or_prologue_allowing_vector) - - always_comb begin : update_signal - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) - recv_data__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin - send_data__val[3'(i)] = 1'd0; - send_data__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_opt__rdy = 1'd0; - if ( recv_opt__val & ( recv_opt__msg.operation != 7'( __const__OPT_START ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) - recv_data__rdy[2'(i)] = ( ( & recv_valid_vector ) & ( & send_rdy_vector ) ) & recv_required_vector[2'(i)]; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin - send_data__val[3'(i)] = ( & recv_valid_vector ) & send_required_vector[3'(i)]; - if ( ( & recv_valid_vector ) & send_required_vector[3'(i)] ) begin - send_data__msg[3'(i)].payload = recv_data_msg[in_dir_local[3'(i)]].payload; - send_data__msg[3'(i)].predicate = recv_data_msg[in_dir_local[3'(i)]].predicate; - end - end - recv_opt__rdy = ( & send_rdy_vector ) & ( & recv_valid_or_prologue_allowing_vector ); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:180 - // @update - // def update_valid_vector(): - // s.recv_valid_vector @= 0 - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.recv_valid_vector[i] @= s.recv_data_val[s.in_dir_local[i]] - // else: - // s.recv_valid_vector[i] @= 1 - - always_comb begin : update_valid_vector - recv_valid_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_valid_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 3'd0 ) begin - recv_valid_vector[3'(i)] = recv_data_val[in_dir_local[3'(i)]]; - end - else - recv_valid_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:108 - // @update_ff - // def update_prologue_counter(): - // if s.reset | s.clear: - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter[addr][i] <<= 0 - // else: - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter[addr][i] <<= s.prologue_counter_next[addr][i] - - always_ff @(posedge clk) begin : update_prologue_counter - if ( reset | clear ) begin - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) - prologue_counter[4'(addr)][2'(i)] <= 3'd0; - end - else - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) - prologue_counter[4'(addr)][2'(i)] <= prologue_counter_next[4'(addr)][2'(i)]; - end - - assign recv_data_msg[0] = recv_data__msg[0]; - assign recv_data_val[0] = recv_data__val[0]; - assign recv_data_msg[1] = recv_data__msg[1]; - assign recv_data_val[1] = recv_data__val[1]; - assign recv_data_msg[2] = recv_data__msg[2]; - assign recv_data_val[2] = recv_data__val[2]; - assign recv_data_msg[3] = recv_data__msg[3]; - assign recv_data_val[3] = recv_data__val[3]; - assign prologue_count_wire[0][0] = prologue_count_inport[0][0]; - assign prologue_count_wire[0][1] = prologue_count_inport[0][1]; - assign prologue_count_wire[0][2] = prologue_count_inport[0][2]; - assign prologue_count_wire[0][3] = prologue_count_inport[0][3]; - assign prologue_count_wire[1][0] = prologue_count_inport[1][0]; - assign prologue_count_wire[1][1] = prologue_count_inport[1][1]; - assign prologue_count_wire[1][2] = prologue_count_inport[1][2]; - assign prologue_count_wire[1][3] = prologue_count_inport[1][3]; - assign prologue_count_wire[2][0] = prologue_count_inport[2][0]; - assign prologue_count_wire[2][1] = prologue_count_inport[2][1]; - assign prologue_count_wire[2][2] = prologue_count_inport[2][2]; - assign prologue_count_wire[2][3] = prologue_count_inport[2][3]; - assign prologue_count_wire[3][0] = prologue_count_inport[3][0]; - assign prologue_count_wire[3][1] = prologue_count_inport[3][1]; - assign prologue_count_wire[3][2] = prologue_count_inport[3][2]; - assign prologue_count_wire[3][3] = prologue_count_inport[3][3]; - assign prologue_count_wire[4][0] = prologue_count_inport[4][0]; - assign prologue_count_wire[4][1] = prologue_count_inport[4][1]; - assign prologue_count_wire[4][2] = prologue_count_inport[4][2]; - assign prologue_count_wire[4][3] = prologue_count_inport[4][3]; - assign prologue_count_wire[5][0] = prologue_count_inport[5][0]; - assign prologue_count_wire[5][1] = prologue_count_inport[5][1]; - assign prologue_count_wire[5][2] = prologue_count_inport[5][2]; - assign prologue_count_wire[5][3] = prologue_count_inport[5][3]; - assign prologue_count_wire[6][0] = prologue_count_inport[6][0]; - assign prologue_count_wire[6][1] = prologue_count_inport[6][1]; - assign prologue_count_wire[6][2] = prologue_count_inport[6][2]; - assign prologue_count_wire[6][3] = prologue_count_inport[6][3]; - assign prologue_count_wire[7][0] = prologue_count_inport[7][0]; - assign prologue_count_wire[7][1] = prologue_count_inport[7][1]; - assign prologue_count_wire[7][2] = prologue_count_inport[7][2]; - assign prologue_count_wire[7][3] = prologue_count_inport[7][3]; - assign prologue_count_wire[8][0] = prologue_count_inport[8][0]; - assign prologue_count_wire[8][1] = prologue_count_inport[8][1]; - assign prologue_count_wire[8][2] = prologue_count_inport[8][2]; - assign prologue_count_wire[8][3] = prologue_count_inport[8][3]; - assign prologue_count_wire[9][0] = prologue_count_inport[9][0]; - assign prologue_count_wire[9][1] = prologue_count_inport[9][1]; - assign prologue_count_wire[9][2] = prologue_count_inport[9][2]; - assign prologue_count_wire[9][3] = prologue_count_inport[9][3]; - assign prologue_count_wire[10][0] = prologue_count_inport[10][0]; - assign prologue_count_wire[10][1] = prologue_count_inport[10][1]; - assign prologue_count_wire[10][2] = prologue_count_inport[10][2]; - assign prologue_count_wire[10][3] = prologue_count_inport[10][3]; - assign prologue_count_wire[11][0] = prologue_count_inport[11][0]; - assign prologue_count_wire[11][1] = prologue_count_inport[11][1]; - assign prologue_count_wire[11][2] = prologue_count_inport[11][2]; - assign prologue_count_wire[11][3] = prologue_count_inport[11][3]; - assign prologue_count_wire[12][0] = prologue_count_inport[12][0]; - assign prologue_count_wire[12][1] = prologue_count_inport[12][1]; - assign prologue_count_wire[12][2] = prologue_count_inport[12][2]; - assign prologue_count_wire[12][3] = prologue_count_inport[12][3]; - assign prologue_count_wire[13][0] = prologue_count_inport[13][0]; - assign prologue_count_wire[13][1] = prologue_count_inport[13][1]; - assign prologue_count_wire[13][2] = prologue_count_inport[13][2]; - assign prologue_count_wire[13][3] = prologue_count_inport[13][3]; - assign prologue_count_wire[14][0] = prologue_count_inport[14][0]; - assign prologue_count_wire[14][1] = prologue_count_inport[14][1]; - assign prologue_count_wire[14][2] = prologue_count_inport[14][2]; - assign prologue_count_wire[14][3] = prologue_count_inport[14][3]; - assign prologue_count_wire[15][0] = prologue_count_inport[15][0]; - assign prologue_count_wire[15][1] = prologue_count_inport[15][1]; - assign prologue_count_wire[15][2] = prologue_count_inport[15][2]; - assign prologue_count_wire[15][3] = prologue_count_inport[15][3]; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__684a25db9dbebdb9 -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__43c9394e24dc368f -( - input logic [0:0] clk , - input logic [0:0] raddr , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_msg , - input logic [0:0] reset , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__684a25db9dbebdb9 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__43c9394e24dc368f -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__raddr; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 dpath__recv_msg; - logic [0:0] dpath__reset; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__43c9394e24dc368f dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component ChannelRTL Definition -// Full name: ChannelRTL__PacketType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__QueueType_NormalQueueRTL__latency_1 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py - -module ChannelRTL__694d252f21ac798b -( - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queues[0:0] - //------------------------------------------------------------- - - logic [0:0] queues__clk [0:0]; - logic [1:0] queues__count [0:0]; - logic [0:0] queues__reset [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 queues__recv__msg [0:0]; - logic [0:0] queues__recv__rdy [0:0]; - logic [0:0] queues__recv__val [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 queues__send__msg [0:0]; - logic [0:0] queues__send__rdy [0:0]; - logic [0:0] queues__send__val [0:0]; - - NormalQueueRTL__43c9394e24dc368f queues__0 - ( - .clk( queues__clk[0] ), - .count( queues__count[0] ), - .reset( queues__reset[0] ), - .recv__msg( queues__recv__msg[0] ), - .recv__rdy( queues__recv__rdy[0] ), - .recv__val( queues__recv__val[0] ), - .send__msg( queues__send__msg[0] ), - .send__rdy( queues__send__rdy[0] ), - .send__val( queues__send__val[0] ) - ); - - //------------------------------------------------------------- - // End of component queues[0:0] - //------------------------------------------------------------- - - assign queues__clk[0] = clk; - assign queues__reset[0] = reset; - assign queues__recv__msg[0] = recv__msg; - assign recv__rdy = queues__recv__rdy[0]; - assign queues__recv__val[0] = recv__val; - assign send__msg = queues__send__msg[0]; - assign queues__send__rdy[0] = send__rdy; - assign send__val = queues__send__val[0]; - -endmodule - - -// PyMTL Component LinkOrRTL Definition -// Full name: LinkOrRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/LinkOrRTL.py - -module LinkOrRTL__0fce34ff986f61fe -( - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_fu__msg , - output logic [0:0] recv_fu__rdy , - input logic [0:0] recv_fu__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_xbar__msg , - output logic [0:0] recv_xbar__rdy , - input logic [0:0] recv_xbar__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/LinkOrRTL.py:28 - // @update - // def process(): - // # Initializes the delivered message. - // s.send.msg @= DataType() - // - // # The messages from two sources (i.e., xbar and FU) won't be valid - // # simultaneously (confliction would be caused if they both are valid), - // # which is guaranteed by the compiler/software. - // s.send.msg.predicate @= s.recv_fu.msg.predicate | s.recv_xbar.msg.predicate - // s.send.msg.payload @= s.recv_xbar.msg.payload | s.recv_fu.msg.payload - // - // # FIXME: bypass won't be necessary any more with separate xbar design. - // # s.send.msg.bypass @= 0 - // # s.send.msg.delay @= s.recv_fu.msg.delay | s.recv_xbar.msg.delay - // - // # s.send.val @= s.send.rdy & (s.recv_fu.val | s.recv_xbar.val) - // s.send.val @= s.recv_fu.val | s.recv_xbar.val - // s.recv_fu.rdy @= s.send.rdy - // s.recv_xbar.rdy @= s.send.rdy - - always_comb begin : process - send__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - send__msg.predicate = recv_fu__msg.predicate | recv_xbar__msg.predicate; - send__msg.payload = recv_xbar__msg.payload | recv_fu__msg.payload; - send__val = recv_fu__val | recv_xbar__val; - recv_fu__rdy = send__rdy; - recv_xbar__rdy = send__rdy; - end - -endmodule - - -// PyMTL Component TileRTL Definition -// Full name: TileRTL__IntraCgraPktType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ctrl_mem_size_16__data_mem_size_128__num_ctrl_4__total_steps_38__num_fu_inports_4__num_fu_outports_2__num_tile_inports_4__num_tile_outports_4__num_cgras_4__num_tiles_16__num_registers_per_reg_bank_16__Fu_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ] -// At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py - -module TileRTL__78da5e3970e1cd1d -( - input logic [1:0] cgra_id , - input logic [0:0] clk , - input logic [0:0] reset , - input logic [4:0] tile_id , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:3] , - output logic [0:0] recv_data__rdy [0:3] , - input logic [0:0] recv_data__val [0:3] , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_controller_pkt__msg , - output logic [0:0] recv_from_controller_pkt__rdy , - input logic [0:0] recv_from_controller_pkt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:3] , - input logic [0:0] send_data__rdy [0:3] , - output logic [0:0] send_data__val [0:3] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_controller_pkt__msg , - input logic [0:0] send_to_controller_pkt__rdy , - output logic [0:0] send_to_controller_pkt__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam logic [1:0] __const__CMD_CONFIG = 2'd3; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; - localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; - localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; - localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; - localparam logic [3:0] __const__CMD_CONST = 4'd13; - logic [0:0] element_done; - logic [0:0] fu_crossbar_done; - logic [0:0] routing_crossbar_done; - //------------------------------------------------------------- - // Component const_mem - //------------------------------------------------------------- - - logic [0:0] const_mem__clear; - logic [0:0] const_mem__clk; - logic [0:0] const_mem__ctrl_proceed; - logic [0:0] const_mem__reset; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_mem__recv_const__msg; - logic [0:0] const_mem__recv_const__rdy; - logic [0:0] const_mem__recv_const__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_mem__send_const__msg; - logic [0:0] const_mem__send_const__rdy; - logic [0:0] const_mem__send_const__val; - - ConstQueueDynamicRTL__9d3397f72f19af52 const_mem - ( - .clear( const_mem__clear ), - .clk( const_mem__clk ), - .ctrl_proceed( const_mem__ctrl_proceed ), - .reset( const_mem__reset ), - .recv_const__msg( const_mem__recv_const__msg ), - .recv_const__rdy( const_mem__recv_const__rdy ), - .recv_const__val( const_mem__recv_const__val ), - .send_const__msg( const_mem__send_const__msg ), - .send_const__rdy( const_mem__send_const__rdy ), - .send_const__val( const_mem__send_const__val ) - ); - - //------------------------------------------------------------- - // End of component const_mem - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component ctrl_mem - //------------------------------------------------------------- - - logic [1:0] ctrl_mem__cgra_id; - logic [0:0] ctrl_mem__clk; - logic [3:0] ctrl_mem__ctrl_addr_outport; - logic [2:0] ctrl_mem__prologue_count_outport_fu; - logic [2:0] ctrl_mem__prologue_count_outport_fu_crossbar [0:15][0:1]; - logic [2:0] ctrl_mem__prologue_count_outport_routing_crossbar [0:15][0:3]; - logic [0:0] ctrl_mem__reset; - logic [4:0] ctrl_mem__tile_id; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a ctrl_mem__recv_from_element__msg; - logic [0:0] ctrl_mem__recv_from_element__rdy; - logic [0:0] ctrl_mem__recv_from_element__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_mem__recv_pkt_from_controller__msg; - logic [0:0] ctrl_mem__recv_pkt_from_controller__rdy; - logic [0:0] ctrl_mem__recv_pkt_from_controller__val; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 ctrl_mem__send_ctrl__msg; - logic [0:0] ctrl_mem__send_ctrl__rdy; - logic [0:0] ctrl_mem__send_ctrl__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_mem__send_pkt_to_controller__msg; - logic [0:0] ctrl_mem__send_pkt_to_controller__rdy; - logic [0:0] ctrl_mem__send_pkt_to_controller__val; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a ctrl_mem__send_to_element__msg; - logic [0:0] ctrl_mem__send_to_element__rdy; - logic [0:0] ctrl_mem__send_to_element__val; - - CtrlMemDynamicRTL__427d547b7d58aa8e ctrl_mem - ( - .cgra_id( ctrl_mem__cgra_id ), - .clk( ctrl_mem__clk ), - .ctrl_addr_outport( ctrl_mem__ctrl_addr_outport ), - .prologue_count_outport_fu( ctrl_mem__prologue_count_outport_fu ), - .prologue_count_outport_fu_crossbar( ctrl_mem__prologue_count_outport_fu_crossbar ), - .prologue_count_outport_routing_crossbar( ctrl_mem__prologue_count_outport_routing_crossbar ), - .reset( ctrl_mem__reset ), - .tile_id( ctrl_mem__tile_id ), - .recv_from_element__msg( ctrl_mem__recv_from_element__msg ), - .recv_from_element__rdy( ctrl_mem__recv_from_element__rdy ), - .recv_from_element__val( ctrl_mem__recv_from_element__val ), - .recv_pkt_from_controller__msg( ctrl_mem__recv_pkt_from_controller__msg ), - .recv_pkt_from_controller__rdy( ctrl_mem__recv_pkt_from_controller__rdy ), - .recv_pkt_from_controller__val( ctrl_mem__recv_pkt_from_controller__val ), - .send_ctrl__msg( ctrl_mem__send_ctrl__msg ), - .send_ctrl__rdy( ctrl_mem__send_ctrl__rdy ), - .send_ctrl__val( ctrl_mem__send_ctrl__val ), - .send_pkt_to_controller__msg( ctrl_mem__send_pkt_to_controller__msg ), - .send_pkt_to_controller__rdy( ctrl_mem__send_pkt_to_controller__rdy ), - .send_pkt_to_controller__val( ctrl_mem__send_pkt_to_controller__val ), - .send_to_element__msg( ctrl_mem__send_to_element__msg ), - .send_to_element__rdy( ctrl_mem__send_to_element__rdy ), - .send_to_element__val( ctrl_mem__send_to_element__val ) - ); - - //------------------------------------------------------------- - // End of component ctrl_mem - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component element - //------------------------------------------------------------- - - logic [0:0] element__clear [0:14]; - logic [0:0] element__clk; - logic [2:0] element__prologue_count_inport; - logic [0:0] element__reset; - logic [4:0] element__tile_id; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__from_mem_rdata__msg [0:14]; - logic [0:0] element__from_mem_rdata__rdy [0:14]; - logic [0:0] element__from_mem_rdata__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__recv_const__msg; - logic [0:0] element__recv_const__rdy; - logic [0:0] element__recv_const__val; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a element__recv_from_ctrl_mem__msg; - logic [0:0] element__recv_from_ctrl_mem__rdy; - logic [0:0] element__recv_from_ctrl_mem__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__recv_in__msg [0:3]; - logic [0:0] element__recv_in__rdy [0:3]; - logic [0:0] element__recv_in__val [0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 element__recv_opt__msg; - logic [0:0] element__recv_opt__rdy; - logic [0:0] element__recv_opt__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__send_out__msg [0:1]; - logic [0:0] element__send_out__rdy [0:1]; - logic [0:0] element__send_out__val [0:1]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a element__send_to_ctrl_mem__msg; - logic [0:0] element__send_to_ctrl_mem__rdy; - logic [0:0] element__send_to_ctrl_mem__val; - logic [6:0] element__to_mem_raddr__msg [0:14]; - logic [0:0] element__to_mem_raddr__rdy [0:14]; - logic [0:0] element__to_mem_raddr__val [0:14]; - logic [6:0] element__to_mem_waddr__msg [0:14]; - logic [0:0] element__to_mem_waddr__rdy [0:14]; - logic [0:0] element__to_mem_waddr__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__to_mem_wdata__msg [0:14]; - logic [0:0] element__to_mem_wdata__rdy [0:14]; - logic [0:0] element__to_mem_wdata__val [0:14]; - - FlexibleFuRTL__07217382918d0fc2 element - ( - .clear( element__clear ), - .clk( element__clk ), - .prologue_count_inport( element__prologue_count_inport ), - .reset( element__reset ), - .tile_id( element__tile_id ), - .from_mem_rdata__msg( element__from_mem_rdata__msg ), - .from_mem_rdata__rdy( element__from_mem_rdata__rdy ), - .from_mem_rdata__val( element__from_mem_rdata__val ), - .recv_const__msg( element__recv_const__msg ), - .recv_const__rdy( element__recv_const__rdy ), - .recv_const__val( element__recv_const__val ), - .recv_from_ctrl_mem__msg( element__recv_from_ctrl_mem__msg ), - .recv_from_ctrl_mem__rdy( element__recv_from_ctrl_mem__rdy ), - .recv_from_ctrl_mem__val( element__recv_from_ctrl_mem__val ), - .recv_in__msg( element__recv_in__msg ), - .recv_in__rdy( element__recv_in__rdy ), - .recv_in__val( element__recv_in__val ), - .recv_opt__msg( element__recv_opt__msg ), - .recv_opt__rdy( element__recv_opt__rdy ), - .recv_opt__val( element__recv_opt__val ), - .send_out__msg( element__send_out__msg ), - .send_out__rdy( element__send_out__rdy ), - .send_out__val( element__send_out__val ), - .send_to_ctrl_mem__msg( element__send_to_ctrl_mem__msg ), - .send_to_ctrl_mem__rdy( element__send_to_ctrl_mem__rdy ), - .send_to_ctrl_mem__val( element__send_to_ctrl_mem__val ), - .to_mem_raddr__msg( element__to_mem_raddr__msg ), - .to_mem_raddr__rdy( element__to_mem_raddr__rdy ), - .to_mem_raddr__val( element__to_mem_raddr__val ), - .to_mem_waddr__msg( element__to_mem_waddr__msg ), - .to_mem_waddr__rdy( element__to_mem_waddr__rdy ), - .to_mem_waddr__val( element__to_mem_waddr__val ), - .to_mem_wdata__msg( element__to_mem_wdata__msg ), - .to_mem_wdata__rdy( element__to_mem_wdata__rdy ), - .to_mem_wdata__val( element__to_mem_wdata__val ) - ); - - //------------------------------------------------------------- - // End of component element - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component fu_crossbar - //------------------------------------------------------------- - - logic [1:0] fu_crossbar__cgra_id; - logic [0:0] fu_crossbar__clear; - logic [0:0] fu_crossbar__clk; - logic [0:0] fu_crossbar__compute_done; - logic [0:0] fu_crossbar__crossbar_id; - logic [1:0] fu_crossbar__crossbar_outport [0:7]; - logic [3:0] fu_crossbar__ctrl_addr_inport; - logic [2:0] fu_crossbar__prologue_count_inport [0:15][0:1]; - logic [0:0] fu_crossbar__reset; - logic [4:0] fu_crossbar__tile_id; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu_crossbar__recv_data__msg [0:1]; - logic [0:0] fu_crossbar__recv_data__rdy [0:1]; - logic [0:0] fu_crossbar__recv_data__val [0:1]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 fu_crossbar__recv_opt__msg; - logic [0:0] fu_crossbar__recv_opt__rdy; - logic [0:0] fu_crossbar__recv_opt__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu_crossbar__send_data__msg [0:7]; - logic [0:0] fu_crossbar__send_data__rdy [0:7]; - logic [0:0] fu_crossbar__send_data__val [0:7]; - - CrossbarRTL__45ee026205c61975 fu_crossbar - ( - .cgra_id( fu_crossbar__cgra_id ), - .clear( fu_crossbar__clear ), - .clk( fu_crossbar__clk ), - .compute_done( fu_crossbar__compute_done ), - .crossbar_id( fu_crossbar__crossbar_id ), - .crossbar_outport( fu_crossbar__crossbar_outport ), - .ctrl_addr_inport( fu_crossbar__ctrl_addr_inport ), - .prologue_count_inport( fu_crossbar__prologue_count_inport ), - .reset( fu_crossbar__reset ), - .tile_id( fu_crossbar__tile_id ), - .recv_data__msg( fu_crossbar__recv_data__msg ), - .recv_data__rdy( fu_crossbar__recv_data__rdy ), - .recv_data__val( fu_crossbar__recv_data__val ), - .recv_opt__msg( fu_crossbar__recv_opt__msg ), - .recv_opt__rdy( fu_crossbar__recv_opt__rdy ), - .recv_opt__val( fu_crossbar__recv_opt__val ), - .send_data__msg( fu_crossbar__send_data__msg ), - .send_data__rdy( fu_crossbar__send_data__rdy ), - .send_data__val( fu_crossbar__send_data__val ) - ); - - //------------------------------------------------------------- - // End of component fu_crossbar - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component register_cluster - //------------------------------------------------------------- - - logic [0:0] register_cluster__clk; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 register_cluster__inport_opt; - logic [0:0] register_cluster__reset; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_const__msg [0:3]; - logic [0:0] register_cluster__recv_data_from_const__rdy [0:3]; - logic [0:0] register_cluster__recv_data_from_const__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_fu_crossbar__msg [0:3]; - logic [0:0] register_cluster__recv_data_from_fu_crossbar__rdy [0:3]; - logic [0:0] register_cluster__recv_data_from_fu_crossbar__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_routing_crossbar__msg [0:3]; - logic [0:0] register_cluster__recv_data_from_routing_crossbar__rdy [0:3]; - logic [0:0] register_cluster__recv_data_from_routing_crossbar__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__send_data_to_fu__msg [0:3]; - logic [0:0] register_cluster__send_data_to_fu__rdy [0:3]; - logic [0:0] register_cluster__send_data_to_fu__val [0:3]; - - RegisterClusterRTL__7f2febb613462546 register_cluster - ( - .clk( register_cluster__clk ), - .inport_opt( register_cluster__inport_opt ), - .reset( register_cluster__reset ), - .recv_data_from_const__msg( register_cluster__recv_data_from_const__msg ), - .recv_data_from_const__rdy( register_cluster__recv_data_from_const__rdy ), - .recv_data_from_const__val( register_cluster__recv_data_from_const__val ), - .recv_data_from_fu_crossbar__msg( register_cluster__recv_data_from_fu_crossbar__msg ), - .recv_data_from_fu_crossbar__rdy( register_cluster__recv_data_from_fu_crossbar__rdy ), - .recv_data_from_fu_crossbar__val( register_cluster__recv_data_from_fu_crossbar__val ), - .recv_data_from_routing_crossbar__msg( register_cluster__recv_data_from_routing_crossbar__msg ), - .recv_data_from_routing_crossbar__rdy( register_cluster__recv_data_from_routing_crossbar__rdy ), - .recv_data_from_routing_crossbar__val( register_cluster__recv_data_from_routing_crossbar__val ), - .send_data_to_fu__msg( register_cluster__send_data_to_fu__msg ), - .send_data_to_fu__rdy( register_cluster__send_data_to_fu__rdy ), - .send_data_to_fu__val( register_cluster__send_data_to_fu__val ) - ); - - //------------------------------------------------------------- - // End of component register_cluster - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component routing_crossbar - //------------------------------------------------------------- - - logic [1:0] routing_crossbar__cgra_id; - logic [0:0] routing_crossbar__clear; - logic [0:0] routing_crossbar__clk; - logic [0:0] routing_crossbar__compute_done; - logic [0:0] routing_crossbar__crossbar_id; - logic [2:0] routing_crossbar__crossbar_outport [0:7]; - logic [3:0] routing_crossbar__ctrl_addr_inport; - logic [2:0] routing_crossbar__prologue_count_inport [0:15][0:3]; - logic [0:0] routing_crossbar__reset; - logic [4:0] routing_crossbar__tile_id; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 routing_crossbar__recv_data__msg [0:3]; - logic [0:0] routing_crossbar__recv_data__rdy [0:3]; - logic [0:0] routing_crossbar__recv_data__val [0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 routing_crossbar__recv_opt__msg; - logic [0:0] routing_crossbar__recv_opt__rdy; - logic [0:0] routing_crossbar__recv_opt__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 routing_crossbar__send_data__msg [0:7]; - logic [0:0] routing_crossbar__send_data__rdy [0:7]; - logic [0:0] routing_crossbar__send_data__val [0:7]; - - CrossbarRTL__cad4150dfdc32fbd routing_crossbar - ( - .cgra_id( routing_crossbar__cgra_id ), - .clear( routing_crossbar__clear ), - .clk( routing_crossbar__clk ), - .compute_done( routing_crossbar__compute_done ), - .crossbar_id( routing_crossbar__crossbar_id ), - .crossbar_outport( routing_crossbar__crossbar_outport ), - .ctrl_addr_inport( routing_crossbar__ctrl_addr_inport ), - .prologue_count_inport( routing_crossbar__prologue_count_inport ), - .reset( routing_crossbar__reset ), - .tile_id( routing_crossbar__tile_id ), - .recv_data__msg( routing_crossbar__recv_data__msg ), - .recv_data__rdy( routing_crossbar__recv_data__rdy ), - .recv_data__val( routing_crossbar__recv_data__val ), - .recv_opt__msg( routing_crossbar__recv_opt__msg ), - .recv_opt__rdy( routing_crossbar__recv_opt__rdy ), - .recv_opt__val( routing_crossbar__recv_opt__val ), - .send_data__msg( routing_crossbar__send_data__msg ), - .send_data__rdy( routing_crossbar__send_data__rdy ), - .send_data__val( routing_crossbar__send_data__val ) - ); - - //------------------------------------------------------------- - // End of component routing_crossbar - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component tile_in_channel[0:3] - //------------------------------------------------------------- - - logic [0:0] tile_in_channel__clk [0:3]; - logic [0:0] tile_in_channel__reset [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_in_channel__recv__msg [0:3]; - logic [0:0] tile_in_channel__recv__rdy [0:3]; - logic [0:0] tile_in_channel__recv__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_in_channel__send__msg [0:3]; - logic [0:0] tile_in_channel__send__rdy [0:3]; - logic [0:0] tile_in_channel__send__val [0:3]; - - ChannelRTL__694d252f21ac798b tile_in_channel__0 - ( - .clk( tile_in_channel__clk[0] ), - .reset( tile_in_channel__reset[0] ), - .recv__msg( tile_in_channel__recv__msg[0] ), - .recv__rdy( tile_in_channel__recv__rdy[0] ), - .recv__val( tile_in_channel__recv__val[0] ), - .send__msg( tile_in_channel__send__msg[0] ), - .send__rdy( tile_in_channel__send__rdy[0] ), - .send__val( tile_in_channel__send__val[0] ) - ); - - ChannelRTL__694d252f21ac798b tile_in_channel__1 - ( - .clk( tile_in_channel__clk[1] ), - .reset( tile_in_channel__reset[1] ), - .recv__msg( tile_in_channel__recv__msg[1] ), - .recv__rdy( tile_in_channel__recv__rdy[1] ), - .recv__val( tile_in_channel__recv__val[1] ), - .send__msg( tile_in_channel__send__msg[1] ), - .send__rdy( tile_in_channel__send__rdy[1] ), - .send__val( tile_in_channel__send__val[1] ) - ); - - ChannelRTL__694d252f21ac798b tile_in_channel__2 - ( - .clk( tile_in_channel__clk[2] ), - .reset( tile_in_channel__reset[2] ), - .recv__msg( tile_in_channel__recv__msg[2] ), - .recv__rdy( tile_in_channel__recv__rdy[2] ), - .recv__val( tile_in_channel__recv__val[2] ), - .send__msg( tile_in_channel__send__msg[2] ), - .send__rdy( tile_in_channel__send__rdy[2] ), - .send__val( tile_in_channel__send__val[2] ) - ); - - ChannelRTL__694d252f21ac798b tile_in_channel__3 - ( - .clk( tile_in_channel__clk[3] ), - .reset( tile_in_channel__reset[3] ), - .recv__msg( tile_in_channel__recv__msg[3] ), - .recv__rdy( tile_in_channel__recv__rdy[3] ), - .recv__val( tile_in_channel__recv__val[3] ), - .send__msg( tile_in_channel__send__msg[3] ), - .send__rdy( tile_in_channel__send__rdy[3] ), - .send__val( tile_in_channel__send__val[3] ) - ); - - //------------------------------------------------------------- - // End of component tile_in_channel[0:3] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component tile_out_or_link[0:3] - //------------------------------------------------------------- - - logic [0:0] tile_out_or_link__clk [0:3]; - logic [0:0] tile_out_or_link__reset [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__recv_fu__msg [0:3]; - logic [0:0] tile_out_or_link__recv_fu__rdy [0:3]; - logic [0:0] tile_out_or_link__recv_fu__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__recv_xbar__msg [0:3]; - logic [0:0] tile_out_or_link__recv_xbar__rdy [0:3]; - logic [0:0] tile_out_or_link__recv_xbar__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__send__msg [0:3]; - logic [0:0] tile_out_or_link__send__rdy [0:3]; - logic [0:0] tile_out_or_link__send__val [0:3]; - - LinkOrRTL__0fce34ff986f61fe tile_out_or_link__0 - ( - .clk( tile_out_or_link__clk[0] ), - .reset( tile_out_or_link__reset[0] ), - .recv_fu__msg( tile_out_or_link__recv_fu__msg[0] ), - .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[0] ), - .recv_fu__val( tile_out_or_link__recv_fu__val[0] ), - .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[0] ), - .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[0] ), - .recv_xbar__val( tile_out_or_link__recv_xbar__val[0] ), - .send__msg( tile_out_or_link__send__msg[0] ), - .send__rdy( tile_out_or_link__send__rdy[0] ), - .send__val( tile_out_or_link__send__val[0] ) - ); - - LinkOrRTL__0fce34ff986f61fe tile_out_or_link__1 - ( - .clk( tile_out_or_link__clk[1] ), - .reset( tile_out_or_link__reset[1] ), - .recv_fu__msg( tile_out_or_link__recv_fu__msg[1] ), - .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[1] ), - .recv_fu__val( tile_out_or_link__recv_fu__val[1] ), - .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[1] ), - .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[1] ), - .recv_xbar__val( tile_out_or_link__recv_xbar__val[1] ), - .send__msg( tile_out_or_link__send__msg[1] ), - .send__rdy( tile_out_or_link__send__rdy[1] ), - .send__val( tile_out_or_link__send__val[1] ) - ); - - LinkOrRTL__0fce34ff986f61fe tile_out_or_link__2 - ( - .clk( tile_out_or_link__clk[2] ), - .reset( tile_out_or_link__reset[2] ), - .recv_fu__msg( tile_out_or_link__recv_fu__msg[2] ), - .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[2] ), - .recv_fu__val( tile_out_or_link__recv_fu__val[2] ), - .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[2] ), - .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[2] ), - .recv_xbar__val( tile_out_or_link__recv_xbar__val[2] ), - .send__msg( tile_out_or_link__send__msg[2] ), - .send__rdy( tile_out_or_link__send__rdy[2] ), - .send__val( tile_out_or_link__send__val[2] ) - ); - - LinkOrRTL__0fce34ff986f61fe tile_out_or_link__3 - ( - .clk( tile_out_or_link__clk[3] ), - .reset( tile_out_or_link__reset[3] ), - .recv_fu__msg( tile_out_or_link__recv_fu__msg[3] ), - .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[3] ), - .recv_fu__val( tile_out_or_link__recv_fu__val[3] ), - .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[3] ), - .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[3] ), - .recv_xbar__val( tile_out_or_link__recv_xbar__val[3] ), - .send__msg( tile_out_or_link__send__msg[3] ), - .send__rdy( tile_out_or_link__send__rdy[3] ), - .send__val( tile_out_or_link__send__val[3] ) - ); - - //------------------------------------------------------------- - // End of component tile_out_or_link[0:3] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:236 - // @update - // def feed_pkt(): - // s.ctrl_mem.recv_pkt_from_controller.msg @= CtrlPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) # , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.const_mem.recv_const.msg @= DataType(0, 0, 0, 0) - // s.ctrl_mem.recv_pkt_from_controller.val @= 0 - // s.const_mem.recv_const.val @= 0 - // s.recv_from_controller_pkt.rdy @= 0 - // - // if s.recv_from_controller_pkt.val & \ - // ((s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_LAUNCH)): - // s.ctrl_mem.recv_pkt_from_controller.val @= 1 - // s.ctrl_mem.recv_pkt_from_controller.msg @= s.recv_from_controller_pkt.msg - // s.recv_from_controller_pkt.rdy @= s.ctrl_mem.recv_pkt_from_controller.rdy - // elif s.recv_from_controller_pkt.val & (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONST): - // s.const_mem.recv_const.val @= 1 - // s.const_mem.recv_const.msg @= s.recv_from_controller_pkt.msg.payload.data - // s.recv_from_controller_pkt.rdy @= s.const_mem.recv_const.rdy - - always_comb begin : feed_pkt - ctrl_mem__recv_pkt_from_controller__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; - const_mem__recv_const__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - ctrl_mem__recv_pkt_from_controller__val = 1'd0; - const_mem__recv_const__val = 1'd0; - recv_from_controller_pkt__rdy = 1'd0; - if ( recv_from_controller_pkt__val & ( ( ( ( ( ( ( ( ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) ) begin - ctrl_mem__recv_pkt_from_controller__val = 1'd1; - ctrl_mem__recv_pkt_from_controller__msg = recv_from_controller_pkt__msg; - recv_from_controller_pkt__rdy = ctrl_mem__recv_pkt_from_controller__rdy; - end - else if ( recv_from_controller_pkt__val & ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONST ) ) ) begin - const_mem__recv_const__val = 1'd1; - const_mem__recv_const__msg = recv_from_controller_pkt__msg.payload.data; - recv_from_controller_pkt__rdy = const_mem__recv_const__rdy; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:292 - // @update - // def notify_const_mem(): - // s.const_mem.ctrl_proceed @= s.ctrl_mem.send_ctrl.rdy & s.ctrl_mem.send_ctrl.val - - always_comb begin : notify_const_mem - const_mem__ctrl_proceed = ctrl_mem__send_ctrl__rdy & ctrl_mem__send_ctrl__val; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:311 - // @update - // def notify_crossbars_compute_status(): - // s.routing_crossbar.compute_done @= s.element_done - // s.fu_crossbar.compute_done @= s.element_done - - always_comb begin : notify_crossbars_compute_status - routing_crossbar__compute_done = element_done; - fu_crossbar__compute_done = element_done; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:272 - // @update - // def update_opt(): - // s.element.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg - // s.routing_crossbar.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg - // s.fu_crossbar.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg - // - // # FIXME: Do we still need separate element and routing_xbar? - // # FIXME: Do we need to consider reg bank here? - // s.element.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.element_done - // s.routing_crossbar.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.routing_crossbar_done - // s.fu_crossbar.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.fu_crossbar_done - // - // # FIXME: yo96, rename ctrl.rdy to ctrl.proceed or sth similar. - // # Allows either the FU-related go out first or routing-xbar go out first. And only - // # allows the ctrl signal proceed till all the sub-modules done their own job (once). - // s.ctrl_mem.send_ctrl.rdy @= (s.element.recv_opt.rdy | s.element_done) & \ - // (s.routing_crossbar.recv_opt.rdy | s.routing_crossbar_done) & \ - // (s.fu_crossbar.recv_opt.rdy | s.fu_crossbar_done) - - always_comb begin : update_opt - element__recv_opt__msg = ctrl_mem__send_ctrl__msg; - routing_crossbar__recv_opt__msg = ctrl_mem__send_ctrl__msg; - fu_crossbar__recv_opt__msg = ctrl_mem__send_ctrl__msg; - element__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~element_done ); - routing_crossbar__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~routing_crossbar_done ); - fu_crossbar__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~fu_crossbar_done ); - ctrl_mem__send_ctrl__rdy = ( ( element__recv_opt__rdy | element_done ) & ( routing_crossbar__recv_opt__rdy | routing_crossbar_done ) ) & ( fu_crossbar__recv_opt__rdy | fu_crossbar_done ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:262 - // @update - // def update_send_out_signal(): - // s.send_to_controller_pkt.val @= 0 - // s.send_to_controller_pkt.msg @= CtrlPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) # , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // if s.ctrl_mem.send_pkt_to_controller.val: - // s.send_to_controller_pkt.val @= 1 - // s.send_to_controller_pkt.msg @= s.ctrl_mem.send_pkt_to_controller.msg - // s.ctrl_mem.send_pkt_to_controller.rdy @= s.send_to_controller_pkt.rdy - - always_comb begin : update_send_out_signal - send_to_controller_pkt__val = 1'd0; - send_to_controller_pkt__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; - if ( ctrl_mem__send_pkt_to_controller__val ) begin - send_to_controller_pkt__val = 1'd1; - send_to_controller_pkt__msg = ctrl_mem__send_pkt_to_controller__msg; - end - ctrl_mem__send_pkt_to_controller__rdy = send_to_controller_pkt__rdy; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:297 - // @update_ff - // def already_done(): - // if s.reset | s.ctrl_mem.send_ctrl.rdy: - // s.element_done <<= 0 - // s.fu_crossbar_done <<= 0 - // s.routing_crossbar_done <<= 0 - // else: - // if s.element.recv_opt.rdy: - // s.element_done <<= 1 - // if s.fu_crossbar.recv_opt.rdy: - // s.fu_crossbar_done <<= 1 - // if s.routing_crossbar.recv_opt.rdy: - // s.routing_crossbar_done <<= 1 - - always_ff @(posedge clk) begin : already_done - if ( reset | ctrl_mem__send_ctrl__rdy ) begin - element_done <= 1'd0; - fu_crossbar_done <= 1'd0; - routing_crossbar_done <= 1'd0; - end - else begin - if ( element__recv_opt__rdy ) begin - element_done <= 1'd1; - end - if ( fu_crossbar__recv_opt__rdy ) begin - fu_crossbar_done <= 1'd1; - end - if ( routing_crossbar__recv_opt__rdy ) begin - routing_crossbar_done <= 1'd1; - end - end - end - - assign element__clk = clk; - assign element__reset = reset; - assign const_mem__clk = clk; - assign const_mem__reset = reset; - assign routing_crossbar__clk = clk; - assign routing_crossbar__reset = reset; - assign fu_crossbar__clk = clk; - assign fu_crossbar__reset = reset; - assign register_cluster__clk = clk; - assign register_cluster__reset = reset; - assign ctrl_mem__clk = clk; - assign ctrl_mem__reset = reset; - assign tile_in_channel__clk[0] = clk; - assign tile_in_channel__reset[0] = reset; - assign tile_in_channel__clk[1] = clk; - assign tile_in_channel__reset[1] = reset; - assign tile_in_channel__clk[2] = clk; - assign tile_in_channel__reset[2] = reset; - assign tile_in_channel__clk[3] = clk; - assign tile_in_channel__reset[3] = reset; - assign tile_out_or_link__clk[0] = clk; - assign tile_out_or_link__reset[0] = reset; - assign tile_out_or_link__clk[1] = clk; - assign tile_out_or_link__reset[1] = reset; - assign tile_out_or_link__clk[2] = clk; - assign tile_out_or_link__reset[2] = reset; - assign tile_out_or_link__clk[3] = clk; - assign tile_out_or_link__reset[3] = reset; - assign element__tile_id = tile_id; - assign ctrl_mem__cgra_id = cgra_id; - assign ctrl_mem__tile_id = tile_id; - assign fu_crossbar__cgra_id = cgra_id; - assign fu_crossbar__tile_id = tile_id; - assign routing_crossbar__cgra_id = cgra_id; - assign routing_crossbar__tile_id = tile_id; - assign routing_crossbar__crossbar_id = 1'd0; - assign fu_crossbar__crossbar_id = 1'd1; - assign element__recv_const__msg = const_mem__send_const__msg; - assign const_mem__send_const__rdy = element__recv_const__rdy; - assign element__recv_const__val = const_mem__send_const__val; - assign ctrl_mem__recv_from_element__msg = element__send_to_ctrl_mem__msg; - assign element__send_to_ctrl_mem__rdy = ctrl_mem__recv_from_element__rdy; - assign ctrl_mem__recv_from_element__val = element__send_to_ctrl_mem__val; - assign element__recv_from_ctrl_mem__msg = ctrl_mem__send_to_element__msg; - assign ctrl_mem__send_to_element__rdy = element__recv_from_ctrl_mem__rdy; - assign element__recv_from_ctrl_mem__val = ctrl_mem__send_to_element__val; - assign routing_crossbar__ctrl_addr_inport = ctrl_mem__ctrl_addr_outport; - assign fu_crossbar__ctrl_addr_inport = ctrl_mem__ctrl_addr_outport; - assign element__prologue_count_inport = ctrl_mem__prologue_count_outport_fu; - assign routing_crossbar__prologue_count_inport[0][0] = ctrl_mem__prologue_count_outport_routing_crossbar[0][0]; - assign routing_crossbar__prologue_count_inport[0][1] = ctrl_mem__prologue_count_outport_routing_crossbar[0][1]; - assign routing_crossbar__prologue_count_inport[0][2] = ctrl_mem__prologue_count_outport_routing_crossbar[0][2]; - assign routing_crossbar__prologue_count_inport[0][3] = ctrl_mem__prologue_count_outport_routing_crossbar[0][3]; - assign fu_crossbar__prologue_count_inport[0][0] = ctrl_mem__prologue_count_outport_fu_crossbar[0][0]; - assign fu_crossbar__prologue_count_inport[0][1] = ctrl_mem__prologue_count_outport_fu_crossbar[0][1]; - assign routing_crossbar__prologue_count_inport[1][0] = ctrl_mem__prologue_count_outport_routing_crossbar[1][0]; - assign routing_crossbar__prologue_count_inport[1][1] = ctrl_mem__prologue_count_outport_routing_crossbar[1][1]; - assign routing_crossbar__prologue_count_inport[1][2] = ctrl_mem__prologue_count_outport_routing_crossbar[1][2]; - assign routing_crossbar__prologue_count_inport[1][3] = ctrl_mem__prologue_count_outport_routing_crossbar[1][3]; - assign fu_crossbar__prologue_count_inport[1][0] = ctrl_mem__prologue_count_outport_fu_crossbar[1][0]; - assign fu_crossbar__prologue_count_inport[1][1] = ctrl_mem__prologue_count_outport_fu_crossbar[1][1]; - assign routing_crossbar__prologue_count_inport[2][0] = ctrl_mem__prologue_count_outport_routing_crossbar[2][0]; - assign routing_crossbar__prologue_count_inport[2][1] = ctrl_mem__prologue_count_outport_routing_crossbar[2][1]; - assign routing_crossbar__prologue_count_inport[2][2] = ctrl_mem__prologue_count_outport_routing_crossbar[2][2]; - assign routing_crossbar__prologue_count_inport[2][3] = ctrl_mem__prologue_count_outport_routing_crossbar[2][3]; - assign fu_crossbar__prologue_count_inport[2][0] = ctrl_mem__prologue_count_outport_fu_crossbar[2][0]; - assign fu_crossbar__prologue_count_inport[2][1] = ctrl_mem__prologue_count_outport_fu_crossbar[2][1]; - assign routing_crossbar__prologue_count_inport[3][0] = ctrl_mem__prologue_count_outport_routing_crossbar[3][0]; - assign routing_crossbar__prologue_count_inport[3][1] = ctrl_mem__prologue_count_outport_routing_crossbar[3][1]; - assign routing_crossbar__prologue_count_inport[3][2] = ctrl_mem__prologue_count_outport_routing_crossbar[3][2]; - assign routing_crossbar__prologue_count_inport[3][3] = ctrl_mem__prologue_count_outport_routing_crossbar[3][3]; - assign fu_crossbar__prologue_count_inport[3][0] = ctrl_mem__prologue_count_outport_fu_crossbar[3][0]; - assign fu_crossbar__prologue_count_inport[3][1] = ctrl_mem__prologue_count_outport_fu_crossbar[3][1]; - assign routing_crossbar__prologue_count_inport[4][0] = ctrl_mem__prologue_count_outport_routing_crossbar[4][0]; - assign routing_crossbar__prologue_count_inport[4][1] = ctrl_mem__prologue_count_outport_routing_crossbar[4][1]; - assign routing_crossbar__prologue_count_inport[4][2] = ctrl_mem__prologue_count_outport_routing_crossbar[4][2]; - assign routing_crossbar__prologue_count_inport[4][3] = ctrl_mem__prologue_count_outport_routing_crossbar[4][3]; - assign fu_crossbar__prologue_count_inport[4][0] = ctrl_mem__prologue_count_outport_fu_crossbar[4][0]; - assign fu_crossbar__prologue_count_inport[4][1] = ctrl_mem__prologue_count_outport_fu_crossbar[4][1]; - assign routing_crossbar__prologue_count_inport[5][0] = ctrl_mem__prologue_count_outport_routing_crossbar[5][0]; - assign routing_crossbar__prologue_count_inport[5][1] = ctrl_mem__prologue_count_outport_routing_crossbar[5][1]; - assign routing_crossbar__prologue_count_inport[5][2] = ctrl_mem__prologue_count_outport_routing_crossbar[5][2]; - assign routing_crossbar__prologue_count_inport[5][3] = ctrl_mem__prologue_count_outport_routing_crossbar[5][3]; - assign fu_crossbar__prologue_count_inport[5][0] = ctrl_mem__prologue_count_outport_fu_crossbar[5][0]; - assign fu_crossbar__prologue_count_inport[5][1] = ctrl_mem__prologue_count_outport_fu_crossbar[5][1]; - assign routing_crossbar__prologue_count_inport[6][0] = ctrl_mem__prologue_count_outport_routing_crossbar[6][0]; - assign routing_crossbar__prologue_count_inport[6][1] = ctrl_mem__prologue_count_outport_routing_crossbar[6][1]; - assign routing_crossbar__prologue_count_inport[6][2] = ctrl_mem__prologue_count_outport_routing_crossbar[6][2]; - assign routing_crossbar__prologue_count_inport[6][3] = ctrl_mem__prologue_count_outport_routing_crossbar[6][3]; - assign fu_crossbar__prologue_count_inport[6][0] = ctrl_mem__prologue_count_outport_fu_crossbar[6][0]; - assign fu_crossbar__prologue_count_inport[6][1] = ctrl_mem__prologue_count_outport_fu_crossbar[6][1]; - assign routing_crossbar__prologue_count_inport[7][0] = ctrl_mem__prologue_count_outport_routing_crossbar[7][0]; - assign routing_crossbar__prologue_count_inport[7][1] = ctrl_mem__prologue_count_outport_routing_crossbar[7][1]; - assign routing_crossbar__prologue_count_inport[7][2] = ctrl_mem__prologue_count_outport_routing_crossbar[7][2]; - assign routing_crossbar__prologue_count_inport[7][3] = ctrl_mem__prologue_count_outport_routing_crossbar[7][3]; - assign fu_crossbar__prologue_count_inport[7][0] = ctrl_mem__prologue_count_outport_fu_crossbar[7][0]; - assign fu_crossbar__prologue_count_inport[7][1] = ctrl_mem__prologue_count_outport_fu_crossbar[7][1]; - assign routing_crossbar__prologue_count_inport[8][0] = ctrl_mem__prologue_count_outport_routing_crossbar[8][0]; - assign routing_crossbar__prologue_count_inport[8][1] = ctrl_mem__prologue_count_outport_routing_crossbar[8][1]; - assign routing_crossbar__prologue_count_inport[8][2] = ctrl_mem__prologue_count_outport_routing_crossbar[8][2]; - assign routing_crossbar__prologue_count_inport[8][3] = ctrl_mem__prologue_count_outport_routing_crossbar[8][3]; - assign fu_crossbar__prologue_count_inport[8][0] = ctrl_mem__prologue_count_outport_fu_crossbar[8][0]; - assign fu_crossbar__prologue_count_inport[8][1] = ctrl_mem__prologue_count_outport_fu_crossbar[8][1]; - assign routing_crossbar__prologue_count_inport[9][0] = ctrl_mem__prologue_count_outport_routing_crossbar[9][0]; - assign routing_crossbar__prologue_count_inport[9][1] = ctrl_mem__prologue_count_outport_routing_crossbar[9][1]; - assign routing_crossbar__prologue_count_inport[9][2] = ctrl_mem__prologue_count_outport_routing_crossbar[9][2]; - assign routing_crossbar__prologue_count_inport[9][3] = ctrl_mem__prologue_count_outport_routing_crossbar[9][3]; - assign fu_crossbar__prologue_count_inport[9][0] = ctrl_mem__prologue_count_outport_fu_crossbar[9][0]; - assign fu_crossbar__prologue_count_inport[9][1] = ctrl_mem__prologue_count_outport_fu_crossbar[9][1]; - assign routing_crossbar__prologue_count_inport[10][0] = ctrl_mem__prologue_count_outport_routing_crossbar[10][0]; - assign routing_crossbar__prologue_count_inport[10][1] = ctrl_mem__prologue_count_outport_routing_crossbar[10][1]; - assign routing_crossbar__prologue_count_inport[10][2] = ctrl_mem__prologue_count_outport_routing_crossbar[10][2]; - assign routing_crossbar__prologue_count_inport[10][3] = ctrl_mem__prologue_count_outport_routing_crossbar[10][3]; - assign fu_crossbar__prologue_count_inport[10][0] = ctrl_mem__prologue_count_outport_fu_crossbar[10][0]; - assign fu_crossbar__prologue_count_inport[10][1] = ctrl_mem__prologue_count_outport_fu_crossbar[10][1]; - assign routing_crossbar__prologue_count_inport[11][0] = ctrl_mem__prologue_count_outport_routing_crossbar[11][0]; - assign routing_crossbar__prologue_count_inport[11][1] = ctrl_mem__prologue_count_outport_routing_crossbar[11][1]; - assign routing_crossbar__prologue_count_inport[11][2] = ctrl_mem__prologue_count_outport_routing_crossbar[11][2]; - assign routing_crossbar__prologue_count_inport[11][3] = ctrl_mem__prologue_count_outport_routing_crossbar[11][3]; - assign fu_crossbar__prologue_count_inport[11][0] = ctrl_mem__prologue_count_outport_fu_crossbar[11][0]; - assign fu_crossbar__prologue_count_inport[11][1] = ctrl_mem__prologue_count_outport_fu_crossbar[11][1]; - assign routing_crossbar__prologue_count_inport[12][0] = ctrl_mem__prologue_count_outport_routing_crossbar[12][0]; - assign routing_crossbar__prologue_count_inport[12][1] = ctrl_mem__prologue_count_outport_routing_crossbar[12][1]; - assign routing_crossbar__prologue_count_inport[12][2] = ctrl_mem__prologue_count_outport_routing_crossbar[12][2]; - assign routing_crossbar__prologue_count_inport[12][3] = ctrl_mem__prologue_count_outport_routing_crossbar[12][3]; - assign fu_crossbar__prologue_count_inport[12][0] = ctrl_mem__prologue_count_outport_fu_crossbar[12][0]; - assign fu_crossbar__prologue_count_inport[12][1] = ctrl_mem__prologue_count_outport_fu_crossbar[12][1]; - assign routing_crossbar__prologue_count_inport[13][0] = ctrl_mem__prologue_count_outport_routing_crossbar[13][0]; - assign routing_crossbar__prologue_count_inport[13][1] = ctrl_mem__prologue_count_outport_routing_crossbar[13][1]; - assign routing_crossbar__prologue_count_inport[13][2] = ctrl_mem__prologue_count_outport_routing_crossbar[13][2]; - assign routing_crossbar__prologue_count_inport[13][3] = ctrl_mem__prologue_count_outport_routing_crossbar[13][3]; - assign fu_crossbar__prologue_count_inport[13][0] = ctrl_mem__prologue_count_outport_fu_crossbar[13][0]; - assign fu_crossbar__prologue_count_inport[13][1] = ctrl_mem__prologue_count_outport_fu_crossbar[13][1]; - assign routing_crossbar__prologue_count_inport[14][0] = ctrl_mem__prologue_count_outport_routing_crossbar[14][0]; - assign routing_crossbar__prologue_count_inport[14][1] = ctrl_mem__prologue_count_outport_routing_crossbar[14][1]; - assign routing_crossbar__prologue_count_inport[14][2] = ctrl_mem__prologue_count_outport_routing_crossbar[14][2]; - assign routing_crossbar__prologue_count_inport[14][3] = ctrl_mem__prologue_count_outport_routing_crossbar[14][3]; - assign fu_crossbar__prologue_count_inport[14][0] = ctrl_mem__prologue_count_outport_fu_crossbar[14][0]; - assign fu_crossbar__prologue_count_inport[14][1] = ctrl_mem__prologue_count_outport_fu_crossbar[14][1]; - assign routing_crossbar__prologue_count_inport[15][0] = ctrl_mem__prologue_count_outport_routing_crossbar[15][0]; - assign routing_crossbar__prologue_count_inport[15][1] = ctrl_mem__prologue_count_outport_routing_crossbar[15][1]; - assign routing_crossbar__prologue_count_inport[15][2] = ctrl_mem__prologue_count_outport_routing_crossbar[15][2]; - assign routing_crossbar__prologue_count_inport[15][3] = ctrl_mem__prologue_count_outport_routing_crossbar[15][3]; - assign fu_crossbar__prologue_count_inport[15][0] = ctrl_mem__prologue_count_outport_fu_crossbar[15][0]; - assign fu_crossbar__prologue_count_inport[15][1] = ctrl_mem__prologue_count_outport_fu_crossbar[15][1]; - assign element__to_mem_raddr__rdy[0] = 1'd0; - assign element__from_mem_rdata__val[0] = 1'd0; - assign element__from_mem_rdata__msg[0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[0] = 1'd0; - assign element__to_mem_wdata__rdy[0] = 1'd0; - assign element__to_mem_raddr__rdy[1] = 1'd0; - assign element__from_mem_rdata__val[1] = 1'd0; - assign element__from_mem_rdata__msg[1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[1] = 1'd0; - assign element__to_mem_wdata__rdy[1] = 1'd0; - assign element__to_mem_raddr__rdy[2] = 1'd0; - assign element__from_mem_rdata__val[2] = 1'd0; - assign element__from_mem_rdata__msg[2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[2] = 1'd0; - assign element__to_mem_wdata__rdy[2] = 1'd0; - assign element__to_mem_raddr__rdy[3] = 1'd0; - assign element__from_mem_rdata__val[3] = 1'd0; - assign element__from_mem_rdata__msg[3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[3] = 1'd0; - assign element__to_mem_wdata__rdy[3] = 1'd0; - assign element__to_mem_raddr__rdy[4] = 1'd0; - assign element__from_mem_rdata__val[4] = 1'd0; - assign element__from_mem_rdata__msg[4] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[4] = 1'd0; - assign element__to_mem_wdata__rdy[4] = 1'd0; - assign element__to_mem_raddr__rdy[5] = 1'd0; - assign element__from_mem_rdata__val[5] = 1'd0; - assign element__from_mem_rdata__msg[5] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[5] = 1'd0; - assign element__to_mem_wdata__rdy[5] = 1'd0; - assign element__to_mem_raddr__rdy[6] = 1'd0; - assign element__from_mem_rdata__val[6] = 1'd0; - assign element__from_mem_rdata__msg[6] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[6] = 1'd0; - assign element__to_mem_wdata__rdy[6] = 1'd0; - assign to_mem_raddr__msg = element__to_mem_raddr__msg[7]; - assign element__to_mem_raddr__rdy[7] = to_mem_raddr__rdy; - assign to_mem_raddr__val = element__to_mem_raddr__val[7]; - assign element__from_mem_rdata__msg[7] = from_mem_rdata__msg; - assign from_mem_rdata__rdy = element__from_mem_rdata__rdy[7]; - assign element__from_mem_rdata__val[7] = from_mem_rdata__val; - assign to_mem_waddr__msg = element__to_mem_waddr__msg[7]; - assign element__to_mem_waddr__rdy[7] = to_mem_waddr__rdy; - assign to_mem_waddr__val = element__to_mem_waddr__val[7]; - assign to_mem_wdata__msg = element__to_mem_wdata__msg[7]; - assign element__to_mem_wdata__rdy[7] = to_mem_wdata__rdy; - assign to_mem_wdata__val = element__to_mem_wdata__val[7]; - assign element__to_mem_raddr__rdy[8] = 1'd0; - assign element__from_mem_rdata__val[8] = 1'd0; - assign element__from_mem_rdata__msg[8] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[8] = 1'd0; - assign element__to_mem_wdata__rdy[8] = 1'd0; - assign element__to_mem_raddr__rdy[9] = 1'd0; - assign element__from_mem_rdata__val[9] = 1'd0; - assign element__from_mem_rdata__msg[9] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[9] = 1'd0; - assign element__to_mem_wdata__rdy[9] = 1'd0; - assign element__to_mem_raddr__rdy[10] = 1'd0; - assign element__from_mem_rdata__val[10] = 1'd0; - assign element__from_mem_rdata__msg[10] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[10] = 1'd0; - assign element__to_mem_wdata__rdy[10] = 1'd0; - assign element__to_mem_raddr__rdy[11] = 1'd0; - assign element__from_mem_rdata__val[11] = 1'd0; - assign element__from_mem_rdata__msg[11] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[11] = 1'd0; - assign element__to_mem_wdata__rdy[11] = 1'd0; - assign element__to_mem_raddr__rdy[12] = 1'd0; - assign element__from_mem_rdata__val[12] = 1'd0; - assign element__from_mem_rdata__msg[12] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[12] = 1'd0; - assign element__to_mem_wdata__rdy[12] = 1'd0; - assign element__to_mem_raddr__rdy[13] = 1'd0; - assign element__from_mem_rdata__val[13] = 1'd0; - assign element__from_mem_rdata__msg[13] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[13] = 1'd0; - assign element__to_mem_wdata__rdy[13] = 1'd0; - assign element__to_mem_raddr__rdy[14] = 1'd0; - assign element__from_mem_rdata__val[14] = 1'd0; - assign element__from_mem_rdata__msg[14] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[14] = 1'd0; - assign element__to_mem_wdata__rdy[14] = 1'd0; - assign tile_in_channel__recv__msg[0] = recv_data__msg[0]; - assign recv_data__rdy[0] = tile_in_channel__recv__rdy[0]; - assign tile_in_channel__recv__val[0] = recv_data__val[0]; - assign routing_crossbar__recv_data__msg[0] = tile_in_channel__send__msg[0]; - assign tile_in_channel__send__rdy[0] = routing_crossbar__recv_data__rdy[0]; - assign routing_crossbar__recv_data__val[0] = tile_in_channel__send__val[0]; - assign tile_in_channel__recv__msg[1] = recv_data__msg[1]; - assign recv_data__rdy[1] = tile_in_channel__recv__rdy[1]; - assign tile_in_channel__recv__val[1] = recv_data__val[1]; - assign routing_crossbar__recv_data__msg[1] = tile_in_channel__send__msg[1]; - assign tile_in_channel__send__rdy[1] = routing_crossbar__recv_data__rdy[1]; - assign routing_crossbar__recv_data__val[1] = tile_in_channel__send__val[1]; - assign tile_in_channel__recv__msg[2] = recv_data__msg[2]; - assign recv_data__rdy[2] = tile_in_channel__recv__rdy[2]; - assign tile_in_channel__recv__val[2] = recv_data__val[2]; - assign routing_crossbar__recv_data__msg[2] = tile_in_channel__send__msg[2]; - assign tile_in_channel__send__rdy[2] = routing_crossbar__recv_data__rdy[2]; - assign routing_crossbar__recv_data__val[2] = tile_in_channel__send__val[2]; - assign tile_in_channel__recv__msg[3] = recv_data__msg[3]; - assign recv_data__rdy[3] = tile_in_channel__recv__rdy[3]; - assign tile_in_channel__recv__val[3] = recv_data__val[3]; - assign routing_crossbar__recv_data__msg[3] = tile_in_channel__send__msg[3]; - assign tile_in_channel__send__rdy[3] = routing_crossbar__recv_data__rdy[3]; - assign routing_crossbar__recv_data__val[3] = tile_in_channel__send__val[3]; - assign routing_crossbar__crossbar_outport[0] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[0]; - assign fu_crossbar__crossbar_outport[0] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[0]; - assign routing_crossbar__crossbar_outport[1] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[1]; - assign fu_crossbar__crossbar_outport[1] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[1]; - assign routing_crossbar__crossbar_outport[2] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[2]; - assign fu_crossbar__crossbar_outport[2] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[2]; - assign routing_crossbar__crossbar_outport[3] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[3]; - assign fu_crossbar__crossbar_outport[3] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[3]; - assign routing_crossbar__crossbar_outport[4] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[4]; - assign fu_crossbar__crossbar_outport[4] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[4]; - assign routing_crossbar__crossbar_outport[5] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[5]; - assign fu_crossbar__crossbar_outport[5] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[5]; - assign routing_crossbar__crossbar_outport[6] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[6]; - assign fu_crossbar__crossbar_outport[6] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[6]; - assign routing_crossbar__crossbar_outport[7] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[7]; - assign fu_crossbar__crossbar_outport[7] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[7]; - assign fu_crossbar__recv_data__msg[0] = element__send_out__msg[0]; - assign element__send_out__rdy[0] = fu_crossbar__recv_data__rdy[0]; - assign fu_crossbar__recv_data__val[0] = element__send_out__val[0]; - assign fu_crossbar__recv_data__msg[1] = element__send_out__msg[1]; - assign element__send_out__rdy[1] = fu_crossbar__recv_data__rdy[1]; - assign fu_crossbar__recv_data__val[1] = element__send_out__val[1]; - assign tile_out_or_link__recv_fu__msg[0] = fu_crossbar__send_data__msg[0]; - assign fu_crossbar__send_data__rdy[0] = tile_out_or_link__recv_fu__rdy[0]; - assign tile_out_or_link__recv_fu__val[0] = fu_crossbar__send_data__val[0]; - assign tile_out_or_link__recv_xbar__msg[0] = routing_crossbar__send_data__msg[0]; - assign routing_crossbar__send_data__rdy[0] = tile_out_or_link__recv_xbar__rdy[0]; - assign tile_out_or_link__recv_xbar__val[0] = routing_crossbar__send_data__val[0]; - assign send_data__msg[0] = tile_out_or_link__send__msg[0]; - assign tile_out_or_link__send__rdy[0] = send_data__rdy[0]; - assign send_data__val[0] = tile_out_or_link__send__val[0]; - assign tile_out_or_link__recv_fu__msg[1] = fu_crossbar__send_data__msg[1]; - assign fu_crossbar__send_data__rdy[1] = tile_out_or_link__recv_fu__rdy[1]; - assign tile_out_or_link__recv_fu__val[1] = fu_crossbar__send_data__val[1]; - assign tile_out_or_link__recv_xbar__msg[1] = routing_crossbar__send_data__msg[1]; - assign routing_crossbar__send_data__rdy[1] = tile_out_or_link__recv_xbar__rdy[1]; - assign tile_out_or_link__recv_xbar__val[1] = routing_crossbar__send_data__val[1]; - assign send_data__msg[1] = tile_out_or_link__send__msg[1]; - assign tile_out_or_link__send__rdy[1] = send_data__rdy[1]; - assign send_data__val[1] = tile_out_or_link__send__val[1]; - assign tile_out_or_link__recv_fu__msg[2] = fu_crossbar__send_data__msg[2]; - assign fu_crossbar__send_data__rdy[2] = tile_out_or_link__recv_fu__rdy[2]; - assign tile_out_or_link__recv_fu__val[2] = fu_crossbar__send_data__val[2]; - assign tile_out_or_link__recv_xbar__msg[2] = routing_crossbar__send_data__msg[2]; - assign routing_crossbar__send_data__rdy[2] = tile_out_or_link__recv_xbar__rdy[2]; - assign tile_out_or_link__recv_xbar__val[2] = routing_crossbar__send_data__val[2]; - assign send_data__msg[2] = tile_out_or_link__send__msg[2]; - assign tile_out_or_link__send__rdy[2] = send_data__rdy[2]; - assign send_data__val[2] = tile_out_or_link__send__val[2]; - assign tile_out_or_link__recv_fu__msg[3] = fu_crossbar__send_data__msg[3]; - assign fu_crossbar__send_data__rdy[3] = tile_out_or_link__recv_fu__rdy[3]; - assign tile_out_or_link__recv_fu__val[3] = fu_crossbar__send_data__val[3]; - assign tile_out_or_link__recv_xbar__msg[3] = routing_crossbar__send_data__msg[3]; - assign routing_crossbar__send_data__rdy[3] = tile_out_or_link__recv_xbar__rdy[3]; - assign tile_out_or_link__recv_xbar__val[3] = routing_crossbar__send_data__val[3]; - assign send_data__msg[3] = tile_out_or_link__send__msg[3]; - assign tile_out_or_link__send__rdy[3] = send_data__rdy[3]; - assign send_data__val[3] = tile_out_or_link__send__val[3]; - assign register_cluster__recv_data_from_routing_crossbar__msg[0] = routing_crossbar__send_data__msg[4]; - assign routing_crossbar__send_data__rdy[4] = register_cluster__recv_data_from_routing_crossbar__rdy[0]; - assign register_cluster__recv_data_from_routing_crossbar__val[0] = routing_crossbar__send_data__val[4]; - assign register_cluster__recv_data_from_fu_crossbar__msg[0] = fu_crossbar__send_data__msg[4]; - assign fu_crossbar__send_data__rdy[4] = register_cluster__recv_data_from_fu_crossbar__rdy[0]; - assign register_cluster__recv_data_from_fu_crossbar__val[0] = fu_crossbar__send_data__val[4]; - assign register_cluster__recv_data_from_const__msg[0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign register_cluster__recv_data_from_const__val[0] = 1'd0; - assign element__recv_in__msg[0] = register_cluster__send_data_to_fu__msg[0]; - assign register_cluster__send_data_to_fu__rdy[0] = element__recv_in__rdy[0]; - assign element__recv_in__val[0] = register_cluster__send_data_to_fu__val[0]; - assign register_cluster__inport_opt = ctrl_mem__send_ctrl__msg; - assign register_cluster__recv_data_from_routing_crossbar__msg[1] = routing_crossbar__send_data__msg[5]; - assign routing_crossbar__send_data__rdy[5] = register_cluster__recv_data_from_routing_crossbar__rdy[1]; - assign register_cluster__recv_data_from_routing_crossbar__val[1] = routing_crossbar__send_data__val[5]; - assign register_cluster__recv_data_from_fu_crossbar__msg[1] = fu_crossbar__send_data__msg[5]; - assign fu_crossbar__send_data__rdy[5] = register_cluster__recv_data_from_fu_crossbar__rdy[1]; - assign register_cluster__recv_data_from_fu_crossbar__val[1] = fu_crossbar__send_data__val[5]; - assign register_cluster__recv_data_from_const__msg[1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign register_cluster__recv_data_from_const__val[1] = 1'd0; - assign element__recv_in__msg[1] = register_cluster__send_data_to_fu__msg[1]; - assign register_cluster__send_data_to_fu__rdy[1] = element__recv_in__rdy[1]; - assign element__recv_in__val[1] = register_cluster__send_data_to_fu__val[1]; - assign register_cluster__recv_data_from_routing_crossbar__msg[2] = routing_crossbar__send_data__msg[6]; - assign routing_crossbar__send_data__rdy[6] = register_cluster__recv_data_from_routing_crossbar__rdy[2]; - assign register_cluster__recv_data_from_routing_crossbar__val[2] = routing_crossbar__send_data__val[6]; - assign register_cluster__recv_data_from_fu_crossbar__msg[2] = fu_crossbar__send_data__msg[6]; - assign fu_crossbar__send_data__rdy[6] = register_cluster__recv_data_from_fu_crossbar__rdy[2]; - assign register_cluster__recv_data_from_fu_crossbar__val[2] = fu_crossbar__send_data__val[6]; - assign register_cluster__recv_data_from_const__msg[2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign register_cluster__recv_data_from_const__val[2] = 1'd0; - assign element__recv_in__msg[2] = register_cluster__send_data_to_fu__msg[2]; - assign register_cluster__send_data_to_fu__rdy[2] = element__recv_in__rdy[2]; - assign element__recv_in__val[2] = register_cluster__send_data_to_fu__val[2]; - assign register_cluster__recv_data_from_routing_crossbar__msg[3] = routing_crossbar__send_data__msg[7]; - assign routing_crossbar__send_data__rdy[7] = register_cluster__recv_data_from_routing_crossbar__rdy[3]; - assign register_cluster__recv_data_from_routing_crossbar__val[3] = routing_crossbar__send_data__val[7]; - assign register_cluster__recv_data_from_fu_crossbar__msg[3] = fu_crossbar__send_data__msg[7]; - assign fu_crossbar__send_data__rdy[7] = register_cluster__recv_data_from_fu_crossbar__rdy[3]; - assign register_cluster__recv_data_from_fu_crossbar__val[3] = fu_crossbar__send_data__val[7]; - assign register_cluster__recv_data_from_const__msg[3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign register_cluster__recv_data_from_const__val[3] = 1'd0; - assign element__recv_in__msg[3] = register_cluster__send_data_to_fu__msg[3]; - assign register_cluster__send_data_to_fu__rdy[3] = element__recv_in__rdy[3]; - assign element__recv_in__val[3] = register_cluster__send_data_to_fu__val[3]; - assign element__clear[0] = 1'd0; - assign element__clear[1] = 1'd0; - assign element__clear[2] = 1'd0; - assign element__clear[3] = 1'd0; - assign element__clear[4] = 1'd0; - assign element__clear[5] = 1'd0; - assign element__clear[6] = 1'd0; - assign element__clear[7] = 1'd0; - assign element__clear[8] = 1'd0; - assign element__clear[9] = 1'd0; - assign element__clear[10] = 1'd0; - assign element__clear[11] = 1'd0; - assign element__clear[12] = 1'd0; - assign element__clear[13] = 1'd0; - assign element__clear[14] = 1'd0; - assign fu_crossbar__clear = 1'd0; - assign routing_crossbar__clear = 1'd0; - -endmodule - - -// PyMTL Component CgraRTL Definition -// Full name: CgraRTL__CgraPayloadType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__multi_cgra_rows_2__multi_cgra_columns_2__width_4__height_4__ctrl_mem_size_16__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_registers_per_reg_bank_16__num_ctrl_4__total_steps_38__mem_access_is_combinational_True__FunctionUnit_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ]__cgra_topology_Mesh__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)}__is_multi_cgra_True__has_ctrl_ring_True -// At /home/ajokai/cgra/VectorCGRAfork0/cgra/CgraRTL.py - -module CgraRTL__72d915b46abe89cb -( - input logic [6:0] address_lower , - input logic [6:0] address_upper , - input logic [1:0] cgra_id , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_east__msg [0:3] , - output logic [0:0] recv_data_on_boundary_east__rdy [0:3] , - input logic [0:0] recv_data_on_boundary_east__val [0:3] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_north__msg [0:3] , - output logic [0:0] recv_data_on_boundary_north__rdy [0:3] , - input logic [0:0] recv_data_on_boundary_north__val [0:3] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_south__msg [0:3] , - output logic [0:0] recv_data_on_boundary_south__rdy [0:3] , - input logic [0:0] recv_data_on_boundary_south__val [0:3] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_west__msg [0:3] , - output logic [0:0] recv_data_on_boundary_west__rdy [0:3] , - input logic [0:0] recv_data_on_boundary_west__val [0:3] , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , - output logic [0:0] recv_from_cpu_pkt__rdy , - input logic [0:0] recv_from_cpu_pkt__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_inter_cgra_noc__msg , - output logic [0:0] recv_from_inter_cgra_noc__rdy , - input logic [0:0] recv_from_inter_cgra_noc__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_east__msg [0:3] , - input logic [0:0] send_data_on_boundary_east__rdy [0:3] , - output logic [0:0] send_data_on_boundary_east__val [0:3] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_north__msg [0:3] , - input logic [0:0] send_data_on_boundary_north__rdy [0:3] , - output logic [0:0] send_data_on_boundary_north__val [0:3] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_south__msg [0:3] , - input logic [0:0] send_data_on_boundary_south__rdy [0:3] , - output logic [0:0] send_data_on_boundary_south__val [0:3] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_west__msg [0:3] , - input logic [0:0] send_data_on_boundary_west__rdy [0:3] , - output logic [0:0] send_data_on_boundary_west__val [0:3] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , - input logic [0:0] send_to_cpu_pkt__rdy , - output logic [0:0] send_to_cpu_pkt__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_inter_cgra_noc__msg , - input logic [0:0] send_to_inter_cgra_noc__rdy , - output logic [0:0] send_to_inter_cgra_noc__val -); - //------------------------------------------------------------- - // Component controller - //------------------------------------------------------------- - - logic [1:0] controller__cgra_id; - logic [0:0] controller__clk; - logic [0:0] controller__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__recv_from_cpu_pkt__msg; - logic [0:0] controller__recv_from_cpu_pkt__rdy; - logic [0:0] controller__recv_from_cpu_pkt__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__recv_from_ctrl_ring_pkt__msg; - logic [0:0] controller__recv_from_ctrl_ring_pkt__rdy; - logic [0:0] controller__recv_from_ctrl_ring_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_inter_cgra_noc__msg; - logic [0:0] controller__recv_from_inter_cgra_noc__rdy; - logic [0:0] controller__recv_from_inter_cgra_noc__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_load_request_pkt__msg; - logic [0:0] controller__recv_from_tile_load_request_pkt__rdy; - logic [0:0] controller__recv_from_tile_load_request_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_load_response_pkt__msg; - logic [0:0] controller__recv_from_tile_load_response_pkt__rdy; - logic [0:0] controller__recv_from_tile_load_response_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_store_request_pkt__msg; - logic [0:0] controller__recv_from_tile_store_request_pkt__rdy; - logic [0:0] controller__recv_from_tile_store_request_pkt__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__send_to_cpu_pkt__msg; - logic [0:0] controller__send_to_cpu_pkt__rdy; - logic [0:0] controller__send_to_cpu_pkt__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__send_to_ctrl_ring_pkt__msg; - logic [0:0] controller__send_to_ctrl_ring_pkt__rdy; - logic [0:0] controller__send_to_ctrl_ring_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_inter_cgra_noc__msg; - logic [0:0] controller__send_to_inter_cgra_noc__rdy; - logic [0:0] controller__send_to_inter_cgra_noc__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_mem_load_request__msg; - logic [0:0] controller__send_to_mem_load_request__rdy; - logic [0:0] controller__send_to_mem_load_request__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_mem_store_request__msg; - logic [0:0] controller__send_to_mem_store_request__rdy; - logic [0:0] controller__send_to_mem_store_request__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_tile_load_response__msg; - logic [0:0] controller__send_to_tile_load_response__rdy; - logic [0:0] controller__send_to_tile_load_response__val; - - ControllerRTL__e06602ce343fdc8d controller - ( - .cgra_id( controller__cgra_id ), - .clk( controller__clk ), - .reset( controller__reset ), - .recv_from_cpu_pkt__msg( controller__recv_from_cpu_pkt__msg ), - .recv_from_cpu_pkt__rdy( controller__recv_from_cpu_pkt__rdy ), - .recv_from_cpu_pkt__val( controller__recv_from_cpu_pkt__val ), - .recv_from_ctrl_ring_pkt__msg( controller__recv_from_ctrl_ring_pkt__msg ), - .recv_from_ctrl_ring_pkt__rdy( controller__recv_from_ctrl_ring_pkt__rdy ), - .recv_from_ctrl_ring_pkt__val( controller__recv_from_ctrl_ring_pkt__val ), - .recv_from_inter_cgra_noc__msg( controller__recv_from_inter_cgra_noc__msg ), - .recv_from_inter_cgra_noc__rdy( controller__recv_from_inter_cgra_noc__rdy ), - .recv_from_inter_cgra_noc__val( controller__recv_from_inter_cgra_noc__val ), - .recv_from_tile_load_request_pkt__msg( controller__recv_from_tile_load_request_pkt__msg ), - .recv_from_tile_load_request_pkt__rdy( controller__recv_from_tile_load_request_pkt__rdy ), - .recv_from_tile_load_request_pkt__val( controller__recv_from_tile_load_request_pkt__val ), - .recv_from_tile_load_response_pkt__msg( controller__recv_from_tile_load_response_pkt__msg ), - .recv_from_tile_load_response_pkt__rdy( controller__recv_from_tile_load_response_pkt__rdy ), - .recv_from_tile_load_response_pkt__val( controller__recv_from_tile_load_response_pkt__val ), - .recv_from_tile_store_request_pkt__msg( controller__recv_from_tile_store_request_pkt__msg ), - .recv_from_tile_store_request_pkt__rdy( controller__recv_from_tile_store_request_pkt__rdy ), - .recv_from_tile_store_request_pkt__val( controller__recv_from_tile_store_request_pkt__val ), - .send_to_cpu_pkt__msg( controller__send_to_cpu_pkt__msg ), - .send_to_cpu_pkt__rdy( controller__send_to_cpu_pkt__rdy ), - .send_to_cpu_pkt__val( controller__send_to_cpu_pkt__val ), - .send_to_ctrl_ring_pkt__msg( controller__send_to_ctrl_ring_pkt__msg ), - .send_to_ctrl_ring_pkt__rdy( controller__send_to_ctrl_ring_pkt__rdy ), - .send_to_ctrl_ring_pkt__val( controller__send_to_ctrl_ring_pkt__val ), - .send_to_inter_cgra_noc__msg( controller__send_to_inter_cgra_noc__msg ), - .send_to_inter_cgra_noc__rdy( controller__send_to_inter_cgra_noc__rdy ), - .send_to_inter_cgra_noc__val( controller__send_to_inter_cgra_noc__val ), - .send_to_mem_load_request__msg( controller__send_to_mem_load_request__msg ), - .send_to_mem_load_request__rdy( controller__send_to_mem_load_request__rdy ), - .send_to_mem_load_request__val( controller__send_to_mem_load_request__val ), - .send_to_mem_store_request__msg( controller__send_to_mem_store_request__msg ), - .send_to_mem_store_request__rdy( controller__send_to_mem_store_request__rdy ), - .send_to_mem_store_request__val( controller__send_to_mem_store_request__val ), - .send_to_tile_load_response__msg( controller__send_to_tile_load_response__msg ), - .send_to_tile_load_response__rdy( controller__send_to_tile_load_response__rdy ), - .send_to_tile_load_response__val( controller__send_to_tile_load_response__val ) - ); - - //------------------------------------------------------------- - // End of component controller - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component ctrl_ring - //------------------------------------------------------------- - - logic [0:0] ctrl_ring__clk; - logic [0:0] ctrl_ring__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_ring__recv__msg [0:16]; - logic [0:0] ctrl_ring__recv__rdy [0:16]; - logic [0:0] ctrl_ring__recv__val [0:16]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_ring__send__msg [0:16]; - logic [0:0] ctrl_ring__send__rdy [0:16]; - logic [0:0] ctrl_ring__send__val [0:16]; - - RingNetworkRTL__8866f4e00dbc912a ctrl_ring - ( - .clk( ctrl_ring__clk ), - .reset( ctrl_ring__reset ), - .recv__msg( ctrl_ring__recv__msg ), - .recv__rdy( ctrl_ring__recv__rdy ), - .recv__val( ctrl_ring__recv__val ), - .send__msg( ctrl_ring__send__msg ), - .send__rdy( ctrl_ring__send__rdy ), - .send__val( ctrl_ring__send__val ) - ); - - //------------------------------------------------------------- - // End of component ctrl_ring - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component data_mem - //------------------------------------------------------------- - - logic [6:0] data_mem__address_lower; - logic [6:0] data_mem__address_upper; - logic [1:0] data_mem__cgra_id; - logic [0:0] data_mem__clk; - logic [0:0] data_mem__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_load_request__msg; - logic [0:0] data_mem__recv_from_noc_load_request__rdy; - logic [0:0] data_mem__recv_from_noc_load_request__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_load_response_pkt__msg; - logic [0:0] data_mem__recv_from_noc_load_response_pkt__rdy; - logic [0:0] data_mem__recv_from_noc_load_response_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_store_request__msg; - logic [0:0] data_mem__recv_from_noc_store_request__rdy; - logic [0:0] data_mem__recv_from_noc_store_request__val; - logic [6:0] data_mem__recv_raddr__msg [0:6]; - logic [0:0] data_mem__recv_raddr__rdy [0:6]; - logic [0:0] data_mem__recv_raddr__val [0:6]; - logic [6:0] data_mem__recv_waddr__msg [0:6]; - logic [0:0] data_mem__recv_waddr__rdy [0:6]; - logic [0:0] data_mem__recv_waddr__val [0:6]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data_mem__recv_wdata__msg [0:6]; - logic [0:0] data_mem__recv_wdata__rdy [0:6]; - logic [0:0] data_mem__recv_wdata__val [0:6]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data_mem__send_rdata__msg [0:6]; - logic [0:0] data_mem__send_rdata__rdy [0:6]; - logic [0:0] data_mem__send_rdata__val [0:6]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_load_request_pkt__msg; - logic [0:0] data_mem__send_to_noc_load_request_pkt__rdy; - logic [0:0] data_mem__send_to_noc_load_request_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_load_response_pkt__msg; - logic [0:0] data_mem__send_to_noc_load_response_pkt__rdy; - logic [0:0] data_mem__send_to_noc_load_response_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_store_pkt__msg; - logic [0:0] data_mem__send_to_noc_store_pkt__rdy; - logic [0:0] data_mem__send_to_noc_store_pkt__val; - - DataMemControllerRTL__20df9b544ed809f0 data_mem - ( - .address_lower( data_mem__address_lower ), - .address_upper( data_mem__address_upper ), - .cgra_id( data_mem__cgra_id ), - .clk( data_mem__clk ), - .reset( data_mem__reset ), - .recv_from_noc_load_request__msg( data_mem__recv_from_noc_load_request__msg ), - .recv_from_noc_load_request__rdy( data_mem__recv_from_noc_load_request__rdy ), - .recv_from_noc_load_request__val( data_mem__recv_from_noc_load_request__val ), - .recv_from_noc_load_response_pkt__msg( data_mem__recv_from_noc_load_response_pkt__msg ), - .recv_from_noc_load_response_pkt__rdy( data_mem__recv_from_noc_load_response_pkt__rdy ), - .recv_from_noc_load_response_pkt__val( data_mem__recv_from_noc_load_response_pkt__val ), - .recv_from_noc_store_request__msg( data_mem__recv_from_noc_store_request__msg ), - .recv_from_noc_store_request__rdy( data_mem__recv_from_noc_store_request__rdy ), - .recv_from_noc_store_request__val( data_mem__recv_from_noc_store_request__val ), - .recv_raddr__msg( data_mem__recv_raddr__msg ), - .recv_raddr__rdy( data_mem__recv_raddr__rdy ), - .recv_raddr__val( data_mem__recv_raddr__val ), - .recv_waddr__msg( data_mem__recv_waddr__msg ), - .recv_waddr__rdy( data_mem__recv_waddr__rdy ), - .recv_waddr__val( data_mem__recv_waddr__val ), - .recv_wdata__msg( data_mem__recv_wdata__msg ), - .recv_wdata__rdy( data_mem__recv_wdata__rdy ), - .recv_wdata__val( data_mem__recv_wdata__val ), - .send_rdata__msg( data_mem__send_rdata__msg ), - .send_rdata__rdy( data_mem__send_rdata__rdy ), - .send_rdata__val( data_mem__send_rdata__val ), - .send_to_noc_load_request_pkt__msg( data_mem__send_to_noc_load_request_pkt__msg ), - .send_to_noc_load_request_pkt__rdy( data_mem__send_to_noc_load_request_pkt__rdy ), - .send_to_noc_load_request_pkt__val( data_mem__send_to_noc_load_request_pkt__val ), - .send_to_noc_load_response_pkt__msg( data_mem__send_to_noc_load_response_pkt__msg ), - .send_to_noc_load_response_pkt__rdy( data_mem__send_to_noc_load_response_pkt__rdy ), - .send_to_noc_load_response_pkt__val( data_mem__send_to_noc_load_response_pkt__val ), - .send_to_noc_store_pkt__msg( data_mem__send_to_noc_store_pkt__msg ), - .send_to_noc_store_pkt__rdy( data_mem__send_to_noc_store_pkt__rdy ), - .send_to_noc_store_pkt__val( data_mem__send_to_noc_store_pkt__val ) - ); - - //------------------------------------------------------------- - // End of component data_mem - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component tile[0:15] - //------------------------------------------------------------- - - logic [1:0] tile__cgra_id [0:15]; - logic [0:0] tile__clk [0:15]; - logic [0:0] tile__reset [0:15]; - logic [4:0] tile__tile_id [0:15]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__from_mem_rdata__msg [0:15]; - logic [0:0] tile__from_mem_rdata__rdy [0:15]; - logic [0:0] tile__from_mem_rdata__val [0:15]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__recv_data__msg [0:15][0:3]; - logic [0:0] tile__recv_data__rdy [0:15][0:3]; - logic [0:0] tile__recv_data__val [0:15][0:3]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 tile__recv_from_controller_pkt__msg [0:15]; - logic [0:0] tile__recv_from_controller_pkt__rdy [0:15]; - logic [0:0] tile__recv_from_controller_pkt__val [0:15]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__send_data__msg [0:15][0:3]; - logic [0:0] tile__send_data__rdy [0:15][0:3]; - logic [0:0] tile__send_data__val [0:15][0:3]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 tile__send_to_controller_pkt__msg [0:15]; - logic [0:0] tile__send_to_controller_pkt__rdy [0:15]; - logic [0:0] tile__send_to_controller_pkt__val [0:15]; - logic [6:0] tile__to_mem_raddr__msg [0:15]; - logic [0:0] tile__to_mem_raddr__rdy [0:15]; - logic [0:0] tile__to_mem_raddr__val [0:15]; - logic [6:0] tile__to_mem_waddr__msg [0:15]; - logic [0:0] tile__to_mem_waddr__rdy [0:15]; - logic [0:0] tile__to_mem_waddr__val [0:15]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__to_mem_wdata__msg [0:15]; - logic [0:0] tile__to_mem_wdata__rdy [0:15]; - logic [0:0] tile__to_mem_wdata__val [0:15]; - - TileRTL__78da5e3970e1cd1d tile__0 - ( - .cgra_id( tile__cgra_id[0] ), - .clk( tile__clk[0] ), - .reset( tile__reset[0] ), - .tile_id( tile__tile_id[0] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[0] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[0] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[0] ), - .recv_data__msg( tile__recv_data__msg[0] ), - .recv_data__rdy( tile__recv_data__rdy[0] ), - .recv_data__val( tile__recv_data__val[0] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[0] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[0] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[0] ), - .send_data__msg( tile__send_data__msg[0] ), - .send_data__rdy( tile__send_data__rdy[0] ), - .send_data__val( tile__send_data__val[0] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[0] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[0] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[0] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[0] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[0] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[0] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[0] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[0] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[0] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[0] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[0] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[0] ) - ); - - TileRTL__78da5e3970e1cd1d tile__1 - ( - .cgra_id( tile__cgra_id[1] ), - .clk( tile__clk[1] ), - .reset( tile__reset[1] ), - .tile_id( tile__tile_id[1] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[1] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[1] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[1] ), - .recv_data__msg( tile__recv_data__msg[1] ), - .recv_data__rdy( tile__recv_data__rdy[1] ), - .recv_data__val( tile__recv_data__val[1] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[1] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[1] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[1] ), - .send_data__msg( tile__send_data__msg[1] ), - .send_data__rdy( tile__send_data__rdy[1] ), - .send_data__val( tile__send_data__val[1] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[1] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[1] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[1] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[1] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[1] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[1] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[1] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[1] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[1] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[1] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[1] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[1] ) - ); - - TileRTL__78da5e3970e1cd1d tile__2 - ( - .cgra_id( tile__cgra_id[2] ), - .clk( tile__clk[2] ), - .reset( tile__reset[2] ), - .tile_id( tile__tile_id[2] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[2] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[2] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[2] ), - .recv_data__msg( tile__recv_data__msg[2] ), - .recv_data__rdy( tile__recv_data__rdy[2] ), - .recv_data__val( tile__recv_data__val[2] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[2] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[2] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[2] ), - .send_data__msg( tile__send_data__msg[2] ), - .send_data__rdy( tile__send_data__rdy[2] ), - .send_data__val( tile__send_data__val[2] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[2] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[2] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[2] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[2] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[2] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[2] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[2] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[2] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[2] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[2] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[2] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[2] ) - ); - - TileRTL__78da5e3970e1cd1d tile__3 - ( - .cgra_id( tile__cgra_id[3] ), - .clk( tile__clk[3] ), - .reset( tile__reset[3] ), - .tile_id( tile__tile_id[3] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[3] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[3] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[3] ), - .recv_data__msg( tile__recv_data__msg[3] ), - .recv_data__rdy( tile__recv_data__rdy[3] ), - .recv_data__val( tile__recv_data__val[3] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[3] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[3] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[3] ), - .send_data__msg( tile__send_data__msg[3] ), - .send_data__rdy( tile__send_data__rdy[3] ), - .send_data__val( tile__send_data__val[3] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[3] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[3] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[3] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[3] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[3] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[3] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[3] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[3] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[3] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[3] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[3] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[3] ) - ); - - TileRTL__78da5e3970e1cd1d tile__4 - ( - .cgra_id( tile__cgra_id[4] ), - .clk( tile__clk[4] ), - .reset( tile__reset[4] ), - .tile_id( tile__tile_id[4] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[4] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[4] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[4] ), - .recv_data__msg( tile__recv_data__msg[4] ), - .recv_data__rdy( tile__recv_data__rdy[4] ), - .recv_data__val( tile__recv_data__val[4] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[4] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[4] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[4] ), - .send_data__msg( tile__send_data__msg[4] ), - .send_data__rdy( tile__send_data__rdy[4] ), - .send_data__val( tile__send_data__val[4] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[4] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[4] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[4] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[4] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[4] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[4] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[4] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[4] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[4] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[4] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[4] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[4] ) - ); - - TileRTL__78da5e3970e1cd1d tile__5 - ( - .cgra_id( tile__cgra_id[5] ), - .clk( tile__clk[5] ), - .reset( tile__reset[5] ), - .tile_id( tile__tile_id[5] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[5] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[5] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[5] ), - .recv_data__msg( tile__recv_data__msg[5] ), - .recv_data__rdy( tile__recv_data__rdy[5] ), - .recv_data__val( tile__recv_data__val[5] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[5] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[5] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[5] ), - .send_data__msg( tile__send_data__msg[5] ), - .send_data__rdy( tile__send_data__rdy[5] ), - .send_data__val( tile__send_data__val[5] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[5] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[5] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[5] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[5] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[5] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[5] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[5] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[5] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[5] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[5] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[5] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[5] ) - ); - - TileRTL__78da5e3970e1cd1d tile__6 - ( - .cgra_id( tile__cgra_id[6] ), - .clk( tile__clk[6] ), - .reset( tile__reset[6] ), - .tile_id( tile__tile_id[6] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[6] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[6] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[6] ), - .recv_data__msg( tile__recv_data__msg[6] ), - .recv_data__rdy( tile__recv_data__rdy[6] ), - .recv_data__val( tile__recv_data__val[6] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[6] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[6] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[6] ), - .send_data__msg( tile__send_data__msg[6] ), - .send_data__rdy( tile__send_data__rdy[6] ), - .send_data__val( tile__send_data__val[6] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[6] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[6] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[6] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[6] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[6] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[6] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[6] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[6] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[6] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[6] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[6] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[6] ) - ); - - TileRTL__78da5e3970e1cd1d tile__7 - ( - .cgra_id( tile__cgra_id[7] ), - .clk( tile__clk[7] ), - .reset( tile__reset[7] ), - .tile_id( tile__tile_id[7] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[7] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[7] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[7] ), - .recv_data__msg( tile__recv_data__msg[7] ), - .recv_data__rdy( tile__recv_data__rdy[7] ), - .recv_data__val( tile__recv_data__val[7] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[7] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[7] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[7] ), - .send_data__msg( tile__send_data__msg[7] ), - .send_data__rdy( tile__send_data__rdy[7] ), - .send_data__val( tile__send_data__val[7] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[7] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[7] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[7] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[7] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[7] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[7] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[7] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[7] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[7] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[7] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[7] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[7] ) - ); - - TileRTL__78da5e3970e1cd1d tile__8 - ( - .cgra_id( tile__cgra_id[8] ), - .clk( tile__clk[8] ), - .reset( tile__reset[8] ), - .tile_id( tile__tile_id[8] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[8] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[8] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[8] ), - .recv_data__msg( tile__recv_data__msg[8] ), - .recv_data__rdy( tile__recv_data__rdy[8] ), - .recv_data__val( tile__recv_data__val[8] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[8] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[8] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[8] ), - .send_data__msg( tile__send_data__msg[8] ), - .send_data__rdy( tile__send_data__rdy[8] ), - .send_data__val( tile__send_data__val[8] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[8] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[8] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[8] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[8] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[8] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[8] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[8] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[8] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[8] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[8] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[8] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[8] ) - ); - - TileRTL__78da5e3970e1cd1d tile__9 - ( - .cgra_id( tile__cgra_id[9] ), - .clk( tile__clk[9] ), - .reset( tile__reset[9] ), - .tile_id( tile__tile_id[9] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[9] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[9] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[9] ), - .recv_data__msg( tile__recv_data__msg[9] ), - .recv_data__rdy( tile__recv_data__rdy[9] ), - .recv_data__val( tile__recv_data__val[9] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[9] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[9] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[9] ), - .send_data__msg( tile__send_data__msg[9] ), - .send_data__rdy( tile__send_data__rdy[9] ), - .send_data__val( tile__send_data__val[9] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[9] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[9] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[9] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[9] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[9] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[9] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[9] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[9] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[9] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[9] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[9] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[9] ) - ); - - TileRTL__78da5e3970e1cd1d tile__10 - ( - .cgra_id( tile__cgra_id[10] ), - .clk( tile__clk[10] ), - .reset( tile__reset[10] ), - .tile_id( tile__tile_id[10] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[10] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[10] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[10] ), - .recv_data__msg( tile__recv_data__msg[10] ), - .recv_data__rdy( tile__recv_data__rdy[10] ), - .recv_data__val( tile__recv_data__val[10] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[10] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[10] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[10] ), - .send_data__msg( tile__send_data__msg[10] ), - .send_data__rdy( tile__send_data__rdy[10] ), - .send_data__val( tile__send_data__val[10] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[10] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[10] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[10] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[10] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[10] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[10] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[10] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[10] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[10] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[10] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[10] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[10] ) - ); - - TileRTL__78da5e3970e1cd1d tile__11 - ( - .cgra_id( tile__cgra_id[11] ), - .clk( tile__clk[11] ), - .reset( tile__reset[11] ), - .tile_id( tile__tile_id[11] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[11] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[11] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[11] ), - .recv_data__msg( tile__recv_data__msg[11] ), - .recv_data__rdy( tile__recv_data__rdy[11] ), - .recv_data__val( tile__recv_data__val[11] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[11] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[11] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[11] ), - .send_data__msg( tile__send_data__msg[11] ), - .send_data__rdy( tile__send_data__rdy[11] ), - .send_data__val( tile__send_data__val[11] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[11] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[11] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[11] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[11] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[11] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[11] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[11] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[11] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[11] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[11] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[11] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[11] ) - ); - - TileRTL__78da5e3970e1cd1d tile__12 - ( - .cgra_id( tile__cgra_id[12] ), - .clk( tile__clk[12] ), - .reset( tile__reset[12] ), - .tile_id( tile__tile_id[12] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[12] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[12] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[12] ), - .recv_data__msg( tile__recv_data__msg[12] ), - .recv_data__rdy( tile__recv_data__rdy[12] ), - .recv_data__val( tile__recv_data__val[12] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[12] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[12] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[12] ), - .send_data__msg( tile__send_data__msg[12] ), - .send_data__rdy( tile__send_data__rdy[12] ), - .send_data__val( tile__send_data__val[12] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[12] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[12] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[12] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[12] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[12] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[12] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[12] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[12] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[12] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[12] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[12] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[12] ) - ); - - TileRTL__78da5e3970e1cd1d tile__13 - ( - .cgra_id( tile__cgra_id[13] ), - .clk( tile__clk[13] ), - .reset( tile__reset[13] ), - .tile_id( tile__tile_id[13] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[13] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[13] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[13] ), - .recv_data__msg( tile__recv_data__msg[13] ), - .recv_data__rdy( tile__recv_data__rdy[13] ), - .recv_data__val( tile__recv_data__val[13] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[13] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[13] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[13] ), - .send_data__msg( tile__send_data__msg[13] ), - .send_data__rdy( tile__send_data__rdy[13] ), - .send_data__val( tile__send_data__val[13] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[13] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[13] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[13] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[13] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[13] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[13] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[13] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[13] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[13] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[13] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[13] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[13] ) - ); - - TileRTL__78da5e3970e1cd1d tile__14 - ( - .cgra_id( tile__cgra_id[14] ), - .clk( tile__clk[14] ), - .reset( tile__reset[14] ), - .tile_id( tile__tile_id[14] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[14] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[14] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[14] ), - .recv_data__msg( tile__recv_data__msg[14] ), - .recv_data__rdy( tile__recv_data__rdy[14] ), - .recv_data__val( tile__recv_data__val[14] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[14] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[14] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[14] ), - .send_data__msg( tile__send_data__msg[14] ), - .send_data__rdy( tile__send_data__rdy[14] ), - .send_data__val( tile__send_data__val[14] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[14] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[14] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[14] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[14] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[14] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[14] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[14] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[14] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[14] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[14] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[14] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[14] ) - ); - - TileRTL__78da5e3970e1cd1d tile__15 - ( - .cgra_id( tile__cgra_id[15] ), - .clk( tile__clk[15] ), - .reset( tile__reset[15] ), - .tile_id( tile__tile_id[15] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[15] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[15] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[15] ), - .recv_data__msg( tile__recv_data__msg[15] ), - .recv_data__rdy( tile__recv_data__rdy[15] ), - .recv_data__val( tile__recv_data__val[15] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[15] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[15] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[15] ), - .send_data__msg( tile__send_data__msg[15] ), - .send_data__rdy( tile__send_data__rdy[15] ), - .send_data__val( tile__send_data__val[15] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[15] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[15] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[15] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[15] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[15] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[15] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[15] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[15] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[15] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[15] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[15] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[15] ) - ); - - //------------------------------------------------------------- - // End of component tile[0:15] - //------------------------------------------------------------- - - assign tile__clk[0] = clk; - assign tile__reset[0] = reset; - assign tile__clk[1] = clk; - assign tile__reset[1] = reset; - assign tile__clk[2] = clk; - assign tile__reset[2] = reset; - assign tile__clk[3] = clk; - assign tile__reset[3] = reset; - assign tile__clk[4] = clk; - assign tile__reset[4] = reset; - assign tile__clk[5] = clk; - assign tile__reset[5] = reset; - assign tile__clk[6] = clk; - assign tile__reset[6] = reset; - assign tile__clk[7] = clk; - assign tile__reset[7] = reset; - assign tile__clk[8] = clk; - assign tile__reset[8] = reset; - assign tile__clk[9] = clk; - assign tile__reset[9] = reset; - assign tile__clk[10] = clk; - assign tile__reset[10] = reset; - assign tile__clk[11] = clk; - assign tile__reset[11] = reset; - assign tile__clk[12] = clk; - assign tile__reset[12] = reset; - assign tile__clk[13] = clk; - assign tile__reset[13] = reset; - assign tile__clk[14] = clk; - assign tile__reset[14] = reset; - assign tile__clk[15] = clk; - assign tile__reset[15] = reset; - assign data_mem__clk = clk; - assign data_mem__reset = reset; - assign controller__clk = clk; - assign controller__reset = reset; - assign ctrl_ring__clk = clk; - assign ctrl_ring__reset = reset; - assign controller__cgra_id = cgra_id; - assign data_mem__cgra_id = cgra_id; - assign data_mem__address_lower = address_lower; - assign data_mem__address_upper = address_upper; - assign data_mem__recv_from_noc_load_request__msg = controller__send_to_mem_load_request__msg; - assign controller__send_to_mem_load_request__rdy = data_mem__recv_from_noc_load_request__rdy; - assign data_mem__recv_from_noc_load_request__val = controller__send_to_mem_load_request__val; - assign data_mem__recv_from_noc_store_request__msg = controller__send_to_mem_store_request__msg; - assign controller__send_to_mem_store_request__rdy = data_mem__recv_from_noc_store_request__rdy; - assign data_mem__recv_from_noc_store_request__val = controller__send_to_mem_store_request__val; - assign data_mem__recv_from_noc_load_response_pkt__msg = controller__send_to_tile_load_response__msg; - assign controller__send_to_tile_load_response__rdy = data_mem__recv_from_noc_load_response_pkt__rdy; - assign data_mem__recv_from_noc_load_response_pkt__val = controller__send_to_tile_load_response__val; - assign controller__recv_from_tile_load_request_pkt__msg = data_mem__send_to_noc_load_request_pkt__msg; - assign data_mem__send_to_noc_load_request_pkt__rdy = controller__recv_from_tile_load_request_pkt__rdy; - assign controller__recv_from_tile_load_request_pkt__val = data_mem__send_to_noc_load_request_pkt__val; - assign controller__recv_from_tile_load_response_pkt__msg = data_mem__send_to_noc_load_response_pkt__msg; - assign data_mem__send_to_noc_load_response_pkt__rdy = controller__recv_from_tile_load_response_pkt__rdy; - assign controller__recv_from_tile_load_response_pkt__val = data_mem__send_to_noc_load_response_pkt__val; - assign controller__recv_from_tile_store_request_pkt__msg = data_mem__send_to_noc_store_pkt__msg; - assign data_mem__send_to_noc_store_pkt__rdy = controller__recv_from_tile_store_request_pkt__rdy; - assign controller__recv_from_tile_store_request_pkt__val = data_mem__send_to_noc_store_pkt__val; - assign controller__recv_from_inter_cgra_noc__msg = recv_from_inter_cgra_noc__msg; - assign recv_from_inter_cgra_noc__rdy = controller__recv_from_inter_cgra_noc__rdy; - assign controller__recv_from_inter_cgra_noc__val = recv_from_inter_cgra_noc__val; - assign send_to_inter_cgra_noc__msg = controller__send_to_inter_cgra_noc__msg; - assign controller__send_to_inter_cgra_noc__rdy = send_to_inter_cgra_noc__rdy; - assign send_to_inter_cgra_noc__val = controller__send_to_inter_cgra_noc__val; - assign controller__recv_from_cpu_pkt__msg = recv_from_cpu_pkt__msg; - assign recv_from_cpu_pkt__rdy = controller__recv_from_cpu_pkt__rdy; - assign controller__recv_from_cpu_pkt__val = recv_from_cpu_pkt__val; - assign send_to_cpu_pkt__msg = controller__send_to_cpu_pkt__msg; - assign controller__send_to_cpu_pkt__rdy = send_to_cpu_pkt__rdy; - assign send_to_cpu_pkt__val = controller__send_to_cpu_pkt__val; - assign tile__tile_id[0] = 5'd0; - assign tile__cgra_id[0] = cgra_id; - assign tile__tile_id[1] = 5'd1; - assign tile__cgra_id[1] = cgra_id; - assign tile__tile_id[2] = 5'd2; - assign tile__cgra_id[2] = cgra_id; - assign tile__tile_id[3] = 5'd3; - assign tile__cgra_id[3] = cgra_id; - assign tile__tile_id[4] = 5'd4; - assign tile__cgra_id[4] = cgra_id; - assign tile__tile_id[5] = 5'd5; - assign tile__cgra_id[5] = cgra_id; - assign tile__tile_id[6] = 5'd6; - assign tile__cgra_id[6] = cgra_id; - assign tile__tile_id[7] = 5'd7; - assign tile__cgra_id[7] = cgra_id; - assign tile__tile_id[8] = 5'd8; - assign tile__cgra_id[8] = cgra_id; - assign tile__tile_id[9] = 5'd9; - assign tile__cgra_id[9] = cgra_id; - assign tile__tile_id[10] = 5'd10; - assign tile__cgra_id[10] = cgra_id; - assign tile__tile_id[11] = 5'd11; - assign tile__cgra_id[11] = cgra_id; - assign tile__tile_id[12] = 5'd12; - assign tile__cgra_id[12] = cgra_id; - assign tile__tile_id[13] = 5'd13; - assign tile__cgra_id[13] = cgra_id; - assign tile__tile_id[14] = 5'd14; - assign tile__cgra_id[14] = cgra_id; - assign tile__tile_id[15] = 5'd15; - assign tile__cgra_id[15] = cgra_id; - assign tile__recv_from_controller_pkt__msg[0] = ctrl_ring__send__msg[0]; - assign ctrl_ring__send__rdy[0] = tile__recv_from_controller_pkt__rdy[0]; - assign tile__recv_from_controller_pkt__val[0] = ctrl_ring__send__val[0]; - assign ctrl_ring__recv__msg[0] = tile__send_to_controller_pkt__msg[0]; - assign tile__send_to_controller_pkt__rdy[0] = ctrl_ring__recv__rdy[0]; - assign ctrl_ring__recv__val[0] = tile__send_to_controller_pkt__val[0]; - assign tile__recv_from_controller_pkt__msg[1] = ctrl_ring__send__msg[1]; - assign ctrl_ring__send__rdy[1] = tile__recv_from_controller_pkt__rdy[1]; - assign tile__recv_from_controller_pkt__val[1] = ctrl_ring__send__val[1]; - assign ctrl_ring__recv__msg[1] = tile__send_to_controller_pkt__msg[1]; - assign tile__send_to_controller_pkt__rdy[1] = ctrl_ring__recv__rdy[1]; - assign ctrl_ring__recv__val[1] = tile__send_to_controller_pkt__val[1]; - assign tile__recv_from_controller_pkt__msg[2] = ctrl_ring__send__msg[2]; - assign ctrl_ring__send__rdy[2] = tile__recv_from_controller_pkt__rdy[2]; - assign tile__recv_from_controller_pkt__val[2] = ctrl_ring__send__val[2]; - assign ctrl_ring__recv__msg[2] = tile__send_to_controller_pkt__msg[2]; - assign tile__send_to_controller_pkt__rdy[2] = ctrl_ring__recv__rdy[2]; - assign ctrl_ring__recv__val[2] = tile__send_to_controller_pkt__val[2]; - assign tile__recv_from_controller_pkt__msg[3] = ctrl_ring__send__msg[3]; - assign ctrl_ring__send__rdy[3] = tile__recv_from_controller_pkt__rdy[3]; - assign tile__recv_from_controller_pkt__val[3] = ctrl_ring__send__val[3]; - assign ctrl_ring__recv__msg[3] = tile__send_to_controller_pkt__msg[3]; - assign tile__send_to_controller_pkt__rdy[3] = ctrl_ring__recv__rdy[3]; - assign ctrl_ring__recv__val[3] = tile__send_to_controller_pkt__val[3]; - assign tile__recv_from_controller_pkt__msg[4] = ctrl_ring__send__msg[4]; - assign ctrl_ring__send__rdy[4] = tile__recv_from_controller_pkt__rdy[4]; - assign tile__recv_from_controller_pkt__val[4] = ctrl_ring__send__val[4]; - assign ctrl_ring__recv__msg[4] = tile__send_to_controller_pkt__msg[4]; - assign tile__send_to_controller_pkt__rdy[4] = ctrl_ring__recv__rdy[4]; - assign ctrl_ring__recv__val[4] = tile__send_to_controller_pkt__val[4]; - assign tile__recv_from_controller_pkt__msg[5] = ctrl_ring__send__msg[5]; - assign ctrl_ring__send__rdy[5] = tile__recv_from_controller_pkt__rdy[5]; - assign tile__recv_from_controller_pkt__val[5] = ctrl_ring__send__val[5]; - assign ctrl_ring__recv__msg[5] = tile__send_to_controller_pkt__msg[5]; - assign tile__send_to_controller_pkt__rdy[5] = ctrl_ring__recv__rdy[5]; - assign ctrl_ring__recv__val[5] = tile__send_to_controller_pkt__val[5]; - assign tile__recv_from_controller_pkt__msg[6] = ctrl_ring__send__msg[6]; - assign ctrl_ring__send__rdy[6] = tile__recv_from_controller_pkt__rdy[6]; - assign tile__recv_from_controller_pkt__val[6] = ctrl_ring__send__val[6]; - assign ctrl_ring__recv__msg[6] = tile__send_to_controller_pkt__msg[6]; - assign tile__send_to_controller_pkt__rdy[6] = ctrl_ring__recv__rdy[6]; - assign ctrl_ring__recv__val[6] = tile__send_to_controller_pkt__val[6]; - assign tile__recv_from_controller_pkt__msg[7] = ctrl_ring__send__msg[7]; - assign ctrl_ring__send__rdy[7] = tile__recv_from_controller_pkt__rdy[7]; - assign tile__recv_from_controller_pkt__val[7] = ctrl_ring__send__val[7]; - assign ctrl_ring__recv__msg[7] = tile__send_to_controller_pkt__msg[7]; - assign tile__send_to_controller_pkt__rdy[7] = ctrl_ring__recv__rdy[7]; - assign ctrl_ring__recv__val[7] = tile__send_to_controller_pkt__val[7]; - assign tile__recv_from_controller_pkt__msg[8] = ctrl_ring__send__msg[8]; - assign ctrl_ring__send__rdy[8] = tile__recv_from_controller_pkt__rdy[8]; - assign tile__recv_from_controller_pkt__val[8] = ctrl_ring__send__val[8]; - assign ctrl_ring__recv__msg[8] = tile__send_to_controller_pkt__msg[8]; - assign tile__send_to_controller_pkt__rdy[8] = ctrl_ring__recv__rdy[8]; - assign ctrl_ring__recv__val[8] = tile__send_to_controller_pkt__val[8]; - assign tile__recv_from_controller_pkt__msg[9] = ctrl_ring__send__msg[9]; - assign ctrl_ring__send__rdy[9] = tile__recv_from_controller_pkt__rdy[9]; - assign tile__recv_from_controller_pkt__val[9] = ctrl_ring__send__val[9]; - assign ctrl_ring__recv__msg[9] = tile__send_to_controller_pkt__msg[9]; - assign tile__send_to_controller_pkt__rdy[9] = ctrl_ring__recv__rdy[9]; - assign ctrl_ring__recv__val[9] = tile__send_to_controller_pkt__val[9]; - assign tile__recv_from_controller_pkt__msg[10] = ctrl_ring__send__msg[10]; - assign ctrl_ring__send__rdy[10] = tile__recv_from_controller_pkt__rdy[10]; - assign tile__recv_from_controller_pkt__val[10] = ctrl_ring__send__val[10]; - assign ctrl_ring__recv__msg[10] = tile__send_to_controller_pkt__msg[10]; - assign tile__send_to_controller_pkt__rdy[10] = ctrl_ring__recv__rdy[10]; - assign ctrl_ring__recv__val[10] = tile__send_to_controller_pkt__val[10]; - assign tile__recv_from_controller_pkt__msg[11] = ctrl_ring__send__msg[11]; - assign ctrl_ring__send__rdy[11] = tile__recv_from_controller_pkt__rdy[11]; - assign tile__recv_from_controller_pkt__val[11] = ctrl_ring__send__val[11]; - assign ctrl_ring__recv__msg[11] = tile__send_to_controller_pkt__msg[11]; - assign tile__send_to_controller_pkt__rdy[11] = ctrl_ring__recv__rdy[11]; - assign ctrl_ring__recv__val[11] = tile__send_to_controller_pkt__val[11]; - assign tile__recv_from_controller_pkt__msg[12] = ctrl_ring__send__msg[12]; - assign ctrl_ring__send__rdy[12] = tile__recv_from_controller_pkt__rdy[12]; - assign tile__recv_from_controller_pkt__val[12] = ctrl_ring__send__val[12]; - assign ctrl_ring__recv__msg[12] = tile__send_to_controller_pkt__msg[12]; - assign tile__send_to_controller_pkt__rdy[12] = ctrl_ring__recv__rdy[12]; - assign ctrl_ring__recv__val[12] = tile__send_to_controller_pkt__val[12]; - assign tile__recv_from_controller_pkt__msg[13] = ctrl_ring__send__msg[13]; - assign ctrl_ring__send__rdy[13] = tile__recv_from_controller_pkt__rdy[13]; - assign tile__recv_from_controller_pkt__val[13] = ctrl_ring__send__val[13]; - assign ctrl_ring__recv__msg[13] = tile__send_to_controller_pkt__msg[13]; - assign tile__send_to_controller_pkt__rdy[13] = ctrl_ring__recv__rdy[13]; - assign ctrl_ring__recv__val[13] = tile__send_to_controller_pkt__val[13]; - assign tile__recv_from_controller_pkt__msg[14] = ctrl_ring__send__msg[14]; - assign ctrl_ring__send__rdy[14] = tile__recv_from_controller_pkt__rdy[14]; - assign tile__recv_from_controller_pkt__val[14] = ctrl_ring__send__val[14]; - assign ctrl_ring__recv__msg[14] = tile__send_to_controller_pkt__msg[14]; - assign tile__send_to_controller_pkt__rdy[14] = ctrl_ring__recv__rdy[14]; - assign ctrl_ring__recv__val[14] = tile__send_to_controller_pkt__val[14]; - assign tile__recv_from_controller_pkt__msg[15] = ctrl_ring__send__msg[15]; - assign ctrl_ring__send__rdy[15] = tile__recv_from_controller_pkt__rdy[15]; - assign tile__recv_from_controller_pkt__val[15] = ctrl_ring__send__val[15]; - assign ctrl_ring__recv__msg[15] = tile__send_to_controller_pkt__msg[15]; - assign tile__send_to_controller_pkt__rdy[15] = ctrl_ring__recv__rdy[15]; - assign ctrl_ring__recv__val[15] = tile__send_to_controller_pkt__val[15]; - assign ctrl_ring__recv__msg[16] = controller__send_to_ctrl_ring_pkt__msg; - assign controller__send_to_ctrl_ring_pkt__rdy = ctrl_ring__recv__rdy[16]; - assign ctrl_ring__recv__val[16] = controller__send_to_ctrl_ring_pkt__val; - assign controller__recv_from_ctrl_ring_pkt__msg = ctrl_ring__send__msg[16]; - assign ctrl_ring__send__rdy[16] = controller__recv_from_ctrl_ring_pkt__rdy; - assign controller__recv_from_ctrl_ring_pkt__val = ctrl_ring__send__val[16]; - assign tile__recv_data__msg[4][1] = tile__send_data__msg[0][0]; - assign tile__send_data__rdy[0][0] = tile__recv_data__rdy[4][1]; - assign tile__recv_data__val[4][1] = tile__send_data__val[0][0]; - assign tile__recv_data__msg[1][2] = tile__send_data__msg[0][3]; - assign tile__send_data__rdy[0][3] = tile__recv_data__rdy[1][2]; - assign tile__recv_data__val[1][2] = tile__send_data__val[0][3]; - assign send_data_on_boundary_south__msg[0] = tile__send_data__msg[0][1]; - assign tile__send_data__rdy[0][1] = send_data_on_boundary_south__rdy[0]; - assign send_data_on_boundary_south__val[0] = tile__send_data__val[0][1]; - assign tile__recv_data__msg[0][1] = recv_data_on_boundary_south__msg[0]; - assign recv_data_on_boundary_south__rdy[0] = tile__recv_data__rdy[0][1]; - assign tile__recv_data__val[0][1] = recv_data_on_boundary_south__val[0]; - assign send_data_on_boundary_west__msg[0] = tile__send_data__msg[0][2]; - assign tile__send_data__rdy[0][2] = send_data_on_boundary_west__rdy[0]; - assign send_data_on_boundary_west__val[0] = tile__send_data__val[0][2]; - assign tile__recv_data__msg[0][2] = recv_data_on_boundary_west__msg[0]; - assign recv_data_on_boundary_west__rdy[0] = tile__recv_data__rdy[0][2]; - assign tile__recv_data__val[0][2] = recv_data_on_boundary_west__val[0]; - assign data_mem__recv_raddr__msg[0] = tile__to_mem_raddr__msg[0]; - assign tile__to_mem_raddr__rdy[0] = data_mem__recv_raddr__rdy[0]; - assign data_mem__recv_raddr__val[0] = tile__to_mem_raddr__val[0]; - assign tile__from_mem_rdata__msg[0] = data_mem__send_rdata__msg[0]; - assign data_mem__send_rdata__rdy[0] = tile__from_mem_rdata__rdy[0]; - assign tile__from_mem_rdata__val[0] = data_mem__send_rdata__val[0]; - assign data_mem__recv_waddr__msg[0] = tile__to_mem_waddr__msg[0]; - assign tile__to_mem_waddr__rdy[0] = data_mem__recv_waddr__rdy[0]; - assign data_mem__recv_waddr__val[0] = tile__to_mem_waddr__val[0]; - assign data_mem__recv_wdata__msg[0] = tile__to_mem_wdata__msg[0]; - assign tile__to_mem_wdata__rdy[0] = data_mem__recv_wdata__rdy[0]; - assign data_mem__recv_wdata__val[0] = tile__to_mem_wdata__val[0]; - assign tile__recv_data__msg[5][1] = tile__send_data__msg[1][0]; - assign tile__send_data__rdy[1][0] = tile__recv_data__rdy[5][1]; - assign tile__recv_data__val[5][1] = tile__send_data__val[1][0]; - assign tile__recv_data__msg[0][3] = tile__send_data__msg[1][2]; - assign tile__send_data__rdy[1][2] = tile__recv_data__rdy[0][3]; - assign tile__recv_data__val[0][3] = tile__send_data__val[1][2]; - assign tile__recv_data__msg[2][2] = tile__send_data__msg[1][3]; - assign tile__send_data__rdy[1][3] = tile__recv_data__rdy[2][2]; - assign tile__recv_data__val[2][2] = tile__send_data__val[1][3]; - assign send_data_on_boundary_south__msg[1] = tile__send_data__msg[1][1]; - assign tile__send_data__rdy[1][1] = send_data_on_boundary_south__rdy[1]; - assign send_data_on_boundary_south__val[1] = tile__send_data__val[1][1]; - assign tile__recv_data__msg[1][1] = recv_data_on_boundary_south__msg[1]; - assign recv_data_on_boundary_south__rdy[1] = tile__recv_data__rdy[1][1]; - assign tile__recv_data__val[1][1] = recv_data_on_boundary_south__val[1]; - assign data_mem__recv_raddr__msg[1] = tile__to_mem_raddr__msg[1]; - assign tile__to_mem_raddr__rdy[1] = data_mem__recv_raddr__rdy[1]; - assign data_mem__recv_raddr__val[1] = tile__to_mem_raddr__val[1]; - assign tile__from_mem_rdata__msg[1] = data_mem__send_rdata__msg[1]; - assign data_mem__send_rdata__rdy[1] = tile__from_mem_rdata__rdy[1]; - assign tile__from_mem_rdata__val[1] = data_mem__send_rdata__val[1]; - assign data_mem__recv_waddr__msg[1] = tile__to_mem_waddr__msg[1]; - assign tile__to_mem_waddr__rdy[1] = data_mem__recv_waddr__rdy[1]; - assign data_mem__recv_waddr__val[1] = tile__to_mem_waddr__val[1]; - assign data_mem__recv_wdata__msg[1] = tile__to_mem_wdata__msg[1]; - assign tile__to_mem_wdata__rdy[1] = data_mem__recv_wdata__rdy[1]; - assign data_mem__recv_wdata__val[1] = tile__to_mem_wdata__val[1]; - assign tile__recv_data__msg[6][1] = tile__send_data__msg[2][0]; - assign tile__send_data__rdy[2][0] = tile__recv_data__rdy[6][1]; - assign tile__recv_data__val[6][1] = tile__send_data__val[2][0]; - assign tile__recv_data__msg[1][3] = tile__send_data__msg[2][2]; - assign tile__send_data__rdy[2][2] = tile__recv_data__rdy[1][3]; - assign tile__recv_data__val[1][3] = tile__send_data__val[2][2]; - assign tile__recv_data__msg[3][2] = tile__send_data__msg[2][3]; - assign tile__send_data__rdy[2][3] = tile__recv_data__rdy[3][2]; - assign tile__recv_data__val[3][2] = tile__send_data__val[2][3]; - assign send_data_on_boundary_south__msg[2] = tile__send_data__msg[2][1]; - assign tile__send_data__rdy[2][1] = send_data_on_boundary_south__rdy[2]; - assign send_data_on_boundary_south__val[2] = tile__send_data__val[2][1]; - assign tile__recv_data__msg[2][1] = recv_data_on_boundary_south__msg[2]; - assign recv_data_on_boundary_south__rdy[2] = tile__recv_data__rdy[2][1]; - assign tile__recv_data__val[2][1] = recv_data_on_boundary_south__val[2]; - assign data_mem__recv_raddr__msg[2] = tile__to_mem_raddr__msg[2]; - assign tile__to_mem_raddr__rdy[2] = data_mem__recv_raddr__rdy[2]; - assign data_mem__recv_raddr__val[2] = tile__to_mem_raddr__val[2]; - assign tile__from_mem_rdata__msg[2] = data_mem__send_rdata__msg[2]; - assign data_mem__send_rdata__rdy[2] = tile__from_mem_rdata__rdy[2]; - assign tile__from_mem_rdata__val[2] = data_mem__send_rdata__val[2]; - assign data_mem__recv_waddr__msg[2] = tile__to_mem_waddr__msg[2]; - assign tile__to_mem_waddr__rdy[2] = data_mem__recv_waddr__rdy[2]; - assign data_mem__recv_waddr__val[2] = tile__to_mem_waddr__val[2]; - assign data_mem__recv_wdata__msg[2] = tile__to_mem_wdata__msg[2]; - assign tile__to_mem_wdata__rdy[2] = data_mem__recv_wdata__rdy[2]; - assign data_mem__recv_wdata__val[2] = tile__to_mem_wdata__val[2]; - assign tile__recv_data__msg[7][1] = tile__send_data__msg[3][0]; - assign tile__send_data__rdy[3][0] = tile__recv_data__rdy[7][1]; - assign tile__recv_data__val[7][1] = tile__send_data__val[3][0]; - assign tile__recv_data__msg[2][3] = tile__send_data__msg[3][2]; - assign tile__send_data__rdy[3][2] = tile__recv_data__rdy[2][3]; - assign tile__recv_data__val[2][3] = tile__send_data__val[3][2]; - assign send_data_on_boundary_south__msg[3] = tile__send_data__msg[3][1]; - assign tile__send_data__rdy[3][1] = send_data_on_boundary_south__rdy[3]; - assign send_data_on_boundary_south__val[3] = tile__send_data__val[3][1]; - assign tile__recv_data__msg[3][1] = recv_data_on_boundary_south__msg[3]; - assign recv_data_on_boundary_south__rdy[3] = tile__recv_data__rdy[3][1]; - assign tile__recv_data__val[3][1] = recv_data_on_boundary_south__val[3]; - assign send_data_on_boundary_east__msg[0] = tile__send_data__msg[3][3]; - assign tile__send_data__rdy[3][3] = send_data_on_boundary_east__rdy[0]; - assign send_data_on_boundary_east__val[0] = tile__send_data__val[3][3]; - assign tile__recv_data__msg[3][3] = recv_data_on_boundary_east__msg[0]; - assign recv_data_on_boundary_east__rdy[0] = tile__recv_data__rdy[3][3]; - assign tile__recv_data__val[3][3] = recv_data_on_boundary_east__val[0]; - assign data_mem__recv_raddr__msg[3] = tile__to_mem_raddr__msg[3]; - assign tile__to_mem_raddr__rdy[3] = data_mem__recv_raddr__rdy[3]; - assign data_mem__recv_raddr__val[3] = tile__to_mem_raddr__val[3]; - assign tile__from_mem_rdata__msg[3] = data_mem__send_rdata__msg[3]; - assign data_mem__send_rdata__rdy[3] = tile__from_mem_rdata__rdy[3]; - assign tile__from_mem_rdata__val[3] = data_mem__send_rdata__val[3]; - assign data_mem__recv_waddr__msg[3] = tile__to_mem_waddr__msg[3]; - assign tile__to_mem_waddr__rdy[3] = data_mem__recv_waddr__rdy[3]; - assign data_mem__recv_waddr__val[3] = tile__to_mem_waddr__val[3]; - assign data_mem__recv_wdata__msg[3] = tile__to_mem_wdata__msg[3]; - assign tile__to_mem_wdata__rdy[3] = data_mem__recv_wdata__rdy[3]; - assign data_mem__recv_wdata__val[3] = tile__to_mem_wdata__val[3]; - assign tile__recv_data__msg[0][0] = tile__send_data__msg[4][1]; - assign tile__send_data__rdy[4][1] = tile__recv_data__rdy[0][0]; - assign tile__recv_data__val[0][0] = tile__send_data__val[4][1]; - assign tile__recv_data__msg[8][1] = tile__send_data__msg[4][0]; - assign tile__send_data__rdy[4][0] = tile__recv_data__rdy[8][1]; - assign tile__recv_data__val[8][1] = tile__send_data__val[4][0]; - assign tile__recv_data__msg[5][2] = tile__send_data__msg[4][3]; - assign tile__send_data__rdy[4][3] = tile__recv_data__rdy[5][2]; - assign tile__recv_data__val[5][2] = tile__send_data__val[4][3]; - assign send_data_on_boundary_west__msg[1] = tile__send_data__msg[4][2]; - assign tile__send_data__rdy[4][2] = send_data_on_boundary_west__rdy[1]; - assign send_data_on_boundary_west__val[1] = tile__send_data__val[4][2]; - assign tile__recv_data__msg[4][2] = recv_data_on_boundary_west__msg[1]; - assign recv_data_on_boundary_west__rdy[1] = tile__recv_data__rdy[4][2]; - assign tile__recv_data__val[4][2] = recv_data_on_boundary_west__val[1]; - assign data_mem__recv_raddr__msg[4] = tile__to_mem_raddr__msg[4]; - assign tile__to_mem_raddr__rdy[4] = data_mem__recv_raddr__rdy[4]; - assign data_mem__recv_raddr__val[4] = tile__to_mem_raddr__val[4]; - assign tile__from_mem_rdata__msg[4] = data_mem__send_rdata__msg[4]; - assign data_mem__send_rdata__rdy[4] = tile__from_mem_rdata__rdy[4]; - assign tile__from_mem_rdata__val[4] = data_mem__send_rdata__val[4]; - assign data_mem__recv_waddr__msg[4] = tile__to_mem_waddr__msg[4]; - assign tile__to_mem_waddr__rdy[4] = data_mem__recv_waddr__rdy[4]; - assign data_mem__recv_waddr__val[4] = tile__to_mem_waddr__val[4]; - assign data_mem__recv_wdata__msg[4] = tile__to_mem_wdata__msg[4]; - assign tile__to_mem_wdata__rdy[4] = data_mem__recv_wdata__rdy[4]; - assign data_mem__recv_wdata__val[4] = tile__to_mem_wdata__val[4]; - assign tile__recv_data__msg[1][0] = tile__send_data__msg[5][1]; - assign tile__send_data__rdy[5][1] = tile__recv_data__rdy[1][0]; - assign tile__recv_data__val[1][0] = tile__send_data__val[5][1]; - assign tile__recv_data__msg[9][1] = tile__send_data__msg[5][0]; - assign tile__send_data__rdy[5][0] = tile__recv_data__rdy[9][1]; - assign tile__recv_data__val[9][1] = tile__send_data__val[5][0]; - assign tile__recv_data__msg[4][3] = tile__send_data__msg[5][2]; - assign tile__send_data__rdy[5][2] = tile__recv_data__rdy[4][3]; - assign tile__recv_data__val[4][3] = tile__send_data__val[5][2]; - assign tile__recv_data__msg[6][2] = tile__send_data__msg[5][3]; - assign tile__send_data__rdy[5][3] = tile__recv_data__rdy[6][2]; - assign tile__recv_data__val[6][2] = tile__send_data__val[5][3]; - assign tile__to_mem_raddr__rdy[5] = 1'd0; - assign tile__from_mem_rdata__val[5] = 1'd0; - assign tile__from_mem_rdata__msg[5] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[5] = 1'd0; - assign tile__to_mem_wdata__rdy[5] = 1'd0; - assign tile__recv_data__msg[2][0] = tile__send_data__msg[6][1]; - assign tile__send_data__rdy[6][1] = tile__recv_data__rdy[2][0]; - assign tile__recv_data__val[2][0] = tile__send_data__val[6][1]; - assign tile__recv_data__msg[10][1] = tile__send_data__msg[6][0]; - assign tile__send_data__rdy[6][0] = tile__recv_data__rdy[10][1]; - assign tile__recv_data__val[10][1] = tile__send_data__val[6][0]; - assign tile__recv_data__msg[5][3] = tile__send_data__msg[6][2]; - assign tile__send_data__rdy[6][2] = tile__recv_data__rdy[5][3]; - assign tile__recv_data__val[5][3] = tile__send_data__val[6][2]; - assign tile__recv_data__msg[7][2] = tile__send_data__msg[6][3]; - assign tile__send_data__rdy[6][3] = tile__recv_data__rdy[7][2]; - assign tile__recv_data__val[7][2] = tile__send_data__val[6][3]; - assign tile__to_mem_raddr__rdy[6] = 1'd0; - assign tile__from_mem_rdata__val[6] = 1'd0; - assign tile__from_mem_rdata__msg[6] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[6] = 1'd0; - assign tile__to_mem_wdata__rdy[6] = 1'd0; - assign tile__recv_data__msg[3][0] = tile__send_data__msg[7][1]; - assign tile__send_data__rdy[7][1] = tile__recv_data__rdy[3][0]; - assign tile__recv_data__val[3][0] = tile__send_data__val[7][1]; - assign tile__recv_data__msg[11][1] = tile__send_data__msg[7][0]; - assign tile__send_data__rdy[7][0] = tile__recv_data__rdy[11][1]; - assign tile__recv_data__val[11][1] = tile__send_data__val[7][0]; - assign tile__recv_data__msg[6][3] = tile__send_data__msg[7][2]; - assign tile__send_data__rdy[7][2] = tile__recv_data__rdy[6][3]; - assign tile__recv_data__val[6][3] = tile__send_data__val[7][2]; - assign send_data_on_boundary_east__msg[1] = tile__send_data__msg[7][3]; - assign tile__send_data__rdy[7][3] = send_data_on_boundary_east__rdy[1]; - assign send_data_on_boundary_east__val[1] = tile__send_data__val[7][3]; - assign tile__recv_data__msg[7][3] = recv_data_on_boundary_east__msg[1]; - assign recv_data_on_boundary_east__rdy[1] = tile__recv_data__rdy[7][3]; - assign tile__recv_data__val[7][3] = recv_data_on_boundary_east__val[1]; - assign tile__to_mem_raddr__rdy[7] = 1'd0; - assign tile__from_mem_rdata__val[7] = 1'd0; - assign tile__from_mem_rdata__msg[7] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[7] = 1'd0; - assign tile__to_mem_wdata__rdy[7] = 1'd0; - assign tile__recv_data__msg[4][0] = tile__send_data__msg[8][1]; - assign tile__send_data__rdy[8][1] = tile__recv_data__rdy[4][0]; - assign tile__recv_data__val[4][0] = tile__send_data__val[8][1]; - assign tile__recv_data__msg[12][1] = tile__send_data__msg[8][0]; - assign tile__send_data__rdy[8][0] = tile__recv_data__rdy[12][1]; - assign tile__recv_data__val[12][1] = tile__send_data__val[8][0]; - assign tile__recv_data__msg[9][2] = tile__send_data__msg[8][3]; - assign tile__send_data__rdy[8][3] = tile__recv_data__rdy[9][2]; - assign tile__recv_data__val[9][2] = tile__send_data__val[8][3]; - assign send_data_on_boundary_west__msg[2] = tile__send_data__msg[8][2]; - assign tile__send_data__rdy[8][2] = send_data_on_boundary_west__rdy[2]; - assign send_data_on_boundary_west__val[2] = tile__send_data__val[8][2]; - assign tile__recv_data__msg[8][2] = recv_data_on_boundary_west__msg[2]; - assign recv_data_on_boundary_west__rdy[2] = tile__recv_data__rdy[8][2]; - assign tile__recv_data__val[8][2] = recv_data_on_boundary_west__val[2]; - assign data_mem__recv_raddr__msg[5] = tile__to_mem_raddr__msg[8]; - assign tile__to_mem_raddr__rdy[8] = data_mem__recv_raddr__rdy[5]; - assign data_mem__recv_raddr__val[5] = tile__to_mem_raddr__val[8]; - assign tile__from_mem_rdata__msg[8] = data_mem__send_rdata__msg[5]; - assign data_mem__send_rdata__rdy[5] = tile__from_mem_rdata__rdy[8]; - assign tile__from_mem_rdata__val[8] = data_mem__send_rdata__val[5]; - assign data_mem__recv_waddr__msg[5] = tile__to_mem_waddr__msg[8]; - assign tile__to_mem_waddr__rdy[8] = data_mem__recv_waddr__rdy[5]; - assign data_mem__recv_waddr__val[5] = tile__to_mem_waddr__val[8]; - assign data_mem__recv_wdata__msg[5] = tile__to_mem_wdata__msg[8]; - assign tile__to_mem_wdata__rdy[8] = data_mem__recv_wdata__rdy[5]; - assign data_mem__recv_wdata__val[5] = tile__to_mem_wdata__val[8]; - assign tile__recv_data__msg[5][0] = tile__send_data__msg[9][1]; - assign tile__send_data__rdy[9][1] = tile__recv_data__rdy[5][0]; - assign tile__recv_data__val[5][0] = tile__send_data__val[9][1]; - assign tile__recv_data__msg[13][1] = tile__send_data__msg[9][0]; - assign tile__send_data__rdy[9][0] = tile__recv_data__rdy[13][1]; - assign tile__recv_data__val[13][1] = tile__send_data__val[9][0]; - assign tile__recv_data__msg[8][3] = tile__send_data__msg[9][2]; - assign tile__send_data__rdy[9][2] = tile__recv_data__rdy[8][3]; - assign tile__recv_data__val[8][3] = tile__send_data__val[9][2]; - assign tile__recv_data__msg[10][2] = tile__send_data__msg[9][3]; - assign tile__send_data__rdy[9][3] = tile__recv_data__rdy[10][2]; - assign tile__recv_data__val[10][2] = tile__send_data__val[9][3]; - assign tile__to_mem_raddr__rdy[9] = 1'd0; - assign tile__from_mem_rdata__val[9] = 1'd0; - assign tile__from_mem_rdata__msg[9] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[9] = 1'd0; - assign tile__to_mem_wdata__rdy[9] = 1'd0; - assign tile__recv_data__msg[6][0] = tile__send_data__msg[10][1]; - assign tile__send_data__rdy[10][1] = tile__recv_data__rdy[6][0]; - assign tile__recv_data__val[6][0] = tile__send_data__val[10][1]; - assign tile__recv_data__msg[14][1] = tile__send_data__msg[10][0]; - assign tile__send_data__rdy[10][0] = tile__recv_data__rdy[14][1]; - assign tile__recv_data__val[14][1] = tile__send_data__val[10][0]; - assign tile__recv_data__msg[9][3] = tile__send_data__msg[10][2]; - assign tile__send_data__rdy[10][2] = tile__recv_data__rdy[9][3]; - assign tile__recv_data__val[9][3] = tile__send_data__val[10][2]; - assign tile__recv_data__msg[11][2] = tile__send_data__msg[10][3]; - assign tile__send_data__rdy[10][3] = tile__recv_data__rdy[11][2]; - assign tile__recv_data__val[11][2] = tile__send_data__val[10][3]; - assign tile__to_mem_raddr__rdy[10] = 1'd0; - assign tile__from_mem_rdata__val[10] = 1'd0; - assign tile__from_mem_rdata__msg[10] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[10] = 1'd0; - assign tile__to_mem_wdata__rdy[10] = 1'd0; - assign tile__recv_data__msg[7][0] = tile__send_data__msg[11][1]; - assign tile__send_data__rdy[11][1] = tile__recv_data__rdy[7][0]; - assign tile__recv_data__val[7][0] = tile__send_data__val[11][1]; - assign tile__recv_data__msg[15][1] = tile__send_data__msg[11][0]; - assign tile__send_data__rdy[11][0] = tile__recv_data__rdy[15][1]; - assign tile__recv_data__val[15][1] = tile__send_data__val[11][0]; - assign tile__recv_data__msg[10][3] = tile__send_data__msg[11][2]; - assign tile__send_data__rdy[11][2] = tile__recv_data__rdy[10][3]; - assign tile__recv_data__val[10][3] = tile__send_data__val[11][2]; - assign send_data_on_boundary_east__msg[2] = tile__send_data__msg[11][3]; - assign tile__send_data__rdy[11][3] = send_data_on_boundary_east__rdy[2]; - assign send_data_on_boundary_east__val[2] = tile__send_data__val[11][3]; - assign tile__recv_data__msg[11][3] = recv_data_on_boundary_east__msg[2]; - assign recv_data_on_boundary_east__rdy[2] = tile__recv_data__rdy[11][3]; - assign tile__recv_data__val[11][3] = recv_data_on_boundary_east__val[2]; - assign tile__to_mem_raddr__rdy[11] = 1'd0; - assign tile__from_mem_rdata__val[11] = 1'd0; - assign tile__from_mem_rdata__msg[11] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[11] = 1'd0; - assign tile__to_mem_wdata__rdy[11] = 1'd0; - assign tile__recv_data__msg[8][0] = tile__send_data__msg[12][1]; - assign tile__send_data__rdy[12][1] = tile__recv_data__rdy[8][0]; - assign tile__recv_data__val[8][0] = tile__send_data__val[12][1]; - assign tile__recv_data__msg[13][2] = tile__send_data__msg[12][3]; - assign tile__send_data__rdy[12][3] = tile__recv_data__rdy[13][2]; - assign tile__recv_data__val[13][2] = tile__send_data__val[12][3]; - assign send_data_on_boundary_north__msg[0] = tile__send_data__msg[12][0]; - assign tile__send_data__rdy[12][0] = send_data_on_boundary_north__rdy[0]; - assign send_data_on_boundary_north__val[0] = tile__send_data__val[12][0]; - assign tile__recv_data__msg[12][0] = recv_data_on_boundary_north__msg[0]; - assign recv_data_on_boundary_north__rdy[0] = tile__recv_data__rdy[12][0]; - assign tile__recv_data__val[12][0] = recv_data_on_boundary_north__val[0]; - assign send_data_on_boundary_west__msg[3] = tile__send_data__msg[12][2]; - assign tile__send_data__rdy[12][2] = send_data_on_boundary_west__rdy[3]; - assign send_data_on_boundary_west__val[3] = tile__send_data__val[12][2]; - assign tile__recv_data__msg[12][2] = recv_data_on_boundary_west__msg[3]; - assign recv_data_on_boundary_west__rdy[3] = tile__recv_data__rdy[12][2]; - assign tile__recv_data__val[12][2] = recv_data_on_boundary_west__val[3]; - assign data_mem__recv_raddr__msg[6] = tile__to_mem_raddr__msg[12]; - assign tile__to_mem_raddr__rdy[12] = data_mem__recv_raddr__rdy[6]; - assign data_mem__recv_raddr__val[6] = tile__to_mem_raddr__val[12]; - assign tile__from_mem_rdata__msg[12] = data_mem__send_rdata__msg[6]; - assign data_mem__send_rdata__rdy[6] = tile__from_mem_rdata__rdy[12]; - assign tile__from_mem_rdata__val[12] = data_mem__send_rdata__val[6]; - assign data_mem__recv_waddr__msg[6] = tile__to_mem_waddr__msg[12]; - assign tile__to_mem_waddr__rdy[12] = data_mem__recv_waddr__rdy[6]; - assign data_mem__recv_waddr__val[6] = tile__to_mem_waddr__val[12]; - assign data_mem__recv_wdata__msg[6] = tile__to_mem_wdata__msg[12]; - assign tile__to_mem_wdata__rdy[12] = data_mem__recv_wdata__rdy[6]; - assign data_mem__recv_wdata__val[6] = tile__to_mem_wdata__val[12]; - assign tile__recv_data__msg[9][0] = tile__send_data__msg[13][1]; - assign tile__send_data__rdy[13][1] = tile__recv_data__rdy[9][0]; - assign tile__recv_data__val[9][0] = tile__send_data__val[13][1]; - assign tile__recv_data__msg[12][3] = tile__send_data__msg[13][2]; - assign tile__send_data__rdy[13][2] = tile__recv_data__rdy[12][3]; - assign tile__recv_data__val[12][3] = tile__send_data__val[13][2]; - assign tile__recv_data__msg[14][2] = tile__send_data__msg[13][3]; - assign tile__send_data__rdy[13][3] = tile__recv_data__rdy[14][2]; - assign tile__recv_data__val[14][2] = tile__send_data__val[13][3]; - assign send_data_on_boundary_north__msg[1] = tile__send_data__msg[13][0]; - assign tile__send_data__rdy[13][0] = send_data_on_boundary_north__rdy[1]; - assign send_data_on_boundary_north__val[1] = tile__send_data__val[13][0]; - assign tile__recv_data__msg[13][0] = recv_data_on_boundary_north__msg[1]; - assign recv_data_on_boundary_north__rdy[1] = tile__recv_data__rdy[13][0]; - assign tile__recv_data__val[13][0] = recv_data_on_boundary_north__val[1]; - assign tile__to_mem_raddr__rdy[13] = 1'd0; - assign tile__from_mem_rdata__val[13] = 1'd0; - assign tile__from_mem_rdata__msg[13] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[13] = 1'd0; - assign tile__to_mem_wdata__rdy[13] = 1'd0; - assign tile__recv_data__msg[10][0] = tile__send_data__msg[14][1]; - assign tile__send_data__rdy[14][1] = tile__recv_data__rdy[10][0]; - assign tile__recv_data__val[10][0] = tile__send_data__val[14][1]; - assign tile__recv_data__msg[13][3] = tile__send_data__msg[14][2]; - assign tile__send_data__rdy[14][2] = tile__recv_data__rdy[13][3]; - assign tile__recv_data__val[13][3] = tile__send_data__val[14][2]; - assign tile__recv_data__msg[15][2] = tile__send_data__msg[14][3]; - assign tile__send_data__rdy[14][3] = tile__recv_data__rdy[15][2]; - assign tile__recv_data__val[15][2] = tile__send_data__val[14][3]; - assign send_data_on_boundary_north__msg[2] = tile__send_data__msg[14][0]; - assign tile__send_data__rdy[14][0] = send_data_on_boundary_north__rdy[2]; - assign send_data_on_boundary_north__val[2] = tile__send_data__val[14][0]; - assign tile__recv_data__msg[14][0] = recv_data_on_boundary_north__msg[2]; - assign recv_data_on_boundary_north__rdy[2] = tile__recv_data__rdy[14][0]; - assign tile__recv_data__val[14][0] = recv_data_on_boundary_north__val[2]; - assign tile__to_mem_raddr__rdy[14] = 1'd0; - assign tile__from_mem_rdata__val[14] = 1'd0; - assign tile__from_mem_rdata__msg[14] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[14] = 1'd0; - assign tile__to_mem_wdata__rdy[14] = 1'd0; - assign tile__recv_data__msg[11][0] = tile__send_data__msg[15][1]; - assign tile__send_data__rdy[15][1] = tile__recv_data__rdy[11][0]; - assign tile__recv_data__val[11][0] = tile__send_data__val[15][1]; - assign tile__recv_data__msg[14][3] = tile__send_data__msg[15][2]; - assign tile__send_data__rdy[15][2] = tile__recv_data__rdy[14][3]; - assign tile__recv_data__val[14][3] = tile__send_data__val[15][2]; - assign send_data_on_boundary_north__msg[3] = tile__send_data__msg[15][0]; - assign tile__send_data__rdy[15][0] = send_data_on_boundary_north__rdy[3]; - assign send_data_on_boundary_north__val[3] = tile__send_data__val[15][0]; - assign tile__recv_data__msg[15][0] = recv_data_on_boundary_north__msg[3]; - assign recv_data_on_boundary_north__rdy[3] = tile__recv_data__rdy[15][0]; - assign tile__recv_data__val[15][0] = recv_data_on_boundary_north__val[3]; - assign send_data_on_boundary_east__msg[3] = tile__send_data__msg[15][3]; - assign tile__send_data__rdy[15][3] = send_data_on_boundary_east__rdy[3]; - assign send_data_on_boundary_east__val[3] = tile__send_data__val[15][3]; - assign tile__recv_data__msg[15][3] = recv_data_on_boundary_east__msg[3]; - assign recv_data_on_boundary_east__rdy[3] = tile__recv_data__rdy[15][3]; - assign tile__recv_data__val[15][3] = recv_data_on_boundary_east__val[3]; - assign tile__to_mem_raddr__rdy[15] = 1'd0; - assign tile__from_mem_rdata__val[15] = 1'd0; - assign tile__from_mem_rdata__msg[15] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[15] = 1'd0; - assign tile__to_mem_wdata__rdy[15] = 1'd0; - -endmodule - - -// PyMTL Component InputUnitRTL Definition -// Full name: InputUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_NormalQueueRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py - -module InputUnitRTL__8ea2cb5fb7536c6c -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queue - //------------------------------------------------------------- - - logic [0:0] queue__clk; - logic [1:0] queue__count; - logic [0:0] queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__recv__msg; - logic [0:0] queue__recv__rdy; - logic [0:0] queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__send__msg; - logic [0:0] queue__send__rdy; - logic [0:0] queue__send__val; - - NormalQueueRTL__c7280ffb0786127e queue - ( - .clk( queue__clk ), - .count( queue__count ), - .reset( queue__reset ), - .recv__msg( queue__recv__msg ), - .recv__rdy( queue__recv__rdy ), - .recv__val( queue__recv__val ), - .send__msg( queue__send__msg ), - .send__rdy( queue__send__rdy ), - .send__val( queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component queue - //------------------------------------------------------------- - - assign queue__clk = clk; - assign queue__reset = reset; - assign queue__recv__msg = recv__msg; - assign recv__rdy = queue__recv__rdy; - assign queue__recv__val = recv__val; - assign send__msg = queue__send__msg; - assign queue__send__rdy = send__rdy; - assign send__val = queue__send__val; - -endmodule - - -// PyMTL Component OutputUnitRTL Definition -// Full name: OutputUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_None -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py - -module OutputUnitRTL__e43ef936c3b236b0 -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - assign send__msg = recv__msg; - assign recv__rdy = send__rdy; - assign send__val = recv__val; - -endmodule - - -// PyMTL Component DORYMeshRouteUnitRTL Definition -// Full name: DORYMeshRouteUnitRTL__MsgType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__num_outports_5 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py - -module DORYMeshRouteUnitRTL__cf2d804ed36fdf23 -( - input logic [0:0] clk , - input MeshPosition_2x2__pos_x_1__pos_y_1 pos , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:4] , - input logic [0:0] send__rdy [0:4] , - output logic [0:0] send__val [0:4] -); - localparam logic [2:0] __const__num_outports_at_up_ru_routing = 3'd5; - localparam logic [2:0] __const__SELF = 3'd4; - localparam logic [0:0] __const__SOUTH = 1'd1; - localparam logic [0:0] __const__NORTH = 1'd0; - localparam logic [1:0] __const__WEST = 2'd2; - localparam logic [1:0] __const__EAST = 2'd3; - logic [2:0] out_dir; - logic [4:0] send_rdy; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py:57 - // @update - // def up_ru_recv_rdy(): - // s.recv.rdy @= s.send_rdy[ s.out_dir ] - - always_comb begin : up_ru_recv_rdy - recv__rdy = send_rdy[out_dir]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py:38 - // @update - // def up_ru_routing(): - // s.out_dir @= Bits3(0) - // for i in range( num_outports ): - // s.send[i].val @= Bits1(0) - // - // if s.recv.val: - // if (s.pos.pos_x == s.recv.msg.dst_x) & (s.pos.pos_y == s.recv.msg.dst_y): - // s.out_dir @= SELF - // elif s.recv.msg.dst_y < s.pos.pos_y: - // s.out_dir @= SOUTH - // elif s.recv.msg.dst_y > s.pos.pos_y: - // s.out_dir @= NORTH - // elif s.recv.msg.dst_x < s.pos.pos_x: - // s.out_dir @= WEST - // else: - // s.out_dir @= EAST - // s.send[ s.out_dir ].val @= Bits1(1) - - always_comb begin : up_ru_routing - out_dir = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) - send__val[3'(i)] = 1'd0; - if ( recv__val ) begin - if ( ( pos.pos_x == recv__msg.dst_x ) & ( pos.pos_y == recv__msg.dst_y ) ) begin - out_dir = 3'( __const__SELF ); - end - else if ( recv__msg.dst_y < pos.pos_y ) begin - out_dir = 3'( __const__SOUTH ); - end - else if ( recv__msg.dst_y > pos.pos_y ) begin - out_dir = 3'( __const__NORTH ); - end - else if ( recv__msg.dst_x < pos.pos_x ) begin - out_dir = 3'( __const__WEST ); - end - else - out_dir = 3'( __const__EAST ); - send__val[out_dir] = 1'd1; - end - end - - assign send__msg[0] = recv__msg; - assign send_rdy[0:0] = send__rdy[0]; - assign send__msg[1] = recv__msg; - assign send_rdy[1:1] = send__rdy[1]; - assign send__msg[2] = recv__msg; - assign send_rdy[2:2] = send__rdy[2]; - assign send__msg[3] = recv__msg; - assign send_rdy[3:3] = send__rdy[3]; - assign send__msg[4] = recv__msg; - assign send_rdy[4:4] = send__rdy[4]; - -endmodule - - -// PyMTL Component RegEnRst Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py - -module RegEnRst__Type_Bits5__reset_value_1 -( - input logic [0:0] clk , - input logic [0:0] en , - input logic [4:0] in_ , - output logic [4:0] out , - input logic [0:0] reset -); - localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 - // @update_ff - // def up_regenrst(): - // if s.reset: s.out <<= reset_value - // elif s.en: s.out <<= s.in_ - - always_ff @(posedge clk) begin : up_regenrst - if ( reset ) begin - out <= 5'( __const__reset_value_at_up_regenrst ); - end - else if ( en ) begin - out <= in_; - end - end - -endmodule - - -// PyMTL Component RoundRobinArbiterEn Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py - -module RoundRobinArbiterEn__nreqs_5 -( - input logic [0:0] clk , - input logic [0:0] en , - output logic [4:0] grants , - input logic [4:0] reqs , - input logic [0:0] reset -); - localparam logic [2:0] __const__nreqs_at_comb_reqs_int = 3'd5; - localparam logic [3:0] __const__nreqsX2_at_comb_reqs_int = 4'd10; - localparam logic [2:0] __const__nreqs_at_comb_grants = 3'd5; - localparam logic [2:0] __const__nreqs_at_comb_priority_int = 3'd5; - localparam logic [3:0] __const__nreqsX2_at_comb_priority_int = 4'd10; - localparam logic [3:0] __const__nreqsX2_at_comb_kills = 4'd10; - localparam logic [3:0] __const__nreqsX2_at_comb_grants_int = 4'd10; - logic [9:0] grants_int; - logic [10:0] kills; - logic [0:0] priority_en; - logic [9:0] priority_int; - logic [9:0] reqs_int; - //------------------------------------------------------------- - // Component priority_reg - //------------------------------------------------------------- - - logic [0:0] priority_reg__clk; - logic [0:0] priority_reg__en; - logic [4:0] priority_reg__in_; - logic [4:0] priority_reg__out; - logic [0:0] priority_reg__reset; - - RegEnRst__Type_Bits5__reset_value_1 priority_reg - ( - .clk( priority_reg__clk ), - .en( priority_reg__en ), - .in_( priority_reg__in_ ), - .out( priority_reg__out ), - .reset( priority_reg__reset ) - ); - - //------------------------------------------------------------- - // End of component priority_reg - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 - // @update - // def comb_grants(): - // for i in range( nreqs ): - // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] - - always_comb begin : comb_grants - for ( int unsigned i = 1'd0; i < 3'( __const__nreqs_at_comb_grants ); i += 1'd1 ) - grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 - // @update - // def comb_grants_int(): - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.grants_int[i] @= s.reqs_int[i] - // else: - // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] - - always_comb begin : comb_grants_int - for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - grants_int[4'(i)] = reqs_int[4'(i)]; - end - else - grants_int[4'(i)] = ( ~kills[4'(i)] ) & reqs_int[4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 - // @update - // def comb_kills(): - // s.kills[0] @= 1 - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.kills[i+1] @= s.reqs_int[i] - // else: - // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) - - always_comb begin : comb_kills - kills[4'd0] = 1'd1; - for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - kills[4'(i) + 4'd1] = reqs_int[4'(i)]; - end - else - kills[4'(i) + 4'd1] = kills[4'(i)] | ( ( ~kills[4'(i)] ) & reqs_int[4'(i)] ); - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 - // @update - // def comb_priority_en(): - // s.priority_en @= ( s.grants != 0 ) & s.en - - always_comb begin : comb_priority_en - priority_en = ( grants != 5'd0 ) & en; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 - // @update - // def comb_priority_int(): - // s.priority_int[ 0:nreqs ] @= s.priority_reg.out - // s.priority_int[nreqs:nreqsX2] @= 0 - - always_comb begin : comb_priority_int - priority_int[4'd4:4'd0] = priority_reg__out; - priority_int[4'd9:4'( __const__nreqs_at_comb_priority_int )] = 5'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 - // @update - // def comb_reqs_int(): - // s.reqs_int [ 0:nreqs ] @= s.reqs - // s.reqs_int [nreqs:nreqsX2] @= s.reqs - - always_comb begin : comb_reqs_int - reqs_int[4'd4:4'd0] = reqs; - reqs_int[4'd9:4'( __const__nreqs_at_comb_reqs_int )] = reqs; - end - - assign priority_reg__clk = clk; - assign priority_reg__reset = reset; - assign priority_reg__en = priority_en; - assign priority_reg__in_[4:1] = grants[3:0]; - assign priority_reg__in_[0:0] = grants[4:4]; - -endmodule - - -// PyMTL Component Encoder Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py - -module Encoder__in_nbits_5__out_nbits_3 -( - input logic [0:0] clk , - input logic [4:0] in_ , - output logic [2:0] out , - input logic [0:0] reset -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 - // @update - // def encode(): - // s.out @= 0 - // for i in range( s.in_nbits ): - // if s.in_[i]: - // s.out @= i - - always_comb begin : encode - out = 3'd0; - for ( int unsigned i = 1'd0; i < 3'd5; i += 1'd1 ) - if ( in_[3'(i)] ) begin - out = 3'(i); - end - end - -endmodule - - -// PyMTL Component Mux Definition -// Full name: Mux__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__ninputs_5 -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__5c29509c868f9669 -( - input logic [0:0] clk , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d in_ [0:4], - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d out , - input logic [0:0] reset , - input logic [2:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component SwitchUnitRTL Definition -// Full name: SwitchUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_inports_5 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py - -module SwitchUnitRTL__1ccc072d8fcd170f -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:4] , - output logic [0:0] recv__rdy [0:4] , - input logic [0:0] recv__val [0:4] , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd5; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [4:0] arbiter__grants; - logic [4:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_5 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [4:0] encoder__in_; - logic [2:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_5__out_nbits_3 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mux__in_ [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mux__out; - logic [0:0] mux__reset; - logic [2:0] mux__sel; - - Mux__5c29509c868f9669 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 - // @update - // def up_get_en(): - // for i in range( num_inports ): - // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) - - always_comb begin : up_get_en - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) - recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 - // @update - // def up_send_val(): - // s.send.val @= s.arbiter.grants > 0 - - always_comb begin : up_send_val - send__val = arbiter__grants > 5'd0; - end - - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign arbiter__en = 1'd1; - assign mux__clk = clk; - assign mux__reset = reset; - assign send__msg = mux__out; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign encoder__in_ = arbiter__grants; - assign mux__sel = encoder__out; - assign arbiter__reqs[0:0] = recv__val[0]; - assign mux__in_[0] = recv__msg[0]; - assign arbiter__reqs[1:1] = recv__val[1]; - assign mux__in_[1] = recv__msg[1]; - assign arbiter__reqs[2:2] = recv__val[2]; - assign mux__in_[2] = recv__msg[2]; - assign arbiter__reqs[3:3] = recv__val[3]; - assign mux__in_[3] = recv__msg[3]; - assign arbiter__reqs[4:4] = recv__val[4]; - assign mux__in_[4] = recv__msg[4]; - -endmodule - - -// PyMTL Component MeshRouterRTL Definition -// Full name: MeshRouterRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__InputUnitType_InputUnitRTL__RouteUnitType_DORYMeshRouteUnitRTL__SwitchUnitType_SwitchUnitRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/MeshRouterRTL.py - -module MeshRouterRTL__574f02d875fdbb92 -( - input logic [0:0] clk , - input MeshPosition_2x2__pos_x_1__pos_y_1 pos , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:4] , - output logic [0:0] recv__rdy [0:4] , - input logic [0:0] recv__val [0:4] , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:4] , - input logic [0:0] send__rdy [0:4] , - output logic [0:0] send__val [0:4] -); - //------------------------------------------------------------- - // Component input_units[0:4] - //------------------------------------------------------------- - - logic [0:0] input_units__clk [0:4]; - logic [0:0] input_units__reset [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d input_units__recv__msg [0:4]; - logic [0:0] input_units__recv__rdy [0:4]; - logic [0:0] input_units__recv__val [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d input_units__send__msg [0:4]; - logic [0:0] input_units__send__rdy [0:4]; - logic [0:0] input_units__send__val [0:4]; - - InputUnitRTL__8ea2cb5fb7536c6c input_units__0 - ( - .clk( input_units__clk[0] ), - .reset( input_units__reset[0] ), - .recv__msg( input_units__recv__msg[0] ), - .recv__rdy( input_units__recv__rdy[0] ), - .recv__val( input_units__recv__val[0] ), - .send__msg( input_units__send__msg[0] ), - .send__rdy( input_units__send__rdy[0] ), - .send__val( input_units__send__val[0] ) - ); - - InputUnitRTL__8ea2cb5fb7536c6c input_units__1 - ( - .clk( input_units__clk[1] ), - .reset( input_units__reset[1] ), - .recv__msg( input_units__recv__msg[1] ), - .recv__rdy( input_units__recv__rdy[1] ), - .recv__val( input_units__recv__val[1] ), - .send__msg( input_units__send__msg[1] ), - .send__rdy( input_units__send__rdy[1] ), - .send__val( input_units__send__val[1] ) - ); - - InputUnitRTL__8ea2cb5fb7536c6c input_units__2 - ( - .clk( input_units__clk[2] ), - .reset( input_units__reset[2] ), - .recv__msg( input_units__recv__msg[2] ), - .recv__rdy( input_units__recv__rdy[2] ), - .recv__val( input_units__recv__val[2] ), - .send__msg( input_units__send__msg[2] ), - .send__rdy( input_units__send__rdy[2] ), - .send__val( input_units__send__val[2] ) - ); - - InputUnitRTL__8ea2cb5fb7536c6c input_units__3 - ( - .clk( input_units__clk[3] ), - .reset( input_units__reset[3] ), - .recv__msg( input_units__recv__msg[3] ), - .recv__rdy( input_units__recv__rdy[3] ), - .recv__val( input_units__recv__val[3] ), - .send__msg( input_units__send__msg[3] ), - .send__rdy( input_units__send__rdy[3] ), - .send__val( input_units__send__val[3] ) - ); - - InputUnitRTL__8ea2cb5fb7536c6c input_units__4 - ( - .clk( input_units__clk[4] ), - .reset( input_units__reset[4] ), - .recv__msg( input_units__recv__msg[4] ), - .recv__rdy( input_units__recv__rdy[4] ), - .recv__val( input_units__recv__val[4] ), - .send__msg( input_units__send__msg[4] ), - .send__rdy( input_units__send__rdy[4] ), - .send__val( input_units__send__val[4] ) - ); - - //------------------------------------------------------------- - // End of component input_units[0:4] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component output_units[0:4] - //------------------------------------------------------------- - - logic [0:0] output_units__clk [0:4]; - logic [0:0] output_units__reset [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d output_units__recv__msg [0:4]; - logic [0:0] output_units__recv__rdy [0:4]; - logic [0:0] output_units__recv__val [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d output_units__send__msg [0:4]; - logic [0:0] output_units__send__rdy [0:4]; - logic [0:0] output_units__send__val [0:4]; - - OutputUnitRTL__e43ef936c3b236b0 output_units__0 - ( - .clk( output_units__clk[0] ), - .reset( output_units__reset[0] ), - .recv__msg( output_units__recv__msg[0] ), - .recv__rdy( output_units__recv__rdy[0] ), - .recv__val( output_units__recv__val[0] ), - .send__msg( output_units__send__msg[0] ), - .send__rdy( output_units__send__rdy[0] ), - .send__val( output_units__send__val[0] ) - ); - - OutputUnitRTL__e43ef936c3b236b0 output_units__1 - ( - .clk( output_units__clk[1] ), - .reset( output_units__reset[1] ), - .recv__msg( output_units__recv__msg[1] ), - .recv__rdy( output_units__recv__rdy[1] ), - .recv__val( output_units__recv__val[1] ), - .send__msg( output_units__send__msg[1] ), - .send__rdy( output_units__send__rdy[1] ), - .send__val( output_units__send__val[1] ) - ); - - OutputUnitRTL__e43ef936c3b236b0 output_units__2 - ( - .clk( output_units__clk[2] ), - .reset( output_units__reset[2] ), - .recv__msg( output_units__recv__msg[2] ), - .recv__rdy( output_units__recv__rdy[2] ), - .recv__val( output_units__recv__val[2] ), - .send__msg( output_units__send__msg[2] ), - .send__rdy( output_units__send__rdy[2] ), - .send__val( output_units__send__val[2] ) - ); - - OutputUnitRTL__e43ef936c3b236b0 output_units__3 - ( - .clk( output_units__clk[3] ), - .reset( output_units__reset[3] ), - .recv__msg( output_units__recv__msg[3] ), - .recv__rdy( output_units__recv__rdy[3] ), - .recv__val( output_units__recv__val[3] ), - .send__msg( output_units__send__msg[3] ), - .send__rdy( output_units__send__rdy[3] ), - .send__val( output_units__send__val[3] ) - ); - - OutputUnitRTL__e43ef936c3b236b0 output_units__4 - ( - .clk( output_units__clk[4] ), - .reset( output_units__reset[4] ), - .recv__msg( output_units__recv__msg[4] ), - .recv__rdy( output_units__recv__rdy[4] ), - .recv__val( output_units__recv__val[4] ), - .send__msg( output_units__send__msg[4] ), - .send__rdy( output_units__send__rdy[4] ), - .send__val( output_units__send__val[4] ) - ); - - //------------------------------------------------------------- - // End of component output_units[0:4] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component route_units[0:4] - //------------------------------------------------------------- - - logic [0:0] route_units__clk [0:4]; - MeshPosition_2x2__pos_x_1__pos_y_1 route_units__pos [0:4]; - logic [0:0] route_units__reset [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d route_units__recv__msg [0:4]; - logic [0:0] route_units__recv__rdy [0:4]; - logic [0:0] route_units__recv__val [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d route_units__send__msg [0:4][0:4]; - logic [0:0] route_units__send__rdy [0:4][0:4]; - logic [0:0] route_units__send__val [0:4][0:4]; - - DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__0 - ( - .clk( route_units__clk[0] ), - .pos( route_units__pos[0] ), - .reset( route_units__reset[0] ), - .recv__msg( route_units__recv__msg[0] ), - .recv__rdy( route_units__recv__rdy[0] ), - .recv__val( route_units__recv__val[0] ), - .send__msg( route_units__send__msg[0] ), - .send__rdy( route_units__send__rdy[0] ), - .send__val( route_units__send__val[0] ) - ); - - DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__1 - ( - .clk( route_units__clk[1] ), - .pos( route_units__pos[1] ), - .reset( route_units__reset[1] ), - .recv__msg( route_units__recv__msg[1] ), - .recv__rdy( route_units__recv__rdy[1] ), - .recv__val( route_units__recv__val[1] ), - .send__msg( route_units__send__msg[1] ), - .send__rdy( route_units__send__rdy[1] ), - .send__val( route_units__send__val[1] ) - ); - - DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__2 - ( - .clk( route_units__clk[2] ), - .pos( route_units__pos[2] ), - .reset( route_units__reset[2] ), - .recv__msg( route_units__recv__msg[2] ), - .recv__rdy( route_units__recv__rdy[2] ), - .recv__val( route_units__recv__val[2] ), - .send__msg( route_units__send__msg[2] ), - .send__rdy( route_units__send__rdy[2] ), - .send__val( route_units__send__val[2] ) - ); - - DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__3 - ( - .clk( route_units__clk[3] ), - .pos( route_units__pos[3] ), - .reset( route_units__reset[3] ), - .recv__msg( route_units__recv__msg[3] ), - .recv__rdy( route_units__recv__rdy[3] ), - .recv__val( route_units__recv__val[3] ), - .send__msg( route_units__send__msg[3] ), - .send__rdy( route_units__send__rdy[3] ), - .send__val( route_units__send__val[3] ) - ); - - DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__4 - ( - .clk( route_units__clk[4] ), - .pos( route_units__pos[4] ), - .reset( route_units__reset[4] ), - .recv__msg( route_units__recv__msg[4] ), - .recv__rdy( route_units__recv__rdy[4] ), - .recv__val( route_units__recv__val[4] ), - .send__msg( route_units__send__msg[4] ), - .send__rdy( route_units__send__rdy[4] ), - .send__val( route_units__send__val[4] ) - ); - - //------------------------------------------------------------- - // End of component route_units[0:4] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component switch_units[0:4] - //------------------------------------------------------------- - - logic [0:0] switch_units__clk [0:4]; - logic [0:0] switch_units__reset [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d switch_units__recv__msg [0:4][0:4]; - logic [0:0] switch_units__recv__rdy [0:4][0:4]; - logic [0:0] switch_units__recv__val [0:4][0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d switch_units__send__msg [0:4]; - logic [0:0] switch_units__send__rdy [0:4]; - logic [0:0] switch_units__send__val [0:4]; - - SwitchUnitRTL__1ccc072d8fcd170f switch_units__0 - ( - .clk( switch_units__clk[0] ), - .reset( switch_units__reset[0] ), - .recv__msg( switch_units__recv__msg[0] ), - .recv__rdy( switch_units__recv__rdy[0] ), - .recv__val( switch_units__recv__val[0] ), - .send__msg( switch_units__send__msg[0] ), - .send__rdy( switch_units__send__rdy[0] ), - .send__val( switch_units__send__val[0] ) - ); - - SwitchUnitRTL__1ccc072d8fcd170f switch_units__1 - ( - .clk( switch_units__clk[1] ), - .reset( switch_units__reset[1] ), - .recv__msg( switch_units__recv__msg[1] ), - .recv__rdy( switch_units__recv__rdy[1] ), - .recv__val( switch_units__recv__val[1] ), - .send__msg( switch_units__send__msg[1] ), - .send__rdy( switch_units__send__rdy[1] ), - .send__val( switch_units__send__val[1] ) - ); - - SwitchUnitRTL__1ccc072d8fcd170f switch_units__2 - ( - .clk( switch_units__clk[2] ), - .reset( switch_units__reset[2] ), - .recv__msg( switch_units__recv__msg[2] ), - .recv__rdy( switch_units__recv__rdy[2] ), - .recv__val( switch_units__recv__val[2] ), - .send__msg( switch_units__send__msg[2] ), - .send__rdy( switch_units__send__rdy[2] ), - .send__val( switch_units__send__val[2] ) - ); - - SwitchUnitRTL__1ccc072d8fcd170f switch_units__3 - ( - .clk( switch_units__clk[3] ), - .reset( switch_units__reset[3] ), - .recv__msg( switch_units__recv__msg[3] ), - .recv__rdy( switch_units__recv__rdy[3] ), - .recv__val( switch_units__recv__val[3] ), - .send__msg( switch_units__send__msg[3] ), - .send__rdy( switch_units__send__rdy[3] ), - .send__val( switch_units__send__val[3] ) - ); - - SwitchUnitRTL__1ccc072d8fcd170f switch_units__4 - ( - .clk( switch_units__clk[4] ), - .reset( switch_units__reset[4] ), - .recv__msg( switch_units__recv__msg[4] ), - .recv__rdy( switch_units__recv__rdy[4] ), - .recv__val( switch_units__recv__val[4] ), - .send__msg( switch_units__send__msg[4] ), - .send__rdy( switch_units__send__rdy[4] ), - .send__val( switch_units__send__val[4] ) - ); - - //------------------------------------------------------------- - // End of component switch_units[0:4] - //------------------------------------------------------------- - - assign input_units__clk[0] = clk; - assign input_units__reset[0] = reset; - assign input_units__clk[1] = clk; - assign input_units__reset[1] = reset; - assign input_units__clk[2] = clk; - assign input_units__reset[2] = reset; - assign input_units__clk[3] = clk; - assign input_units__reset[3] = reset; - assign input_units__clk[4] = clk; - assign input_units__reset[4] = reset; - assign route_units__clk[0] = clk; - assign route_units__reset[0] = reset; - assign route_units__clk[1] = clk; - assign route_units__reset[1] = reset; - assign route_units__clk[2] = clk; - assign route_units__reset[2] = reset; - assign route_units__clk[3] = clk; - assign route_units__reset[3] = reset; - assign route_units__clk[4] = clk; - assign route_units__reset[4] = reset; - assign switch_units__clk[0] = clk; - assign switch_units__reset[0] = reset; - assign switch_units__clk[1] = clk; - assign switch_units__reset[1] = reset; - assign switch_units__clk[2] = clk; - assign switch_units__reset[2] = reset; - assign switch_units__clk[3] = clk; - assign switch_units__reset[3] = reset; - assign switch_units__clk[4] = clk; - assign switch_units__reset[4] = reset; - assign output_units__clk[0] = clk; - assign output_units__reset[0] = reset; - assign output_units__clk[1] = clk; - assign output_units__reset[1] = reset; - assign output_units__clk[2] = clk; - assign output_units__reset[2] = reset; - assign output_units__clk[3] = clk; - assign output_units__reset[3] = reset; - assign output_units__clk[4] = clk; - assign output_units__reset[4] = reset; - assign input_units__recv__msg[0] = recv__msg[0]; - assign recv__rdy[0] = input_units__recv__rdy[0]; - assign input_units__recv__val[0] = recv__val[0]; - assign route_units__recv__msg[0] = input_units__send__msg[0]; - assign input_units__send__rdy[0] = route_units__recv__rdy[0]; - assign route_units__recv__val[0] = input_units__send__val[0]; - assign route_units__pos[0] = pos; - assign input_units__recv__msg[1] = recv__msg[1]; - assign recv__rdy[1] = input_units__recv__rdy[1]; - assign input_units__recv__val[1] = recv__val[1]; - assign route_units__recv__msg[1] = input_units__send__msg[1]; - assign input_units__send__rdy[1] = route_units__recv__rdy[1]; - assign route_units__recv__val[1] = input_units__send__val[1]; - assign route_units__pos[1] = pos; - assign input_units__recv__msg[2] = recv__msg[2]; - assign recv__rdy[2] = input_units__recv__rdy[2]; - assign input_units__recv__val[2] = recv__val[2]; - assign route_units__recv__msg[2] = input_units__send__msg[2]; - assign input_units__send__rdy[2] = route_units__recv__rdy[2]; - assign route_units__recv__val[2] = input_units__send__val[2]; - assign route_units__pos[2] = pos; - assign input_units__recv__msg[3] = recv__msg[3]; - assign recv__rdy[3] = input_units__recv__rdy[3]; - assign input_units__recv__val[3] = recv__val[3]; - assign route_units__recv__msg[3] = input_units__send__msg[3]; - assign input_units__send__rdy[3] = route_units__recv__rdy[3]; - assign route_units__recv__val[3] = input_units__send__val[3]; - assign route_units__pos[3] = pos; - assign input_units__recv__msg[4] = recv__msg[4]; - assign recv__rdy[4] = input_units__recv__rdy[4]; - assign input_units__recv__val[4] = recv__val[4]; - assign route_units__recv__msg[4] = input_units__send__msg[4]; - assign input_units__send__rdy[4] = route_units__recv__rdy[4]; - assign route_units__recv__val[4] = input_units__send__val[4]; - assign route_units__pos[4] = pos; - assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; - assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; - assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; - assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; - assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; - assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; - assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; - assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; - assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; - assign switch_units__recv__msg[3][0] = route_units__send__msg[0][3]; - assign route_units__send__rdy[0][3] = switch_units__recv__rdy[3][0]; - assign switch_units__recv__val[3][0] = route_units__send__val[0][3]; - assign switch_units__recv__msg[4][0] = route_units__send__msg[0][4]; - assign route_units__send__rdy[0][4] = switch_units__recv__rdy[4][0]; - assign switch_units__recv__val[4][0] = route_units__send__val[0][4]; - assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; - assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; - assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; - assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; - assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; - assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; - assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; - assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; - assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; - assign switch_units__recv__msg[3][1] = route_units__send__msg[1][3]; - assign route_units__send__rdy[1][3] = switch_units__recv__rdy[3][1]; - assign switch_units__recv__val[3][1] = route_units__send__val[1][3]; - assign switch_units__recv__msg[4][1] = route_units__send__msg[1][4]; - assign route_units__send__rdy[1][4] = switch_units__recv__rdy[4][1]; - assign switch_units__recv__val[4][1] = route_units__send__val[1][4]; - assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; - assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; - assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; - assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; - assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; - assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; - assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; - assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; - assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; - assign switch_units__recv__msg[3][2] = route_units__send__msg[2][3]; - assign route_units__send__rdy[2][3] = switch_units__recv__rdy[3][2]; - assign switch_units__recv__val[3][2] = route_units__send__val[2][3]; - assign switch_units__recv__msg[4][2] = route_units__send__msg[2][4]; - assign route_units__send__rdy[2][4] = switch_units__recv__rdy[4][2]; - assign switch_units__recv__val[4][2] = route_units__send__val[2][4]; - assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; - assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; - assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; - assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; - assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; - assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; - assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; - assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; - assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; - assign switch_units__recv__msg[3][3] = route_units__send__msg[3][3]; - assign route_units__send__rdy[3][3] = switch_units__recv__rdy[3][3]; - assign switch_units__recv__val[3][3] = route_units__send__val[3][3]; - assign switch_units__recv__msg[4][3] = route_units__send__msg[3][4]; - assign route_units__send__rdy[3][4] = switch_units__recv__rdy[4][3]; - assign switch_units__recv__val[4][3] = route_units__send__val[3][4]; - assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; - assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; - assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; - assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; - assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; - assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; - assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; - assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; - assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; - assign switch_units__recv__msg[3][4] = route_units__send__msg[4][3]; - assign route_units__send__rdy[4][3] = switch_units__recv__rdy[3][4]; - assign switch_units__recv__val[3][4] = route_units__send__val[4][3]; - assign switch_units__recv__msg[4][4] = route_units__send__msg[4][4]; - assign route_units__send__rdy[4][4] = switch_units__recv__rdy[4][4]; - assign switch_units__recv__val[4][4] = route_units__send__val[4][4]; - assign output_units__recv__msg[0] = switch_units__send__msg[0]; - assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; - assign output_units__recv__val[0] = switch_units__send__val[0]; - assign send__msg[0] = output_units__send__msg[0]; - assign output_units__send__rdy[0] = send__rdy[0]; - assign send__val[0] = output_units__send__val[0]; - assign output_units__recv__msg[1] = switch_units__send__msg[1]; - assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; - assign output_units__recv__val[1] = switch_units__send__val[1]; - assign send__msg[1] = output_units__send__msg[1]; - assign output_units__send__rdy[1] = send__rdy[1]; - assign send__val[1] = output_units__send__val[1]; - assign output_units__recv__msg[2] = switch_units__send__msg[2]; - assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; - assign output_units__recv__val[2] = switch_units__send__val[2]; - assign send__msg[2] = output_units__send__msg[2]; - assign output_units__send__rdy[2] = send__rdy[2]; - assign send__val[2] = output_units__send__val[2]; - assign output_units__recv__msg[3] = switch_units__send__msg[3]; - assign switch_units__send__rdy[3] = output_units__recv__rdy[3]; - assign output_units__recv__val[3] = switch_units__send__val[3]; - assign send__msg[3] = output_units__send__msg[3]; - assign output_units__send__rdy[3] = send__rdy[3]; - assign send__val[3] = output_units__send__val[3]; - assign output_units__recv__msg[4] = switch_units__send__msg[4]; - assign switch_units__send__rdy[4] = output_units__recv__rdy[4]; - assign output_units__recv__val[4] = switch_units__send__val[4]; - assign send__msg[4] = output_units__send__msg[4]; - assign output_units__send__rdy[4] = send__rdy[4]; - assign send__val[4] = output_units__send__val[4]; - -endmodule - - -// PyMTL Component MeshNetworkRTL Definition -// Full name: MeshNetworkRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__ncols_2__nrows_2__chl_lat_1 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/MeshNetworkRTL.py - -module MeshNetworkRTL__4ca7f469967df194 -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:3] , - output logic [0:0] recv__rdy [0:3] , - input logic [0:0] recv__val [0:3] , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:3] , - input logic [0:0] send__rdy [0:3] , - output logic [0:0] send__val [0:3] -); - //------------------------------------------------------------- - // Component channels[0:7] - //------------------------------------------------------------- - - logic [0:0] channels__clk [0:7]; - logic [0:0] channels__reset [0:7]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d channels__recv__msg [0:7]; - logic [0:0] channels__recv__rdy [0:7]; - logic [0:0] channels__recv__val [0:7]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d channels__send__msg [0:7]; - logic [0:0] channels__send__rdy [0:7]; - logic [0:0] channels__send__val [0:7]; - - ChannelRTL__551ecec02ed96ac9 channels__0 - ( - .clk( channels__clk[0] ), - .reset( channels__reset[0] ), - .recv__msg( channels__recv__msg[0] ), - .recv__rdy( channels__recv__rdy[0] ), - .recv__val( channels__recv__val[0] ), - .send__msg( channels__send__msg[0] ), - .send__rdy( channels__send__rdy[0] ), - .send__val( channels__send__val[0] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__1 - ( - .clk( channels__clk[1] ), - .reset( channels__reset[1] ), - .recv__msg( channels__recv__msg[1] ), - .recv__rdy( channels__recv__rdy[1] ), - .recv__val( channels__recv__val[1] ), - .send__msg( channels__send__msg[1] ), - .send__rdy( channels__send__rdy[1] ), - .send__val( channels__send__val[1] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__2 - ( - .clk( channels__clk[2] ), - .reset( channels__reset[2] ), - .recv__msg( channels__recv__msg[2] ), - .recv__rdy( channels__recv__rdy[2] ), - .recv__val( channels__recv__val[2] ), - .send__msg( channels__send__msg[2] ), - .send__rdy( channels__send__rdy[2] ), - .send__val( channels__send__val[2] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__3 - ( - .clk( channels__clk[3] ), - .reset( channels__reset[3] ), - .recv__msg( channels__recv__msg[3] ), - .recv__rdy( channels__recv__rdy[3] ), - .recv__val( channels__recv__val[3] ), - .send__msg( channels__send__msg[3] ), - .send__rdy( channels__send__rdy[3] ), - .send__val( channels__send__val[3] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__4 - ( - .clk( channels__clk[4] ), - .reset( channels__reset[4] ), - .recv__msg( channels__recv__msg[4] ), - .recv__rdy( channels__recv__rdy[4] ), - .recv__val( channels__recv__val[4] ), - .send__msg( channels__send__msg[4] ), - .send__rdy( channels__send__rdy[4] ), - .send__val( channels__send__val[4] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__5 - ( - .clk( channels__clk[5] ), - .reset( channels__reset[5] ), - .recv__msg( channels__recv__msg[5] ), - .recv__rdy( channels__recv__rdy[5] ), - .recv__val( channels__recv__val[5] ), - .send__msg( channels__send__msg[5] ), - .send__rdy( channels__send__rdy[5] ), - .send__val( channels__send__val[5] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__6 - ( - .clk( channels__clk[6] ), - .reset( channels__reset[6] ), - .recv__msg( channels__recv__msg[6] ), - .recv__rdy( channels__recv__rdy[6] ), - .recv__val( channels__recv__val[6] ), - .send__msg( channels__send__msg[6] ), - .send__rdy( channels__send__rdy[6] ), - .send__val( channels__send__val[6] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__7 - ( - .clk( channels__clk[7] ), - .reset( channels__reset[7] ), - .recv__msg( channels__recv__msg[7] ), - .recv__rdy( channels__recv__rdy[7] ), - .recv__val( channels__recv__val[7] ), - .send__msg( channels__send__msg[7] ), - .send__rdy( channels__send__rdy[7] ), - .send__val( channels__send__val[7] ) - ); - - //------------------------------------------------------------- - // End of component channels[0:7] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component routers[0:3] - //------------------------------------------------------------- - - logic [0:0] routers__clk [0:3]; - MeshPosition_2x2__pos_x_1__pos_y_1 routers__pos [0:3]; - logic [0:0] routers__reset [0:3]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d routers__recv__msg [0:3][0:4]; - logic [0:0] routers__recv__rdy [0:3][0:4]; - logic [0:0] routers__recv__val [0:3][0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d routers__send__msg [0:3][0:4]; - logic [0:0] routers__send__rdy [0:3][0:4]; - logic [0:0] routers__send__val [0:3][0:4]; - - MeshRouterRTL__574f02d875fdbb92 routers__0 - ( - .clk( routers__clk[0] ), - .pos( routers__pos[0] ), - .reset( routers__reset[0] ), - .recv__msg( routers__recv__msg[0] ), - .recv__rdy( routers__recv__rdy[0] ), - .recv__val( routers__recv__val[0] ), - .send__msg( routers__send__msg[0] ), - .send__rdy( routers__send__rdy[0] ), - .send__val( routers__send__val[0] ) - ); - - MeshRouterRTL__574f02d875fdbb92 routers__1 - ( - .clk( routers__clk[1] ), - .pos( routers__pos[1] ), - .reset( routers__reset[1] ), - .recv__msg( routers__recv__msg[1] ), - .recv__rdy( routers__recv__rdy[1] ), - .recv__val( routers__recv__val[1] ), - .send__msg( routers__send__msg[1] ), - .send__rdy( routers__send__rdy[1] ), - .send__val( routers__send__val[1] ) - ); - - MeshRouterRTL__574f02d875fdbb92 routers__2 - ( - .clk( routers__clk[2] ), - .pos( routers__pos[2] ), - .reset( routers__reset[2] ), - .recv__msg( routers__recv__msg[2] ), - .recv__rdy( routers__recv__rdy[2] ), - .recv__val( routers__recv__val[2] ), - .send__msg( routers__send__msg[2] ), - .send__rdy( routers__send__rdy[2] ), - .send__val( routers__send__val[2] ) - ); - - MeshRouterRTL__574f02d875fdbb92 routers__3 - ( - .clk( routers__clk[3] ), - .pos( routers__pos[3] ), - .reset( routers__reset[3] ), - .recv__msg( routers__recv__msg[3] ), - .recv__rdy( routers__recv__rdy[3] ), - .recv__val( routers__recv__val[3] ), - .send__msg( routers__send__msg[3] ), - .send__rdy( routers__send__rdy[3] ), - .send__val( routers__send__val[3] ) - ); - - //------------------------------------------------------------- - // End of component routers[0:3] - //------------------------------------------------------------- - - assign routers__clk[0] = clk; - assign routers__reset[0] = reset; - assign routers__clk[1] = clk; - assign routers__reset[1] = reset; - assign routers__clk[2] = clk; - assign routers__reset[2] = reset; - assign routers__clk[3] = clk; - assign routers__reset[3] = reset; - assign channels__clk[0] = clk; - assign channels__reset[0] = reset; - assign channels__clk[1] = clk; - assign channels__reset[1] = reset; - assign channels__clk[2] = clk; - assign channels__reset[2] = reset; - assign channels__clk[3] = clk; - assign channels__reset[3] = reset; - assign channels__clk[4] = clk; - assign channels__reset[4] = reset; - assign channels__clk[5] = clk; - assign channels__reset[5] = reset; - assign channels__clk[6] = clk; - assign channels__reset[6] = reset; - assign channels__clk[7] = clk; - assign channels__reset[7] = reset; - assign routers__pos[0].pos_x = 1'd0; - assign routers__pos[0].pos_y = 1'd0; - assign routers__pos[1].pos_x = 1'd1; - assign routers__pos[1].pos_y = 1'd0; - assign routers__pos[2].pos_x = 1'd0; - assign routers__pos[2].pos_y = 1'd1; - assign routers__pos[3].pos_x = 1'd1; - assign routers__pos[3].pos_y = 1'd1; - assign channels__recv__msg[0] = routers__send__msg[0][0]; - assign routers__send__rdy[0][0] = channels__recv__rdy[0]; - assign channels__recv__val[0] = routers__send__val[0][0]; - assign routers__recv__msg[2][1] = channels__send__msg[0]; - assign channels__send__rdy[0] = routers__recv__rdy[2][1]; - assign routers__recv__val[2][1] = channels__send__val[0]; - assign channels__recv__msg[1] = routers__send__msg[0][3]; - assign routers__send__rdy[0][3] = channels__recv__rdy[1]; - assign channels__recv__val[1] = routers__send__val[0][3]; - assign routers__recv__msg[1][2] = channels__send__msg[1]; - assign channels__send__rdy[1] = routers__recv__rdy[1][2]; - assign routers__recv__val[1][2] = channels__send__val[1]; - assign routers__recv__msg[0][4] = recv__msg[0]; - assign recv__rdy[0] = routers__recv__rdy[0][4]; - assign routers__recv__val[0][4] = recv__val[0]; - assign send__msg[0] = routers__send__msg[0][4]; - assign routers__send__rdy[0][4] = send__rdy[0]; - assign send__val[0] = routers__send__val[0][4]; - assign routers__send__rdy[0][1] = 1'd0; - assign routers__recv__val[0][1] = 1'd0; - assign routers__recv__msg[0][1] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign routers__send__rdy[0][2] = 1'd0; - assign routers__recv__val[0][2] = 1'd0; - assign routers__recv__msg[0][2] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign channels__recv__msg[2] = routers__send__msg[1][0]; - assign routers__send__rdy[1][0] = channels__recv__rdy[2]; - assign channels__recv__val[2] = routers__send__val[1][0]; - assign routers__recv__msg[3][1] = channels__send__msg[2]; - assign channels__send__rdy[2] = routers__recv__rdy[3][1]; - assign routers__recv__val[3][1] = channels__send__val[2]; - assign channels__recv__msg[3] = routers__send__msg[1][2]; - assign routers__send__rdy[1][2] = channels__recv__rdy[3]; - assign channels__recv__val[3] = routers__send__val[1][2]; - assign routers__recv__msg[0][3] = channels__send__msg[3]; - assign channels__send__rdy[3] = routers__recv__rdy[0][3]; - assign routers__recv__val[0][3] = channels__send__val[3]; - assign routers__recv__msg[1][4] = recv__msg[1]; - assign recv__rdy[1] = routers__recv__rdy[1][4]; - assign routers__recv__val[1][4] = recv__val[1]; - assign send__msg[1] = routers__send__msg[1][4]; - assign routers__send__rdy[1][4] = send__rdy[1]; - assign send__val[1] = routers__send__val[1][4]; - assign routers__send__rdy[1][1] = 1'd0; - assign routers__recv__val[1][1] = 1'd0; - assign routers__recv__msg[1][1] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign routers__send__rdy[1][3] = 1'd0; - assign routers__recv__val[1][3] = 1'd0; - assign routers__recv__msg[1][3] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign channels__recv__msg[4] = routers__send__msg[2][1]; - assign routers__send__rdy[2][1] = channels__recv__rdy[4]; - assign channels__recv__val[4] = routers__send__val[2][1]; - assign routers__recv__msg[0][0] = channels__send__msg[4]; - assign channels__send__rdy[4] = routers__recv__rdy[0][0]; - assign routers__recv__val[0][0] = channels__send__val[4]; - assign channels__recv__msg[5] = routers__send__msg[2][3]; - assign routers__send__rdy[2][3] = channels__recv__rdy[5]; - assign channels__recv__val[5] = routers__send__val[2][3]; - assign routers__recv__msg[3][2] = channels__send__msg[5]; - assign channels__send__rdy[5] = routers__recv__rdy[3][2]; - assign routers__recv__val[3][2] = channels__send__val[5]; - assign routers__recv__msg[2][4] = recv__msg[2]; - assign recv__rdy[2] = routers__recv__rdy[2][4]; - assign routers__recv__val[2][4] = recv__val[2]; - assign send__msg[2] = routers__send__msg[2][4]; - assign routers__send__rdy[2][4] = send__rdy[2]; - assign send__val[2] = routers__send__val[2][4]; - assign routers__send__rdy[2][0] = 1'd0; - assign routers__recv__val[2][0] = 1'd0; - assign routers__recv__msg[2][0] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign routers__send__rdy[2][2] = 1'd0; - assign routers__recv__val[2][2] = 1'd0; - assign routers__recv__msg[2][2] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign channels__recv__msg[6] = routers__send__msg[3][1]; - assign routers__send__rdy[3][1] = channels__recv__rdy[6]; - assign channels__recv__val[6] = routers__send__val[3][1]; - assign routers__recv__msg[1][0] = channels__send__msg[6]; - assign channels__send__rdy[6] = routers__recv__rdy[1][0]; - assign routers__recv__val[1][0] = channels__send__val[6]; - assign channels__recv__msg[7] = routers__send__msg[3][2]; - assign routers__send__rdy[3][2] = channels__recv__rdy[7]; - assign channels__recv__val[7] = routers__send__val[3][2]; - assign routers__recv__msg[2][3] = channels__send__msg[7]; - assign channels__send__rdy[7] = routers__recv__rdy[2][3]; - assign routers__recv__val[2][3] = channels__send__val[7]; - assign routers__recv__msg[3][4] = recv__msg[3]; - assign recv__rdy[3] = routers__recv__rdy[3][4]; - assign routers__recv__val[3][4] = recv__val[3]; - assign send__msg[3] = routers__send__msg[3][4]; - assign routers__send__rdy[3][4] = send__rdy[3]; - assign send__val[3] = routers__send__val[3][4]; - assign routers__send__rdy[3][0] = 1'd0; - assign routers__recv__val[3][0] = 1'd0; - assign routers__recv__msg[3][0] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign routers__send__rdy[3][3] = 1'd0; - assign routers__recv__val[3][3] = 1'd0; - assign routers__recv__msg[3][3] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - -endmodule - - -// PyMTL Component MeshMultiCgraRTL Definition -// Full name: MeshMultiCgraRTL__CgraPayloadType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__cgra_rows_2__cgra_columns_2__tile_rows_4__tile_columns_4__ctrl_mem_size_16__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_registers_per_reg_bank_16__num_ctrl_4__total_steps_38__mem_access_is_combinational_True__FunctionUnit_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ]__per_cgra_topology_Mesh__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__support_task_switching_False -// At /home/ajokai/cgra/VectorCGRAfork0/multi_cgra/MeshMultiCgraRTL.py - -module MeshMultiCgraRTL__explicit_vector_global_reduce -( - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , - output logic [0:0] recv_from_cpu_pkt__rdy , - input logic [0:0] recv_from_cpu_pkt__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , - input logic [0:0] send_to_cpu_pkt__rdy , - output logic [0:0] send_to_cpu_pkt__val -); - //------------------------------------------------------------- - // Component cgra[0:3] - //------------------------------------------------------------- - - logic [6:0] cgra__address_lower [0:3]; - logic [6:0] cgra__address_upper [0:3]; - logic [1:0] cgra__cgra_id [0:3]; - logic [0:0] cgra__clk [0:3]; - logic [0:0] cgra__reset [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_east__msg [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_east__rdy [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_east__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_north__msg [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_north__rdy [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_north__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_south__msg [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_south__rdy [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_south__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_west__msg [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_west__rdy [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_west__val [0:3][0:3]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 cgra__recv_from_cpu_pkt__msg [0:3]; - logic [0:0] cgra__recv_from_cpu_pkt__rdy [0:3]; - logic [0:0] cgra__recv_from_cpu_pkt__val [0:3]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d cgra__recv_from_inter_cgra_noc__msg [0:3]; - logic [0:0] cgra__recv_from_inter_cgra_noc__rdy [0:3]; - logic [0:0] cgra__recv_from_inter_cgra_noc__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_east__msg [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_east__rdy [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_east__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_north__msg [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_north__rdy [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_north__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_south__msg [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_south__rdy [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_south__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_west__msg [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_west__rdy [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_west__val [0:3][0:3]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 cgra__send_to_cpu_pkt__msg [0:3]; - logic [0:0] cgra__send_to_cpu_pkt__rdy [0:3]; - logic [0:0] cgra__send_to_cpu_pkt__val [0:3]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d cgra__send_to_inter_cgra_noc__msg [0:3]; - logic [0:0] cgra__send_to_inter_cgra_noc__rdy [0:3]; - logic [0:0] cgra__send_to_inter_cgra_noc__val [0:3]; - - CgraRTL__72d915b46abe89cb cgra__0 - ( - .address_lower( cgra__address_lower[0] ), - .address_upper( cgra__address_upper[0] ), - .cgra_id( cgra__cgra_id[0] ), - .clk( cgra__clk[0] ), - .reset( cgra__reset[0] ), - .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[0] ), - .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[0] ), - .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[0] ), - .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[0] ), - .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[0] ), - .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[0] ), - .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[0] ), - .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[0] ), - .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[0] ), - .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[0] ), - .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[0] ), - .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[0] ), - .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[0] ), - .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[0] ), - .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[0] ), - .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[0] ), - .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[0] ), - .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[0] ), - .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[0] ), - .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[0] ), - .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[0] ), - .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[0] ), - .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[0] ), - .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[0] ), - .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[0] ), - .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[0] ), - .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[0] ), - .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[0] ), - .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[0] ), - .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[0] ), - .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[0] ), - .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[0] ), - .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[0] ), - .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[0] ), - .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[0] ), - .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[0] ) - ); - - CgraRTL__72d915b46abe89cb cgra__1 - ( - .address_lower( cgra__address_lower[1] ), - .address_upper( cgra__address_upper[1] ), - .cgra_id( cgra__cgra_id[1] ), - .clk( cgra__clk[1] ), - .reset( cgra__reset[1] ), - .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[1] ), - .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[1] ), - .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[1] ), - .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[1] ), - .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[1] ), - .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[1] ), - .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[1] ), - .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[1] ), - .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[1] ), - .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[1] ), - .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[1] ), - .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[1] ), - .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[1] ), - .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[1] ), - .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[1] ), - .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[1] ), - .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[1] ), - .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[1] ), - .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[1] ), - .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[1] ), - .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[1] ), - .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[1] ), - .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[1] ), - .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[1] ), - .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[1] ), - .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[1] ), - .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[1] ), - .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[1] ), - .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[1] ), - .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[1] ), - .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[1] ), - .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[1] ), - .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[1] ), - .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[1] ), - .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[1] ), - .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[1] ) - ); - - CgraRTL__72d915b46abe89cb cgra__2 - ( - .address_lower( cgra__address_lower[2] ), - .address_upper( cgra__address_upper[2] ), - .cgra_id( cgra__cgra_id[2] ), - .clk( cgra__clk[2] ), - .reset( cgra__reset[2] ), - .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[2] ), - .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[2] ), - .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[2] ), - .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[2] ), - .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[2] ), - .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[2] ), - .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[2] ), - .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[2] ), - .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[2] ), - .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[2] ), - .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[2] ), - .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[2] ), - .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[2] ), - .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[2] ), - .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[2] ), - .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[2] ), - .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[2] ), - .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[2] ), - .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[2] ), - .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[2] ), - .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[2] ), - .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[2] ), - .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[2] ), - .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[2] ), - .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[2] ), - .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[2] ), - .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[2] ), - .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[2] ), - .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[2] ), - .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[2] ), - .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[2] ), - .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[2] ), - .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[2] ), - .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[2] ), - .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[2] ), - .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[2] ) - ); - - CgraRTL__72d915b46abe89cb cgra__3 - ( - .address_lower( cgra__address_lower[3] ), - .address_upper( cgra__address_upper[3] ), - .cgra_id( cgra__cgra_id[3] ), - .clk( cgra__clk[3] ), - .reset( cgra__reset[3] ), - .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[3] ), - .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[3] ), - .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[3] ), - .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[3] ), - .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[3] ), - .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[3] ), - .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[3] ), - .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[3] ), - .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[3] ), - .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[3] ), - .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[3] ), - .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[3] ), - .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[3] ), - .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[3] ), - .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[3] ), - .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[3] ), - .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[3] ), - .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[3] ), - .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[3] ), - .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[3] ), - .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[3] ), - .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[3] ), - .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[3] ), - .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[3] ), - .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[3] ), - .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[3] ), - .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[3] ), - .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[3] ), - .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[3] ), - .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[3] ), - .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[3] ), - .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[3] ), - .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[3] ), - .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[3] ), - .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[3] ), - .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[3] ) - ); - - //------------------------------------------------------------- - // End of component cgra[0:3] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mesh - //------------------------------------------------------------- - - logic [0:0] mesh__clk; - logic [0:0] mesh__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mesh__recv__msg [0:3]; - logic [0:0] mesh__recv__rdy [0:3]; - logic [0:0] mesh__recv__val [0:3]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mesh__send__msg [0:3]; - logic [0:0] mesh__send__rdy [0:3]; - logic [0:0] mesh__send__val [0:3]; - - MeshNetworkRTL__4ca7f469967df194 mesh - ( - .clk( mesh__clk ), - .reset( mesh__reset ), - .recv__msg( mesh__recv__msg ), - .recv__rdy( mesh__recv__rdy ), - .recv__val( mesh__recv__val ), - .send__msg( mesh__send__msg ), - .send__rdy( mesh__send__rdy ), - .send__val( mesh__send__val ) - ); - - //------------------------------------------------------------- - // End of component mesh - //------------------------------------------------------------- - - assign cgra__clk[0] = clk; - assign cgra__reset[0] = reset; - assign cgra__clk[1] = clk; - assign cgra__reset[1] = reset; - assign cgra__clk[2] = clk; - assign cgra__reset[2] = reset; - assign cgra__clk[3] = clk; - assign cgra__reset[3] = reset; - assign mesh__clk = clk; - assign mesh__reset = reset; - assign cgra__recv_from_inter_cgra_noc__msg[0] = mesh__send__msg[0]; - assign mesh__send__rdy[0] = cgra__recv_from_inter_cgra_noc__rdy[0]; - assign cgra__recv_from_inter_cgra_noc__val[0] = mesh__send__val[0]; - assign mesh__recv__msg[0] = cgra__send_to_inter_cgra_noc__msg[0]; - assign cgra__send_to_inter_cgra_noc__rdy[0] = mesh__recv__rdy[0]; - assign mesh__recv__val[0] = cgra__send_to_inter_cgra_noc__val[0]; - assign cgra__recv_from_inter_cgra_noc__msg[1] = mesh__send__msg[1]; - assign mesh__send__rdy[1] = cgra__recv_from_inter_cgra_noc__rdy[1]; - assign cgra__recv_from_inter_cgra_noc__val[1] = mesh__send__val[1]; - assign mesh__recv__msg[1] = cgra__send_to_inter_cgra_noc__msg[1]; - assign cgra__send_to_inter_cgra_noc__rdy[1] = mesh__recv__rdy[1]; - assign mesh__recv__val[1] = cgra__send_to_inter_cgra_noc__val[1]; - assign cgra__recv_from_inter_cgra_noc__msg[2] = mesh__send__msg[2]; - assign mesh__send__rdy[2] = cgra__recv_from_inter_cgra_noc__rdy[2]; - assign cgra__recv_from_inter_cgra_noc__val[2] = mesh__send__val[2]; - assign mesh__recv__msg[2] = cgra__send_to_inter_cgra_noc__msg[2]; - assign cgra__send_to_inter_cgra_noc__rdy[2] = mesh__recv__rdy[2]; - assign mesh__recv__val[2] = cgra__send_to_inter_cgra_noc__val[2]; - assign cgra__recv_from_inter_cgra_noc__msg[3] = mesh__send__msg[3]; - assign mesh__send__rdy[3] = cgra__recv_from_inter_cgra_noc__rdy[3]; - assign cgra__recv_from_inter_cgra_noc__val[3] = mesh__send__val[3]; - assign mesh__recv__msg[3] = cgra__send_to_inter_cgra_noc__msg[3]; - assign cgra__send_to_inter_cgra_noc__rdy[3] = mesh__recv__rdy[3]; - assign mesh__recv__val[3] = cgra__send_to_inter_cgra_noc__val[3]; - assign cgra__cgra_id[0] = 2'd0; - assign cgra__cgra_id[1] = 2'd1; - assign cgra__cgra_id[2] = 2'd2; - assign cgra__cgra_id[3] = 2'd3; - assign cgra__address_lower[0] = 7'd0; - assign cgra__address_upper[0] = 7'd31; - assign cgra__address_lower[1] = 7'd32; - assign cgra__address_upper[1] = 7'd63; - assign cgra__address_lower[2] = 7'd64; - assign cgra__address_upper[2] = 7'd95; - assign cgra__address_lower[3] = 7'd96; - assign cgra__address_upper[3] = 7'd127; - assign cgra__recv_from_cpu_pkt__msg[0] = recv_from_cpu_pkt__msg; - assign recv_from_cpu_pkt__rdy = cgra__recv_from_cpu_pkt__rdy[0]; - assign cgra__recv_from_cpu_pkt__val[0] = recv_from_cpu_pkt__val; - assign send_to_cpu_pkt__msg = cgra__send_to_cpu_pkt__msg[0]; - assign cgra__send_to_cpu_pkt__rdy[0] = send_to_cpu_pkt__rdy; - assign send_to_cpu_pkt__val = cgra__send_to_cpu_pkt__val[0]; - assign cgra__recv_from_cpu_pkt__val[1] = 1'd0; - assign cgra__recv_from_cpu_pkt__msg[1] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign cgra__send_to_cpu_pkt__rdy[1] = 1'd0; - assign cgra__recv_from_cpu_pkt__val[2] = 1'd0; - assign cgra__recv_from_cpu_pkt__msg[2] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign cgra__send_to_cpu_pkt__rdy[2] = 1'd0; - assign cgra__recv_from_cpu_pkt__val[3] = 1'd0; - assign cgra__recv_from_cpu_pkt__msg[3] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign cgra__send_to_cpu_pkt__rdy[3] = 1'd0; - assign cgra__send_data_on_boundary_south__rdy[0][0] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[0][0] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[0][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[0][1] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[0][1] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[0][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[0][2] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[0][2] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[0][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[0][3] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[0][3] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[0][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[0][0] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[0][0] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[0][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[0][1] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[0][1] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[0][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[0][2] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[0][2] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[0][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[0][3] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[0][3] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[0][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[1][0] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[1][0] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[1][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[1][1] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[1][1] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[1][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[1][2] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[1][2] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[1][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[1][3] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[1][3] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[1][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__recv_data_on_boundary_east__msg[0][0] = cgra__send_data_on_boundary_west__msg[1][0]; - assign cgra__send_data_on_boundary_west__rdy[1][0] = cgra__recv_data_on_boundary_east__rdy[0][0]; - assign cgra__recv_data_on_boundary_east__val[0][0] = cgra__send_data_on_boundary_west__val[1][0]; - assign cgra__recv_data_on_boundary_west__msg[1][0] = cgra__send_data_on_boundary_east__msg[0][0]; - assign cgra__send_data_on_boundary_east__rdy[0][0] = cgra__recv_data_on_boundary_west__rdy[1][0]; - assign cgra__recv_data_on_boundary_west__val[1][0] = cgra__send_data_on_boundary_east__val[0][0]; - assign cgra__recv_data_on_boundary_east__msg[0][1] = cgra__send_data_on_boundary_west__msg[1][1]; - assign cgra__send_data_on_boundary_west__rdy[1][1] = cgra__recv_data_on_boundary_east__rdy[0][1]; - assign cgra__recv_data_on_boundary_east__val[0][1] = cgra__send_data_on_boundary_west__val[1][1]; - assign cgra__recv_data_on_boundary_west__msg[1][1] = cgra__send_data_on_boundary_east__msg[0][1]; - assign cgra__send_data_on_boundary_east__rdy[0][1] = cgra__recv_data_on_boundary_west__rdy[1][1]; - assign cgra__recv_data_on_boundary_west__val[1][1] = cgra__send_data_on_boundary_east__val[0][1]; - assign cgra__recv_data_on_boundary_east__msg[0][2] = cgra__send_data_on_boundary_west__msg[1][2]; - assign cgra__send_data_on_boundary_west__rdy[1][2] = cgra__recv_data_on_boundary_east__rdy[0][2]; - assign cgra__recv_data_on_boundary_east__val[0][2] = cgra__send_data_on_boundary_west__val[1][2]; - assign cgra__recv_data_on_boundary_west__msg[1][2] = cgra__send_data_on_boundary_east__msg[0][2]; - assign cgra__send_data_on_boundary_east__rdy[0][2] = cgra__recv_data_on_boundary_west__rdy[1][2]; - assign cgra__recv_data_on_boundary_west__val[1][2] = cgra__send_data_on_boundary_east__val[0][2]; - assign cgra__recv_data_on_boundary_east__msg[0][3] = cgra__send_data_on_boundary_west__msg[1][3]; - assign cgra__send_data_on_boundary_west__rdy[1][3] = cgra__recv_data_on_boundary_east__rdy[0][3]; - assign cgra__recv_data_on_boundary_east__val[0][3] = cgra__send_data_on_boundary_west__val[1][3]; - assign cgra__recv_data_on_boundary_west__msg[1][3] = cgra__send_data_on_boundary_east__msg[0][3]; - assign cgra__send_data_on_boundary_east__rdy[0][3] = cgra__recv_data_on_boundary_west__rdy[1][3]; - assign cgra__recv_data_on_boundary_west__val[1][3] = cgra__send_data_on_boundary_east__val[0][3]; - assign cgra__send_data_on_boundary_east__rdy[1][0] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[1][0] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[1][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[1][1] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[1][1] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[1][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[1][2] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[1][2] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[1][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[1][3] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[1][3] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[1][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__recv_data_on_boundary_north__msg[0][0] = cgra__send_data_on_boundary_south__msg[2][0]; - assign cgra__send_data_on_boundary_south__rdy[2][0] = cgra__recv_data_on_boundary_north__rdy[0][0]; - assign cgra__recv_data_on_boundary_north__val[0][0] = cgra__send_data_on_boundary_south__val[2][0]; - assign cgra__recv_data_on_boundary_south__msg[2][0] = cgra__send_data_on_boundary_north__msg[0][0]; - assign cgra__send_data_on_boundary_north__rdy[0][0] = cgra__recv_data_on_boundary_south__rdy[2][0]; - assign cgra__recv_data_on_boundary_south__val[2][0] = cgra__send_data_on_boundary_north__val[0][0]; - assign cgra__recv_data_on_boundary_north__msg[0][1] = cgra__send_data_on_boundary_south__msg[2][1]; - assign cgra__send_data_on_boundary_south__rdy[2][1] = cgra__recv_data_on_boundary_north__rdy[0][1]; - assign cgra__recv_data_on_boundary_north__val[0][1] = cgra__send_data_on_boundary_south__val[2][1]; - assign cgra__recv_data_on_boundary_south__msg[2][1] = cgra__send_data_on_boundary_north__msg[0][1]; - assign cgra__send_data_on_boundary_north__rdy[0][1] = cgra__recv_data_on_boundary_south__rdy[2][1]; - assign cgra__recv_data_on_boundary_south__val[2][1] = cgra__send_data_on_boundary_north__val[0][1]; - assign cgra__recv_data_on_boundary_north__msg[0][2] = cgra__send_data_on_boundary_south__msg[2][2]; - assign cgra__send_data_on_boundary_south__rdy[2][2] = cgra__recv_data_on_boundary_north__rdy[0][2]; - assign cgra__recv_data_on_boundary_north__val[0][2] = cgra__send_data_on_boundary_south__val[2][2]; - assign cgra__recv_data_on_boundary_south__msg[2][2] = cgra__send_data_on_boundary_north__msg[0][2]; - assign cgra__send_data_on_boundary_north__rdy[0][2] = cgra__recv_data_on_boundary_south__rdy[2][2]; - assign cgra__recv_data_on_boundary_south__val[2][2] = cgra__send_data_on_boundary_north__val[0][2]; - assign cgra__recv_data_on_boundary_north__msg[0][3] = cgra__send_data_on_boundary_south__msg[2][3]; - assign cgra__send_data_on_boundary_south__rdy[2][3] = cgra__recv_data_on_boundary_north__rdy[0][3]; - assign cgra__recv_data_on_boundary_north__val[0][3] = cgra__send_data_on_boundary_south__val[2][3]; - assign cgra__recv_data_on_boundary_south__msg[2][3] = cgra__send_data_on_boundary_north__msg[0][3]; - assign cgra__send_data_on_boundary_north__rdy[0][3] = cgra__recv_data_on_boundary_south__rdy[2][3]; - assign cgra__recv_data_on_boundary_south__val[2][3] = cgra__send_data_on_boundary_north__val[0][3]; - assign cgra__send_data_on_boundary_north__rdy[2][0] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[2][0] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[2][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[2][1] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[2][1] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[2][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[2][2] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[2][2] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[2][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[2][3] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[2][3] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[2][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[2][0] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[2][0] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[2][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[2][1] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[2][1] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[2][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[2][2] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[2][2] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[2][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[2][3] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[2][3] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[2][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__recv_data_on_boundary_north__msg[1][0] = cgra__send_data_on_boundary_south__msg[3][0]; - assign cgra__send_data_on_boundary_south__rdy[3][0] = cgra__recv_data_on_boundary_north__rdy[1][0]; - assign cgra__recv_data_on_boundary_north__val[1][0] = cgra__send_data_on_boundary_south__val[3][0]; - assign cgra__recv_data_on_boundary_south__msg[3][0] = cgra__send_data_on_boundary_north__msg[1][0]; - assign cgra__send_data_on_boundary_north__rdy[1][0] = cgra__recv_data_on_boundary_south__rdy[3][0]; - assign cgra__recv_data_on_boundary_south__val[3][0] = cgra__send_data_on_boundary_north__val[1][0]; - assign cgra__recv_data_on_boundary_north__msg[1][1] = cgra__send_data_on_boundary_south__msg[3][1]; - assign cgra__send_data_on_boundary_south__rdy[3][1] = cgra__recv_data_on_boundary_north__rdy[1][1]; - assign cgra__recv_data_on_boundary_north__val[1][1] = cgra__send_data_on_boundary_south__val[3][1]; - assign cgra__recv_data_on_boundary_south__msg[3][1] = cgra__send_data_on_boundary_north__msg[1][1]; - assign cgra__send_data_on_boundary_north__rdy[1][1] = cgra__recv_data_on_boundary_south__rdy[3][1]; - assign cgra__recv_data_on_boundary_south__val[3][1] = cgra__send_data_on_boundary_north__val[1][1]; - assign cgra__recv_data_on_boundary_north__msg[1][2] = cgra__send_data_on_boundary_south__msg[3][2]; - assign cgra__send_data_on_boundary_south__rdy[3][2] = cgra__recv_data_on_boundary_north__rdy[1][2]; - assign cgra__recv_data_on_boundary_north__val[1][2] = cgra__send_data_on_boundary_south__val[3][2]; - assign cgra__recv_data_on_boundary_south__msg[3][2] = cgra__send_data_on_boundary_north__msg[1][2]; - assign cgra__send_data_on_boundary_north__rdy[1][2] = cgra__recv_data_on_boundary_south__rdy[3][2]; - assign cgra__recv_data_on_boundary_south__val[3][2] = cgra__send_data_on_boundary_north__val[1][2]; - assign cgra__recv_data_on_boundary_north__msg[1][3] = cgra__send_data_on_boundary_south__msg[3][3]; - assign cgra__send_data_on_boundary_south__rdy[3][3] = cgra__recv_data_on_boundary_north__rdy[1][3]; - assign cgra__recv_data_on_boundary_north__val[1][3] = cgra__send_data_on_boundary_south__val[3][3]; - assign cgra__recv_data_on_boundary_south__msg[3][3] = cgra__send_data_on_boundary_north__msg[1][3]; - assign cgra__send_data_on_boundary_north__rdy[1][3] = cgra__recv_data_on_boundary_south__rdy[3][3]; - assign cgra__recv_data_on_boundary_south__val[3][3] = cgra__send_data_on_boundary_north__val[1][3]; - assign cgra__send_data_on_boundary_north__rdy[3][0] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[3][0] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[3][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[3][1] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[3][1] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[3][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[3][2] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[3][2] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[3][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[3][3] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[3][3] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[3][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__recv_data_on_boundary_east__msg[2][0] = cgra__send_data_on_boundary_west__msg[3][0]; - assign cgra__send_data_on_boundary_west__rdy[3][0] = cgra__recv_data_on_boundary_east__rdy[2][0]; - assign cgra__recv_data_on_boundary_east__val[2][0] = cgra__send_data_on_boundary_west__val[3][0]; - assign cgra__recv_data_on_boundary_west__msg[3][0] = cgra__send_data_on_boundary_east__msg[2][0]; - assign cgra__send_data_on_boundary_east__rdy[2][0] = cgra__recv_data_on_boundary_west__rdy[3][0]; - assign cgra__recv_data_on_boundary_west__val[3][0] = cgra__send_data_on_boundary_east__val[2][0]; - assign cgra__recv_data_on_boundary_east__msg[2][1] = cgra__send_data_on_boundary_west__msg[3][1]; - assign cgra__send_data_on_boundary_west__rdy[3][1] = cgra__recv_data_on_boundary_east__rdy[2][1]; - assign cgra__recv_data_on_boundary_east__val[2][1] = cgra__send_data_on_boundary_west__val[3][1]; - assign cgra__recv_data_on_boundary_west__msg[3][1] = cgra__send_data_on_boundary_east__msg[2][1]; - assign cgra__send_data_on_boundary_east__rdy[2][1] = cgra__recv_data_on_boundary_west__rdy[3][1]; - assign cgra__recv_data_on_boundary_west__val[3][1] = cgra__send_data_on_boundary_east__val[2][1]; - assign cgra__recv_data_on_boundary_east__msg[2][2] = cgra__send_data_on_boundary_west__msg[3][2]; - assign cgra__send_data_on_boundary_west__rdy[3][2] = cgra__recv_data_on_boundary_east__rdy[2][2]; - assign cgra__recv_data_on_boundary_east__val[2][2] = cgra__send_data_on_boundary_west__val[3][2]; - assign cgra__recv_data_on_boundary_west__msg[3][2] = cgra__send_data_on_boundary_east__msg[2][2]; - assign cgra__send_data_on_boundary_east__rdy[2][2] = cgra__recv_data_on_boundary_west__rdy[3][2]; - assign cgra__recv_data_on_boundary_west__val[3][2] = cgra__send_data_on_boundary_east__val[2][2]; - assign cgra__recv_data_on_boundary_east__msg[2][3] = cgra__send_data_on_boundary_west__msg[3][3]; - assign cgra__send_data_on_boundary_west__rdy[3][3] = cgra__recv_data_on_boundary_east__rdy[2][3]; - assign cgra__recv_data_on_boundary_east__val[2][3] = cgra__send_data_on_boundary_west__val[3][3]; - assign cgra__recv_data_on_boundary_west__msg[3][3] = cgra__send_data_on_boundary_east__msg[2][3]; - assign cgra__send_data_on_boundary_east__rdy[2][3] = cgra__recv_data_on_boundary_west__rdy[3][3]; - assign cgra__recv_data_on_boundary_west__val[3][3] = cgra__send_data_on_boundary_east__val[2][3]; - assign cgra__send_data_on_boundary_east__rdy[3][0] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[3][0] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[3][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[3][1] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[3][1] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[3][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[3][2] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[3][2] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[3][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[3][3] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[3][3] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[3][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - -endmodule From 8a4b346b46290ab16220a77bbb30149ef39fe686 Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Tue, 6 Jan 2026 16:32:18 -0600 Subject: [PATCH 11/12] Revert "[PyMTL SV tb] Remove x-chk fail." This reverts commit 730cb5eb0e42362feeb778c9b2cdaad0b64a5d34. --- ...1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v index 4216cc64..3abd9dd5 100644 --- a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v +++ b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v @@ -27,7 +27,7 @@ cycle_count += 1; \ $fatal; -`define CHECK2(lineno, out, ref, port_name) \ +`define CHECK(lineno, out, ref, port_name) \ if ((|(out ^ out)) == 1'b0) ; \ else begin \ $display(""); \ @@ -42,13 +42,6 @@ `VTB_TEST_FAIL(lineno, out, ref, port_name) \ end -`define CHECK(lineno, out, ref, port_name) \ - if (out != ref) begin \ - $display(""); \ - $display("The test bench received an incorrect value!"); \ - `VTB_TEST_FAIL(lineno, out, ref, port_name) \ - end - module MeshMultiCgraRTL__975ce70dc1a0740a_tb; // convention logic clk; From 7eeb4a1ef72c511e6ddf24d177a0a604dfd040dd Mon Sep 17 00:00:00 2001 From: Ron Jokai Date: Tue, 6 Jan 2026 16:32:34 -0600 Subject: [PATCH 12/12] Revert "[PyMTL output] Adding generated RTL and tb files." This reverts commit 54356c473e96a476844d3f823c5e3e77a0d996a4. --- ...hMultiCgraRTL__975ce70dc1a0740a__pickled.v | 23492 ---------------- ...t_multi_CGRA_fir_vector_global_reduce_tb.v | 138 - ...i_CGRA_fir_vector_global_reduce_tb.v.cases | 201 - 3 files changed, 23831 deletions(-) delete mode 100644 multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a__pickled.v delete mode 100644 multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v delete mode 100644 multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v.cases diff --git a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a__pickled.v b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a__pickled.v deleted file mode 100644 index aea6ccbe..00000000 --- a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a__pickled.v +++ /dev/null @@ -1,23492 +0,0 @@ -//------------------------------------------------------------------------- -// MeshMultiCgraRTL__975ce70dc1a0740a.v -//------------------------------------------------------------------------- -// This file is generated by PyMTL SystemVerilog translation pass. - -// PyMTL BitStruct CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Definition -typedef struct packed { - logic [63:0] payload; - logic [0:0] predicate; - logic [0:0] bypass; - logic [0:0] delay; -} CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1; - -// PyMTL BitStruct CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Definition -typedef struct packed { - logic [6:0] operation; - logic [3:0][2:0] fu_in; - logic [7:0][2:0] routing_xbar_outport; - logic [7:0][1:0] fu_xbar_outport; - logic [2:0] vector_factor_power; - logic [0:0] is_last_ctrl; - logic [3:0][1:0] write_reg_from; - logic [3:0][3:0] write_reg_idx; - logic [3:0][0:0] read_reg_from; - logic [3:0][3:0] read_reg_idx; -} CGRAConfig_7_4_2_4_4_3__49d22cda396bec88; - -// PyMTL BitStruct MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Definition -typedef struct packed { - logic [4:0] cmd; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; - logic [6:0] data_addr; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 ctrl; - logic [3:0] ctrl_addr; -} MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a; - -// PyMTL BitStruct InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d Definition -typedef struct packed { - logic [1:0] src; - logic [1:0] dst; - logic [0:0] src_x; - logic [0:0] src_y; - logic [0:0] dst_x; - logic [0:0] dst_y; - logic [4:0] src_tile_id; - logic [4:0] dst_tile_id; - logic [2:0] remote_src_port; - logic [7:0] opaque; - logic [1:0] vc_id; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a payload; -} InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d; - -// PyMTL BitStruct IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 Definition -typedef struct packed { - logic [4:0] src; - logic [4:0] dst; - logic [1:0] src_cgra_id; - logic [1:0] dst_cgra_id; - logic [0:0] src_cgra_x; - logic [0:0] src_cgra_y; - logic [0:0] dst_cgra_x; - logic [0:0] dst_cgra_y; - logic [7:0] opaque; - logic [0:0] vc_id; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a payload; -} IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69; - -// PyMTL BitStruct ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad Definition -typedef struct packed { - logic [0:0] dst; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d inter_cgra_pkt; -} ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad; - -// PyMTL BitStruct MemAccessPacket_8_3_128__43c148781d2f2a57 Definition -typedef struct packed { - logic [2:0] src; - logic [1:0] dst; - logic [6:0] addr; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; - logic [1:0] src_cgra; - logic [4:0] src_tile; - logic [2:0] remote_src_port; - logic [0:0] streaming_rd; - logic [6:0] streaming_rd_stride; - logic [6:0] streaming_rd_end_addr; -} MemAccessPacket_8_3_128__43c148781d2f2a57; - -// PyMTL BitStruct MemAccessPacket_3_8_128__9f21b0bcdad2c061 Definition -typedef struct packed { - logic [1:0] src; - logic [2:0] dst; - logic [6:0] addr; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data; - logic [1:0] src_cgra; - logic [4:0] src_tile; - logic [2:0] remote_src_port; - logic [0:0] streaming_rd; - logic [6:0] streaming_rd_stride; - logic [6:0] streaming_rd_end_addr; -} MemAccessPacket_3_8_128__9f21b0bcdad2c061; - -// PyMTL BitStruct MeshPosition_2x2__pos_x_1__pos_y_1 Definition -typedef struct packed { - logic [0:0] pos_x; - logic [0:0] pos_y; -} MeshPosition_2x2__pos_x_1__pos_y_1; - -// PyMTL Component NormalQueueCtrlRTL Definition -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueCtrlRTL__num_entries_2 -( - input logic [0:0] clk , - output logic [1:0] count , - output logic [0:0] raddr , - output logic [0:0] recv_rdy , - input logic [0:0] recv_val , - input logic [0:0] reset , - input logic [0:0] send_rdy , - output logic [0:0] send_val , - output logic [0:0] waddr , - output logic [0:0] wen -); - localparam logic [1:0] __const__num_entries_at__lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy = 2'd2; - localparam logic [1:0] __const__num_entries_at_up_reg = 2'd2; - logic [0:0] head; - logic [0:0] recv_xfer; - logic [0:0] send_xfer; - logic [0:0] tail; - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:121 - // s.recv_rdy //= lambda: s.count < num_entries - - always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy - recv_rdy = count < 2'( __const__num_entries_at__lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_rdy ); - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:124 - // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy - - always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_recv_xfer - recv_xfer = recv_val & recv_rdy; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:122 - // s.send_val //= lambda: s.count > 0 - - always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_send_val - send_val = count > 2'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:125 - // s.send_xfer //= lambda: s.send_val & s.send_rdy - - always_comb begin : _lambda__s_dut_cgra_0__controller_crossbar_input_units_0__queue_ctrl_send_xfer - send_xfer = send_val & send_rdy; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:127 - // @update_ff - // def up_reg(): - // - // if s.reset: - // s.head <<= 0 - // s.tail <<= 0 - // s.count <<= 0 - // - // else: - // if s.recv_xfer: - // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 - // - // if s.send_xfer: - // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 - // - // if s.recv_xfer & ~s.send_xfer: - // s.count <<= s.count + 1 - // elif ~s.recv_xfer & s.send_xfer: - // s.count <<= s.count - 1 - - always_ff @(posedge clk) begin : up_reg - if ( reset ) begin - head <= 1'd0; - tail <= 1'd0; - count <= 2'd0; - end - else begin - if ( recv_xfer ) begin - tail <= ( tail < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? tail + 1'd1 : 1'd0; - end - if ( send_xfer ) begin - head <= ( head < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? head + 1'd1 : 1'd0; - end - if ( recv_xfer & ( ~send_xfer ) ) begin - count <= count + 2'd1; - end - else if ( ( ~recv_xfer ) & send_xfer ) begin - count <= count - 2'd1; - end - end - end - - assign wen = recv_xfer; - assign waddr = tail; - assign raddr = head; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__a60a466e6e87778c -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__b5f6715511792c61 -( - input logic [0:0] clk , - input logic [0:0] raddr , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv_msg , - input logic [0:0] reset , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__a60a466e6e87778c rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__b5f6715511792c61 -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__raddr; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad dpath__recv_msg; - logic [0:0] dpath__reset; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__b5f6715511792c61 dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component InputUnitRTL Definition -// Full name: InputUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__QueueType_NormalQueueRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py - -module InputUnitRTL__d71c3d07db1f649e -( - input logic [0:0] clk , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queue - //------------------------------------------------------------- - - logic [0:0] queue__clk; - logic [1:0] queue__count; - logic [0:0] queue__reset; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad queue__recv__msg; - logic [0:0] queue__recv__rdy; - logic [0:0] queue__recv__val; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad queue__send__msg; - logic [0:0] queue__send__rdy; - logic [0:0] queue__send__val; - - NormalQueueRTL__b5f6715511792c61 queue - ( - .clk( queue__clk ), - .count( queue__count ), - .reset( queue__reset ), - .recv__msg( queue__recv__msg ), - .recv__rdy( queue__recv__rdy ), - .recv__val( queue__recv__val ), - .send__msg( queue__send__msg ), - .send__rdy( queue__send__rdy ), - .send__val( queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component queue - //------------------------------------------------------------- - - assign queue__clk = clk; - assign queue__reset = reset; - assign queue__recv__msg = recv__msg; - assign recv__rdy = queue__recv__rdy; - assign queue__recv__val = recv__val; - assign send__msg = queue__send__msg; - assign queue__send__rdy = send__rdy; - assign send__val = queue__send__val; - -endmodule - - -// PyMTL Component OutputUnitRTL Definition -// Full name: OutputUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__QueueType_None -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py - -module OutputUnitRTL__c199f9a52ff41678 -( - input logic [0:0] clk , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - assign send__msg = recv__msg; - assign recv__rdy = send__rdy; - assign send__val = recv__val; - -endmodule - - -// PyMTL Component XbarRouteUnitRTL Definition -// Full name: XbarRouteUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_outports_1 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py - -module XbarRouteUnitRTL__2110ed3935ab4c25 -( - input logic [0:0] clk , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg [0:0] , - input logic [0:0] send__rdy [0:0] , - output logic [0:0] send__val [0:0] -); - localparam logic [0:0] __const__num_outports_at_up_ru_routing = 1'd1; - logic [0:0] out_dir; - logic [0:0] send_val; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 - // @update - // def up_ru_recv_rdy(): - // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 - - always_comb begin : up_ru_recv_rdy - recv__rdy = send__rdy[out_dir] > 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 - // @update - // def up_ru_routing(): - // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) - // - // for i in range( num_outports ): - // s.send[i].val @= b1(0) - // - // if s.recv.val: - // s.send[ s.out_dir ].val @= b1(1) - - always_comb begin : up_ru_routing - out_dir = recv__msg.dst; - for ( int unsigned i = 1'd0; i < 1'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) - send__val[1'(i)] = 1'd0; - if ( recv__val ) begin - send__val[out_dir] = 1'd1; - end - end - - assign send__msg[0] = recv__msg; - assign send_val[0:0] = send__val[0]; - -endmodule - - -// PyMTL Component RegEnRst Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py - -module RegEnRst__Type_Bits6__reset_value_1 -( - input logic [0:0] clk , - input logic [0:0] en , - input logic [5:0] in_ , - output logic [5:0] out , - input logic [0:0] reset -); - localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 - // @update_ff - // def up_regenrst(): - // if s.reset: s.out <<= reset_value - // elif s.en: s.out <<= s.in_ - - always_ff @(posedge clk) begin : up_regenrst - if ( reset ) begin - out <= 6'( __const__reset_value_at_up_regenrst ); - end - else if ( en ) begin - out <= in_; - end - end - -endmodule - - -// PyMTL Component RoundRobinArbiterEn Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py - -module RoundRobinArbiterEn__nreqs_6 -( - input logic [0:0] clk , - input logic [0:0] en , - output logic [5:0] grants , - input logic [5:0] reqs , - input logic [0:0] reset -); - localparam logic [2:0] __const__nreqs_at_comb_reqs_int = 3'd6; - localparam logic [3:0] __const__nreqsX2_at_comb_reqs_int = 4'd12; - localparam logic [2:0] __const__nreqs_at_comb_grants = 3'd6; - localparam logic [2:0] __const__nreqs_at_comb_priority_int = 3'd6; - localparam logic [3:0] __const__nreqsX2_at_comb_priority_int = 4'd12; - localparam logic [3:0] __const__nreqsX2_at_comb_kills = 4'd12; - localparam logic [3:0] __const__nreqsX2_at_comb_grants_int = 4'd12; - logic [11:0] grants_int; - logic [12:0] kills; - logic [0:0] priority_en; - logic [11:0] priority_int; - logic [11:0] reqs_int; - //------------------------------------------------------------- - // Component priority_reg - //------------------------------------------------------------- - - logic [0:0] priority_reg__clk; - logic [0:0] priority_reg__en; - logic [5:0] priority_reg__in_; - logic [5:0] priority_reg__out; - logic [0:0] priority_reg__reset; - - RegEnRst__Type_Bits6__reset_value_1 priority_reg - ( - .clk( priority_reg__clk ), - .en( priority_reg__en ), - .in_( priority_reg__in_ ), - .out( priority_reg__out ), - .reset( priority_reg__reset ) - ); - - //------------------------------------------------------------- - // End of component priority_reg - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 - // @update - // def comb_grants(): - // for i in range( nreqs ): - // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] - - always_comb begin : comb_grants - for ( int unsigned i = 1'd0; i < 3'( __const__nreqs_at_comb_grants ); i += 1'd1 ) - grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 - // @update - // def comb_grants_int(): - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.grants_int[i] @= s.reqs_int[i] - // else: - // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] - - always_comb begin : comb_grants_int - for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - grants_int[4'(i)] = reqs_int[4'(i)]; - end - else - grants_int[4'(i)] = ( ~kills[4'(i)] ) & reqs_int[4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 - // @update - // def comb_kills(): - // s.kills[0] @= 1 - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.kills[i+1] @= s.reqs_int[i] - // else: - // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) - - always_comb begin : comb_kills - kills[4'd0] = 1'd1; - for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - kills[4'(i) + 4'd1] = reqs_int[4'(i)]; - end - else - kills[4'(i) + 4'd1] = kills[4'(i)] | ( ( ~kills[4'(i)] ) & reqs_int[4'(i)] ); - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 - // @update - // def comb_priority_en(): - // s.priority_en @= ( s.grants != 0 ) & s.en - - always_comb begin : comb_priority_en - priority_en = ( grants != 6'd0 ) & en; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 - // @update - // def comb_priority_int(): - // s.priority_int[ 0:nreqs ] @= s.priority_reg.out - // s.priority_int[nreqs:nreqsX2] @= 0 - - always_comb begin : comb_priority_int - priority_int[4'd5:4'd0] = priority_reg__out; - priority_int[4'd11:4'( __const__nreqs_at_comb_priority_int )] = 6'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 - // @update - // def comb_reqs_int(): - // s.reqs_int [ 0:nreqs ] @= s.reqs - // s.reqs_int [nreqs:nreqsX2] @= s.reqs - - always_comb begin : comb_reqs_int - reqs_int[4'd5:4'd0] = reqs; - reqs_int[4'd11:4'( __const__nreqs_at_comb_reqs_int )] = reqs; - end - - assign priority_reg__clk = clk; - assign priority_reg__reset = reset; - assign priority_reg__en = priority_en; - assign priority_reg__in_[5:1] = grants[4:0]; - assign priority_reg__in_[0:0] = grants[5:5]; - -endmodule - - -// PyMTL Component Encoder Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py - -module Encoder__in_nbits_6__out_nbits_3 -( - input logic [0:0] clk , - input logic [5:0] in_ , - output logic [2:0] out , - input logic [0:0] reset -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 - // @update - // def encode(): - // s.out @= 0 - // for i in range( s.in_nbits ): - // if s.in_[i]: - // s.out @= i - - always_comb begin : encode - out = 3'd0; - for ( int unsigned i = 1'd0; i < 3'd6; i += 1'd1 ) - if ( in_[3'(i)] ) begin - out = 3'(i); - end - end - -endmodule - - -// PyMTL Component Mux Definition -// Full name: Mux__Type_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__ninputs_6 -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__899292f481a8b227 -( - input logic [0:0] clk , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad in_ [0:5], - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad out , - input logic [0:0] reset , - input logic [2:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component SwitchUnitRTL Definition -// Full name: SwitchUnitRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_inports_6 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py - -module SwitchUnitRTL__2dc7ee83ee1f485f -( - input logic [0:0] clk , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg [0:5] , - output logic [0:0] recv__rdy [0:5] , - input logic [0:0] recv__val [0:5] , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd6; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [5:0] arbiter__grants; - logic [5:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_6 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [5:0] encoder__in_; - logic [2:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_6__out_nbits_3 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad mux__in_ [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad mux__out; - logic [0:0] mux__reset; - logic [2:0] mux__sel; - - Mux__899292f481a8b227 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 - // @update - // def up_get_en(): - // for i in range( num_inports ): - // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) - - always_comb begin : up_get_en - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) - recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 - // @update - // def up_send_val(): - // s.send.val @= s.arbiter.grants > 0 - - always_comb begin : up_send_val - send__val = arbiter__grants > 6'd0; - end - - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign arbiter__en = 1'd1; - assign mux__clk = clk; - assign mux__reset = reset; - assign send__msg = mux__out; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign encoder__in_ = arbiter__grants; - assign mux__sel = encoder__out; - assign arbiter__reqs[0:0] = recv__val[0]; - assign mux__in_[0] = recv__msg[0]; - assign arbiter__reqs[1:1] = recv__val[1]; - assign mux__in_[1] = recv__msg[1]; - assign arbiter__reqs[2:2] = recv__val[2]; - assign mux__in_[2] = recv__msg[2]; - assign arbiter__reqs[3:3] = recv__val[3]; - assign mux__in_[3] = recv__msg[3]; - assign arbiter__reqs[4:4] = recv__val[4]; - assign mux__in_[4] = recv__msg[4]; - assign arbiter__reqs[5:5] = recv__val[5]; - assign mux__in_[5] = recv__msg[5]; - -endmodule - - -// PyMTL Component XbarRTL Definition -// Full name: XbarRTL__PacketType_ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad__num_inports_6__num_outports_1__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRTL.py - -module XbarRTL__51e7846dd37f4a41 -( - input logic [0:0] clk , - input logic [0:0] reset , - input ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad recv__msg [0:5] , - output logic [0:0] recv__rdy [0:5] , - input logic [0:0] recv__val [0:5] , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg [0:0] , - input logic [0:0] send__rdy [0:0] , - output logic [0:0] send__val [0:0] -); - //------------------------------------------------------------- - // Component input_units[0:5] - //------------------------------------------------------------- - - logic [0:0] input_units__clk [0:5]; - logic [0:0] input_units__reset [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad input_units__recv__msg [0:5]; - logic [0:0] input_units__recv__rdy [0:5]; - logic [0:0] input_units__recv__val [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad input_units__send__msg [0:5]; - logic [0:0] input_units__send__rdy [0:5]; - logic [0:0] input_units__send__val [0:5]; - - InputUnitRTL__d71c3d07db1f649e input_units__0 - ( - .clk( input_units__clk[0] ), - .reset( input_units__reset[0] ), - .recv__msg( input_units__recv__msg[0] ), - .recv__rdy( input_units__recv__rdy[0] ), - .recv__val( input_units__recv__val[0] ), - .send__msg( input_units__send__msg[0] ), - .send__rdy( input_units__send__rdy[0] ), - .send__val( input_units__send__val[0] ) - ); - - InputUnitRTL__d71c3d07db1f649e input_units__1 - ( - .clk( input_units__clk[1] ), - .reset( input_units__reset[1] ), - .recv__msg( input_units__recv__msg[1] ), - .recv__rdy( input_units__recv__rdy[1] ), - .recv__val( input_units__recv__val[1] ), - .send__msg( input_units__send__msg[1] ), - .send__rdy( input_units__send__rdy[1] ), - .send__val( input_units__send__val[1] ) - ); - - InputUnitRTL__d71c3d07db1f649e input_units__2 - ( - .clk( input_units__clk[2] ), - .reset( input_units__reset[2] ), - .recv__msg( input_units__recv__msg[2] ), - .recv__rdy( input_units__recv__rdy[2] ), - .recv__val( input_units__recv__val[2] ), - .send__msg( input_units__send__msg[2] ), - .send__rdy( input_units__send__rdy[2] ), - .send__val( input_units__send__val[2] ) - ); - - InputUnitRTL__d71c3d07db1f649e input_units__3 - ( - .clk( input_units__clk[3] ), - .reset( input_units__reset[3] ), - .recv__msg( input_units__recv__msg[3] ), - .recv__rdy( input_units__recv__rdy[3] ), - .recv__val( input_units__recv__val[3] ), - .send__msg( input_units__send__msg[3] ), - .send__rdy( input_units__send__rdy[3] ), - .send__val( input_units__send__val[3] ) - ); - - InputUnitRTL__d71c3d07db1f649e input_units__4 - ( - .clk( input_units__clk[4] ), - .reset( input_units__reset[4] ), - .recv__msg( input_units__recv__msg[4] ), - .recv__rdy( input_units__recv__rdy[4] ), - .recv__val( input_units__recv__val[4] ), - .send__msg( input_units__send__msg[4] ), - .send__rdy( input_units__send__rdy[4] ), - .send__val( input_units__send__val[4] ) - ); - - InputUnitRTL__d71c3d07db1f649e input_units__5 - ( - .clk( input_units__clk[5] ), - .reset( input_units__reset[5] ), - .recv__msg( input_units__recv__msg[5] ), - .recv__rdy( input_units__recv__rdy[5] ), - .recv__val( input_units__recv__val[5] ), - .send__msg( input_units__send__msg[5] ), - .send__rdy( input_units__send__rdy[5] ), - .send__val( input_units__send__val[5] ) - ); - - //------------------------------------------------------------- - // End of component input_units[0:5] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component output_units[0:0] - //------------------------------------------------------------- - - logic [0:0] output_units__clk [0:0]; - logic [0:0] output_units__reset [0:0]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad output_units__recv__msg [0:0]; - logic [0:0] output_units__recv__rdy [0:0]; - logic [0:0] output_units__recv__val [0:0]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad output_units__send__msg [0:0]; - logic [0:0] output_units__send__rdy [0:0]; - logic [0:0] output_units__send__val [0:0]; - - OutputUnitRTL__c199f9a52ff41678 output_units__0 - ( - .clk( output_units__clk[0] ), - .reset( output_units__reset[0] ), - .recv__msg( output_units__recv__msg[0] ), - .recv__rdy( output_units__recv__rdy[0] ), - .recv__val( output_units__recv__val[0] ), - .send__msg( output_units__send__msg[0] ), - .send__rdy( output_units__send__rdy[0] ), - .send__val( output_units__send__val[0] ) - ); - - //------------------------------------------------------------- - // End of component output_units[0:0] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component route_units[0:5] - //------------------------------------------------------------- - - logic [0:0] route_units__clk [0:5]; - logic [0:0] route_units__reset [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad route_units__recv__msg [0:5]; - logic [0:0] route_units__recv__rdy [0:5]; - logic [0:0] route_units__recv__val [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad route_units__send__msg [0:5][0:0]; - logic [0:0] route_units__send__rdy [0:5][0:0]; - logic [0:0] route_units__send__val [0:5][0:0]; - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__0 - ( - .clk( route_units__clk[0] ), - .reset( route_units__reset[0] ), - .recv__msg( route_units__recv__msg[0] ), - .recv__rdy( route_units__recv__rdy[0] ), - .recv__val( route_units__recv__val[0] ), - .send__msg( route_units__send__msg[0] ), - .send__rdy( route_units__send__rdy[0] ), - .send__val( route_units__send__val[0] ) - ); - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__1 - ( - .clk( route_units__clk[1] ), - .reset( route_units__reset[1] ), - .recv__msg( route_units__recv__msg[1] ), - .recv__rdy( route_units__recv__rdy[1] ), - .recv__val( route_units__recv__val[1] ), - .send__msg( route_units__send__msg[1] ), - .send__rdy( route_units__send__rdy[1] ), - .send__val( route_units__send__val[1] ) - ); - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__2 - ( - .clk( route_units__clk[2] ), - .reset( route_units__reset[2] ), - .recv__msg( route_units__recv__msg[2] ), - .recv__rdy( route_units__recv__rdy[2] ), - .recv__val( route_units__recv__val[2] ), - .send__msg( route_units__send__msg[2] ), - .send__rdy( route_units__send__rdy[2] ), - .send__val( route_units__send__val[2] ) - ); - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__3 - ( - .clk( route_units__clk[3] ), - .reset( route_units__reset[3] ), - .recv__msg( route_units__recv__msg[3] ), - .recv__rdy( route_units__recv__rdy[3] ), - .recv__val( route_units__recv__val[3] ), - .send__msg( route_units__send__msg[3] ), - .send__rdy( route_units__send__rdy[3] ), - .send__val( route_units__send__val[3] ) - ); - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__4 - ( - .clk( route_units__clk[4] ), - .reset( route_units__reset[4] ), - .recv__msg( route_units__recv__msg[4] ), - .recv__rdy( route_units__recv__rdy[4] ), - .recv__val( route_units__recv__val[4] ), - .send__msg( route_units__send__msg[4] ), - .send__rdy( route_units__send__rdy[4] ), - .send__val( route_units__send__val[4] ) - ); - - XbarRouteUnitRTL__2110ed3935ab4c25 route_units__5 - ( - .clk( route_units__clk[5] ), - .reset( route_units__reset[5] ), - .recv__msg( route_units__recv__msg[5] ), - .recv__rdy( route_units__recv__rdy[5] ), - .recv__val( route_units__recv__val[5] ), - .send__msg( route_units__send__msg[5] ), - .send__rdy( route_units__send__rdy[5] ), - .send__val( route_units__send__val[5] ) - ); - - //------------------------------------------------------------- - // End of component route_units[0:5] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component switch_units[0:0] - //------------------------------------------------------------- - - logic [0:0] switch_units__clk [0:0]; - logic [0:0] switch_units__reset [0:0]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad switch_units__recv__msg [0:0][0:5]; - logic [0:0] switch_units__recv__rdy [0:0][0:5]; - logic [0:0] switch_units__recv__val [0:0][0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad switch_units__send__msg [0:0]; - logic [0:0] switch_units__send__rdy [0:0]; - logic [0:0] switch_units__send__val [0:0]; - - SwitchUnitRTL__2dc7ee83ee1f485f switch_units__0 - ( - .clk( switch_units__clk[0] ), - .reset( switch_units__reset[0] ), - .recv__msg( switch_units__recv__msg[0] ), - .recv__rdy( switch_units__recv__rdy[0] ), - .recv__val( switch_units__recv__val[0] ), - .send__msg( switch_units__send__msg[0] ), - .send__rdy( switch_units__send__rdy[0] ), - .send__val( switch_units__send__val[0] ) - ); - - //------------------------------------------------------------- - // End of component switch_units[0:0] - //------------------------------------------------------------- - - assign input_units__clk[0] = clk; - assign input_units__reset[0] = reset; - assign input_units__clk[1] = clk; - assign input_units__reset[1] = reset; - assign input_units__clk[2] = clk; - assign input_units__reset[2] = reset; - assign input_units__clk[3] = clk; - assign input_units__reset[3] = reset; - assign input_units__clk[4] = clk; - assign input_units__reset[4] = reset; - assign input_units__clk[5] = clk; - assign input_units__reset[5] = reset; - assign route_units__clk[0] = clk; - assign route_units__reset[0] = reset; - assign route_units__clk[1] = clk; - assign route_units__reset[1] = reset; - assign route_units__clk[2] = clk; - assign route_units__reset[2] = reset; - assign route_units__clk[3] = clk; - assign route_units__reset[3] = reset; - assign route_units__clk[4] = clk; - assign route_units__reset[4] = reset; - assign route_units__clk[5] = clk; - assign route_units__reset[5] = reset; - assign switch_units__clk[0] = clk; - assign switch_units__reset[0] = reset; - assign output_units__clk[0] = clk; - assign output_units__reset[0] = reset; - assign input_units__recv__msg[0] = recv__msg[0]; - assign recv__rdy[0] = input_units__recv__rdy[0]; - assign input_units__recv__val[0] = recv__val[0]; - assign route_units__recv__msg[0] = input_units__send__msg[0]; - assign input_units__send__rdy[0] = route_units__recv__rdy[0]; - assign route_units__recv__val[0] = input_units__send__val[0]; - assign input_units__recv__msg[1] = recv__msg[1]; - assign recv__rdy[1] = input_units__recv__rdy[1]; - assign input_units__recv__val[1] = recv__val[1]; - assign route_units__recv__msg[1] = input_units__send__msg[1]; - assign input_units__send__rdy[1] = route_units__recv__rdy[1]; - assign route_units__recv__val[1] = input_units__send__val[1]; - assign input_units__recv__msg[2] = recv__msg[2]; - assign recv__rdy[2] = input_units__recv__rdy[2]; - assign input_units__recv__val[2] = recv__val[2]; - assign route_units__recv__msg[2] = input_units__send__msg[2]; - assign input_units__send__rdy[2] = route_units__recv__rdy[2]; - assign route_units__recv__val[2] = input_units__send__val[2]; - assign input_units__recv__msg[3] = recv__msg[3]; - assign recv__rdy[3] = input_units__recv__rdy[3]; - assign input_units__recv__val[3] = recv__val[3]; - assign route_units__recv__msg[3] = input_units__send__msg[3]; - assign input_units__send__rdy[3] = route_units__recv__rdy[3]; - assign route_units__recv__val[3] = input_units__send__val[3]; - assign input_units__recv__msg[4] = recv__msg[4]; - assign recv__rdy[4] = input_units__recv__rdy[4]; - assign input_units__recv__val[4] = recv__val[4]; - assign route_units__recv__msg[4] = input_units__send__msg[4]; - assign input_units__send__rdy[4] = route_units__recv__rdy[4]; - assign route_units__recv__val[4] = input_units__send__val[4]; - assign input_units__recv__msg[5] = recv__msg[5]; - assign recv__rdy[5] = input_units__recv__rdy[5]; - assign input_units__recv__val[5] = recv__val[5]; - assign route_units__recv__msg[5] = input_units__send__msg[5]; - assign input_units__send__rdy[5] = route_units__recv__rdy[5]; - assign route_units__recv__val[5] = input_units__send__val[5]; - assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; - assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; - assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; - assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; - assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; - assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; - assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; - assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; - assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; - assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; - assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; - assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; - assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; - assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; - assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; - assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; - assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; - assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; - assign output_units__recv__msg[0] = switch_units__send__msg[0]; - assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; - assign output_units__recv__val[0] = switch_units__send__val[0]; - assign send__msg[0] = output_units__send__msg[0]; - assign output_units__send__rdy[0] = send__rdy[0]; - assign send__val[0] = output_units__send__val[0]; - -endmodule - - -// PyMTL Component NormalQueueCtrlRTL Definition -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueCtrlRTL__num_entries_16 -( - input logic [0:0] clk , - output logic [4:0] count , - output logic [3:0] raddr , - output logic [0:0] recv_rdy , - input logic [0:0] recv_val , - input logic [0:0] reset , - input logic [0:0] send_rdy , - output logic [0:0] send_val , - output logic [3:0] waddr , - output logic [0:0] wen -); - localparam logic [4:0] __const__num_entries_at__lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy = 5'd16; - localparam logic [4:0] __const__num_entries_at_up_reg = 5'd16; - logic [3:0] head; - logic [0:0] recv_xfer; - logic [0:0] send_xfer; - logic [3:0] tail; - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:121 - // s.recv_rdy //= lambda: s.count < num_entries - - always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy - recv_rdy = count < 5'( __const__num_entries_at__lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_rdy ); - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:124 - // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy - - always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_recv_xfer - recv_xfer = recv_val & recv_rdy; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:122 - // s.send_val //= lambda: s.count > 0 - - always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_send_val - send_val = count > 5'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:125 - // s.send_xfer //= lambda: s.send_val & s.send_rdy - - always_comb begin : _lambda__s_dut_cgra_0__controller_global_reduce_unit_queue_ctrl_send_xfer - send_xfer = send_val & send_rdy; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:127 - // @update_ff - // def up_reg(): - // - // if s.reset: - // s.head <<= 0 - // s.tail <<= 0 - // s.count <<= 0 - // - // else: - // if s.recv_xfer: - // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 - // - // if s.send_xfer: - // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 - // - // if s.recv_xfer & ~s.send_xfer: - // s.count <<= s.count + 1 - // elif ~s.recv_xfer & s.send_xfer: - // s.count <<= s.count - 1 - - always_ff @(posedge clk) begin : up_reg - if ( reset ) begin - head <= 4'd0; - tail <= 4'd0; - count <= 5'd0; - end - else begin - if ( recv_xfer ) begin - tail <= ( tail < ( 4'( __const__num_entries_at_up_reg ) - 4'd1 ) ) ? tail + 4'd1 : 4'd0; - end - if ( send_xfer ) begin - head <= ( head < ( 4'( __const__num_entries_at_up_reg ) - 4'd1 ) ) ? head + 4'd1 : 4'd0; - end - if ( recv_xfer & ( ~send_xfer ) ) begin - count <= count + 5'd1; - end - else if ( ( ~recv_xfer ) & send_xfer ) begin - count <= count - 5'd1; - end - end - end - - assign wen = recv_xfer; - assign waddr = tail; - assign raddr = head; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__nregs_16__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__769ad531033521b3 -( - input logic [0:0] clk , - input logic [3:0] raddr [0:0], - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rdata [0:0], - input logic [0:0] reset , - input logic [3:0] waddr [0:0], - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d regs [0:15]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_16 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__a1611e9294891a09 -( - input logic [0:0] clk , - input logic [3:0] raddr , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_msg , - input logic [0:0] reset , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_msg , - input logic [3:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [3:0] rf__raddr [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [3:0] rf__waddr [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__769ad531033521b3 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_16 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__a1611e9294891a09 -( - input logic [0:0] clk , - output logic [4:0] count , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [4:0] ctrl__count; - logic [3:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [3:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_16 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [3:0] dpath__raddr; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__recv_msg; - logic [0:0] dpath__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__send_msg; - logic [3:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__a1611e9294891a09 dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component GlobalReduceUnitRTL Definition -// Full name: GlobalReduceUnitRTL__InterCgraPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d -// At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py - -module GlobalReduceUnitRTL__7c4d8effbf794a25 -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_count__msg , - output logic [0:0] recv_count__rdy , - input logic [0:0] recv_count__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_data__msg , - output logic [0:0] recv_data__rdy , - input logic [0:0] recv_data__val , - output ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL = 5'd19; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 receiving_count; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reduce_add_value; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reduce_mul_value; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 sending_count; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 target_count; - //------------------------------------------------------------- - // Component queue - //------------------------------------------------------------- - - logic [0:0] queue__clk; - logic [4:0] queue__count; - logic [0:0] queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__recv__msg; - logic [0:0] queue__recv__rdy; - logic [0:0] queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__send__msg; - logic [0:0] queue__send__rdy; - logic [0:0] queue__send__val; - - NormalQueueRTL__a1611e9294891a09 queue - ( - .clk( queue__clk ), - .count( queue__count ), - .reset( queue__reset ), - .recv__msg( queue__recv__msg ), - .recv__rdy( queue__recv__rdy ), - .recv__val( queue__recv__val ), - .send__msg( queue__send__msg ), - .send__rdy( queue__send__rdy ), - .send__val( queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component queue - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:45 - // @update - // def set_recv_rdy(): - // s.recv_data.rdy @= 0 - // s.queue.recv.val @= 0 - // s.queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // if s.target_count.payload > s.receiving_count.payload: - // s.recv_data.rdy @= s.queue.recv.rdy - // s.queue.recv.msg @= s.recv_data.msg - // s.queue.recv.val @= s.recv_data.val - - always_comb begin : set_recv_rdy - recv_data__rdy = 1'd0; - queue__recv__val = 1'd0; - queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - if ( target_count.payload > receiving_count.payload ) begin - recv_data__rdy = queue__recv__rdy; - queue__recv__msg = recv_data__msg; - queue__recv__val = recv_data__val; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:74 - // @update - // def update_send(): - // s.send.msg @= ControllerXbarPktType(0, 0) - // s.send.val @= 0 - // s.queue.send.rdy @= 0 - // if (s.target_count.payload > 0) & (s.receiving_count.payload == s.target_count.payload): - // # Updates the cmd type, result value, and src/dst. - // if s.queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: - // s.send.msg.inter_cgra_pkt.payload.cmd @= CMD_GLOBAL_REDUCE_ADD_RESPONSE - // s.send.msg.inter_cgra_pkt.payload.data @= s.reduce_add_value - // elif s.queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL: - // s.send.msg.inter_cgra_pkt.payload.cmd @= CMD_GLOBAL_REDUCE_MUL_RESPONSE - // s.send.msg.inter_cgra_pkt.payload.data @= s.reduce_mul_value - // s.send.msg.inter_cgra_pkt.src @= s.queue.send.msg.dst - // s.send.msg.inter_cgra_pkt.dst @= s.queue.send.msg.src - // s.send.msg.inter_cgra_pkt.src_x @= s.queue.send.msg.dst_x - // s.send.msg.inter_cgra_pkt.src_y @= s.queue.send.msg.dst_y - // s.send.msg.inter_cgra_pkt.dst_x @= s.queue.send.msg.src_x - // s.send.msg.inter_cgra_pkt.dst_y @= s.queue.send.msg.src_y - // s.send.msg.inter_cgra_pkt.src_tile_id @= s.queue.send.msg.dst_tile_id - // s.send.msg.inter_cgra_pkt.dst_tile_id @= s.queue.send.msg.src_tile_id - // s.queue.send.rdy @= s.send.rdy - // s.send.val @= s.queue.send.val - - always_comb begin : update_send - send__msg = { 1'd0, 221'd0 }; - send__val = 1'd0; - queue__send__rdy = 1'd0; - if ( ( target_count.payload > 64'd0 ) & ( receiving_count.payload == target_count.payload ) ) begin - if ( queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin - send__msg.inter_cgra_pkt.payload.cmd = 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ); - send__msg.inter_cgra_pkt.payload.data = reduce_add_value; - end - else if ( queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL ) ) begin - send__msg.inter_cgra_pkt.payload.cmd = 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ); - send__msg.inter_cgra_pkt.payload.data = reduce_mul_value; - end - send__msg.inter_cgra_pkt.src = queue__send__msg.dst; - send__msg.inter_cgra_pkt.dst = queue__send__msg.src; - send__msg.inter_cgra_pkt.src_x = queue__send__msg.dst_x; - send__msg.inter_cgra_pkt.src_y = queue__send__msg.dst_y; - send__msg.inter_cgra_pkt.dst_x = queue__send__msg.src_x; - send__msg.inter_cgra_pkt.dst_y = queue__send__msg.src_y; - send__msg.inter_cgra_pkt.src_tile_id = queue__send__msg.dst_tile_id; - send__msg.inter_cgra_pkt.dst_tile_id = queue__send__msg.src_tile_id; - queue__send__rdy = send__rdy; - send__val = queue__send__val; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:98 - // @update_ff - // def accumulate_value(): - // if s.reset | (s.sending_count == s.target_count): - // s.reduce_add_value <<= DataType(0, 0, 0, 0) - // s.reduce_mul_value <<= DataType(1, 0, 0, 0) - // else: - // if s.recv_data.val & \ - // s.recv_data.rdy: - // if s.recv_data.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: - // s.reduce_add_value <<= DataType(s.reduce_add_value.payload + s.recv_data.msg.payload.data.payload, - // s.recv_data.msg.payload.data.predicate, - // 0, - // 0) - // elif s.recv_data.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL: - // s.reduce_mul_value <<= DataType(s.reduce_mul_value.payload * s.recv_data.msg.payload.data.payload, - // s.recv_data.msg.payload.data.predicate, - // 0, - // 0) - - always_ff @(posedge clk) begin : accumulate_value - if ( reset | ( sending_count == target_count ) ) begin - reduce_add_value <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - reduce_mul_value <= { 64'd1, 1'd0, 1'd0, 1'd0 }; - end - else if ( recv_data__val & recv_data__rdy ) begin - if ( recv_data__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin - reduce_add_value <= { reduce_add_value.payload + recv_data__msg.payload.data.payload, recv_data__msg.payload.data.predicate, 1'd0, 1'd0 }; - end - else if ( recv_data__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL ) ) begin - reduce_mul_value <= { reduce_mul_value.payload * recv_data__msg.payload.data.payload, recv_data__msg.payload.data.predicate, 1'd0, 1'd0 }; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/GlobalReduceUnitRTL.py:55 - // @update_ff - // def update_count(): - // if s.reset: - // s.target_count <<= DataType(0, 0, 0, 0) - // s.receiving_count <<= DataType(0, 0, 0, 0) - // s.sending_count <<= DataType(0, 0, 0, 0) - // else: - // if s.recv_count.val & s.recv_count.rdy: - // s.target_count <<= DataType(s.recv_count.msg.payload.data.payload, 0, 0, 0) - // if s.recv_data.val & s.recv_data.rdy: - // s.receiving_count <<= DataType(s.receiving_count.payload + 1, 0, 0, 0) - // if s.send.rdy & s.send.val: - // s.sending_count <<= DataType(s.sending_count.payload + 1, 0, 0, 0) - // elif (s.sending_count == s.receiving_count) & \ - // (s.sending_count == s.target_count) & \ - // (s.target_count.payload > 0): - // s.sending_count <<= DataType(0, 0, 0, 0) - // s.receiving_count <<= DataType(0, 0, 0, 0) - - always_ff @(posedge clk) begin : update_count - if ( reset ) begin - target_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - receiving_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - sending_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - else begin - if ( recv_count__val & recv_count__rdy ) begin - target_count <= { recv_count__msg.payload.data.payload, 1'd0, 1'd0, 1'd0 }; - end - if ( recv_data__val & recv_data__rdy ) begin - receiving_count <= { receiving_count.payload + 64'd1, 1'd0, 1'd0, 1'd0 }; - end - if ( send__rdy & send__val ) begin - sending_count <= { sending_count.payload + 64'd1, 1'd0, 1'd0, 1'd0 }; - end - else if ( ( ( sending_count == receiving_count ) & ( sending_count == target_count ) ) & ( target_count.payload > 64'd0 ) ) begin - sending_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - receiving_count <= { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - end - end - - assign queue__clk = clk; - assign queue__reset = reset; - assign recv_count__rdy = 1'd1; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__80167091524f71e4 -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__a1c7a5a18a302c36 -( - input logic [0:0] clk , - input logic [0:0] raddr , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_msg , - input logic [0:0] reset , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__80167091524f71e4 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__a1c7a5a18a302c36 -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__raddr; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__recv_msg; - logic [0:0] dpath__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__a1c7a5a18a302c36 dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__96d83eaf701da4cb -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__c7280ffb0786127e -( - input logic [0:0] clk , - input logic [0:0] raddr , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_msg , - input logic [0:0] reset , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__96d83eaf701da4cb rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__c7280ffb0786127e -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__raddr; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__recv_msg; - logic [0:0] dpath__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__c7280ffb0786127e dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component ChannelRTL Definition -// Full name: ChannelRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_NormalQueueRTL__latency_1 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py - -module ChannelRTL__551ecec02ed96ac9 -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queues[0:0] - //------------------------------------------------------------- - - logic [0:0] queues__clk [0:0]; - logic [1:0] queues__count [0:0]; - logic [0:0] queues__reset [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queues__recv__msg [0:0]; - logic [0:0] queues__recv__rdy [0:0]; - logic [0:0] queues__recv__val [0:0]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queues__send__msg [0:0]; - logic [0:0] queues__send__rdy [0:0]; - logic [0:0] queues__send__val [0:0]; - - NormalQueueRTL__c7280ffb0786127e queues__0 - ( - .clk( queues__clk[0] ), - .count( queues__count[0] ), - .reset( queues__reset[0] ), - .recv__msg( queues__recv__msg[0] ), - .recv__rdy( queues__recv__rdy[0] ), - .recv__val( queues__recv__val[0] ), - .send__msg( queues__send__msg[0] ), - .send__rdy( queues__send__rdy[0] ), - .send__val( queues__send__val[0] ) - ); - - //------------------------------------------------------------- - // End of component queues[0:0] - //------------------------------------------------------------- - - assign queues__clk[0] = clk; - assign queues__reset[0] = reset; - assign queues__recv__msg[0] = recv__msg; - assign recv__rdy = queues__recv__rdy[0]; - assign queues__recv__val[0] = recv__val; - assign send__msg = queues__send__msg[0]; - assign queues__send__rdy[0] = send__rdy; - assign send__val = queues__send__val[0]; - -endmodule - - -// PyMTL Component ControllerRTL Definition -// Full name: ControllerRTL__InterCgraPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__multi_cgra_rows_2__multi_cgra_columns_2__num_tiles_16__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)} -// At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py - -module ControllerRTL__e06602ce343fdc8d -( - input logic [1:0] cgra_id , - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , - output logic [0:0] recv_from_cpu_pkt__rdy , - input logic [0:0] recv_from_cpu_pkt__val , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_ctrl_ring_pkt__msg , - output logic [0:0] recv_from_ctrl_ring_pkt__rdy , - input logic [0:0] recv_from_ctrl_ring_pkt__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_inter_cgra_noc__msg , - output logic [0:0] recv_from_inter_cgra_noc__rdy , - input logic [0:0] recv_from_inter_cgra_noc__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt__msg , - output logic [0:0] recv_from_tile_load_request_pkt__rdy , - input logic [0:0] recv_from_tile_load_request_pkt__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt__msg , - output logic [0:0] recv_from_tile_load_response_pkt__rdy , - input logic [0:0] recv_from_tile_load_response_pkt__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt__msg , - output logic [0:0] recv_from_tile_store_request_pkt__rdy , - input logic [0:0] recv_from_tile_store_request_pkt__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , - input logic [0:0] send_to_cpu_pkt__rdy , - output logic [0:0] send_to_cpu_pkt__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_ctrl_ring_pkt__msg , - input logic [0:0] send_to_ctrl_ring_pkt__rdy , - output logic [0:0] send_to_ctrl_ring_pkt__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_inter_cgra_noc__msg , - input logic [0:0] send_to_inter_cgra_noc__rdy , - output logic [0:0] send_to_inter_cgra_noc__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request__msg , - input logic [0:0] send_to_mem_load_request__rdy , - output logic [0:0] send_to_mem_load_request__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request__msg , - input logic [0:0] send_to_mem_store_request__rdy , - output logic [0:0] send_to_mem_store_request__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response__msg , - input logic [0:0] send_to_tile_load_response__rdy , - output logic [0:0] send_to_tile_load_response__val -); - localparam logic [2:0] __const__CONTROLLER_CROSSBAR_INPORTS = 3'd6; - localparam logic [4:0] __const__num_tiles_at_update_received_msg = 5'd16; - localparam logic [3:0] __const__CMD_LOAD_REQUEST = 4'd10; - localparam logic [3:0] __const__CMD_STORE_REQUEST = 4'd12; - localparam logic [3:0] __const__CMD_LOAD_RESPONSE = 4'd11; - localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_COUNT = 5'd17; - localparam logic [1:0] __const__CMD_CONFIG = 2'd3; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; - localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; - localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; - localparam logic [3:0] __const__CMD_CONFIG_CTRL_LOWER_BOUND = 4'd9; - localparam logic [3:0] __const__CMD_CONST = 4'd13; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; - localparam logic [0:0] __const__CMD_PAUSE = 1'd1; - localparam logic [4:0] __const__CMD_PRESERVE = 5'd22; - localparam logic [3:0] __const__CMD_RESUME = 4'd15; - localparam logic [4:0] __const__CMD_RECORD_PHI_ADDR = 5'd16; - localparam logic [1:0] __const__CMD_TERMINATE = 2'd2; - localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; - localparam logic [2:0] __const__addr_offset_nbits_at_capture_addr_dst_id = 3'd5; - logic [1:0] addr2controller_lut [0:3]; - logic [1:0] addr_dst_id; - logic [0:0] idTo2d_x_lut [0:3]; - logic [0:0] idTo2d_y_lut [0:3]; - //------------------------------------------------------------- - // Component crossbar - //------------------------------------------------------------- - - logic [0:0] crossbar__clk; - logic [0:0] crossbar__reset; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad crossbar__recv__msg [0:5]; - logic [0:0] crossbar__recv__rdy [0:5]; - logic [0:0] crossbar__recv__val [0:5]; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad crossbar__send__msg [0:0]; - logic [0:0] crossbar__send__rdy [0:0]; - logic [0:0] crossbar__send__val [0:0]; - - XbarRTL__51e7846dd37f4a41 crossbar - ( - .clk( crossbar__clk ), - .reset( crossbar__reset ), - .recv__msg( crossbar__recv__msg ), - .recv__rdy( crossbar__recv__rdy ), - .recv__val( crossbar__recv__val ), - .send__msg( crossbar__send__msg ), - .send__rdy( crossbar__send__rdy ), - .send__val( crossbar__send__val ) - ); - - //------------------------------------------------------------- - // End of component crossbar - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component global_reduce_unit - //------------------------------------------------------------- - - logic [0:0] global_reduce_unit__clk; - logic [0:0] global_reduce_unit__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d global_reduce_unit__recv_count__msg; - logic [0:0] global_reduce_unit__recv_count__rdy; - logic [0:0] global_reduce_unit__recv_count__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d global_reduce_unit__recv_data__msg; - logic [0:0] global_reduce_unit__recv_data__rdy; - logic [0:0] global_reduce_unit__recv_data__val; - ControllerNocXbarPacket_InterCgraPktType__b413f2c5b5afa0ad global_reduce_unit__send__msg; - logic [0:0] global_reduce_unit__send__rdy; - logic [0:0] global_reduce_unit__send__val; - - GlobalReduceUnitRTL__7c4d8effbf794a25 global_reduce_unit - ( - .clk( global_reduce_unit__clk ), - .reset( global_reduce_unit__reset ), - .recv_count__msg( global_reduce_unit__recv_count__msg ), - .recv_count__rdy( global_reduce_unit__recv_count__rdy ), - .recv_count__val( global_reduce_unit__recv_count__val ), - .recv_data__msg( global_reduce_unit__recv_data__msg ), - .recv_data__rdy( global_reduce_unit__recv_data__rdy ), - .recv_data__val( global_reduce_unit__recv_data__val ), - .send__msg( global_reduce_unit__send__msg ), - .send__rdy( global_reduce_unit__send__rdy ), - .send__val( global_reduce_unit__send__val ) - ); - - //------------------------------------------------------------- - // End of component global_reduce_unit - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component recv_from_cpu_pkt_queue - //------------------------------------------------------------- - - logic [0:0] recv_from_cpu_pkt_queue__clk; - logic [1:0] recv_from_cpu_pkt_queue__count; - logic [0:0] recv_from_cpu_pkt_queue__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt_queue__recv__msg; - logic [0:0] recv_from_cpu_pkt_queue__recv__rdy; - logic [0:0] recv_from_cpu_pkt_queue__recv__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt_queue__send__msg; - logic [0:0] recv_from_cpu_pkt_queue__send__rdy; - logic [0:0] recv_from_cpu_pkt_queue__send__val; - - NormalQueueRTL__a1c7a5a18a302c36 recv_from_cpu_pkt_queue - ( - .clk( recv_from_cpu_pkt_queue__clk ), - .count( recv_from_cpu_pkt_queue__count ), - .reset( recv_from_cpu_pkt_queue__reset ), - .recv__msg( recv_from_cpu_pkt_queue__recv__msg ), - .recv__rdy( recv_from_cpu_pkt_queue__recv__rdy ), - .recv__val( recv_from_cpu_pkt_queue__recv__val ), - .send__msg( recv_from_cpu_pkt_queue__send__msg ), - .send__rdy( recv_from_cpu_pkt_queue__send__rdy ), - .send__val( recv_from_cpu_pkt_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_from_cpu_pkt_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component recv_from_tile_load_request_pkt_queue - //------------------------------------------------------------- - - logic [0:0] recv_from_tile_load_request_pkt_queue__clk; - logic [0:0] recv_from_tile_load_request_pkt_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt_queue__recv__msg; - logic [0:0] recv_from_tile_load_request_pkt_queue__recv__rdy; - logic [0:0] recv_from_tile_load_request_pkt_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_request_pkt_queue__send__msg; - logic [0:0] recv_from_tile_load_request_pkt_queue__send__rdy; - logic [0:0] recv_from_tile_load_request_pkt_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 recv_from_tile_load_request_pkt_queue - ( - .clk( recv_from_tile_load_request_pkt_queue__clk ), - .reset( recv_from_tile_load_request_pkt_queue__reset ), - .recv__msg( recv_from_tile_load_request_pkt_queue__recv__msg ), - .recv__rdy( recv_from_tile_load_request_pkt_queue__recv__rdy ), - .recv__val( recv_from_tile_load_request_pkt_queue__recv__val ), - .send__msg( recv_from_tile_load_request_pkt_queue__send__msg ), - .send__rdy( recv_from_tile_load_request_pkt_queue__send__rdy ), - .send__val( recv_from_tile_load_request_pkt_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_from_tile_load_request_pkt_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component recv_from_tile_load_response_pkt_queue - //------------------------------------------------------------- - - logic [0:0] recv_from_tile_load_response_pkt_queue__clk; - logic [0:0] recv_from_tile_load_response_pkt_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt_queue__recv__msg; - logic [0:0] recv_from_tile_load_response_pkt_queue__recv__rdy; - logic [0:0] recv_from_tile_load_response_pkt_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_load_response_pkt_queue__send__msg; - logic [0:0] recv_from_tile_load_response_pkt_queue__send__rdy; - logic [0:0] recv_from_tile_load_response_pkt_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 recv_from_tile_load_response_pkt_queue - ( - .clk( recv_from_tile_load_response_pkt_queue__clk ), - .reset( recv_from_tile_load_response_pkt_queue__reset ), - .recv__msg( recv_from_tile_load_response_pkt_queue__recv__msg ), - .recv__rdy( recv_from_tile_load_response_pkt_queue__recv__rdy ), - .recv__val( recv_from_tile_load_response_pkt_queue__recv__val ), - .send__msg( recv_from_tile_load_response_pkt_queue__send__msg ), - .send__rdy( recv_from_tile_load_response_pkt_queue__send__rdy ), - .send__val( recv_from_tile_load_response_pkt_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_from_tile_load_response_pkt_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component recv_from_tile_store_request_pkt_queue - //------------------------------------------------------------- - - logic [0:0] recv_from_tile_store_request_pkt_queue__clk; - logic [0:0] recv_from_tile_store_request_pkt_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt_queue__recv__msg; - logic [0:0] recv_from_tile_store_request_pkt_queue__recv__rdy; - logic [0:0] recv_from_tile_store_request_pkt_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_tile_store_request_pkt_queue__send__msg; - logic [0:0] recv_from_tile_store_request_pkt_queue__send__rdy; - logic [0:0] recv_from_tile_store_request_pkt_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 recv_from_tile_store_request_pkt_queue - ( - .clk( recv_from_tile_store_request_pkt_queue__clk ), - .reset( recv_from_tile_store_request_pkt_queue__reset ), - .recv__msg( recv_from_tile_store_request_pkt_queue__recv__msg ), - .recv__rdy( recv_from_tile_store_request_pkt_queue__recv__rdy ), - .recv__val( recv_from_tile_store_request_pkt_queue__recv__val ), - .send__msg( recv_from_tile_store_request_pkt_queue__send__msg ), - .send__rdy( recv_from_tile_store_request_pkt_queue__send__rdy ), - .send__val( recv_from_tile_store_request_pkt_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_from_tile_store_request_pkt_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component send_to_cpu_pkt_queue - //------------------------------------------------------------- - - logic [0:0] send_to_cpu_pkt_queue__clk; - logic [1:0] send_to_cpu_pkt_queue__count; - logic [0:0] send_to_cpu_pkt_queue__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt_queue__recv__msg; - logic [0:0] send_to_cpu_pkt_queue__recv__rdy; - logic [0:0] send_to_cpu_pkt_queue__recv__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt_queue__send__msg; - logic [0:0] send_to_cpu_pkt_queue__send__rdy; - logic [0:0] send_to_cpu_pkt_queue__send__val; - - NormalQueueRTL__a1c7a5a18a302c36 send_to_cpu_pkt_queue - ( - .clk( send_to_cpu_pkt_queue__clk ), - .count( send_to_cpu_pkt_queue__count ), - .reset( send_to_cpu_pkt_queue__reset ), - .recv__msg( send_to_cpu_pkt_queue__recv__msg ), - .recv__rdy( send_to_cpu_pkt_queue__recv__rdy ), - .recv__val( send_to_cpu_pkt_queue__recv__val ), - .send__msg( send_to_cpu_pkt_queue__send__msg ), - .send__rdy( send_to_cpu_pkt_queue__send__rdy ), - .send__val( send_to_cpu_pkt_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component send_to_cpu_pkt_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component send_to_mem_load_request_queue - //------------------------------------------------------------- - - logic [0:0] send_to_mem_load_request_queue__clk; - logic [0:0] send_to_mem_load_request_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request_queue__recv__msg; - logic [0:0] send_to_mem_load_request_queue__recv__rdy; - logic [0:0] send_to_mem_load_request_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_load_request_queue__send__msg; - logic [0:0] send_to_mem_load_request_queue__send__rdy; - logic [0:0] send_to_mem_load_request_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 send_to_mem_load_request_queue - ( - .clk( send_to_mem_load_request_queue__clk ), - .reset( send_to_mem_load_request_queue__reset ), - .recv__msg( send_to_mem_load_request_queue__recv__msg ), - .recv__rdy( send_to_mem_load_request_queue__recv__rdy ), - .recv__val( send_to_mem_load_request_queue__recv__val ), - .send__msg( send_to_mem_load_request_queue__send__msg ), - .send__rdy( send_to_mem_load_request_queue__send__rdy ), - .send__val( send_to_mem_load_request_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component send_to_mem_load_request_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component send_to_mem_store_request_queue - //------------------------------------------------------------- - - logic [0:0] send_to_mem_store_request_queue__clk; - logic [0:0] send_to_mem_store_request_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request_queue__recv__msg; - logic [0:0] send_to_mem_store_request_queue__recv__rdy; - logic [0:0] send_to_mem_store_request_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_mem_store_request_queue__send__msg; - logic [0:0] send_to_mem_store_request_queue__send__rdy; - logic [0:0] send_to_mem_store_request_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 send_to_mem_store_request_queue - ( - .clk( send_to_mem_store_request_queue__clk ), - .reset( send_to_mem_store_request_queue__reset ), - .recv__msg( send_to_mem_store_request_queue__recv__msg ), - .recv__rdy( send_to_mem_store_request_queue__recv__rdy ), - .recv__val( send_to_mem_store_request_queue__recv__val ), - .send__msg( send_to_mem_store_request_queue__send__msg ), - .send__rdy( send_to_mem_store_request_queue__send__rdy ), - .send__val( send_to_mem_store_request_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component send_to_mem_store_request_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component send_to_tile_load_response_queue - //------------------------------------------------------------- - - logic [0:0] send_to_tile_load_response_queue__clk; - logic [0:0] send_to_tile_load_response_queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response_queue__recv__msg; - logic [0:0] send_to_tile_load_response_queue__recv__rdy; - logic [0:0] send_to_tile_load_response_queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_tile_load_response_queue__send__msg; - logic [0:0] send_to_tile_load_response_queue__send__rdy; - logic [0:0] send_to_tile_load_response_queue__send__val; - - ChannelRTL__551ecec02ed96ac9 send_to_tile_load_response_queue - ( - .clk( send_to_tile_load_response_queue__clk ), - .reset( send_to_tile_load_response_queue__reset ), - .recv__msg( send_to_tile_load_response_queue__recv__msg ), - .recv__rdy( send_to_tile_load_response_queue__recv__rdy ), - .recv__val( send_to_tile_load_response_queue__recv__val ), - .send__msg( send_to_tile_load_response_queue__send__msg ), - .send__rdy( send_to_tile_load_response_queue__send__rdy ), - .send__val( send_to_tile_load_response_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component send_to_tile_load_response_queue - //------------------------------------------------------------- - logic [0:0] __tmpvar__update_received_msg_kLoadRequestInportIdx; - logic [0:0] __tmpvar__update_received_msg_kLoadResponseInportIdx; - logic [1:0] __tmpvar__update_received_msg_kStoreRequestInportIdx; - logic [1:0] __tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx; - logic [2:0] __tmpvar__update_received_msg_kFromInterTileRingIdx; - logic [2:0] __tmpvar__update_received_msg_kFromReduceUnitIdx; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d __tmpvar__update_received_msg_received_pkt; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:362 - // @update - // def capture_addr_dst_id(): - // s.addr_dst_id @= s.addr2controller_lut[trunc(s.crossbar.send[0].msg.inter_cgra_pkt.payload.data_addr >> addr_offset_nbits, CgraIdType)] - - always_comb begin : capture_addr_dst_id - addr_dst_id = addr2controller_lut[2'(crossbar__send__msg[1'd0].inter_cgra_pkt.payload.data_addr >> 3'( __const__addr_offset_nbits_at_capture_addr_dst_id ))]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:141 - // @update - // def update_received_msg(): - // kLoadRequestInportIdx = 0 - // kLoadResponseInportIdx = 1 - // kStoreRequestInportIdx = 2 - // kFromCpuCtrlAndDataIdx = 3 - // kFromInterTileRingIdx = 4 - // kFromReduceUnitIdx = 5 - // - // s.send_to_cpu_pkt_queue.recv.val @= 0 - // s.send_to_cpu_pkt_queue.recv.msg @= IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.recv_from_ctrl_ring_pkt.rdy @= 0 - // - // for i in range(CONTROLLER_CROSSBAR_INPORTS): - // s.crossbar.recv[i].val @= 0 - // s.crossbar.recv[i].msg @= ControllerXbarPktType(0, 0) - // - // # For the command signal from inter-tile/intra-cgra control ring. - // s.crossbar.recv[kFromInterTileRingIdx].val @= s.recv_from_ctrl_ring_pkt.val - // s.recv_from_ctrl_ring_pkt.rdy @= s.crossbar.recv[kFromInterTileRingIdx].rdy - // s.crossbar.recv[kFromInterTileRingIdx].msg @= \ - // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) - // InterCgraPktType(s.cgra_id, - // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_id, - // s.idTo2d_x_lut[s.cgra_id], # src_x - // s.idTo2d_y_lut[s.cgra_id], # src_y - // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_x, # dst_x - // s.recv_from_ctrl_ring_pkt.msg.dst_cgra_y, # dst_y - // s.recv_from_ctrl_ring_pkt.msg.src, # src_tile_id - // s.recv_from_ctrl_ring_pkt.msg.dst, # dst_tile_id - // 0, # remote_src_port, only used for inter-cgra remote load request/response. - // 0, # opaque - // 0, # vc_id. No need to specify vc_id for self produce-consume pkt thanks to the additional VC buffer. - // s.recv_from_ctrl_ring_pkt.msg.payload)) - // - // # For the load request from local tiles. - // s.crossbar.recv[kLoadRequestInportIdx].val @= s.recv_from_tile_load_request_pkt_queue.send.val - // s.recv_from_tile_load_request_pkt_queue.send.rdy @= s.crossbar.recv[kLoadRequestInportIdx].rdy - // s.crossbar.recv[kLoadRequestInportIdx].msg @= \ - // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) - // s.recv_from_tile_load_request_pkt_queue.send.msg) - // - // # For the store request from local tiles. - // s.crossbar.recv[kStoreRequestInportIdx].val @= s.recv_from_tile_store_request_pkt_queue.send.val - // s.recv_from_tile_store_request_pkt_queue.send.rdy @= s.crossbar.recv[kStoreRequestInportIdx].rdy - // s.crossbar.recv[kStoreRequestInportIdx].msg @= \ - // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) - // s.recv_from_tile_store_request_pkt_queue.send.msg) - // - // # For the load response (i.e., the data towards other) from local memory. - // s.crossbar.recv[kLoadResponseInportIdx].val @= \ - // s.recv_from_tile_load_response_pkt_queue.send.val - // s.recv_from_tile_load_response_pkt_queue.send.rdy @= s.crossbar.recv[kLoadResponseInportIdx].rdy - // s.crossbar.recv[kLoadResponseInportIdx].msg @= \ - // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) - // s.recv_from_tile_load_response_pkt_queue.send.msg) - // - // # For the load response (i.e., the data towards other) from local memory. - // s.crossbar.recv[kFromReduceUnitIdx].val @= \ - // s.global_reduce_unit.send.val - // s.global_reduce_unit.send.rdy @= s.crossbar.recv[kFromReduceUnitIdx].rdy - // s.crossbar.recv[kFromReduceUnitIdx].msg @= s.global_reduce_unit.send.msg - // - // # For the ctrl and data preloading. - // s.crossbar.recv[kFromCpuCtrlAndDataIdx].val @= \ - // s.recv_from_cpu_pkt_queue.send.val - // s.recv_from_cpu_pkt_queue.send.rdy @= s.crossbar.recv[kFromCpuCtrlAndDataIdx].rdy - // s.crossbar.recv[kFromCpuCtrlAndDataIdx].msg @= \ - // ControllerXbarPktType(0, # dst (always 0 to align with the single outport of the crossbar, i.e., NoC) - // InterCgraPktType(s.cgra_id, # src - // s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id, # dst - // 0, # src_x - // 0, # src_y - // s.idTo2d_x_lut[s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id], # dst_x - // s.idTo2d_y_lut[s.recv_from_cpu_pkt_queue.send.msg.dst_cgra_id], # dst_y - // num_tiles, # src_tile_id, num_tiles is used to indicate the request is from CPU, so the LOAD response can come back. - // s.recv_from_cpu_pkt_queue.send.msg.dst, # dst_tile_id - // 0, # remote_src_port, only used for inter-cgra remote load request/response. - // 0, # opaque - // 0, # vc_id - // s.recv_from_cpu_pkt_queue.send.msg.payload)) - // - // # TODO: For the other cmd types. - // - // - // # @update - // # def update_received_msg_from_noc(): - // - // # Initiates the signals. - // s.send_to_mem_load_request_queue.recv.val @= 0 - // s.send_to_mem_store_request_queue.recv.val @= 0 - // s.send_to_tile_load_response_queue.recv.val @= 0 - // - // s.send_to_mem_load_request_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.send_to_mem_store_request_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.send_to_tile_load_response_queue.recv.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // - // s.recv_from_inter_cgra_noc.rdy @= 0 - // s.send_to_ctrl_ring_pkt.val @= 0 - // s.send_to_ctrl_ring_pkt.msg @= IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.global_reduce_unit.recv_count.val @= 0 - // s.global_reduce_unit.recv_count.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.global_reduce_unit.recv_data.val @= 0 - // s.global_reduce_unit.recv_data.msg @= InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // - // # For the load request from NoC. - // received_pkt = s.recv_from_inter_cgra_noc.msg - // if s.recv_from_inter_cgra_noc.val: - // if s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LOAD_REQUEST: - // s.send_to_mem_load_request_queue.recv.val @= 1 - // - // if s.send_to_mem_load_request_queue.recv.rdy: - // s.recv_from_inter_cgra_noc.rdy @= 1 - // s.send_to_mem_load_request_queue.recv.msg @= received_pkt - // - // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_STORE_REQUEST: - // s.send_to_mem_store_request_queue.recv.msg @= received_pkt - // s.send_to_mem_store_request_queue.recv.val @= 1 - // - // if s.send_to_mem_store_request_queue.recv.rdy: - // s.recv_from_inter_cgra_noc.rdy @= 1 - // - // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LOAD_RESPONSE: - // # FIXME: This condition needs to check whether this controller is the - // # one connecting to CPU, and with the help from additional field indicating - // # whether the packet is originally from CPU. - // # https://github.com/tancheng/VectorCGRA/issues/116. - // if s.recv_from_inter_cgra_noc.msg.dst_tile_id == num_tiles: - // s.recv_from_inter_cgra_noc.rdy @= s.send_to_cpu_pkt_queue.recv.rdy - // s.send_to_cpu_pkt_queue.recv.val @= 1 - // s.send_to_cpu_pkt_queue.recv.msg @= \ - // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src - // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst - // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x - // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y - // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x - // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y - // 0, # opaque - // 0, # vc_id - // s.recv_from_inter_cgra_noc.msg.payload) - // - // else: - // s.recv_from_inter_cgra_noc.rdy @= s.send_to_tile_load_response_queue.recv.rdy - // s.send_to_tile_load_response_queue.recv.msg @= received_pkt - // s.send_to_tile_load_response_queue.recv.val @= 1 - // - // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_COMPLETE: - // s.recv_from_inter_cgra_noc.rdy @= s.send_to_cpu_pkt_queue.recv.rdy - // s.send_to_cpu_pkt_queue.recv.val @= 1 - // s.send_to_cpu_pkt_queue.recv.msg @= \ - // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src - // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst - // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x - // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y - // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x - // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y - // 0, # opaque - // 0, # vc_id - // s.recv_from_inter_cgra_noc.msg.payload) - // - // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD: - // s.recv_from_inter_cgra_noc.rdy @= s.global_reduce_unit.recv_data.rdy - // s.global_reduce_unit.recv_data.val @= 1 - // s.global_reduce_unit.recv_data.msg @= s.recv_from_inter_cgra_noc.msg - // - // elif s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_COUNT: - // s.recv_from_inter_cgra_noc.rdy @= s.global_reduce_unit.recv_count.rdy - // s.global_reduce_unit.recv_count.val @= 1 - // s.global_reduce_unit.recv_count.msg @= s.recv_from_inter_cgra_noc.msg - // - // elif (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_CONST) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_PAUSE) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_PRESERVE) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_RESUME) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_RECORD_PHI_ADDR) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_TERMINATE) | \ - // (s.recv_from_inter_cgra_noc.msg.payload.cmd == CMD_LAUNCH): - // s.recv_from_inter_cgra_noc.rdy @= s.send_to_ctrl_ring_pkt.rdy - // s.send_to_ctrl_ring_pkt.val @= s.recv_from_inter_cgra_noc.val - // s.send_to_ctrl_ring_pkt.msg @= \ - // IntraCgraPktType(s.recv_from_inter_cgra_noc.msg.src_tile_id, # src - // s.recv_from_inter_cgra_noc.msg.dst_tile_id, # dst - // s.recv_from_inter_cgra_noc.msg.src, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.dst, # src_cgra_id - // s.recv_from_inter_cgra_noc.msg.src_x, # src_cgra_x - // s.recv_from_inter_cgra_noc.msg.src_y, # src_cgra_y - // s.recv_from_inter_cgra_noc.msg.dst_x, # dst_cgra_x - // s.recv_from_inter_cgra_noc.msg.dst_y, # dst_cgra_y - // 0, # opaque - // 0, # vc_id - // s.recv_from_inter_cgra_noc.msg.payload) - // - // # else: - // # # TODO: Handle other cmd types. - // # assert(False) - - always_comb begin : update_received_msg - __tmpvar__update_received_msg_kLoadRequestInportIdx = 1'd0; - __tmpvar__update_received_msg_kLoadResponseInportIdx = 1'd1; - __tmpvar__update_received_msg_kStoreRequestInportIdx = 2'd2; - __tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx = 2'd3; - __tmpvar__update_received_msg_kFromInterTileRingIdx = 3'd4; - __tmpvar__update_received_msg_kFromReduceUnitIdx = 3'd5; - send_to_cpu_pkt_queue__recv__val = 1'd0; - send_to_cpu_pkt_queue__recv__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; - recv_from_ctrl_ring_pkt__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__CONTROLLER_CROSSBAR_INPORTS ); i += 1'd1 ) begin - crossbar__recv__val[3'(i)] = 1'd0; - crossbar__recv__msg[3'(i)] = { 1'd0, 221'd0 }; - end - crossbar__recv__val[__tmpvar__update_received_msg_kFromInterTileRingIdx] = recv_from_ctrl_ring_pkt__val; - recv_from_ctrl_ring_pkt__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromInterTileRingIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kFromInterTileRingIdx] = { 1'd0, { cgra_id, recv_from_ctrl_ring_pkt__msg.dst_cgra_id, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], recv_from_ctrl_ring_pkt__msg.dst_cgra_x, recv_from_ctrl_ring_pkt__msg.dst_cgra_y, recv_from_ctrl_ring_pkt__msg.src, recv_from_ctrl_ring_pkt__msg.dst, 3'd0, 8'd0, 2'd0, recv_from_ctrl_ring_pkt__msg.payload } }; - crossbar__recv__val[__tmpvar__update_received_msg_kLoadRequestInportIdx] = recv_from_tile_load_request_pkt_queue__send__val; - recv_from_tile_load_request_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kLoadRequestInportIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kLoadRequestInportIdx] = { 1'd0, recv_from_tile_load_request_pkt_queue__send__msg }; - crossbar__recv__val[__tmpvar__update_received_msg_kStoreRequestInportIdx] = recv_from_tile_store_request_pkt_queue__send__val; - recv_from_tile_store_request_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kStoreRequestInportIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kStoreRequestInportIdx] = { 1'd0, recv_from_tile_store_request_pkt_queue__send__msg }; - crossbar__recv__val[__tmpvar__update_received_msg_kLoadResponseInportIdx] = recv_from_tile_load_response_pkt_queue__send__val; - recv_from_tile_load_response_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kLoadResponseInportIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kLoadResponseInportIdx] = { 1'd0, recv_from_tile_load_response_pkt_queue__send__msg }; - crossbar__recv__val[__tmpvar__update_received_msg_kFromReduceUnitIdx] = global_reduce_unit__send__val; - global_reduce_unit__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromReduceUnitIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kFromReduceUnitIdx] = global_reduce_unit__send__msg; - crossbar__recv__val[__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx] = recv_from_cpu_pkt_queue__send__val; - recv_from_cpu_pkt_queue__send__rdy = crossbar__recv__rdy[3'(__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx)]; - crossbar__recv__msg[__tmpvar__update_received_msg_kFromCpuCtrlAndDataIdx] = { 1'd0, { cgra_id, recv_from_cpu_pkt_queue__send__msg.dst_cgra_id, 1'd0, 1'd0, idTo2d_x_lut[recv_from_cpu_pkt_queue__send__msg.dst_cgra_id], idTo2d_y_lut[recv_from_cpu_pkt_queue__send__msg.dst_cgra_id], 5'( __const__num_tiles_at_update_received_msg ), recv_from_cpu_pkt_queue__send__msg.dst, 3'd0, 8'd0, 2'd0, recv_from_cpu_pkt_queue__send__msg.payload } }; - send_to_mem_load_request_queue__recv__val = 1'd0; - send_to_mem_store_request_queue__recv__val = 1'd0; - send_to_tile_load_response_queue__recv__val = 1'd0; - send_to_mem_load_request_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - send_to_mem_store_request_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - send_to_tile_load_response_queue__recv__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - recv_from_inter_cgra_noc__rdy = 1'd0; - send_to_ctrl_ring_pkt__val = 1'd0; - send_to_ctrl_ring_pkt__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; - global_reduce_unit__recv_count__val = 1'd0; - global_reduce_unit__recv_count__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - global_reduce_unit__recv_data__val = 1'd0; - global_reduce_unit__recv_data__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, 190'd0 }; - __tmpvar__update_received_msg_received_pkt = recv_from_inter_cgra_noc__msg; - if ( recv_from_inter_cgra_noc__val ) begin - if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LOAD_REQUEST ) ) begin - send_to_mem_load_request_queue__recv__val = 1'd1; - if ( send_to_mem_load_request_queue__recv__rdy ) begin - recv_from_inter_cgra_noc__rdy = 1'd1; - send_to_mem_load_request_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; - end - end - else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_STORE_REQUEST ) ) begin - send_to_mem_store_request_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; - send_to_mem_store_request_queue__recv__val = 1'd1; - if ( send_to_mem_store_request_queue__recv__rdy ) begin - recv_from_inter_cgra_noc__rdy = 1'd1; - end - end - else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LOAD_RESPONSE ) ) begin - if ( recv_from_inter_cgra_noc__msg.dst_tile_id == 5'( __const__num_tiles_at_update_received_msg ) ) begin - recv_from_inter_cgra_noc__rdy = send_to_cpu_pkt_queue__recv__rdy; - send_to_cpu_pkt_queue__recv__val = 1'd1; - send_to_cpu_pkt_queue__recv__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; - end - else begin - recv_from_inter_cgra_noc__rdy = send_to_tile_load_response_queue__recv__rdy; - send_to_tile_load_response_queue__recv__msg = __tmpvar__update_received_msg_received_pkt; - send_to_tile_load_response_queue__recv__val = 1'd1; - end - end - else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_COMPLETE ) ) begin - recv_from_inter_cgra_noc__rdy = send_to_cpu_pkt_queue__recv__rdy; - send_to_cpu_pkt_queue__recv__val = 1'd1; - send_to_cpu_pkt_queue__recv__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; - end - else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD ) ) begin - recv_from_inter_cgra_noc__rdy = global_reduce_unit__recv_data__rdy; - global_reduce_unit__recv_data__val = 1'd1; - global_reduce_unit__recv_data__msg = recv_from_inter_cgra_noc__msg; - end - else if ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_COUNT ) ) begin - recv_from_inter_cgra_noc__rdy = global_reduce_unit__recv_count__rdy; - global_reduce_unit__recv_count__val = 1'd1; - global_reduce_unit__recv_count__msg = recv_from_inter_cgra_noc__msg; - end - else if ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_CONST ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_PAUSE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_PRESERVE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_RECORD_PHI_ADDR ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) | ( recv_from_inter_cgra_noc__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) begin - recv_from_inter_cgra_noc__rdy = send_to_ctrl_ring_pkt__rdy; - send_to_ctrl_ring_pkt__val = recv_from_inter_cgra_noc__val; - send_to_ctrl_ring_pkt__msg = { recv_from_inter_cgra_noc__msg.src_tile_id, recv_from_inter_cgra_noc__msg.dst_tile_id, recv_from_inter_cgra_noc__msg.src, recv_from_inter_cgra_noc__msg.dst, recv_from_inter_cgra_noc__msg.src_x, recv_from_inter_cgra_noc__msg.src_y, recv_from_inter_cgra_noc__msg.dst_x, recv_from_inter_cgra_noc__msg.dst_y, 8'd0, 1'd0, recv_from_inter_cgra_noc__msg.payload }; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/controller/ControllerRTL.py:350 - // @update - // def update_sending_to_noc_msg(): - // s.send_to_inter_cgra_noc.val @= s.crossbar.send[0].val - // s.crossbar.send[0].rdy @= s.send_to_inter_cgra_noc.rdy - // s.send_to_inter_cgra_noc.msg @= s.crossbar.send[0].msg.inter_cgra_pkt - // # addr_dst_id = 0 - // if (s.crossbar.send[0].msg.inter_cgra_pkt.payload.cmd == CMD_LOAD_REQUEST) | \ - // (s.crossbar.send[0].msg.inter_cgra_pkt.payload.cmd == CMD_STORE_REQUEST): - // s.send_to_inter_cgra_noc.msg.dst @= s.addr_dst_id - // s.send_to_inter_cgra_noc.msg.dst_x @= s.idTo2d_x_lut[s.addr_dst_id] - // s.send_to_inter_cgra_noc.msg.dst_y @= s.idTo2d_y_lut[s.addr_dst_id] - - always_comb begin : update_sending_to_noc_msg - send_to_inter_cgra_noc__val = crossbar__send__val[1'd0]; - crossbar__send__rdy[1'd0] = send_to_inter_cgra_noc__rdy; - send_to_inter_cgra_noc__msg = crossbar__send__msg[1'd0].inter_cgra_pkt; - if ( ( crossbar__send__msg[1'd0].inter_cgra_pkt.payload.cmd == 5'( __const__CMD_LOAD_REQUEST ) ) | ( crossbar__send__msg[1'd0].inter_cgra_pkt.payload.cmd == 5'( __const__CMD_STORE_REQUEST ) ) ) begin - send_to_inter_cgra_noc__msg.dst = addr_dst_id; - send_to_inter_cgra_noc__msg.dst_x = idTo2d_x_lut[addr_dst_id]; - send_to_inter_cgra_noc__msg.dst_y = idTo2d_y_lut[addr_dst_id]; - end - end - - assign recv_from_tile_load_request_pkt_queue__clk = clk; - assign recv_from_tile_load_request_pkt_queue__reset = reset; - assign recv_from_tile_load_response_pkt_queue__clk = clk; - assign recv_from_tile_load_response_pkt_queue__reset = reset; - assign recv_from_tile_store_request_pkt_queue__clk = clk; - assign recv_from_tile_store_request_pkt_queue__reset = reset; - assign send_to_mem_load_request_queue__clk = clk; - assign send_to_mem_load_request_queue__reset = reset; - assign send_to_tile_load_response_queue__clk = clk; - assign send_to_tile_load_response_queue__reset = reset; - assign send_to_mem_store_request_queue__clk = clk; - assign send_to_mem_store_request_queue__reset = reset; - assign crossbar__clk = clk; - assign crossbar__reset = reset; - assign recv_from_cpu_pkt_queue__clk = clk; - assign recv_from_cpu_pkt_queue__reset = reset; - assign send_to_cpu_pkt_queue__clk = clk; - assign send_to_cpu_pkt_queue__reset = reset; - assign global_reduce_unit__clk = clk; - assign global_reduce_unit__reset = reset; - assign addr2controller_lut[0] = 2'd0; - assign addr2controller_lut[1] = 2'd1; - assign addr2controller_lut[2] = 2'd2; - assign addr2controller_lut[3] = 2'd3; - assign idTo2d_x_lut[0] = 1'd0; - assign idTo2d_y_lut[0] = 1'd0; - assign idTo2d_x_lut[1] = 1'd1; - assign idTo2d_y_lut[1] = 1'd0; - assign idTo2d_x_lut[2] = 1'd0; - assign idTo2d_y_lut[2] = 1'd1; - assign idTo2d_x_lut[3] = 1'd1; - assign idTo2d_y_lut[3] = 1'd1; - assign recv_from_tile_load_request_pkt_queue__recv__msg = recv_from_tile_load_request_pkt__msg; - assign recv_from_tile_load_request_pkt__rdy = recv_from_tile_load_request_pkt_queue__recv__rdy; - assign recv_from_tile_load_request_pkt_queue__recv__val = recv_from_tile_load_request_pkt__val; - assign recv_from_tile_load_response_pkt_queue__recv__msg = recv_from_tile_load_response_pkt__msg; - assign recv_from_tile_load_response_pkt__rdy = recv_from_tile_load_response_pkt_queue__recv__rdy; - assign recv_from_tile_load_response_pkt_queue__recv__val = recv_from_tile_load_response_pkt__val; - assign recv_from_tile_store_request_pkt_queue__recv__msg = recv_from_tile_store_request_pkt__msg; - assign recv_from_tile_store_request_pkt__rdy = recv_from_tile_store_request_pkt_queue__recv__rdy; - assign recv_from_tile_store_request_pkt_queue__recv__val = recv_from_tile_store_request_pkt__val; - assign send_to_mem_load_request__msg = send_to_mem_load_request_queue__send__msg; - assign send_to_mem_load_request_queue__send__rdy = send_to_mem_load_request__rdy; - assign send_to_mem_load_request__val = send_to_mem_load_request_queue__send__val; - assign send_to_tile_load_response__msg = send_to_tile_load_response_queue__send__msg; - assign send_to_tile_load_response_queue__send__rdy = send_to_tile_load_response__rdy; - assign send_to_tile_load_response__val = send_to_tile_load_response_queue__send__val; - assign send_to_mem_store_request__msg = send_to_mem_store_request_queue__send__msg; - assign send_to_mem_store_request_queue__send__rdy = send_to_mem_store_request__rdy; - assign send_to_mem_store_request__val = send_to_mem_store_request_queue__send__val; - assign recv_from_cpu_pkt_queue__recv__msg = recv_from_cpu_pkt__msg; - assign recv_from_cpu_pkt__rdy = recv_from_cpu_pkt_queue__recv__rdy; - assign recv_from_cpu_pkt_queue__recv__val = recv_from_cpu_pkt__val; - assign send_to_cpu_pkt__msg = send_to_cpu_pkt_queue__send__msg; - assign send_to_cpu_pkt_queue__send__rdy = send_to_cpu_pkt__rdy; - assign send_to_cpu_pkt__val = send_to_cpu_pkt_queue__send__val; - -endmodule - - -// PyMTL Component Counter Definition -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/rtl/Counter.py - -module Counter__Type_Bits2__reset_value_2 -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] decr , - input logic [0:0] incr , - input logic [0:0] load , - input logic [1:0] load_value , - input logic [0:0] reset -); - localparam logic [1:0] __const__reset_value_at_up_count = 2'd2; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/rtl/Counter.py:28 - // @update_ff - // def up_count(): - // - // if s.reset: - // s.count <<= reset_value - // - // elif s.load: - // s.count <<= s.load_value - // - // elif s.incr & ~s.decr: - // s.count <<= s.count + 1 - // - // elif ~s.incr & s.decr: - // s.count <<= s.count - 1 - - always_ff @(posedge clk) begin : up_count - if ( reset ) begin - count <= 2'( __const__reset_value_at_up_count ); - end - else if ( load ) begin - count <= load_value; - end - else if ( incr & ( ~decr ) ) begin - count <= count + 2'd1; - end - else if ( ( ~incr ) & decr ) begin - count <= count - 2'd1; - end - end - -endmodule - - -// PyMTL Component RecvRTL2CreditSendRTL Definition -// Full name: RecvRTL2CreditSendRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py - -module RecvRTL2CreditSendRTL__6d49e584a986d10c -( - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output logic [0:0] send__en , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__yum [0:1] -); - localparam logic [1:0] __const__vc_at_up_credit_send = 2'd2; - localparam logic [1:0] __const__vc_at_up_counter_decr = 2'd2; - //------------------------------------------------------------- - // Component credit[0:1] - //------------------------------------------------------------- - - logic [0:0] credit__clk [0:1]; - logic [1:0] credit__count [0:1]; - logic [0:0] credit__decr [0:1]; - logic [0:0] credit__incr [0:1]; - logic [0:0] credit__load [0:1]; - logic [1:0] credit__load_value [0:1]; - logic [0:0] credit__reset [0:1]; - - Counter__Type_Bits2__reset_value_2 credit__0 - ( - .clk( credit__clk[0] ), - .count( credit__count[0] ), - .decr( credit__decr[0] ), - .incr( credit__incr[0] ), - .load( credit__load[0] ), - .load_value( credit__load_value[0] ), - .reset( credit__reset[0] ) - ); - - Counter__Type_Bits2__reset_value_2 credit__1 - ( - .clk( credit__clk[1] ), - .count( credit__count[1] ), - .decr( credit__decr[1] ), - .incr( credit__incr[1] ), - .load( credit__load[1] ), - .load_value( credit__load_value[1] ), - .reset( credit__reset[1] ) - ); - - //------------------------------------------------------------- - // End of component credit[0:1] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:149 - // @update - // def up_counter_decr(): - // for i in range( vc ): - // s.credit[i].decr @= s.send.en & ( i == s.send.msg.vc_id ) - - always_comb begin : up_counter_decr - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_counter_decr ); i += 1'd1 ) - credit__decr[1'(i)] = send__en & ( 1'(i) == send__msg.vc_id ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:137 - // @update - // def up_credit_send(): - // s.send.en @= 0 - // s.recv.rdy @= 0 - // # NOTE: recv.rdy depends on recv.val. - // # Be careful about combinationl loop. - // if s.recv.val: - // for i in range( vc ): - // if ( i == s.recv.msg.vc_id ) & ( s.credit[i].count > 0 ): - // s.send.en @= 1 - // s.recv.rdy @= 1 - - always_comb begin : up_credit_send - send__en = 1'd0; - recv__rdy = 1'd0; - if ( recv__val ) begin - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_credit_send ); i += 1'd1 ) - if ( ( 1'(i) == recv__msg.vc_id ) & ( credit__count[1'(i)] > 2'd0 ) ) begin - send__en = 1'd1; - recv__rdy = 1'd1; - end - end - end - - assign credit__clk[0] = clk; - assign credit__reset[0] = reset; - assign credit__clk[1] = clk; - assign credit__reset[1] = reset; - assign send__msg = recv__msg; - assign credit__incr[0] = send__yum[0]; - assign credit__load[0] = 1'd0; - assign credit__load_value[0] = 2'd0; - assign credit__incr[1] = send__yum[1]; - assign credit__load[1] = 1'd0; - assign credit__load_value[1] = 2'd0; - -endmodule - - -// PyMTL Component InputUnitCreditRTL Definition -// Full name: InputUnitCreditRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__QueueType_NormalQueueRTL__vc_2__credit_line_2 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py - -module InputUnitCreditRTL__797fe657f4e9d44e -( - input logic [0:0] clk , - input logic [0:0] reset , - input logic [0:0] recv__en , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__yum [0:1] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:1] , - input logic [0:0] send__rdy [0:1] , - output logic [0:0] send__val [0:1] -); - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ = 1'd0; - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ = 1'd1; - localparam logic [1:0] __const__vc_at_up_enq = 2'd2; - //------------------------------------------------------------- - // Component buffers[0:1] - //------------------------------------------------------------- - - logic [0:0] buffers__clk [0:1]; - logic [1:0] buffers__count [0:1]; - logic [0:0] buffers__reset [0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__recv__msg [0:1]; - logic [0:0] buffers__recv__rdy [0:1]; - logic [0:0] buffers__recv__val [0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__send__msg [0:1]; - logic [0:0] buffers__send__rdy [0:1]; - logic [0:0] buffers__send__val [0:1]; - - NormalQueueRTL__a1c7a5a18a302c36 buffers__0 - ( - .clk( buffers__clk[0] ), - .count( buffers__count[0] ), - .reset( buffers__reset[0] ), - .recv__msg( buffers__recv__msg[0] ), - .recv__rdy( buffers__recv__rdy[0] ), - .recv__val( buffers__recv__val[0] ), - .send__msg( buffers__send__msg[0] ), - .send__rdy( buffers__send__rdy[0] ), - .send__val( buffers__send__val[0] ) - ); - - NormalQueueRTL__a1c7a5a18a302c36 buffers__1 - ( - .clk( buffers__clk[1] ), - .count( buffers__count[1] ), - .reset( buffers__reset[1] ), - .recv__msg( buffers__recv__msg[1] ), - .recv__rdy( buffers__recv__rdy[1] ), - .recv__val( buffers__recv__val[1] ), - .send__msg( buffers__send__msg[1] ), - .send__rdy( buffers__send__rdy[1] ), - .send__val( buffers__send__val[1] ) - ); - - //------------------------------------------------------------- - // End of component buffers[0:1] - //------------------------------------------------------------- - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:39 - // s.recv.yum[i] //= lambda: s.send[i].val & s.send[i].rdy - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ - recv__yum[1'd0] = send__val[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ )] & send__rdy[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_0_ )]; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:39 - // s.recv.yum[i] //= lambda: s.send[i].val & s.send[i].rdy - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ - recv__yum[1'd1] = send__val[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ )] & send__rdy[1'( __const__i_at__lambda__s_dut_cgra_0__ctrl_ring_routers_0__input_units_0__recv_yum_1_ )]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitCreditRTL.py:41 - // @update - // def up_enq(): - // if s.recv.en: - // for i in range( vc ): - // s.buffers[i].recv.val @= ( s.recv.msg.vc_id == i ) - // else: - // for i in range( vc ): - // s.buffers[i].recv.val @= 0 - - always_comb begin : up_enq - if ( recv__en ) begin - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) - buffers__recv__val[1'(i)] = recv__msg.vc_id == 1'(i); - end - else - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) - buffers__recv__val[1'(i)] = 1'd0; - end - - assign buffers__clk[0] = clk; - assign buffers__reset[0] = reset; - assign buffers__clk[1] = clk; - assign buffers__reset[1] = reset; - assign buffers__recv__msg[0] = recv__msg; - assign send__msg[0] = buffers__send__msg[0]; - assign buffers__send__rdy[0] = send__rdy[0]; - assign send__val[0] = buffers__send__val[0]; - assign buffers__recv__msg[1] = recv__msg; - assign send__msg[1] = buffers__send__msg[1]; - assign buffers__send__rdy[1] = send__rdy[1]; - assign send__val[1] = buffers__send__val[1]; - -endmodule - - -// PyMTL Component OutputUnitCreditRTL Definition -// Full name: OutputUnitCreditRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py - -module OutputUnitCreditRTL__6d49e584a986d10c -( - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output logic [0:0] send__en , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__yum [0:1] -); - localparam logic [1:0] __const__vc_at_up_credit_send = 2'd2; - localparam logic [1:0] __const__vc_at_up_counter_decr = 2'd2; - //------------------------------------------------------------- - // Component credit[0:1] - //------------------------------------------------------------- - - logic [0:0] credit__clk [0:1]; - logic [1:0] credit__count [0:1]; - logic [0:0] credit__decr [0:1]; - logic [0:0] credit__incr [0:1]; - logic [0:0] credit__load [0:1]; - logic [1:0] credit__load_value [0:1]; - logic [0:0] credit__reset [0:1]; - - Counter__Type_Bits2__reset_value_2 credit__0 - ( - .clk( credit__clk[0] ), - .count( credit__count[0] ), - .decr( credit__decr[0] ), - .incr( credit__incr[0] ), - .load( credit__load[0] ), - .load_value( credit__load_value[0] ), - .reset( credit__reset[0] ) - ); - - Counter__Type_Bits2__reset_value_2 credit__1 - ( - .clk( credit__clk[1] ), - .count( credit__count[1] ), - .decr( credit__decr[1] ), - .incr( credit__incr[1] ), - .load( credit__load[1] ), - .load_value( credit__load_value[1] ), - .reset( credit__reset[1] ) - ); - - //------------------------------------------------------------- - // End of component credit[0:1] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py:47 - // @update - // def up_counter_decr(): - // for i in range( vc ): - // s.credit[i].decr @= s.send.en & ( i == s.send.msg.vc_id ) - - always_comb begin : up_counter_decr - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_counter_decr ); i += 1'd1 ) - credit__decr[1'(i)] = send__en & ( 1'(i) == send__msg.vc_id ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitCreditRTL.py:35 - // @update - // def up_credit_send(): - // s.send.en @= 0 - // s.recv.rdy @= 0 - // # NOTE: Here the recv.rdy depends on recv.val. - // # Be careful about combinational loop. - // if s.recv.val: - // for i in range( vc ): - // if (i == s.recv.msg.vc_id) & (s.credit[i].count > 0): - // s.send.en @= 1 - // s.recv.rdy @= 1 - - always_comb begin : up_credit_send - send__en = 1'd0; - recv__rdy = 1'd0; - if ( recv__val ) begin - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_credit_send ); i += 1'd1 ) - if ( ( 1'(i) == recv__msg.vc_id ) & ( credit__count[1'(i)] > 2'd0 ) ) begin - send__en = 1'd1; - recv__rdy = 1'd1; - end - end - end - - assign credit__clk[0] = clk; - assign credit__reset[0] = reset; - assign credit__clk[1] = clk; - assign credit__reset[1] = reset; - assign send__msg = recv__msg; - assign credit__incr[0] = send__yum[0]; - assign credit__load[0] = 1'd0; - assign credit__load_value[0] = 2'd0; - assign credit__incr[1] = send__yum[1]; - assign credit__load[1] = 1'd0; - assign credit__load_value[1] = 2'd0; - -endmodule - - -// PyMTL Component RingRouteUnitRTL Definition -// Full name: RingRouteUnitRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py - -module RingRouteUnitRTL__6d1cae73cf31e9a0 -( - input logic [0:0] clk , - input logic [4:0] pos , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:2] , - input logic [0:0] send__rdy [0:2] , - output logic [0:0] send__val [0:2] -); - localparam logic [1:0] __const__SELF = 2'd2; - localparam logic [0:0] __const__LEFT = 1'd0; - localparam logic [0:0] __const__RIGHT = 1'd1; - logic [4:0] left_dist; - logic [1:0] out_dir; - logic [4:0] right_dist; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg_wire; - logic [2:0] send_rdy; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:51 - // @update - // def up_left_right_dist(): - // if s.recv.msg.dst < s.pos: - // s.left_dist @= zext(s.pos, DistType) - zext(s.recv.msg.dst, DistType) - // s.right_dist @= zext(s.last_idx, DistType) - zext(s.pos, DistType) + zext(s.recv.msg.dst, DistType) + 1 - // else: - // s.left_dist @= 1 + zext(s.last_idx, DistType) + zext(s.pos, DistType) - zext(s.recv.msg.dst, DistType) - // s.right_dist @= zext(s.recv.msg.dst, DistType) - zext(s.pos, DistType) - - always_comb begin : up_left_right_dist - if ( recv__msg.dst < pos ) begin - left_dist = pos - recv__msg.dst; - right_dist = ( ( 5'd16 - pos ) + recv__msg.dst ) + 5'd1; - end - else begin - left_dist = ( ( 5'd1 + 5'd16 ) + pos ) - recv__msg.dst; - right_dist = recv__msg.dst - pos; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:85 - // @update - // def up_ru_recv_rdy(): - // s.recv.rdy @= s.send_rdy[ s.out_dir ] - - always_comb begin : up_ru_recv_rdy - recv__rdy = send_rdy[out_dir]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouteUnitRTL.py:60 - // @update - // def up_ru_routing(): - // - // s.out_dir @= 0 - // s.send_msg_wire @= s.recv.msg - // for i in range( s.num_outports ): - // s.send[i].val @= 0 - // s.send[i].msg @= s.recv.msg - // - // if s.recv.val: - // if s.pos == s.recv.msg.dst: - // s.out_dir @= SELF - // elif s.left_dist < s.right_dist: - // s.out_dir @= LEFT - // else: - // s.out_dir @= RIGHT - // - // if ( s.pos == s.last_idx ) & ( s.out_dir == RIGHT ): - // s.send_msg_wire.vc_id @= 1 - // elif ( s.pos == 0 ) & ( s.out_dir == LEFT ): - // s.send_msg_wire.vc_id @= 1 - // - // s.send[ s.out_dir ].val @= 1 - // s.send[ s.out_dir ].msg @= s.send_msg_wire - - always_comb begin : up_ru_routing - out_dir = 2'd0; - send_msg_wire = recv__msg; - for ( int unsigned i = 1'd0; i < 2'd3; i += 1'd1 ) begin - send__val[2'(i)] = 1'd0; - send__msg[2'(i)] = recv__msg; - end - if ( recv__val ) begin - if ( pos == recv__msg.dst ) begin - out_dir = 2'( __const__SELF ); - end - else if ( left_dist < right_dist ) begin - out_dir = 2'( __const__LEFT ); - end - else - out_dir = 2'( __const__RIGHT ); - if ( ( pos == 5'd16 ) & ( out_dir == 2'( __const__RIGHT ) ) ) begin - send_msg_wire.vc_id = 1'd1; - end - else if ( ( pos == 5'd0 ) & ( out_dir == 2'( __const__LEFT ) ) ) begin - send_msg_wire.vc_id = 1'd1; - end - send__val[out_dir] = 1'd1; - send__msg[out_dir] = send_msg_wire; - end - end - - assign send_rdy[0:0] = send__rdy[0]; - assign send_rdy[1:1] = send__rdy[1]; - assign send_rdy[2:2] = send__rdy[2]; - -endmodule - - -// PyMTL Component Mux Definition -// Full name: Mux__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ninputs_6 -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__1cc75bdfd067f505 -( - input logic [0:0] clk , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 in_ [0:5], - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 out , - input logic [0:0] reset , - input logic [2:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component SwitchUnitRTL Definition -// Full name: SwitchUnitRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_inports_6 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py - -module SwitchUnitRTL__ae7d6e1a8f952f91 -( - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:5] , - output logic [0:0] recv__rdy [0:5] , - input logic [0:0] recv__val [0:5] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd6; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [5:0] arbiter__grants; - logic [5:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_6 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [5:0] encoder__in_; - logic [2:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_6__out_nbits_3 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__in_ [0:5]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__out; - logic [0:0] mux__reset; - logic [2:0] mux__sel; - - Mux__1cc75bdfd067f505 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 - // @update - // def up_get_en(): - // for i in range( num_inports ): - // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) - - always_comb begin : up_get_en - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) - recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 - // @update - // def up_send_val(): - // s.send.val @= s.arbiter.grants > 0 - - always_comb begin : up_send_val - send__val = arbiter__grants > 6'd0; - end - - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign arbiter__en = 1'd1; - assign mux__clk = clk; - assign mux__reset = reset; - assign send__msg = mux__out; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign encoder__in_ = arbiter__grants; - assign mux__sel = encoder__out; - assign arbiter__reqs[0:0] = recv__val[0]; - assign mux__in_[0] = recv__msg[0]; - assign arbiter__reqs[1:1] = recv__val[1]; - assign mux__in_[1] = recv__msg[1]; - assign arbiter__reqs[2:2] = recv__val[2]; - assign mux__in_[2] = recv__msg[2]; - assign arbiter__reqs[3:3] = recv__val[3]; - assign mux__in_[3] = recv__msg[3]; - assign arbiter__reqs[4:4] = recv__val[4]; - assign mux__in_[4] = recv__msg[4]; - assign arbiter__reqs[5:5] = recv__val[5]; - assign mux__in_[5] = recv__msg[5]; - -endmodule - - -// PyMTL Component RingRouterRTL Definition -// Full name: RingRouterRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17__InputUnitType_InputUnitCreditRTL__RouteUnitType_RingRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitCreditRTL__vc_2__credit_line_2 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingRouterRTL.py - -module RingRouterRTL__6e670e447e1766e0 -( - input logic [0:0] clk , - input logic [4:0] pos , - input logic [0:0] reset , - input logic [0:0] recv__en [0:2] , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:2] , - output logic [0:0] recv__yum [0:2][0:1] , - output logic [0:0] send__en [0:2] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:2] , - input logic [0:0] send__yum [0:2][0:1] -); - //------------------------------------------------------------- - // Component input_units[0:2] - //------------------------------------------------------------- - - logic [0:0] input_units__clk [0:2]; - logic [0:0] input_units__reset [0:2]; - logic [0:0] input_units__recv__en [0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 input_units__recv__msg [0:2]; - logic [0:0] input_units__recv__yum [0:2][0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 input_units__send__msg [0:2][0:1]; - logic [0:0] input_units__send__rdy [0:2][0:1]; - logic [0:0] input_units__send__val [0:2][0:1]; - - InputUnitCreditRTL__797fe657f4e9d44e input_units__0 - ( - .clk( input_units__clk[0] ), - .reset( input_units__reset[0] ), - .recv__en( input_units__recv__en[0] ), - .recv__msg( input_units__recv__msg[0] ), - .recv__yum( input_units__recv__yum[0] ), - .send__msg( input_units__send__msg[0] ), - .send__rdy( input_units__send__rdy[0] ), - .send__val( input_units__send__val[0] ) - ); - - InputUnitCreditRTL__797fe657f4e9d44e input_units__1 - ( - .clk( input_units__clk[1] ), - .reset( input_units__reset[1] ), - .recv__en( input_units__recv__en[1] ), - .recv__msg( input_units__recv__msg[1] ), - .recv__yum( input_units__recv__yum[1] ), - .send__msg( input_units__send__msg[1] ), - .send__rdy( input_units__send__rdy[1] ), - .send__val( input_units__send__val[1] ) - ); - - InputUnitCreditRTL__797fe657f4e9d44e input_units__2 - ( - .clk( input_units__clk[2] ), - .reset( input_units__reset[2] ), - .recv__en( input_units__recv__en[2] ), - .recv__msg( input_units__recv__msg[2] ), - .recv__yum( input_units__recv__yum[2] ), - .send__msg( input_units__send__msg[2] ), - .send__rdy( input_units__send__rdy[2] ), - .send__val( input_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component input_units[0:2] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component output_units[0:2] - //------------------------------------------------------------- - - logic [0:0] output_units__clk [0:2]; - logic [0:0] output_units__reset [0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 output_units__recv__msg [0:2]; - logic [0:0] output_units__recv__rdy [0:2]; - logic [0:0] output_units__recv__val [0:2]; - logic [0:0] output_units__send__en [0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 output_units__send__msg [0:2]; - logic [0:0] output_units__send__yum [0:2][0:1]; - - OutputUnitCreditRTL__6d49e584a986d10c output_units__0 - ( - .clk( output_units__clk[0] ), - .reset( output_units__reset[0] ), - .recv__msg( output_units__recv__msg[0] ), - .recv__rdy( output_units__recv__rdy[0] ), - .recv__val( output_units__recv__val[0] ), - .send__en( output_units__send__en[0] ), - .send__msg( output_units__send__msg[0] ), - .send__yum( output_units__send__yum[0] ) - ); - - OutputUnitCreditRTL__6d49e584a986d10c output_units__1 - ( - .clk( output_units__clk[1] ), - .reset( output_units__reset[1] ), - .recv__msg( output_units__recv__msg[1] ), - .recv__rdy( output_units__recv__rdy[1] ), - .recv__val( output_units__recv__val[1] ), - .send__en( output_units__send__en[1] ), - .send__msg( output_units__send__msg[1] ), - .send__yum( output_units__send__yum[1] ) - ); - - OutputUnitCreditRTL__6d49e584a986d10c output_units__2 - ( - .clk( output_units__clk[2] ), - .reset( output_units__reset[2] ), - .recv__msg( output_units__recv__msg[2] ), - .recv__rdy( output_units__recv__rdy[2] ), - .recv__val( output_units__recv__val[2] ), - .send__en( output_units__send__en[2] ), - .send__msg( output_units__send__msg[2] ), - .send__yum( output_units__send__yum[2] ) - ); - - //------------------------------------------------------------- - // End of component output_units[0:2] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component route_units[0:5] - //------------------------------------------------------------- - - logic [0:0] route_units__clk [0:5]; - logic [4:0] route_units__pos [0:5]; - logic [0:0] route_units__reset [0:5]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 route_units__recv__msg [0:5]; - logic [0:0] route_units__recv__rdy [0:5]; - logic [0:0] route_units__recv__val [0:5]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 route_units__send__msg [0:5][0:2]; - logic [0:0] route_units__send__rdy [0:5][0:2]; - logic [0:0] route_units__send__val [0:5][0:2]; - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__0 - ( - .clk( route_units__clk[0] ), - .pos( route_units__pos[0] ), - .reset( route_units__reset[0] ), - .recv__msg( route_units__recv__msg[0] ), - .recv__rdy( route_units__recv__rdy[0] ), - .recv__val( route_units__recv__val[0] ), - .send__msg( route_units__send__msg[0] ), - .send__rdy( route_units__send__rdy[0] ), - .send__val( route_units__send__val[0] ) - ); - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__1 - ( - .clk( route_units__clk[1] ), - .pos( route_units__pos[1] ), - .reset( route_units__reset[1] ), - .recv__msg( route_units__recv__msg[1] ), - .recv__rdy( route_units__recv__rdy[1] ), - .recv__val( route_units__recv__val[1] ), - .send__msg( route_units__send__msg[1] ), - .send__rdy( route_units__send__rdy[1] ), - .send__val( route_units__send__val[1] ) - ); - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__2 - ( - .clk( route_units__clk[2] ), - .pos( route_units__pos[2] ), - .reset( route_units__reset[2] ), - .recv__msg( route_units__recv__msg[2] ), - .recv__rdy( route_units__recv__rdy[2] ), - .recv__val( route_units__recv__val[2] ), - .send__msg( route_units__send__msg[2] ), - .send__rdy( route_units__send__rdy[2] ), - .send__val( route_units__send__val[2] ) - ); - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__3 - ( - .clk( route_units__clk[3] ), - .pos( route_units__pos[3] ), - .reset( route_units__reset[3] ), - .recv__msg( route_units__recv__msg[3] ), - .recv__rdy( route_units__recv__rdy[3] ), - .recv__val( route_units__recv__val[3] ), - .send__msg( route_units__send__msg[3] ), - .send__rdy( route_units__send__rdy[3] ), - .send__val( route_units__send__val[3] ) - ); - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__4 - ( - .clk( route_units__clk[4] ), - .pos( route_units__pos[4] ), - .reset( route_units__reset[4] ), - .recv__msg( route_units__recv__msg[4] ), - .recv__rdy( route_units__recv__rdy[4] ), - .recv__val( route_units__recv__val[4] ), - .send__msg( route_units__send__msg[4] ), - .send__rdy( route_units__send__rdy[4] ), - .send__val( route_units__send__val[4] ) - ); - - RingRouteUnitRTL__6d1cae73cf31e9a0 route_units__5 - ( - .clk( route_units__clk[5] ), - .pos( route_units__pos[5] ), - .reset( route_units__reset[5] ), - .recv__msg( route_units__recv__msg[5] ), - .recv__rdy( route_units__recv__rdy[5] ), - .recv__val( route_units__recv__val[5] ), - .send__msg( route_units__send__msg[5] ), - .send__rdy( route_units__send__rdy[5] ), - .send__val( route_units__send__val[5] ) - ); - - //------------------------------------------------------------- - // End of component route_units[0:5] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component switch_units[0:2] - //------------------------------------------------------------- - - logic [0:0] switch_units__clk [0:2]; - logic [0:0] switch_units__reset [0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 switch_units__recv__msg [0:2][0:5]; - logic [0:0] switch_units__recv__rdy [0:2][0:5]; - logic [0:0] switch_units__recv__val [0:2][0:5]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 switch_units__send__msg [0:2]; - logic [0:0] switch_units__send__rdy [0:2]; - logic [0:0] switch_units__send__val [0:2]; - - SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__0 - ( - .clk( switch_units__clk[0] ), - .reset( switch_units__reset[0] ), - .recv__msg( switch_units__recv__msg[0] ), - .recv__rdy( switch_units__recv__rdy[0] ), - .recv__val( switch_units__recv__val[0] ), - .send__msg( switch_units__send__msg[0] ), - .send__rdy( switch_units__send__rdy[0] ), - .send__val( switch_units__send__val[0] ) - ); - - SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__1 - ( - .clk( switch_units__clk[1] ), - .reset( switch_units__reset[1] ), - .recv__msg( switch_units__recv__msg[1] ), - .recv__rdy( switch_units__recv__rdy[1] ), - .recv__val( switch_units__recv__val[1] ), - .send__msg( switch_units__send__msg[1] ), - .send__rdy( switch_units__send__rdy[1] ), - .send__val( switch_units__send__val[1] ) - ); - - SwitchUnitRTL__ae7d6e1a8f952f91 switch_units__2 - ( - .clk( switch_units__clk[2] ), - .reset( switch_units__reset[2] ), - .recv__msg( switch_units__recv__msg[2] ), - .recv__rdy( switch_units__recv__rdy[2] ), - .recv__val( switch_units__recv__val[2] ), - .send__msg( switch_units__send__msg[2] ), - .send__rdy( switch_units__send__rdy[2] ), - .send__val( switch_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component switch_units[0:2] - //------------------------------------------------------------- - - assign input_units__clk[0] = clk; - assign input_units__reset[0] = reset; - assign input_units__clk[1] = clk; - assign input_units__reset[1] = reset; - assign input_units__clk[2] = clk; - assign input_units__reset[2] = reset; - assign route_units__clk[0] = clk; - assign route_units__reset[0] = reset; - assign route_units__clk[1] = clk; - assign route_units__reset[1] = reset; - assign route_units__clk[2] = clk; - assign route_units__reset[2] = reset; - assign route_units__clk[3] = clk; - assign route_units__reset[3] = reset; - assign route_units__clk[4] = clk; - assign route_units__reset[4] = reset; - assign route_units__clk[5] = clk; - assign route_units__reset[5] = reset; - assign switch_units__clk[0] = clk; - assign switch_units__reset[0] = reset; - assign switch_units__clk[1] = clk; - assign switch_units__reset[1] = reset; - assign switch_units__clk[2] = clk; - assign switch_units__reset[2] = reset; - assign output_units__clk[0] = clk; - assign output_units__reset[0] = reset; - assign output_units__clk[1] = clk; - assign output_units__reset[1] = reset; - assign output_units__clk[2] = clk; - assign output_units__reset[2] = reset; - assign input_units__recv__en[0] = recv__en[0]; - assign input_units__recv__msg[0] = recv__msg[0]; - assign recv__yum[0][0] = input_units__recv__yum[0][0]; - assign recv__yum[0][1] = input_units__recv__yum[0][1]; - assign route_units__recv__msg[0] = input_units__send__msg[0][0]; - assign input_units__send__rdy[0][0] = route_units__recv__rdy[0]; - assign route_units__recv__val[0] = input_units__send__val[0][0]; - assign route_units__pos[0] = pos; - assign route_units__recv__msg[1] = input_units__send__msg[0][1]; - assign input_units__send__rdy[0][1] = route_units__recv__rdy[1]; - assign route_units__recv__val[1] = input_units__send__val[0][1]; - assign route_units__pos[1] = pos; - assign input_units__recv__en[1] = recv__en[1]; - assign input_units__recv__msg[1] = recv__msg[1]; - assign recv__yum[1][0] = input_units__recv__yum[1][0]; - assign recv__yum[1][1] = input_units__recv__yum[1][1]; - assign route_units__recv__msg[2] = input_units__send__msg[1][0]; - assign input_units__send__rdy[1][0] = route_units__recv__rdy[2]; - assign route_units__recv__val[2] = input_units__send__val[1][0]; - assign route_units__pos[2] = pos; - assign route_units__recv__msg[3] = input_units__send__msg[1][1]; - assign input_units__send__rdy[1][1] = route_units__recv__rdy[3]; - assign route_units__recv__val[3] = input_units__send__val[1][1]; - assign route_units__pos[3] = pos; - assign input_units__recv__en[2] = recv__en[2]; - assign input_units__recv__msg[2] = recv__msg[2]; - assign recv__yum[2][0] = input_units__recv__yum[2][0]; - assign recv__yum[2][1] = input_units__recv__yum[2][1]; - assign route_units__recv__msg[4] = input_units__send__msg[2][0]; - assign input_units__send__rdy[2][0] = route_units__recv__rdy[4]; - assign route_units__recv__val[4] = input_units__send__val[2][0]; - assign route_units__pos[4] = pos; - assign route_units__recv__msg[5] = input_units__send__msg[2][1]; - assign input_units__send__rdy[2][1] = route_units__recv__rdy[5]; - assign route_units__recv__val[5] = input_units__send__val[2][1]; - assign route_units__pos[5] = pos; - assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; - assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; - assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; - assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; - assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; - assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; - assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; - assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; - assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; - assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; - assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; - assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; - assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; - assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; - assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; - assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; - assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; - assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; - assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; - assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; - assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; - assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; - assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; - assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; - assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; - assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; - assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; - assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; - assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; - assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; - assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; - assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; - assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; - assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; - assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; - assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; - assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; - assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; - assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; - assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; - assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; - assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; - assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; - assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; - assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; - assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; - assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; - assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; - assign switch_units__recv__msg[1][5] = route_units__send__msg[5][1]; - assign route_units__send__rdy[5][1] = switch_units__recv__rdy[1][5]; - assign switch_units__recv__val[1][5] = route_units__send__val[5][1]; - assign switch_units__recv__msg[2][5] = route_units__send__msg[5][2]; - assign route_units__send__rdy[5][2] = switch_units__recv__rdy[2][5]; - assign switch_units__recv__val[2][5] = route_units__send__val[5][2]; - assign output_units__recv__msg[0] = switch_units__send__msg[0]; - assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; - assign output_units__recv__val[0] = switch_units__send__val[0]; - assign send__en[0] = output_units__send__en[0]; - assign send__msg[0] = output_units__send__msg[0]; - assign output_units__send__yum[0][0] = send__yum[0][0]; - assign output_units__send__yum[0][1] = send__yum[0][1]; - assign output_units__recv__msg[1] = switch_units__send__msg[1]; - assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; - assign output_units__recv__val[1] = switch_units__send__val[1]; - assign send__en[1] = output_units__send__en[1]; - assign send__msg[1] = output_units__send__msg[1]; - assign output_units__send__yum[1][0] = send__yum[1][0]; - assign output_units__send__yum[1][1] = send__yum[1][1]; - assign output_units__recv__msg[2] = switch_units__send__msg[2]; - assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; - assign output_units__recv__val[2] = switch_units__send__val[2]; - assign send__en[2] = output_units__send__en[2]; - assign send__msg[2] = output_units__send__msg[2]; - assign output_units__send__yum[2][0] = send__yum[2][0]; - assign output_units__send__yum[2][1] = send__yum[2][1]; - -endmodule - - -// PyMTL Component RegEnRst Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py - -module RegEnRst__Type_Bits2__reset_value_1 -( - input logic [0:0] clk , - input logic [0:0] en , - input logic [1:0] in_ , - output logic [1:0] out , - input logic [0:0] reset -); - localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 - // @update_ff - // def up_regenrst(): - // if s.reset: s.out <<= reset_value - // elif s.en: s.out <<= s.in_ - - always_ff @(posedge clk) begin : up_regenrst - if ( reset ) begin - out <= 2'( __const__reset_value_at_up_regenrst ); - end - else if ( en ) begin - out <= in_; - end - end - -endmodule - - -// PyMTL Component RoundRobinArbiterEn Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py - -module RoundRobinArbiterEn__nreqs_2 -( - input logic [0:0] clk , - input logic [0:0] en , - output logic [1:0] grants , - input logic [1:0] reqs , - input logic [0:0] reset -); - localparam logic [1:0] __const__nreqs_at_comb_reqs_int = 2'd2; - localparam logic [2:0] __const__nreqsX2_at_comb_reqs_int = 3'd4; - localparam logic [1:0] __const__nreqs_at_comb_grants = 2'd2; - localparam logic [1:0] __const__nreqs_at_comb_priority_int = 2'd2; - localparam logic [2:0] __const__nreqsX2_at_comb_priority_int = 3'd4; - localparam logic [2:0] __const__nreqsX2_at_comb_kills = 3'd4; - localparam logic [2:0] __const__nreqsX2_at_comb_grants_int = 3'd4; - logic [3:0] grants_int; - logic [4:0] kills; - logic [0:0] priority_en; - logic [3:0] priority_int; - logic [3:0] reqs_int; - //------------------------------------------------------------- - // Component priority_reg - //------------------------------------------------------------- - - logic [0:0] priority_reg__clk; - logic [0:0] priority_reg__en; - logic [1:0] priority_reg__in_; - logic [1:0] priority_reg__out; - logic [0:0] priority_reg__reset; - - RegEnRst__Type_Bits2__reset_value_1 priority_reg - ( - .clk( priority_reg__clk ), - .en( priority_reg__en ), - .in_( priority_reg__in_ ), - .out( priority_reg__out ), - .reset( priority_reg__reset ) - ); - - //------------------------------------------------------------- - // End of component priority_reg - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 - // @update - // def comb_grants(): - // for i in range( nreqs ): - // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] - - always_comb begin : comb_grants - for ( int unsigned i = 1'd0; i < 2'( __const__nreqs_at_comb_grants ); i += 1'd1 ) - grants[1'(i)] = grants_int[2'(i)] | grants_int[2'( __const__nreqs_at_comb_grants ) + 2'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 - // @update - // def comb_grants_int(): - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.grants_int[i] @= s.reqs_int[i] - // else: - // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] - - always_comb begin : comb_grants_int - for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) - if ( priority_int[2'(i)] ) begin - grants_int[2'(i)] = reqs_int[2'(i)]; - end - else - grants_int[2'(i)] = ( ~kills[3'(i)] ) & reqs_int[2'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 - // @update - // def comb_kills(): - // s.kills[0] @= 1 - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.kills[i+1] @= s.reqs_int[i] - // else: - // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) - - always_comb begin : comb_kills - kills[3'd0] = 1'd1; - for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) - if ( priority_int[2'(i)] ) begin - kills[3'(i) + 3'd1] = reqs_int[2'(i)]; - end - else - kills[3'(i) + 3'd1] = kills[3'(i)] | ( ( ~kills[3'(i)] ) & reqs_int[2'(i)] ); - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 - // @update - // def comb_priority_en(): - // s.priority_en @= ( s.grants != 0 ) & s.en - - always_comb begin : comb_priority_en - priority_en = ( grants != 2'd0 ) & en; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 - // @update - // def comb_priority_int(): - // s.priority_int[ 0:nreqs ] @= s.priority_reg.out - // s.priority_int[nreqs:nreqsX2] @= 0 - - always_comb begin : comb_priority_int - priority_int[2'd1:2'd0] = priority_reg__out; - priority_int[2'd3:2'( __const__nreqs_at_comb_priority_int )] = 2'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 - // @update - // def comb_reqs_int(): - // s.reqs_int [ 0:nreqs ] @= s.reqs - // s.reqs_int [nreqs:nreqsX2] @= s.reqs - - always_comb begin : comb_reqs_int - reqs_int[2'd1:2'd0] = reqs; - reqs_int[2'd3:2'( __const__nreqs_at_comb_reqs_int )] = reqs; - end - - assign priority_reg__clk = clk; - assign priority_reg__reset = reset; - assign priority_reg__en = priority_en; - assign priority_reg__in_[1:1] = grants[0:0]; - assign priority_reg__in_[0:0] = grants[1:1]; - -endmodule - - -// PyMTL Component BypassQueueCtrlRTL Definition -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueCtrlRTL__num_entries_2 -( - input logic [0:0] clk , - output logic [1:0] count , - output logic [0:0] mux_sel , - output logic [0:0] raddr , - output logic [0:0] recv_rdy , - input logic [0:0] recv_val , - input logic [0:0] reset , - input logic [0:0] send_rdy , - output logic [0:0] send_val , - output logic [0:0] waddr , - output logic [0:0] wen -); - localparam logic [1:0] __const__num_entries_at__lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy = 2'd2; - localparam logic [1:0] __const__num_entries_at_up_reg = 2'd2; - logic [0:0] head; - logic [0:0] recv_xfer; - logic [0:0] send_xfer; - logic [0:0] tail; - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:645 - // s.mux_sel //= lambda: s.count == 0 - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_mux_sel - mux_sel = count == 2'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:642 - // s.recv_rdy //= lambda: s.count < num_entries - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy - recv_rdy = count < 2'( __const__num_entries_at__lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_rdy ); - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:647 - // s.recv_xfer //= lambda: s.recv_val & s.recv_rdy - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_recv_xfer - recv_xfer = recv_val & recv_rdy; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:643 - // s.send_val //= lambda: (s.count > 0) | s.recv_val - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_send_val - send_val = ( count > 2'd0 ) | recv_val; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:648 - // s.send_xfer //= lambda: s.send_val & s.send_rdy - - always_comb begin : _lambda__s_dut_cgra_0__ctrl_ring_send_adp_0__buffers_0__ctrl_send_xfer - send_xfer = send_val & send_rdy; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py:650 - // @update_ff - // def up_reg(): - // - // if s.reset: - // s.head <<= 0 - // s.tail <<= 0 - // s.count <<= 0 - // - // else: - // if s.recv_xfer: - // s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 - // - // if s.send_xfer: - // s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 - // - // if s.recv_xfer & ~s.send_xfer: - // s.count <<= s.count + 1 - // if ~s.recv_xfer & s.send_xfer: - // s.count <<= s.count - 1 - - always_ff @(posedge clk) begin : up_reg - if ( reset ) begin - head <= 1'd0; - tail <= 1'd0; - count <= 2'd0; - end - else begin - if ( recv_xfer ) begin - tail <= ( tail < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? tail + 1'd1 : 1'd0; - end - if ( send_xfer ) begin - head <= ( head < ( 1'( __const__num_entries_at_up_reg ) - 1'd1 ) ) ? head + 1'd1 : 1'd0; - end - if ( recv_xfer & ( ~send_xfer ) ) begin - count <= count + 2'd1; - end - if ( ( ~recv_xfer ) & send_xfer ) begin - count <= count - 2'd1; - end - end - end - - assign wen = recv_xfer; - assign waddr = tail; - assign raddr = head; - -endmodule - - -// PyMTL Component Mux Definition -// Full name: Mux__Type_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ninputs_2 -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__4754a371c6cda085 -( - input logic [0:0] clk , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 in_ [0:1], - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 out , - input logic [0:0] reset , - input logic [0:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component BypassQueueDpathRTL Definition -// Full name: BypassQueueDpathRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueDpathRTL__a1c7a5a18a302c36 -( - input logic [0:0] clk , - input logic [0:0] mux_sel , - input logic [0:0] raddr , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_msg , - input logic [0:0] reset , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__in_ [0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 mux__out; - logic [0:0] mux__reset; - logic [0:0] mux__sel; - - Mux__4754a371c6cda085 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__80167091524f71e4 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - assign mux__clk = clk; - assign mux__reset = reset; - assign mux__sel = mux_sel; - assign mux__in_[0] = rf__rdata[0]; - assign mux__in_[1] = recv_msg; - assign send_msg = mux__out; - -endmodule - - -// PyMTL Component BypassQueueRTL Definition -// Full name: BypassQueueRTL__EntryType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueRTL__a1c7a5a18a302c36 -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__mux_sel; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - BypassQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .mux_sel( ctrl__mux_sel ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__mux_sel; - logic [0:0] dpath__raddr; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__recv_msg; - logic [0:0] dpath__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - BypassQueueDpathRTL__a1c7a5a18a302c36 dpath - ( - .clk( dpath__clk ), - .mux_sel( dpath__mux_sel ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign dpath__mux_sel = ctrl__mux_sel; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign count = ctrl__count; - assign dpath__recv_msg = recv__msg; - assign send__msg = dpath__send_msg; - -endmodule - - -// PyMTL Component Encoder Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py - -module Encoder__in_nbits_2__out_nbits_1 -( - input logic [0:0] clk , - input logic [1:0] in_ , - output logic [0:0] out , - input logic [0:0] reset -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 - // @update - // def encode(): - // s.out @= 0 - // for i in range( s.in_nbits ): - // if s.in_[i]: - // s.out @= i - - always_comb begin : encode - out = 1'd0; - for ( int unsigned i = 1'd0; i < 2'd2; i += 1'd1 ) - if ( in_[1'(i)] ) begin - out = 1'(i); - end - end - -endmodule - - -// PyMTL Component CreditRecvRTL2SendRTL Definition -// Full name: CreditRecvRTL2SendRTL__MsgType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__vc_2__credit_line_2__QType_BypassQueueRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py - -module CreditRecvRTL2SendRTL__0d4276a185d5c616 -( - input logic [0:0] clk , - input logic [0:0] reset , - input logic [0:0] recv__en , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg , - output logic [0:0] recv__yum [0:1] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [1:0] __const__vc_at_up_enq = 2'd2; - localparam logic [1:0] __const__vc_at_up_deq_and_send = 2'd2; - localparam logic [1:0] __const__vc_at_up_yummy = 2'd2; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [1:0] arbiter__grants; - logic [1:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_2 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component buffers[0:1] - //------------------------------------------------------------- - - logic [0:0] buffers__clk [0:1]; - logic [1:0] buffers__count [0:1]; - logic [0:0] buffers__reset [0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__recv__msg [0:1]; - logic [0:0] buffers__recv__rdy [0:1]; - logic [0:0] buffers__recv__val [0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 buffers__send__msg [0:1]; - logic [0:0] buffers__send__rdy [0:1]; - logic [0:0] buffers__send__val [0:1]; - - BypassQueueRTL__a1c7a5a18a302c36 buffers__0 - ( - .clk( buffers__clk[0] ), - .count( buffers__count[0] ), - .reset( buffers__reset[0] ), - .recv__msg( buffers__recv__msg[0] ), - .recv__rdy( buffers__recv__rdy[0] ), - .recv__val( buffers__recv__val[0] ), - .send__msg( buffers__send__msg[0] ), - .send__rdy( buffers__send__rdy[0] ), - .send__val( buffers__send__val[0] ) - ); - - BypassQueueRTL__a1c7a5a18a302c36 buffers__1 - ( - .clk( buffers__clk[1] ), - .count( buffers__count[1] ), - .reset( buffers__reset[1] ), - .recv__msg( buffers__recv__msg[1] ), - .recv__rdy( buffers__recv__rdy[1] ), - .recv__val( buffers__recv__val[1] ), - .send__msg( buffers__send__msg[1] ), - .send__rdy( buffers__send__rdy[1] ), - .send__val( buffers__send__val[1] ) - ); - - //------------------------------------------------------------- - // End of component buffers[0:1] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [1:0] encoder__in_; - logic [0:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_2__out_nbits_1 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:205 - // @update - // def up_deq_and_send(): - // for i in range( vc ): - // s.buffers[i].send.rdy @= 0 - // - // s.send.msg @= s.buffers[ s.encoder.out ].send.msg - // - // if s.arbiter.grants > 0: - // s.send.val @= 1 - // s.buffers[ s.encoder.out ].send.rdy @= s.send.rdy - // else: - // s.send.val @= 0 - - always_comb begin : up_deq_and_send - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_deq_and_send ); i += 1'd1 ) - buffers__send__rdy[1'(i)] = 1'd0; - send__msg = buffers__send__msg[encoder__out]; - if ( arbiter__grants > 2'd0 ) begin - send__val = 1'd1; - buffers__send__rdy[encoder__out] = send__rdy; - end - else - send__val = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:194 - // @update - // def up_enq(): - // if s.recv.en: - // for i in range( vc ): - // s.buffers[i].recv.val @= ( s.recv.msg.vc_id == i ) - // else: - // for i in range( vc ): - // s.buffers[i].recv.val @= 0 - - always_comb begin : up_enq - if ( recv__en ) begin - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) - buffers__recv__val[1'(i)] = recv__msg.vc_id == 1'(i); - end - else - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_enq ); i += 1'd1 ) - buffers__recv__val[1'(i)] = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ocnlib/ifcs/CreditIfc.py:218 - // @update - // def up_yummy(): - // for i in range( vc ): - // s.recv.yum[i] @= s.buffers[i].send.val & s.buffers[i].send.rdy - - always_comb begin : up_yummy - for ( int unsigned i = 1'd0; i < 2'( __const__vc_at_up_yummy ); i += 1'd1 ) - recv__yum[1'(i)] = buffers__send__val[1'(i)] & buffers__send__rdy[1'(i)]; - end - - assign buffers__clk[0] = clk; - assign buffers__reset[0] = reset; - assign buffers__clk[1] = clk; - assign buffers__reset[1] = reset; - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign buffers__recv__msg[0] = recv__msg; - assign arbiter__reqs[0:0] = buffers__send__val[0]; - assign buffers__recv__msg[1] = recv__msg; - assign arbiter__reqs[1:1] = buffers__send__val[1]; - assign encoder__in_ = arbiter__grants; - assign arbiter__en = send__val; - -endmodule - - -// PyMTL Component RingNetworkRTL Definition -// Full name: RingNetworkRTL__PacketType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__PositionType_Bits5__num_routers_17__chl_lat_1__vc_2__credit_line_2 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingNetworkRTL.py - -module RingNetworkRTL__8866f4e00dbc912a -( - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv__msg [0:16] , - output logic [0:0] recv__rdy [0:16] , - input logic [0:0] recv__val [0:16] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send__msg [0:16] , - input logic [0:0] send__rdy [0:16] , - output logic [0:0] send__val [0:16] -); - //------------------------------------------------------------- - // Component recv_adp[0:16] - //------------------------------------------------------------- - - logic [0:0] recv_adp__clk [0:16]; - logic [0:0] recv_adp__reset [0:16]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_adp__recv__msg [0:16]; - logic [0:0] recv_adp__recv__rdy [0:16]; - logic [0:0] recv_adp__recv__val [0:16]; - logic [0:0] recv_adp__send__en [0:16]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_adp__send__msg [0:16]; - logic [0:0] recv_adp__send__yum [0:16][0:1]; - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__0 - ( - .clk( recv_adp__clk[0] ), - .reset( recv_adp__reset[0] ), - .recv__msg( recv_adp__recv__msg[0] ), - .recv__rdy( recv_adp__recv__rdy[0] ), - .recv__val( recv_adp__recv__val[0] ), - .send__en( recv_adp__send__en[0] ), - .send__msg( recv_adp__send__msg[0] ), - .send__yum( recv_adp__send__yum[0] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__1 - ( - .clk( recv_adp__clk[1] ), - .reset( recv_adp__reset[1] ), - .recv__msg( recv_adp__recv__msg[1] ), - .recv__rdy( recv_adp__recv__rdy[1] ), - .recv__val( recv_adp__recv__val[1] ), - .send__en( recv_adp__send__en[1] ), - .send__msg( recv_adp__send__msg[1] ), - .send__yum( recv_adp__send__yum[1] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__2 - ( - .clk( recv_adp__clk[2] ), - .reset( recv_adp__reset[2] ), - .recv__msg( recv_adp__recv__msg[2] ), - .recv__rdy( recv_adp__recv__rdy[2] ), - .recv__val( recv_adp__recv__val[2] ), - .send__en( recv_adp__send__en[2] ), - .send__msg( recv_adp__send__msg[2] ), - .send__yum( recv_adp__send__yum[2] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__3 - ( - .clk( recv_adp__clk[3] ), - .reset( recv_adp__reset[3] ), - .recv__msg( recv_adp__recv__msg[3] ), - .recv__rdy( recv_adp__recv__rdy[3] ), - .recv__val( recv_adp__recv__val[3] ), - .send__en( recv_adp__send__en[3] ), - .send__msg( recv_adp__send__msg[3] ), - .send__yum( recv_adp__send__yum[3] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__4 - ( - .clk( recv_adp__clk[4] ), - .reset( recv_adp__reset[4] ), - .recv__msg( recv_adp__recv__msg[4] ), - .recv__rdy( recv_adp__recv__rdy[4] ), - .recv__val( recv_adp__recv__val[4] ), - .send__en( recv_adp__send__en[4] ), - .send__msg( recv_adp__send__msg[4] ), - .send__yum( recv_adp__send__yum[4] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__5 - ( - .clk( recv_adp__clk[5] ), - .reset( recv_adp__reset[5] ), - .recv__msg( recv_adp__recv__msg[5] ), - .recv__rdy( recv_adp__recv__rdy[5] ), - .recv__val( recv_adp__recv__val[5] ), - .send__en( recv_adp__send__en[5] ), - .send__msg( recv_adp__send__msg[5] ), - .send__yum( recv_adp__send__yum[5] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__6 - ( - .clk( recv_adp__clk[6] ), - .reset( recv_adp__reset[6] ), - .recv__msg( recv_adp__recv__msg[6] ), - .recv__rdy( recv_adp__recv__rdy[6] ), - .recv__val( recv_adp__recv__val[6] ), - .send__en( recv_adp__send__en[6] ), - .send__msg( recv_adp__send__msg[6] ), - .send__yum( recv_adp__send__yum[6] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__7 - ( - .clk( recv_adp__clk[7] ), - .reset( recv_adp__reset[7] ), - .recv__msg( recv_adp__recv__msg[7] ), - .recv__rdy( recv_adp__recv__rdy[7] ), - .recv__val( recv_adp__recv__val[7] ), - .send__en( recv_adp__send__en[7] ), - .send__msg( recv_adp__send__msg[7] ), - .send__yum( recv_adp__send__yum[7] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__8 - ( - .clk( recv_adp__clk[8] ), - .reset( recv_adp__reset[8] ), - .recv__msg( recv_adp__recv__msg[8] ), - .recv__rdy( recv_adp__recv__rdy[8] ), - .recv__val( recv_adp__recv__val[8] ), - .send__en( recv_adp__send__en[8] ), - .send__msg( recv_adp__send__msg[8] ), - .send__yum( recv_adp__send__yum[8] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__9 - ( - .clk( recv_adp__clk[9] ), - .reset( recv_adp__reset[9] ), - .recv__msg( recv_adp__recv__msg[9] ), - .recv__rdy( recv_adp__recv__rdy[9] ), - .recv__val( recv_adp__recv__val[9] ), - .send__en( recv_adp__send__en[9] ), - .send__msg( recv_adp__send__msg[9] ), - .send__yum( recv_adp__send__yum[9] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__10 - ( - .clk( recv_adp__clk[10] ), - .reset( recv_adp__reset[10] ), - .recv__msg( recv_adp__recv__msg[10] ), - .recv__rdy( recv_adp__recv__rdy[10] ), - .recv__val( recv_adp__recv__val[10] ), - .send__en( recv_adp__send__en[10] ), - .send__msg( recv_adp__send__msg[10] ), - .send__yum( recv_adp__send__yum[10] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__11 - ( - .clk( recv_adp__clk[11] ), - .reset( recv_adp__reset[11] ), - .recv__msg( recv_adp__recv__msg[11] ), - .recv__rdy( recv_adp__recv__rdy[11] ), - .recv__val( recv_adp__recv__val[11] ), - .send__en( recv_adp__send__en[11] ), - .send__msg( recv_adp__send__msg[11] ), - .send__yum( recv_adp__send__yum[11] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__12 - ( - .clk( recv_adp__clk[12] ), - .reset( recv_adp__reset[12] ), - .recv__msg( recv_adp__recv__msg[12] ), - .recv__rdy( recv_adp__recv__rdy[12] ), - .recv__val( recv_adp__recv__val[12] ), - .send__en( recv_adp__send__en[12] ), - .send__msg( recv_adp__send__msg[12] ), - .send__yum( recv_adp__send__yum[12] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__13 - ( - .clk( recv_adp__clk[13] ), - .reset( recv_adp__reset[13] ), - .recv__msg( recv_adp__recv__msg[13] ), - .recv__rdy( recv_adp__recv__rdy[13] ), - .recv__val( recv_adp__recv__val[13] ), - .send__en( recv_adp__send__en[13] ), - .send__msg( recv_adp__send__msg[13] ), - .send__yum( recv_adp__send__yum[13] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__14 - ( - .clk( recv_adp__clk[14] ), - .reset( recv_adp__reset[14] ), - .recv__msg( recv_adp__recv__msg[14] ), - .recv__rdy( recv_adp__recv__rdy[14] ), - .recv__val( recv_adp__recv__val[14] ), - .send__en( recv_adp__send__en[14] ), - .send__msg( recv_adp__send__msg[14] ), - .send__yum( recv_adp__send__yum[14] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__15 - ( - .clk( recv_adp__clk[15] ), - .reset( recv_adp__reset[15] ), - .recv__msg( recv_adp__recv__msg[15] ), - .recv__rdy( recv_adp__recv__rdy[15] ), - .recv__val( recv_adp__recv__val[15] ), - .send__en( recv_adp__send__en[15] ), - .send__msg( recv_adp__send__msg[15] ), - .send__yum( recv_adp__send__yum[15] ) - ); - - RecvRTL2CreditSendRTL__6d49e584a986d10c recv_adp__16 - ( - .clk( recv_adp__clk[16] ), - .reset( recv_adp__reset[16] ), - .recv__msg( recv_adp__recv__msg[16] ), - .recv__rdy( recv_adp__recv__rdy[16] ), - .recv__val( recv_adp__recv__val[16] ), - .send__en( recv_adp__send__en[16] ), - .send__msg( recv_adp__send__msg[16] ), - .send__yum( recv_adp__send__yum[16] ) - ); - - //------------------------------------------------------------- - // End of component recv_adp[0:16] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component routers[0:16] - //------------------------------------------------------------- - - logic [0:0] routers__clk [0:16]; - logic [4:0] routers__pos [0:16]; - logic [0:0] routers__reset [0:16]; - logic [0:0] routers__recv__en [0:16][0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 routers__recv__msg [0:16][0:2]; - logic [0:0] routers__recv__yum [0:16][0:2][0:1]; - logic [0:0] routers__send__en [0:16][0:2]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 routers__send__msg [0:16][0:2]; - logic [0:0] routers__send__yum [0:16][0:2][0:1]; - - RingRouterRTL__6e670e447e1766e0 routers__0 - ( - .clk( routers__clk[0] ), - .pos( routers__pos[0] ), - .reset( routers__reset[0] ), - .recv__en( routers__recv__en[0] ), - .recv__msg( routers__recv__msg[0] ), - .recv__yum( routers__recv__yum[0] ), - .send__en( routers__send__en[0] ), - .send__msg( routers__send__msg[0] ), - .send__yum( routers__send__yum[0] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__1 - ( - .clk( routers__clk[1] ), - .pos( routers__pos[1] ), - .reset( routers__reset[1] ), - .recv__en( routers__recv__en[1] ), - .recv__msg( routers__recv__msg[1] ), - .recv__yum( routers__recv__yum[1] ), - .send__en( routers__send__en[1] ), - .send__msg( routers__send__msg[1] ), - .send__yum( routers__send__yum[1] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__2 - ( - .clk( routers__clk[2] ), - .pos( routers__pos[2] ), - .reset( routers__reset[2] ), - .recv__en( routers__recv__en[2] ), - .recv__msg( routers__recv__msg[2] ), - .recv__yum( routers__recv__yum[2] ), - .send__en( routers__send__en[2] ), - .send__msg( routers__send__msg[2] ), - .send__yum( routers__send__yum[2] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__3 - ( - .clk( routers__clk[3] ), - .pos( routers__pos[3] ), - .reset( routers__reset[3] ), - .recv__en( routers__recv__en[3] ), - .recv__msg( routers__recv__msg[3] ), - .recv__yum( routers__recv__yum[3] ), - .send__en( routers__send__en[3] ), - .send__msg( routers__send__msg[3] ), - .send__yum( routers__send__yum[3] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__4 - ( - .clk( routers__clk[4] ), - .pos( routers__pos[4] ), - .reset( routers__reset[4] ), - .recv__en( routers__recv__en[4] ), - .recv__msg( routers__recv__msg[4] ), - .recv__yum( routers__recv__yum[4] ), - .send__en( routers__send__en[4] ), - .send__msg( routers__send__msg[4] ), - .send__yum( routers__send__yum[4] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__5 - ( - .clk( routers__clk[5] ), - .pos( routers__pos[5] ), - .reset( routers__reset[5] ), - .recv__en( routers__recv__en[5] ), - .recv__msg( routers__recv__msg[5] ), - .recv__yum( routers__recv__yum[5] ), - .send__en( routers__send__en[5] ), - .send__msg( routers__send__msg[5] ), - .send__yum( routers__send__yum[5] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__6 - ( - .clk( routers__clk[6] ), - .pos( routers__pos[6] ), - .reset( routers__reset[6] ), - .recv__en( routers__recv__en[6] ), - .recv__msg( routers__recv__msg[6] ), - .recv__yum( routers__recv__yum[6] ), - .send__en( routers__send__en[6] ), - .send__msg( routers__send__msg[6] ), - .send__yum( routers__send__yum[6] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__7 - ( - .clk( routers__clk[7] ), - .pos( routers__pos[7] ), - .reset( routers__reset[7] ), - .recv__en( routers__recv__en[7] ), - .recv__msg( routers__recv__msg[7] ), - .recv__yum( routers__recv__yum[7] ), - .send__en( routers__send__en[7] ), - .send__msg( routers__send__msg[7] ), - .send__yum( routers__send__yum[7] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__8 - ( - .clk( routers__clk[8] ), - .pos( routers__pos[8] ), - .reset( routers__reset[8] ), - .recv__en( routers__recv__en[8] ), - .recv__msg( routers__recv__msg[8] ), - .recv__yum( routers__recv__yum[8] ), - .send__en( routers__send__en[8] ), - .send__msg( routers__send__msg[8] ), - .send__yum( routers__send__yum[8] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__9 - ( - .clk( routers__clk[9] ), - .pos( routers__pos[9] ), - .reset( routers__reset[9] ), - .recv__en( routers__recv__en[9] ), - .recv__msg( routers__recv__msg[9] ), - .recv__yum( routers__recv__yum[9] ), - .send__en( routers__send__en[9] ), - .send__msg( routers__send__msg[9] ), - .send__yum( routers__send__yum[9] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__10 - ( - .clk( routers__clk[10] ), - .pos( routers__pos[10] ), - .reset( routers__reset[10] ), - .recv__en( routers__recv__en[10] ), - .recv__msg( routers__recv__msg[10] ), - .recv__yum( routers__recv__yum[10] ), - .send__en( routers__send__en[10] ), - .send__msg( routers__send__msg[10] ), - .send__yum( routers__send__yum[10] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__11 - ( - .clk( routers__clk[11] ), - .pos( routers__pos[11] ), - .reset( routers__reset[11] ), - .recv__en( routers__recv__en[11] ), - .recv__msg( routers__recv__msg[11] ), - .recv__yum( routers__recv__yum[11] ), - .send__en( routers__send__en[11] ), - .send__msg( routers__send__msg[11] ), - .send__yum( routers__send__yum[11] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__12 - ( - .clk( routers__clk[12] ), - .pos( routers__pos[12] ), - .reset( routers__reset[12] ), - .recv__en( routers__recv__en[12] ), - .recv__msg( routers__recv__msg[12] ), - .recv__yum( routers__recv__yum[12] ), - .send__en( routers__send__en[12] ), - .send__msg( routers__send__msg[12] ), - .send__yum( routers__send__yum[12] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__13 - ( - .clk( routers__clk[13] ), - .pos( routers__pos[13] ), - .reset( routers__reset[13] ), - .recv__en( routers__recv__en[13] ), - .recv__msg( routers__recv__msg[13] ), - .recv__yum( routers__recv__yum[13] ), - .send__en( routers__send__en[13] ), - .send__msg( routers__send__msg[13] ), - .send__yum( routers__send__yum[13] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__14 - ( - .clk( routers__clk[14] ), - .pos( routers__pos[14] ), - .reset( routers__reset[14] ), - .recv__en( routers__recv__en[14] ), - .recv__msg( routers__recv__msg[14] ), - .recv__yum( routers__recv__yum[14] ), - .send__en( routers__send__en[14] ), - .send__msg( routers__send__msg[14] ), - .send__yum( routers__send__yum[14] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__15 - ( - .clk( routers__clk[15] ), - .pos( routers__pos[15] ), - .reset( routers__reset[15] ), - .recv__en( routers__recv__en[15] ), - .recv__msg( routers__recv__msg[15] ), - .recv__yum( routers__recv__yum[15] ), - .send__en( routers__send__en[15] ), - .send__msg( routers__send__msg[15] ), - .send__yum( routers__send__yum[15] ) - ); - - RingRouterRTL__6e670e447e1766e0 routers__16 - ( - .clk( routers__clk[16] ), - .pos( routers__pos[16] ), - .reset( routers__reset[16] ), - .recv__en( routers__recv__en[16] ), - .recv__msg( routers__recv__msg[16] ), - .recv__yum( routers__recv__yum[16] ), - .send__en( routers__send__en[16] ), - .send__msg( routers__send__msg[16] ), - .send__yum( routers__send__yum[16] ) - ); - - //------------------------------------------------------------- - // End of component routers[0:16] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component send_adp[0:16] - //------------------------------------------------------------- - - logic [0:0] send_adp__clk [0:16]; - logic [0:0] send_adp__reset [0:16]; - logic [0:0] send_adp__recv__en [0:16]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_adp__recv__msg [0:16]; - logic [0:0] send_adp__recv__yum [0:16][0:1]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_adp__send__msg [0:16]; - logic [0:0] send_adp__send__rdy [0:16]; - logic [0:0] send_adp__send__val [0:16]; - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__0 - ( - .clk( send_adp__clk[0] ), - .reset( send_adp__reset[0] ), - .recv__en( send_adp__recv__en[0] ), - .recv__msg( send_adp__recv__msg[0] ), - .recv__yum( send_adp__recv__yum[0] ), - .send__msg( send_adp__send__msg[0] ), - .send__rdy( send_adp__send__rdy[0] ), - .send__val( send_adp__send__val[0] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__1 - ( - .clk( send_adp__clk[1] ), - .reset( send_adp__reset[1] ), - .recv__en( send_adp__recv__en[1] ), - .recv__msg( send_adp__recv__msg[1] ), - .recv__yum( send_adp__recv__yum[1] ), - .send__msg( send_adp__send__msg[1] ), - .send__rdy( send_adp__send__rdy[1] ), - .send__val( send_adp__send__val[1] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__2 - ( - .clk( send_adp__clk[2] ), - .reset( send_adp__reset[2] ), - .recv__en( send_adp__recv__en[2] ), - .recv__msg( send_adp__recv__msg[2] ), - .recv__yum( send_adp__recv__yum[2] ), - .send__msg( send_adp__send__msg[2] ), - .send__rdy( send_adp__send__rdy[2] ), - .send__val( send_adp__send__val[2] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__3 - ( - .clk( send_adp__clk[3] ), - .reset( send_adp__reset[3] ), - .recv__en( send_adp__recv__en[3] ), - .recv__msg( send_adp__recv__msg[3] ), - .recv__yum( send_adp__recv__yum[3] ), - .send__msg( send_adp__send__msg[3] ), - .send__rdy( send_adp__send__rdy[3] ), - .send__val( send_adp__send__val[3] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__4 - ( - .clk( send_adp__clk[4] ), - .reset( send_adp__reset[4] ), - .recv__en( send_adp__recv__en[4] ), - .recv__msg( send_adp__recv__msg[4] ), - .recv__yum( send_adp__recv__yum[4] ), - .send__msg( send_adp__send__msg[4] ), - .send__rdy( send_adp__send__rdy[4] ), - .send__val( send_adp__send__val[4] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__5 - ( - .clk( send_adp__clk[5] ), - .reset( send_adp__reset[5] ), - .recv__en( send_adp__recv__en[5] ), - .recv__msg( send_adp__recv__msg[5] ), - .recv__yum( send_adp__recv__yum[5] ), - .send__msg( send_adp__send__msg[5] ), - .send__rdy( send_adp__send__rdy[5] ), - .send__val( send_adp__send__val[5] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__6 - ( - .clk( send_adp__clk[6] ), - .reset( send_adp__reset[6] ), - .recv__en( send_adp__recv__en[6] ), - .recv__msg( send_adp__recv__msg[6] ), - .recv__yum( send_adp__recv__yum[6] ), - .send__msg( send_adp__send__msg[6] ), - .send__rdy( send_adp__send__rdy[6] ), - .send__val( send_adp__send__val[6] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__7 - ( - .clk( send_adp__clk[7] ), - .reset( send_adp__reset[7] ), - .recv__en( send_adp__recv__en[7] ), - .recv__msg( send_adp__recv__msg[7] ), - .recv__yum( send_adp__recv__yum[7] ), - .send__msg( send_adp__send__msg[7] ), - .send__rdy( send_adp__send__rdy[7] ), - .send__val( send_adp__send__val[7] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__8 - ( - .clk( send_adp__clk[8] ), - .reset( send_adp__reset[8] ), - .recv__en( send_adp__recv__en[8] ), - .recv__msg( send_adp__recv__msg[8] ), - .recv__yum( send_adp__recv__yum[8] ), - .send__msg( send_adp__send__msg[8] ), - .send__rdy( send_adp__send__rdy[8] ), - .send__val( send_adp__send__val[8] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__9 - ( - .clk( send_adp__clk[9] ), - .reset( send_adp__reset[9] ), - .recv__en( send_adp__recv__en[9] ), - .recv__msg( send_adp__recv__msg[9] ), - .recv__yum( send_adp__recv__yum[9] ), - .send__msg( send_adp__send__msg[9] ), - .send__rdy( send_adp__send__rdy[9] ), - .send__val( send_adp__send__val[9] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__10 - ( - .clk( send_adp__clk[10] ), - .reset( send_adp__reset[10] ), - .recv__en( send_adp__recv__en[10] ), - .recv__msg( send_adp__recv__msg[10] ), - .recv__yum( send_adp__recv__yum[10] ), - .send__msg( send_adp__send__msg[10] ), - .send__rdy( send_adp__send__rdy[10] ), - .send__val( send_adp__send__val[10] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__11 - ( - .clk( send_adp__clk[11] ), - .reset( send_adp__reset[11] ), - .recv__en( send_adp__recv__en[11] ), - .recv__msg( send_adp__recv__msg[11] ), - .recv__yum( send_adp__recv__yum[11] ), - .send__msg( send_adp__send__msg[11] ), - .send__rdy( send_adp__send__rdy[11] ), - .send__val( send_adp__send__val[11] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__12 - ( - .clk( send_adp__clk[12] ), - .reset( send_adp__reset[12] ), - .recv__en( send_adp__recv__en[12] ), - .recv__msg( send_adp__recv__msg[12] ), - .recv__yum( send_adp__recv__yum[12] ), - .send__msg( send_adp__send__msg[12] ), - .send__rdy( send_adp__send__rdy[12] ), - .send__val( send_adp__send__val[12] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__13 - ( - .clk( send_adp__clk[13] ), - .reset( send_adp__reset[13] ), - .recv__en( send_adp__recv__en[13] ), - .recv__msg( send_adp__recv__msg[13] ), - .recv__yum( send_adp__recv__yum[13] ), - .send__msg( send_adp__send__msg[13] ), - .send__rdy( send_adp__send__rdy[13] ), - .send__val( send_adp__send__val[13] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__14 - ( - .clk( send_adp__clk[14] ), - .reset( send_adp__reset[14] ), - .recv__en( send_adp__recv__en[14] ), - .recv__msg( send_adp__recv__msg[14] ), - .recv__yum( send_adp__recv__yum[14] ), - .send__msg( send_adp__send__msg[14] ), - .send__rdy( send_adp__send__rdy[14] ), - .send__val( send_adp__send__val[14] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__15 - ( - .clk( send_adp__clk[15] ), - .reset( send_adp__reset[15] ), - .recv__en( send_adp__recv__en[15] ), - .recv__msg( send_adp__recv__msg[15] ), - .recv__yum( send_adp__recv__yum[15] ), - .send__msg( send_adp__send__msg[15] ), - .send__rdy( send_adp__send__rdy[15] ), - .send__val( send_adp__send__val[15] ) - ); - - CreditRecvRTL2SendRTL__0d4276a185d5c616 send_adp__16 - ( - .clk( send_adp__clk[16] ), - .reset( send_adp__reset[16] ), - .recv__en( send_adp__recv__en[16] ), - .recv__msg( send_adp__recv__msg[16] ), - .recv__yum( send_adp__recv__yum[16] ), - .send__msg( send_adp__send__msg[16] ), - .send__rdy( send_adp__send__rdy[16] ), - .send__val( send_adp__send__val[16] ) - ); - - //------------------------------------------------------------- - // End of component send_adp[0:16] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/ringnet/RingNetworkRTL.py:58 - // @update - // def up_pos(): - // for r in range( s.num_routers ): - // s.routers[r].pos @= r - - always_comb begin : up_pos - for ( int unsigned r = 1'd0; r < 5'd17; r += 1'd1 ) - routers__pos[5'(r)] = 5'(r); - end - - assign routers__clk[0] = clk; - assign routers__reset[0] = reset; - assign routers__clk[1] = clk; - assign routers__reset[1] = reset; - assign routers__clk[2] = clk; - assign routers__reset[2] = reset; - assign routers__clk[3] = clk; - assign routers__reset[3] = reset; - assign routers__clk[4] = clk; - assign routers__reset[4] = reset; - assign routers__clk[5] = clk; - assign routers__reset[5] = reset; - assign routers__clk[6] = clk; - assign routers__reset[6] = reset; - assign routers__clk[7] = clk; - assign routers__reset[7] = reset; - assign routers__clk[8] = clk; - assign routers__reset[8] = reset; - assign routers__clk[9] = clk; - assign routers__reset[9] = reset; - assign routers__clk[10] = clk; - assign routers__reset[10] = reset; - assign routers__clk[11] = clk; - assign routers__reset[11] = reset; - assign routers__clk[12] = clk; - assign routers__reset[12] = reset; - assign routers__clk[13] = clk; - assign routers__reset[13] = reset; - assign routers__clk[14] = clk; - assign routers__reset[14] = reset; - assign routers__clk[15] = clk; - assign routers__reset[15] = reset; - assign routers__clk[16] = clk; - assign routers__reset[16] = reset; - assign recv_adp__clk[0] = clk; - assign recv_adp__reset[0] = reset; - assign recv_adp__clk[1] = clk; - assign recv_adp__reset[1] = reset; - assign recv_adp__clk[2] = clk; - assign recv_adp__reset[2] = reset; - assign recv_adp__clk[3] = clk; - assign recv_adp__reset[3] = reset; - assign recv_adp__clk[4] = clk; - assign recv_adp__reset[4] = reset; - assign recv_adp__clk[5] = clk; - assign recv_adp__reset[5] = reset; - assign recv_adp__clk[6] = clk; - assign recv_adp__reset[6] = reset; - assign recv_adp__clk[7] = clk; - assign recv_adp__reset[7] = reset; - assign recv_adp__clk[8] = clk; - assign recv_adp__reset[8] = reset; - assign recv_adp__clk[9] = clk; - assign recv_adp__reset[9] = reset; - assign recv_adp__clk[10] = clk; - assign recv_adp__reset[10] = reset; - assign recv_adp__clk[11] = clk; - assign recv_adp__reset[11] = reset; - assign recv_adp__clk[12] = clk; - assign recv_adp__reset[12] = reset; - assign recv_adp__clk[13] = clk; - assign recv_adp__reset[13] = reset; - assign recv_adp__clk[14] = clk; - assign recv_adp__reset[14] = reset; - assign recv_adp__clk[15] = clk; - assign recv_adp__reset[15] = reset; - assign recv_adp__clk[16] = clk; - assign recv_adp__reset[16] = reset; - assign send_adp__clk[0] = clk; - assign send_adp__reset[0] = reset; - assign send_adp__clk[1] = clk; - assign send_adp__reset[1] = reset; - assign send_adp__clk[2] = clk; - assign send_adp__reset[2] = reset; - assign send_adp__clk[3] = clk; - assign send_adp__reset[3] = reset; - assign send_adp__clk[4] = clk; - assign send_adp__reset[4] = reset; - assign send_adp__clk[5] = clk; - assign send_adp__reset[5] = reset; - assign send_adp__clk[6] = clk; - assign send_adp__reset[6] = reset; - assign send_adp__clk[7] = clk; - assign send_adp__reset[7] = reset; - assign send_adp__clk[8] = clk; - assign send_adp__reset[8] = reset; - assign send_adp__clk[9] = clk; - assign send_adp__reset[9] = reset; - assign send_adp__clk[10] = clk; - assign send_adp__reset[10] = reset; - assign send_adp__clk[11] = clk; - assign send_adp__reset[11] = reset; - assign send_adp__clk[12] = clk; - assign send_adp__reset[12] = reset; - assign send_adp__clk[13] = clk; - assign send_adp__reset[13] = reset; - assign send_adp__clk[14] = clk; - assign send_adp__reset[14] = reset; - assign send_adp__clk[15] = clk; - assign send_adp__reset[15] = reset; - assign send_adp__clk[16] = clk; - assign send_adp__reset[16] = reset; - assign routers__recv__en[1][0] = routers__send__en[0][1]; - assign routers__recv__msg[1][0] = routers__send__msg[0][1]; - assign routers__send__yum[0][1][0] = routers__recv__yum[1][0][0]; - assign routers__send__yum[0][1][1] = routers__recv__yum[1][0][1]; - assign routers__recv__en[0][1] = routers__send__en[1][0]; - assign routers__recv__msg[0][1] = routers__send__msg[1][0]; - assign routers__send__yum[1][0][0] = routers__recv__yum[0][1][0]; - assign routers__send__yum[1][0][1] = routers__recv__yum[0][1][1]; - assign recv_adp__recv__msg[0] = recv__msg[0]; - assign recv__rdy[0] = recv_adp__recv__rdy[0]; - assign recv_adp__recv__val[0] = recv__val[0]; - assign routers__recv__en[0][2] = recv_adp__send__en[0]; - assign routers__recv__msg[0][2] = recv_adp__send__msg[0]; - assign recv_adp__send__yum[0][0] = routers__recv__yum[0][2][0]; - assign recv_adp__send__yum[0][1] = routers__recv__yum[0][2][1]; - assign send_adp__recv__en[0] = routers__send__en[0][2]; - assign send_adp__recv__msg[0] = routers__send__msg[0][2]; - assign routers__send__yum[0][2][0] = send_adp__recv__yum[0][0]; - assign routers__send__yum[0][2][1] = send_adp__recv__yum[0][1]; - assign send__msg[0] = send_adp__send__msg[0]; - assign send_adp__send__rdy[0] = send__rdy[0]; - assign send__val[0] = send_adp__send__val[0]; - assign routers__recv__en[2][0] = routers__send__en[1][1]; - assign routers__recv__msg[2][0] = routers__send__msg[1][1]; - assign routers__send__yum[1][1][0] = routers__recv__yum[2][0][0]; - assign routers__send__yum[1][1][1] = routers__recv__yum[2][0][1]; - assign routers__recv__en[1][1] = routers__send__en[2][0]; - assign routers__recv__msg[1][1] = routers__send__msg[2][0]; - assign routers__send__yum[2][0][0] = routers__recv__yum[1][1][0]; - assign routers__send__yum[2][0][1] = routers__recv__yum[1][1][1]; - assign recv_adp__recv__msg[1] = recv__msg[1]; - assign recv__rdy[1] = recv_adp__recv__rdy[1]; - assign recv_adp__recv__val[1] = recv__val[1]; - assign routers__recv__en[1][2] = recv_adp__send__en[1]; - assign routers__recv__msg[1][2] = recv_adp__send__msg[1]; - assign recv_adp__send__yum[1][0] = routers__recv__yum[1][2][0]; - assign recv_adp__send__yum[1][1] = routers__recv__yum[1][2][1]; - assign send_adp__recv__en[1] = routers__send__en[1][2]; - assign send_adp__recv__msg[1] = routers__send__msg[1][2]; - assign routers__send__yum[1][2][0] = send_adp__recv__yum[1][0]; - assign routers__send__yum[1][2][1] = send_adp__recv__yum[1][1]; - assign send__msg[1] = send_adp__send__msg[1]; - assign send_adp__send__rdy[1] = send__rdy[1]; - assign send__val[1] = send_adp__send__val[1]; - assign routers__recv__en[3][0] = routers__send__en[2][1]; - assign routers__recv__msg[3][0] = routers__send__msg[2][1]; - assign routers__send__yum[2][1][0] = routers__recv__yum[3][0][0]; - assign routers__send__yum[2][1][1] = routers__recv__yum[3][0][1]; - assign routers__recv__en[2][1] = routers__send__en[3][0]; - assign routers__recv__msg[2][1] = routers__send__msg[3][0]; - assign routers__send__yum[3][0][0] = routers__recv__yum[2][1][0]; - assign routers__send__yum[3][0][1] = routers__recv__yum[2][1][1]; - assign recv_adp__recv__msg[2] = recv__msg[2]; - assign recv__rdy[2] = recv_adp__recv__rdy[2]; - assign recv_adp__recv__val[2] = recv__val[2]; - assign routers__recv__en[2][2] = recv_adp__send__en[2]; - assign routers__recv__msg[2][2] = recv_adp__send__msg[2]; - assign recv_adp__send__yum[2][0] = routers__recv__yum[2][2][0]; - assign recv_adp__send__yum[2][1] = routers__recv__yum[2][2][1]; - assign send_adp__recv__en[2] = routers__send__en[2][2]; - assign send_adp__recv__msg[2] = routers__send__msg[2][2]; - assign routers__send__yum[2][2][0] = send_adp__recv__yum[2][0]; - assign routers__send__yum[2][2][1] = send_adp__recv__yum[2][1]; - assign send__msg[2] = send_adp__send__msg[2]; - assign send_adp__send__rdy[2] = send__rdy[2]; - assign send__val[2] = send_adp__send__val[2]; - assign routers__recv__en[4][0] = routers__send__en[3][1]; - assign routers__recv__msg[4][0] = routers__send__msg[3][1]; - assign routers__send__yum[3][1][0] = routers__recv__yum[4][0][0]; - assign routers__send__yum[3][1][1] = routers__recv__yum[4][0][1]; - assign routers__recv__en[3][1] = routers__send__en[4][0]; - assign routers__recv__msg[3][1] = routers__send__msg[4][0]; - assign routers__send__yum[4][0][0] = routers__recv__yum[3][1][0]; - assign routers__send__yum[4][0][1] = routers__recv__yum[3][1][1]; - assign recv_adp__recv__msg[3] = recv__msg[3]; - assign recv__rdy[3] = recv_adp__recv__rdy[3]; - assign recv_adp__recv__val[3] = recv__val[3]; - assign routers__recv__en[3][2] = recv_adp__send__en[3]; - assign routers__recv__msg[3][2] = recv_adp__send__msg[3]; - assign recv_adp__send__yum[3][0] = routers__recv__yum[3][2][0]; - assign recv_adp__send__yum[3][1] = routers__recv__yum[3][2][1]; - assign send_adp__recv__en[3] = routers__send__en[3][2]; - assign send_adp__recv__msg[3] = routers__send__msg[3][2]; - assign routers__send__yum[3][2][0] = send_adp__recv__yum[3][0]; - assign routers__send__yum[3][2][1] = send_adp__recv__yum[3][1]; - assign send__msg[3] = send_adp__send__msg[3]; - assign send_adp__send__rdy[3] = send__rdy[3]; - assign send__val[3] = send_adp__send__val[3]; - assign routers__recv__en[5][0] = routers__send__en[4][1]; - assign routers__recv__msg[5][0] = routers__send__msg[4][1]; - assign routers__send__yum[4][1][0] = routers__recv__yum[5][0][0]; - assign routers__send__yum[4][1][1] = routers__recv__yum[5][0][1]; - assign routers__recv__en[4][1] = routers__send__en[5][0]; - assign routers__recv__msg[4][1] = routers__send__msg[5][0]; - assign routers__send__yum[5][0][0] = routers__recv__yum[4][1][0]; - assign routers__send__yum[5][0][1] = routers__recv__yum[4][1][1]; - assign recv_adp__recv__msg[4] = recv__msg[4]; - assign recv__rdy[4] = recv_adp__recv__rdy[4]; - assign recv_adp__recv__val[4] = recv__val[4]; - assign routers__recv__en[4][2] = recv_adp__send__en[4]; - assign routers__recv__msg[4][2] = recv_adp__send__msg[4]; - assign recv_adp__send__yum[4][0] = routers__recv__yum[4][2][0]; - assign recv_adp__send__yum[4][1] = routers__recv__yum[4][2][1]; - assign send_adp__recv__en[4] = routers__send__en[4][2]; - assign send_adp__recv__msg[4] = routers__send__msg[4][2]; - assign routers__send__yum[4][2][0] = send_adp__recv__yum[4][0]; - assign routers__send__yum[4][2][1] = send_adp__recv__yum[4][1]; - assign send__msg[4] = send_adp__send__msg[4]; - assign send_adp__send__rdy[4] = send__rdy[4]; - assign send__val[4] = send_adp__send__val[4]; - assign routers__recv__en[6][0] = routers__send__en[5][1]; - assign routers__recv__msg[6][0] = routers__send__msg[5][1]; - assign routers__send__yum[5][1][0] = routers__recv__yum[6][0][0]; - assign routers__send__yum[5][1][1] = routers__recv__yum[6][0][1]; - assign routers__recv__en[5][1] = routers__send__en[6][0]; - assign routers__recv__msg[5][1] = routers__send__msg[6][0]; - assign routers__send__yum[6][0][0] = routers__recv__yum[5][1][0]; - assign routers__send__yum[6][0][1] = routers__recv__yum[5][1][1]; - assign recv_adp__recv__msg[5] = recv__msg[5]; - assign recv__rdy[5] = recv_adp__recv__rdy[5]; - assign recv_adp__recv__val[5] = recv__val[5]; - assign routers__recv__en[5][2] = recv_adp__send__en[5]; - assign routers__recv__msg[5][2] = recv_adp__send__msg[5]; - assign recv_adp__send__yum[5][0] = routers__recv__yum[5][2][0]; - assign recv_adp__send__yum[5][1] = routers__recv__yum[5][2][1]; - assign send_adp__recv__en[5] = routers__send__en[5][2]; - assign send_adp__recv__msg[5] = routers__send__msg[5][2]; - assign routers__send__yum[5][2][0] = send_adp__recv__yum[5][0]; - assign routers__send__yum[5][2][1] = send_adp__recv__yum[5][1]; - assign send__msg[5] = send_adp__send__msg[5]; - assign send_adp__send__rdy[5] = send__rdy[5]; - assign send__val[5] = send_adp__send__val[5]; - assign routers__recv__en[7][0] = routers__send__en[6][1]; - assign routers__recv__msg[7][0] = routers__send__msg[6][1]; - assign routers__send__yum[6][1][0] = routers__recv__yum[7][0][0]; - assign routers__send__yum[6][1][1] = routers__recv__yum[7][0][1]; - assign routers__recv__en[6][1] = routers__send__en[7][0]; - assign routers__recv__msg[6][1] = routers__send__msg[7][0]; - assign routers__send__yum[7][0][0] = routers__recv__yum[6][1][0]; - assign routers__send__yum[7][0][1] = routers__recv__yum[6][1][1]; - assign recv_adp__recv__msg[6] = recv__msg[6]; - assign recv__rdy[6] = recv_adp__recv__rdy[6]; - assign recv_adp__recv__val[6] = recv__val[6]; - assign routers__recv__en[6][2] = recv_adp__send__en[6]; - assign routers__recv__msg[6][2] = recv_adp__send__msg[6]; - assign recv_adp__send__yum[6][0] = routers__recv__yum[6][2][0]; - assign recv_adp__send__yum[6][1] = routers__recv__yum[6][2][1]; - assign send_adp__recv__en[6] = routers__send__en[6][2]; - assign send_adp__recv__msg[6] = routers__send__msg[6][2]; - assign routers__send__yum[6][2][0] = send_adp__recv__yum[6][0]; - assign routers__send__yum[6][2][1] = send_adp__recv__yum[6][1]; - assign send__msg[6] = send_adp__send__msg[6]; - assign send_adp__send__rdy[6] = send__rdy[6]; - assign send__val[6] = send_adp__send__val[6]; - assign routers__recv__en[8][0] = routers__send__en[7][1]; - assign routers__recv__msg[8][0] = routers__send__msg[7][1]; - assign routers__send__yum[7][1][0] = routers__recv__yum[8][0][0]; - assign routers__send__yum[7][1][1] = routers__recv__yum[8][0][1]; - assign routers__recv__en[7][1] = routers__send__en[8][0]; - assign routers__recv__msg[7][1] = routers__send__msg[8][0]; - assign routers__send__yum[8][0][0] = routers__recv__yum[7][1][0]; - assign routers__send__yum[8][0][1] = routers__recv__yum[7][1][1]; - assign recv_adp__recv__msg[7] = recv__msg[7]; - assign recv__rdy[7] = recv_adp__recv__rdy[7]; - assign recv_adp__recv__val[7] = recv__val[7]; - assign routers__recv__en[7][2] = recv_adp__send__en[7]; - assign routers__recv__msg[7][2] = recv_adp__send__msg[7]; - assign recv_adp__send__yum[7][0] = routers__recv__yum[7][2][0]; - assign recv_adp__send__yum[7][1] = routers__recv__yum[7][2][1]; - assign send_adp__recv__en[7] = routers__send__en[7][2]; - assign send_adp__recv__msg[7] = routers__send__msg[7][2]; - assign routers__send__yum[7][2][0] = send_adp__recv__yum[7][0]; - assign routers__send__yum[7][2][1] = send_adp__recv__yum[7][1]; - assign send__msg[7] = send_adp__send__msg[7]; - assign send_adp__send__rdy[7] = send__rdy[7]; - assign send__val[7] = send_adp__send__val[7]; - assign routers__recv__en[9][0] = routers__send__en[8][1]; - assign routers__recv__msg[9][0] = routers__send__msg[8][1]; - assign routers__send__yum[8][1][0] = routers__recv__yum[9][0][0]; - assign routers__send__yum[8][1][1] = routers__recv__yum[9][0][1]; - assign routers__recv__en[8][1] = routers__send__en[9][0]; - assign routers__recv__msg[8][1] = routers__send__msg[9][0]; - assign routers__send__yum[9][0][0] = routers__recv__yum[8][1][0]; - assign routers__send__yum[9][0][1] = routers__recv__yum[8][1][1]; - assign recv_adp__recv__msg[8] = recv__msg[8]; - assign recv__rdy[8] = recv_adp__recv__rdy[8]; - assign recv_adp__recv__val[8] = recv__val[8]; - assign routers__recv__en[8][2] = recv_adp__send__en[8]; - assign routers__recv__msg[8][2] = recv_adp__send__msg[8]; - assign recv_adp__send__yum[8][0] = routers__recv__yum[8][2][0]; - assign recv_adp__send__yum[8][1] = routers__recv__yum[8][2][1]; - assign send_adp__recv__en[8] = routers__send__en[8][2]; - assign send_adp__recv__msg[8] = routers__send__msg[8][2]; - assign routers__send__yum[8][2][0] = send_adp__recv__yum[8][0]; - assign routers__send__yum[8][2][1] = send_adp__recv__yum[8][1]; - assign send__msg[8] = send_adp__send__msg[8]; - assign send_adp__send__rdy[8] = send__rdy[8]; - assign send__val[8] = send_adp__send__val[8]; - assign routers__recv__en[10][0] = routers__send__en[9][1]; - assign routers__recv__msg[10][0] = routers__send__msg[9][1]; - assign routers__send__yum[9][1][0] = routers__recv__yum[10][0][0]; - assign routers__send__yum[9][1][1] = routers__recv__yum[10][0][1]; - assign routers__recv__en[9][1] = routers__send__en[10][0]; - assign routers__recv__msg[9][1] = routers__send__msg[10][0]; - assign routers__send__yum[10][0][0] = routers__recv__yum[9][1][0]; - assign routers__send__yum[10][0][1] = routers__recv__yum[9][1][1]; - assign recv_adp__recv__msg[9] = recv__msg[9]; - assign recv__rdy[9] = recv_adp__recv__rdy[9]; - assign recv_adp__recv__val[9] = recv__val[9]; - assign routers__recv__en[9][2] = recv_adp__send__en[9]; - assign routers__recv__msg[9][2] = recv_adp__send__msg[9]; - assign recv_adp__send__yum[9][0] = routers__recv__yum[9][2][0]; - assign recv_adp__send__yum[9][1] = routers__recv__yum[9][2][1]; - assign send_adp__recv__en[9] = routers__send__en[9][2]; - assign send_adp__recv__msg[9] = routers__send__msg[9][2]; - assign routers__send__yum[9][2][0] = send_adp__recv__yum[9][0]; - assign routers__send__yum[9][2][1] = send_adp__recv__yum[9][1]; - assign send__msg[9] = send_adp__send__msg[9]; - assign send_adp__send__rdy[9] = send__rdy[9]; - assign send__val[9] = send_adp__send__val[9]; - assign routers__recv__en[11][0] = routers__send__en[10][1]; - assign routers__recv__msg[11][0] = routers__send__msg[10][1]; - assign routers__send__yum[10][1][0] = routers__recv__yum[11][0][0]; - assign routers__send__yum[10][1][1] = routers__recv__yum[11][0][1]; - assign routers__recv__en[10][1] = routers__send__en[11][0]; - assign routers__recv__msg[10][1] = routers__send__msg[11][0]; - assign routers__send__yum[11][0][0] = routers__recv__yum[10][1][0]; - assign routers__send__yum[11][0][1] = routers__recv__yum[10][1][1]; - assign recv_adp__recv__msg[10] = recv__msg[10]; - assign recv__rdy[10] = recv_adp__recv__rdy[10]; - assign recv_adp__recv__val[10] = recv__val[10]; - assign routers__recv__en[10][2] = recv_adp__send__en[10]; - assign routers__recv__msg[10][2] = recv_adp__send__msg[10]; - assign recv_adp__send__yum[10][0] = routers__recv__yum[10][2][0]; - assign recv_adp__send__yum[10][1] = routers__recv__yum[10][2][1]; - assign send_adp__recv__en[10] = routers__send__en[10][2]; - assign send_adp__recv__msg[10] = routers__send__msg[10][2]; - assign routers__send__yum[10][2][0] = send_adp__recv__yum[10][0]; - assign routers__send__yum[10][2][1] = send_adp__recv__yum[10][1]; - assign send__msg[10] = send_adp__send__msg[10]; - assign send_adp__send__rdy[10] = send__rdy[10]; - assign send__val[10] = send_adp__send__val[10]; - assign routers__recv__en[12][0] = routers__send__en[11][1]; - assign routers__recv__msg[12][0] = routers__send__msg[11][1]; - assign routers__send__yum[11][1][0] = routers__recv__yum[12][0][0]; - assign routers__send__yum[11][1][1] = routers__recv__yum[12][0][1]; - assign routers__recv__en[11][1] = routers__send__en[12][0]; - assign routers__recv__msg[11][1] = routers__send__msg[12][0]; - assign routers__send__yum[12][0][0] = routers__recv__yum[11][1][0]; - assign routers__send__yum[12][0][1] = routers__recv__yum[11][1][1]; - assign recv_adp__recv__msg[11] = recv__msg[11]; - assign recv__rdy[11] = recv_adp__recv__rdy[11]; - assign recv_adp__recv__val[11] = recv__val[11]; - assign routers__recv__en[11][2] = recv_adp__send__en[11]; - assign routers__recv__msg[11][2] = recv_adp__send__msg[11]; - assign recv_adp__send__yum[11][0] = routers__recv__yum[11][2][0]; - assign recv_adp__send__yum[11][1] = routers__recv__yum[11][2][1]; - assign send_adp__recv__en[11] = routers__send__en[11][2]; - assign send_adp__recv__msg[11] = routers__send__msg[11][2]; - assign routers__send__yum[11][2][0] = send_adp__recv__yum[11][0]; - assign routers__send__yum[11][2][1] = send_adp__recv__yum[11][1]; - assign send__msg[11] = send_adp__send__msg[11]; - assign send_adp__send__rdy[11] = send__rdy[11]; - assign send__val[11] = send_adp__send__val[11]; - assign routers__recv__en[13][0] = routers__send__en[12][1]; - assign routers__recv__msg[13][0] = routers__send__msg[12][1]; - assign routers__send__yum[12][1][0] = routers__recv__yum[13][0][0]; - assign routers__send__yum[12][1][1] = routers__recv__yum[13][0][1]; - assign routers__recv__en[12][1] = routers__send__en[13][0]; - assign routers__recv__msg[12][1] = routers__send__msg[13][0]; - assign routers__send__yum[13][0][0] = routers__recv__yum[12][1][0]; - assign routers__send__yum[13][0][1] = routers__recv__yum[12][1][1]; - assign recv_adp__recv__msg[12] = recv__msg[12]; - assign recv__rdy[12] = recv_adp__recv__rdy[12]; - assign recv_adp__recv__val[12] = recv__val[12]; - assign routers__recv__en[12][2] = recv_adp__send__en[12]; - assign routers__recv__msg[12][2] = recv_adp__send__msg[12]; - assign recv_adp__send__yum[12][0] = routers__recv__yum[12][2][0]; - assign recv_adp__send__yum[12][1] = routers__recv__yum[12][2][1]; - assign send_adp__recv__en[12] = routers__send__en[12][2]; - assign send_adp__recv__msg[12] = routers__send__msg[12][2]; - assign routers__send__yum[12][2][0] = send_adp__recv__yum[12][0]; - assign routers__send__yum[12][2][1] = send_adp__recv__yum[12][1]; - assign send__msg[12] = send_adp__send__msg[12]; - assign send_adp__send__rdy[12] = send__rdy[12]; - assign send__val[12] = send_adp__send__val[12]; - assign routers__recv__en[14][0] = routers__send__en[13][1]; - assign routers__recv__msg[14][0] = routers__send__msg[13][1]; - assign routers__send__yum[13][1][0] = routers__recv__yum[14][0][0]; - assign routers__send__yum[13][1][1] = routers__recv__yum[14][0][1]; - assign routers__recv__en[13][1] = routers__send__en[14][0]; - assign routers__recv__msg[13][1] = routers__send__msg[14][0]; - assign routers__send__yum[14][0][0] = routers__recv__yum[13][1][0]; - assign routers__send__yum[14][0][1] = routers__recv__yum[13][1][1]; - assign recv_adp__recv__msg[13] = recv__msg[13]; - assign recv__rdy[13] = recv_adp__recv__rdy[13]; - assign recv_adp__recv__val[13] = recv__val[13]; - assign routers__recv__en[13][2] = recv_adp__send__en[13]; - assign routers__recv__msg[13][2] = recv_adp__send__msg[13]; - assign recv_adp__send__yum[13][0] = routers__recv__yum[13][2][0]; - assign recv_adp__send__yum[13][1] = routers__recv__yum[13][2][1]; - assign send_adp__recv__en[13] = routers__send__en[13][2]; - assign send_adp__recv__msg[13] = routers__send__msg[13][2]; - assign routers__send__yum[13][2][0] = send_adp__recv__yum[13][0]; - assign routers__send__yum[13][2][1] = send_adp__recv__yum[13][1]; - assign send__msg[13] = send_adp__send__msg[13]; - assign send_adp__send__rdy[13] = send__rdy[13]; - assign send__val[13] = send_adp__send__val[13]; - assign routers__recv__en[15][0] = routers__send__en[14][1]; - assign routers__recv__msg[15][0] = routers__send__msg[14][1]; - assign routers__send__yum[14][1][0] = routers__recv__yum[15][0][0]; - assign routers__send__yum[14][1][1] = routers__recv__yum[15][0][1]; - assign routers__recv__en[14][1] = routers__send__en[15][0]; - assign routers__recv__msg[14][1] = routers__send__msg[15][0]; - assign routers__send__yum[15][0][0] = routers__recv__yum[14][1][0]; - assign routers__send__yum[15][0][1] = routers__recv__yum[14][1][1]; - assign recv_adp__recv__msg[14] = recv__msg[14]; - assign recv__rdy[14] = recv_adp__recv__rdy[14]; - assign recv_adp__recv__val[14] = recv__val[14]; - assign routers__recv__en[14][2] = recv_adp__send__en[14]; - assign routers__recv__msg[14][2] = recv_adp__send__msg[14]; - assign recv_adp__send__yum[14][0] = routers__recv__yum[14][2][0]; - assign recv_adp__send__yum[14][1] = routers__recv__yum[14][2][1]; - assign send_adp__recv__en[14] = routers__send__en[14][2]; - assign send_adp__recv__msg[14] = routers__send__msg[14][2]; - assign routers__send__yum[14][2][0] = send_adp__recv__yum[14][0]; - assign routers__send__yum[14][2][1] = send_adp__recv__yum[14][1]; - assign send__msg[14] = send_adp__send__msg[14]; - assign send_adp__send__rdy[14] = send__rdy[14]; - assign send__val[14] = send_adp__send__val[14]; - assign routers__recv__en[16][0] = routers__send__en[15][1]; - assign routers__recv__msg[16][0] = routers__send__msg[15][1]; - assign routers__send__yum[15][1][0] = routers__recv__yum[16][0][0]; - assign routers__send__yum[15][1][1] = routers__recv__yum[16][0][1]; - assign routers__recv__en[15][1] = routers__send__en[16][0]; - assign routers__recv__msg[15][1] = routers__send__msg[16][0]; - assign routers__send__yum[16][0][0] = routers__recv__yum[15][1][0]; - assign routers__send__yum[16][0][1] = routers__recv__yum[15][1][1]; - assign recv_adp__recv__msg[15] = recv__msg[15]; - assign recv__rdy[15] = recv_adp__recv__rdy[15]; - assign recv_adp__recv__val[15] = recv__val[15]; - assign routers__recv__en[15][2] = recv_adp__send__en[15]; - assign routers__recv__msg[15][2] = recv_adp__send__msg[15]; - assign recv_adp__send__yum[15][0] = routers__recv__yum[15][2][0]; - assign recv_adp__send__yum[15][1] = routers__recv__yum[15][2][1]; - assign send_adp__recv__en[15] = routers__send__en[15][2]; - assign send_adp__recv__msg[15] = routers__send__msg[15][2]; - assign routers__send__yum[15][2][0] = send_adp__recv__yum[15][0]; - assign routers__send__yum[15][2][1] = send_adp__recv__yum[15][1]; - assign send__msg[15] = send_adp__send__msg[15]; - assign send_adp__send__rdy[15] = send__rdy[15]; - assign send__val[15] = send_adp__send__val[15]; - assign routers__recv__en[0][0] = routers__send__en[16][1]; - assign routers__recv__msg[0][0] = routers__send__msg[16][1]; - assign routers__send__yum[16][1][0] = routers__recv__yum[0][0][0]; - assign routers__send__yum[16][1][1] = routers__recv__yum[0][0][1]; - assign routers__recv__en[16][1] = routers__send__en[0][0]; - assign routers__recv__msg[16][1] = routers__send__msg[0][0]; - assign routers__send__yum[0][0][0] = routers__recv__yum[16][1][0]; - assign routers__send__yum[0][0][1] = routers__recv__yum[16][1][1]; - assign recv_adp__recv__msg[16] = recv__msg[16]; - assign recv__rdy[16] = recv_adp__recv__rdy[16]; - assign recv_adp__recv__val[16] = recv__val[16]; - assign routers__recv__en[16][2] = recv_adp__send__en[16]; - assign routers__recv__msg[16][2] = recv_adp__send__msg[16]; - assign recv_adp__send__yum[16][0] = routers__recv__yum[16][2][0]; - assign recv_adp__send__yum[16][1] = routers__recv__yum[16][2][1]; - assign send_adp__recv__en[16] = routers__send__en[16][2]; - assign send_adp__recv__msg[16] = routers__send__msg[16][2]; - assign routers__send__yum[16][2][0] = send_adp__recv__yum[16][0]; - assign routers__send__yum[16][2][1] = send_adp__recv__yum[16][1]; - assign send__msg[16] = send_adp__send__msg[16]; - assign send_adp__send__rdy[16] = send__rdy[16]; - assign send__val[16] = send_adp__send__val[16]; - -endmodule - - -// PyMTL Component ChannelRTL Definition -// Full name: ChannelRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_NormalQueueRTL__latency_0 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py - -module ChannelRTL__c31a2b1c86c6a129 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - assign send__msg = recv__msg; - assign recv__rdy = send__rdy; - assign send__val = recv__val; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__nregs_16__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__bd22936ec5812d0d -( - input logic [0:0] clk , - input logic [3:0] raddr [0:0], - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rdata [0:0], - input logic [0:0] reset , - input logic [3:0] waddr [0:0], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 regs [0:15]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component DataMemWrapperRTL Definition -// Full name: DataMemWrapperRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__MemReadType_MemAccessPacket_8_3_128__43c148781d2f2a57__MemWriteType_MemAccessPacket_8_3_128__43c148781d2f2a57__MemResponseType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__global_data_mem_size_128__per_bank_data_mem_size_16__is_combinational_True -// At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py - -module DataMemWrapperRTL__33e0a5b37976e571 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_rd__msg , - output logic [0:0] recv_rd__rdy , - input logic [0:0] recv_rd__val , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_wr__msg , - output logic [0:0] recv_wr__rdy , - input logic [0:0] recv_wr__val , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [4:0] __const__per_bank_data_mem_size_at_request_memory = 5'd16; - logic [6:0] streaming_rd_addr; - MemAccessPacket_8_3_128__43c148781d2f2a57 streaming_rd_read_reqeust; - logic [0:0] streaming_rd_status; - //------------------------------------------------------------- - // Component channel_rd - //------------------------------------------------------------- - - logic [0:0] channel_rd__clk; - logic [0:0] channel_rd__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 channel_rd__recv__msg; - logic [0:0] channel_rd__recv__rdy; - logic [0:0] channel_rd__recv__val; - MemAccessPacket_8_3_128__43c148781d2f2a57 channel_rd__send__msg; - logic [0:0] channel_rd__send__rdy; - logic [0:0] channel_rd__send__val; - - ChannelRTL__c31a2b1c86c6a129 channel_rd - ( - .clk( channel_rd__clk ), - .reset( channel_rd__reset ), - .recv__msg( channel_rd__recv__msg ), - .recv__rdy( channel_rd__recv__rdy ), - .recv__val( channel_rd__recv__val ), - .send__msg( channel_rd__send__msg ), - .send__rdy( channel_rd__send__rdy ), - .send__val( channel_rd__send__val ) - ); - - //------------------------------------------------------------- - // End of component channel_rd - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component channel_wr - //------------------------------------------------------------- - - logic [0:0] channel_wr__clk; - logic [0:0] channel_wr__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 channel_wr__recv__msg; - logic [0:0] channel_wr__recv__rdy; - logic [0:0] channel_wr__recv__val; - MemAccessPacket_8_3_128__43c148781d2f2a57 channel_wr__send__msg; - logic [0:0] channel_wr__send__rdy; - logic [0:0] channel_wr__send__val; - - ChannelRTL__c31a2b1c86c6a129 channel_wr - ( - .clk( channel_wr__clk ), - .reset( channel_wr__reset ), - .recv__msg( channel_wr__recv__msg ), - .recv__rdy( channel_wr__recv__rdy ), - .recv__val( channel_wr__recv__val ), - .send__msg( channel_wr__send__msg ), - .send__rdy( channel_wr__send__rdy ), - .send__val( channel_wr__send__val ) - ); - - //------------------------------------------------------------- - // End of component channel_wr - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component memory - //------------------------------------------------------------- - - logic [0:0] memory__clk; - logic [3:0] memory__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 memory__rdata [0:0]; - logic [0:0] memory__reset; - logic [3:0] memory__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 memory__wdata [0:0]; - logic [0:0] memory__wen [0:0]; - - RegisterFile__bd22936ec5812d0d memory - ( - .clk( memory__clk ), - .raddr( memory__raddr ), - .rdata( memory__rdata ), - .reset( memory__reset ), - .waddr( memory__waddr ), - .wdata( memory__wdata ), - .wen( memory__wen ) - ); - - //------------------------------------------------------------- - // End of component memory - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:76 - // @update - // def compose_send_msg(): - // s.send.msg @= MemResponseType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) - // # TODO: change to pipe's out's wen. - // # Streaming read example: - // # At cycle 0, s.channel_rd issues one single streaming read request (indicated by - // # s.channel_rd.send.msg.streaming_rd = 1) with s.channel_rd.send.msg.addr = 2, - // # s.channel_rd.send.msg.streaming_rd_stride = 2, and s.channel_rd.send.msg.streaming_rd_end_addr = 6. - // # Then s.send will return the multiple response data from addr=2, addr=4, and addr=6 - // # at cycle 0, cycle 1, and cycle 2, respectively. - // if s.streaming_rd_status: - // s.send.msg.src @= s.streaming_rd_read_reqeust.dst - // s.send.msg.dst @= s.streaming_rd_read_reqeust.src - // s.send.msg.addr @= s.streaming_rd_addr - // s.send.msg.data @= s.memory.rdata[0] - // s.send.msg.src_cgra @= s.streaming_rd_read_reqeust.src_cgra - // s.send.msg.src_tile @= s.streaming_rd_read_reqeust.src_tile - // s.send.msg.remote_src_port @= s.streaming_rd_read_reqeust.remote_src_port - // elif s.channel_rd.send.val: - // s.send.msg.src @= s.channel_rd.send.msg.dst - // s.send.msg.dst @= s.channel_rd.send.msg.src - // s.send.msg.addr @= s.channel_rd.send.msg.addr - // s.send.msg.data @= s.memory.rdata[0] - // s.send.msg.src_cgra @= s.channel_rd.send.msg.src_cgra - // s.send.msg.src_tile @= s.channel_rd.send.msg.src_tile - // s.send.msg.remote_src_port @= s.channel_rd.send.msg.remote_src_port - - always_comb begin : compose_send_msg - send__msg = { 2'd0, 3'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; - if ( streaming_rd_status ) begin - send__msg.src = streaming_rd_read_reqeust.dst; - send__msg.dst = streaming_rd_read_reqeust.src; - send__msg.addr = streaming_rd_addr; - send__msg.data = memory__rdata[1'd0]; - send__msg.src_cgra = streaming_rd_read_reqeust.src_cgra; - send__msg.src_tile = streaming_rd_read_reqeust.src_tile; - send__msg.remote_src_port = streaming_rd_read_reqeust.remote_src_port; - end - else if ( channel_rd__send__val ) begin - send__msg.src = channel_rd__send__msg.dst; - send__msg.dst = channel_rd__send__msg.src; - send__msg.addr = channel_rd__send__msg.addr; - send__msg.data = memory__rdata[1'd0]; - send__msg.src_cgra = channel_rd__send__msg.src_cgra; - send__msg.src_tile = channel_rd__send__msg.src_tile; - send__msg.remote_src_port = channel_rd__send__msg.remote_src_port; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:123 - // @update - // def notify_channel_rdy(): - // # TODO: change to SRAM's rdy when replacing register file - // # with SRAM. - // if s.streaming_rd_status: - // # Issue one streaming request at one time. - // s.channel_rd.send.rdy @= 0 - // else: - // s.channel_rd.send.rdy @= s.send.rdy - // s.channel_wr.send.rdy @= 1 - - always_comb begin : notify_channel_rdy - if ( streaming_rd_status ) begin - channel_rd__send__rdy = 1'd0; - end - else - channel_rd__send__rdy = send__rdy; - channel_wr__send__rdy = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:134 - // @update - // def notify_send_val(): - // # TODO: change to SRAM's valid when replacing register file - // # with SRAM. - // if s.streaming_rd_status: - // # Keep sending read data during streaming status. - // s.send.val @= 1 - // else: - // s.send.val @= s.channel_rd.send.val - - always_comb begin : notify_send_val - if ( streaming_rd_status ) begin - send__val = 1'd1; - end - else - send__val = channel_rd__send__val; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:103 - // @update - // def request_memory(): - // # Default values. - // s.memory.wen[0] @= 0 - // s.memory.raddr[0] @= PerBankAddrType(0) - // s.memory.waddr[0] @= PerBankAddrType(0) - // s.memory.wdata[0] @= DataType(0, 0, 0, 0) - // - // if s.streaming_rd_status: - // s.memory.raddr[0] @= \ - // trunc(s.streaming_rd_addr % per_bank_data_mem_size, PerBankAddrType) - // if s.channel_rd.send.val: - // s.memory.raddr[0] @= \ - // trunc(s.channel_rd.send.msg.addr % per_bank_data_mem_size, PerBankAddrType) - // if s.channel_wr.send.val: - // s.memory.waddr[0] @= \ - // trunc(s.channel_wr.send.msg.addr % per_bank_data_mem_size, PerBankAddrType) - // s.memory.wdata[0] @= s.channel_wr.send.msg.data - // s.memory.wen[0] @= 1 - - always_comb begin : request_memory - memory__wen[1'd0] = 1'd0; - memory__raddr[1'd0] = 4'd0; - memory__waddr[1'd0] = 4'd0; - memory__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - if ( streaming_rd_status ) begin - memory__raddr[1'd0] = 4'(streaming_rd_addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); - end - if ( channel_rd__send__val ) begin - memory__raddr[1'd0] = 4'(channel_rd__send__msg.addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); - end - if ( channel_wr__send__val ) begin - memory__waddr[1'd0] = 4'(channel_wr__send__msg.addr % 7'( __const__per_bank_data_mem_size_at_request_memory )); - memory__wdata[1'd0] = channel_wr__send__msg.data; - memory__wen[1'd0] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemWrapperRTL.py:63 - // @update_ff - // def update_streaming_rd_regs(): - // if s.channel_rd.send.val & s.channel_rd.send.msg.streaming_rd: - // s.streaming_rd_status <<= 1 - // s.streaming_rd_addr <<= s.channel_rd.send.msg.addr + s.channel_rd.send.msg.streaming_rd_stride - // s.streaming_rd_read_reqeust <<= s.channel_rd.send.msg - // elif s.streaming_rd_addr == s.streaming_rd_read_reqeust.streaming_rd_end_addr: - // s.streaming_rd_status <<= 0 - // s.streaming_rd_addr <<= GlobalAddrType(0) - // s.streaming_rd_read_reqeust <<= MemReadType() - // else: - // s.streaming_rd_addr <<= s.streaming_rd_addr + s.streaming_rd_read_reqeust.streaming_rd_stride - - always_ff @(posedge clk) begin : update_streaming_rd_regs - if ( channel_rd__send__val & channel_rd__send__msg.streaming_rd ) begin - streaming_rd_status <= 1'd1; - streaming_rd_addr <= channel_rd__send__msg.addr + channel_rd__send__msg.streaming_rd_stride; - streaming_rd_read_reqeust <= channel_rd__send__msg; - end - else if ( streaming_rd_addr == streaming_rd_read_reqeust.streaming_rd_end_addr ) begin - streaming_rd_status <= 1'd0; - streaming_rd_addr <= 7'd0; - streaming_rd_read_reqeust <= { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; - end - else - streaming_rd_addr <= streaming_rd_addr + streaming_rd_read_reqeust.streaming_rd_stride; - end - - assign memory__clk = clk; - assign memory__reset = reset; - assign channel_rd__clk = clk; - assign channel_rd__reset = reset; - assign channel_wr__clk = clk; - assign channel_wr__reset = reset; - assign channel_rd__recv__msg = recv_rd__msg; - assign recv_rd__rdy = channel_rd__recv__rdy; - assign channel_rd__recv__val = recv_rd__val; - assign channel_wr__recv__msg = recv_wr__msg; - assign recv_wr__rdy = channel_wr__recv__rdy; - assign channel_wr__recv__val = recv_wr__val; - -endmodule - - -// PyMTL Component Mux Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_2 -( - input logic [0:0] clk , - input MemAccessPacket_8_3_128__43c148781d2f2a57 in_ [0:1], - output MemAccessPacket_8_3_128__43c148781d2f2a57 out , - input logic [0:0] reset , - input logic [0:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__7305dd76cfb05fd9 -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output MemAccessPacket_8_3_128__43c148781d2f2a57 rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input MemAccessPacket_8_3_128__43c148781d2f2a57 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - MemAccessPacket_8_3_128__43c148781d2f2a57 regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component BypassQueueDpathRTL Definition -// Full name: BypassQueueDpathRTL__EntryType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueDpathRTL__4eac613e5285098c -( - input logic [0:0] clk , - input logic [0:0] mux_sel , - input logic [0:0] raddr , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv_msg , - input logic [0:0] reset , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - MemAccessPacket_8_3_128__43c148781d2f2a57 mux__in_ [0:1]; - MemAccessPacket_8_3_128__43c148781d2f2a57 mux__out; - logic [0:0] mux__reset; - logic [0:0] mux__sel; - - Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_2 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - MemAccessPacket_8_3_128__43c148781d2f2a57 rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - MemAccessPacket_8_3_128__43c148781d2f2a57 rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__7305dd76cfb05fd9 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - assign mux__clk = clk; - assign mux__reset = reset; - assign mux__sel = mux_sel; - assign mux__in_[0] = rf__rdata[0]; - assign mux__in_[1] = recv_msg; - assign send_msg = mux__out; - -endmodule - - -// PyMTL Component BypassQueueRTL Definition -// Full name: BypassQueueRTL__EntryType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueRTL__4eac613e5285098c -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__mux_sel; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - BypassQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .mux_sel( ctrl__mux_sel ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__mux_sel; - logic [0:0] dpath__raddr; - MemAccessPacket_8_3_128__43c148781d2f2a57 dpath__recv_msg; - logic [0:0] dpath__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - BypassQueueDpathRTL__4eac613e5285098c dpath - ( - .clk( dpath__clk ), - .mux_sel( dpath__mux_sel ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign dpath__mux_sel = ctrl__mux_sel; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign count = ctrl__count; - assign dpath__recv_msg = recv__msg; - assign send__msg = dpath__send_msg; - -endmodule - - -// PyMTL Component InputUnitRTL Definition -// Full name: InputUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_BypassQueueRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py - -module InputUnitRTL__1864e8652261553b -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queue - //------------------------------------------------------------- - - logic [0:0] queue__clk; - logic [1:0] queue__count; - logic [0:0] queue__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 queue__recv__msg; - logic [0:0] queue__recv__rdy; - logic [0:0] queue__recv__val; - MemAccessPacket_8_3_128__43c148781d2f2a57 queue__send__msg; - logic [0:0] queue__send__rdy; - logic [0:0] queue__send__val; - - BypassQueueRTL__4eac613e5285098c queue - ( - .clk( queue__clk ), - .count( queue__count ), - .reset( queue__reset ), - .recv__msg( queue__recv__msg ), - .recv__rdy( queue__recv__rdy ), - .recv__val( queue__recv__val ), - .send__msg( queue__send__msg ), - .send__rdy( queue__send__rdy ), - .send__val( queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component queue - //------------------------------------------------------------- - - assign queue__clk = clk; - assign queue__reset = reset; - assign queue__recv__msg = recv__msg; - assign recv__rdy = queue__recv__rdy; - assign queue__recv__val = recv__val; - assign send__msg = queue__send__msg; - assign queue__send__rdy = send__rdy; - assign send__val = queue__send__val; - -endmodule - - -// PyMTL Component OutputUnitRTL Definition -// Full name: OutputUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__QueueType_None -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py - -module OutputUnitRTL__a3f8631b75bafad0 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - assign send__msg = recv__msg; - assign recv__rdy = send__rdy; - assign send__val = recv__val; - -endmodule - - -// PyMTL Component XbarRouteUnitRTL Definition -// Full name: XbarRouteUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_outports_3 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py - -module XbarRouteUnitRTL__32c7752a7c15587d -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg [0:2] , - input logic [0:0] send__rdy [0:2] , - output logic [0:0] send__val [0:2] -); - localparam logic [1:0] __const__num_outports_at_up_ru_routing = 2'd3; - logic [1:0] out_dir; - logic [2:0] send_val; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 - // @update - // def up_ru_recv_rdy(): - // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 - - always_comb begin : up_ru_recv_rdy - recv__rdy = send__rdy[out_dir] > 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 - // @update - // def up_ru_routing(): - // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) - // - // for i in range( num_outports ): - // s.send[i].val @= b1(0) - // - // if s.recv.val: - // s.send[ s.out_dir ].val @= b1(1) - - always_comb begin : up_ru_routing - out_dir = recv__msg.dst; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) - send__val[2'(i)] = 1'd0; - if ( recv__val ) begin - send__val[out_dir] = 1'd1; - end - end - - assign send__msg[0] = recv__msg; - assign send_val[0:0] = send__val[0]; - assign send__msg[1] = recv__msg; - assign send_val[1:1] = send__val[1]; - assign send__msg[2] = recv__msg; - assign send_val[2:2] = send__val[2]; - -endmodule - - -// PyMTL Component RegEnRst Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py - -module RegEnRst__Type_Bits8__reset_value_1 -( - input logic [0:0] clk , - input logic [0:0] en , - input logic [7:0] in_ , - output logic [7:0] out , - input logic [0:0] reset -); - localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 - // @update_ff - // def up_regenrst(): - // if s.reset: s.out <<= reset_value - // elif s.en: s.out <<= s.in_ - - always_ff @(posedge clk) begin : up_regenrst - if ( reset ) begin - out <= 8'( __const__reset_value_at_up_regenrst ); - end - else if ( en ) begin - out <= in_; - end - end - -endmodule - - -// PyMTL Component RoundRobinArbiterEn Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py - -module RoundRobinArbiterEn__nreqs_8 -( - input logic [0:0] clk , - input logic [0:0] en , - output logic [7:0] grants , - input logic [7:0] reqs , - input logic [0:0] reset -); - localparam logic [3:0] __const__nreqs_at_comb_reqs_int = 4'd8; - localparam logic [4:0] __const__nreqsX2_at_comb_reqs_int = 5'd16; - localparam logic [3:0] __const__nreqs_at_comb_grants = 4'd8; - localparam logic [3:0] __const__nreqs_at_comb_priority_int = 4'd8; - localparam logic [4:0] __const__nreqsX2_at_comb_priority_int = 5'd16; - localparam logic [4:0] __const__nreqsX2_at_comb_kills = 5'd16; - localparam logic [4:0] __const__nreqsX2_at_comb_grants_int = 5'd16; - logic [15:0] grants_int; - logic [16:0] kills; - logic [0:0] priority_en; - logic [15:0] priority_int; - logic [15:0] reqs_int; - //------------------------------------------------------------- - // Component priority_reg - //------------------------------------------------------------- - - logic [0:0] priority_reg__clk; - logic [0:0] priority_reg__en; - logic [7:0] priority_reg__in_; - logic [7:0] priority_reg__out; - logic [0:0] priority_reg__reset; - - RegEnRst__Type_Bits8__reset_value_1 priority_reg - ( - .clk( priority_reg__clk ), - .en( priority_reg__en ), - .in_( priority_reg__in_ ), - .out( priority_reg__out ), - .reset( priority_reg__reset ) - ); - - //------------------------------------------------------------- - // End of component priority_reg - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 - // @update - // def comb_grants(): - // for i in range( nreqs ): - // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] - - always_comb begin : comb_grants - for ( int unsigned i = 1'd0; i < 4'( __const__nreqs_at_comb_grants ); i += 1'd1 ) - grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 - // @update - // def comb_grants_int(): - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.grants_int[i] @= s.reqs_int[i] - // else: - // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] - - always_comb begin : comb_grants_int - for ( int unsigned i = 1'd0; i < 5'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - grants_int[4'(i)] = reqs_int[4'(i)]; - end - else - grants_int[4'(i)] = ( ~kills[5'(i)] ) & reqs_int[4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 - // @update - // def comb_kills(): - // s.kills[0] @= 1 - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.kills[i+1] @= s.reqs_int[i] - // else: - // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) - - always_comb begin : comb_kills - kills[5'd0] = 1'd1; - for ( int unsigned i = 1'd0; i < 5'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - kills[5'(i) + 5'd1] = reqs_int[4'(i)]; - end - else - kills[5'(i) + 5'd1] = kills[5'(i)] | ( ( ~kills[5'(i)] ) & reqs_int[4'(i)] ); - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 - // @update - // def comb_priority_en(): - // s.priority_en @= ( s.grants != 0 ) & s.en - - always_comb begin : comb_priority_en - priority_en = ( grants != 8'd0 ) & en; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 - // @update - // def comb_priority_int(): - // s.priority_int[ 0:nreqs ] @= s.priority_reg.out - // s.priority_int[nreqs:nreqsX2] @= 0 - - always_comb begin : comb_priority_int - priority_int[4'd7:4'd0] = priority_reg__out; - priority_int[4'd15:4'( __const__nreqs_at_comb_priority_int )] = 8'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 - // @update - // def comb_reqs_int(): - // s.reqs_int [ 0:nreqs ] @= s.reqs - // s.reqs_int [nreqs:nreqsX2] @= s.reqs - - always_comb begin : comb_reqs_int - reqs_int[4'd7:4'd0] = reqs; - reqs_int[4'd15:4'( __const__nreqs_at_comb_reqs_int )] = reqs; - end - - assign priority_reg__clk = clk; - assign priority_reg__reset = reset; - assign priority_reg__en = priority_en; - assign priority_reg__in_[7:1] = grants[6:0]; - assign priority_reg__in_[0:0] = grants[7:7]; - -endmodule - - -// PyMTL Component Encoder Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py - -module Encoder__in_nbits_8__out_nbits_3 -( - input logic [0:0] clk , - input logic [7:0] in_ , - output logic [2:0] out , - input logic [0:0] reset -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 - // @update - // def encode(): - // s.out @= 0 - // for i in range( s.in_nbits ): - // if s.in_[i]: - // s.out @= i - - always_comb begin : encode - out = 3'd0; - for ( int unsigned i = 1'd0; i < 4'd8; i += 1'd1 ) - if ( in_[3'(i)] ) begin - out = 3'(i); - end - end - -endmodule - - -// PyMTL Component Mux Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_8 -( - input logic [0:0] clk , - input MemAccessPacket_8_3_128__43c148781d2f2a57 in_ [0:7], - output MemAccessPacket_8_3_128__43c148781d2f2a57 out , - input logic [0:0] reset , - input logic [2:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component SwitchUnitRTL Definition -// Full name: SwitchUnitRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_inports_8 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py - -module SwitchUnitRTL__10097976fa423359 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg [0:7] , - output logic [0:0] recv__rdy [0:7] , - input logic [0:0] recv__val [0:7] , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [3:0] __const__num_inports_at_up_get_en = 4'd8; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [7:0] arbiter__grants; - logic [7:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_8 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [7:0] encoder__in_; - logic [2:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_8__out_nbits_3 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - MemAccessPacket_8_3_128__43c148781d2f2a57 mux__in_ [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 mux__out; - logic [0:0] mux__reset; - logic [2:0] mux__sel; - - Mux__Type_MemAccessPacket_8_3_128__43c148781d2f2a57__ninputs_8 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 - // @update - // def up_get_en(): - // for i in range( num_inports ): - // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) - - always_comb begin : up_get_en - for ( int unsigned i = 1'd0; i < 4'( __const__num_inports_at_up_get_en ); i += 1'd1 ) - recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 - // @update - // def up_send_val(): - // s.send.val @= s.arbiter.grants > 0 - - always_comb begin : up_send_val - send__val = arbiter__grants > 8'd0; - end - - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign arbiter__en = 1'd1; - assign mux__clk = clk; - assign mux__reset = reset; - assign send__msg = mux__out; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign encoder__in_ = arbiter__grants; - assign mux__sel = encoder__out; - assign arbiter__reqs[0:0] = recv__val[0]; - assign mux__in_[0] = recv__msg[0]; - assign arbiter__reqs[1:1] = recv__val[1]; - assign mux__in_[1] = recv__msg[1]; - assign arbiter__reqs[2:2] = recv__val[2]; - assign mux__in_[2] = recv__msg[2]; - assign arbiter__reqs[3:3] = recv__val[3]; - assign mux__in_[3] = recv__msg[3]; - assign arbiter__reqs[4:4] = recv__val[4]; - assign mux__in_[4] = recv__msg[4]; - assign arbiter__reqs[5:5] = recv__val[5]; - assign mux__in_[5] = recv__msg[5]; - assign arbiter__reqs[6:6] = recv__val[6]; - assign mux__in_[6] = recv__msg[6]; - assign arbiter__reqs[7:7] = recv__val[7]; - assign mux__in_[7] = recv__msg[7]; - -endmodule - - -// PyMTL Component XbarBypassQueueRTL Definition -// Full name: XbarBypassQueueRTL__PacketType_MemAccessPacket_8_3_128__43c148781d2f2a57__num_inports_8__num_outports_3__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarBypassQueueRTL.py - -module XbarBypassQueueRTL__045133ee283ca701 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_8_3_128__43c148781d2f2a57 recv__msg [0:7] , - output logic [0:0] recv__rdy [0:7] , - input logic [0:0] recv__val [0:7] , - output MemAccessPacket_8_3_128__43c148781d2f2a57 send__msg [0:2] , - input logic [0:0] send__rdy [0:2] , - output logic [0:0] send__val [0:2] -); - //------------------------------------------------------------- - // Component input_units[0:7] - //------------------------------------------------------------- - - logic [0:0] input_units__clk [0:7]; - logic [0:0] input_units__reset [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 input_units__recv__msg [0:7]; - logic [0:0] input_units__recv__rdy [0:7]; - logic [0:0] input_units__recv__val [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 input_units__send__msg [0:7]; - logic [0:0] input_units__send__rdy [0:7]; - logic [0:0] input_units__send__val [0:7]; - - InputUnitRTL__1864e8652261553b input_units__0 - ( - .clk( input_units__clk[0] ), - .reset( input_units__reset[0] ), - .recv__msg( input_units__recv__msg[0] ), - .recv__rdy( input_units__recv__rdy[0] ), - .recv__val( input_units__recv__val[0] ), - .send__msg( input_units__send__msg[0] ), - .send__rdy( input_units__send__rdy[0] ), - .send__val( input_units__send__val[0] ) - ); - - InputUnitRTL__1864e8652261553b input_units__1 - ( - .clk( input_units__clk[1] ), - .reset( input_units__reset[1] ), - .recv__msg( input_units__recv__msg[1] ), - .recv__rdy( input_units__recv__rdy[1] ), - .recv__val( input_units__recv__val[1] ), - .send__msg( input_units__send__msg[1] ), - .send__rdy( input_units__send__rdy[1] ), - .send__val( input_units__send__val[1] ) - ); - - InputUnitRTL__1864e8652261553b input_units__2 - ( - .clk( input_units__clk[2] ), - .reset( input_units__reset[2] ), - .recv__msg( input_units__recv__msg[2] ), - .recv__rdy( input_units__recv__rdy[2] ), - .recv__val( input_units__recv__val[2] ), - .send__msg( input_units__send__msg[2] ), - .send__rdy( input_units__send__rdy[2] ), - .send__val( input_units__send__val[2] ) - ); - - InputUnitRTL__1864e8652261553b input_units__3 - ( - .clk( input_units__clk[3] ), - .reset( input_units__reset[3] ), - .recv__msg( input_units__recv__msg[3] ), - .recv__rdy( input_units__recv__rdy[3] ), - .recv__val( input_units__recv__val[3] ), - .send__msg( input_units__send__msg[3] ), - .send__rdy( input_units__send__rdy[3] ), - .send__val( input_units__send__val[3] ) - ); - - InputUnitRTL__1864e8652261553b input_units__4 - ( - .clk( input_units__clk[4] ), - .reset( input_units__reset[4] ), - .recv__msg( input_units__recv__msg[4] ), - .recv__rdy( input_units__recv__rdy[4] ), - .recv__val( input_units__recv__val[4] ), - .send__msg( input_units__send__msg[4] ), - .send__rdy( input_units__send__rdy[4] ), - .send__val( input_units__send__val[4] ) - ); - - InputUnitRTL__1864e8652261553b input_units__5 - ( - .clk( input_units__clk[5] ), - .reset( input_units__reset[5] ), - .recv__msg( input_units__recv__msg[5] ), - .recv__rdy( input_units__recv__rdy[5] ), - .recv__val( input_units__recv__val[5] ), - .send__msg( input_units__send__msg[5] ), - .send__rdy( input_units__send__rdy[5] ), - .send__val( input_units__send__val[5] ) - ); - - InputUnitRTL__1864e8652261553b input_units__6 - ( - .clk( input_units__clk[6] ), - .reset( input_units__reset[6] ), - .recv__msg( input_units__recv__msg[6] ), - .recv__rdy( input_units__recv__rdy[6] ), - .recv__val( input_units__recv__val[6] ), - .send__msg( input_units__send__msg[6] ), - .send__rdy( input_units__send__rdy[6] ), - .send__val( input_units__send__val[6] ) - ); - - InputUnitRTL__1864e8652261553b input_units__7 - ( - .clk( input_units__clk[7] ), - .reset( input_units__reset[7] ), - .recv__msg( input_units__recv__msg[7] ), - .recv__rdy( input_units__recv__rdy[7] ), - .recv__val( input_units__recv__val[7] ), - .send__msg( input_units__send__msg[7] ), - .send__rdy( input_units__send__rdy[7] ), - .send__val( input_units__send__val[7] ) - ); - - //------------------------------------------------------------- - // End of component input_units[0:7] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component output_units[0:2] - //------------------------------------------------------------- - - logic [0:0] output_units__clk [0:2]; - logic [0:0] output_units__reset [0:2]; - MemAccessPacket_8_3_128__43c148781d2f2a57 output_units__recv__msg [0:2]; - logic [0:0] output_units__recv__rdy [0:2]; - logic [0:0] output_units__recv__val [0:2]; - MemAccessPacket_8_3_128__43c148781d2f2a57 output_units__send__msg [0:2]; - logic [0:0] output_units__send__rdy [0:2]; - logic [0:0] output_units__send__val [0:2]; - - OutputUnitRTL__a3f8631b75bafad0 output_units__0 - ( - .clk( output_units__clk[0] ), - .reset( output_units__reset[0] ), - .recv__msg( output_units__recv__msg[0] ), - .recv__rdy( output_units__recv__rdy[0] ), - .recv__val( output_units__recv__val[0] ), - .send__msg( output_units__send__msg[0] ), - .send__rdy( output_units__send__rdy[0] ), - .send__val( output_units__send__val[0] ) - ); - - OutputUnitRTL__a3f8631b75bafad0 output_units__1 - ( - .clk( output_units__clk[1] ), - .reset( output_units__reset[1] ), - .recv__msg( output_units__recv__msg[1] ), - .recv__rdy( output_units__recv__rdy[1] ), - .recv__val( output_units__recv__val[1] ), - .send__msg( output_units__send__msg[1] ), - .send__rdy( output_units__send__rdy[1] ), - .send__val( output_units__send__val[1] ) - ); - - OutputUnitRTL__a3f8631b75bafad0 output_units__2 - ( - .clk( output_units__clk[2] ), - .reset( output_units__reset[2] ), - .recv__msg( output_units__recv__msg[2] ), - .recv__rdy( output_units__recv__rdy[2] ), - .recv__val( output_units__recv__val[2] ), - .send__msg( output_units__send__msg[2] ), - .send__rdy( output_units__send__rdy[2] ), - .send__val( output_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component output_units[0:2] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component route_units[0:7] - //------------------------------------------------------------- - - logic [0:0] route_units__clk [0:7]; - logic [0:0] route_units__reset [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 route_units__recv__msg [0:7]; - logic [0:0] route_units__recv__rdy [0:7]; - logic [0:0] route_units__recv__val [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 route_units__send__msg [0:7][0:2]; - logic [0:0] route_units__send__rdy [0:7][0:2]; - logic [0:0] route_units__send__val [0:7][0:2]; - - XbarRouteUnitRTL__32c7752a7c15587d route_units__0 - ( - .clk( route_units__clk[0] ), - .reset( route_units__reset[0] ), - .recv__msg( route_units__recv__msg[0] ), - .recv__rdy( route_units__recv__rdy[0] ), - .recv__val( route_units__recv__val[0] ), - .send__msg( route_units__send__msg[0] ), - .send__rdy( route_units__send__rdy[0] ), - .send__val( route_units__send__val[0] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__1 - ( - .clk( route_units__clk[1] ), - .reset( route_units__reset[1] ), - .recv__msg( route_units__recv__msg[1] ), - .recv__rdy( route_units__recv__rdy[1] ), - .recv__val( route_units__recv__val[1] ), - .send__msg( route_units__send__msg[1] ), - .send__rdy( route_units__send__rdy[1] ), - .send__val( route_units__send__val[1] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__2 - ( - .clk( route_units__clk[2] ), - .reset( route_units__reset[2] ), - .recv__msg( route_units__recv__msg[2] ), - .recv__rdy( route_units__recv__rdy[2] ), - .recv__val( route_units__recv__val[2] ), - .send__msg( route_units__send__msg[2] ), - .send__rdy( route_units__send__rdy[2] ), - .send__val( route_units__send__val[2] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__3 - ( - .clk( route_units__clk[3] ), - .reset( route_units__reset[3] ), - .recv__msg( route_units__recv__msg[3] ), - .recv__rdy( route_units__recv__rdy[3] ), - .recv__val( route_units__recv__val[3] ), - .send__msg( route_units__send__msg[3] ), - .send__rdy( route_units__send__rdy[3] ), - .send__val( route_units__send__val[3] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__4 - ( - .clk( route_units__clk[4] ), - .reset( route_units__reset[4] ), - .recv__msg( route_units__recv__msg[4] ), - .recv__rdy( route_units__recv__rdy[4] ), - .recv__val( route_units__recv__val[4] ), - .send__msg( route_units__send__msg[4] ), - .send__rdy( route_units__send__rdy[4] ), - .send__val( route_units__send__val[4] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__5 - ( - .clk( route_units__clk[5] ), - .reset( route_units__reset[5] ), - .recv__msg( route_units__recv__msg[5] ), - .recv__rdy( route_units__recv__rdy[5] ), - .recv__val( route_units__recv__val[5] ), - .send__msg( route_units__send__msg[5] ), - .send__rdy( route_units__send__rdy[5] ), - .send__val( route_units__send__val[5] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__6 - ( - .clk( route_units__clk[6] ), - .reset( route_units__reset[6] ), - .recv__msg( route_units__recv__msg[6] ), - .recv__rdy( route_units__recv__rdy[6] ), - .recv__val( route_units__recv__val[6] ), - .send__msg( route_units__send__msg[6] ), - .send__rdy( route_units__send__rdy[6] ), - .send__val( route_units__send__val[6] ) - ); - - XbarRouteUnitRTL__32c7752a7c15587d route_units__7 - ( - .clk( route_units__clk[7] ), - .reset( route_units__reset[7] ), - .recv__msg( route_units__recv__msg[7] ), - .recv__rdy( route_units__recv__rdy[7] ), - .recv__val( route_units__recv__val[7] ), - .send__msg( route_units__send__msg[7] ), - .send__rdy( route_units__send__rdy[7] ), - .send__val( route_units__send__val[7] ) - ); - - //------------------------------------------------------------- - // End of component route_units[0:7] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component switch_units[0:2] - //------------------------------------------------------------- - - logic [0:0] switch_units__clk [0:2]; - logic [0:0] switch_units__reset [0:2]; - MemAccessPacket_8_3_128__43c148781d2f2a57 switch_units__recv__msg [0:2][0:7]; - logic [0:0] switch_units__recv__rdy [0:2][0:7]; - logic [0:0] switch_units__recv__val [0:2][0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 switch_units__send__msg [0:2]; - logic [0:0] switch_units__send__rdy [0:2]; - logic [0:0] switch_units__send__val [0:2]; - - SwitchUnitRTL__10097976fa423359 switch_units__0 - ( - .clk( switch_units__clk[0] ), - .reset( switch_units__reset[0] ), - .recv__msg( switch_units__recv__msg[0] ), - .recv__rdy( switch_units__recv__rdy[0] ), - .recv__val( switch_units__recv__val[0] ), - .send__msg( switch_units__send__msg[0] ), - .send__rdy( switch_units__send__rdy[0] ), - .send__val( switch_units__send__val[0] ) - ); - - SwitchUnitRTL__10097976fa423359 switch_units__1 - ( - .clk( switch_units__clk[1] ), - .reset( switch_units__reset[1] ), - .recv__msg( switch_units__recv__msg[1] ), - .recv__rdy( switch_units__recv__rdy[1] ), - .recv__val( switch_units__recv__val[1] ), - .send__msg( switch_units__send__msg[1] ), - .send__rdy( switch_units__send__rdy[1] ), - .send__val( switch_units__send__val[1] ) - ); - - SwitchUnitRTL__10097976fa423359 switch_units__2 - ( - .clk( switch_units__clk[2] ), - .reset( switch_units__reset[2] ), - .recv__msg( switch_units__recv__msg[2] ), - .recv__rdy( switch_units__recv__rdy[2] ), - .recv__val( switch_units__recv__val[2] ), - .send__msg( switch_units__send__msg[2] ), - .send__rdy( switch_units__send__rdy[2] ), - .send__val( switch_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component switch_units[0:2] - //------------------------------------------------------------- - - assign input_units__clk[0] = clk; - assign input_units__reset[0] = reset; - assign input_units__clk[1] = clk; - assign input_units__reset[1] = reset; - assign input_units__clk[2] = clk; - assign input_units__reset[2] = reset; - assign input_units__clk[3] = clk; - assign input_units__reset[3] = reset; - assign input_units__clk[4] = clk; - assign input_units__reset[4] = reset; - assign input_units__clk[5] = clk; - assign input_units__reset[5] = reset; - assign input_units__clk[6] = clk; - assign input_units__reset[6] = reset; - assign input_units__clk[7] = clk; - assign input_units__reset[7] = reset; - assign route_units__clk[0] = clk; - assign route_units__reset[0] = reset; - assign route_units__clk[1] = clk; - assign route_units__reset[1] = reset; - assign route_units__clk[2] = clk; - assign route_units__reset[2] = reset; - assign route_units__clk[3] = clk; - assign route_units__reset[3] = reset; - assign route_units__clk[4] = clk; - assign route_units__reset[4] = reset; - assign route_units__clk[5] = clk; - assign route_units__reset[5] = reset; - assign route_units__clk[6] = clk; - assign route_units__reset[6] = reset; - assign route_units__clk[7] = clk; - assign route_units__reset[7] = reset; - assign switch_units__clk[0] = clk; - assign switch_units__reset[0] = reset; - assign switch_units__clk[1] = clk; - assign switch_units__reset[1] = reset; - assign switch_units__clk[2] = clk; - assign switch_units__reset[2] = reset; - assign output_units__clk[0] = clk; - assign output_units__reset[0] = reset; - assign output_units__clk[1] = clk; - assign output_units__reset[1] = reset; - assign output_units__clk[2] = clk; - assign output_units__reset[2] = reset; - assign input_units__recv__msg[0] = recv__msg[0]; - assign recv__rdy[0] = input_units__recv__rdy[0]; - assign input_units__recv__val[0] = recv__val[0]; - assign route_units__recv__msg[0] = input_units__send__msg[0]; - assign input_units__send__rdy[0] = route_units__recv__rdy[0]; - assign route_units__recv__val[0] = input_units__send__val[0]; - assign input_units__recv__msg[1] = recv__msg[1]; - assign recv__rdy[1] = input_units__recv__rdy[1]; - assign input_units__recv__val[1] = recv__val[1]; - assign route_units__recv__msg[1] = input_units__send__msg[1]; - assign input_units__send__rdy[1] = route_units__recv__rdy[1]; - assign route_units__recv__val[1] = input_units__send__val[1]; - assign input_units__recv__msg[2] = recv__msg[2]; - assign recv__rdy[2] = input_units__recv__rdy[2]; - assign input_units__recv__val[2] = recv__val[2]; - assign route_units__recv__msg[2] = input_units__send__msg[2]; - assign input_units__send__rdy[2] = route_units__recv__rdy[2]; - assign route_units__recv__val[2] = input_units__send__val[2]; - assign input_units__recv__msg[3] = recv__msg[3]; - assign recv__rdy[3] = input_units__recv__rdy[3]; - assign input_units__recv__val[3] = recv__val[3]; - assign route_units__recv__msg[3] = input_units__send__msg[3]; - assign input_units__send__rdy[3] = route_units__recv__rdy[3]; - assign route_units__recv__val[3] = input_units__send__val[3]; - assign input_units__recv__msg[4] = recv__msg[4]; - assign recv__rdy[4] = input_units__recv__rdy[4]; - assign input_units__recv__val[4] = recv__val[4]; - assign route_units__recv__msg[4] = input_units__send__msg[4]; - assign input_units__send__rdy[4] = route_units__recv__rdy[4]; - assign route_units__recv__val[4] = input_units__send__val[4]; - assign input_units__recv__msg[5] = recv__msg[5]; - assign recv__rdy[5] = input_units__recv__rdy[5]; - assign input_units__recv__val[5] = recv__val[5]; - assign route_units__recv__msg[5] = input_units__send__msg[5]; - assign input_units__send__rdy[5] = route_units__recv__rdy[5]; - assign route_units__recv__val[5] = input_units__send__val[5]; - assign input_units__recv__msg[6] = recv__msg[6]; - assign recv__rdy[6] = input_units__recv__rdy[6]; - assign input_units__recv__val[6] = recv__val[6]; - assign route_units__recv__msg[6] = input_units__send__msg[6]; - assign input_units__send__rdy[6] = route_units__recv__rdy[6]; - assign route_units__recv__val[6] = input_units__send__val[6]; - assign input_units__recv__msg[7] = recv__msg[7]; - assign recv__rdy[7] = input_units__recv__rdy[7]; - assign input_units__recv__val[7] = recv__val[7]; - assign route_units__recv__msg[7] = input_units__send__msg[7]; - assign input_units__send__rdy[7] = route_units__recv__rdy[7]; - assign route_units__recv__val[7] = input_units__send__val[7]; - assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; - assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; - assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; - assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; - assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; - assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; - assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; - assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; - assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; - assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; - assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; - assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; - assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; - assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; - assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; - assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; - assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; - assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; - assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; - assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; - assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; - assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; - assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; - assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; - assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; - assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; - assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; - assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; - assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; - assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; - assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; - assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; - assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; - assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; - assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; - assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; - assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; - assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; - assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; - assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; - assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; - assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; - assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; - assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; - assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; - assign switch_units__recv__msg[0][5] = route_units__send__msg[5][0]; - assign route_units__send__rdy[5][0] = switch_units__recv__rdy[0][5]; - assign switch_units__recv__val[0][5] = route_units__send__val[5][0]; - assign switch_units__recv__msg[1][5] = route_units__send__msg[5][1]; - assign route_units__send__rdy[5][1] = switch_units__recv__rdy[1][5]; - assign switch_units__recv__val[1][5] = route_units__send__val[5][1]; - assign switch_units__recv__msg[2][5] = route_units__send__msg[5][2]; - assign route_units__send__rdy[5][2] = switch_units__recv__rdy[2][5]; - assign switch_units__recv__val[2][5] = route_units__send__val[5][2]; - assign switch_units__recv__msg[0][6] = route_units__send__msg[6][0]; - assign route_units__send__rdy[6][0] = switch_units__recv__rdy[0][6]; - assign switch_units__recv__val[0][6] = route_units__send__val[6][0]; - assign switch_units__recv__msg[1][6] = route_units__send__msg[6][1]; - assign route_units__send__rdy[6][1] = switch_units__recv__rdy[1][6]; - assign switch_units__recv__val[1][6] = route_units__send__val[6][1]; - assign switch_units__recv__msg[2][6] = route_units__send__msg[6][2]; - assign route_units__send__rdy[6][2] = switch_units__recv__rdy[2][6]; - assign switch_units__recv__val[2][6] = route_units__send__val[6][2]; - assign switch_units__recv__msg[0][7] = route_units__send__msg[7][0]; - assign route_units__send__rdy[7][0] = switch_units__recv__rdy[0][7]; - assign switch_units__recv__val[0][7] = route_units__send__val[7][0]; - assign switch_units__recv__msg[1][7] = route_units__send__msg[7][1]; - assign route_units__send__rdy[7][1] = switch_units__recv__rdy[1][7]; - assign switch_units__recv__val[1][7] = route_units__send__val[7][1]; - assign switch_units__recv__msg[2][7] = route_units__send__msg[7][2]; - assign route_units__send__rdy[7][2] = switch_units__recv__rdy[2][7]; - assign switch_units__recv__val[2][7] = route_units__send__val[7][2]; - assign output_units__recv__msg[0] = switch_units__send__msg[0]; - assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; - assign output_units__recv__val[0] = switch_units__send__val[0]; - assign send__msg[0] = output_units__send__msg[0]; - assign output_units__send__rdy[0] = send__rdy[0]; - assign send__val[0] = output_units__send__val[0]; - assign output_units__recv__msg[1] = switch_units__send__msg[1]; - assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; - assign output_units__recv__val[1] = switch_units__send__val[1]; - assign send__msg[1] = output_units__send__msg[1]; - assign output_units__send__rdy[1] = send__rdy[1]; - assign send__val[1] = output_units__send__val[1]; - assign output_units__recv__msg[2] = switch_units__send__msg[2]; - assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; - assign output_units__recv__val[2] = switch_units__send__val[2]; - assign send__msg[2] = output_units__send__msg[2]; - assign output_units__send__rdy[2] = send__rdy[2]; - assign send__val[2] = output_units__send__val[2]; - -endmodule - - -// PyMTL Component Mux Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_2 -( - input logic [0:0] clk , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 in_ [0:1], - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 out , - input logic [0:0] reset , - input logic [0:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__3969b2773d1d2f8e -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component BypassQueueDpathRTL Definition -// Full name: BypassQueueDpathRTL__EntryType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueDpathRTL__60d0395b9f70f062 -( - input logic [0:0] clk , - input logic [0:0] mux_sel , - input logic [0:0] raddr , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv_msg , - input logic [0:0] reset , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__in_ [0:1]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__out; - logic [0:0] mux__reset; - logic [0:0] mux__sel; - - Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_2 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__3969b2773d1d2f8e rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - assign mux__clk = clk; - assign mux__reset = reset; - assign mux__sel = mux_sel; - assign mux__in_[0] = rf__rdata[0]; - assign mux__in_[1] = recv_msg; - assign send_msg = mux__out; - -endmodule - - -// PyMTL Component BypassQueueRTL Definition -// Full name: BypassQueueRTL__EntryType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module BypassQueueRTL__60d0395b9f70f062 -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__mux_sel; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - BypassQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .mux_sel( ctrl__mux_sel ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__mux_sel; - logic [0:0] dpath__raddr; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 dpath__recv_msg; - logic [0:0] dpath__reset; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - BypassQueueDpathRTL__60d0395b9f70f062 dpath - ( - .clk( dpath__clk ), - .mux_sel( dpath__mux_sel ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign dpath__mux_sel = ctrl__mux_sel; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign count = ctrl__count; - assign dpath__recv_msg = recv__msg; - assign send__msg = dpath__send_msg; - -endmodule - - -// PyMTL Component InputUnitRTL Definition -// Full name: InputUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__QueueType_BypassQueueRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py - -module InputUnitRTL__cff279ef5009e7c6 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queue - //------------------------------------------------------------- - - logic [0:0] queue__clk; - logic [1:0] queue__count; - logic [0:0] queue__reset; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 queue__recv__msg; - logic [0:0] queue__recv__rdy; - logic [0:0] queue__recv__val; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 queue__send__msg; - logic [0:0] queue__send__rdy; - logic [0:0] queue__send__val; - - BypassQueueRTL__60d0395b9f70f062 queue - ( - .clk( queue__clk ), - .count( queue__count ), - .reset( queue__reset ), - .recv__msg( queue__recv__msg ), - .recv__rdy( queue__recv__rdy ), - .recv__val( queue__recv__val ), - .send__msg( queue__send__msg ), - .send__rdy( queue__send__rdy ), - .send__val( queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component queue - //------------------------------------------------------------- - - assign queue__clk = clk; - assign queue__reset = reset; - assign queue__recv__msg = recv__msg; - assign recv__rdy = queue__recv__rdy; - assign queue__recv__val = recv__val; - assign send__msg = queue__send__msg; - assign queue__send__rdy = send__rdy; - assign send__val = queue__send__val; - -endmodule - - -// PyMTL Component OutputUnitRTL Definition -// Full name: OutputUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__QueueType_None -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py - -module OutputUnitRTL__e96d78a3d0126314 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - assign send__msg = recv__msg; - assign recv__rdy = send__rdy; - assign send__val = recv__val; - -endmodule - - -// PyMTL Component XbarRouteUnitRTL Definition -// Full name: XbarRouteUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_outports_8 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py - -module XbarRouteUnitRTL__c063f4910bbc0b50 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg [0:7] , - input logic [0:0] send__rdy [0:7] , - output logic [0:0] send__val [0:7] -); - localparam logic [3:0] __const__num_outports_at_up_ru_routing = 4'd8; - logic [2:0] out_dir; - logic [7:0] send_val; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:51 - // @update - // def up_ru_recv_rdy(): - // s.recv.rdy @= s.send[ s.out_dir ].rdy > 0 - - always_comb begin : up_ru_recv_rdy - recv__rdy = send__rdy[out_dir] > 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarRouteUnitRTL.py:41 - // @update - // def up_ru_routing(): - // s.out_dir @= trunc( s.recv.msg.dst, dir_nbits ) - // - // for i in range( num_outports ): - // s.send[i].val @= b1(0) - // - // if s.recv.val: - // s.send[ s.out_dir ].val @= b1(1) - - always_comb begin : up_ru_routing - out_dir = recv__msg.dst; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) - send__val[3'(i)] = 1'd0; - if ( recv__val ) begin - send__val[out_dir] = 1'd1; - end - end - - assign send__msg[0] = recv__msg; - assign send_val[0:0] = send__val[0]; - assign send__msg[1] = recv__msg; - assign send_val[1:1] = send__val[1]; - assign send__msg[2] = recv__msg; - assign send_val[2:2] = send__val[2]; - assign send__msg[3] = recv__msg; - assign send_val[3:3] = send__val[3]; - assign send__msg[4] = recv__msg; - assign send_val[4:4] = send__val[4]; - assign send__msg[5] = recv__msg; - assign send_val[5:5] = send__val[5]; - assign send__msg[6] = recv__msg; - assign send_val[6:6] = send__val[6]; - assign send__msg[7] = recv__msg; - assign send_val[7:7] = send__val[7]; - -endmodule - - -// PyMTL Component RegEnRst Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py - -module RegEnRst__Type_Bits3__reset_value_1 -( - input logic [0:0] clk , - input logic [0:0] en , - input logic [2:0] in_ , - output logic [2:0] out , - input logic [0:0] reset -); - localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 - // @update_ff - // def up_regenrst(): - // if s.reset: s.out <<= reset_value - // elif s.en: s.out <<= s.in_ - - always_ff @(posedge clk) begin : up_regenrst - if ( reset ) begin - out <= 3'( __const__reset_value_at_up_regenrst ); - end - else if ( en ) begin - out <= in_; - end - end - -endmodule - - -// PyMTL Component RoundRobinArbiterEn Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py - -module RoundRobinArbiterEn__nreqs_3 -( - input logic [0:0] clk , - input logic [0:0] en , - output logic [2:0] grants , - input logic [2:0] reqs , - input logic [0:0] reset -); - localparam logic [1:0] __const__nreqs_at_comb_reqs_int = 2'd3; - localparam logic [2:0] __const__nreqsX2_at_comb_reqs_int = 3'd6; - localparam logic [1:0] __const__nreqs_at_comb_grants = 2'd3; - localparam logic [1:0] __const__nreqs_at_comb_priority_int = 2'd3; - localparam logic [2:0] __const__nreqsX2_at_comb_priority_int = 3'd6; - localparam logic [2:0] __const__nreqsX2_at_comb_kills = 3'd6; - localparam logic [2:0] __const__nreqsX2_at_comb_grants_int = 3'd6; - logic [5:0] grants_int; - logic [6:0] kills; - logic [0:0] priority_en; - logic [5:0] priority_int; - logic [5:0] reqs_int; - //------------------------------------------------------------- - // Component priority_reg - //------------------------------------------------------------- - - logic [0:0] priority_reg__clk; - logic [0:0] priority_reg__en; - logic [2:0] priority_reg__in_; - logic [2:0] priority_reg__out; - logic [0:0] priority_reg__reset; - - RegEnRst__Type_Bits3__reset_value_1 priority_reg - ( - .clk( priority_reg__clk ), - .en( priority_reg__en ), - .in_( priority_reg__in_ ), - .out( priority_reg__out ), - .reset( priority_reg__reset ) - ); - - //------------------------------------------------------------- - // End of component priority_reg - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 - // @update - // def comb_grants(): - // for i in range( nreqs ): - // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] - - always_comb begin : comb_grants - for ( int unsigned i = 1'd0; i < 2'( __const__nreqs_at_comb_grants ); i += 1'd1 ) - grants[2'(i)] = grants_int[3'(i)] | grants_int[3'( __const__nreqs_at_comb_grants ) + 3'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 - // @update - // def comb_grants_int(): - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.grants_int[i] @= s.reqs_int[i] - // else: - // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] - - always_comb begin : comb_grants_int - for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) - if ( priority_int[3'(i)] ) begin - grants_int[3'(i)] = reqs_int[3'(i)]; - end - else - grants_int[3'(i)] = ( ~kills[3'(i)] ) & reqs_int[3'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 - // @update - // def comb_kills(): - // s.kills[0] @= 1 - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.kills[i+1] @= s.reqs_int[i] - // else: - // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) - - always_comb begin : comb_kills - kills[3'd0] = 1'd1; - for ( int unsigned i = 1'd0; i < 3'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) - if ( priority_int[3'(i)] ) begin - kills[3'(i) + 3'd1] = reqs_int[3'(i)]; - end - else - kills[3'(i) + 3'd1] = kills[3'(i)] | ( ( ~kills[3'(i)] ) & reqs_int[3'(i)] ); - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 - // @update - // def comb_priority_en(): - // s.priority_en @= ( s.grants != 0 ) & s.en - - always_comb begin : comb_priority_en - priority_en = ( grants != 3'd0 ) & en; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 - // @update - // def comb_priority_int(): - // s.priority_int[ 0:nreqs ] @= s.priority_reg.out - // s.priority_int[nreqs:nreqsX2] @= 0 - - always_comb begin : comb_priority_int - priority_int[3'd2:3'd0] = priority_reg__out; - priority_int[3'd5:3'( __const__nreqs_at_comb_priority_int )] = 3'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 - // @update - // def comb_reqs_int(): - // s.reqs_int [ 0:nreqs ] @= s.reqs - // s.reqs_int [nreqs:nreqsX2] @= s.reqs - - always_comb begin : comb_reqs_int - reqs_int[3'd2:3'd0] = reqs; - reqs_int[3'd5:3'( __const__nreqs_at_comb_reqs_int )] = reqs; - end - - assign priority_reg__clk = clk; - assign priority_reg__reset = reset; - assign priority_reg__en = priority_en; - assign priority_reg__in_[2:1] = grants[1:0]; - assign priority_reg__in_[0:0] = grants[2:2]; - -endmodule - - -// PyMTL Component Encoder Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py - -module Encoder__in_nbits_3__out_nbits_2 -( - input logic [0:0] clk , - input logic [2:0] in_ , - output logic [1:0] out , - input logic [0:0] reset -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 - // @update - // def encode(): - // s.out @= 0 - // for i in range( s.in_nbits ): - // if s.in_[i]: - // s.out @= i - - always_comb begin : encode - out = 2'd0; - for ( int unsigned i = 1'd0; i < 2'd3; i += 1'd1 ) - if ( in_[2'(i)] ) begin - out = 2'(i); - end - end - -endmodule - - -// PyMTL Component Mux Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_3 -( - input logic [0:0] clk , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 in_ [0:2], - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 out , - input logic [0:0] reset , - input logic [1:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component SwitchUnitRTL Definition -// Full name: SwitchUnitRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_inports_3 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py - -module SwitchUnitRTL__4cc70db240bb572a -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg [0:2] , - output logic [0:0] recv__rdy [0:2] , - input logic [0:0] recv__val [0:2] , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [1:0] __const__num_inports_at_up_get_en = 2'd3; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [2:0] arbiter__grants; - logic [2:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_3 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [2:0] encoder__in_; - logic [1:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_3__out_nbits_2 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__in_ [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 mux__out; - logic [0:0] mux__reset; - logic [1:0] mux__sel; - - Mux__Type_MemAccessPacket_3_8_128__9f21b0bcdad2c061__ninputs_3 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 - // @update - // def up_get_en(): - // for i in range( num_inports ): - // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) - - always_comb begin : up_get_en - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_up_get_en ); i += 1'd1 ) - recv__rdy[2'(i)] = send__rdy & ( mux__sel == 2'(i) ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 - // @update - // def up_send_val(): - // s.send.val @= s.arbiter.grants > 0 - - always_comb begin : up_send_val - send__val = arbiter__grants > 3'd0; - end - - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign arbiter__en = 1'd1; - assign mux__clk = clk; - assign mux__reset = reset; - assign send__msg = mux__out; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign encoder__in_ = arbiter__grants; - assign mux__sel = encoder__out; - assign arbiter__reqs[0:0] = recv__val[0]; - assign mux__in_[0] = recv__msg[0]; - assign arbiter__reqs[1:1] = recv__val[1]; - assign mux__in_[1] = recv__msg[1]; - assign arbiter__reqs[2:2] = recv__val[2]; - assign mux__in_[2] = recv__msg[2]; - -endmodule - - -// PyMTL Component XbarBypassQueueRTL Definition -// Full name: XbarBypassQueueRTL__PacketType_MemAccessPacket_3_8_128__9f21b0bcdad2c061__num_inports_3__num_outports_8__InputUnitType_InputUnitRTL__RouteUnitType_XbarRouteUnitRTL__SwitchUnitType_SwitchUnitRTL__OutputUnitType_OutputUnitRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/xbar/XbarBypassQueueRTL.py - -module XbarBypassQueueRTL__510da12df6787984 -( - input logic [0:0] clk , - input logic [0:0] reset , - input MemAccessPacket_3_8_128__9f21b0bcdad2c061 recv__msg [0:2] , - output logic [0:0] recv__rdy [0:2] , - input logic [0:0] recv__val [0:2] , - output MemAccessPacket_3_8_128__9f21b0bcdad2c061 send__msg [0:7] , - input logic [0:0] send__rdy [0:7] , - output logic [0:0] send__val [0:7] -); - //------------------------------------------------------------- - // Component input_units[0:2] - //------------------------------------------------------------- - - logic [0:0] input_units__clk [0:2]; - logic [0:0] input_units__reset [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 input_units__recv__msg [0:2]; - logic [0:0] input_units__recv__rdy [0:2]; - logic [0:0] input_units__recv__val [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 input_units__send__msg [0:2]; - logic [0:0] input_units__send__rdy [0:2]; - logic [0:0] input_units__send__val [0:2]; - - InputUnitRTL__cff279ef5009e7c6 input_units__0 - ( - .clk( input_units__clk[0] ), - .reset( input_units__reset[0] ), - .recv__msg( input_units__recv__msg[0] ), - .recv__rdy( input_units__recv__rdy[0] ), - .recv__val( input_units__recv__val[0] ), - .send__msg( input_units__send__msg[0] ), - .send__rdy( input_units__send__rdy[0] ), - .send__val( input_units__send__val[0] ) - ); - - InputUnitRTL__cff279ef5009e7c6 input_units__1 - ( - .clk( input_units__clk[1] ), - .reset( input_units__reset[1] ), - .recv__msg( input_units__recv__msg[1] ), - .recv__rdy( input_units__recv__rdy[1] ), - .recv__val( input_units__recv__val[1] ), - .send__msg( input_units__send__msg[1] ), - .send__rdy( input_units__send__rdy[1] ), - .send__val( input_units__send__val[1] ) - ); - - InputUnitRTL__cff279ef5009e7c6 input_units__2 - ( - .clk( input_units__clk[2] ), - .reset( input_units__reset[2] ), - .recv__msg( input_units__recv__msg[2] ), - .recv__rdy( input_units__recv__rdy[2] ), - .recv__val( input_units__recv__val[2] ), - .send__msg( input_units__send__msg[2] ), - .send__rdy( input_units__send__rdy[2] ), - .send__val( input_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component input_units[0:2] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component output_units[0:7] - //------------------------------------------------------------- - - logic [0:0] output_units__clk [0:7]; - logic [0:0] output_units__reset [0:7]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 output_units__recv__msg [0:7]; - logic [0:0] output_units__recv__rdy [0:7]; - logic [0:0] output_units__recv__val [0:7]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 output_units__send__msg [0:7]; - logic [0:0] output_units__send__rdy [0:7]; - logic [0:0] output_units__send__val [0:7]; - - OutputUnitRTL__e96d78a3d0126314 output_units__0 - ( - .clk( output_units__clk[0] ), - .reset( output_units__reset[0] ), - .recv__msg( output_units__recv__msg[0] ), - .recv__rdy( output_units__recv__rdy[0] ), - .recv__val( output_units__recv__val[0] ), - .send__msg( output_units__send__msg[0] ), - .send__rdy( output_units__send__rdy[0] ), - .send__val( output_units__send__val[0] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__1 - ( - .clk( output_units__clk[1] ), - .reset( output_units__reset[1] ), - .recv__msg( output_units__recv__msg[1] ), - .recv__rdy( output_units__recv__rdy[1] ), - .recv__val( output_units__recv__val[1] ), - .send__msg( output_units__send__msg[1] ), - .send__rdy( output_units__send__rdy[1] ), - .send__val( output_units__send__val[1] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__2 - ( - .clk( output_units__clk[2] ), - .reset( output_units__reset[2] ), - .recv__msg( output_units__recv__msg[2] ), - .recv__rdy( output_units__recv__rdy[2] ), - .recv__val( output_units__recv__val[2] ), - .send__msg( output_units__send__msg[2] ), - .send__rdy( output_units__send__rdy[2] ), - .send__val( output_units__send__val[2] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__3 - ( - .clk( output_units__clk[3] ), - .reset( output_units__reset[3] ), - .recv__msg( output_units__recv__msg[3] ), - .recv__rdy( output_units__recv__rdy[3] ), - .recv__val( output_units__recv__val[3] ), - .send__msg( output_units__send__msg[3] ), - .send__rdy( output_units__send__rdy[3] ), - .send__val( output_units__send__val[3] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__4 - ( - .clk( output_units__clk[4] ), - .reset( output_units__reset[4] ), - .recv__msg( output_units__recv__msg[4] ), - .recv__rdy( output_units__recv__rdy[4] ), - .recv__val( output_units__recv__val[4] ), - .send__msg( output_units__send__msg[4] ), - .send__rdy( output_units__send__rdy[4] ), - .send__val( output_units__send__val[4] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__5 - ( - .clk( output_units__clk[5] ), - .reset( output_units__reset[5] ), - .recv__msg( output_units__recv__msg[5] ), - .recv__rdy( output_units__recv__rdy[5] ), - .recv__val( output_units__recv__val[5] ), - .send__msg( output_units__send__msg[5] ), - .send__rdy( output_units__send__rdy[5] ), - .send__val( output_units__send__val[5] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__6 - ( - .clk( output_units__clk[6] ), - .reset( output_units__reset[6] ), - .recv__msg( output_units__recv__msg[6] ), - .recv__rdy( output_units__recv__rdy[6] ), - .recv__val( output_units__recv__val[6] ), - .send__msg( output_units__send__msg[6] ), - .send__rdy( output_units__send__rdy[6] ), - .send__val( output_units__send__val[6] ) - ); - - OutputUnitRTL__e96d78a3d0126314 output_units__7 - ( - .clk( output_units__clk[7] ), - .reset( output_units__reset[7] ), - .recv__msg( output_units__recv__msg[7] ), - .recv__rdy( output_units__recv__rdy[7] ), - .recv__val( output_units__recv__val[7] ), - .send__msg( output_units__send__msg[7] ), - .send__rdy( output_units__send__rdy[7] ), - .send__val( output_units__send__val[7] ) - ); - - //------------------------------------------------------------- - // End of component output_units[0:7] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component route_units[0:2] - //------------------------------------------------------------- - - logic [0:0] route_units__clk [0:2]; - logic [0:0] route_units__reset [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 route_units__recv__msg [0:2]; - logic [0:0] route_units__recv__rdy [0:2]; - logic [0:0] route_units__recv__val [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 route_units__send__msg [0:2][0:7]; - logic [0:0] route_units__send__rdy [0:2][0:7]; - logic [0:0] route_units__send__val [0:2][0:7]; - - XbarRouteUnitRTL__c063f4910bbc0b50 route_units__0 - ( - .clk( route_units__clk[0] ), - .reset( route_units__reset[0] ), - .recv__msg( route_units__recv__msg[0] ), - .recv__rdy( route_units__recv__rdy[0] ), - .recv__val( route_units__recv__val[0] ), - .send__msg( route_units__send__msg[0] ), - .send__rdy( route_units__send__rdy[0] ), - .send__val( route_units__send__val[0] ) - ); - - XbarRouteUnitRTL__c063f4910bbc0b50 route_units__1 - ( - .clk( route_units__clk[1] ), - .reset( route_units__reset[1] ), - .recv__msg( route_units__recv__msg[1] ), - .recv__rdy( route_units__recv__rdy[1] ), - .recv__val( route_units__recv__val[1] ), - .send__msg( route_units__send__msg[1] ), - .send__rdy( route_units__send__rdy[1] ), - .send__val( route_units__send__val[1] ) - ); - - XbarRouteUnitRTL__c063f4910bbc0b50 route_units__2 - ( - .clk( route_units__clk[2] ), - .reset( route_units__reset[2] ), - .recv__msg( route_units__recv__msg[2] ), - .recv__rdy( route_units__recv__rdy[2] ), - .recv__val( route_units__recv__val[2] ), - .send__msg( route_units__send__msg[2] ), - .send__rdy( route_units__send__rdy[2] ), - .send__val( route_units__send__val[2] ) - ); - - //------------------------------------------------------------- - // End of component route_units[0:2] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component switch_units[0:7] - //------------------------------------------------------------- - - logic [0:0] switch_units__clk [0:7]; - logic [0:0] switch_units__reset [0:7]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 switch_units__recv__msg [0:7][0:2]; - logic [0:0] switch_units__recv__rdy [0:7][0:2]; - logic [0:0] switch_units__recv__val [0:7][0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 switch_units__send__msg [0:7]; - logic [0:0] switch_units__send__rdy [0:7]; - logic [0:0] switch_units__send__val [0:7]; - - SwitchUnitRTL__4cc70db240bb572a switch_units__0 - ( - .clk( switch_units__clk[0] ), - .reset( switch_units__reset[0] ), - .recv__msg( switch_units__recv__msg[0] ), - .recv__rdy( switch_units__recv__rdy[0] ), - .recv__val( switch_units__recv__val[0] ), - .send__msg( switch_units__send__msg[0] ), - .send__rdy( switch_units__send__rdy[0] ), - .send__val( switch_units__send__val[0] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__1 - ( - .clk( switch_units__clk[1] ), - .reset( switch_units__reset[1] ), - .recv__msg( switch_units__recv__msg[1] ), - .recv__rdy( switch_units__recv__rdy[1] ), - .recv__val( switch_units__recv__val[1] ), - .send__msg( switch_units__send__msg[1] ), - .send__rdy( switch_units__send__rdy[1] ), - .send__val( switch_units__send__val[1] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__2 - ( - .clk( switch_units__clk[2] ), - .reset( switch_units__reset[2] ), - .recv__msg( switch_units__recv__msg[2] ), - .recv__rdy( switch_units__recv__rdy[2] ), - .recv__val( switch_units__recv__val[2] ), - .send__msg( switch_units__send__msg[2] ), - .send__rdy( switch_units__send__rdy[2] ), - .send__val( switch_units__send__val[2] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__3 - ( - .clk( switch_units__clk[3] ), - .reset( switch_units__reset[3] ), - .recv__msg( switch_units__recv__msg[3] ), - .recv__rdy( switch_units__recv__rdy[3] ), - .recv__val( switch_units__recv__val[3] ), - .send__msg( switch_units__send__msg[3] ), - .send__rdy( switch_units__send__rdy[3] ), - .send__val( switch_units__send__val[3] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__4 - ( - .clk( switch_units__clk[4] ), - .reset( switch_units__reset[4] ), - .recv__msg( switch_units__recv__msg[4] ), - .recv__rdy( switch_units__recv__rdy[4] ), - .recv__val( switch_units__recv__val[4] ), - .send__msg( switch_units__send__msg[4] ), - .send__rdy( switch_units__send__rdy[4] ), - .send__val( switch_units__send__val[4] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__5 - ( - .clk( switch_units__clk[5] ), - .reset( switch_units__reset[5] ), - .recv__msg( switch_units__recv__msg[5] ), - .recv__rdy( switch_units__recv__rdy[5] ), - .recv__val( switch_units__recv__val[5] ), - .send__msg( switch_units__send__msg[5] ), - .send__rdy( switch_units__send__rdy[5] ), - .send__val( switch_units__send__val[5] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__6 - ( - .clk( switch_units__clk[6] ), - .reset( switch_units__reset[6] ), - .recv__msg( switch_units__recv__msg[6] ), - .recv__rdy( switch_units__recv__rdy[6] ), - .recv__val( switch_units__recv__val[6] ), - .send__msg( switch_units__send__msg[6] ), - .send__rdy( switch_units__send__rdy[6] ), - .send__val( switch_units__send__val[6] ) - ); - - SwitchUnitRTL__4cc70db240bb572a switch_units__7 - ( - .clk( switch_units__clk[7] ), - .reset( switch_units__reset[7] ), - .recv__msg( switch_units__recv__msg[7] ), - .recv__rdy( switch_units__recv__rdy[7] ), - .recv__val( switch_units__recv__val[7] ), - .send__msg( switch_units__send__msg[7] ), - .send__rdy( switch_units__send__rdy[7] ), - .send__val( switch_units__send__val[7] ) - ); - - //------------------------------------------------------------- - // End of component switch_units[0:7] - //------------------------------------------------------------- - - assign input_units__clk[0] = clk; - assign input_units__reset[0] = reset; - assign input_units__clk[1] = clk; - assign input_units__reset[1] = reset; - assign input_units__clk[2] = clk; - assign input_units__reset[2] = reset; - assign route_units__clk[0] = clk; - assign route_units__reset[0] = reset; - assign route_units__clk[1] = clk; - assign route_units__reset[1] = reset; - assign route_units__clk[2] = clk; - assign route_units__reset[2] = reset; - assign switch_units__clk[0] = clk; - assign switch_units__reset[0] = reset; - assign switch_units__clk[1] = clk; - assign switch_units__reset[1] = reset; - assign switch_units__clk[2] = clk; - assign switch_units__reset[2] = reset; - assign switch_units__clk[3] = clk; - assign switch_units__reset[3] = reset; - assign switch_units__clk[4] = clk; - assign switch_units__reset[4] = reset; - assign switch_units__clk[5] = clk; - assign switch_units__reset[5] = reset; - assign switch_units__clk[6] = clk; - assign switch_units__reset[6] = reset; - assign switch_units__clk[7] = clk; - assign switch_units__reset[7] = reset; - assign output_units__clk[0] = clk; - assign output_units__reset[0] = reset; - assign output_units__clk[1] = clk; - assign output_units__reset[1] = reset; - assign output_units__clk[2] = clk; - assign output_units__reset[2] = reset; - assign output_units__clk[3] = clk; - assign output_units__reset[3] = reset; - assign output_units__clk[4] = clk; - assign output_units__reset[4] = reset; - assign output_units__clk[5] = clk; - assign output_units__reset[5] = reset; - assign output_units__clk[6] = clk; - assign output_units__reset[6] = reset; - assign output_units__clk[7] = clk; - assign output_units__reset[7] = reset; - assign input_units__recv__msg[0] = recv__msg[0]; - assign recv__rdy[0] = input_units__recv__rdy[0]; - assign input_units__recv__val[0] = recv__val[0]; - assign route_units__recv__msg[0] = input_units__send__msg[0]; - assign input_units__send__rdy[0] = route_units__recv__rdy[0]; - assign route_units__recv__val[0] = input_units__send__val[0]; - assign input_units__recv__msg[1] = recv__msg[1]; - assign recv__rdy[1] = input_units__recv__rdy[1]; - assign input_units__recv__val[1] = recv__val[1]; - assign route_units__recv__msg[1] = input_units__send__msg[1]; - assign input_units__send__rdy[1] = route_units__recv__rdy[1]; - assign route_units__recv__val[1] = input_units__send__val[1]; - assign input_units__recv__msg[2] = recv__msg[2]; - assign recv__rdy[2] = input_units__recv__rdy[2]; - assign input_units__recv__val[2] = recv__val[2]; - assign route_units__recv__msg[2] = input_units__send__msg[2]; - assign input_units__send__rdy[2] = route_units__recv__rdy[2]; - assign route_units__recv__val[2] = input_units__send__val[2]; - assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; - assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; - assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; - assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; - assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; - assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; - assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; - assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; - assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; - assign switch_units__recv__msg[3][0] = route_units__send__msg[0][3]; - assign route_units__send__rdy[0][3] = switch_units__recv__rdy[3][0]; - assign switch_units__recv__val[3][0] = route_units__send__val[0][3]; - assign switch_units__recv__msg[4][0] = route_units__send__msg[0][4]; - assign route_units__send__rdy[0][4] = switch_units__recv__rdy[4][0]; - assign switch_units__recv__val[4][0] = route_units__send__val[0][4]; - assign switch_units__recv__msg[5][0] = route_units__send__msg[0][5]; - assign route_units__send__rdy[0][5] = switch_units__recv__rdy[5][0]; - assign switch_units__recv__val[5][0] = route_units__send__val[0][5]; - assign switch_units__recv__msg[6][0] = route_units__send__msg[0][6]; - assign route_units__send__rdy[0][6] = switch_units__recv__rdy[6][0]; - assign switch_units__recv__val[6][0] = route_units__send__val[0][6]; - assign switch_units__recv__msg[7][0] = route_units__send__msg[0][7]; - assign route_units__send__rdy[0][7] = switch_units__recv__rdy[7][0]; - assign switch_units__recv__val[7][0] = route_units__send__val[0][7]; - assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; - assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; - assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; - assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; - assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; - assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; - assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; - assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; - assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; - assign switch_units__recv__msg[3][1] = route_units__send__msg[1][3]; - assign route_units__send__rdy[1][3] = switch_units__recv__rdy[3][1]; - assign switch_units__recv__val[3][1] = route_units__send__val[1][3]; - assign switch_units__recv__msg[4][1] = route_units__send__msg[1][4]; - assign route_units__send__rdy[1][4] = switch_units__recv__rdy[4][1]; - assign switch_units__recv__val[4][1] = route_units__send__val[1][4]; - assign switch_units__recv__msg[5][1] = route_units__send__msg[1][5]; - assign route_units__send__rdy[1][5] = switch_units__recv__rdy[5][1]; - assign switch_units__recv__val[5][1] = route_units__send__val[1][5]; - assign switch_units__recv__msg[6][1] = route_units__send__msg[1][6]; - assign route_units__send__rdy[1][6] = switch_units__recv__rdy[6][1]; - assign switch_units__recv__val[6][1] = route_units__send__val[1][6]; - assign switch_units__recv__msg[7][1] = route_units__send__msg[1][7]; - assign route_units__send__rdy[1][7] = switch_units__recv__rdy[7][1]; - assign switch_units__recv__val[7][1] = route_units__send__val[1][7]; - assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; - assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; - assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; - assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; - assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; - assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; - assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; - assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; - assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; - assign switch_units__recv__msg[3][2] = route_units__send__msg[2][3]; - assign route_units__send__rdy[2][3] = switch_units__recv__rdy[3][2]; - assign switch_units__recv__val[3][2] = route_units__send__val[2][3]; - assign switch_units__recv__msg[4][2] = route_units__send__msg[2][4]; - assign route_units__send__rdy[2][4] = switch_units__recv__rdy[4][2]; - assign switch_units__recv__val[4][2] = route_units__send__val[2][4]; - assign switch_units__recv__msg[5][2] = route_units__send__msg[2][5]; - assign route_units__send__rdy[2][5] = switch_units__recv__rdy[5][2]; - assign switch_units__recv__val[5][2] = route_units__send__val[2][5]; - assign switch_units__recv__msg[6][2] = route_units__send__msg[2][6]; - assign route_units__send__rdy[2][6] = switch_units__recv__rdy[6][2]; - assign switch_units__recv__val[6][2] = route_units__send__val[2][6]; - assign switch_units__recv__msg[7][2] = route_units__send__msg[2][7]; - assign route_units__send__rdy[2][7] = switch_units__recv__rdy[7][2]; - assign switch_units__recv__val[7][2] = route_units__send__val[2][7]; - assign output_units__recv__msg[0] = switch_units__send__msg[0]; - assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; - assign output_units__recv__val[0] = switch_units__send__val[0]; - assign send__msg[0] = output_units__send__msg[0]; - assign output_units__send__rdy[0] = send__rdy[0]; - assign send__val[0] = output_units__send__val[0]; - assign output_units__recv__msg[1] = switch_units__send__msg[1]; - assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; - assign output_units__recv__val[1] = switch_units__send__val[1]; - assign send__msg[1] = output_units__send__msg[1]; - assign output_units__send__rdy[1] = send__rdy[1]; - assign send__val[1] = output_units__send__val[1]; - assign output_units__recv__msg[2] = switch_units__send__msg[2]; - assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; - assign output_units__recv__val[2] = switch_units__send__val[2]; - assign send__msg[2] = output_units__send__msg[2]; - assign output_units__send__rdy[2] = send__rdy[2]; - assign send__val[2] = output_units__send__val[2]; - assign output_units__recv__msg[3] = switch_units__send__msg[3]; - assign switch_units__send__rdy[3] = output_units__recv__rdy[3]; - assign output_units__recv__val[3] = switch_units__send__val[3]; - assign send__msg[3] = output_units__send__msg[3]; - assign output_units__send__rdy[3] = send__rdy[3]; - assign send__val[3] = output_units__send__val[3]; - assign output_units__recv__msg[4] = switch_units__send__msg[4]; - assign switch_units__send__rdy[4] = output_units__recv__rdy[4]; - assign output_units__recv__val[4] = switch_units__send__val[4]; - assign send__msg[4] = output_units__send__msg[4]; - assign output_units__send__rdy[4] = send__rdy[4]; - assign send__val[4] = output_units__send__val[4]; - assign output_units__recv__msg[5] = switch_units__send__msg[5]; - assign switch_units__send__rdy[5] = output_units__recv__rdy[5]; - assign output_units__recv__val[5] = switch_units__send__val[5]; - assign send__msg[5] = output_units__send__msg[5]; - assign output_units__send__rdy[5] = send__rdy[5]; - assign send__val[5] = output_units__send__val[5]; - assign output_units__recv__msg[6] = switch_units__send__msg[6]; - assign switch_units__send__rdy[6] = output_units__recv__rdy[6]; - assign output_units__recv__val[6] = switch_units__send__val[6]; - assign send__msg[6] = output_units__send__msg[6]; - assign output_units__send__rdy[6] = send__rdy[6]; - assign send__val[6] = output_units__send__val[6]; - assign output_units__recv__msg[7] = switch_units__send__msg[7]; - assign switch_units__send__rdy[7] = output_units__recv__rdy[7]; - assign output_units__recv__val[7] = switch_units__send__val[7]; - assign send__msg[7] = output_units__send__msg[7]; - assign output_units__send__rdy[7] = send__rdy[7]; - assign send__val[7] = output_units__send__val[7]; - -endmodule - - -// PyMTL Component DataMemControllerRTL Definition -// Full name: DataMemControllerRTL__NocPktType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_rd_tiles_7__num_wr_tiles_7__multi_cgra_rows_2__multi_cgra_columns_2__num_tiles_16__mem_access_is_combinational_True__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)} -// At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py - -module DataMemControllerRTL__20df9b544ed809f0 -( - input logic [6:0] address_lower , - input logic [6:0] address_upper , - input logic [1:0] cgra_id , - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_load_request__msg , - output logic [0:0] recv_from_noc_load_request__rdy , - input logic [0:0] recv_from_noc_load_request__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_load_response_pkt__msg , - output logic [0:0] recv_from_noc_load_response_pkt__rdy , - input logic [0:0] recv_from_noc_load_response_pkt__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_noc_store_request__msg , - output logic [0:0] recv_from_noc_store_request__rdy , - input logic [0:0] recv_from_noc_store_request__val , - input logic [6:0] recv_raddr__msg [0:6] , - output logic [0:0] recv_raddr__rdy [0:6] , - input logic [0:0] recv_raddr__val [0:6] , - input logic [6:0] recv_waddr__msg [0:6] , - output logic [0:0] recv_waddr__rdy [0:6] , - input logic [0:0] recv_waddr__val [0:6] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_wdata__msg [0:6] , - output logic [0:0] recv_wdata__rdy [0:6] , - input logic [0:0] recv_wdata__val [0:6] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_rdata__msg [0:6] , - input logic [0:0] send_rdata__rdy [0:6] , - output logic [0:0] send_rdata__val [0:6] , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_load_request_pkt__msg , - input logic [0:0] send_to_noc_load_request_pkt__rdy , - output logic [0:0] send_to_noc_load_request_pkt__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_load_response_pkt__msg , - input logic [0:0] send_to_noc_load_response_pkt__rdy , - output logic [0:0] send_to_noc_load_response_pkt__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_noc_store_pkt__msg , - input logic [0:0] send_to_noc_store_pkt__rdy , - output logic [0:0] send_to_noc_store_pkt__val -); - localparam logic [3:0] __const__num_xbar_in_rd_ports_at_assemble_xbar_pkt = 4'd8; - localparam logic [3:0] __const__num_xbar_in_wr_ports_at_assemble_xbar_pkt = 4'd8; - localparam logic [2:0] __const__num_rd_tiles_at_assemble_xbar_pkt = 3'd7; - localparam logic [2:0] __const__per_bank_addr_nbits_at_assemble_xbar_pkt = 3'd4; - localparam logic [1:0] __const__num_banks_per_cgra_at_assemble_xbar_pkt = 2'd2; - localparam logic [2:0] __const__num_wr_tiles_at_assemble_xbar_pkt = 3'd7; - localparam logic [2:0] __const__num_rd_tiles_at_update_all = 3'd7; - localparam logic [2:0] __const__num_wr_tiles_at_update_all = 3'd7; - localparam logic [3:0] __const__num_xbar_in_rd_ports_at_update_all = 4'd8; - localparam logic [3:0] __const__num_xbar_in_wr_ports_at_update_all = 4'd8; - localparam logic [3:0] __const__CMD_LOAD_RESPONSE = 4'd11; - localparam logic [1:0] __const__num_banks_per_cgra_at_update_all = 2'd2; - localparam logic [3:0] __const__CMD_LOAD_REQUEST = 4'd10; - localparam logic [3:0] __const__CMD_STORE_REQUEST = 4'd12; - logic [0:0] idTo2d_x_lut [0:3]; - logic [0:0] idTo2d_y_lut [0:3]; - MemAccessPacket_8_3_128__43c148781d2f2a57 rd_pkt [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 wr_pkt [0:7]; - //------------------------------------------------------------- - // Component memory_wrapper[0:1] - //------------------------------------------------------------- - - logic [0:0] memory_wrapper__clk [0:1]; - logic [0:0] memory_wrapper__reset [0:1]; - MemAccessPacket_8_3_128__43c148781d2f2a57 memory_wrapper__recv_rd__msg [0:1]; - logic [0:0] memory_wrapper__recv_rd__rdy [0:1]; - logic [0:0] memory_wrapper__recv_rd__val [0:1]; - MemAccessPacket_8_3_128__43c148781d2f2a57 memory_wrapper__recv_wr__msg [0:1]; - logic [0:0] memory_wrapper__recv_wr__rdy [0:1]; - logic [0:0] memory_wrapper__recv_wr__val [0:1]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 memory_wrapper__send__msg [0:1]; - logic [0:0] memory_wrapper__send__rdy [0:1]; - logic [0:0] memory_wrapper__send__val [0:1]; - - DataMemWrapperRTL__33e0a5b37976e571 memory_wrapper__0 - ( - .clk( memory_wrapper__clk[0] ), - .reset( memory_wrapper__reset[0] ), - .recv_rd__msg( memory_wrapper__recv_rd__msg[0] ), - .recv_rd__rdy( memory_wrapper__recv_rd__rdy[0] ), - .recv_rd__val( memory_wrapper__recv_rd__val[0] ), - .recv_wr__msg( memory_wrapper__recv_wr__msg[0] ), - .recv_wr__rdy( memory_wrapper__recv_wr__rdy[0] ), - .recv_wr__val( memory_wrapper__recv_wr__val[0] ), - .send__msg( memory_wrapper__send__msg[0] ), - .send__rdy( memory_wrapper__send__rdy[0] ), - .send__val( memory_wrapper__send__val[0] ) - ); - - DataMemWrapperRTL__33e0a5b37976e571 memory_wrapper__1 - ( - .clk( memory_wrapper__clk[1] ), - .reset( memory_wrapper__reset[1] ), - .recv_rd__msg( memory_wrapper__recv_rd__msg[1] ), - .recv_rd__rdy( memory_wrapper__recv_rd__rdy[1] ), - .recv_rd__val( memory_wrapper__recv_rd__val[1] ), - .recv_wr__msg( memory_wrapper__recv_wr__msg[1] ), - .recv_wr__rdy( memory_wrapper__recv_wr__rdy[1] ), - .recv_wr__val( memory_wrapper__recv_wr__val[1] ), - .send__msg( memory_wrapper__send__msg[1] ), - .send__rdy( memory_wrapper__send__rdy[1] ), - .send__val( memory_wrapper__send__val[1] ) - ); - - //------------------------------------------------------------- - // End of component memory_wrapper[0:1] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component read_crossbar - //------------------------------------------------------------- - - logic [0:0] read_crossbar__clk; - logic [0:0] read_crossbar__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 read_crossbar__recv__msg [0:7]; - logic [0:0] read_crossbar__recv__rdy [0:7]; - logic [0:0] read_crossbar__recv__val [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 read_crossbar__send__msg [0:2]; - logic [0:0] read_crossbar__send__rdy [0:2]; - logic [0:0] read_crossbar__send__val [0:2]; - - XbarBypassQueueRTL__045133ee283ca701 read_crossbar - ( - .clk( read_crossbar__clk ), - .reset( read_crossbar__reset ), - .recv__msg( read_crossbar__recv__msg ), - .recv__rdy( read_crossbar__recv__rdy ), - .recv__val( read_crossbar__recv__val ), - .send__msg( read_crossbar__send__msg ), - .send__rdy( read_crossbar__send__rdy ), - .send__val( read_crossbar__send__val ) - ); - - //------------------------------------------------------------- - // End of component read_crossbar - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component response_crossbar - //------------------------------------------------------------- - - logic [0:0] response_crossbar__clk; - logic [0:0] response_crossbar__reset; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 response_crossbar__recv__msg [0:2]; - logic [0:0] response_crossbar__recv__rdy [0:2]; - logic [0:0] response_crossbar__recv__val [0:2]; - MemAccessPacket_3_8_128__9f21b0bcdad2c061 response_crossbar__send__msg [0:7]; - logic [0:0] response_crossbar__send__rdy [0:7]; - logic [0:0] response_crossbar__send__val [0:7]; - - XbarBypassQueueRTL__510da12df6787984 response_crossbar - ( - .clk( response_crossbar__clk ), - .reset( response_crossbar__reset ), - .recv__msg( response_crossbar__recv__msg ), - .recv__rdy( response_crossbar__recv__rdy ), - .recv__val( response_crossbar__recv__val ), - .send__msg( response_crossbar__send__msg ), - .send__rdy( response_crossbar__send__rdy ), - .send__val( response_crossbar__send__val ) - ); - - //------------------------------------------------------------- - // End of component response_crossbar - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component write_crossbar - //------------------------------------------------------------- - - logic [0:0] write_crossbar__clk; - logic [0:0] write_crossbar__reset; - MemAccessPacket_8_3_128__43c148781d2f2a57 write_crossbar__recv__msg [0:7]; - logic [0:0] write_crossbar__recv__rdy [0:7]; - logic [0:0] write_crossbar__recv__val [0:7]; - MemAccessPacket_8_3_128__43c148781d2f2a57 write_crossbar__send__msg [0:2]; - logic [0:0] write_crossbar__send__rdy [0:2]; - logic [0:0] write_crossbar__send__val [0:2]; - - XbarBypassQueueRTL__045133ee283ca701 write_crossbar - ( - .clk( write_crossbar__clk ), - .reset( write_crossbar__reset ), - .recv__msg( write_crossbar__recv__msg ), - .recv__rdy( write_crossbar__recv__rdy ), - .recv__val( write_crossbar__recv__val ), - .send__msg( write_crossbar__send__msg ), - .send__rdy( write_crossbar__send__rdy ), - .send__val( write_crossbar__send__val ) - ); - - //------------------------------------------------------------- - // End of component write_crossbar - //------------------------------------------------------------- - logic [6:0] __tmpvar__assemble_xbar_pkt_recv_raddr; - logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_load_local; - logic [6:0] __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc; - logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc; - logic [6:0] __tmpvar__assemble_xbar_pkt_recv_waddr; - logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_store_local; - logic [6:0] __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc; - logic [1:0] __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc; - logic [1:0] __tmpvar__update_all_from_cgra_id; - logic [4:0] __tmpvar__update_all_from_tile_id; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py:159 - // @update - // def assemble_xbar_pkt(): - // for i in range(num_xbar_in_rd_ports): - // s.rd_pkt[i] @= MemReadPktType(i, 0, 0, DataType(0, 0, 0, 0), 0, 0, i, 0, 0, 0) - // - // for i in range(num_xbar_in_wr_ports): - // s.wr_pkt[i] @= MemWritePktType(i, 0, 0, DataType(0, 0, 0, 0), 0, 0, i, 0, 0, 0) - // - // for i in range(num_rd_tiles): - // recv_raddr = s.recv_raddr[i].msg - // # Calculates the target bank index for load. - // if (recv_raddr >= s.address_lower) & (recv_raddr <= s.address_upper): - // bank_index_load_local = trunc((recv_raddr - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType) - // else: - // bank_index_load_local = XbarOutRdType(num_banks_per_cgra) - // # FIXME: change to exact tile id. - // s.rd_pkt[i] @= MemReadPktType(i, # src - // bank_index_load_local, # dst - // recv_raddr, # addr - // DataType(0, 0, 0, 0), # data - // s.cgra_id, # src_cgra - // 0, # src_tile - // i, # remote_src_port - // 0, # streaming_rd - // 0, # streaming_rd_stride - // 0) # streaming_rd_end_addr - // - // recv_raddr_from_noc = s.recv_from_noc_load_request.msg.payload.data_addr - // # Calculates the target bank index. - // if (recv_raddr_from_noc >= s.address_lower) & (recv_raddr_from_noc <= s.address_upper): - // bank_index_load_from_noc = trunc((recv_raddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutRdType) - // else: - // bank_index_load_from_noc = XbarOutRdType(num_banks_per_cgra) - // s.rd_pkt[num_rd_tiles] @= MemReadPktType(num_rd_tiles, # src - // bank_index_load_from_noc, # dst - // recv_raddr_from_noc, # addr - // DataType(0, 0, 0, 0), # data - // s.recv_from_noc_load_request.msg.src, # src_cgra - // s.recv_from_noc_load_request.msg.src_tile_id, # src_tile - // s.recv_from_noc_load_request.msg.remote_src_port, # remote_src_port - // 0, # streaming_rd - // 0, # streaming_rd_stride - // 0) # streaming_rd_end_addr - // - // - // for i in range(num_wr_tiles): - // recv_waddr = s.recv_waddr[i].msg - // # Calculates the target bank index for store. - // if (recv_waddr >= s.address_lower) & (recv_waddr <= s.address_upper): - // bank_index_store_local = trunc((recv_waddr - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType) - // else: - // bank_index_store_local = XbarOutWrType(num_banks_per_cgra) - // s.wr_pkt[i] @= MemWritePktType(i, # src - // bank_index_store_local, # dst - // recv_waddr, # addr - // s.recv_wdata[i].msg, # data - // 0, # src_cgra - // 0, # src_tile - // i, # remote_src_port - // 0, # streaming_rd - // 0, # streaming_rd_stride - // 0) # streaming_rd_end_addr - // - // - // recv_waddr_from_noc = s.recv_from_noc_store_request.msg.payload.data_addr - // recv_wdata_from_noc = s.recv_from_noc_store_request.msg.payload.data - // if (recv_waddr_from_noc >= s.address_lower) & (recv_waddr_from_noc <= s.address_upper): - // bank_index_store_from_noc = trunc((recv_waddr_from_noc - s.address_lower) >> per_bank_addr_nbits, XbarOutWrType) - // else: - // bank_index_store_from_noc = XbarOutWrType(num_banks_per_cgra) - // s.wr_pkt[num_wr_tiles] @= MemWritePktType(num_wr_tiles, # src - // bank_index_store_from_noc, # dst - // recv_waddr_from_noc, # addr - // recv_wdata_from_noc, # data - // 0, # src_cgra - // 0, # src_tile - // num_wr_tiles, # remote_src_port - // 0, # streaming_rd - // 0, # streaming_rd_stride - // 0) # streaming_rd_end_addr - - always_comb begin : assemble_xbar_pkt - for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_assemble_xbar_pkt ); i += 1'd1 ) - rd_pkt[3'(i)] = { 3'(i), 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; - for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_wr_ports_at_assemble_xbar_pkt ); i += 1'd1 ) - wr_pkt[3'(i)] = { 3'(i), 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; - for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_assemble_xbar_pkt ); i += 1'd1 ) begin - __tmpvar__assemble_xbar_pkt_recv_raddr = recv_raddr__msg[3'(i)]; - if ( ( __tmpvar__assemble_xbar_pkt_recv_raddr >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_raddr <= address_upper ) ) begin - __tmpvar__assemble_xbar_pkt_bank_index_load_local = 2'(( __tmpvar__assemble_xbar_pkt_recv_raddr - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); - end - else - __tmpvar__assemble_xbar_pkt_bank_index_load_local = 2'd2; - rd_pkt[3'(i)] = { 3'(i), __tmpvar__assemble_xbar_pkt_bank_index_load_local, __tmpvar__assemble_xbar_pkt_recv_raddr, { 64'd0, 1'd0, 1'd0, 1'd0 }, cgra_id, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; - end - __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc = recv_from_noc_load_request__msg.payload.data_addr; - if ( ( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc <= address_upper ) ) begin - __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc = 2'(( __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); - end - else - __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc = 2'd2; - rd_pkt[3'( __const__num_rd_tiles_at_assemble_xbar_pkt )] = { 3'( __const__num_rd_tiles_at_assemble_xbar_pkt ), __tmpvar__assemble_xbar_pkt_bank_index_load_from_noc, __tmpvar__assemble_xbar_pkt_recv_raddr_from_noc, { 64'd0, 1'd0, 1'd0, 1'd0 }, recv_from_noc_load_request__msg.src, recv_from_noc_load_request__msg.src_tile_id, recv_from_noc_load_request__msg.remote_src_port, 1'd0, 7'd0, 7'd0 }; - for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ); i += 1'd1 ) begin - __tmpvar__assemble_xbar_pkt_recv_waddr = recv_waddr__msg[3'(i)]; - if ( ( __tmpvar__assemble_xbar_pkt_recv_waddr >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_waddr <= address_upper ) ) begin - __tmpvar__assemble_xbar_pkt_bank_index_store_local = 2'(( __tmpvar__assemble_xbar_pkt_recv_waddr - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); - end - else - __tmpvar__assemble_xbar_pkt_bank_index_store_local = 2'd2; - wr_pkt[3'(i)] = { 3'(i), __tmpvar__assemble_xbar_pkt_bank_index_store_local, __tmpvar__assemble_xbar_pkt_recv_waddr, recv_wdata__msg[3'(i)], 2'd0, 5'd0, 3'(i), 1'd0, 7'd0, 7'd0 }; - end - __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc = recv_from_noc_store_request__msg.payload.data_addr; - __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc = recv_from_noc_store_request__msg.payload.data; - if ( ( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc >= address_lower ) & ( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc <= address_upper ) ) begin - __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc = 2'(( __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc - address_lower ) >> 3'( __const__per_bank_addr_nbits_at_assemble_xbar_pkt )); - end - else - __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc = 2'd2; - wr_pkt[3'( __const__num_wr_tiles_at_assemble_xbar_pkt )] = { 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ), __tmpvar__assemble_xbar_pkt_bank_index_store_from_noc, __tmpvar__assemble_xbar_pkt_recv_waddr_from_noc, __tmpvar__assemble_xbar_pkt_recv_wdata_from_noc, 2'd0, 5'd0, 3'( __const__num_wr_tiles_at_assemble_xbar_pkt ), 1'd0, 7'd0, 7'd0 }; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/data/DataMemControllerRTL.py:242 - // @update - // def update_all(): - // # Initializes the signals. - // for i in range(num_rd_tiles): - // s.recv_raddr[i].rdy @= 0 - // s.recv_from_noc_load_request.rdy @= 0 - // - // for i in range(num_wr_tiles): - // s.recv_waddr[i].rdy @= 0 - // # s.recv_wdata_bypass_q[i].send.rdy @= 0 - // s.recv_from_noc_store_request.rdy @= 0 - // # s.recv_wdata_bypass_q[num_wr_tiles].send.rdy @= 0 - // - // for i in range(num_rd_tiles): - // s.send_rdata[i].val @= 0 - // s.send_rdata[i].msg @= DataType() - // s.send_to_noc_load_response_pkt.val @= 0 - // - // s.send_to_noc_load_response_pkt.msg @= \ - // NocPktType(0, # src - // 0, # dst - // 0, # src_x - // 0, # src_y - // 0, # dst_x - // 0, # dst_y - // 0, # src_tile_id - // 0, # dst_tile_id - // 0, # remote_src_port - // 0, # opaque - // 0, # vc_id - // CgraPayloadType(0, 0, 0, 0, 0)) - // - // - // for i in range(num_wr_tiles): - // s.recv_wdata[i].rdy @= 0 - // - // s.send_to_noc_store_pkt.msg @= \ - // NocPktType(0, # src - // 0, # dst - // 0, # src_x - // 0, # src_y - // 0, # dst_x - // 0, # dst_y - // 0, # src_tile_id - // 0, # dst_tile_id - // 0, # remote_src_port - // 0, # opaque - // 0, # vc_id - // CgraPayloadType(0, 0, 0, 0, 0)) - // - // s.send_to_noc_store_pkt.val @= 0 - // - // for i in range(num_xbar_in_rd_ports): - // s.read_crossbar.recv[i].val @= 0 - // s.read_crossbar.recv[i].msg @= MemReadPktType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) - // - // s.recv_from_noc_load_response_pkt.rdy @= 0 - // - // for i in range(num_xbar_in_wr_ports): - // s.write_crossbar.recv[i].val @= 0 - // s.write_crossbar.recv[i].msg @= MemWritePktType(0, 0, 0, DataType(0, 0, 0, 0), 0, 0, 0, 0, 0, 0) - // - // s.send_to_noc_load_request_pkt.msg @= \ - // NocPktType(0, # src - // 0, # dst - // 0, # src_x - // 0, # src_y - // 0, # dst_x - // 0, # dst_y - // 0, # src_tile_id - // 0, # dst_tile_id - // 0, # remote_src_port - // 0, # opaque - // 0, # vc_id - // CgraPayloadType(0, 0, 0, 0, 0)) - // - // s.send_to_noc_load_request_pkt.val @= 0 - // - // # Connects the load request ports (from tiles and NoC) to the xbar targetting memory and NoC. - // for i in range(num_rd_tiles): - // s.read_crossbar.recv[i].val @= s.recv_raddr[i].val - // s.read_crossbar.recv[i].msg @= s.rd_pkt[i] - // s.recv_raddr[i].rdy @= s.read_crossbar.recv[i].rdy - // s.read_crossbar.recv[num_rd_tiles].val @= s.recv_from_noc_load_request.val - // s.read_crossbar.recv[num_rd_tiles].msg @= s.rd_pkt[num_rd_tiles] - // s.recv_from_noc_load_request.rdy @= s.read_crossbar.recv[num_rd_tiles].rdy - // - // # Connects the store request ports (from tiles and NoC) to the xbar targetting memory and NoC. - // for i in range(num_wr_tiles): - // s.write_crossbar.recv[i].val @= s.recv_waddr[i].val - // s.write_crossbar.recv[i].msg @= s.wr_pkt[i] - // s.recv_waddr[i].rdy @= s.write_crossbar.recv[i].rdy - // s.recv_wdata[i].rdy @= s.write_crossbar.recv[i].rdy - // s.write_crossbar.recv[num_wr_tiles].val @= s.recv_from_noc_store_request.val - // s.write_crossbar.recv[num_wr_tiles].msg @= s.wr_pkt[num_wr_tiles] - // s.recv_from_noc_store_request.rdy @= s.write_crossbar.recv[num_wr_tiles].rdy - // - // # Connects the response ports to tiles and NoC from the xbar. - // # Number of load responses is expected to be the same as the number of load requests. - // for i in range(num_xbar_in_rd_ports): - // if i < num_rd_tiles: - // s.send_rdata[RdTileIdType(i)].msg @= s.response_crossbar.send[i].msg.data - // s.send_rdata[RdTileIdType(i)].val @= s.response_crossbar.send[i].val - // s.response_crossbar.send[i].rdy @= s.send_rdata[RdTileIdType(i)].rdy - // else: - // from_cgra_id = s.response_crossbar.send[i].msg.src_cgra - // from_tile_id = s.response_crossbar.send[i].msg.src_tile - // s.send_to_noc_load_response_pkt.msg @= \ - // NocPktType( - // s.cgra_id, # src_cgra_id - // from_cgra_id, # dst_cgra_id - // s.idTo2d_x_lut[s.cgra_id], # src_cgra_x - // s.idTo2d_y_lut[s.cgra_id], # src_cgra_y - // s.idTo2d_x_lut[from_cgra_id], # dst_cgra_x - // s.idTo2d_y_lut[from_cgra_id], # dst_cgra_y - // 0, # src_tile_id set as 0 as it is from memory rather than a specific tile. - // from_tile_id, # dst_tile_id - // s.response_crossbar.send[i].msg.remote_src_port, # remote_src_port, carries the original source port id towards the src. - // 0, # opaque - // 0, # vc_id - // CgraPayloadType( - // CMD_LOAD_RESPONSE, - // s.response_crossbar.send[i].msg.data, - // s.response_crossbar.send[i].msg.addr, 0, 0)) - // - // s.send_to_noc_load_response_pkt.val @= s.response_crossbar.send[i].val - // s.response_crossbar.send[i].rdy @= s.send_to_noc_load_response_pkt.rdy - // - // # Handles the request (not response) towards the others via the NoC. The dst would be - // # updated in the controller. - // s.send_to_noc_load_request_pkt.msg @= \ - // NocPktType(s.cgra_id, # src - // 0, # dst - // s.idTo2d_x_lut[s.cgra_id], # src_x - // s.idTo2d_y_lut[s.cgra_id], # src_y - // 0, # dst_x - // 0, # dst_y - // 0, # src_tile_id - // 0, # dst_tile_id - // s.read_crossbar.send[num_banks_per_cgra].msg.src, # remote_src_port - // 0, # opaque - // 0, # vc_id - // CgraPayloadType( - // CMD_LOAD_REQUEST, - // 0, - // s.read_crossbar.send[num_banks_per_cgra].msg.addr, 0, 0)) - // - // s.send_to_noc_load_request_pkt.val @= s.read_crossbar.send[num_banks_per_cgra].val - // # TODO: https://github.com/tancheng/VectorCGRA/issues/26 -- Modify this part for non-blocking access. - // # 'val` indicates the data is arbitrated successfully. - // s.recv_from_noc_load_response_pkt.rdy @= s.response_crossbar.recv[num_banks_per_cgra].rdy - // s.response_crossbar.recv[num_banks_per_cgra].val @= s.recv_from_noc_load_response_pkt.val - // s.response_crossbar.recv[num_banks_per_cgra].msg @= \ - // MemResponsePktType(num_banks_per_cgra, - // s.recv_from_noc_load_response_pkt.msg.remote_src_port, - // s.recv_from_noc_load_response_pkt.msg.payload.data_addr, - // s.recv_from_noc_load_response_pkt.msg.payload.data, - // s.recv_from_noc_load_response_pkt.msg.src, - // s.recv_from_noc_load_response_pkt.msg.src_tile_id, - // 0, - // 0, # streaming_rd - // 0, # streaming_rd_stride - // 0) # streaming_rd_end_addr - // - // # Allows other load request towards NoC when the previous one is not responded. There - // # could be out-of-order load response, i.e., potential consistency issue. - // s.read_crossbar.send[num_banks_per_cgra].rdy @= s.send_to_noc_load_request_pkt.rdy - // - // # Handles the write port towards the NoC. - // s.send_to_noc_store_pkt.msg @= \ - // NocPktType(s.cgra_id, # src - // 0, # dst - // s.idTo2d_x_lut[s.cgra_id], # src_x - // s.idTo2d_y_lut[s.cgra_id], # src_y - // 0, # dst_x - // 0, # dst_y - // 0, # src_tile_id - // 0, # dst_tile_id - // s.write_crossbar.send[num_banks_per_cgra].msg.src, # remote_src_port - // 0, # opaque - // 0, # vc_id - // CgraPayloadType( - // CMD_STORE_REQUEST, - // s.write_crossbar.send[num_banks_per_cgra].msg.data, - // s.write_crossbar.send[num_banks_per_cgra].msg.addr, 0, 0)) - // - // s.send_to_noc_store_pkt.val @= s.write_crossbar.send[num_banks_per_cgra].val - // s.write_crossbar.send[num_banks_per_cgra].rdy @= s.send_to_noc_store_pkt.rdy - - always_comb begin : update_all - for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) - recv_raddr__rdy[3'(i)] = 1'd0; - recv_from_noc_load_request__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) - recv_waddr__rdy[3'(i)] = 1'd0; - recv_from_noc_store_request__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) begin - send_rdata__val[3'(i)] = 1'd0; - send_rdata__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - send_to_noc_load_response_pkt__val = 1'd0; - send_to_noc_load_response_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; - for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) - recv_wdata__rdy[3'(i)] = 1'd0; - send_to_noc_store_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; - send_to_noc_store_pkt__val = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_update_all ); i += 1'd1 ) begin - read_crossbar__recv__val[3'(i)] = 1'd0; - read_crossbar__recv__msg[3'(i)] = { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; - end - recv_from_noc_load_response_pkt__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_wr_ports_at_update_all ); i += 1'd1 ) begin - write_crossbar__recv__val[3'(i)] = 1'd0; - write_crossbar__recv__msg[3'(i)] = { 3'd0, 2'd0, 7'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 2'd0, 5'd0, 3'd0, 1'd0, 7'd0, 7'd0 }; - end - send_to_noc_load_request_pkt__msg = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 } }; - send_to_noc_load_request_pkt__val = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_rd_tiles_at_update_all ); i += 1'd1 ) begin - read_crossbar__recv__val[3'(i)] = recv_raddr__val[3'(i)]; - read_crossbar__recv__msg[3'(i)] = rd_pkt[3'(i)]; - recv_raddr__rdy[3'(i)] = read_crossbar__recv__rdy[3'(i)]; - end - read_crossbar__recv__val[3'( __const__num_rd_tiles_at_update_all )] = recv_from_noc_load_request__val; - read_crossbar__recv__msg[3'( __const__num_rd_tiles_at_update_all )] = rd_pkt[3'( __const__num_rd_tiles_at_update_all )]; - recv_from_noc_load_request__rdy = read_crossbar__recv__rdy[3'( __const__num_rd_tiles_at_update_all )]; - for ( int unsigned i = 1'd0; i < 3'( __const__num_wr_tiles_at_update_all ); i += 1'd1 ) begin - write_crossbar__recv__val[3'(i)] = recv_waddr__val[3'(i)]; - write_crossbar__recv__msg[3'(i)] = wr_pkt[3'(i)]; - recv_waddr__rdy[3'(i)] = write_crossbar__recv__rdy[3'(i)]; - recv_wdata__rdy[3'(i)] = write_crossbar__recv__rdy[3'(i)]; - end - write_crossbar__recv__val[3'( __const__num_wr_tiles_at_update_all )] = recv_from_noc_store_request__val; - write_crossbar__recv__msg[3'( __const__num_wr_tiles_at_update_all )] = wr_pkt[3'( __const__num_wr_tiles_at_update_all )]; - recv_from_noc_store_request__rdy = write_crossbar__recv__rdy[3'( __const__num_wr_tiles_at_update_all )]; - for ( int unsigned i = 1'd0; i < 4'( __const__num_xbar_in_rd_ports_at_update_all ); i += 1'd1 ) - if ( 3'(i) < 3'( __const__num_rd_tiles_at_update_all ) ) begin - send_rdata__msg[3'( 3'(i) )] = response_crossbar__send__msg[3'(i)].data; - send_rdata__val[3'( 3'(i) )] = response_crossbar__send__val[3'(i)]; - response_crossbar__send__rdy[3'(i)] = send_rdata__rdy[3'( 3'(i) )]; - end - else begin - __tmpvar__update_all_from_cgra_id = response_crossbar__send__msg[3'(i)].src_cgra; - __tmpvar__update_all_from_tile_id = response_crossbar__send__msg[3'(i)].src_tile; - send_to_noc_load_response_pkt__msg = { cgra_id, __tmpvar__update_all_from_cgra_id, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], idTo2d_x_lut[__tmpvar__update_all_from_cgra_id], idTo2d_y_lut[__tmpvar__update_all_from_cgra_id], 5'd0, __tmpvar__update_all_from_tile_id, response_crossbar__send__msg[3'(i)].remote_src_port, 8'd0, 2'd0, { 5'( __const__CMD_LOAD_RESPONSE ), response_crossbar__send__msg[3'(i)].data, response_crossbar__send__msg[3'(i)].addr, 107'd0, 4'd0 } }; - send_to_noc_load_response_pkt__val = response_crossbar__send__val[3'(i)]; - response_crossbar__send__rdy[3'(i)] = send_to_noc_load_response_pkt__rdy; - end - send_to_noc_load_request_pkt__msg = { cgra_id, 2'd0, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], 1'd0, 1'd0, 5'd0, 5'd0, read_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].src, 8'd0, 2'd0, { 5'( __const__CMD_LOAD_REQUEST ), 67'd0, read_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].addr, 107'd0, 4'd0 } }; - send_to_noc_load_request_pkt__val = read_crossbar__send__val[2'( __const__num_banks_per_cgra_at_update_all )]; - recv_from_noc_load_response_pkt__rdy = response_crossbar__recv__rdy[2'( __const__num_banks_per_cgra_at_update_all )]; - response_crossbar__recv__val[2'( __const__num_banks_per_cgra_at_update_all )] = recv_from_noc_load_response_pkt__val; - response_crossbar__recv__msg[2'( __const__num_banks_per_cgra_at_update_all )] = { 2'( __const__num_banks_per_cgra_at_update_all ), recv_from_noc_load_response_pkt__msg.remote_src_port, recv_from_noc_load_response_pkt__msg.payload.data_addr, recv_from_noc_load_response_pkt__msg.payload.data, recv_from_noc_load_response_pkt__msg.src, recv_from_noc_load_response_pkt__msg.src_tile_id, 3'd0, 1'd0, 7'd0, 7'd0 }; - read_crossbar__send__rdy[2'( __const__num_banks_per_cgra_at_update_all )] = send_to_noc_load_request_pkt__rdy; - send_to_noc_store_pkt__msg = { cgra_id, 2'd0, idTo2d_x_lut[cgra_id], idTo2d_y_lut[cgra_id], 1'd0, 1'd0, 5'd0, 5'd0, write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].src, 8'd0, 2'd0, { 5'( __const__CMD_STORE_REQUEST ), write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].data, write_crossbar__send__msg[2'( __const__num_banks_per_cgra_at_update_all )].addr, 107'd0, 4'd0 } }; - send_to_noc_store_pkt__val = write_crossbar__send__val[2'( __const__num_banks_per_cgra_at_update_all )]; - write_crossbar__send__rdy[2'( __const__num_banks_per_cgra_at_update_all )] = send_to_noc_store_pkt__rdy; - end - - assign memory_wrapper__clk[0] = clk; - assign memory_wrapper__reset[0] = reset; - assign memory_wrapper__clk[1] = clk; - assign memory_wrapper__reset[1] = reset; - assign read_crossbar__clk = clk; - assign read_crossbar__reset = reset; - assign write_crossbar__clk = clk; - assign write_crossbar__reset = reset; - assign response_crossbar__clk = clk; - assign response_crossbar__reset = reset; - assign idTo2d_x_lut[0] = 1'd0; - assign idTo2d_y_lut[0] = 1'd0; - assign idTo2d_x_lut[1] = 1'd1; - assign idTo2d_y_lut[1] = 1'd0; - assign idTo2d_x_lut[2] = 1'd0; - assign idTo2d_y_lut[2] = 1'd1; - assign idTo2d_x_lut[3] = 1'd1; - assign idTo2d_y_lut[3] = 1'd1; - assign memory_wrapper__recv_rd__msg[0] = read_crossbar__send__msg[0]; - assign read_crossbar__send__rdy[0] = memory_wrapper__recv_rd__rdy[0]; - assign memory_wrapper__recv_rd__val[0] = read_crossbar__send__val[0]; - assign memory_wrapper__recv_wr__msg[0] = write_crossbar__send__msg[0]; - assign write_crossbar__send__rdy[0] = memory_wrapper__recv_wr__rdy[0]; - assign memory_wrapper__recv_wr__val[0] = write_crossbar__send__val[0]; - assign response_crossbar__recv__msg[0] = memory_wrapper__send__msg[0]; - assign memory_wrapper__send__rdy[0] = response_crossbar__recv__rdy[0]; - assign response_crossbar__recv__val[0] = memory_wrapper__send__val[0]; - assign memory_wrapper__recv_rd__msg[1] = read_crossbar__send__msg[1]; - assign read_crossbar__send__rdy[1] = memory_wrapper__recv_rd__rdy[1]; - assign memory_wrapper__recv_rd__val[1] = read_crossbar__send__val[1]; - assign memory_wrapper__recv_wr__msg[1] = write_crossbar__send__msg[1]; - assign write_crossbar__send__rdy[1] = memory_wrapper__recv_wr__rdy[1]; - assign memory_wrapper__recv_wr__val[1] = write_crossbar__send__val[1]; - assign response_crossbar__recv__msg[1] = memory_wrapper__send__msg[1]; - assign memory_wrapper__send__rdy[1] = response_crossbar__recv__rdy[1]; - assign response_crossbar__recv__val[1] = memory_wrapper__send__val[1]; - -endmodule - - -// PyMTL Component ConstQueueDynamicRTL Definition -// Full name: ConstQueueDynamicRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__const_mem_size_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py - -module ConstQueueDynamicRTL__9d3397f72f19af52 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] ctrl_proceed , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_const__msg , - input logic [0:0] send_const__rdy , - output logic [0:0] send_const__val -); - localparam logic [4:0] __const__const_mem_size_at_load_const = 5'd16; - localparam logic [4:0] __const__const_mem_size_at_update_wr_cur = 5'd16; - logic [3:0] rd_cur; - logic [4:0] wr_cur; - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__bd22936ec5812d0d reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [0:0] __tmpvar__load_const_not_full; - logic [0:0] __tmpvar__update_wr_cur_not_full; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:56 - // @update - // def load_const(): - // # Initializes signals. - // s.reg_file.waddr[0] @= AddrType() - // s.reg_file.wdata[0] @= DataType() - // s.reg_file.wen[0] @= 0 - // - // not_full = s.wr_cur < const_mem_size - // s.recv_const.rdy @= not_full - // - // if s.recv_const.val & not_full: - // s.reg_file.waddr[0] @= trunc(s.wr_cur, AddrType) - // s.reg_file.wdata[0] @= s.recv_const.msg - // s.reg_file.wen[0] @= 1 - - always_comb begin : load_const - reg_file__waddr[1'd0] = 4'd0; - reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__wen[1'd0] = 1'd0; - __tmpvar__load_const_not_full = wr_cur < 5'( __const__const_mem_size_at_load_const ); - recv_const__rdy = __tmpvar__load_const_not_full; - if ( recv_const__val & __tmpvar__load_const_not_full ) begin - reg_file__waddr[1'd0] = 4'(wr_cur); - reg_file__wdata[1'd0] = recv_const__msg; - reg_file__wen[1'd0] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:83 - // @update - // def update_send_val(): - // # Checks if read cursor is in front of write cursor. - // if (zext(s.rd_cur, WrCurType) < s.wr_cur): - // s.send_const.val @= 1 - // else: - // s.send_const.val @= 0 - - always_comb begin : update_send_val - if ( { { 1 { 1'b0 } }, rd_cur } < wr_cur ) begin - send_const__val = 1'd1; - end - else - send_const__val = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:92 - // @update_ff - // def update_rd_cur(): - // if s.reset | s.clear: - // s.rd_cur <<= 0 - // else: - // # Checks whether the "reader" successfully read the data at rd_cur, - // # and proceed rd_cur accordingly. - // if s.send_const.rdy & s.ctrl_proceed: - // if zext((s.rd_cur), WrCurType) < (s.wr_cur - 1): - // s.rd_cur <<= s.rd_cur + 1 - // else: - // s.rd_cur <<= 0 - - always_ff @(posedge clk) begin : update_rd_cur - if ( reset | clear ) begin - rd_cur <= 4'd0; - end - else if ( send_const__rdy & ctrl_proceed ) begin - if ( { { 1 { 1'b0 } }, rd_cur } < ( wr_cur - 5'd1 ) ) begin - rd_cur <= rd_cur + 4'd1; - end - else - rd_cur <= 4'd0; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/const/ConstQueueDynamicRTL.py:72 - // @update_ff - // def update_wr_cur(): - // not_full = (s.wr_cur < const_mem_size) - // if s.reset | s.clear: - // s.wr_cur <<= 0 - // # Checks if there's a valid const (from producer) to be written. - // else: - // if s.recv_const.val & not_full: - // s.wr_cur <<= s.wr_cur + 1 - - always_ff @(posedge clk) begin : update_wr_cur - __tmpvar__update_wr_cur_not_full = wr_cur < 5'( __const__const_mem_size_at_update_wr_cur ); - if ( reset | clear ) begin - wr_cur <= 5'd0; - end - else if ( recv_const__val & __tmpvar__update_wr_cur_not_full ) begin - wr_cur <= wr_cur + 5'd1; - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - assign send_const__msg = reg_file__rdata[0]; - assign reg_file__raddr[0] = rd_cur; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__736a0143e1873b49 -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__66f570731410737c -( - input logic [0:0] clk , - input logic [0:0] raddr , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_msg , - input logic [0:0] reset , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__736a0143e1873b49 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__66f570731410737c -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__raddr; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a dpath__recv_msg; - logic [0:0] dpath__reset; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__66f570731410737c dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__nregs_16__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__46d8b36a7a21259f -( - input logic [0:0] clk , - input logic [3:0] raddr [0:0], - output CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 rdata [0:0], - input logic [0:0] reset , - input logic [3:0] waddr [0:0], - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 regs [0:15]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component CtrlMemDynamicRTL Definition -// Full name: CtrlMemDynamicRTL__IntraCgraPktType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ctrl_mem_size_16__num_fu_inports_4__num_fu_outports_2__num_tile_inports_4__num_tile_outports_4__num_cgras_4__num_tiles_16__ctrl_count_per_iter_4__total_ctrl_steps_38 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py - -module CtrlMemDynamicRTL__427d547b7d58aa8e -( - input logic [1:0] cgra_id , - input logic [0:0] clk , - output logic [3:0] ctrl_addr_outport , - output logic [2:0] prologue_count_outport_fu , - output logic [2:0] prologue_count_outport_fu_crossbar [0:15][0:1], - output logic [2:0] prologue_count_outport_routing_crossbar [0:15][0:3], - input logic [0:0] reset , - input logic [4:0] tile_id , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element__msg , - output logic [0:0] recv_from_element__rdy , - input logic [0:0] recv_from_element__val , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller__msg , - output logic [0:0] recv_pkt_from_controller__rdy , - input logic [0:0] recv_pkt_from_controller__val , - output CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 send_ctrl__msg , - input logic [0:0] send_ctrl__rdy , - output logic [0:0] send_ctrl__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_pkt_to_controller__msg , - input logic [0:0] send_pkt_to_controller__rdy , - output logic [0:0] send_pkt_to_controller__val , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_element__msg , - input logic [0:0] send_to_element__rdy , - output logic [0:0] send_to_element__val -); - localparam logic [2:0] __const__num_fu_inports_at_update_msg = 3'd4; - localparam logic [3:0] __const__num_routing_outports_at_update_msg = 4'd8; - localparam logic [1:0] __const__CMD_CONFIG = 2'd3; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; - localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; - localparam logic [1:0] __const__CMD_TERMINATE = 2'd2; - localparam logic [0:0] __const__CMD_PAUSE = 1'd1; - localparam logic [4:0] __const__CMD_PRESERVE = 5'd22; - localparam logic [3:0] __const__CMD_RESUME = 4'd15; - localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; - localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; - localparam logic [3:0] __const__CMD_CONFIG_CTRL_LOWER_BOUND = 4'd9; - localparam logic [4:0] __const__CMD_RECORD_PHI_ADDR = 5'd16; - localparam logic [4:0] __const__num_tiles_at_update_send_pkt_to_controller = 5'd16; - localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [4:0] __const__ctrl_mem_size_at_update_raddr_and_fu_prologue = 5'd16; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_outport = 5'd16; - localparam logic [2:0] __const__num_tile_inports_at_update_prologue_outport = 3'd4; - localparam logic [1:0] __const__num_fu_outports_at_update_prologue_outport = 2'd2; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_reg = 5'd16; - localparam logic [2:0] __const__num_tile_inports_at_update_prologue_reg = 3'd4; - localparam logic [1:0] __const__num_fu_outports_at_update_prologue_reg = 2'd2; - localparam logic [2:0] __const__ctrl_count_per_iter_at_update_ctrl_count_per_iter = 3'd4; - localparam logic [5:0] __const__total_ctrl_steps_at_update_total_ctrl_steps = 6'd38; - logic [3:0] ctrl_count_lower_bound; - logic [2:0] ctrl_count_per_iter_val; - logic [4:0] ctrl_count_upper_bound; - logic [2:0] prologue_count_reg_fu [0:15]; - logic [2:0] prologue_count_reg_fu_crossbar [0:15][0:1]; - logic [2:0] prologue_count_reg_routing_crossbar [0:15][0:3]; - logic [0:0] sent_complete; - logic [0:0] start_iterate_ctrl; - logic [10:0] times; - logic [10:0] total_ctrl_steps_val; - //------------------------------------------------------------- - // Component recv_from_element_queue - //------------------------------------------------------------- - - logic [0:0] recv_from_element_queue__clk; - logic [1:0] recv_from_element_queue__count; - logic [0:0] recv_from_element_queue__reset; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element_queue__recv__msg; - logic [0:0] recv_from_element_queue__recv__rdy; - logic [0:0] recv_from_element_queue__recv__val; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_element_queue__send__msg; - logic [0:0] recv_from_element_queue__send__rdy; - logic [0:0] recv_from_element_queue__send__val; - - NormalQueueRTL__66f570731410737c recv_from_element_queue - ( - .clk( recv_from_element_queue__clk ), - .count( recv_from_element_queue__count ), - .reset( recv_from_element_queue__reset ), - .recv__msg( recv_from_element_queue__recv__msg ), - .recv__rdy( recv_from_element_queue__recv__rdy ), - .recv__val( recv_from_element_queue__recv__val ), - .send__msg( recv_from_element_queue__send__msg ), - .send__rdy( recv_from_element_queue__send__rdy ), - .send__val( recv_from_element_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_from_element_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component recv_pkt_from_controller_queue - //------------------------------------------------------------- - - logic [0:0] recv_pkt_from_controller_queue__clk; - logic [1:0] recv_pkt_from_controller_queue__count; - logic [0:0] recv_pkt_from_controller_queue__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller_queue__recv__msg; - logic [0:0] recv_pkt_from_controller_queue__recv__rdy; - logic [0:0] recv_pkt_from_controller_queue__recv__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_pkt_from_controller_queue__send__msg; - logic [0:0] recv_pkt_from_controller_queue__send__rdy; - logic [0:0] recv_pkt_from_controller_queue__send__val; - - NormalQueueRTL__a1c7a5a18a302c36 recv_pkt_from_controller_queue - ( - .clk( recv_pkt_from_controller_queue__clk ), - .count( recv_pkt_from_controller_queue__count ), - .reset( recv_pkt_from_controller_queue__reset ), - .recv__msg( recv_pkt_from_controller_queue__recv__msg ), - .recv__rdy( recv_pkt_from_controller_queue__recv__rdy ), - .recv__val( recv_pkt_from_controller_queue__recv__val ), - .send__msg( recv_pkt_from_controller_queue__send__msg ), - .send__rdy( recv_pkt_from_controller_queue__send__rdy ), - .send__val( recv_pkt_from_controller_queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component recv_pkt_from_controller_queue - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__46d8b36a7a21259f reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [2:0] __tmpvar__update_prologue_reg_temp_routing_crossbar_in; - logic [1:0] __tmpvar__update_prologue_reg_temp_fu_crossbar_in; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:157 - // @update - // def update_ctrl_addr_outport(): - // s.ctrl_addr_outport @= s.reg_file.raddr[0] - - always_comb begin : update_ctrl_addr_outport - ctrl_addr_outport = reg_file__raddr[1'd0]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:94 - // @update - // def update_msg(): - // s.recv_pkt_from_controller_queue.send.rdy @= 0 - // s.send_to_element.msg @= CgraPayloadType(0, 0, 0, 0, 0) - // s.send_to_element.val @= 0 - // s.reg_file.wen[0] @= 0 - // s.reg_file.waddr[0] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr - // # Initializes the fields of the control signal. - // s.reg_file.wdata[0].operation @= 0 - // for i in range(num_fu_inports): - // s.reg_file.wdata[0].fu_in[i] @= 0 - // s.reg_file.wdata[0].write_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_from[i] - // s.reg_file.wdata[0].write_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_idx[i] - // s.reg_file.wdata[0].read_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_from[i] - // s.reg_file.wdata[0].read_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_idx[i] - // for i in range(num_routing_outports): - // s.reg_file.wdata[0].routing_xbar_outport[i] @= 0 - // s.reg_file.wdata[0].fu_xbar_outport[i] @= 0 - // s.reg_file.wdata[0].vector_factor_power @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.vector_factor_power - // s.reg_file.wdata[0].is_last_ctrl @= 0 - // - // if s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG): - // s.reg_file.wen[0] @= 1 - // s.reg_file.waddr[0] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr - // # Fills the fields of the control signal. - // s.reg_file.wdata[0].operation @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.operation - // for i in range(num_fu_inports): - // s.reg_file.wdata[0].fu_in[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_in[i] - // s.reg_file.wdata[0].write_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_from[i] - // s.reg_file.wdata[0].write_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.write_reg_idx[i] - // s.reg_file.wdata[0].read_reg_from[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_from[i] - // s.reg_file.wdata[0].read_reg_idx[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.read_reg_idx[i] - // for i in range(num_routing_outports): - // s.reg_file.wdata[0].routing_xbar_outport[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.routing_xbar_outport[i] - // s.reg_file.wdata[0].fu_xbar_outport[i] @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_xbar_outport[i] - // s.reg_file.wdata[0].vector_factor_power @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.vector_factor_power - // s.reg_file.wdata[0].is_last_ctrl @= s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.is_last_ctrl - // elif s.recv_pkt_from_controller_queue.send.val & \ - // ((s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE)): - // s.send_to_element.msg @= s.recv_pkt_from_controller_queue.send.msg.payload - // s.send_to_element.val @= 1 - // - // if (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_PAUSE) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_PRESERVE) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RECORD_PHI_ADDR) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE): - // s.recv_pkt_from_controller_queue.send.rdy @= 1 - // # TODO: Extend for the other commands. Maybe another queue to - // # handle complicated actions. - // # else: - - always_comb begin : update_msg - recv_pkt_from_controller_queue__send__rdy = 1'd0; - send_to_element__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - send_to_element__val = 1'd0; - reg_file__wen[1'd0] = 1'd0; - reg_file__waddr[1'd0] = recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr; - reg_file__wdata[1'd0].operation = 7'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_fu_inports_at_update_msg ); i += 1'd1 ) begin - reg_file__wdata[1'd0].fu_in[2'(i)] = 3'd0; - reg_file__wdata[1'd0].write_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_from[2'(i)]; - reg_file__wdata[1'd0].write_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_idx[2'(i)]; - reg_file__wdata[1'd0].read_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_from[2'(i)]; - reg_file__wdata[1'd0].read_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_idx[2'(i)]; - end - for ( int unsigned i = 1'd0; i < 4'( __const__num_routing_outports_at_update_msg ); i += 1'd1 ) begin - reg_file__wdata[1'd0].routing_xbar_outport[3'(i)] = 3'd0; - reg_file__wdata[1'd0].fu_xbar_outport[3'(i)] = 2'd0; - end - reg_file__wdata[1'd0].vector_factor_power = recv_pkt_from_controller_queue__send__msg.payload.ctrl.vector_factor_power; - reg_file__wdata[1'd0].is_last_ctrl = 1'd0; - if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) ) begin - reg_file__wen[1'd0] = 1'd1; - reg_file__waddr[1'd0] = recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr; - reg_file__wdata[1'd0].operation = recv_pkt_from_controller_queue__send__msg.payload.ctrl.operation; - for ( int unsigned i = 1'd0; i < 3'( __const__num_fu_inports_at_update_msg ); i += 1'd1 ) begin - reg_file__wdata[1'd0].fu_in[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_in[2'(i)]; - reg_file__wdata[1'd0].write_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_from[2'(i)]; - reg_file__wdata[1'd0].write_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.write_reg_idx[2'(i)]; - reg_file__wdata[1'd0].read_reg_from[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_from[2'(i)]; - reg_file__wdata[1'd0].read_reg_idx[2'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.read_reg_idx[2'(i)]; - end - for ( int unsigned i = 1'd0; i < 4'( __const__num_routing_outports_at_update_msg ); i += 1'd1 ) begin - reg_file__wdata[1'd0].routing_xbar_outport[3'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.routing_xbar_outport[3'(i)]; - reg_file__wdata[1'd0].fu_xbar_outport[3'(i)] = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_xbar_outport[3'(i)]; - end - reg_file__wdata[1'd0].vector_factor_power = recv_pkt_from_controller_queue__send__msg.payload.ctrl.vector_factor_power; - reg_file__wdata[1'd0].is_last_ctrl = recv_pkt_from_controller_queue__send__msg.payload.ctrl.is_last_ctrl; - end - else if ( recv_pkt_from_controller_queue__send__val & ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) ) begin - send_to_element__msg = recv_pkt_from_controller_queue__send__msg.payload; - send_to_element__val = 1'd1; - end - if ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_PAUSE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_PRESERVE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RECORD_PHI_ADDR ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) begin - recv_pkt_from_controller_queue__send__rdy = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:255 - // @update - // def update_prologue_outport(): - // s.prologue_count_outport_fu @= s.prologue_count_reg_fu[s.reg_file.raddr[0]] - // for addr in range(ctrl_mem_size): - // for i in range(num_tile_inports): - // s.prologue_count_outport_routing_crossbar[addr][i] @= \ - // s.prologue_count_reg_routing_crossbar[addr][i] - // for i in range(num_fu_outports): - // s.prologue_count_outport_fu_crossbar[addr][i] @= \ - // s.prologue_count_reg_fu_crossbar[addr][i] - - always_comb begin : update_prologue_outport - prologue_count_outport_fu = prologue_count_reg_fu[reg_file__raddr[1'd0]]; - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_outport ); addr += 1'd1 ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_tile_inports_at_update_prologue_outport ); i += 1'd1 ) - prologue_count_outport_routing_crossbar[4'(addr)][2'(i)] = prologue_count_reg_routing_crossbar[4'(addr)][2'(i)]; - for ( int unsigned i = 1'd0; i < 2'( __const__num_fu_outports_at_update_prologue_outport ); i += 1'd1 ) - prologue_count_outport_fu_crossbar[4'(addr)][1'(i)] = prologue_count_reg_fu_crossbar[4'(addr)][1'(i)]; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:181 - // @update - // def update_send_ctrl(): - // s.send_ctrl.val @= 0 - // if s.start_iterate_ctrl == b1(1): - // if s.sent_complete: - // s.send_ctrl.val @= 0 - // elif ((s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val)) | \ - // (s.reg_file.rdata[0].operation == OPT_START): - // s.send_ctrl.val @= b1(0) - // else: - // s.send_ctrl.val @= 1 - // if s.recv_pkt_from_controller_queue.send.val & \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE): - // s.send_ctrl.val @= b1(0) - - always_comb begin : update_send_ctrl - send_ctrl__val = 1'd0; - if ( start_iterate_ctrl == 1'd1 ) begin - if ( sent_complete ) begin - send_ctrl__val = 1'd0; - end - else if ( ( ( total_ctrl_steps_val > 11'd0 ) & ( times == total_ctrl_steps_val ) ) | ( reg_file__rdata[1'd0].operation == 7'( __const__OPT_START ) ) ) begin - send_ctrl__val = 1'd0; - end - else - send_ctrl__val = 1'd1; - end - if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) begin - send_ctrl__val = 1'd0; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:161 - // @update - // def update_send_pkt_to_controller(): - // s.send_pkt_to_controller.val @= 0 - // s.send_pkt_to_controller.msg @= IntraCgraPktType(0, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, CgraPayloadType(CMD_COMPLETE, 0, 0, 0, 0)) - // s.recv_from_element_queue.send.rdy @= 0 - // if s.start_iterate_ctrl == b1(1): - // if s.recv_from_element_queue.send.val & (~s.sent_complete): - // s.send_pkt_to_controller.msg @= \ - // IntraCgraPktType(s.tile_id, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, - // s.recv_from_element_queue.send.msg) - // s.send_pkt_to_controller.val @= 1 - // s.recv_from_element_queue.send.rdy @= s.send_pkt_to_controller.rdy - // elif ((s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val)) | \ - // (s.reg_file.rdata[0].operation == OPT_START): - // # Sends COMPLETE signal to Controller when the last ctrl signal is done. - // if ~s.sent_complete & (s.total_ctrl_steps_val > 0) & (s.times == s.total_ctrl_steps_val) & s.start_iterate_ctrl: - // s.send_pkt_to_controller.msg @= \ - // IntraCgraPktType(s.tile_id, num_tiles, 0, 0, 0, 0, 0, 0, 0, 0, CgraPayloadType(CMD_COMPLETE, 0, 0, 0, 0)) - // s.send_pkt_to_controller.val @= 1 - - always_comb begin : update_send_pkt_to_controller - send_pkt_to_controller__val = 1'd0; - send_pkt_to_controller__msg = { 5'd0, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'( __const__CMD_COMPLETE ), 67'd0, 7'd0, 107'd0, 4'd0 } }; - recv_from_element_queue__send__rdy = 1'd0; - if ( start_iterate_ctrl == 1'd1 ) begin - if ( recv_from_element_queue__send__val & ( ~sent_complete ) ) begin - send_pkt_to_controller__msg = { tile_id, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, recv_from_element_queue__send__msg }; - send_pkt_to_controller__val = 1'd1; - recv_from_element_queue__send__rdy = send_pkt_to_controller__rdy; - end - else if ( ( ( total_ctrl_steps_val > 11'd0 ) & ( times == total_ctrl_steps_val ) ) | ( reg_file__rdata[1'd0].operation == 7'( __const__OPT_START ) ) ) begin - if ( ( ( ( ~sent_complete ) & ( total_ctrl_steps_val > 11'd0 ) ) & ( times == total_ctrl_steps_val ) ) & start_iterate_ctrl ) begin - send_pkt_to_controller__msg = { tile_id, 5'( __const__num_tiles_at_update_send_pkt_to_controller ), 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'( __const__CMD_COMPLETE ), 67'd0, 7'd0, 107'd0, 4'd0 } }; - send_pkt_to_controller__val = 1'd1; - end - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:298 - // @update - // def update_upper_bound(): - // s.ctrl_count_upper_bound @= zext(s.ctrl_count_lower_bound, UpperBoundType) + zext(s.ctrl_count_per_iter_val, UpperBoundType) - - always_comb begin : update_upper_bound - ctrl_count_upper_bound = { { 1 { 1'b0 } }, ctrl_count_lower_bound } + { { 2 { 1'b0 } }, ctrl_count_per_iter_val }; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:210 - // @update_ff - // def issue_complete(): - // if s.reset: - // s.sent_complete <<= 0 - // else: - // if s.send_pkt_to_controller.val & \ - // s.send_pkt_to_controller.rdy & \ - // (s.send_pkt_to_controller.msg.payload.cmd == CMD_COMPLETE): - // s.sent_complete <<= 1 - // elif s.recv_pkt_from_controller_queue.send.val & ( (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME) ): - // s.sent_complete <<= 0 - - always_ff @(posedge clk) begin : issue_complete - if ( reset ) begin - sent_complete <= 1'd0; - end - else if ( ( send_pkt_to_controller__val & send_pkt_to_controller__rdy ) & ( send_pkt_to_controller__msg.payload.cmd == 5'( __const__CMD_COMPLETE ) ) ) begin - sent_complete <= 1'd1; - end - else if ( recv_pkt_from_controller_queue__send__val & ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) ) begin - sent_complete <= 1'd0; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:284 - // @update_ff - // def update_ctrl_count_per_iter(): - // if s.reset: - // s.ctrl_count_per_iter_val <<= PCType(ctrl_count_per_iter) - // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER): - // s.ctrl_count_per_iter_val <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PCType) - - always_ff @(posedge clk) begin : update_ctrl_count_per_iter - if ( reset ) begin - ctrl_count_per_iter_val <= 3'd4; - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) begin - ctrl_count_per_iter_val <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:291 - // @update_ff - // def update_lower_bound(): - // if s.reset: - // s.ctrl_count_lower_bound <<= CtrlAddrType(0) - // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND): - // s.ctrl_count_lower_bound <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, CtrlAddrType) - - always_ff @(posedge clk) begin : update_lower_bound - if ( reset ) begin - ctrl_count_lower_bound <= 4'd0; - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) begin - ctrl_count_lower_bound <= 4'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:266 - // @update_ff - // def update_prologue_reg(): - // if s.reset: - // for addr in range(ctrl_mem_size): - // for i in range(num_tile_inports): - // s.prologue_count_reg_routing_crossbar[addr][i] <<= 0 - // for i in range(num_fu_outports): - // s.prologue_count_reg_fu_crossbar[addr][i] <<= 0 - // else: - // if s.recv_pkt_from_controller_queue.send.val & \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR): - // temp_routing_crossbar_in = s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.routing_xbar_outport[0] - // s.prologue_count_reg_routing_crossbar[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr][trunc(temp_routing_crossbar_in, TileInPortType)] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) - // elif s.recv_pkt_from_controller_queue.send.val & \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR): - // temp_fu_crossbar_in = s.recv_pkt_from_controller_queue.send.msg.payload.ctrl.fu_xbar_outport[0] - // s.prologue_count_reg_fu_crossbar[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr][trunc(temp_fu_crossbar_in, FuOutPortType)] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) - - always_ff @(posedge clk) begin : update_prologue_reg - if ( reset ) begin - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_reg ); addr += 1'd1 ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_tile_inports_at_update_prologue_reg ); i += 1'd1 ) - prologue_count_reg_routing_crossbar[4'(addr)][2'(i)] <= 3'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_fu_outports_at_update_prologue_reg ); i += 1'd1 ) - prologue_count_reg_fu_crossbar[4'(addr)][1'(i)] <= 3'd0; - end - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) begin - __tmpvar__update_prologue_reg_temp_routing_crossbar_in = recv_pkt_from_controller_queue__send__msg.payload.ctrl.routing_xbar_outport[3'd0]; - prologue_count_reg_routing_crossbar[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr][2'(__tmpvar__update_prologue_reg_temp_routing_crossbar_in)] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) begin - __tmpvar__update_prologue_reg_temp_fu_crossbar_in = recv_pkt_from_controller_queue__send__msg.payload.ctrl.fu_xbar_outport[3'd0]; - prologue_count_reg_fu_crossbar[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr][1'(__tmpvar__update_prologue_reg_temp_fu_crossbar_in)] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:223 - // @update_ff - // def update_raddr_and_fu_prologue(): - // if s.reset: - // s.times <<= 0 - // s.reg_file.raddr[0] <<= 0 - // for i in range(ctrl_mem_size): - // s.prologue_count_reg_fu[i] <<= 0 - // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_CTRL_LOWER_BOUND): - // s.reg_file.raddr[0] <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, CtrlAddrType) - // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE): - // s.times <<= TimeType(0) - // else: - // if s.recv_pkt_from_controller_queue.send.val & \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU): - // s.prologue_count_reg_fu[s.recv_pkt_from_controller_queue.send.msg.payload.ctrl_addr] <<= \ - // trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, PrologueCountType) - // - // if s.start_iterate_ctrl == b1(1): - // if ((s.total_ctrl_steps_val == 0) | \ - // (s.times < s.total_ctrl_steps_val)) & \ - // s.send_ctrl.rdy & s.send_ctrl.val: - // s.times <<= s.times + TimeType(1) - // - // # Reads the next ctrl signal only when the current one is done. - // if s.send_ctrl.rdy & s.send_ctrl.val: - // if zext(s.reg_file.raddr[0], UpperBoundType) == s.ctrl_count_upper_bound - UpperBoundType(1): - // s.reg_file.raddr[0] <<= s.ctrl_count_lower_bound - // else: - // s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + CtrlAddrType(1) - // if s.prologue_count_reg_fu[s.reg_file.raddr[0]] > 0: - // s.prologue_count_reg_fu[s.reg_file.raddr[0]] <<= s.prologue_count_reg_fu[s.reg_file.raddr[0]] - 1 - - always_ff @(posedge clk) begin : update_raddr_and_fu_prologue - if ( reset ) begin - times <= 11'd0; - reg_file__raddr[1'd0] <= 4'd0; - for ( int unsigned i = 1'd0; i < 5'( __const__ctrl_mem_size_at_update_raddr_and_fu_prologue ); i += 1'd1 ) - prologue_count_reg_fu[4'(i)] <= 3'd0; - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_CTRL_LOWER_BOUND ) ) ) begin - reg_file__raddr[1'd0] <= 4'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) ) begin - times <= 11'd0; - end - else begin - if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) begin - prologue_count_reg_fu[recv_pkt_from_controller_queue__send__msg.payload.ctrl_addr] <= 3'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - if ( start_iterate_ctrl == 1'd1 ) begin - if ( ( ( ( total_ctrl_steps_val == 11'd0 ) | ( times < total_ctrl_steps_val ) ) & send_ctrl__rdy ) & send_ctrl__val ) begin - times <= times + 11'd1; - end - if ( send_ctrl__rdy & send_ctrl__val ) begin - if ( { { 1 { 1'b0 } }, reg_file__raddr[1'd0] } == ( ctrl_count_upper_bound - 5'd1 ) ) begin - reg_file__raddr[1'd0] <= ctrl_count_lower_bound; - end - else - reg_file__raddr[1'd0] <= reg_file__raddr[1'd0] + 4'd1; - if ( prologue_count_reg_fu[reg_file__raddr[1'd0]] > 3'd0 ) begin - prologue_count_reg_fu[reg_file__raddr[1'd0]] <= prologue_count_reg_fu[reg_file__raddr[1'd0]] - 3'd1; - end - end - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:302 - // @update_ff - // def update_total_ctrl_steps(): - // if s.reset: - // s.total_ctrl_steps_val <<= TimeType(total_ctrl_steps) - // elif s.recv_pkt_from_controller_queue.send.val & (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT): - // s.total_ctrl_steps_val <<= trunc(s.recv_pkt_from_controller_queue.send.msg.payload.data.payload, TimeType) - - always_ff @(posedge clk) begin : update_total_ctrl_steps - if ( reset ) begin - total_ctrl_steps_val <= 11'd38; - end - else if ( recv_pkt_from_controller_queue__send__val & ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) begin - total_ctrl_steps_val <= 11'(recv_pkt_from_controller_queue__send__msg.payload.data.payload); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/ctrl/CtrlMemDynamicRTL.py:196 - // @update_ff - // def update_whether_we_can_iterate_ctrl(): - // if s.reset: - // s.start_iterate_ctrl <<= 0 - // else: - // if s.recv_pkt_from_controller_queue.send.val: - // if (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_LAUNCH) | \ - // (s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_RESUME): - // s.start_iterate_ctrl <<= 1 - // # TODO: issue #191, stop iterate ctrl after 10 cycels during pausing status, - // # so as to clear channels safely. - // elif s.recv_pkt_from_controller_queue.send.msg.payload.cmd == CMD_TERMINATE: - // s.start_iterate_ctrl <<= 0 - - always_ff @(posedge clk) begin : update_whether_we_can_iterate_ctrl - if ( reset ) begin - start_iterate_ctrl <= 1'd0; - end - else if ( recv_pkt_from_controller_queue__send__val ) begin - if ( ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) | ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_RESUME ) ) ) begin - start_iterate_ctrl <= 1'd1; - end - else if ( recv_pkt_from_controller_queue__send__msg.payload.cmd == 5'( __const__CMD_TERMINATE ) ) begin - start_iterate_ctrl <= 1'd0; - end - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - assign recv_pkt_from_controller_queue__clk = clk; - assign recv_pkt_from_controller_queue__reset = reset; - assign recv_from_element_queue__clk = clk; - assign recv_from_element_queue__reset = reset; - assign send_ctrl__msg = reg_file__rdata[0]; - assign recv_pkt_from_controller_queue__recv__msg = recv_pkt_from_controller__msg; - assign recv_pkt_from_controller__rdy = recv_pkt_from_controller_queue__recv__rdy; - assign recv_pkt_from_controller_queue__recv__val = recv_pkt_from_controller__val; - assign recv_from_element_queue__recv__msg = recv_from_element__msg; - assign recv_from_element__rdy = recv_from_element_queue__recv__rdy; - assign recv_from_element_queue__recv__val = recv_from_element__val; - -endmodule - - -// PyMTL Component AdderRTL Definition -// Full name: AdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py - -module AdderRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_ADD = 7'd2; - localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; - localparam logic [6:0] __const__OPT_INC = 7'd3; - localparam logic [6:0] __const__OPT_SUB = 7'd4; - localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; - localparam logic [6:0] __const__OPT_PAS = 7'd31; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py:45 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // s.in0 @= 0 - // s.in1 @= 0 - // # For pick input register - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // # Though different operations might not need to consume - // # all the operands, as long as the opcode indicating it - // # is an operand, the data would disappear from the register. - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != 0: - // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) - // if s.recv_opt.msg.fu_in[1] != 0: - // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_ADD: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_ADD_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // s.recv_const.rdy @= s.send_out[0].rdy - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_INC: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.const_one.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_PAS: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_const__msg.payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; - recv_const__rdy = send_out__rdy[1'd0]; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + 64'd1; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_const__msg.payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component MulRTL Definition -// Full name: MulRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_32 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py - -module MulRTL__903abe7e5de73fa1 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_MUL = 7'd7; - localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py:44 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != 0: - // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) - // if s.recv_opt.msg.fu_in[1] != 0: - // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_MUL: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_MUL_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_const__msg.payload; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component AdderRTL Definition -// Full name: AdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_32 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py - -module AdderRTL__903abe7e5de73fa1 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_ADD = 7'd2; - localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; - localparam logic [6:0] __const__OPT_INC = 7'd3; - localparam logic [6:0] __const__OPT_SUB = 7'd4; - localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; - localparam logic [6:0] __const__OPT_PAS = 7'd31; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/AdderRTL.py:45 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // s.in0 @= 0 - // s.in1 @= 0 - // # For pick input register - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // # Though different operations might not need to consume - // # all the operands, as long as the opcode indicating it - // # is an operand, the data would disappear from the register. - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != 0: - // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) - // if s.recv_opt.msg.fu_in[1] != 0: - // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_ADD: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_ADD_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // s.recv_const.rdy @= s.send_out[0].rdy - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_INC: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.const_one.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_PAS: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + recv_const__msg.payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; - recv_const__rdy = send_out__rdy[1'd0]; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload + 64'd1; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload - recv_const__msg.payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component SeqMulAdderRTL Definition -// Full name: SeqMulAdderRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/double/SeqMulAdderRTL.py - -module SeqMulAdderRTL__b741248a3a1dca5f -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_MUL_ADD = 7'd18; - localparam logic [6:0] __const__OPT_MUL = 7'd7; - localparam logic [6:0] __const__OPT_ADD = 7'd2; - localparam logic [6:0] __const__OPT_MUL_CONST_ADD = 7'd30; - localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; - localparam logic [6:0] __const__OPT_PAS = 7'd31; - localparam logic [6:0] __const__OPT_MUL_SUB = 7'd19; - localparam logic [6:0] __const__OPT_SUB = 7'd4; - localparam logic [6:0] __const__OPT_START = 7'd0; - //------------------------------------------------------------- - // Component Fu0 - //------------------------------------------------------------- - - logic [0:0] Fu0__clear; - logic [0:0] Fu0__clk; - logic [0:0] Fu0__reset; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__from_mem_rdata__msg; - logic [0:0] Fu0__from_mem_rdata__rdy; - logic [0:0] Fu0__from_mem_rdata__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__recv_const__msg; - logic [0:0] Fu0__recv_const__rdy; - logic [0:0] Fu0__recv_const__val; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu0__recv_from_ctrl_mem__msg; - logic [0:0] Fu0__recv_from_ctrl_mem__rdy; - logic [0:0] Fu0__recv_from_ctrl_mem__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__recv_in__msg [0:3]; - logic [0:0] Fu0__recv_in__rdy [0:3]; - logic [0:0] Fu0__recv_in__val [0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu0__recv_opt__msg; - logic [0:0] Fu0__recv_opt__rdy; - logic [0:0] Fu0__recv_opt__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__send_out__msg [0:1]; - logic [0:0] Fu0__send_out__rdy [0:1]; - logic [0:0] Fu0__send_out__val [0:1]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu0__send_to_ctrl_mem__msg; - logic [0:0] Fu0__send_to_ctrl_mem__rdy; - logic [0:0] Fu0__send_to_ctrl_mem__val; - logic [6:0] Fu0__to_mem_raddr__msg; - logic [0:0] Fu0__to_mem_raddr__rdy; - logic [0:0] Fu0__to_mem_raddr__val; - logic [6:0] Fu0__to_mem_waddr__msg; - logic [0:0] Fu0__to_mem_waddr__rdy; - logic [0:0] Fu0__to_mem_waddr__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu0__to_mem_wdata__msg; - logic [0:0] Fu0__to_mem_wdata__rdy; - logic [0:0] Fu0__to_mem_wdata__val; - - MulRTL__903abe7e5de73fa1 Fu0 - ( - .clear( Fu0__clear ), - .clk( Fu0__clk ), - .reset( Fu0__reset ), - .from_mem_rdata__msg( Fu0__from_mem_rdata__msg ), - .from_mem_rdata__rdy( Fu0__from_mem_rdata__rdy ), - .from_mem_rdata__val( Fu0__from_mem_rdata__val ), - .recv_const__msg( Fu0__recv_const__msg ), - .recv_const__rdy( Fu0__recv_const__rdy ), - .recv_const__val( Fu0__recv_const__val ), - .recv_from_ctrl_mem__msg( Fu0__recv_from_ctrl_mem__msg ), - .recv_from_ctrl_mem__rdy( Fu0__recv_from_ctrl_mem__rdy ), - .recv_from_ctrl_mem__val( Fu0__recv_from_ctrl_mem__val ), - .recv_in__msg( Fu0__recv_in__msg ), - .recv_in__rdy( Fu0__recv_in__rdy ), - .recv_in__val( Fu0__recv_in__val ), - .recv_opt__msg( Fu0__recv_opt__msg ), - .recv_opt__rdy( Fu0__recv_opt__rdy ), - .recv_opt__val( Fu0__recv_opt__val ), - .send_out__msg( Fu0__send_out__msg ), - .send_out__rdy( Fu0__send_out__rdy ), - .send_out__val( Fu0__send_out__val ), - .send_to_ctrl_mem__msg( Fu0__send_to_ctrl_mem__msg ), - .send_to_ctrl_mem__rdy( Fu0__send_to_ctrl_mem__rdy ), - .send_to_ctrl_mem__val( Fu0__send_to_ctrl_mem__val ), - .to_mem_raddr__msg( Fu0__to_mem_raddr__msg ), - .to_mem_raddr__rdy( Fu0__to_mem_raddr__rdy ), - .to_mem_raddr__val( Fu0__to_mem_raddr__val ), - .to_mem_waddr__msg( Fu0__to_mem_waddr__msg ), - .to_mem_waddr__rdy( Fu0__to_mem_waddr__rdy ), - .to_mem_waddr__val( Fu0__to_mem_waddr__val ), - .to_mem_wdata__msg( Fu0__to_mem_wdata__msg ), - .to_mem_wdata__rdy( Fu0__to_mem_wdata__rdy ), - .to_mem_wdata__val( Fu0__to_mem_wdata__val ) - ); - - //------------------------------------------------------------- - // End of component Fu0 - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component Fu1 - //------------------------------------------------------------- - - logic [0:0] Fu1__clear; - logic [0:0] Fu1__clk; - logic [0:0] Fu1__reset; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__from_mem_rdata__msg; - logic [0:0] Fu1__from_mem_rdata__rdy; - logic [0:0] Fu1__from_mem_rdata__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__recv_const__msg; - logic [0:0] Fu1__recv_const__rdy; - logic [0:0] Fu1__recv_const__val; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu1__recv_from_ctrl_mem__msg; - logic [0:0] Fu1__recv_from_ctrl_mem__rdy; - logic [0:0] Fu1__recv_from_ctrl_mem__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__recv_in__msg [0:3]; - logic [0:0] Fu1__recv_in__rdy [0:3]; - logic [0:0] Fu1__recv_in__val [0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu1__recv_opt__msg; - logic [0:0] Fu1__recv_opt__rdy; - logic [0:0] Fu1__recv_opt__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__send_out__msg [0:1]; - logic [0:0] Fu1__send_out__rdy [0:1]; - logic [0:0] Fu1__send_out__val [0:1]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a Fu1__send_to_ctrl_mem__msg; - logic [0:0] Fu1__send_to_ctrl_mem__rdy; - logic [0:0] Fu1__send_to_ctrl_mem__val; - logic [6:0] Fu1__to_mem_raddr__msg; - logic [0:0] Fu1__to_mem_raddr__rdy; - logic [0:0] Fu1__to_mem_raddr__val; - logic [6:0] Fu1__to_mem_waddr__msg; - logic [0:0] Fu1__to_mem_waddr__rdy; - logic [0:0] Fu1__to_mem_waddr__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 Fu1__to_mem_wdata__msg; - logic [0:0] Fu1__to_mem_wdata__rdy; - logic [0:0] Fu1__to_mem_wdata__val; - - AdderRTL__903abe7e5de73fa1 Fu1 - ( - .clear( Fu1__clear ), - .clk( Fu1__clk ), - .reset( Fu1__reset ), - .from_mem_rdata__msg( Fu1__from_mem_rdata__msg ), - .from_mem_rdata__rdy( Fu1__from_mem_rdata__rdy ), - .from_mem_rdata__val( Fu1__from_mem_rdata__val ), - .recv_const__msg( Fu1__recv_const__msg ), - .recv_const__rdy( Fu1__recv_const__rdy ), - .recv_const__val( Fu1__recv_const__val ), - .recv_from_ctrl_mem__msg( Fu1__recv_from_ctrl_mem__msg ), - .recv_from_ctrl_mem__rdy( Fu1__recv_from_ctrl_mem__rdy ), - .recv_from_ctrl_mem__val( Fu1__recv_from_ctrl_mem__val ), - .recv_in__msg( Fu1__recv_in__msg ), - .recv_in__rdy( Fu1__recv_in__rdy ), - .recv_in__val( Fu1__recv_in__val ), - .recv_opt__msg( Fu1__recv_opt__msg ), - .recv_opt__rdy( Fu1__recv_opt__rdy ), - .recv_opt__val( Fu1__recv_opt__val ), - .send_out__msg( Fu1__send_out__msg ), - .send_out__rdy( Fu1__send_out__rdy ), - .send_out__val( Fu1__send_out__val ), - .send_to_ctrl_mem__msg( Fu1__send_to_ctrl_mem__msg ), - .send_to_ctrl_mem__rdy( Fu1__send_to_ctrl_mem__rdy ), - .send_to_ctrl_mem__val( Fu1__send_to_ctrl_mem__val ), - .to_mem_raddr__msg( Fu1__to_mem_raddr__msg ), - .to_mem_raddr__rdy( Fu1__to_mem_raddr__rdy ), - .to_mem_raddr__val( Fu1__to_mem_raddr__val ), - .to_mem_waddr__msg( Fu1__to_mem_waddr__msg ), - .to_mem_waddr__rdy( Fu1__to_mem_waddr__rdy ), - .to_mem_waddr__val( Fu1__to_mem_waddr__val ), - .to_mem_wdata__msg( Fu1__to_mem_wdata__msg ), - .to_mem_wdata__rdy( Fu1__to_mem_wdata__rdy ), - .to_mem_wdata__val( Fu1__to_mem_wdata__val ) - ); - - //------------------------------------------------------------- - // End of component Fu1 - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:90 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= AddrType(0) - // s.to_mem_raddr.msg @= AddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/double/SeqMulAdderRTL.py:32 - // @update - // def update_opt(): - // - // s.Fu0.recv_opt.msg @= s.recv_opt.msg - // s.Fu1.recv_opt.msg @= s.recv_opt.msg - // - // s.Fu0.recv_opt.msg.fu_in[0] @= 1 - // s.Fu0.recv_opt.msg.fu_in[1] @= 2 - // s.Fu1.recv_opt.msg.fu_in[0] @= 1 - // s.Fu1.recv_opt.msg.fu_in[1] @= 2 - // - // if s.recv_opt.msg.operation == OPT_MUL_ADD: - // s.Fu0.recv_opt.msg.operation @= OPT_MUL - // s.Fu1.recv_opt.msg.operation @= OPT_ADD - // elif s.recv_opt.msg.operation == OPT_MUL_CONST_ADD: - // s.Fu0.recv_opt.msg.operation @= OPT_MUL_CONST - // s.Fu1.recv_opt.msg.operation @= OPT_ADD - // elif s.recv_opt.msg.operation == OPT_MUL_CONST: - // s.Fu0.recv_opt.msg.operation @= OPT_MUL_CONST - // s.Fu1.recv_opt.msg.operation @= OPT_PAS - // elif s.recv_opt.msg.operation == OPT_MUL_SUB: - // s.Fu0.recv_opt.msg.operation @= OPT_MUL - // s.Fu1.recv_opt.msg.operation @= OPT_SUB - // else: - // # Indicates no computation should happen no this fused FU. - // # This is necessary to avoid the OPT_MUL_CONST be executed - // # by both Mul and MulAdder. - // s.Fu0.recv_opt.msg.operation @= OPT_START - // s.Fu1.recv_opt.msg.operation @= OPT_START - // - // # TODO: need to handle the other cases - - always_comb begin : update_opt - Fu0__recv_opt__msg = recv_opt__msg; - Fu1__recv_opt__msg = recv_opt__msg; - Fu0__recv_opt__msg.fu_in[2'd0] = 3'd1; - Fu0__recv_opt__msg.fu_in[2'd1] = 3'd2; - Fu1__recv_opt__msg.fu_in[2'd0] = 3'd1; - Fu1__recv_opt__msg.fu_in[2'd1] = 3'd2; - if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_ADD ) ) begin - Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL ); - Fu1__recv_opt__msg.operation = 7'( __const__OPT_ADD ); - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST_ADD ) ) begin - Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL_CONST ); - Fu1__recv_opt__msg.operation = 7'( __const__OPT_ADD ); - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin - Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL_CONST ); - Fu1__recv_opt__msg.operation = 7'( __const__OPT_PAS ); - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_SUB ) ) begin - Fu0__recv_opt__msg.operation = 7'( __const__OPT_MUL ); - Fu1__recv_opt__msg.operation = 7'( __const__OPT_SUB ); - end - else begin - Fu0__recv_opt__msg.operation = 7'( __const__OPT_START ); - Fu1__recv_opt__msg.operation = 7'( __const__OPT_START ); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:100 - // @update - // def update_send_to_controller(): - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - - always_comb begin : update_send_to_controller - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/TwoSeqCombo.py:68 - // @update - // def update_signal(): - // - // s.recv_in[0].rdy @= s.Fu0.recv_in[0].rdy - // s.recv_in[1].rdy @= s.Fu0.recv_in[1].rdy - // s.recv_in[2].rdy @= s.Fu1.recv_in[1].rdy - // - // s.Fu0.recv_in[0].val @= s.recv_in[0].val - // s.Fu0.recv_in[1].val @= s.recv_in[1].val - // s.Fu1.recv_in[0].val @= s.Fu0.send_out[0].val - // s.Fu1.recv_in[1].val @= s.recv_in[2].val - // - // s.Fu0.recv_opt.val @= s.recv_opt.val - // s.Fu1.recv_opt.val @= s.recv_opt.val - // - // s.recv_opt.rdy @= s.Fu0.recv_opt.rdy & s.Fu1.recv_opt.rdy - // - // s.send_out[0].val @= s.Fu1.send_out[0].val - // - // s.Fu0.send_out[0].rdy @= s.Fu1.recv_in[0].rdy - // s.Fu1.send_out[0].rdy @= s.send_out[0].rdy - - always_comb begin : update_signal - recv_in__rdy[2'd0] = Fu0__recv_in__rdy[2'd0]; - recv_in__rdy[2'd1] = Fu0__recv_in__rdy[2'd1]; - recv_in__rdy[2'd2] = Fu1__recv_in__rdy[2'd1]; - Fu0__recv_in__val[2'd0] = recv_in__val[2'd0]; - Fu0__recv_in__val[2'd1] = recv_in__val[2'd1]; - Fu1__recv_in__val[2'd0] = Fu0__send_out__val[1'd0]; - Fu1__recv_in__val[2'd1] = recv_in__val[2'd2]; - Fu0__recv_opt__val = recv_opt__val; - Fu1__recv_opt__val = recv_opt__val; - recv_opt__rdy = Fu0__recv_opt__rdy & Fu1__recv_opt__rdy; - send_out__val[1'd0] = Fu1__send_out__val[1'd0]; - Fu0__send_out__rdy[1'd0] = Fu1__recv_in__rdy[2'd0]; - Fu1__send_out__rdy[1'd0] = send_out__rdy[1'd0]; - end - - assign Fu0__clk = clk; - assign Fu0__reset = reset; - assign Fu1__clk = clk; - assign Fu1__reset = reset; - assign Fu0__recv_in__msg[0] = recv_in__msg[0]; - assign Fu0__recv_in__msg[1] = recv_in__msg[1]; - assign Fu1__recv_in__msg[1] = recv_in__msg[2]; - assign Fu1__recv_in__msg[0] = Fu0__send_out__msg[0]; - assign send_out__msg[0] = Fu1__send_out__msg[0]; - assign Fu0__recv_const__msg = recv_const__msg; - assign recv_const__rdy = Fu0__recv_const__rdy; - assign Fu0__recv_const__val = recv_const__val; - -endmodule - - -// PyMTL Component VectorMulRTL Definition -// Full name: VectorMulRTL__bw_16__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulRTL.py - -module VectorMulRTL__848c3e0c53bb478c -( - input logic [0:0] clk , - input logic [0:0] reset , - input logic [31:0] recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input logic [31:0] recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output logic [31:0] send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] -); - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_MUL = 7'd7; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] recv_all_val; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulRTL.py:55 - // @update - // def comb_logic(): - // s.recv_all_val @= 0 - // # Picks input register. - // s.in0 @= FuInType(0) - // s.in1 @= FuInType(0) - // - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range( num_outports ): - // s.send_out[i].val @= b1(0) - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_MUL: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg * s.recv_in[s.in1_idx].msg - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = 32'd0; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin - send_out__msg[1'd0] = recv_in__msg[in0_idx] * recv_in__msg[in1_idx]; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component VectorMulComboRTL Definition -// Full name: VectorMulComboRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py - -module VectorMulComboRTL__e2d25a29972e2033 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [1:0] __const__num_outports_at_update_input_output = 2'd2; - localparam logic [2:0] __const__num_lanes_at_update_input_output = 3'd4; - localparam logic [4:0] __const__sub_bw_at_update_input_output = 5'd16; - localparam logic [6:0] __const__OPT_VEC_MUL = 7'd55; - localparam logic [5:0] __const__sub_bw_2_at_update_input_output = 6'd32; - localparam logic [5:0] __const__sub_bw_3_at_update_input_output = 6'd48; - localparam logic [6:0] __const__sub_bw_4_at_update_input_output = 7'd64; - localparam logic [6:0] __const__data_bitwidth_at_update_input_output = 7'd64; - localparam logic [6:0] __const__OPT_VEC_MUL_COMBINED = 7'd75; - localparam logic [2:0] __const__num_lanes_at_update_signal = 3'd4; - localparam logic [1:0] __const__num_outports_at_update_signal = 2'd2; - localparam logic [2:0] __const__num_lanes_at_update_opt = 3'd4; - localparam logic [6:0] __const__OPT_NAH = 7'd1; - localparam logic [6:0] __const__OPT_MUL = 7'd7; - logic [63:0] temp_result [0:3]; - //------------------------------------------------------------- - // Component Fu[0:3] - //------------------------------------------------------------- - - logic [0:0] Fu__clk [0:3]; - logic [0:0] Fu__reset [0:3]; - logic [31:0] Fu__recv_const__msg [0:3]; - logic [0:0] Fu__recv_const__rdy [0:3]; - logic [0:0] Fu__recv_const__val [0:3]; - logic [31:0] Fu__recv_in__msg [0:3][0:3]; - logic [0:0] Fu__recv_in__rdy [0:3][0:3]; - logic [0:0] Fu__recv_in__val [0:3][0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu__recv_opt__msg [0:3]; - logic [0:0] Fu__recv_opt__rdy [0:3]; - logic [0:0] Fu__recv_opt__val [0:3]; - logic [31:0] Fu__send_out__msg [0:3][0:1]; - logic [0:0] Fu__send_out__rdy [0:3][0:1]; - logic [0:0] Fu__send_out__val [0:3][0:1]; - - VectorMulRTL__848c3e0c53bb478c Fu__0 - ( - .clk( Fu__clk[0] ), - .reset( Fu__reset[0] ), - .recv_const__msg( Fu__recv_const__msg[0] ), - .recv_const__rdy( Fu__recv_const__rdy[0] ), - .recv_const__val( Fu__recv_const__val[0] ), - .recv_in__msg( Fu__recv_in__msg[0] ), - .recv_in__rdy( Fu__recv_in__rdy[0] ), - .recv_in__val( Fu__recv_in__val[0] ), - .recv_opt__msg( Fu__recv_opt__msg[0] ), - .recv_opt__rdy( Fu__recv_opt__rdy[0] ), - .recv_opt__val( Fu__recv_opt__val[0] ), - .send_out__msg( Fu__send_out__msg[0] ), - .send_out__rdy( Fu__send_out__rdy[0] ), - .send_out__val( Fu__send_out__val[0] ) - ); - - VectorMulRTL__848c3e0c53bb478c Fu__1 - ( - .clk( Fu__clk[1] ), - .reset( Fu__reset[1] ), - .recv_const__msg( Fu__recv_const__msg[1] ), - .recv_const__rdy( Fu__recv_const__rdy[1] ), - .recv_const__val( Fu__recv_const__val[1] ), - .recv_in__msg( Fu__recv_in__msg[1] ), - .recv_in__rdy( Fu__recv_in__rdy[1] ), - .recv_in__val( Fu__recv_in__val[1] ), - .recv_opt__msg( Fu__recv_opt__msg[1] ), - .recv_opt__rdy( Fu__recv_opt__rdy[1] ), - .recv_opt__val( Fu__recv_opt__val[1] ), - .send_out__msg( Fu__send_out__msg[1] ), - .send_out__rdy( Fu__send_out__rdy[1] ), - .send_out__val( Fu__send_out__val[1] ) - ); - - VectorMulRTL__848c3e0c53bb478c Fu__2 - ( - .clk( Fu__clk[2] ), - .reset( Fu__reset[2] ), - .recv_const__msg( Fu__recv_const__msg[2] ), - .recv_const__rdy( Fu__recv_const__rdy[2] ), - .recv_const__val( Fu__recv_const__val[2] ), - .recv_in__msg( Fu__recv_in__msg[2] ), - .recv_in__rdy( Fu__recv_in__rdy[2] ), - .recv_in__val( Fu__recv_in__val[2] ), - .recv_opt__msg( Fu__recv_opt__msg[2] ), - .recv_opt__rdy( Fu__recv_opt__rdy[2] ), - .recv_opt__val( Fu__recv_opt__val[2] ), - .send_out__msg( Fu__send_out__msg[2] ), - .send_out__rdy( Fu__send_out__rdy[2] ), - .send_out__val( Fu__send_out__val[2] ) - ); - - VectorMulRTL__848c3e0c53bb478c Fu__3 - ( - .clk( Fu__clk[3] ), - .reset( Fu__reset[3] ), - .recv_const__msg( Fu__recv_const__msg[3] ), - .recv_const__rdy( Fu__recv_const__rdy[3] ), - .recv_const__val( Fu__recv_const__val[3] ), - .recv_in__msg( Fu__recv_in__msg[3] ), - .recv_in__rdy( Fu__recv_in__rdy[3] ), - .recv_in__val( Fu__recv_in__val[3] ), - .recv_opt__msg( Fu__recv_opt__msg[3] ), - .recv_opt__rdy( Fu__recv_opt__rdy[3] ), - .recv_opt__val( Fu__recv_opt__val[3] ), - .send_out__msg( Fu__send_out__msg[3] ), - .send_out__rdy( Fu__send_out__rdy[3] ), - .send_out__val( Fu__send_out__val[3] ) - ); - - //------------------------------------------------------------- - // End of component Fu[0:3] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:80 - // @update - // def update_input_output(): - // - // # Initialization to avoid latches - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // - // s.send_out[0].val @= s.Fu[0].send_out[0].val & \ - // s.recv_opt.val - // s.send_out[0].msg.payload @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // - // s.recv_from_ctrl_mem.rdy @= 0 - // - // for i in range(num_lanes): - // s.temp_result[i] @= TempDataType(0) - // s.Fu[i].recv_in[0].msg[0:sub_bw] @= FuDataType() - // s.Fu[i].recv_in[1].msg[0:sub_bw] @= FuDataType() - // - // if s.recv_opt.msg.operation == OPT_VEC_MUL: - // # Connection: split into vectorized FUs - // s.Fu[0].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] - // s.Fu[0].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] - // s.Fu[1].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] - // s.Fu[1].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] - // s.Fu[2].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw_2:sub_bw_3] - // s.Fu[2].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw_2:sub_bw_3] - // s.Fu[3].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw_3:sub_bw_4] - // s.Fu[3].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw_3:sub_bw_4] - // - // for i in range(num_lanes): - // s.temp_result[i] @= TempDataType(0) - // s.temp_result[i][0:sub_bw_2] @= s.Fu[i].send_out[0].msg[0:sub_bw_2] - // - // s.send_out[0].msg.payload[0:data_bitwidth] @= \ - // (s.temp_result[3] << (sub_bw * 3)) + \ - // (s.temp_result[2] << (sub_bw * 2)) + \ - // (s.temp_result[1] << sub_bw) + \ - // s.temp_result[0] - // - // elif s.recv_opt.msg.operation == OPT_VEC_MUL_COMBINED: # with highest precision - // s.Fu[0].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] - // s.Fu[0].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] - // s.Fu[1].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[0:sub_bw] - // s.Fu[1].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] - // s.Fu[2].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] - // s.Fu[2].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[0:sub_bw] - // s.Fu[3].recv_in[0].msg[0:sub_bw] @= s.recv_in[0].msg.payload[sub_bw:sub_bw_2] - // s.Fu[3].recv_in[1].msg[0:sub_bw] @= s.recv_in[1].msg.payload[sub_bw:sub_bw_2] - // - // for i in range(num_lanes): - // s.temp_result[i] @= TempDataType(0) - // s.temp_result[i][0:sub_bw_2] @= s.Fu[i].send_out[0].msg[0:sub_bw_2] - // - // s.send_out[0].msg.payload[0:data_bitwidth] @= \ - // s.temp_result[0] + \ - // (s.temp_result[1] << sub_bw) + \ - // (s.temp_result[2] << sub_bw) + \ - // (s.temp_result[3] << (sub_bw * 2)) - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - - always_comb begin : update_input_output - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_input_output ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - send_out__val[1'd0] = Fu__send_out__val[2'd0][1'd0] & recv_opt__val; - send_out__msg[1'd0].payload = 64'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin - temp_result[2'(i)] = 64'd0; - Fu__recv_in__msg[2'(i)][2'd0][5'd15:5'd0] = 16'd0; - Fu__recv_in__msg[2'(i)][2'd1][5'd15:5'd0] = 16'd0; - end - if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL ) ) begin - Fu__recv_in__msg[2'd0][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd0][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd1][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - Fu__recv_in__msg[2'd1][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - Fu__recv_in__msg[2'd2][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd47:6'( __const__sub_bw_2_at_update_input_output )]; - Fu__recv_in__msg[2'd2][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd47:6'( __const__sub_bw_2_at_update_input_output )]; - Fu__recv_in__msg[2'd3][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd63:6'( __const__sub_bw_3_at_update_input_output )]; - Fu__recv_in__msg[2'd3][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd63:6'( __const__sub_bw_3_at_update_input_output )]; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin - temp_result[2'(i)] = 64'd0; - temp_result[2'(i)][6'd31:6'd0] = Fu__send_out__msg[2'(i)][1'd0][5'd31:5'd0]; - end - send_out__msg[1'd0].payload[6'd63:6'd0] = ( ( ( temp_result[2'd3] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd3 ) ) + ( temp_result[2'd2] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd2 ) ) ) + ( temp_result[2'd1] << 5'( __const__sub_bw_at_update_input_output ) ) ) + temp_result[2'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL_COMBINED ) ) begin - Fu__recv_in__msg[2'd0][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd0][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd1][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd1][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - Fu__recv_in__msg[2'd2][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - Fu__recv_in__msg[2'd2][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd15:6'd0]; - Fu__recv_in__msg[2'd3][2'd0][5'd15:5'd0] = recv_in__msg[2'd0].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - Fu__recv_in__msg[2'd3][2'd1][5'd15:5'd0] = recv_in__msg[2'd1].payload[6'd31:6'( __const__sub_bw_at_update_input_output )]; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_input_output ); i += 1'd1 ) begin - temp_result[2'(i)] = 64'd0; - temp_result[2'(i)][6'd31:6'd0] = Fu__send_out__msg[2'(i)][1'd0][5'd31:5'd0]; - end - send_out__msg[1'd0].payload[6'd63:6'd0] = ( ( temp_result[2'd0] + ( temp_result[2'd1] << 5'( __const__sub_bw_at_update_input_output ) ) ) + ( temp_result[2'd2] << 5'( __const__sub_bw_at_update_input_output ) ) ) + ( temp_result[2'd3] << ( 5'( __const__sub_bw_at_update_input_output ) * 5'd2 ) ); - end - else - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_input_output ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:183 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= AddrType(0) - // s.to_mem_raddr.msg @= AddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:168 - // @update - // def update_opt(): - // s.send_out[0].msg.predicate @= b1(0) - // - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.fu_in[0] @= 1 - // s.Fu[i].recv_opt.msg.fu_in[1] @= 2 - // s.Fu[i].recv_opt.msg.operation @= OPT_NAH - // - // if (s.recv_opt.msg.operation == OPT_VEC_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_MUL_COMBINED): - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.operation @= OPT_MUL - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate - - always_comb begin : update_opt - send_out__msg[1'd0].predicate = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].fu_in[2'd0] = 3'd1; - Fu__recv_opt__msg[2'(i)].fu_in[2'd1] = 3'd2; - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_NAH ); - end - if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_MUL_COMBINED ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_MUL ); - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorMulComboRTL.py:146 - // @update - // def update_signal(): - // s.recv_in[0].rdy @= s.Fu[0].recv_in[0].rdy - // s.recv_in[1].rdy @= s.Fu[0].recv_in[1].rdy - // - // for i in range(num_lanes): - // s.Fu[i].recv_opt.val @= s.recv_opt.val - // - // # Note that the predication for a combined FU should be identical/shareable, - // # which means the computation in different basic block cannot be combined. - // # s.Fu[i].recv_opt.msg.predicate = s.recv_opt.msg.predicate - // - // s.Fu[i].recv_in[0].val @= s.recv_in[0].val - // s.Fu[i].recv_in[1].val @= s.recv_in[1].val - // s.Fu[i].recv_const.val @= s.recv_const.val - // - // for j in range(num_outports): - // s.Fu[i].send_out[j].rdy @= s.send_out[j].rdy - // - // s.recv_const.rdy @= s.Fu[0].recv_const.rdy - // s.recv_opt.rdy @= s.send_out[0].rdy - - always_comb begin : update_signal - recv_in__rdy[2'd0] = Fu__recv_in__rdy[2'd0][2'd0]; - recv_in__rdy[2'd1] = Fu__recv_in__rdy[2'd0][2'd1]; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_signal ); i += 1'd1 ) begin - Fu__recv_opt__val[2'(i)] = recv_opt__val; - Fu__recv_in__val[2'(i)][2'd0] = recv_in__val[2'd0]; - Fu__recv_in__val[2'(i)][2'd1] = recv_in__val[2'd1]; - Fu__recv_const__val[2'(i)] = recv_const__val; - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_signal ); j += 1'd1 ) - Fu__send_out__rdy[2'(i)][1'(j)] = send_out__rdy[1'(j)]; - end - recv_const__rdy = Fu__recv_const__rdy[2'd0]; - recv_opt__rdy = send_out__rdy[1'd0]; - end - - assign Fu__clk[0] = clk; - assign Fu__reset[0] = reset; - assign Fu__clk[1] = clk; - assign Fu__reset[1] = reset; - assign Fu__clk[2] = clk; - assign Fu__reset[2] = reset; - assign Fu__clk[3] = clk; - assign Fu__reset[3] = reset; - -endmodule - - -// PyMTL Component VectorAdderRTL Definition -// Full name: VectorAdderRTL__bw_16__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderRTL.py - -module VectorAdderRTL__848c3e0c53bb478c -( - input logic [0:0] carry_in , - output logic [0:0] carry_out , - input logic [0:0] clk , - input logic [0:0] combine_adder , - input logic [0:0] reset , - input logic [16:0] recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input logic [16:0] recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output logic [16:0] send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] -); - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_ADD = 7'd2; - localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; - localparam logic [6:0] __const__OPT_INC = 7'd3; - localparam logic [6:0] __const__OPT_SUB = 7'd4; - localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; - localparam logic [6:0] __const__OPT_PAS = 7'd31; - localparam logic [4:0] __const__bw_at_comb_logic = 5'd16; - logic [16:0] carry_in_temp; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] recv_all_val; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderRTL.py:58 - // @update - // def comb_logic(): - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= b1(0) - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.carry_in_temp[0] @= s.carry_in & s.combine_adder - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_ADD: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.recv_in[s.in1_idx].msg + s.carry_in_temp - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_ADD_CONST: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.recv_const.msg + s.carry_in_temp - // s.recv_const.rdy @= s.send_out[0].rdy - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_INC: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg + s.const_one - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - s.recv_in[s.in1_idx].msg - s.carry_in_temp - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_SUB_CONST: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - s.recv_const.msg - s.carry_in_temp - // s.recv_const.rdy @= s.send_out[0].rdy - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_PAS: - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - // - // s.carry_out @= s.send_out[0].msg[bw:bw+1] - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = 17'd0; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - carry_in_temp[5'd0] = carry_in & combine_adder; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_ADD ) ) begin - send_out__msg[1'd0] = ( recv_in__msg[in0_idx] + recv_in__msg[in1_idx] ) + carry_in_temp; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST ) ) begin - send_out__msg[1'd0] = ( recv_in__msg[in0_idx] + recv_const__msg ) + carry_in_temp; - recv_const__rdy = send_out__rdy[1'd0]; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_INC ) ) begin - send_out__msg[1'd0] = recv_in__msg[in0_idx] + 17'd1; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB ) ) begin - send_out__msg[1'd0] = ( recv_in__msg[in0_idx] - recv_in__msg[in1_idx] ) - carry_in_temp; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_SUB_CONST ) ) begin - send_out__msg[1'd0] = ( recv_in__msg[in0_idx] - recv_const__msg ) - carry_in_temp; - recv_const__rdy = send_out__rdy[1'd0]; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_PAS ) ) begin - send_out__msg[1'd0] = recv_in__msg[in0_idx]; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - carry_out = send_out__msg[1'd0][5'd16:5'( __const__bw_at_comb_logic )]; - end - - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component VectorAdderComboRTL Definition -// Full name: VectorAdderComboRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py - -module VectorAdderComboRTL__e2d25a29972e2033 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [2:0] __const__num_lanes_at_update_signal = 3'd4; - localparam logic [1:0] __const__num_outports_at_update_signal = 2'd2; - localparam logic [1:0] __const__num_outports_at_update_opt = 2'd2; - localparam logic [2:0] __const__num_lanes_at_update_opt = 3'd4; - localparam logic [6:0] __const__OPT_NAH = 7'd1; - localparam logic [6:0] __const__OPT_VEC_ADD = 7'd51; - localparam logic [6:0] __const__OPT_VEC_ADD_COMBINED = 7'd71; - localparam logic [6:0] __const__OPT_ADD = 7'd2; - localparam logic [6:0] __const__OPT_VEC_SUB = 7'd53; - localparam logic [6:0] __const__OPT_VEC_SUB_COMBINED = 7'd73; - localparam logic [6:0] __const__OPT_SUB = 7'd4; - localparam logic [6:0] __const__OPT_VEC_ADD_CONST = 7'd52; - localparam logic [6:0] __const__OPT_VEC_ADD_CONST_COMBINED = 7'd72; - localparam logic [6:0] __const__OPT_ADD_CONST = 7'd25; - localparam logic [6:0] __const__OPT_VEC_SUB_CONST = 7'd54; - localparam logic [6:0] __const__OPT_VEC_SUB_CONST_COMBINED = 7'd74; - localparam logic [6:0] __const__OPT_SUB_CONST = 7'd36; - //------------------------------------------------------------- - // Component Fu[0:3] - //------------------------------------------------------------- - - logic [0:0] Fu__carry_in [0:3]; - logic [0:0] Fu__carry_out [0:3]; - logic [0:0] Fu__clk [0:3]; - logic [0:0] Fu__combine_adder [0:3]; - logic [0:0] Fu__reset [0:3]; - logic [16:0] Fu__recv_const__msg [0:3]; - logic [0:0] Fu__recv_const__rdy [0:3]; - logic [0:0] Fu__recv_const__val [0:3]; - logic [16:0] Fu__recv_in__msg [0:3][0:3]; - logic [0:0] Fu__recv_in__rdy [0:3][0:3]; - logic [0:0] Fu__recv_in__val [0:3][0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 Fu__recv_opt__msg [0:3]; - logic [0:0] Fu__recv_opt__rdy [0:3]; - logic [0:0] Fu__recv_opt__val [0:3]; - logic [16:0] Fu__send_out__msg [0:3][0:1]; - logic [0:0] Fu__send_out__rdy [0:3][0:1]; - logic [0:0] Fu__send_out__val [0:3][0:1]; - - VectorAdderRTL__848c3e0c53bb478c Fu__0 - ( - .carry_in( Fu__carry_in[0] ), - .carry_out( Fu__carry_out[0] ), - .clk( Fu__clk[0] ), - .combine_adder( Fu__combine_adder[0] ), - .reset( Fu__reset[0] ), - .recv_const__msg( Fu__recv_const__msg[0] ), - .recv_const__rdy( Fu__recv_const__rdy[0] ), - .recv_const__val( Fu__recv_const__val[0] ), - .recv_in__msg( Fu__recv_in__msg[0] ), - .recv_in__rdy( Fu__recv_in__rdy[0] ), - .recv_in__val( Fu__recv_in__val[0] ), - .recv_opt__msg( Fu__recv_opt__msg[0] ), - .recv_opt__rdy( Fu__recv_opt__rdy[0] ), - .recv_opt__val( Fu__recv_opt__val[0] ), - .send_out__msg( Fu__send_out__msg[0] ), - .send_out__rdy( Fu__send_out__rdy[0] ), - .send_out__val( Fu__send_out__val[0] ) - ); - - VectorAdderRTL__848c3e0c53bb478c Fu__1 - ( - .carry_in( Fu__carry_in[1] ), - .carry_out( Fu__carry_out[1] ), - .clk( Fu__clk[1] ), - .combine_adder( Fu__combine_adder[1] ), - .reset( Fu__reset[1] ), - .recv_const__msg( Fu__recv_const__msg[1] ), - .recv_const__rdy( Fu__recv_const__rdy[1] ), - .recv_const__val( Fu__recv_const__val[1] ), - .recv_in__msg( Fu__recv_in__msg[1] ), - .recv_in__rdy( Fu__recv_in__rdy[1] ), - .recv_in__val( Fu__recv_in__val[1] ), - .recv_opt__msg( Fu__recv_opt__msg[1] ), - .recv_opt__rdy( Fu__recv_opt__rdy[1] ), - .recv_opt__val( Fu__recv_opt__val[1] ), - .send_out__msg( Fu__send_out__msg[1] ), - .send_out__rdy( Fu__send_out__rdy[1] ), - .send_out__val( Fu__send_out__val[1] ) - ); - - VectorAdderRTL__848c3e0c53bb478c Fu__2 - ( - .carry_in( Fu__carry_in[2] ), - .carry_out( Fu__carry_out[2] ), - .clk( Fu__clk[2] ), - .combine_adder( Fu__combine_adder[2] ), - .reset( Fu__reset[2] ), - .recv_const__msg( Fu__recv_const__msg[2] ), - .recv_const__rdy( Fu__recv_const__rdy[2] ), - .recv_const__val( Fu__recv_const__val[2] ), - .recv_in__msg( Fu__recv_in__msg[2] ), - .recv_in__rdy( Fu__recv_in__rdy[2] ), - .recv_in__val( Fu__recv_in__val[2] ), - .recv_opt__msg( Fu__recv_opt__msg[2] ), - .recv_opt__rdy( Fu__recv_opt__rdy[2] ), - .recv_opt__val( Fu__recv_opt__val[2] ), - .send_out__msg( Fu__send_out__msg[2] ), - .send_out__rdy( Fu__send_out__rdy[2] ), - .send_out__val( Fu__send_out__val[2] ) - ); - - VectorAdderRTL__848c3e0c53bb478c Fu__3 - ( - .carry_in( Fu__carry_in[3] ), - .carry_out( Fu__carry_out[3] ), - .clk( Fu__clk[3] ), - .combine_adder( Fu__combine_adder[3] ), - .reset( Fu__reset[3] ), - .recv_const__msg( Fu__recv_const__msg[3] ), - .recv_const__rdy( Fu__recv_const__rdy[3] ), - .recv_const__val( Fu__recv_const__val[3] ), - .recv_in__msg( Fu__recv_in__msg[3] ), - .recv_in__rdy( Fu__recv_in__rdy[3] ), - .recv_in__val( Fu__recv_in__val[3] ), - .recv_opt__msg( Fu__recv_opt__msg[3] ), - .recv_opt__rdy( Fu__recv_opt__rdy[3] ), - .recv_opt__val( Fu__recv_opt__val[3] ), - .send_out__msg( Fu__send_out__msg[3] ), - .send_out__rdy( Fu__send_out__rdy[3] ), - .send_out__val( Fu__send_out__val[3] ) - ); - - //------------------------------------------------------------- - // End of component Fu[0:3] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:158 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= AddrType(0) - // s.to_mem_raddr.msg @= AddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:108 - // @update - // def update_opt(): - // - // for j in range( num_outports ): - // s.send_out[j].val @= b1(0) - // s.send_out[j].msg.predicate @= b1(0) - // - // s.send_out[0].val @= s.Fu[0].send_out[0].val & \ - // s.recv_opt.val - // - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.fu_in[0] @= 1 - // s.Fu[i].recv_opt.msg.fu_in[1] @= 2 - // s.Fu[i].recv_opt.msg.operation @= OPT_NAH - // s.Fu[i].combine_adder @= 0 - // - // if ( s.recv_opt.msg.operation == OPT_VEC_ADD ) | \ - // ( s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED ): - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.operation @= OPT_ADD - // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED) - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate - // - // elif ( s.recv_opt.msg.operation == OPT_VEC_SUB ) | \ - // ( s.recv_opt.msg.operation == OPT_VEC_SUB_COMBINED ): - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.operation @= OPT_SUB - // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_SUB_COMBINED) - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & s.recv_in[1].msg.predicate - // - // # elif ( s.recv_opt.msg.operation == OPT_VEC_ADD_CONST ) | \ - // # ( s.recv_opt.msg.operation == OPT_ADD_CONST ): - // elif (s.recv_opt.msg.operation == OPT_VEC_ADD_CONST) | \ - // (s.recv_opt.msg.operation == OPT_VEC_ADD_CONST_COMBINED): - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.operation @= OPT_ADD_CONST - // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_ADD_COMBINED) - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate - // - // elif (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST ) | \ - // (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST_COMBINED ): - // for i in range(num_lanes): - // s.Fu[i].recv_opt.msg.operation @= OPT_SUB_CONST - // s.Fu[i].combine_adder @= (s.recv_opt.msg.operation == OPT_VEC_SUB_CONST_COMBINED) - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - - always_comb begin : update_opt - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_opt ); j += 1'd1 ) begin - send_out__val[1'(j)] = 1'd0; - send_out__msg[1'(j)].predicate = 1'd0; - end - send_out__val[1'd0] = Fu__send_out__val[2'd0][1'd0] & recv_opt__val; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].fu_in[2'd0] = 3'd1; - Fu__recv_opt__msg[2'(i)].fu_in[2'd1] = 3'd2; - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_NAH ); - Fu__combine_adder[2'(i)] = 1'd0; - end - if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_ADD ); - Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ); - end - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_COMBINED ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_SUB ); - Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_COMBINED ); - end - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_CONST_COMBINED ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_ADD_CONST ); - Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_ADD_COMBINED ); - end - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST_COMBINED ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_opt ); i += 1'd1 ) begin - Fu__recv_opt__msg[2'(i)].operation = 7'( __const__OPT_SUB_CONST ); - Fu__combine_adder[2'(i)] = recv_opt__msg.operation == 7'( __const__OPT_VEC_SUB_CONST_COMBINED ); - end - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; - end - else - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_opt ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAdderComboRTL.py:82 - // @update - // def update_signal(): - // s.recv_in[0].rdy @= s.Fu[0].recv_in[0].rdy - // s.recv_in[1].rdy @= s.Fu[0].recv_in[1].rdy - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // - // s.recv_from_ctrl_mem.rdy @= 0 - // - // for i in range(num_lanes): - // s.Fu[i].recv_opt.val @= s.recv_opt.val - // - // for j in range(num_outports): - // s.Fu[i].send_out[j].rdy @= s.send_out[j].rdy - // - // s.Fu[i].recv_in[0].val @= s.recv_in[0].val - // s.Fu[i].recv_in[1].val @= s.recv_in[1].val - // s.Fu[i].recv_const.val @= s.recv_const.val - // - // # Note that the predication for a combined FU should be identical/shareable, - // # which means the computation in different basic block cannot be combined. - // # s.Fu[i].recv_opt.msg.predicate = s.recv_opt.msg.predicate - // s.recv_const.rdy @= s.Fu[0].recv_const.rdy - // s.recv_opt.rdy @= s.Fu[0].recv_opt.rdy - - always_comb begin : update_signal - recv_in__rdy[2'd0] = Fu__recv_in__rdy[2'd0][2'd0]; - recv_in__rdy[2'd1] = Fu__recv_in__rdy[2'd0][2'd1]; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_lanes_at_update_signal ); i += 1'd1 ) begin - Fu__recv_opt__val[2'(i)] = recv_opt__val; - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_update_signal ); j += 1'd1 ) - Fu__send_out__rdy[2'(i)][1'(j)] = send_out__rdy[1'(j)]; - Fu__recv_in__val[2'(i)][2'd0] = recv_in__val[2'd0]; - Fu__recv_in__val[2'(i)][2'd1] = recv_in__val[2'd1]; - Fu__recv_const__val[2'(i)] = recv_const__val; - end - recv_const__rdy = Fu__recv_const__rdy[2'd0]; - recv_opt__rdy = Fu__recv_opt__rdy[2'd0]; - end - - assign Fu__clk[0] = clk; - assign Fu__reset[0] = reset; - assign Fu__clk[1] = clk; - assign Fu__reset[1] = reset; - assign Fu__clk[2] = clk; - assign Fu__reset[2] = reset; - assign Fu__clk[3] = clk; - assign Fu__reset[3] = reset; - assign Fu__carry_in[0] = 1'd0; - assign Fu__carry_in[1] = Fu__carry_out[0]; - assign Fu__carry_in[2] = Fu__carry_out[1]; - assign Fu__carry_in[3] = Fu__carry_out[2]; - assign Fu__recv_in__msg[0][0][15:0] = recv_in__msg[0].payload[15:0]; - assign Fu__recv_in__msg[0][1][15:0] = recv_in__msg[1].payload[15:0]; - assign Fu__recv_const__msg[0][15:0] = recv_const__msg.payload[15:0]; - assign send_out__msg[0].payload[15:0] = Fu__send_out__msg[0][0][15:0]; - assign Fu__recv_in__msg[1][0][15:0] = recv_in__msg[0].payload[31:16]; - assign Fu__recv_in__msg[1][1][15:0] = recv_in__msg[1].payload[31:16]; - assign Fu__recv_const__msg[1][15:0] = recv_const__msg.payload[31:16]; - assign send_out__msg[0].payload[31:16] = Fu__send_out__msg[1][0][15:0]; - assign Fu__recv_in__msg[2][0][15:0] = recv_in__msg[0].payload[47:32]; - assign Fu__recv_in__msg[2][1][15:0] = recv_in__msg[1].payload[47:32]; - assign Fu__recv_const__msg[2][15:0] = recv_const__msg.payload[47:32]; - assign send_out__msg[0].payload[47:32] = Fu__send_out__msg[2][0][15:0]; - assign Fu__recv_in__msg[3][0][15:0] = recv_in__msg[0].payload[63:48]; - assign Fu__recv_in__msg[3][1][15:0] = recv_in__msg[1].payload[63:48]; - assign Fu__recv_const__msg[3][15:0] = recv_const__msg.payload[63:48]; - assign send_out__msg[0].payload[63:48] = Fu__send_out__msg[3][0][15:0]; - -endmodule - - -// PyMTL Component SumUnit Definition -// At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py - -module SumUnit__DataType_Bits64__num_inputs_4 -( - input logic [0:0] clk , - input logic [63:0] in_ [0:3], - output logic [63:0] out , - input logic [0:0] reset -); - logic [63:0] partial_sum [0:3]; - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py:37 - // s.out //= lambda: s.partial_sum[s.num_inputs-1] - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_out - out = partial_sum[3'd4 - 3'd1]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/SumUnit.py:31 - // @update - // def up_sum(): - // s.partial_sum[0] @= s.in_[0] - // for i in range( 1, s.num_inputs ): - // s.partial_sum[i] @= s.partial_sum[i-1] + s.in_[i] - - always_comb begin : up_sum - partial_sum[2'd0] = in_[2'd0]; - for ( int unsigned i = 1'd1; i < 3'd4; i += 1'd1 ) - partial_sum[2'(i)] = partial_sum[2'(i) - 2'd1] + in_[2'(i)]; - end - -endmodule - - -// PyMTL Component ReduceMulUnit Definition -// At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/ReduceMulUnit.py - -module ReduceMulUnit__DataType_Bits64__num_inputs_4 -( - input logic [0:0] clk , - input logic [63:0] in_ [0:3], - output logic [63:0] out , - input logic [0:0] reset -); - logic [63:0] partial_sum [0:3]; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/ReduceMulUnit.py:32 - // @update - // def up_sum(): - // s.partial_sum[0] @= s.in_[0] - // for i in range( 1, s.num_inputs ): - // s.partial_sum[i] @= s.partial_sum[i-1] * s.in_[i] - - always_comb begin : up_sum - partial_sum[2'd0] = in_[2'd0]; - for ( int unsigned i = 1'd1; i < 3'd4; i += 1'd1 ) - partial_sum[2'(i)] = partial_sum[2'(i) - 2'd1] * in_[2'(i)]; - end - - assign out = partial_sum[3]; - -endmodule - - -// PyMTL Component VectorAllReduceRTL Definition -// Full name: VectorAllReduceRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__num_lanes_4__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py - -module VectorAllReduceRTL__e2d25a29972e2033 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD = 7'd56; - localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_BASE = 7'd68; - localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_GLOBAL = 7'd76; - localparam logic [6:0] __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL = 7'd78; - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ = 1'd0; - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ = 1'd1; - localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ = 2'd2; - localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ = 2'd3; - localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL = 7'd57; - localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_BASE = 7'd69; - localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_GLOBAL = 7'd77; - localparam logic [6:0] __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL = 7'd79; - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ = 1'd0; - localparam logic [0:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ = 1'd1; - localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ = 2'd2; - localparam logic [1:0] __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ = 2'd3; - localparam logic [6:0] __const__data_bitwidth_at_update_result = 7'd64; - localparam logic [2:0] __const__num_inports_at_update_signal = 3'd4; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD = 5'd18; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL = 5'd19; - logic [0:0] already_sent_to_controller; - logic [63:0] temp_result [0:3]; - //------------------------------------------------------------- - // Component reduce_add - //------------------------------------------------------------- - - logic [0:0] reduce_add__clk; - logic [63:0] reduce_add__in_ [0:3]; - logic [63:0] reduce_add__out; - logic [0:0] reduce_add__reset; - - SumUnit__DataType_Bits64__num_inputs_4 reduce_add - ( - .clk( reduce_add__clk ), - .in_( reduce_add__in_ ), - .out( reduce_add__out ), - .reset( reduce_add__reset ) - ); - - //------------------------------------------------------------- - // End of component reduce_add - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component reduce_mul - //------------------------------------------------------------- - - logic [0:0] reduce_mul__clk; - logic [63:0] reduce_mul__in_ [0:3]; - logic [63:0] reduce_mul__out; - logic [0:0] reduce_mul__reset; - - ReduceMulUnit__DataType_Bits64__num_inputs_4 reduce_mul - ( - .clk( reduce_mul__clk ), - .in_( reduce_mul__in_ ), - .out( reduce_mul__out ), - .reset( reduce_mul__reset ) - ); - - //------------------------------------------------------------- - // End of component reduce_mul - //------------------------------------------------------------- - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 - // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ - reduce_add__in_[2'd0] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__0_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 - // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ - reduce_add__in_[2'd1] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__1_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 - // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ - reduce_add__in_[2'd2] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__2_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:72 - // s.reduce_add.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ - reduce_add__in_[2'd3] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_add_in__3_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 - // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ - reduce_mul__in_[2'd0] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__0_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 - // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ - reduce_mul__in_[2'd1] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__1_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 - // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ - reduce_mul__in_[2'd2] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__2_ )] : 64'd0; - end - - // PyMTL Lambda Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:80 - // s.reduce_mul.in_[i] //= lambda: (s.temp_result[i] - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) else 0) - - always_comb begin : _lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ - reduce_mul__in_[2'd3] = ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ? temp_result[2'( __const__i_at__lambda__s_dut_cgra_0__tile_0__element_fu_13__reduce_mul_in__3_ )] : 64'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:233 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:194 - // @update - // def update_predicate(): - // s.send_out[0].msg.predicate @= 0 - // if ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL)): - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate - // elif ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)): - // s.send_out[0].msg.predicate @= s.recv_in[0].msg.predicate & \ - // s.recv_in[1].msg.predicate - // elif ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)): - // s.send_out[0].msg.predicate @= s.recv_from_ctrl_mem.msg.data.predicate & \ - // s.recv_in[1].msg.predicate - - always_comb begin : update_predicate - send_out__msg[1'd0].predicate = 1'd0; - if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) begin - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) begin - send_out__msg[1'd0].predicate = recv_in__msg[2'd0].predicate & recv_in__msg[2'd1].predicate; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) begin - send_out__msg[1'd0].predicate = recv_from_ctrl_mem__msg.data.predicate & recv_in__msg[2'd1].predicate; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:94 - // @update - // def update_result(): - // # Connection: splits data into vectorized wires. - // s.send_out[0].msg.payload @= 0 - // - // if s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_add.out - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_add.out + s.recv_in[1].msg.payload - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_mul.out - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.reduce_mul.out * s.recv_in[1].msg.payload - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] + s.recv_in[1].msg.payload - // elif s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL: - // s.send_out[0].msg.payload[0:data_bitwidth] @= s.recv_from_ctrl_mem.msg.data.payload[0:data_bitwidth] * s.recv_in[1].msg.payload - - always_comb begin : update_result - send_out__msg[1'd0].payload = 64'd0; - if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_add__out; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_add__out + recv_in__msg[2'd1].payload; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_mul__out; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = reduce_mul__out * recv_in__msg[2'd1].payload; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0] + recv_in__msg[2'd1].payload; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) begin - send_out__msg[1'd0].payload[6'd63:6'd0] = recv_from_ctrl_mem__msg.data.payload[6'd63:6'd0] * recv_in__msg[2'd1].payload; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:116 - // @update - // def update_signal(): - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // - // s.recv_from_ctrl_mem.rdy @= 0 - // - // s.recv_in[0].rdy @= (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)) & \ - // s.send_out[0].rdy) | \ - // (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ - // s.send_to_ctrl_mem.rdy) - // s.recv_opt.rdy @= s.send_out[0].rdy - // s.recv_in[1].rdy @= (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE)) & \ - // s.send_out[0].rdy) | \ - // (((s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ - // s.send_to_ctrl_mem.rdy) - // s.send_out[0].val @= (s.recv_in[0].val & \ - // s.recv_opt.val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL))) | \ - // (s.recv_in[0].val & \ - // s.recv_in[1].val & \ - // s.recv_opt.val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE))) | \ - // (s.recv_opt.val & \ - // s.recv_from_ctrl_mem.val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL))) | \ - // (s.recv_opt.val & \ - // s.recv_from_ctrl_mem.val & \ - // s.recv_in[1].val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL))) - // - // if s.recv_opt.val & \ - // ~s.already_sent_to_controller & \ - // (s.recv_in[0].val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL))) | \ - // (s.recv_in[0].val & \ - // s.recv_in[1].val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL))): - // s.send_to_ctrl_mem.val @= 1 - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL): - // s.send_to_ctrl_mem.msg @= \ - // s.CgraPayloadType(CMD_GLOBAL_REDUCE_ADD, - // DataType(s.reduce_add.out, - // s.recv_in[0].msg.predicate, 0, 0), - // 0, - // s.recv_opt.msg, - // 0) - // if (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL): - // s.send_to_ctrl_mem.msg @= \ - // s.CgraPayloadType(CMD_GLOBAL_REDUCE_MUL, - // DataType(s.reduce_add.out, - // s.recv_in[0].msg.predicate, 0, 0), - // 0, - // s.recv_opt.msg, - // 0) - // - // if s.recv_opt.val & s.already_sent_to_controller: - // s.recv_from_ctrl_mem.rdy @= 1 - - always_comb begin : update_signal - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - recv_in__rdy[2'd0] = ( ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) & send_out__rdy[1'd0] ) | ( ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) & send_to_ctrl_mem__rdy ); - recv_opt__rdy = send_out__rdy[1'd0]; - recv_in__rdy[2'd1] = ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) & send_out__rdy[1'd0] ) | ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) & send_to_ctrl_mem__rdy ); - send_out__val[1'd0] = ( ( ( ( recv_in__val[2'd0] & recv_opt__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL ) ) ) ) | ( ( ( recv_in__val[2'd0] & recv_in__val[2'd1] ) & recv_opt__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE ) ) ) ) ) | ( ( recv_opt__val & recv_from_ctrl_mem__val ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) ) ) | ( ( ( recv_opt__val & recv_from_ctrl_mem__val ) & recv_in__val[2'd1] ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ); - if ( ( ( recv_opt__val & ( ~already_sent_to_controller ) ) & ( recv_in__val[2'd0] & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) ) ) | ( ( recv_in__val[2'd0] & recv_in__val[2'd1] ) & ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) ) begin - send_to_ctrl_mem__val = 1'd1; - if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) begin - send_to_ctrl_mem__msg = { 5'( __const__CMD_GLOBAL_REDUCE_ADD ), { reduce_add__out, recv_in__msg[2'd0].predicate, 1'd0, 1'd0 }, 7'd0, recv_opt__msg, 4'd0 }; - end - if ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) begin - send_to_ctrl_mem__msg = { 5'( __const__CMD_GLOBAL_REDUCE_MUL ), { reduce_add__out, recv_in__msg[2'd0].predicate, 1'd0, 1'd0 }, 7'd0, recv_opt__msg, 4'd0 }; - end - end - if ( recv_opt__val & already_sent_to_controller ) begin - recv_from_ctrl_mem__rdy = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/vector/VectorAllReduceRTL.py:209 - // @update_ff - // def update_already_sent_to_controller(): - // if s.reset: - // s.already_sent_to_controller <<= 0 - // else: - // if s.recv_opt.val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ - // ~s.already_sent_to_controller & \ - // s.send_to_ctrl_mem.val & \ - // s.send_to_ctrl_mem.rdy: - // s.already_sent_to_controller <<= 1 - // # Recovers already_sent_to_controller once the ctrl proceeds to the next one. - // elif s.recv_opt.val & \ - // ((s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_ADD_BASE_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_GLOBAL) | \ - // (s.recv_opt.msg.operation == OPT_VEC_REDUCE_MUL_BASE_GLOBAL)) & \ - // s.already_sent_to_controller & \ - // s.recv_opt.rdy: - // s.already_sent_to_controller <<= 0 - - always_ff @(posedge clk) begin : update_already_sent_to_controller - if ( reset ) begin - already_sent_to_controller <= 1'd0; - end - else if ( ( ( ( recv_opt__val & ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) & ( ~already_sent_to_controller ) ) & send_to_ctrl_mem__val ) & send_to_ctrl_mem__rdy ) begin - already_sent_to_controller <= 1'd1; - end - else if ( ( ( recv_opt__val & ( ( ( ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_GLOBAL ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_ADD_BASE_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_GLOBAL ) ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_VEC_REDUCE_MUL_BASE_GLOBAL ) ) ) ) & already_sent_to_controller ) & recv_opt__rdy ) begin - already_sent_to_controller <= 1'd0; - end - end - - assign reduce_add__clk = clk; - assign reduce_add__reset = reset; - assign reduce_mul__clk = clk; - assign reduce_mul__reset = reset; - assign temp_result[0][15:0] = recv_in__msg[0].payload[15:0]; - assign temp_result[1][15:0] = recv_in__msg[0].payload[31:16]; - assign temp_result[2][15:0] = recv_in__msg[0].payload[47:32]; - assign temp_result[3][15:0] = recv_in__msg[0].payload[63:48]; - -endmodule - - -// PyMTL Component NahRTL Definition -// Full name: NahRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/NahRTL.py - -module NahRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_NAH = 7'd1; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/NahRTL.py:28 - // @update - // def comb_logic(): - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // # For pick input register - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // - // for i in range( num_outports ): - // # s.send_out[i].val @= s.recv_opt.val - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val & (s.recv_opt.msg.operation == OPT_NAH): - // s.recv_opt.rdy @= 1 - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - - always_comb begin : comb_logic - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val & ( recv_opt__msg.operation == 7'( __const__OPT_NAH ) ) ) begin - recv_opt__rdy = 1'd1; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - -endmodule - - -// PyMTL Component MulRTL Definition -// Full name: MulRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py - -module MulRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_MUL = 7'd7; - localparam logic [6:0] __const__OPT_MUL_CONST = 7'd29; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MulRTL.py:44 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != 0: - // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) - // if s.recv_opt.msg.fu_in[1] != 0: - // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_MUL: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_MUL_CONST: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload * s.recv_const.msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_MUL ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_MUL_CONST ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload * recv_const__msg.payload; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component LogicRTL Definition -// Full name: LogicRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/LogicRTL.py - -module LogicRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_OR = 7'd8; - localparam logic [6:0] __const__OPT_AND = 7'd10; - localparam logic [6:0] __const__OPT_BIT_NOT = 7'd43; - localparam logic [6:0] __const__OPT_NOT = 7'd11; - localparam logic [6:0] __const__OPT_XOR = 7'd9; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/LogicRTL.py:44 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range( num_outports ): - // s.send_out[i].val @= b1(0) - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_OR: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload | s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_AND: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload & s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_BIT_NOT: - // s.send_out[0].msg.payload @= ~ s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_NOT: - // if s.recv_in[s.in0_idx].msg.payload == 0: - // s.send_out[0].msg.payload @= 1 - // else: - // s.send_out[0].msg.payload @= 0 - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_XOR: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload ^ s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_OR ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload | recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_AND ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload & recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_BIT_NOT ) ) begin - send_out__msg[1'd0].payload = ~recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_NOT ) ) begin - if ( recv_in__msg[in0_idx].payload == 64'd0 ) begin - send_out__msg[1'd0].payload = 64'd1; - end - else - send_out__msg[1'd0].payload = 64'd0; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_XOR ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload ^ recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component ShifterRTL Definition -// Full name: ShifterRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/ShifterRTL.py - -module ShifterRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_LLS = 7'd5; - localparam logic [6:0] __const__OPT_LRS = 7'd6; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/ShifterRTL.py:44 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= FuInType(0) - // s.in1 @= FuInType(0) - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_LLS: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload << s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_LRS: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload >> s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_LLS ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload << recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_LRS ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload >> recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component PhiRTL Definition -// Full name: PhiRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py - -module PhiRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_PHI = 7'd17; - localparam logic [6:0] __const__OPT_PHI_START = 7'd84; - localparam logic [6:0] __const__OPT_PHI_CONST = 7'd32; - logic [0:0] first; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py:48 - // @update - // def comb_logic(): - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // # TODO: decision needs to be made. Adder could be in FU vector width. Or only effective once on the boundary. - // # if s.recv_opt.val: - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_PHI: - // if s.recv_in[s.in0_idx].msg.predicate == Bits1(1): - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // elif s.recv_in[s.in1_idx].msg.predicate == Bits1(1): - // s.send_out[0].msg.payload @= s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // else: # No predecessor is active. - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= 0 - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_PHI_START: - // if s.first: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // elif s.recv_in[s.in0_idx].msg.predicate == Bits1(1): - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // elif s.recv_in[s.in1_idx].msg.predicate == Bits1(1): - // s.send_out[0].msg.payload @= s.recv_in[s.in1_idx].msg.payload - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // else: # No predecessor is active. - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // s.send_out[0].msg.predicate @= 0 - // s.recv_all_val @= ((s.first & s.recv_in[s.in0_idx].val) | \ - // (~s.first & s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val)) - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= ~s.first & s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_PHI_CONST: - // if s.first: - // s.send_out[0].msg.payload @= s.recv_const.msg.payload - // else: - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // - // s.recv_all_val @= ((s.first & s.recv_const.val) | \ - // (~s.first & s.recv_in[s.in0_idx].val)) - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // if s.first: - // s.send_out[0].msg.predicate @= s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // else: - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_PHI ) ) begin - if ( recv_in__msg[in0_idx].predicate == 1'd1 ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = reached_vector_factor; - end - else if ( recv_in__msg[in1_idx].predicate == 1'd1 ) begin - send_out__msg[1'd0].payload = recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = reached_vector_factor; - end - else begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = 1'd0; - end - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_PHI_START ) ) begin - if ( first ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = reached_vector_factor; - end - else if ( recv_in__msg[in0_idx].predicate == 1'd1 ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = reached_vector_factor; - end - else if ( recv_in__msg[in1_idx].predicate == 1'd1 ) begin - send_out__msg[1'd0].payload = recv_in__msg[in1_idx].payload; - send_out__msg[1'd0].predicate = reached_vector_factor; - end - else begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - send_out__msg[1'd0].predicate = 1'd0; - end - recv_all_val = ( first & recv_in__val[in0_idx] ) | ( ( ( ~first ) & recv_in__val[in0_idx] ) & recv_in__val[in1_idx] ); - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = ( ( ~first ) & recv_all_val ) & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_PHI_CONST ) ) begin - if ( first ) begin - send_out__msg[1'd0].payload = recv_const__msg.payload; - end - else - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - recv_all_val = ( first & recv_const__val ) | ( ( ~first ) & recv_in__val[in0_idx] ); - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - if ( first ) begin - send_out__msg[1'd0].predicate = recv_const__msg.predicate & reached_vector_factor; - end - else - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/PhiRTL.py:141 - // @update_ff - // def br_start_once(): - // if s.reset | s.clear: - // s.first <<= b1(1) - // if ((s.recv_opt.msg.operation == OPT_PHI_CONST) | (s.recv_opt.msg.operation == OPT_PHI_START)) & s.reached_vector_factor: - // s.first <<= b1(0) - - always_ff @(posedge clk) begin : br_start_once - if ( reset | clear ) begin - first <= 1'd1; - end - if ( ( ( recv_opt__msg.operation == 7'( __const__OPT_PHI_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_PHI_START ) ) ) & reached_vector_factor ) begin - first <= 1'd0; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component CompRTL Definition -// Full name: CompRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/CompRTL.py - -module CompRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_one = { 64'd1, 1'd0, 1'd0, 1'd0 }; - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_read_reg = 3'd4; - localparam logic [1:0] __const__num_outports_at_read_reg = 2'd2; - localparam logic [6:0] __const__OPT_EQ = 7'd14; - localparam logic [6:0] __const__OPT_NE = 7'd45; - localparam logic [6:0] __const__OPT_EQ_CONST = 7'd33; - localparam logic [6:0] __const__OPT_NE_CONST = 7'd46; - localparam logic [6:0] __const__OPT_LT = 7'd60; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/CompRTL.py:48 - // @update - // def read_reg(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= FuInType(0) - // s.in1 @= FuInType(0) - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType( 0 ): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if (s.recv_opt.msg.operation == OPT_EQ) | (s.recv_opt.msg.operation == OPT_NE): - // if (s.recv_opt.msg.operation == OPT_EQ) & \ - // (s.recv_in[s.in0_idx].msg.payload == s.recv_in[s.in1_idx].msg.payload): - // s.send_out[0].msg @= s.const_one - // elif (s.recv_opt.msg.operation == OPT_NE) & \ - // (s.recv_in[s.in0_idx].msg.payload != s.recv_in[s.in1_idx].msg.payload): - // s.send_out[0].msg @= s.const_one - // else: - // s.send_out[0].msg @= s.const_zero - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif (s.recv_opt.msg.operation == OPT_EQ_CONST) | (s.recv_opt.msg.operation == OPT_NE_CONST): - // if (s.recv_opt.msg.operation == OPT_EQ_CONST) & \ - // (s.recv_in[s.in0_idx].msg.payload == s.recv_const.msg.payload): - // s.send_out[0].msg @= s.const_one - // elif (s.recv_opt.msg.operation == OPT_NE_CONST) & \ - // (s.recv_in[s.in0_idx].msg.payload != s.recv_const.msg.payload): - // s.send_out[0].msg @= s.const_one - // else: - // s.send_out[0].msg @= s.const_zero - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // elif s.recv_opt.msg.operation == OPT_LT: - // if s.recv_in[s.in0_idx].msg.payload < s.recv_in[s.in1_idx].msg.payload: - // s.send_out[0].msg @= s.const_one - // else: - // s.send_out[0].msg @= s.const_zero - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : read_reg - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_read_reg ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_read_reg ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_NE ) ) ) begin - if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ ) ) & ( recv_in__msg[in0_idx].payload == recv_in__msg[in1_idx].payload ) ) begin - send_out__msg[1'd0] = const_one; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_NE ) ) & ( recv_in__msg[in0_idx].payload != recv_in__msg[in1_idx].payload ) ) begin - send_out__msg[1'd0] = const_one; - end - else - send_out__msg[1'd0] = const_zero; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ_CONST ) ) | ( recv_opt__msg.operation == 7'( __const__OPT_NE_CONST ) ) ) begin - if ( ( recv_opt__msg.operation == 7'( __const__OPT_EQ_CONST ) ) & ( recv_in__msg[in0_idx].payload == recv_const__msg.payload ) ) begin - send_out__msg[1'd0] = const_one; - end - else if ( ( recv_opt__msg.operation == 7'( __const__OPT_NE_CONST ) ) & ( recv_in__msg[in0_idx].payload != recv_const__msg.payload ) ) begin - send_out__msg[1'd0] = const_one; - end - else - send_out__msg[1'd0] = const_zero; - send_out__msg[1'd0].predicate = recv_in__msg[in0_idx].predicate & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_const__rdy = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_LT ) ) begin - if ( recv_in__msg[in0_idx].payload < recv_in__msg[in1_idx].payload ) begin - send_out__msg[1'd0] = const_one; - end - else - send_out__msg[1'd0] = const_zero; - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_read_reg ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component GrantRTL Definition -// Full name: GrantRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py - -module GrantRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_GRT_PRED = 7'd16; - localparam logic [6:0] __const__OPT_GRT_ALWAYS = 7'd34; - localparam logic [6:0] __const__OPT_GRT_ONCE = 7'd47; - logic [0:0] already_grt_once; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py:46 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= 0 - // s.in1 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= b1(0) - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_GRT_PRED: - // # GRANT_PREDICATE is used to apply (`and` operation) predicate onto a value. - // # The second operand would be used/treated as the predicate condition that - // # is usually coming from a `cmp` operation. - // s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - // # Only updates predicate if the condition is true. Note that we respect - // # condition's (operand_1's) both value and predicate. - // if s.recv_in[s.in1_idx].msg.payload != s.const_zero.payload: - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // elif s.recv_opt.msg.operation == OPT_GRT_ALWAYS: - // # GRANT_ALWAYS is used to apply `true` predicate onto a value regardless - // # its original predicate value. This is usually used for the constant declared - // # in the entry block of a function, and then being used as a bound variable - // # in some streaming loop. Note that if we fuse the constant and the grant_always, - // # we may not need this operation, as the constant is usually preloaded into the - // # ConstQueue with `true` predicate. - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - // # Always updates predicate as true. - // s.send_out[0].msg.predicate @= s.reached_vector_factor - // - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // elif s.recv_opt.msg.operation == OPT_GRT_ONCE: - // # GRANT_ONCE is used to apply `true` predicate onto a value only once. This - // # is usually used for the constant declared in the entry block of a function. - // s.send_out[0].msg @= s.recv_in[s.in0_idx].msg - // # Only updates predicate as true for the first time. - // s.send_out[0].msg.predicate @= s.reached_vector_factor & ~s.already_grt_once - // - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // - // else: - // for j in range( num_outports ): - // s.send_out[j].val @= b1( 0 ) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_PRED ) ) begin - send_out__msg[1'd0].payload = recv_in__msg[in0_idx].payload; - if ( recv_in__msg[in1_idx].payload != 64'd0 ) begin - send_out__msg[1'd0].predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - end - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ALWAYS ) ) begin - send_out__msg[1'd0] = recv_in__msg[in0_idx]; - send_out__msg[1'd0].predicate = reached_vector_factor; - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ONCE ) ) begin - send_out__msg[1'd0] = recv_in__msg[in0_idx]; - send_out__msg[1'd0].predicate = reached_vector_factor & ( ~already_grt_once ); - recv_all_val = recv_in__val[in0_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/GrantRTL.py:123 - // @update_ff - // def record_grt_once(): - // if s.reset | s.clear: - // s.already_grt_once <<= 0 - // else: - // if ~s.already_grt_once & s.send_out[0].val & s.send_out[0].rdy & (s.recv_opt.msg.operation == OPT_GRT_ONCE): - // s.already_grt_once <<= 1 - // else: - // s.already_grt_once <<= s.already_grt_once - - always_ff @(posedge clk) begin : record_grt_once - if ( reset | clear ) begin - already_grt_once <= 1'd0; - end - else if ( ( ( ( ~already_grt_once ) & send_out__val[1'd0] ) & send_out__rdy[1'd0] ) & ( recv_opt__msg.operation == 7'( __const__OPT_GRT_ONCE ) ) ) begin - already_grt_once <= 1'd1; - end - else - already_grt_once <= already_grt_once; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - -endmodule - - -// PyMTL Component MemUnitRTL Definition -// Full name: MemUnitRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py - -module MemUnitRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_LD = 7'd12; - localparam logic [6:0] __const__OPT_ADD_CONST_LD = 7'd81; - localparam logic [6:0] __const__OPT_LD_CONST = 7'd28; - localparam logic [6:0] __const__OPT_STR = 7'd13; - localparam logic [6:0] __const__OPT_STR_CONST = 7'd58; - logic [0:0] already_sent_raddr; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [3:0] recv_in_val_vector; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:81 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register - // s.in0 @= FuInType(0) - // s.in1 @= FuInType(0) - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != 0: - // s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) - // if s.recv_opt.msg.fu_in[1] != 0: - // s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - // - // s.to_mem_waddr.val @= 0 - // s.to_mem_waddr.msg @= AddrType() - // s.to_mem_wdata.val @= 0 - // s.to_mem_wdata.msg @= DataType() - // s.to_mem_raddr.val @= 0 - // s.to_mem_raddr.msg @= AddrType() - // s.from_mem_rdata.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_LD: - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_raddr.rdy - // s.to_mem_raddr.msg @= AddrType(s.recv_in[s.in0_idx].msg.payload[0:AddrType.nbits]) - // # Do not access memory by setting raddr.val=0 if the raddr has predicate=0. - // # Note that this only happends "once" when all the required inputs are arrived. - // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): - // s.to_mem_raddr.val @= 0 - // else: - // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr - // s.from_mem_rdata.rdy @= s.send_out[0].rdy - // # Although we do not access memory when raddr has predicate=0, - // # we still need to simulate that memory returns a fake data with predicate=0, - // # so that the consumer will not block due to the lack of data. - // # Then all initiated iterations can be normally drained. - // # Note that this only happends "after" all the required inputs are arrived. - // # Otherwise, the recv_opt's opcode would be consumed at the wrong timing. - // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): - // s.send_out[0].val @= s.recv_all_val - // s.send_out[0].msg.predicate @= 0 - // s.recv_opt.rdy @= s.send_out[0].rdy - // else: - // s.send_out[0].val @= s.from_mem_rdata.val - // s.send_out[0].msg @= s.from_mem_rdata.msg - // # Predicate of 0 is already handled and returned with fake data. So just - // # use the from_mem_rdata's predicate here. - // s.send_out[0].msg.predicate @= s.from_mem_rdata.msg.predicate & \ - // s.reached_vector_factor - // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val - // - // # ADD_CONST_LD indicates the address is added on a const, then perform load. - // elif s.recv_opt.msg.operation == OPT_ADD_CONST_LD: - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_raddr.rdy - // # It is okay to always set recv_const.rdy=1 here, because the const queue - // # would only proceed once the operation is done executing. - // s.recv_const.rdy @= 1 - // s.to_mem_raddr.msg @= AddrType(s.recv_in[s.in0_idx].msg.payload[0:AddrType.nbits] + - // s.recv_const.msg.payload[0:AddrType.nbits]) - // # Do not access memory by setting raddr.val=0 if the raddr has predicate=0. - // # Note that this only happends "once" when all the required inputs are arrived. - // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): - // s.to_mem_raddr.val @= 0 - // else: - // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr - // s.from_mem_rdata.rdy @= s.send_out[0].rdy - // # Although we do not access memory when raddr has predicate=0, - // # we still need to simulate that memory returns a fake data with predicate=0, - // # so that the consumer will not block due to the lack of data. - // # Then all initiated iterations can be normally drained. - // # Note that this only happends "after" all the required inputs are arrived. - // # Otherwise, the recv_opt's opcode would be consumed at the wrong timing. - // if s.recv_all_val & (s.recv_in[s.in0_idx].msg.predicate == 0): - // s.send_out[0].val @= s.recv_all_val - // s.send_out[0].msg.predicate @= 0 - // s.recv_opt.rdy @= s.send_out[0].rdy - // else: - // s.send_out[0].val @= s.from_mem_rdata.val - // s.send_out[0].msg @= s.from_mem_rdata.msg - // # Predicate of 0 is already handled and returned with fake data. So just - // # use the from_mem_rdata's predicate here. - // s.send_out[0].msg.predicate @= s.from_mem_rdata.msg.predicate & \ - // s.reached_vector_factor - // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val - // - // # LD_CONST indicates the address is a const. - // elif s.recv_opt.msg.operation == OPT_LD_CONST: - // s.recv_all_val @= s.recv_const.val - // # It is okay to always set recv_const.rdy=1 here, because the const queue - // # would only proceed once the operation is done executing. - // s.recv_const.rdy @= 1 - // s.to_mem_raddr.msg @= AddrType(s.recv_const.msg.payload[0:AddrType.nbits]) - // s.to_mem_raddr.val @= s.recv_all_val & ~s.already_sent_raddr - // s.from_mem_rdata.rdy @= s.send_out[0].rdy - // s.send_out[0].val @= s.from_mem_rdata.val - // s.send_out[0].msg @= s.from_mem_rdata.msg - // s.send_out[0].msg.predicate @= s.recv_const.msg.predicate & \ - // s.from_mem_rdata.msg.predicate & \ - // s.reached_vector_factor - // s.recv_opt.rdy @= s.send_out[0].rdy & s.from_mem_rdata.val - // - // elif s.recv_opt.msg.operation == OPT_STR: - // s.recv_all_val @= s.recv_in[s.in0_idx].val & \ - // s.recv_in[s.in1_idx].val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // s.to_mem_waddr.msg @= AddrType(s.recv_in[0].msg.payload[0:AddrType.nbits]) - // s.to_mem_waddr.val @= s.recv_all_val - // s.to_mem_wdata.msg @= s.recv_in[s.in1_idx].msg - // s.to_mem_wdata.msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.reached_vector_factor - // s.to_mem_wdata.val @= s.recv_all_val - // - // # `send_out` is meaningless for store operation. - // s.send_out[0].val @= b1(0) - // - // s.recv_opt.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // - // # STR_CONST indicates the address is a const. - // elif s.recv_opt.msg.operation == OPT_STR_CONST: - // s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_const.val - // s.recv_const.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // # Only needs one input register to indicate the storing data. - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // s.to_mem_waddr.msg @= AddrType(s.recv_const.msg.payload[0:AddrType.nbits]) - // s.to_mem_waddr.val @= s.recv_all_val & \ - // s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate - // s.to_mem_wdata.msg @= s.recv_in[s.in0_idx].msg - // s.to_mem_wdata.msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate & \ - // s.reached_vector_factor - // s.to_mem_wdata.val @= s.recv_all_val & \ - // s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_const.msg.predicate - // - // # `send_out` is meaningless for store operation. - // s.send_out[0].val @= b1(0) - // - // s.recv_opt.rdy @= s.recv_all_val & s.to_mem_waddr.rdy & s.to_mem_wdata.rdy - // - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - end - to_mem_waddr__val = 1'd0; - to_mem_waddr__msg = 7'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - to_mem_raddr__val = 1'd0; - to_mem_raddr__msg = 7'd0; - from_mem_rdata__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_LD ) ) begin - recv_all_val = recv_in__val[in0_idx]; - recv_in__rdy[in0_idx] = recv_all_val & to_mem_raddr__rdy; - to_mem_raddr__msg = 7'( recv_in__msg[in0_idx].payload[6'd6:6'd0] ); - if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin - to_mem_raddr__val = 1'd0; - end - else - to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); - from_mem_rdata__rdy = send_out__rdy[1'd0]; - if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin - send_out__val[1'd0] = recv_all_val; - send_out__msg[1'd0].predicate = 1'd0; - recv_opt__rdy = send_out__rdy[1'd0]; - end - else begin - send_out__val[1'd0] = from_mem_rdata__val; - send_out__msg[1'd0] = from_mem_rdata__msg; - send_out__msg[1'd0].predicate = from_mem_rdata__msg.predicate & reached_vector_factor; - recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; - end - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_ADD_CONST_LD ) ) begin - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - recv_in__rdy[in0_idx] = recv_all_val & to_mem_raddr__rdy; - recv_const__rdy = 1'd1; - to_mem_raddr__msg = 7'( recv_in__msg[in0_idx].payload[6'd6:6'd0] + recv_const__msg.payload[6'd6:6'd0] ); - if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin - to_mem_raddr__val = 1'd0; - end - else - to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); - from_mem_rdata__rdy = send_out__rdy[1'd0]; - if ( recv_all_val & ( recv_in__msg[in0_idx].predicate == 1'd0 ) ) begin - send_out__val[1'd0] = recv_all_val; - send_out__msg[1'd0].predicate = 1'd0; - recv_opt__rdy = send_out__rdy[1'd0]; - end - else begin - send_out__val[1'd0] = from_mem_rdata__val; - send_out__msg[1'd0] = from_mem_rdata__msg; - send_out__msg[1'd0].predicate = from_mem_rdata__msg.predicate & reached_vector_factor; - recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; - end - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_LD_CONST ) ) begin - recv_all_val = recv_const__val; - recv_const__rdy = 1'd1; - to_mem_raddr__msg = 7'( recv_const__msg.payload[6'd6:6'd0] ); - to_mem_raddr__val = recv_all_val & ( ~already_sent_raddr ); - from_mem_rdata__rdy = send_out__rdy[1'd0]; - send_out__val[1'd0] = from_mem_rdata__val; - send_out__msg[1'd0] = from_mem_rdata__msg; - send_out__msg[1'd0].predicate = ( recv_const__msg.predicate & from_mem_rdata__msg.predicate ) & reached_vector_factor; - recv_opt__rdy = send_out__rdy[1'd0] & from_mem_rdata__val; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_STR ) ) begin - recv_all_val = recv_in__val[in0_idx] & recv_in__val[in1_idx]; - recv_in__rdy[in0_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - recv_in__rdy[in1_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - to_mem_waddr__msg = 7'( recv_in__msg[2'd0].payload[6'd6:6'd0] ); - to_mem_waddr__val = recv_all_val; - to_mem_wdata__msg = recv_in__msg[in1_idx]; - to_mem_wdata__msg.predicate = ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & reached_vector_factor; - to_mem_wdata__val = recv_all_val; - send_out__val[1'd0] = 1'd0; - recv_opt__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - end - else if ( recv_opt__msg.operation == 7'( __const__OPT_STR_CONST ) ) begin - recv_all_val = recv_in__val[in0_idx] & recv_const__val; - recv_const__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - recv_in__rdy[in0_idx] = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - to_mem_waddr__msg = 7'( recv_const__msg.payload[6'd6:6'd0] ); - to_mem_waddr__val = ( recv_all_val & recv_in__msg[in0_idx].predicate ) & recv_const__msg.predicate; - to_mem_wdata__msg = recv_in__msg[in0_idx]; - to_mem_wdata__msg.predicate = ( recv_in__msg[in0_idx].predicate & recv_const__msg.predicate ) & reached_vector_factor; - to_mem_wdata__val = ( recv_all_val & recv_in__msg[in0_idx].predicate ) & recv_const__msg.predicate; - send_out__val[1'd0] = 1'd0; - recv_opt__rdy = ( recv_all_val & to_mem_waddr__rdy ) & to_mem_wdata__rdy; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:245 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:269 - // @update_ff - // def update_already_sent_raddr(): - // if s.reset: - // s.already_sent_raddr <<= 0 - // else: - // if ~s.recv_opt.val: - // s.already_sent_raddr <<= 0 - // elif s.from_mem_rdata.val & s.from_mem_rdata.rdy: - // # Clears the flag when the data has returned (s.from_mem_rdata.val) - // # and successfully delivered to the destination (s.from_mem_rdata.rdy). - // s.already_sent_raddr <<= 0 - // elif s.to_mem_raddr.val & \ - // s.to_mem_raddr.rdy & \ - // ~s.already_sent_raddr: - // s.already_sent_raddr <<= 1 - // else: - // s.already_sent_raddr <<= s.already_sent_raddr - - always_ff @(posedge clk) begin : update_already_sent_raddr - if ( reset ) begin - already_sent_raddr <= 1'd0; - end - else if ( ~recv_opt__val ) begin - already_sent_raddr <= 1'd0; - end - else if ( from_mem_rdata__val & from_mem_rdata__rdy ) begin - already_sent_raddr <= 1'd0; - end - else if ( ( to_mem_raddr__val & to_mem_raddr__rdy ) & ( ~already_sent_raddr ) ) begin - already_sent_raddr <= 1'd1; - end - else - already_sent_raddr <= already_sent_raddr; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/MemUnitRTL.py:253 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - assign vector_factor_power = 3'd0; - -endmodule - - -// PyMTL Component SelRTL Definition -// Full name: SelRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py - -module SelRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_SEL = 7'd27; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [2:0] in1; - logic [1:0] in1_idx; - logic [2:0] in2; - logic [1:0] in2_idx; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:88 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register, Selector needs at least 3 inputs - // s.in0 @= FuInType(0) - // s.in1 @= FuInType(0) - // s.in2 @= FuInType(0) - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= s.send_out[0].rdy - // - // for i in range(num_outports): - // s.send_out[i].val @= 0 - // s.send_out[i].msg @= DataType() - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // if s.recv_opt.msg.fu_in[1] != FuInType(0): - // s.in1 @= s.recv_opt.msg.fu_in[1] - FuInType(1) - // if s.recv_opt.msg.fu_in[2] != FuInType(0): - // s.in2 @= s.recv_opt.msg.fu_in[2] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_SEL: - // if s.recv_in[s.in0_idx].msg.payload == s.true.payload: - // s.send_out[0].msg @= s.recv_in[s.in1_idx].msg - // else: - // s.send_out[0].msg @= s.recv_in[s.in2_idx].msg - // s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - // s.recv_in[s.in1_idx].msg.predicate & \ - // s.recv_in[s.in2_idx].msg.predicate & \ - // s.reached_vector_factor - // s.recv_all_val @= s.recv_in[s.in0_idx].val & \ - // s.recv_in[s.in1_idx].val & \ - // s.recv_in[s.in2_idx].val - // s.send_out[0].val @= s.recv_all_val - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_in[s.in2_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - // s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy - // else: - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.recv_opt.rdy @= 0 - // s.recv_in[s.in0_idx].rdy @= 0 - // s.recv_in[s.in1_idx].rdy @= 0 - // s.recv_in[s.in2_idx].rdy @= 0 - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - in1 = 3'd0; - in2 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - recv_const__rdy = 1'd0; - recv_opt__rdy = send_out__rdy[1'd0]; - for ( int unsigned i = 1'd0; i < 2'( __const__num_outports_at_comb_logic ); i += 1'd1 ) begin - send_out__val[1'(i)] = 1'd0; - send_out__msg[1'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd1] != 3'd0 ) begin - in1 = recv_opt__msg.fu_in[2'd1] - 3'd1; - end - if ( recv_opt__msg.fu_in[2'd2] != 3'd0 ) begin - in2 = recv_opt__msg.fu_in[2'd2] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_SEL ) ) begin - if ( recv_in__msg[in0_idx].payload == 64'd1 ) begin - send_out__msg[1'd0] = recv_in__msg[in1_idx]; - end - else - send_out__msg[1'd0] = recv_in__msg[in2_idx]; - send_out__msg[1'd0].predicate = ( ( recv_in__msg[in0_idx].predicate & recv_in__msg[in1_idx].predicate ) & recv_in__msg[in2_idx].predicate ) & reached_vector_factor; - recv_all_val = ( recv_in__val[in0_idx] & recv_in__val[in1_idx] ) & recv_in__val[in2_idx]; - send_out__val[1'd0] = recv_all_val; - recv_in__rdy[in0_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in1_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_in__rdy[in2_idx] = recv_all_val & send_out__rdy[1'd0]; - recv_opt__rdy = recv_all_val & send_out__rdy[1'd0]; - end - else begin - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) - send_out__val[1'(j)] = 1'd0; - recv_opt__rdy = 1'd0; - recv_in__rdy[in0_idx] = 1'd0; - recv_in__rdy[in1_idx] = 1'd0; - recv_in__rdy[in2_idx] = 1'd0; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:78 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= AddrType(0) - // s.to_mem_raddr.msg @= AddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:144 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/SelRTL.py:152 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign in0_idx = in0[1:0]; - assign in1_idx = in1[1:0]; - assign in2_idx = in2[1:0]; - assign vector_factor_power = 3'd0; - -endmodule - - -// PyMTL Component RetRTL Definition -// Full name: RetRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__vector_factor_power_0__data_bitwidth_64 -// At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py - -module RetRTL__45df3c5556ff02e3 -( - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_zero = { 64'd0, 1'd0, 1'd0, 1'd0 }; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [0:0] __const__latency_at_proceed_latency = 1'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_RET = 7'd35; - localparam logic [3:0] __const__CMD_COMPLETE = 4'd14; - logic [0:0] already_done; - logic [2:0] in0; - logic [1:0] in0_idx; - logic [0:0] latency; - logic [0:0] reached_vector_factor; - logic [0:0] recv_all_val; - logic [7:0] vector_factor_counter; - logic [2:0] vector_factor_power; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py:48 - // @update - // def comb_logic(): - // - // s.recv_all_val @= 0 - // # For pick input register. - // s.in0 @= 0 - // for i in range(num_inports): - // s.recv_in[i].rdy @= b1(0) - // - // for j in range(num_outports): - // s.send_out[j].val @= 0 - // s.send_out[j].msg @= DataType() - // - // s.send_to_ctrl_mem.val @= 0 - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(0, 0, 0, 0, 0) - // s.recv_from_ctrl_mem.rdy @= 0 - // - // s.recv_const.rdy @= 0 - // s.recv_opt.rdy @= 0 - // - // if s.recv_opt.val: - // if s.recv_opt.msg.fu_in[0] != FuInType(0): - // s.in0 @= s.recv_opt.msg.fu_in[0] - FuInType(1) - // - // if s.recv_opt.val: - // if s.recv_opt.msg.operation == OPT_RET: - // s.recv_all_val @= s.recv_in[s.in0_idx].val - // # Value to be returned is usually granted with a predicate: - // # https://github.com/coredac/dataflow/blob/b9ffc097d67429017323e3d50d3984655f756b91/test/neura/ctrl/branch_for.mlir#L150. - // if s.already_done: - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val - // s.recv_opt.rdy @= s.recv_all_val - // elif s.recv_in[s.in0_idx].msg.predicate: - // # Only when the predicate is true, the value will be sent back to CPU. - // s.send_to_ctrl_mem.val @= s.recv_all_val & s.reached_vector_factor - // # s.send_to_ctrl_mem.msg @= s.recv_in[s.in0_idx].msg - // s.send_to_ctrl_mem.msg @= s.CgraPayloadType(CMD_COMPLETE, s.recv_in[s.in0_idx].msg, 0, s.recv_opt.msg, 0) - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.reached_vector_factor & s.send_to_ctrl_mem.rdy - // s.recv_opt.rdy @= s.recv_all_val & s.reached_vector_factor & s.send_to_ctrl_mem.rdy - // else: - // s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.reached_vector_factor - // s.recv_opt.rdy @= s.recv_all_val & s.reached_vector_factor - - always_comb begin : comb_logic - recv_all_val = 1'd0; - in0 = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_comb_logic ); i += 1'd1 ) - recv_in__rdy[2'(i)] = 1'd0; - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin - send_out__val[1'(j)] = 1'd0; - send_out__msg[1'(j)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - send_to_ctrl_mem__val = 1'd0; - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - recv_from_ctrl_mem__rdy = 1'd0; - recv_const__rdy = 1'd0; - recv_opt__rdy = 1'd0; - if ( recv_opt__val ) begin - if ( recv_opt__msg.fu_in[2'd0] != 3'd0 ) begin - in0 = recv_opt__msg.fu_in[2'd0] - 3'd1; - end - end - if ( recv_opt__val ) begin - if ( recv_opt__msg.operation == 7'( __const__OPT_RET ) ) begin - recv_all_val = recv_in__val[in0_idx]; - if ( already_done ) begin - recv_in__rdy[in0_idx] = recv_all_val; - recv_opt__rdy = recv_all_val; - end - else if ( recv_in__msg[in0_idx].predicate ) begin - send_to_ctrl_mem__val = recv_all_val & reached_vector_factor; - send_to_ctrl_mem__msg = { 5'( __const__CMD_COMPLETE ), recv_in__msg[in0_idx], 7'd0, recv_opt__msg, 4'd0 }; - recv_in__rdy[in0_idx] = ( recv_all_val & reached_vector_factor ) & send_to_ctrl_mem__rdy; - recv_opt__rdy = ( recv_all_val & reached_vector_factor ) & send_to_ctrl_mem__rdy; - end - else begin - recv_in__rdy[in0_idx] = recv_all_val & reached_vector_factor; - recv_opt__rdy = recv_all_val & reached_vector_factor; - end - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:70 - // @update - // def update_mem(): - // s.to_mem_waddr.val @= b1(0) - // s.to_mem_wdata.val @= b1(0) - // s.to_mem_wdata.msg @= s.const_zero - // s.to_mem_waddr.msg @= DataAddrType(0) - // s.to_mem_raddr.msg @= DataAddrType(0) - // s.to_mem_raddr.val @= b1(0) - // s.from_mem_rdata.rdy @= b1(0) - - always_comb begin : update_mem - to_mem_waddr__val = 1'd0; - to_mem_wdata__val = 1'd0; - to_mem_wdata__msg = const_zero; - to_mem_waddr__msg = 7'd0; - to_mem_raddr__msg = 7'd0; - to_mem_raddr__val = 1'd0; - from_mem_rdata__rdy = 1'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:89 - // @update - // def update_reached_vector_factor(): - // s.reached_vector_factor @= 0 - // if s.recv_opt.val & (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) >= \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.reached_vector_factor @= 1 - - always_comb begin : update_reached_vector_factor - reached_vector_factor = 1'd0; - if ( recv_opt__val & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) >= ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - reached_vector_factor = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:80 - // @update_ff - // def proceed_latency(): - // if s.recv_opt.msg.operation == OPT_START: - // s.latency <<= LatencyType(0) - // elif s.latency == latency - 1: - // s.latency <<= LatencyType(0) - // else: - // s.latency <<= s.latency + LatencyType(1) - - always_ff @(posedge clk) begin : proceed_latency - if ( recv_opt__msg.operation == 7'( __const__OPT_START ) ) begin - latency <= 1'd0; - end - else if ( latency == ( 1'( __const__latency_at_proceed_latency ) - 1'd1 ) ) begin - latency <= 1'd0; - end - else - latency <= latency + 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/single/RetRTL.py:91 - // @update_ff - // def update_already_done(): - // if s.reset | s.clear: - // s.already_done <<= 0 - // else: - // if s.recv_opt.val & \ - // (s.recv_opt.msg.operation == OPT_RET) & \ - // ~s.already_done & \ - // s.recv_all_val & \ - // s.send_to_ctrl_mem.val & \ - // s.send_to_ctrl_mem.rdy: - // s.already_done <<= 1 - // else: - // s.already_done <<= s.already_done - - always_ff @(posedge clk) begin : update_already_done - if ( reset | clear ) begin - already_done <= 1'd0; - end - else if ( ( ( ( ( recv_opt__val & ( recv_opt__msg.operation == 7'( __const__OPT_RET ) ) ) & ( ~already_done ) ) & recv_all_val ) & send_to_ctrl_mem__val ) & send_to_ctrl_mem__rdy ) begin - already_done <= 1'd1; - end - else - already_done <= already_done; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/basic/Fu.py:97 - // @update_ff - // def update_vector_factor_counter(): - // if s.reset: - // s.vector_factor_counter <<= 0 - // else: - // if s.recv_opt.val: - // if s.recv_opt.msg.is_last_ctrl & \ - // (s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, VectorFactorType)) < \ - // (VectorFactorType(1) << zext(s.recv_opt.msg.vector_factor_power, VectorFactorType))): - // s.vector_factor_counter <<= s.vector_factor_counter + \ - // (VectorFactorType(1) << zext(s.vector_factor_power, \ - // VectorFactorType)) - // elif s.recv_opt.msg.is_last_ctrl & s.reached_vector_factor: - // s.vector_factor_counter <<= 0 - - always_ff @(posedge clk) begin : update_vector_factor_counter - if ( reset ) begin - vector_factor_counter <= 8'd0; - end - else if ( recv_opt__val ) begin - if ( recv_opt__msg.is_last_ctrl & ( ( vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ) ) < ( 8'd1 << { { 5 { 1'b0 } }, recv_opt__msg.vector_factor_power } ) ) ) begin - vector_factor_counter <= vector_factor_counter + ( 8'd1 << { { 5 { 1'b0 } }, vector_factor_power } ); - end - else if ( recv_opt__msg.is_last_ctrl & reached_vector_factor ) begin - vector_factor_counter <= 8'd0; - end - end - end - - assign vector_factor_power = 3'd0; - assign in0_idx = in0[1:0]; - -endmodule - - -// PyMTL Component FlexibleFuRTL Definition -// Full name: FlexibleFuRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_2__data_mem_size_128__ctrl_mem_size_16__num_tiles_16__FuList_[, , , , , , , , , , , , , , ]__exec_lantency_{} -// At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py - -module FlexibleFuRTL__07217382918d0fc2 -( - input logic [0:0] clear [0:14], - input logic [0:0] clk , - input logic [2:0] prologue_count_inport , - input logic [0:0] reset , - input logic [4:0] tile_id , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg [0:14] , - output logic [0:0] from_mem_rdata__rdy [0:14] , - input logic [0:0] from_mem_rdata__val [0:14] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_const__msg , - output logic [0:0] recv_const__rdy , - input logic [0:0] recv_const__val , - input MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a recv_from_ctrl_mem__msg , - output logic [0:0] recv_from_ctrl_mem__rdy , - input logic [0:0] recv_from_ctrl_mem__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_in__msg [0:3] , - output logic [0:0] recv_in__rdy [0:3] , - input logic [0:0] recv_in__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_out__msg [0:1] , - input logic [0:0] send_out__rdy [0:1] , - output logic [0:0] send_out__val [0:1] , - output MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a send_to_ctrl_mem__msg , - input logic [0:0] send_to_ctrl_mem__rdy , - output logic [0:0] send_to_ctrl_mem__val , - output logic [6:0] to_mem_raddr__msg [0:14] , - input logic [0:0] to_mem_raddr__rdy [0:14] , - output logic [0:0] to_mem_raddr__val [0:14] , - output logic [6:0] to_mem_waddr__msg [0:14] , - input logic [0:0] to_mem_waddr__rdy [0:14] , - output logic [0:0] to_mem_waddr__val [0:14] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg [0:14] , - input logic [0:0] to_mem_wdata__rdy [0:14] , - output logic [0:0] to_mem_wdata__val [0:14] -); - localparam logic [1:0] __const__num_outports_at_comb_logic = 2'd2; - localparam logic [6:0] __const__OPT_NAH = 7'd1; - localparam logic [2:0] __const__num_inports_at_comb_logic = 3'd4; - logic [14:0] fu_recv_const_rdy_vector; - logic [14:0] fu_recv_in_rdy_vector [0:3]; - logic [14:0] fu_recv_opt_rdy_vector; - logic [14:0] recv_from_controller_rdy_vector; - //------------------------------------------------------------- - // Component fu[0:14] - //------------------------------------------------------------- - - logic [0:0] fu__clear [0:14]; - logic [0:0] fu__clk [0:14]; - logic [0:0] fu__reset [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__from_mem_rdata__msg [0:14]; - logic [0:0] fu__from_mem_rdata__rdy [0:14]; - logic [0:0] fu__from_mem_rdata__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__recv_const__msg [0:14]; - logic [0:0] fu__recv_const__rdy [0:14]; - logic [0:0] fu__recv_const__val [0:14]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a fu__recv_from_ctrl_mem__msg [0:14]; - logic [0:0] fu__recv_from_ctrl_mem__rdy [0:14]; - logic [0:0] fu__recv_from_ctrl_mem__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__recv_in__msg [0:14][0:3]; - logic [0:0] fu__recv_in__rdy [0:14][0:3]; - logic [0:0] fu__recv_in__val [0:14][0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 fu__recv_opt__msg [0:14]; - logic [0:0] fu__recv_opt__rdy [0:14]; - logic [0:0] fu__recv_opt__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__send_out__msg [0:14][0:1]; - logic [0:0] fu__send_out__rdy [0:14][0:1]; - logic [0:0] fu__send_out__val [0:14][0:1]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a fu__send_to_ctrl_mem__msg [0:14]; - logic [0:0] fu__send_to_ctrl_mem__rdy [0:14]; - logic [0:0] fu__send_to_ctrl_mem__val [0:14]; - logic [6:0] fu__to_mem_raddr__msg [0:14]; - logic [0:0] fu__to_mem_raddr__rdy [0:14]; - logic [0:0] fu__to_mem_raddr__val [0:14]; - logic [6:0] fu__to_mem_waddr__msg [0:14]; - logic [0:0] fu__to_mem_waddr__rdy [0:14]; - logic [0:0] fu__to_mem_waddr__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu__to_mem_wdata__msg [0:14]; - logic [0:0] fu__to_mem_wdata__rdy [0:14]; - logic [0:0] fu__to_mem_wdata__val [0:14]; - - AdderRTL__45df3c5556ff02e3 fu__0 - ( - .clear( fu__clear[0] ), - .clk( fu__clk[0] ), - .reset( fu__reset[0] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[0] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[0] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[0] ), - .recv_const__msg( fu__recv_const__msg[0] ), - .recv_const__rdy( fu__recv_const__rdy[0] ), - .recv_const__val( fu__recv_const__val[0] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[0] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[0] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[0] ), - .recv_in__msg( fu__recv_in__msg[0] ), - .recv_in__rdy( fu__recv_in__rdy[0] ), - .recv_in__val( fu__recv_in__val[0] ), - .recv_opt__msg( fu__recv_opt__msg[0] ), - .recv_opt__rdy( fu__recv_opt__rdy[0] ), - .recv_opt__val( fu__recv_opt__val[0] ), - .send_out__msg( fu__send_out__msg[0] ), - .send_out__rdy( fu__send_out__rdy[0] ), - .send_out__val( fu__send_out__val[0] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[0] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[0] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[0] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[0] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[0] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[0] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[0] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[0] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[0] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[0] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[0] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[0] ) - ); - - MulRTL__45df3c5556ff02e3 fu__1 - ( - .clear( fu__clear[1] ), - .clk( fu__clk[1] ), - .reset( fu__reset[1] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[1] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[1] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[1] ), - .recv_const__msg( fu__recv_const__msg[1] ), - .recv_const__rdy( fu__recv_const__rdy[1] ), - .recv_const__val( fu__recv_const__val[1] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[1] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[1] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[1] ), - .recv_in__msg( fu__recv_in__msg[1] ), - .recv_in__rdy( fu__recv_in__rdy[1] ), - .recv_in__val( fu__recv_in__val[1] ), - .recv_opt__msg( fu__recv_opt__msg[1] ), - .recv_opt__rdy( fu__recv_opt__rdy[1] ), - .recv_opt__val( fu__recv_opt__val[1] ), - .send_out__msg( fu__send_out__msg[1] ), - .send_out__rdy( fu__send_out__rdy[1] ), - .send_out__val( fu__send_out__val[1] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[1] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[1] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[1] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[1] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[1] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[1] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[1] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[1] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[1] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[1] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[1] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[1] ) - ); - - LogicRTL__45df3c5556ff02e3 fu__2 - ( - .clear( fu__clear[2] ), - .clk( fu__clk[2] ), - .reset( fu__reset[2] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[2] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[2] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[2] ), - .recv_const__msg( fu__recv_const__msg[2] ), - .recv_const__rdy( fu__recv_const__rdy[2] ), - .recv_const__val( fu__recv_const__val[2] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[2] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[2] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[2] ), - .recv_in__msg( fu__recv_in__msg[2] ), - .recv_in__rdy( fu__recv_in__rdy[2] ), - .recv_in__val( fu__recv_in__val[2] ), - .recv_opt__msg( fu__recv_opt__msg[2] ), - .recv_opt__rdy( fu__recv_opt__rdy[2] ), - .recv_opt__val( fu__recv_opt__val[2] ), - .send_out__msg( fu__send_out__msg[2] ), - .send_out__rdy( fu__send_out__rdy[2] ), - .send_out__val( fu__send_out__val[2] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[2] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[2] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[2] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[2] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[2] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[2] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[2] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[2] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[2] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[2] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[2] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[2] ) - ); - - ShifterRTL__45df3c5556ff02e3 fu__3 - ( - .clear( fu__clear[3] ), - .clk( fu__clk[3] ), - .reset( fu__reset[3] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[3] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[3] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[3] ), - .recv_const__msg( fu__recv_const__msg[3] ), - .recv_const__rdy( fu__recv_const__rdy[3] ), - .recv_const__val( fu__recv_const__val[3] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[3] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[3] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[3] ), - .recv_in__msg( fu__recv_in__msg[3] ), - .recv_in__rdy( fu__recv_in__rdy[3] ), - .recv_in__val( fu__recv_in__val[3] ), - .recv_opt__msg( fu__recv_opt__msg[3] ), - .recv_opt__rdy( fu__recv_opt__rdy[3] ), - .recv_opt__val( fu__recv_opt__val[3] ), - .send_out__msg( fu__send_out__msg[3] ), - .send_out__rdy( fu__send_out__rdy[3] ), - .send_out__val( fu__send_out__val[3] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[3] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[3] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[3] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[3] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[3] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[3] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[3] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[3] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[3] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[3] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[3] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[3] ) - ); - - PhiRTL__45df3c5556ff02e3 fu__4 - ( - .clear( fu__clear[4] ), - .clk( fu__clk[4] ), - .reset( fu__reset[4] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[4] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[4] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[4] ), - .recv_const__msg( fu__recv_const__msg[4] ), - .recv_const__rdy( fu__recv_const__rdy[4] ), - .recv_const__val( fu__recv_const__val[4] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[4] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[4] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[4] ), - .recv_in__msg( fu__recv_in__msg[4] ), - .recv_in__rdy( fu__recv_in__rdy[4] ), - .recv_in__val( fu__recv_in__val[4] ), - .recv_opt__msg( fu__recv_opt__msg[4] ), - .recv_opt__rdy( fu__recv_opt__rdy[4] ), - .recv_opt__val( fu__recv_opt__val[4] ), - .send_out__msg( fu__send_out__msg[4] ), - .send_out__rdy( fu__send_out__rdy[4] ), - .send_out__val( fu__send_out__val[4] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[4] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[4] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[4] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[4] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[4] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[4] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[4] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[4] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[4] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[4] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[4] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[4] ) - ); - - CompRTL__45df3c5556ff02e3 fu__5 - ( - .clear( fu__clear[5] ), - .clk( fu__clk[5] ), - .reset( fu__reset[5] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[5] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[5] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[5] ), - .recv_const__msg( fu__recv_const__msg[5] ), - .recv_const__rdy( fu__recv_const__rdy[5] ), - .recv_const__val( fu__recv_const__val[5] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[5] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[5] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[5] ), - .recv_in__msg( fu__recv_in__msg[5] ), - .recv_in__rdy( fu__recv_in__rdy[5] ), - .recv_in__val( fu__recv_in__val[5] ), - .recv_opt__msg( fu__recv_opt__msg[5] ), - .recv_opt__rdy( fu__recv_opt__rdy[5] ), - .recv_opt__val( fu__recv_opt__val[5] ), - .send_out__msg( fu__send_out__msg[5] ), - .send_out__rdy( fu__send_out__rdy[5] ), - .send_out__val( fu__send_out__val[5] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[5] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[5] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[5] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[5] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[5] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[5] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[5] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[5] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[5] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[5] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[5] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[5] ) - ); - - GrantRTL__45df3c5556ff02e3 fu__6 - ( - .clear( fu__clear[6] ), - .clk( fu__clk[6] ), - .reset( fu__reset[6] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[6] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[6] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[6] ), - .recv_const__msg( fu__recv_const__msg[6] ), - .recv_const__rdy( fu__recv_const__rdy[6] ), - .recv_const__val( fu__recv_const__val[6] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[6] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[6] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[6] ), - .recv_in__msg( fu__recv_in__msg[6] ), - .recv_in__rdy( fu__recv_in__rdy[6] ), - .recv_in__val( fu__recv_in__val[6] ), - .recv_opt__msg( fu__recv_opt__msg[6] ), - .recv_opt__rdy( fu__recv_opt__rdy[6] ), - .recv_opt__val( fu__recv_opt__val[6] ), - .send_out__msg( fu__send_out__msg[6] ), - .send_out__rdy( fu__send_out__rdy[6] ), - .send_out__val( fu__send_out__val[6] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[6] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[6] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[6] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[6] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[6] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[6] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[6] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[6] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[6] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[6] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[6] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[6] ) - ); - - MemUnitRTL__45df3c5556ff02e3 fu__7 - ( - .clear( fu__clear[7] ), - .clk( fu__clk[7] ), - .reset( fu__reset[7] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[7] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[7] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[7] ), - .recv_const__msg( fu__recv_const__msg[7] ), - .recv_const__rdy( fu__recv_const__rdy[7] ), - .recv_const__val( fu__recv_const__val[7] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[7] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[7] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[7] ), - .recv_in__msg( fu__recv_in__msg[7] ), - .recv_in__rdy( fu__recv_in__rdy[7] ), - .recv_in__val( fu__recv_in__val[7] ), - .recv_opt__msg( fu__recv_opt__msg[7] ), - .recv_opt__rdy( fu__recv_opt__rdy[7] ), - .recv_opt__val( fu__recv_opt__val[7] ), - .send_out__msg( fu__send_out__msg[7] ), - .send_out__rdy( fu__send_out__rdy[7] ), - .send_out__val( fu__send_out__val[7] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[7] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[7] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[7] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[7] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[7] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[7] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[7] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[7] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[7] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[7] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[7] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[7] ) - ); - - SelRTL__45df3c5556ff02e3 fu__8 - ( - .clear( fu__clear[8] ), - .clk( fu__clk[8] ), - .reset( fu__reset[8] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[8] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[8] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[8] ), - .recv_const__msg( fu__recv_const__msg[8] ), - .recv_const__rdy( fu__recv_const__rdy[8] ), - .recv_const__val( fu__recv_const__val[8] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[8] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[8] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[8] ), - .recv_in__msg( fu__recv_in__msg[8] ), - .recv_in__rdy( fu__recv_in__rdy[8] ), - .recv_in__val( fu__recv_in__val[8] ), - .recv_opt__msg( fu__recv_opt__msg[8] ), - .recv_opt__rdy( fu__recv_opt__rdy[8] ), - .recv_opt__val( fu__recv_opt__val[8] ), - .send_out__msg( fu__send_out__msg[8] ), - .send_out__rdy( fu__send_out__rdy[8] ), - .send_out__val( fu__send_out__val[8] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[8] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[8] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[8] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[8] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[8] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[8] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[8] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[8] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[8] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[8] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[8] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[8] ) - ); - - RetRTL__45df3c5556ff02e3 fu__9 - ( - .clear( fu__clear[9] ), - .clk( fu__clk[9] ), - .reset( fu__reset[9] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[9] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[9] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[9] ), - .recv_const__msg( fu__recv_const__msg[9] ), - .recv_const__rdy( fu__recv_const__rdy[9] ), - .recv_const__val( fu__recv_const__val[9] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[9] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[9] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[9] ), - .recv_in__msg( fu__recv_in__msg[9] ), - .recv_in__rdy( fu__recv_in__rdy[9] ), - .recv_in__val( fu__recv_in__val[9] ), - .recv_opt__msg( fu__recv_opt__msg[9] ), - .recv_opt__rdy( fu__recv_opt__rdy[9] ), - .recv_opt__val( fu__recv_opt__val[9] ), - .send_out__msg( fu__send_out__msg[9] ), - .send_out__rdy( fu__send_out__rdy[9] ), - .send_out__val( fu__send_out__val[9] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[9] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[9] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[9] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[9] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[9] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[9] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[9] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[9] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[9] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[9] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[9] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[9] ) - ); - - SeqMulAdderRTL__b741248a3a1dca5f fu__10 - ( - .clear( fu__clear[10] ), - .clk( fu__clk[10] ), - .reset( fu__reset[10] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[10] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[10] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[10] ), - .recv_const__msg( fu__recv_const__msg[10] ), - .recv_const__rdy( fu__recv_const__rdy[10] ), - .recv_const__val( fu__recv_const__val[10] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[10] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[10] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[10] ), - .recv_in__msg( fu__recv_in__msg[10] ), - .recv_in__rdy( fu__recv_in__rdy[10] ), - .recv_in__val( fu__recv_in__val[10] ), - .recv_opt__msg( fu__recv_opt__msg[10] ), - .recv_opt__rdy( fu__recv_opt__rdy[10] ), - .recv_opt__val( fu__recv_opt__val[10] ), - .send_out__msg( fu__send_out__msg[10] ), - .send_out__rdy( fu__send_out__rdy[10] ), - .send_out__val( fu__send_out__val[10] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[10] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[10] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[10] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[10] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[10] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[10] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[10] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[10] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[10] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[10] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[10] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[10] ) - ); - - VectorMulComboRTL__e2d25a29972e2033 fu__11 - ( - .clear( fu__clear[11] ), - .clk( fu__clk[11] ), - .reset( fu__reset[11] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[11] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[11] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[11] ), - .recv_const__msg( fu__recv_const__msg[11] ), - .recv_const__rdy( fu__recv_const__rdy[11] ), - .recv_const__val( fu__recv_const__val[11] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[11] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[11] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[11] ), - .recv_in__msg( fu__recv_in__msg[11] ), - .recv_in__rdy( fu__recv_in__rdy[11] ), - .recv_in__val( fu__recv_in__val[11] ), - .recv_opt__msg( fu__recv_opt__msg[11] ), - .recv_opt__rdy( fu__recv_opt__rdy[11] ), - .recv_opt__val( fu__recv_opt__val[11] ), - .send_out__msg( fu__send_out__msg[11] ), - .send_out__rdy( fu__send_out__rdy[11] ), - .send_out__val( fu__send_out__val[11] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[11] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[11] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[11] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[11] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[11] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[11] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[11] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[11] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[11] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[11] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[11] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[11] ) - ); - - VectorAdderComboRTL__e2d25a29972e2033 fu__12 - ( - .clear( fu__clear[12] ), - .clk( fu__clk[12] ), - .reset( fu__reset[12] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[12] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[12] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[12] ), - .recv_const__msg( fu__recv_const__msg[12] ), - .recv_const__rdy( fu__recv_const__rdy[12] ), - .recv_const__val( fu__recv_const__val[12] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[12] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[12] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[12] ), - .recv_in__msg( fu__recv_in__msg[12] ), - .recv_in__rdy( fu__recv_in__rdy[12] ), - .recv_in__val( fu__recv_in__val[12] ), - .recv_opt__msg( fu__recv_opt__msg[12] ), - .recv_opt__rdy( fu__recv_opt__rdy[12] ), - .recv_opt__val( fu__recv_opt__val[12] ), - .send_out__msg( fu__send_out__msg[12] ), - .send_out__rdy( fu__send_out__rdy[12] ), - .send_out__val( fu__send_out__val[12] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[12] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[12] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[12] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[12] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[12] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[12] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[12] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[12] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[12] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[12] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[12] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[12] ) - ); - - VectorAllReduceRTL__e2d25a29972e2033 fu__13 - ( - .clear( fu__clear[13] ), - .clk( fu__clk[13] ), - .reset( fu__reset[13] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[13] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[13] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[13] ), - .recv_const__msg( fu__recv_const__msg[13] ), - .recv_const__rdy( fu__recv_const__rdy[13] ), - .recv_const__val( fu__recv_const__val[13] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[13] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[13] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[13] ), - .recv_in__msg( fu__recv_in__msg[13] ), - .recv_in__rdy( fu__recv_in__rdy[13] ), - .recv_in__val( fu__recv_in__val[13] ), - .recv_opt__msg( fu__recv_opt__msg[13] ), - .recv_opt__rdy( fu__recv_opt__rdy[13] ), - .recv_opt__val( fu__recv_opt__val[13] ), - .send_out__msg( fu__send_out__msg[13] ), - .send_out__rdy( fu__send_out__rdy[13] ), - .send_out__val( fu__send_out__val[13] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[13] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[13] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[13] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[13] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[13] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[13] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[13] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[13] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[13] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[13] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[13] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[13] ) - ); - - NahRTL__45df3c5556ff02e3 fu__14 - ( - .clear( fu__clear[14] ), - .clk( fu__clk[14] ), - .reset( fu__reset[14] ), - .from_mem_rdata__msg( fu__from_mem_rdata__msg[14] ), - .from_mem_rdata__rdy( fu__from_mem_rdata__rdy[14] ), - .from_mem_rdata__val( fu__from_mem_rdata__val[14] ), - .recv_const__msg( fu__recv_const__msg[14] ), - .recv_const__rdy( fu__recv_const__rdy[14] ), - .recv_const__val( fu__recv_const__val[14] ), - .recv_from_ctrl_mem__msg( fu__recv_from_ctrl_mem__msg[14] ), - .recv_from_ctrl_mem__rdy( fu__recv_from_ctrl_mem__rdy[14] ), - .recv_from_ctrl_mem__val( fu__recv_from_ctrl_mem__val[14] ), - .recv_in__msg( fu__recv_in__msg[14] ), - .recv_in__rdy( fu__recv_in__rdy[14] ), - .recv_in__val( fu__recv_in__val[14] ), - .recv_opt__msg( fu__recv_opt__msg[14] ), - .recv_opt__rdy( fu__recv_opt__rdy[14] ), - .recv_opt__val( fu__recv_opt__val[14] ), - .send_out__msg( fu__send_out__msg[14] ), - .send_out__rdy( fu__send_out__rdy[14] ), - .send_out__val( fu__send_out__val[14] ), - .send_to_ctrl_mem__msg( fu__send_to_ctrl_mem__msg[14] ), - .send_to_ctrl_mem__rdy( fu__send_to_ctrl_mem__rdy[14] ), - .send_to_ctrl_mem__val( fu__send_to_ctrl_mem__val[14] ), - .to_mem_raddr__msg( fu__to_mem_raddr__msg[14] ), - .to_mem_raddr__rdy( fu__to_mem_raddr__rdy[14] ), - .to_mem_raddr__val( fu__to_mem_raddr__val[14] ), - .to_mem_waddr__msg( fu__to_mem_waddr__msg[14] ), - .to_mem_waddr__rdy( fu__to_mem_waddr__rdy[14] ), - .to_mem_waddr__val( fu__to_mem_waddr__val[14] ), - .to_mem_wdata__msg( fu__to_mem_wdata__msg[14] ), - .to_mem_wdata__rdy( fu__to_mem_wdata__rdy[14] ), - .to_mem_wdata__val( fu__to_mem_wdata__val[14] ) - ); - - //------------------------------------------------------------- - // End of component fu[0:14] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py:107 - // @update - // def comb_logic(): - // for j in range(num_outports): - // s.send_out[j].val @= b1(0) - // s.send_out[j].msg @= DataType() - // - // for i in range(s.fu_list_size): - // # const connection. - // s.fu[i].recv_const.msg @= s.recv_const.msg - // s.fu[i].recv_const.val @= s.recv_const.val - // s.fu_recv_const_rdy_vector[i] @= s.fu[i].recv_const.rdy - // - // # opt connection. - // s.fu[i].recv_opt.msg @= s.recv_opt.msg - // # Sets each FU's op code as NAH when prologue execution is not completed. - // # As they are supposed to do nothing during that prologue cycles. - // if s.prologue_count_inport != 0: - // s.fu[i].recv_opt.msg.operation @= OPT_NAH - // s.fu[i].recv_opt.val @= s.recv_opt.val - // s.fu_recv_opt_rdy_vector[i] @= s.fu[i].recv_opt.rdy - // - // # send_out connection. - // for j in range(num_outports): - // # FIXME: need reduce_or here: https://github.com/tancheng/VectorCGRA/issues/51. - // if s.fu[i].send_out[j].val: - // s.send_out[j].msg @= s.fu[i].send_out[j].msg - // s.send_out[j].val @= s.fu[i].send_out[j].val - // s.fu[i].send_out[j].rdy @= s.send_out[j].rdy - // - // s.recv_const.rdy @= reduce_or(s.fu_recv_const_rdy_vector) - // # Operation (especially mem access) won't perform more than once, because once the - // # operation is performance (i.e., the recv_opt.rdy would be set), the `element_done` - // # register would be set and be respected. - // s.recv_opt.rdy @= reduce_or(s.fu_recv_opt_rdy_vector) | (s.prologue_count_inport != 0) - // - // for j in range(num_inports): - // s.recv_in[j].rdy @= b1(0) - // - // # recv_in connection. - // for port in range(num_inports): - // for i in range(s.fu_list_size): - // s.fu[i].recv_in[port].msg @= s.recv_in[port].msg - // s.fu[i].recv_in[port].val @= s.recv_in[port].val - // # s.recv_in[j].rdy @= s.fu[i].recv_in[j].rdy | s.recv_in[j].rdy - // s.fu_recv_in_rdy_vector[port][i] @= s.fu[i].recv_in[port].rdy - // s.recv_in[port].rdy @= reduce_or(s.fu_recv_in_rdy_vector[port]) - - always_comb begin : comb_logic - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin - send_out__val[1'(j)] = 1'd0; - send_out__msg[1'(j)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin - fu__recv_const__msg[4'(i)] = recv_const__msg; - fu__recv_const__val[4'(i)] = recv_const__val; - fu_recv_const_rdy_vector[4'(i)] = fu__recv_const__rdy[4'(i)]; - fu__recv_opt__msg[4'(i)] = recv_opt__msg; - if ( prologue_count_inport != 3'd0 ) begin - fu__recv_opt__msg[4'(i)].operation = 7'( __const__OPT_NAH ); - end - fu__recv_opt__val[4'(i)] = recv_opt__val; - fu_recv_opt_rdy_vector[4'(i)] = fu__recv_opt__rdy[4'(i)]; - for ( int unsigned j = 1'd0; j < 2'( __const__num_outports_at_comb_logic ); j += 1'd1 ) begin - if ( fu__send_out__val[4'(i)][1'(j)] ) begin - send_out__msg[1'(j)] = fu__send_out__msg[4'(i)][1'(j)]; - send_out__val[1'(j)] = fu__send_out__val[4'(i)][1'(j)]; - end - fu__send_out__rdy[4'(i)][1'(j)] = send_out__rdy[1'(j)]; - end - end - recv_const__rdy = ( | fu_recv_const_rdy_vector ); - recv_opt__rdy = ( | fu_recv_opt_rdy_vector ) | ( prologue_count_inport != 3'd0 ); - for ( int unsigned j = 1'd0; j < 3'( __const__num_inports_at_comb_logic ); j += 1'd1 ) - recv_in__rdy[2'(j)] = 1'd0; - for ( int unsigned port = 1'd0; port < 3'( __const__num_inports_at_comb_logic ); port += 1'd1 ) begin - for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin - fu__recv_in__msg[4'(i)][2'(port)] = recv_in__msg[2'(port)]; - fu__recv_in__val[4'(i)][2'(port)] = recv_in__val[2'(port)]; - fu_recv_in_rdy_vector[2'(port)][4'(i)] = fu__recv_in__rdy[4'(i)][2'(port)]; - end - recv_in__rdy[2'(port)] = ( | fu_recv_in_rdy_vector[2'(port)] ); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/fu/flexible/FlexibleFuRTL.py:90 - // @update - // def connect_to_controller(): - // for i in range(s.fu_list_size): - // # const connection. - // s.fu[i].recv_from_ctrl_mem.msg @= s.recv_from_ctrl_mem.msg - // s.fu[i].recv_from_ctrl_mem.val @= s.recv_from_ctrl_mem.val - // s.recv_from_controller_rdy_vector[i] @= s.fu[i].recv_from_ctrl_mem.rdy - // s.recv_from_ctrl_mem.rdy @= reduce_or(s.recv_from_controller_rdy_vector) - // - // s.send_to_ctrl_mem.msg @= CgraPayloadType(0, 0, 0, 0, 0) - // s.send_to_ctrl_mem.val @= 0 - // for i in range(s.fu_list_size): - // if s.fu[i].send_to_ctrl_mem.val: - // s.send_to_ctrl_mem.msg @= s.fu[i].send_to_ctrl_mem.msg - // s.send_to_ctrl_mem.val @= s.fu[i].send_to_ctrl_mem.val - // s.fu[i].send_to_ctrl_mem.rdy @= s.send_to_ctrl_mem.rdy - - always_comb begin : connect_to_controller - for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin - fu__recv_from_ctrl_mem__msg[4'(i)] = recv_from_ctrl_mem__msg; - fu__recv_from_ctrl_mem__val[4'(i)] = recv_from_ctrl_mem__val; - recv_from_controller_rdy_vector[4'(i)] = fu__recv_from_ctrl_mem__rdy[4'(i)]; - end - recv_from_ctrl_mem__rdy = ( | recv_from_controller_rdy_vector ); - send_to_ctrl_mem__msg = { 5'd0, 67'd0, 7'd0, 107'd0, 4'd0 }; - send_to_ctrl_mem__val = 1'd0; - for ( int unsigned i = 1'd0; i < 4'd15; i += 1'd1 ) begin - if ( fu__send_to_ctrl_mem__val[4'(i)] ) begin - send_to_ctrl_mem__msg = fu__send_to_ctrl_mem__msg[4'(i)]; - send_to_ctrl_mem__val = fu__send_to_ctrl_mem__val[4'(i)]; - end - fu__send_to_ctrl_mem__rdy[4'(i)] = send_to_ctrl_mem__rdy; - end - end - - assign fu__clk[0] = clk; - assign fu__reset[0] = reset; - assign fu__clk[1] = clk; - assign fu__reset[1] = reset; - assign fu__clk[2] = clk; - assign fu__reset[2] = reset; - assign fu__clk[3] = clk; - assign fu__reset[3] = reset; - assign fu__clk[4] = clk; - assign fu__reset[4] = reset; - assign fu__clk[5] = clk; - assign fu__reset[5] = reset; - assign fu__clk[6] = clk; - assign fu__reset[6] = reset; - assign fu__clk[7] = clk; - assign fu__reset[7] = reset; - assign fu__clk[8] = clk; - assign fu__reset[8] = reset; - assign fu__clk[9] = clk; - assign fu__reset[9] = reset; - assign fu__clk[10] = clk; - assign fu__reset[10] = reset; - assign fu__clk[11] = clk; - assign fu__reset[11] = reset; - assign fu__clk[12] = clk; - assign fu__reset[12] = reset; - assign fu__clk[13] = clk; - assign fu__reset[13] = reset; - assign fu__clk[14] = clk; - assign fu__reset[14] = reset; - assign to_mem_raddr__msg[0] = fu__to_mem_raddr__msg[0]; - assign fu__to_mem_raddr__rdy[0] = to_mem_raddr__rdy[0]; - assign to_mem_raddr__val[0] = fu__to_mem_raddr__val[0]; - assign fu__from_mem_rdata__msg[0] = from_mem_rdata__msg[0]; - assign from_mem_rdata__rdy[0] = fu__from_mem_rdata__rdy[0]; - assign fu__from_mem_rdata__val[0] = from_mem_rdata__val[0]; - assign to_mem_waddr__msg[0] = fu__to_mem_waddr__msg[0]; - assign fu__to_mem_waddr__rdy[0] = to_mem_waddr__rdy[0]; - assign to_mem_waddr__val[0] = fu__to_mem_waddr__val[0]; - assign to_mem_wdata__msg[0] = fu__to_mem_wdata__msg[0]; - assign fu__to_mem_wdata__rdy[0] = to_mem_wdata__rdy[0]; - assign to_mem_wdata__val[0] = fu__to_mem_wdata__val[0]; - assign fu__clear[0] = clear[0]; - assign to_mem_raddr__msg[1] = fu__to_mem_raddr__msg[1]; - assign fu__to_mem_raddr__rdy[1] = to_mem_raddr__rdy[1]; - assign to_mem_raddr__val[1] = fu__to_mem_raddr__val[1]; - assign fu__from_mem_rdata__msg[1] = from_mem_rdata__msg[1]; - assign from_mem_rdata__rdy[1] = fu__from_mem_rdata__rdy[1]; - assign fu__from_mem_rdata__val[1] = from_mem_rdata__val[1]; - assign to_mem_waddr__msg[1] = fu__to_mem_waddr__msg[1]; - assign fu__to_mem_waddr__rdy[1] = to_mem_waddr__rdy[1]; - assign to_mem_waddr__val[1] = fu__to_mem_waddr__val[1]; - assign to_mem_wdata__msg[1] = fu__to_mem_wdata__msg[1]; - assign fu__to_mem_wdata__rdy[1] = to_mem_wdata__rdy[1]; - assign to_mem_wdata__val[1] = fu__to_mem_wdata__val[1]; - assign fu__clear[1] = clear[1]; - assign to_mem_raddr__msg[2] = fu__to_mem_raddr__msg[2]; - assign fu__to_mem_raddr__rdy[2] = to_mem_raddr__rdy[2]; - assign to_mem_raddr__val[2] = fu__to_mem_raddr__val[2]; - assign fu__from_mem_rdata__msg[2] = from_mem_rdata__msg[2]; - assign from_mem_rdata__rdy[2] = fu__from_mem_rdata__rdy[2]; - assign fu__from_mem_rdata__val[2] = from_mem_rdata__val[2]; - assign to_mem_waddr__msg[2] = fu__to_mem_waddr__msg[2]; - assign fu__to_mem_waddr__rdy[2] = to_mem_waddr__rdy[2]; - assign to_mem_waddr__val[2] = fu__to_mem_waddr__val[2]; - assign to_mem_wdata__msg[2] = fu__to_mem_wdata__msg[2]; - assign fu__to_mem_wdata__rdy[2] = to_mem_wdata__rdy[2]; - assign to_mem_wdata__val[2] = fu__to_mem_wdata__val[2]; - assign fu__clear[2] = clear[2]; - assign to_mem_raddr__msg[3] = fu__to_mem_raddr__msg[3]; - assign fu__to_mem_raddr__rdy[3] = to_mem_raddr__rdy[3]; - assign to_mem_raddr__val[3] = fu__to_mem_raddr__val[3]; - assign fu__from_mem_rdata__msg[3] = from_mem_rdata__msg[3]; - assign from_mem_rdata__rdy[3] = fu__from_mem_rdata__rdy[3]; - assign fu__from_mem_rdata__val[3] = from_mem_rdata__val[3]; - assign to_mem_waddr__msg[3] = fu__to_mem_waddr__msg[3]; - assign fu__to_mem_waddr__rdy[3] = to_mem_waddr__rdy[3]; - assign to_mem_waddr__val[3] = fu__to_mem_waddr__val[3]; - assign to_mem_wdata__msg[3] = fu__to_mem_wdata__msg[3]; - assign fu__to_mem_wdata__rdy[3] = to_mem_wdata__rdy[3]; - assign to_mem_wdata__val[3] = fu__to_mem_wdata__val[3]; - assign fu__clear[3] = clear[3]; - assign to_mem_raddr__msg[4] = fu__to_mem_raddr__msg[4]; - assign fu__to_mem_raddr__rdy[4] = to_mem_raddr__rdy[4]; - assign to_mem_raddr__val[4] = fu__to_mem_raddr__val[4]; - assign fu__from_mem_rdata__msg[4] = from_mem_rdata__msg[4]; - assign from_mem_rdata__rdy[4] = fu__from_mem_rdata__rdy[4]; - assign fu__from_mem_rdata__val[4] = from_mem_rdata__val[4]; - assign to_mem_waddr__msg[4] = fu__to_mem_waddr__msg[4]; - assign fu__to_mem_waddr__rdy[4] = to_mem_waddr__rdy[4]; - assign to_mem_waddr__val[4] = fu__to_mem_waddr__val[4]; - assign to_mem_wdata__msg[4] = fu__to_mem_wdata__msg[4]; - assign fu__to_mem_wdata__rdy[4] = to_mem_wdata__rdy[4]; - assign to_mem_wdata__val[4] = fu__to_mem_wdata__val[4]; - assign fu__clear[4] = clear[4]; - assign to_mem_raddr__msg[5] = fu__to_mem_raddr__msg[5]; - assign fu__to_mem_raddr__rdy[5] = to_mem_raddr__rdy[5]; - assign to_mem_raddr__val[5] = fu__to_mem_raddr__val[5]; - assign fu__from_mem_rdata__msg[5] = from_mem_rdata__msg[5]; - assign from_mem_rdata__rdy[5] = fu__from_mem_rdata__rdy[5]; - assign fu__from_mem_rdata__val[5] = from_mem_rdata__val[5]; - assign to_mem_waddr__msg[5] = fu__to_mem_waddr__msg[5]; - assign fu__to_mem_waddr__rdy[5] = to_mem_waddr__rdy[5]; - assign to_mem_waddr__val[5] = fu__to_mem_waddr__val[5]; - assign to_mem_wdata__msg[5] = fu__to_mem_wdata__msg[5]; - assign fu__to_mem_wdata__rdy[5] = to_mem_wdata__rdy[5]; - assign to_mem_wdata__val[5] = fu__to_mem_wdata__val[5]; - assign fu__clear[5] = clear[5]; - assign to_mem_raddr__msg[6] = fu__to_mem_raddr__msg[6]; - assign fu__to_mem_raddr__rdy[6] = to_mem_raddr__rdy[6]; - assign to_mem_raddr__val[6] = fu__to_mem_raddr__val[6]; - assign fu__from_mem_rdata__msg[6] = from_mem_rdata__msg[6]; - assign from_mem_rdata__rdy[6] = fu__from_mem_rdata__rdy[6]; - assign fu__from_mem_rdata__val[6] = from_mem_rdata__val[6]; - assign to_mem_waddr__msg[6] = fu__to_mem_waddr__msg[6]; - assign fu__to_mem_waddr__rdy[6] = to_mem_waddr__rdy[6]; - assign to_mem_waddr__val[6] = fu__to_mem_waddr__val[6]; - assign to_mem_wdata__msg[6] = fu__to_mem_wdata__msg[6]; - assign fu__to_mem_wdata__rdy[6] = to_mem_wdata__rdy[6]; - assign to_mem_wdata__val[6] = fu__to_mem_wdata__val[6]; - assign fu__clear[6] = clear[6]; - assign to_mem_raddr__msg[7] = fu__to_mem_raddr__msg[7]; - assign fu__to_mem_raddr__rdy[7] = to_mem_raddr__rdy[7]; - assign to_mem_raddr__val[7] = fu__to_mem_raddr__val[7]; - assign fu__from_mem_rdata__msg[7] = from_mem_rdata__msg[7]; - assign from_mem_rdata__rdy[7] = fu__from_mem_rdata__rdy[7]; - assign fu__from_mem_rdata__val[7] = from_mem_rdata__val[7]; - assign to_mem_waddr__msg[7] = fu__to_mem_waddr__msg[7]; - assign fu__to_mem_waddr__rdy[7] = to_mem_waddr__rdy[7]; - assign to_mem_waddr__val[7] = fu__to_mem_waddr__val[7]; - assign to_mem_wdata__msg[7] = fu__to_mem_wdata__msg[7]; - assign fu__to_mem_wdata__rdy[7] = to_mem_wdata__rdy[7]; - assign to_mem_wdata__val[7] = fu__to_mem_wdata__val[7]; - assign fu__clear[7] = clear[7]; - assign to_mem_raddr__msg[8] = fu__to_mem_raddr__msg[8]; - assign fu__to_mem_raddr__rdy[8] = to_mem_raddr__rdy[8]; - assign to_mem_raddr__val[8] = fu__to_mem_raddr__val[8]; - assign fu__from_mem_rdata__msg[8] = from_mem_rdata__msg[8]; - assign from_mem_rdata__rdy[8] = fu__from_mem_rdata__rdy[8]; - assign fu__from_mem_rdata__val[8] = from_mem_rdata__val[8]; - assign to_mem_waddr__msg[8] = fu__to_mem_waddr__msg[8]; - assign fu__to_mem_waddr__rdy[8] = to_mem_waddr__rdy[8]; - assign to_mem_waddr__val[8] = fu__to_mem_waddr__val[8]; - assign to_mem_wdata__msg[8] = fu__to_mem_wdata__msg[8]; - assign fu__to_mem_wdata__rdy[8] = to_mem_wdata__rdy[8]; - assign to_mem_wdata__val[8] = fu__to_mem_wdata__val[8]; - assign fu__clear[8] = clear[8]; - assign to_mem_raddr__msg[9] = fu__to_mem_raddr__msg[9]; - assign fu__to_mem_raddr__rdy[9] = to_mem_raddr__rdy[9]; - assign to_mem_raddr__val[9] = fu__to_mem_raddr__val[9]; - assign fu__from_mem_rdata__msg[9] = from_mem_rdata__msg[9]; - assign from_mem_rdata__rdy[9] = fu__from_mem_rdata__rdy[9]; - assign fu__from_mem_rdata__val[9] = from_mem_rdata__val[9]; - assign to_mem_waddr__msg[9] = fu__to_mem_waddr__msg[9]; - assign fu__to_mem_waddr__rdy[9] = to_mem_waddr__rdy[9]; - assign to_mem_waddr__val[9] = fu__to_mem_waddr__val[9]; - assign to_mem_wdata__msg[9] = fu__to_mem_wdata__msg[9]; - assign fu__to_mem_wdata__rdy[9] = to_mem_wdata__rdy[9]; - assign to_mem_wdata__val[9] = fu__to_mem_wdata__val[9]; - assign fu__clear[9] = clear[9]; - assign to_mem_raddr__msg[10] = fu__to_mem_raddr__msg[10]; - assign fu__to_mem_raddr__rdy[10] = to_mem_raddr__rdy[10]; - assign to_mem_raddr__val[10] = fu__to_mem_raddr__val[10]; - assign fu__from_mem_rdata__msg[10] = from_mem_rdata__msg[10]; - assign from_mem_rdata__rdy[10] = fu__from_mem_rdata__rdy[10]; - assign fu__from_mem_rdata__val[10] = from_mem_rdata__val[10]; - assign to_mem_waddr__msg[10] = fu__to_mem_waddr__msg[10]; - assign fu__to_mem_waddr__rdy[10] = to_mem_waddr__rdy[10]; - assign to_mem_waddr__val[10] = fu__to_mem_waddr__val[10]; - assign to_mem_wdata__msg[10] = fu__to_mem_wdata__msg[10]; - assign fu__to_mem_wdata__rdy[10] = to_mem_wdata__rdy[10]; - assign to_mem_wdata__val[10] = fu__to_mem_wdata__val[10]; - assign fu__clear[10] = clear[10]; - assign to_mem_raddr__msg[11] = fu__to_mem_raddr__msg[11]; - assign fu__to_mem_raddr__rdy[11] = to_mem_raddr__rdy[11]; - assign to_mem_raddr__val[11] = fu__to_mem_raddr__val[11]; - assign fu__from_mem_rdata__msg[11] = from_mem_rdata__msg[11]; - assign from_mem_rdata__rdy[11] = fu__from_mem_rdata__rdy[11]; - assign fu__from_mem_rdata__val[11] = from_mem_rdata__val[11]; - assign to_mem_waddr__msg[11] = fu__to_mem_waddr__msg[11]; - assign fu__to_mem_waddr__rdy[11] = to_mem_waddr__rdy[11]; - assign to_mem_waddr__val[11] = fu__to_mem_waddr__val[11]; - assign to_mem_wdata__msg[11] = fu__to_mem_wdata__msg[11]; - assign fu__to_mem_wdata__rdy[11] = to_mem_wdata__rdy[11]; - assign to_mem_wdata__val[11] = fu__to_mem_wdata__val[11]; - assign fu__clear[11] = clear[11]; - assign to_mem_raddr__msg[12] = fu__to_mem_raddr__msg[12]; - assign fu__to_mem_raddr__rdy[12] = to_mem_raddr__rdy[12]; - assign to_mem_raddr__val[12] = fu__to_mem_raddr__val[12]; - assign fu__from_mem_rdata__msg[12] = from_mem_rdata__msg[12]; - assign from_mem_rdata__rdy[12] = fu__from_mem_rdata__rdy[12]; - assign fu__from_mem_rdata__val[12] = from_mem_rdata__val[12]; - assign to_mem_waddr__msg[12] = fu__to_mem_waddr__msg[12]; - assign fu__to_mem_waddr__rdy[12] = to_mem_waddr__rdy[12]; - assign to_mem_waddr__val[12] = fu__to_mem_waddr__val[12]; - assign to_mem_wdata__msg[12] = fu__to_mem_wdata__msg[12]; - assign fu__to_mem_wdata__rdy[12] = to_mem_wdata__rdy[12]; - assign to_mem_wdata__val[12] = fu__to_mem_wdata__val[12]; - assign fu__clear[12] = clear[12]; - assign to_mem_raddr__msg[13] = fu__to_mem_raddr__msg[13]; - assign fu__to_mem_raddr__rdy[13] = to_mem_raddr__rdy[13]; - assign to_mem_raddr__val[13] = fu__to_mem_raddr__val[13]; - assign fu__from_mem_rdata__msg[13] = from_mem_rdata__msg[13]; - assign from_mem_rdata__rdy[13] = fu__from_mem_rdata__rdy[13]; - assign fu__from_mem_rdata__val[13] = from_mem_rdata__val[13]; - assign to_mem_waddr__msg[13] = fu__to_mem_waddr__msg[13]; - assign fu__to_mem_waddr__rdy[13] = to_mem_waddr__rdy[13]; - assign to_mem_waddr__val[13] = fu__to_mem_waddr__val[13]; - assign to_mem_wdata__msg[13] = fu__to_mem_wdata__msg[13]; - assign fu__to_mem_wdata__rdy[13] = to_mem_wdata__rdy[13]; - assign to_mem_wdata__val[13] = fu__to_mem_wdata__val[13]; - assign fu__clear[13] = clear[13]; - assign to_mem_raddr__msg[14] = fu__to_mem_raddr__msg[14]; - assign fu__to_mem_raddr__rdy[14] = to_mem_raddr__rdy[14]; - assign to_mem_raddr__val[14] = fu__to_mem_raddr__val[14]; - assign fu__from_mem_rdata__msg[14] = from_mem_rdata__msg[14]; - assign from_mem_rdata__rdy[14] = fu__from_mem_rdata__rdy[14]; - assign fu__from_mem_rdata__val[14] = from_mem_rdata__val[14]; - assign to_mem_waddr__msg[14] = fu__to_mem_waddr__msg[14]; - assign fu__to_mem_waddr__rdy[14] = to_mem_waddr__rdy[14]; - assign to_mem_waddr__val[14] = fu__to_mem_waddr__val[14]; - assign to_mem_wdata__msg[14] = fu__to_mem_wdata__msg[14]; - assign fu__to_mem_wdata__rdy[14] = to_mem_wdata__rdy[14]; - assign to_mem_wdata__val[14] = fu__to_mem_wdata__val[14]; - assign fu__clear[14] = clear[14]; - -endmodule - - -// PyMTL Component CrossbarRTL Definition -// Full name: CrossbarRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_2__num_outports_8__num_cgras_4__num_tiles_16__ctrl_mem_size_16__outport_towards_local_base_id_4 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py - -module CrossbarRTL__45ee026205c61975 -( - input logic [1:0] cgra_id , - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] compute_done , - input logic [0:0] crossbar_id , - input logic [1:0] crossbar_outport [0:7], - input logic [3:0] ctrl_addr_inport , - input logic [2:0] prologue_count_inport [0:15][0:1], - input logic [0:0] reset , - input logic [4:0] tile_id , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:1] , - output logic [0:0] recv_data__rdy [0:1] , - input logic [0:0] recv_data__val [0:1] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:7] , - input logic [0:0] send_data__rdy [0:7] , - output logic [0:0] send_data__val [0:7] -); - localparam logic [1:0] __const__num_inports_at_update_signal = 2'd2; - localparam logic [3:0] __const__num_outports_at_update_signal = 4'd8; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter = 5'd16; - localparam logic [1:0] __const__num_inports_at_update_prologue_counter = 2'd2; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter_next = 5'd16; - localparam logic [1:0] __const__num_inports_at_update_prologue_counter_next = 2'd2; - localparam logic [3:0] __const__num_outports_at_update_prologue_counter_next = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_prologue_allowing_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_prologue_or_valid_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_in_dir_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_rdy_vector = 4'd8; - localparam logic [2:0] __const__outport_towards_local_base_id_at_update_rdy_vector = 3'd4; - localparam logic [3:0] __const__num_outports_at_update_valid_vector = 4'd8; - localparam logic [1:0] __const__num_inports_at_update_recv_required_vector = 2'd2; - localparam logic [3:0] __const__num_outports_at_update_recv_required_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_send_required_vector = 4'd8; - logic [1:0] in_dir [0:7]; - logic [0:0] in_dir_local [0:7]; - logic [7:0] prologue_allowing_vector; - logic [2:0] prologue_count_wire [0:15][0:1]; - logic [2:0] prologue_counter [0:15][0:1]; - logic [2:0] prologue_counter_next [0:15][0:1]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_msg [0:1]; - logic [0:0] recv_data_val [0:1]; - logic [1:0] recv_required_vector; - logic [7:0] recv_valid_or_prologue_allowing_vector; - logic [7:0] recv_valid_vector; - logic [7:0] send_rdy_vector; - logic [7:0] send_required_vector; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:153 - // @update - // def update_in_dir_vector(): - // - // for i in range(num_outports): - // s.in_dir[i] @= 0 - // s.in_dir_local[i] @= 0 - // - // for i in range(num_outports): - // s.in_dir[i] @= s.crossbar_outport[i] - // if s.in_dir[i] > 0: - // s.in_dir_local[i] @= trunc(s.in_dir[i] - 1, NumInportType) - - always_comb begin : update_in_dir_vector - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin - in_dir[3'(i)] = 2'd0; - in_dir_local[3'(i)] = 1'd0; - end - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin - in_dir[3'(i)] = crossbar_outport[3'(i)]; - if ( in_dir[3'(i)] > 2'd0 ) begin - in_dir_local[3'(i)] = 1'(in_dir[3'(i)] - 2'd1); - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:134 - // @update - // def update_prologue_allowing_vector(): - // s.prologue_allowing_vector @= 0 - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // # Records whether the prologue steps have already been satisfied. - // s.prologue_allowing_vector[i] @= \ - // (s.prologue_counter[s.ctrl_addr_inport][s.in_dir_local[i]] < \ - // s.prologue_count_wire[s.ctrl_addr_inport][s.in_dir_local[i]]) - // else: - // s.prologue_allowing_vector[i] @= 1 - - always_comb begin : update_prologue_allowing_vector - prologue_allowing_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_allowing_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 2'd0 ) begin - prologue_allowing_vector[3'(i)] = prologue_counter[ctrl_addr_inport][in_dir_local[3'(i)]] < prologue_count_wire[ctrl_addr_inport][in_dir_local[3'(i)]]; - end - else - prologue_allowing_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:119 - // @update - // def update_prologue_counter_next(): - // # Nested-loop to update the prologue counter, to avoid dynamic indexing to - // # work-around Yosys issue: https://github.com/tancheng/VectorCGRA/issues/148 - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] - // for j in range(num_outports): - // if s.recv_opt.rdy & \ - // (s.in_dir[j] > 0) & \ - // (s.in_dir_local[j] == i) & \ - // (addr == s.ctrl_addr_inport) & \ - // (s.prologue_counter[addr][i] < s.prologue_count_wire[addr][i]): - // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + 1 - - always_comb begin : update_prologue_counter_next - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter_next ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter_next ); i += 1'd1 ) begin - prologue_counter_next[4'(addr)][1'(i)] = prologue_counter[4'(addr)][1'(i)]; - for ( int unsigned j = 1'd0; j < 4'( __const__num_outports_at_update_prologue_counter_next ); j += 1'd1 ) - if ( ( ( ( recv_opt__rdy & ( in_dir[3'(j)] > 2'd0 ) ) & ( in_dir_local[3'(j)] == 1'(i) ) ) & ( 4'(addr) == ctrl_addr_inport ) ) & ( prologue_counter[4'(addr)][1'(i)] < prologue_count_wire[4'(addr)][1'(i)] ) ) begin - prologue_counter_next[4'(addr)][1'(i)] = prologue_counter[4'(addr)][1'(i)] + 3'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:146 - // @update - // def update_prologue_or_valid_vector(): - // s.recv_valid_or_prologue_allowing_vector @= 0 - // for i in range(num_outports): - // s.recv_valid_or_prologue_allowing_vector[i] @= \ - // s.recv_valid_vector[i] | s.prologue_allowing_vector[i] - - always_comb begin : update_prologue_or_valid_vector - recv_valid_or_prologue_allowing_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_or_valid_vector ); i += 1'd1 ) - recv_valid_or_prologue_allowing_vector[3'(i)] = recv_valid_vector[3'(i)] | prologue_allowing_vector[3'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:165 - // @update - // def update_rdy_vector(): - // s.send_rdy_vector @= 0 - // for i in range(num_outports): - // # The `num_inports` indicates the number of outports that go to other tiles. - // # Specifically, if the compute already done, we shouldn't care the ones - // # (i.e., i >= num_inports) go to the FU's inports. In other words, we skip - // # the rdy checking on the FU's inports (connecting from crossbar_outport) if - // # the compute is already completed. - // if (s.in_dir[i] > 0) & \ - // (~s.compute_done | (i < outport_towards_local_base_id)): - // s.send_rdy_vector[i] @= s.send_data[i].rdy - // else: - // s.send_rdy_vector[i] @= 1 - - always_comb begin : update_rdy_vector - send_rdy_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_rdy_vector ); i += 1'd1 ) - if ( ( in_dir[3'(i)] > 2'd0 ) & ( ( ~compute_done ) | ( 3'(i) < 3'( __const__outport_towards_local_base_id_at_update_rdy_vector ) ) ) ) begin - send_rdy_vector[3'(i)] = send_data__rdy[3'(i)]; - end - else - send_rdy_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:189 - // @update - // def update_recv_required_vector(): - // for i in range(num_inports): - // s.recv_required_vector[i] @= 0 - // - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.recv_required_vector[s.in_dir_local[i]] @= 1 - - always_comb begin : update_recv_required_vector - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_recv_required_vector ); i += 1'd1 ) - recv_required_vector[1'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_recv_required_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 2'd0 ) begin - recv_required_vector[in_dir_local[3'(i)]] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:198 - // @update - // def update_send_required_vector(): - // - // for i in range(num_outports): - // s.send_required_vector[i] @= 0 - // - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.send_required_vector[i] @= 1 - - always_comb begin : update_send_required_vector - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) - send_required_vector[3'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 2'd0 ) begin - send_required_vector[3'(i)] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:82 - // @update - // def update_signal(): - // for i in range(num_inports): - // s.recv_data[i].rdy @= 0 - // for i in range(num_outports): - // s.send_data[i].val @= 0 - // s.send_data[i].msg @= DataType() - // s.recv_opt.rdy @= 0 - // - // if s.recv_opt.val & (s.recv_opt.msg.operation != OPT_START): - // for i in range(num_inports): - // s.recv_data[i].rdy @= reduce_and(s.recv_valid_vector) & \ - // reduce_and(s.send_rdy_vector) & \ - // s.recv_required_vector[i] - // - // for i in range(num_outports): - // s.send_data[i].val @= reduce_and(s.recv_valid_vector) & \ - // s.send_required_vector[i] - // if reduce_and(s.recv_valid_vector) & \ - // s.send_required_vector[i]: - // s.send_data[i].msg.payload @= s.recv_data_msg[s.in_dir_local[i]].payload - // s.send_data[i].msg.predicate @= s.recv_data_msg[s.in_dir_local[i]].predicate - // - // s.recv_opt.rdy @= reduce_and(s.send_rdy_vector) & \ - // reduce_and(s.recv_valid_or_prologue_allowing_vector) - - always_comb begin : update_signal - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_signal ); i += 1'd1 ) - recv_data__rdy[1'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin - send_data__val[3'(i)] = 1'd0; - send_data__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_opt__rdy = 1'd0; - if ( recv_opt__val & ( recv_opt__msg.operation != 7'( __const__OPT_START ) ) ) begin - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_signal ); i += 1'd1 ) - recv_data__rdy[1'(i)] = ( ( & recv_valid_vector ) & ( & send_rdy_vector ) ) & recv_required_vector[1'(i)]; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin - send_data__val[3'(i)] = ( & recv_valid_vector ) & send_required_vector[3'(i)]; - if ( ( & recv_valid_vector ) & send_required_vector[3'(i)] ) begin - send_data__msg[3'(i)].payload = recv_data_msg[in_dir_local[3'(i)]].payload; - send_data__msg[3'(i)].predicate = recv_data_msg[in_dir_local[3'(i)]].predicate; - end - end - recv_opt__rdy = ( & send_rdy_vector ) & ( & recv_valid_or_prologue_allowing_vector ); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:180 - // @update - // def update_valid_vector(): - // s.recv_valid_vector @= 0 - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.recv_valid_vector[i] @= s.recv_data_val[s.in_dir_local[i]] - // else: - // s.recv_valid_vector[i] @= 1 - - always_comb begin : update_valid_vector - recv_valid_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_valid_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 2'd0 ) begin - recv_valid_vector[3'(i)] = recv_data_val[in_dir_local[3'(i)]]; - end - else - recv_valid_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:108 - // @update_ff - // def update_prologue_counter(): - // if s.reset | s.clear: - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter[addr][i] <<= 0 - // else: - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter[addr][i] <<= s.prologue_counter_next[addr][i] - - always_ff @(posedge clk) begin : update_prologue_counter - if ( reset | clear ) begin - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) - prologue_counter[4'(addr)][1'(i)] <= 3'd0; - end - else - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 2'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) - prologue_counter[4'(addr)][1'(i)] <= prologue_counter_next[4'(addr)][1'(i)]; - end - - assign recv_data_msg[0] = recv_data__msg[0]; - assign recv_data_val[0] = recv_data__val[0]; - assign recv_data_msg[1] = recv_data__msg[1]; - assign recv_data_val[1] = recv_data__val[1]; - assign prologue_count_wire[0][0] = prologue_count_inport[0][0]; - assign prologue_count_wire[0][1] = prologue_count_inport[0][1]; - assign prologue_count_wire[1][0] = prologue_count_inport[1][0]; - assign prologue_count_wire[1][1] = prologue_count_inport[1][1]; - assign prologue_count_wire[2][0] = prologue_count_inport[2][0]; - assign prologue_count_wire[2][1] = prologue_count_inport[2][1]; - assign prologue_count_wire[3][0] = prologue_count_inport[3][0]; - assign prologue_count_wire[3][1] = prologue_count_inport[3][1]; - assign prologue_count_wire[4][0] = prologue_count_inport[4][0]; - assign prologue_count_wire[4][1] = prologue_count_inport[4][1]; - assign prologue_count_wire[5][0] = prologue_count_inport[5][0]; - assign prologue_count_wire[5][1] = prologue_count_inport[5][1]; - assign prologue_count_wire[6][0] = prologue_count_inport[6][0]; - assign prologue_count_wire[6][1] = prologue_count_inport[6][1]; - assign prologue_count_wire[7][0] = prologue_count_inport[7][0]; - assign prologue_count_wire[7][1] = prologue_count_inport[7][1]; - assign prologue_count_wire[8][0] = prologue_count_inport[8][0]; - assign prologue_count_wire[8][1] = prologue_count_inport[8][1]; - assign prologue_count_wire[9][0] = prologue_count_inport[9][0]; - assign prologue_count_wire[9][1] = prologue_count_inport[9][1]; - assign prologue_count_wire[10][0] = prologue_count_inport[10][0]; - assign prologue_count_wire[10][1] = prologue_count_inport[10][1]; - assign prologue_count_wire[11][0] = prologue_count_inport[11][0]; - assign prologue_count_wire[11][1] = prologue_count_inport[11][1]; - assign prologue_count_wire[12][0] = prologue_count_inport[12][0]; - assign prologue_count_wire[12][1] = prologue_count_inport[12][1]; - assign prologue_count_wire[13][0] = prologue_count_inport[13][0]; - assign prologue_count_wire[13][1] = prologue_count_inport[13][1]; - assign prologue_count_wire[14][0] = prologue_count_inport[14][0]; - assign prologue_count_wire[14][1] = prologue_count_inport[14][1]; - assign prologue_count_wire[15][0] = prologue_count_inport[15][0]; - assign prologue_count_wire[15][1] = prologue_count_inport[15][1]; - -endmodule - - -// PyMTL Component RegisterBankRTL Definition -// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_0__num_registers_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py - -module RegisterBankRTL__649561e613f42979 -( - input logic [0:0] clk , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , - input logic [0:0] inport_valid [0:2], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], - input logic [0:0] reset , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , - input logic [0:0] send_data_to_fu__rdy , - output logic [0:0] send_data_to_fu__val -); - localparam logic [0:0] __const__reg_bank_id_at_access_registers = 1'd0; - localparam logic [0:0] __const__reg_bank_id_at_update_send_val = 1'd0; - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__bd22936ec5812d0d reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [1:0] __tmpvar__access_registers_write_reg_from; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 - // @update - // def access_registers(): - // # Initializes signals. - // s.reg_file.raddr[0] @= AddrType() - // s.send_data_to_fu.msg @= DataType() - // s.reg_file.waddr[0] @= AddrType() - // s.reg_file.wdata[0] @= DataType() - // s.reg_file.wen[0] @= 0 - // - // if s.inport_opt.read_reg_from[reg_bank_id]: - // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] - // s.send_data_to_fu.msg @= s.reg_file.rdata[0] - // - // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] - // if ~s.reset & (write_reg_from > 0): - // if s.inport_valid[write_reg_from - 1]: - // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] - // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] - // s.reg_file.wen[0] @= 1 - - always_comb begin : access_registers - reg_file__raddr[1'd0] = 4'd0; - send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__waddr[1'd0] = 4'd0; - reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__wen[1'd0] = 1'd0; - if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin - reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - send_data_to_fu__msg = reg_file__rdata[1'd0]; - end - __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; - if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin - if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin - reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; - reg_file__wen[1'd0] = 1'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 - // @update - // def update_send_val(): - // s.send_data_to_fu.val @= 0 - // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: - // s.send_data_to_fu.val @= 1 - - always_comb begin : update_send_val - send_data_to_fu__val = 1'd0; - if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin - send_data_to_fu__val = 1'd1; - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - -endmodule - - -// PyMTL Component RegisterBankRTL Definition -// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_1__num_registers_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py - -module RegisterBankRTL__0a5bdf408d921386 -( - input logic [0:0] clk , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , - input logic [0:0] inport_valid [0:2], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], - input logic [0:0] reset , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , - input logic [0:0] send_data_to_fu__rdy , - output logic [0:0] send_data_to_fu__val -); - localparam logic [0:0] __const__reg_bank_id_at_access_registers = 1'd1; - localparam logic [0:0] __const__reg_bank_id_at_update_send_val = 1'd1; - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__bd22936ec5812d0d reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [1:0] __tmpvar__access_registers_write_reg_from; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 - // @update - // def access_registers(): - // # Initializes signals. - // s.reg_file.raddr[0] @= AddrType() - // s.send_data_to_fu.msg @= DataType() - // s.reg_file.waddr[0] @= AddrType() - // s.reg_file.wdata[0] @= DataType() - // s.reg_file.wen[0] @= 0 - // - // if s.inport_opt.read_reg_from[reg_bank_id]: - // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] - // s.send_data_to_fu.msg @= s.reg_file.rdata[0] - // - // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] - // if ~s.reset & (write_reg_from > 0): - // if s.inport_valid[write_reg_from - 1]: - // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] - // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] - // s.reg_file.wen[0] @= 1 - - always_comb begin : access_registers - reg_file__raddr[1'd0] = 4'd0; - send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__waddr[1'd0] = 4'd0; - reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__wen[1'd0] = 1'd0; - if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin - reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - send_data_to_fu__msg = reg_file__rdata[1'd0]; - end - __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; - if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin - if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin - reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; - reg_file__wen[1'd0] = 1'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 - // @update - // def update_send_val(): - // s.send_data_to_fu.val @= 0 - // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: - // s.send_data_to_fu.val @= 1 - - always_comb begin : update_send_val - send_data_to_fu__val = 1'd0; - if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin - send_data_to_fu__val = 1'd1; - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - -endmodule - - -// PyMTL Component RegisterBankRTL Definition -// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_2__num_registers_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py - -module RegisterBankRTL__ddae41891d80e575 -( - input logic [0:0] clk , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , - input logic [0:0] inport_valid [0:2], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], - input logic [0:0] reset , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , - input logic [0:0] send_data_to_fu__rdy , - output logic [0:0] send_data_to_fu__val -); - localparam logic [1:0] __const__reg_bank_id_at_access_registers = 2'd2; - localparam logic [1:0] __const__reg_bank_id_at_update_send_val = 2'd2; - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__bd22936ec5812d0d reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [1:0] __tmpvar__access_registers_write_reg_from; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 - // @update - // def access_registers(): - // # Initializes signals. - // s.reg_file.raddr[0] @= AddrType() - // s.send_data_to_fu.msg @= DataType() - // s.reg_file.waddr[0] @= AddrType() - // s.reg_file.wdata[0] @= DataType() - // s.reg_file.wen[0] @= 0 - // - // if s.inport_opt.read_reg_from[reg_bank_id]: - // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] - // s.send_data_to_fu.msg @= s.reg_file.rdata[0] - // - // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] - // if ~s.reset & (write_reg_from > 0): - // if s.inport_valid[write_reg_from - 1]: - // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] - // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] - // s.reg_file.wen[0] @= 1 - - always_comb begin : access_registers - reg_file__raddr[1'd0] = 4'd0; - send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__waddr[1'd0] = 4'd0; - reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__wen[1'd0] = 1'd0; - if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin - reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - send_data_to_fu__msg = reg_file__rdata[1'd0]; - end - __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; - if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin - if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin - reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; - reg_file__wen[1'd0] = 1'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 - // @update - // def update_send_val(): - // s.send_data_to_fu.val @= 0 - // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: - // s.send_data_to_fu.val @= 1 - - always_comb begin : update_send_val - send_data_to_fu__val = 1'd0; - if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin - send_data_to_fu__val = 1'd1; - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - -endmodule - - -// PyMTL Component RegisterBankRTL Definition -// Full name: RegisterBankRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__reg_bank_id_3__num_registers_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py - -module RegisterBankRTL__ff0588d25abf2ed3 -( - input logic [0:0] clk , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , - input logic [0:0] inport_valid [0:2], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 inport_wdata [0:2], - input logic [0:0] reset , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg , - input logic [0:0] send_data_to_fu__rdy , - output logic [0:0] send_data_to_fu__val -); - localparam logic [1:0] __const__reg_bank_id_at_access_registers = 2'd3; - localparam logic [1:0] __const__reg_bank_id_at_update_send_val = 2'd3; - //------------------------------------------------------------- - // Component reg_file - //------------------------------------------------------------- - - logic [0:0] reg_file__clk; - logic [3:0] reg_file__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__rdata [0:0]; - logic [0:0] reg_file__reset; - logic [3:0] reg_file__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_file__wdata [0:0]; - logic [0:0] reg_file__wen [0:0]; - - RegisterFile__bd22936ec5812d0d reg_file - ( - .clk( reg_file__clk ), - .raddr( reg_file__raddr ), - .rdata( reg_file__rdata ), - .reset( reg_file__reset ), - .waddr( reg_file__waddr ), - .wdata( reg_file__wdata ), - .wen( reg_file__wen ) - ); - - //------------------------------------------------------------- - // End of component reg_file - //------------------------------------------------------------- - logic [1:0] __tmpvar__access_registers_write_reg_from; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:41 - // @update - // def access_registers(): - // # Initializes signals. - // s.reg_file.raddr[0] @= AddrType() - // s.send_data_to_fu.msg @= DataType() - // s.reg_file.waddr[0] @= AddrType() - // s.reg_file.wdata[0] @= DataType() - // s.reg_file.wen[0] @= 0 - // - // if s.inport_opt.read_reg_from[reg_bank_id]: - // s.reg_file.raddr[0] @= s.inport_opt.read_reg_idx[reg_bank_id] - // s.send_data_to_fu.msg @= s.reg_file.rdata[0] - // - // write_reg_from = s.inport_opt.write_reg_from[reg_bank_id] - // if ~s.reset & (write_reg_from > 0): - // if s.inport_valid[write_reg_from - 1]: - // s.reg_file.waddr[0] @= s.inport_opt.write_reg_idx[reg_bank_id] - // s.reg_file.wdata[0] @= s.inport_wdata[write_reg_from - 1] - // s.reg_file.wen[0] @= 1 - - always_comb begin : access_registers - reg_file__raddr[1'd0] = 4'd0; - send_data_to_fu__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__waddr[1'd0] = 4'd0; - reg_file__wdata[1'd0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - reg_file__wen[1'd0] = 1'd0; - if ( inport_opt.read_reg_from[2'( __const__reg_bank_id_at_access_registers )] ) begin - reg_file__raddr[1'd0] = inport_opt.read_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - send_data_to_fu__msg = reg_file__rdata[1'd0]; - end - __tmpvar__access_registers_write_reg_from = inport_opt.write_reg_from[2'( __const__reg_bank_id_at_access_registers )]; - if ( ( ~reset ) & ( __tmpvar__access_registers_write_reg_from > 2'd0 ) ) begin - if ( inport_valid[__tmpvar__access_registers_write_reg_from - 2'd1] ) begin - reg_file__waddr[1'd0] = inport_opt.write_reg_idx[2'( __const__reg_bank_id_at_access_registers )]; - reg_file__wdata[1'd0] = inport_wdata[__tmpvar__access_registers_write_reg_from - 2'd1]; - reg_file__wen[1'd0] = 1'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterBankRTL.py:61 - // @update - // def update_send_val(): - // s.send_data_to_fu.val @= 0 - // if ~s.reset & s.inport_opt.read_reg_from[reg_bank_id]: - // s.send_data_to_fu.val @= 1 - - always_comb begin : update_send_val - send_data_to_fu__val = 1'd0; - if ( ( ~reset ) & inport_opt.read_reg_from[2'( __const__reg_bank_id_at_update_send_val )] ) begin - send_data_to_fu__val = 1'd1; - end - end - - assign reg_file__clk = clk; - assign reg_file__reset = reset; - -endmodule - - -// PyMTL Component RegisterClusterRTL Definition -// Full name: RegisterClusterRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_reg_banks_4__num_registers_per_reg_bank_16 -// At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterClusterRTL.py - -module RegisterClusterRTL__7f2febb613462546 -( - input logic [0:0] clk , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 inport_opt , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_const__msg [0:3] , - output logic [0:0] recv_data_from_const__rdy [0:3] , - input logic [0:0] recv_data_from_const__val [0:3] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_fu_crossbar__msg [0:3] , - output logic [0:0] recv_data_from_fu_crossbar__rdy [0:3] , - input logic [0:0] recv_data_from_fu_crossbar__val [0:3] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_from_routing_crossbar__msg [0:3] , - output logic [0:0] recv_data_from_routing_crossbar__rdy [0:3] , - input logic [0:0] recv_data_from_routing_crossbar__val [0:3] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_to_fu__msg [0:3] , - input logic [0:0] send_data_to_fu__rdy [0:3] , - output logic [0:0] send_data_to_fu__val [0:3] -); - localparam logic [2:0] __const__num_reg_banks_at_update_msgs_signals = 3'd4; - //------------------------------------------------------------- - // Component reg_bank[0:3] - //------------------------------------------------------------- - - logic [0:0] reg_bank__clk [0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 reg_bank__inport_opt [0:3]; - logic [0:0] reg_bank__inport_valid [0:3][0:2]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_bank__inport_wdata [0:3][0:2]; - logic [0:0] reg_bank__reset [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 reg_bank__send_data_to_fu__msg [0:3]; - logic [0:0] reg_bank__send_data_to_fu__rdy [0:3]; - logic [0:0] reg_bank__send_data_to_fu__val [0:3]; - - RegisterBankRTL__649561e613f42979 reg_bank__0 - ( - .clk( reg_bank__clk[0] ), - .inport_opt( reg_bank__inport_opt[0] ), - .inport_valid( reg_bank__inport_valid[0] ), - .inport_wdata( reg_bank__inport_wdata[0] ), - .reset( reg_bank__reset[0] ), - .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[0] ), - .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[0] ), - .send_data_to_fu__val( reg_bank__send_data_to_fu__val[0] ) - ); - - RegisterBankRTL__0a5bdf408d921386 reg_bank__1 - ( - .clk( reg_bank__clk[1] ), - .inport_opt( reg_bank__inport_opt[1] ), - .inport_valid( reg_bank__inport_valid[1] ), - .inport_wdata( reg_bank__inport_wdata[1] ), - .reset( reg_bank__reset[1] ), - .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[1] ), - .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[1] ), - .send_data_to_fu__val( reg_bank__send_data_to_fu__val[1] ) - ); - - RegisterBankRTL__ddae41891d80e575 reg_bank__2 - ( - .clk( reg_bank__clk[2] ), - .inport_opt( reg_bank__inport_opt[2] ), - .inport_valid( reg_bank__inport_valid[2] ), - .inport_wdata( reg_bank__inport_wdata[2] ), - .reset( reg_bank__reset[2] ), - .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[2] ), - .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[2] ), - .send_data_to_fu__val( reg_bank__send_data_to_fu__val[2] ) - ); - - RegisterBankRTL__ff0588d25abf2ed3 reg_bank__3 - ( - .clk( reg_bank__clk[3] ), - .inport_opt( reg_bank__inport_opt[3] ), - .inport_valid( reg_bank__inport_valid[3] ), - .inport_wdata( reg_bank__inport_wdata[3] ), - .reset( reg_bank__reset[3] ), - .send_data_to_fu__msg( reg_bank__send_data_to_fu__msg[3] ), - .send_data_to_fu__rdy( reg_bank__send_data_to_fu__rdy[3] ), - .send_data_to_fu__val( reg_bank__send_data_to_fu__val[3] ) - ); - - //------------------------------------------------------------- - // End of component reg_bank[0:3] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/mem/register_cluster/RegisterClusterRTL.py:45 - // @update - // def update_msgs_signals(): - // # Initializes signals. - // for i in range(num_reg_banks): - // s.send_data_to_fu[i].msg @= DataType() - // s.recv_data_from_routing_crossbar[i].rdy @= 0 - // s.recv_data_from_fu_crossbar[i].rdy @= 0 - // s.recv_data_from_const[i].rdy @= 0 - // s.send_data_to_fu[i].val @= 0 - // - // for i in range(num_reg_banks): - // if s.recv_data_from_routing_crossbar[i].val: - // s.send_data_to_fu[i].msg @= \ - // s.recv_data_from_routing_crossbar[i].msg - // else: - // s.send_data_to_fu[i].msg @= \ - // s.reg_bank[i].send_data_to_fu.msg - // - // s.send_data_to_fu[i].val @= \ - // s.recv_data_from_routing_crossbar[i].val | \ - // s.reg_bank[i].send_data_to_fu.val - // s.reg_bank[i].send_data_to_fu.rdy @= s.send_data_to_fu[i].rdy - // - // s.recv_data_from_routing_crossbar[i].rdy @= s.send_data_to_fu[i].rdy - // s.recv_data_from_fu_crossbar[i].rdy @= 1 - // s.recv_data_from_const[i].rdy @= 1 - - always_comb begin : update_msgs_signals - for ( int unsigned i = 1'd0; i < 3'( __const__num_reg_banks_at_update_msgs_signals ); i += 1'd1 ) begin - send_data_to_fu__msg[2'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - recv_data_from_routing_crossbar__rdy[2'(i)] = 1'd0; - recv_data_from_fu_crossbar__rdy[2'(i)] = 1'd0; - recv_data_from_const__rdy[2'(i)] = 1'd0; - send_data_to_fu__val[2'(i)] = 1'd0; - end - for ( int unsigned i = 1'd0; i < 3'( __const__num_reg_banks_at_update_msgs_signals ); i += 1'd1 ) begin - if ( recv_data_from_routing_crossbar__val[2'(i)] ) begin - send_data_to_fu__msg[2'(i)] = recv_data_from_routing_crossbar__msg[2'(i)]; - end - else - send_data_to_fu__msg[2'(i)] = reg_bank__send_data_to_fu__msg[2'(i)]; - send_data_to_fu__val[2'(i)] = recv_data_from_routing_crossbar__val[2'(i)] | reg_bank__send_data_to_fu__val[2'(i)]; - reg_bank__send_data_to_fu__rdy[2'(i)] = send_data_to_fu__rdy[2'(i)]; - recv_data_from_routing_crossbar__rdy[2'(i)] = send_data_to_fu__rdy[2'(i)]; - recv_data_from_fu_crossbar__rdy[2'(i)] = 1'd1; - recv_data_from_const__rdy[2'(i)] = 1'd1; - end - end - - assign reg_bank__clk[0] = clk; - assign reg_bank__reset[0] = reset; - assign reg_bank__clk[1] = clk; - assign reg_bank__reset[1] = reset; - assign reg_bank__clk[2] = clk; - assign reg_bank__reset[2] = reset; - assign reg_bank__clk[3] = clk; - assign reg_bank__reset[3] = reset; - assign reg_bank__inport_opt[0] = inport_opt; - assign reg_bank__inport_wdata[0][0] = recv_data_from_routing_crossbar__msg[0]; - assign reg_bank__inport_wdata[0][1] = recv_data_from_fu_crossbar__msg[0]; - assign reg_bank__inport_wdata[0][2] = recv_data_from_const__msg[0]; - assign reg_bank__inport_valid[0][0] = recv_data_from_routing_crossbar__val[0]; - assign reg_bank__inport_valid[0][1] = recv_data_from_fu_crossbar__val[0]; - assign reg_bank__inport_valid[0][2] = recv_data_from_const__val[0]; - assign reg_bank__inport_opt[1] = inport_opt; - assign reg_bank__inport_wdata[1][0] = recv_data_from_routing_crossbar__msg[1]; - assign reg_bank__inport_wdata[1][1] = recv_data_from_fu_crossbar__msg[1]; - assign reg_bank__inport_wdata[1][2] = recv_data_from_const__msg[1]; - assign reg_bank__inport_valid[1][0] = recv_data_from_routing_crossbar__val[1]; - assign reg_bank__inport_valid[1][1] = recv_data_from_fu_crossbar__val[1]; - assign reg_bank__inport_valid[1][2] = recv_data_from_const__val[1]; - assign reg_bank__inport_opt[2] = inport_opt; - assign reg_bank__inport_wdata[2][0] = recv_data_from_routing_crossbar__msg[2]; - assign reg_bank__inport_wdata[2][1] = recv_data_from_fu_crossbar__msg[2]; - assign reg_bank__inport_wdata[2][2] = recv_data_from_const__msg[2]; - assign reg_bank__inport_valid[2][0] = recv_data_from_routing_crossbar__val[2]; - assign reg_bank__inport_valid[2][1] = recv_data_from_fu_crossbar__val[2]; - assign reg_bank__inport_valid[2][2] = recv_data_from_const__val[2]; - assign reg_bank__inport_opt[3] = inport_opt; - assign reg_bank__inport_wdata[3][0] = recv_data_from_routing_crossbar__msg[3]; - assign reg_bank__inport_wdata[3][1] = recv_data_from_fu_crossbar__msg[3]; - assign reg_bank__inport_wdata[3][2] = recv_data_from_const__msg[3]; - assign reg_bank__inport_valid[3][0] = recv_data_from_routing_crossbar__val[3]; - assign reg_bank__inport_valid[3][1] = recv_data_from_fu_crossbar__val[3]; - assign reg_bank__inport_valid[3][2] = recv_data_from_const__val[3]; - -endmodule - - -// PyMTL Component CrossbarRTL Definition -// Full name: CrossbarRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__CtrlType_CGRAConfig_7_4_2_4_4_3__49d22cda396bec88__num_inports_4__num_outports_8__num_cgras_4__num_tiles_16__ctrl_mem_size_16__outport_towards_local_base_id_4 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py - -module CrossbarRTL__cad4150dfdc32fbd -( - input logic [1:0] cgra_id , - input logic [0:0] clear , - input logic [0:0] clk , - input logic [0:0] compute_done , - input logic [0:0] crossbar_id , - input logic [2:0] crossbar_outport [0:7], - input logic [3:0] ctrl_addr_inport , - input logic [2:0] prologue_count_inport [0:15][0:3], - input logic [0:0] reset , - input logic [4:0] tile_id , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:3] , - output logic [0:0] recv_data__rdy [0:3] , - input logic [0:0] recv_data__val [0:3] , - input CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 recv_opt__msg , - output logic [0:0] recv_opt__rdy , - input logic [0:0] recv_opt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:7] , - input logic [0:0] send_data__rdy [0:7] , - output logic [0:0] send_data__val [0:7] -); - localparam logic [2:0] __const__num_inports_at_update_signal = 3'd4; - localparam logic [3:0] __const__num_outports_at_update_signal = 4'd8; - localparam logic [6:0] __const__OPT_START = 7'd0; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter = 5'd16; - localparam logic [2:0] __const__num_inports_at_update_prologue_counter = 3'd4; - localparam logic [4:0] __const__ctrl_mem_size_at_update_prologue_counter_next = 5'd16; - localparam logic [2:0] __const__num_inports_at_update_prologue_counter_next = 3'd4; - localparam logic [3:0] __const__num_outports_at_update_prologue_counter_next = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_prologue_allowing_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_prologue_or_valid_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_in_dir_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_rdy_vector = 4'd8; - localparam logic [2:0] __const__outport_towards_local_base_id_at_update_rdy_vector = 3'd4; - localparam logic [3:0] __const__num_outports_at_update_valid_vector = 4'd8; - localparam logic [2:0] __const__num_inports_at_update_recv_required_vector = 3'd4; - localparam logic [3:0] __const__num_outports_at_update_recv_required_vector = 4'd8; - localparam logic [3:0] __const__num_outports_at_update_send_required_vector = 4'd8; - logic [2:0] in_dir [0:7]; - logic [1:0] in_dir_local [0:7]; - logic [7:0] prologue_allowing_vector; - logic [2:0] prologue_count_wire [0:15][0:3]; - logic [2:0] prologue_counter [0:15][0:3]; - logic [2:0] prologue_counter_next [0:15][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_msg [0:3]; - logic [0:0] recv_data_val [0:3]; - logic [3:0] recv_required_vector; - logic [7:0] recv_valid_or_prologue_allowing_vector; - logic [7:0] recv_valid_vector; - logic [7:0] send_rdy_vector; - logic [7:0] send_required_vector; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:153 - // @update - // def update_in_dir_vector(): - // - // for i in range(num_outports): - // s.in_dir[i] @= 0 - // s.in_dir_local[i] @= 0 - // - // for i in range(num_outports): - // s.in_dir[i] @= s.crossbar_outport[i] - // if s.in_dir[i] > 0: - // s.in_dir_local[i] @= trunc(s.in_dir[i] - 1, NumInportType) - - always_comb begin : update_in_dir_vector - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin - in_dir[3'(i)] = 3'd0; - in_dir_local[3'(i)] = 2'd0; - end - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_in_dir_vector ); i += 1'd1 ) begin - in_dir[3'(i)] = crossbar_outport[3'(i)]; - if ( in_dir[3'(i)] > 3'd0 ) begin - in_dir_local[3'(i)] = 2'(in_dir[3'(i)] - 3'd1); - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:134 - // @update - // def update_prologue_allowing_vector(): - // s.prologue_allowing_vector @= 0 - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // # Records whether the prologue steps have already been satisfied. - // s.prologue_allowing_vector[i] @= \ - // (s.prologue_counter[s.ctrl_addr_inport][s.in_dir_local[i]] < \ - // s.prologue_count_wire[s.ctrl_addr_inport][s.in_dir_local[i]]) - // else: - // s.prologue_allowing_vector[i] @= 1 - - always_comb begin : update_prologue_allowing_vector - prologue_allowing_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_allowing_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 3'd0 ) begin - prologue_allowing_vector[3'(i)] = prologue_counter[ctrl_addr_inport][in_dir_local[3'(i)]] < prologue_count_wire[ctrl_addr_inport][in_dir_local[3'(i)]]; - end - else - prologue_allowing_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:119 - // @update - // def update_prologue_counter_next(): - // # Nested-loop to update the prologue counter, to avoid dynamic indexing to - // # work-around Yosys issue: https://github.com/tancheng/VectorCGRA/issues/148 - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] - // for j in range(num_outports): - // if s.recv_opt.rdy & \ - // (s.in_dir[j] > 0) & \ - // (s.in_dir_local[j] == i) & \ - // (addr == s.ctrl_addr_inport) & \ - // (s.prologue_counter[addr][i] < s.prologue_count_wire[addr][i]): - // s.prologue_counter_next[addr][i] @= s.prologue_counter[addr][i] + 1 - - always_comb begin : update_prologue_counter_next - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter_next ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter_next ); i += 1'd1 ) begin - prologue_counter_next[4'(addr)][2'(i)] = prologue_counter[4'(addr)][2'(i)]; - for ( int unsigned j = 1'd0; j < 4'( __const__num_outports_at_update_prologue_counter_next ); j += 1'd1 ) - if ( ( ( ( recv_opt__rdy & ( in_dir[3'(j)] > 3'd0 ) ) & ( in_dir_local[3'(j)] == 2'(i) ) ) & ( 4'(addr) == ctrl_addr_inport ) ) & ( prologue_counter[4'(addr)][2'(i)] < prologue_count_wire[4'(addr)][2'(i)] ) ) begin - prologue_counter_next[4'(addr)][2'(i)] = prologue_counter[4'(addr)][2'(i)] + 3'd1; - end - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:146 - // @update - // def update_prologue_or_valid_vector(): - // s.recv_valid_or_prologue_allowing_vector @= 0 - // for i in range(num_outports): - // s.recv_valid_or_prologue_allowing_vector[i] @= \ - // s.recv_valid_vector[i] | s.prologue_allowing_vector[i] - - always_comb begin : update_prologue_or_valid_vector - recv_valid_or_prologue_allowing_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_prologue_or_valid_vector ); i += 1'd1 ) - recv_valid_or_prologue_allowing_vector[3'(i)] = recv_valid_vector[3'(i)] | prologue_allowing_vector[3'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:165 - // @update - // def update_rdy_vector(): - // s.send_rdy_vector @= 0 - // for i in range(num_outports): - // # The `num_inports` indicates the number of outports that go to other tiles. - // # Specifically, if the compute already done, we shouldn't care the ones - // # (i.e., i >= num_inports) go to the FU's inports. In other words, we skip - // # the rdy checking on the FU's inports (connecting from crossbar_outport) if - // # the compute is already completed. - // if (s.in_dir[i] > 0) & \ - // (~s.compute_done | (i < outport_towards_local_base_id)): - // s.send_rdy_vector[i] @= s.send_data[i].rdy - // else: - // s.send_rdy_vector[i] @= 1 - - always_comb begin : update_rdy_vector - send_rdy_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_rdy_vector ); i += 1'd1 ) - if ( ( in_dir[3'(i)] > 3'd0 ) & ( ( ~compute_done ) | ( 3'(i) < 3'( __const__outport_towards_local_base_id_at_update_rdy_vector ) ) ) ) begin - send_rdy_vector[3'(i)] = send_data__rdy[3'(i)]; - end - else - send_rdy_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:189 - // @update - // def update_recv_required_vector(): - // for i in range(num_inports): - // s.recv_required_vector[i] @= 0 - // - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.recv_required_vector[s.in_dir_local[i]] @= 1 - - always_comb begin : update_recv_required_vector - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_recv_required_vector ); i += 1'd1 ) - recv_required_vector[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_recv_required_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 3'd0 ) begin - recv_required_vector[in_dir_local[3'(i)]] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:198 - // @update - // def update_send_required_vector(): - // - // for i in range(num_outports): - // s.send_required_vector[i] @= 0 - // - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.send_required_vector[i] @= 1 - - always_comb begin : update_send_required_vector - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) - send_required_vector[3'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_send_required_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 3'd0 ) begin - send_required_vector[3'(i)] = 1'd1; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:82 - // @update - // def update_signal(): - // for i in range(num_inports): - // s.recv_data[i].rdy @= 0 - // for i in range(num_outports): - // s.send_data[i].val @= 0 - // s.send_data[i].msg @= DataType() - // s.recv_opt.rdy @= 0 - // - // if s.recv_opt.val & (s.recv_opt.msg.operation != OPT_START): - // for i in range(num_inports): - // s.recv_data[i].rdy @= reduce_and(s.recv_valid_vector) & \ - // reduce_and(s.send_rdy_vector) & \ - // s.recv_required_vector[i] - // - // for i in range(num_outports): - // s.send_data[i].val @= reduce_and(s.recv_valid_vector) & \ - // s.send_required_vector[i] - // if reduce_and(s.recv_valid_vector) & \ - // s.send_required_vector[i]: - // s.send_data[i].msg.payload @= s.recv_data_msg[s.in_dir_local[i]].payload - // s.send_data[i].msg.predicate @= s.recv_data_msg[s.in_dir_local[i]].predicate - // - // s.recv_opt.rdy @= reduce_and(s.send_rdy_vector) & \ - // reduce_and(s.recv_valid_or_prologue_allowing_vector) - - always_comb begin : update_signal - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) - recv_data__rdy[2'(i)] = 1'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin - send_data__val[3'(i)] = 1'd0; - send_data__msg[3'(i)] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - end - recv_opt__rdy = 1'd0; - if ( recv_opt__val & ( recv_opt__msg.operation != 7'( __const__OPT_START ) ) ) begin - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_signal ); i += 1'd1 ) - recv_data__rdy[2'(i)] = ( ( & recv_valid_vector ) & ( & send_rdy_vector ) ) & recv_required_vector[2'(i)]; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_signal ); i += 1'd1 ) begin - send_data__val[3'(i)] = ( & recv_valid_vector ) & send_required_vector[3'(i)]; - if ( ( & recv_valid_vector ) & send_required_vector[3'(i)] ) begin - send_data__msg[3'(i)].payload = recv_data_msg[in_dir_local[3'(i)]].payload; - send_data__msg[3'(i)].predicate = recv_data_msg[in_dir_local[3'(i)]].predicate; - end - end - recv_opt__rdy = ( & send_rdy_vector ) & ( & recv_valid_or_prologue_allowing_vector ); - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:180 - // @update - // def update_valid_vector(): - // s.recv_valid_vector @= 0 - // for i in range(num_outports): - // if s.in_dir[i] > 0: - // s.recv_valid_vector[i] @= s.recv_data_val[s.in_dir_local[i]] - // else: - // s.recv_valid_vector[i] @= 1 - - always_comb begin : update_valid_vector - recv_valid_vector = 8'd0; - for ( int unsigned i = 1'd0; i < 4'( __const__num_outports_at_update_valid_vector ); i += 1'd1 ) - if ( in_dir[3'(i)] > 3'd0 ) begin - recv_valid_vector[3'(i)] = recv_data_val[in_dir_local[3'(i)]]; - end - else - recv_valid_vector[3'(i)] = 1'd1; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/CrossbarRTL.py:108 - // @update_ff - // def update_prologue_counter(): - // if s.reset | s.clear: - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter[addr][i] <<= 0 - // else: - // for addr in range(ctrl_mem_size): - // for i in range(num_inports): - // s.prologue_counter[addr][i] <<= s.prologue_counter_next[addr][i] - - always_ff @(posedge clk) begin : update_prologue_counter - if ( reset | clear ) begin - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) - prologue_counter[4'(addr)][2'(i)] <= 3'd0; - end - else - for ( int unsigned addr = 1'd0; addr < 5'( __const__ctrl_mem_size_at_update_prologue_counter ); addr += 1'd1 ) - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_update_prologue_counter ); i += 1'd1 ) - prologue_counter[4'(addr)][2'(i)] <= prologue_counter_next[4'(addr)][2'(i)]; - end - - assign recv_data_msg[0] = recv_data__msg[0]; - assign recv_data_val[0] = recv_data__val[0]; - assign recv_data_msg[1] = recv_data__msg[1]; - assign recv_data_val[1] = recv_data__val[1]; - assign recv_data_msg[2] = recv_data__msg[2]; - assign recv_data_val[2] = recv_data__val[2]; - assign recv_data_msg[3] = recv_data__msg[3]; - assign recv_data_val[3] = recv_data__val[3]; - assign prologue_count_wire[0][0] = prologue_count_inport[0][0]; - assign prologue_count_wire[0][1] = prologue_count_inport[0][1]; - assign prologue_count_wire[0][2] = prologue_count_inport[0][2]; - assign prologue_count_wire[0][3] = prologue_count_inport[0][3]; - assign prologue_count_wire[1][0] = prologue_count_inport[1][0]; - assign prologue_count_wire[1][1] = prologue_count_inport[1][1]; - assign prologue_count_wire[1][2] = prologue_count_inport[1][2]; - assign prologue_count_wire[1][3] = prologue_count_inport[1][3]; - assign prologue_count_wire[2][0] = prologue_count_inport[2][0]; - assign prologue_count_wire[2][1] = prologue_count_inport[2][1]; - assign prologue_count_wire[2][2] = prologue_count_inport[2][2]; - assign prologue_count_wire[2][3] = prologue_count_inport[2][3]; - assign prologue_count_wire[3][0] = prologue_count_inport[3][0]; - assign prologue_count_wire[3][1] = prologue_count_inport[3][1]; - assign prologue_count_wire[3][2] = prologue_count_inport[3][2]; - assign prologue_count_wire[3][3] = prologue_count_inport[3][3]; - assign prologue_count_wire[4][0] = prologue_count_inport[4][0]; - assign prologue_count_wire[4][1] = prologue_count_inport[4][1]; - assign prologue_count_wire[4][2] = prologue_count_inport[4][2]; - assign prologue_count_wire[4][3] = prologue_count_inport[4][3]; - assign prologue_count_wire[5][0] = prologue_count_inport[5][0]; - assign prologue_count_wire[5][1] = prologue_count_inport[5][1]; - assign prologue_count_wire[5][2] = prologue_count_inport[5][2]; - assign prologue_count_wire[5][3] = prologue_count_inport[5][3]; - assign prologue_count_wire[6][0] = prologue_count_inport[6][0]; - assign prologue_count_wire[6][1] = prologue_count_inport[6][1]; - assign prologue_count_wire[6][2] = prologue_count_inport[6][2]; - assign prologue_count_wire[6][3] = prologue_count_inport[6][3]; - assign prologue_count_wire[7][0] = prologue_count_inport[7][0]; - assign prologue_count_wire[7][1] = prologue_count_inport[7][1]; - assign prologue_count_wire[7][2] = prologue_count_inport[7][2]; - assign prologue_count_wire[7][3] = prologue_count_inport[7][3]; - assign prologue_count_wire[8][0] = prologue_count_inport[8][0]; - assign prologue_count_wire[8][1] = prologue_count_inport[8][1]; - assign prologue_count_wire[8][2] = prologue_count_inport[8][2]; - assign prologue_count_wire[8][3] = prologue_count_inport[8][3]; - assign prologue_count_wire[9][0] = prologue_count_inport[9][0]; - assign prologue_count_wire[9][1] = prologue_count_inport[9][1]; - assign prologue_count_wire[9][2] = prologue_count_inport[9][2]; - assign prologue_count_wire[9][3] = prologue_count_inport[9][3]; - assign prologue_count_wire[10][0] = prologue_count_inport[10][0]; - assign prologue_count_wire[10][1] = prologue_count_inport[10][1]; - assign prologue_count_wire[10][2] = prologue_count_inport[10][2]; - assign prologue_count_wire[10][3] = prologue_count_inport[10][3]; - assign prologue_count_wire[11][0] = prologue_count_inport[11][0]; - assign prologue_count_wire[11][1] = prologue_count_inport[11][1]; - assign prologue_count_wire[11][2] = prologue_count_inport[11][2]; - assign prologue_count_wire[11][3] = prologue_count_inport[11][3]; - assign prologue_count_wire[12][0] = prologue_count_inport[12][0]; - assign prologue_count_wire[12][1] = prologue_count_inport[12][1]; - assign prologue_count_wire[12][2] = prologue_count_inport[12][2]; - assign prologue_count_wire[12][3] = prologue_count_inport[12][3]; - assign prologue_count_wire[13][0] = prologue_count_inport[13][0]; - assign prologue_count_wire[13][1] = prologue_count_inport[13][1]; - assign prologue_count_wire[13][2] = prologue_count_inport[13][2]; - assign prologue_count_wire[13][3] = prologue_count_inport[13][3]; - assign prologue_count_wire[14][0] = prologue_count_inport[14][0]; - assign prologue_count_wire[14][1] = prologue_count_inport[14][1]; - assign prologue_count_wire[14][2] = prologue_count_inport[14][2]; - assign prologue_count_wire[14][3] = prologue_count_inport[14][3]; - assign prologue_count_wire[15][0] = prologue_count_inport[15][0]; - assign prologue_count_wire[15][1] = prologue_count_inport[15][1]; - assign prologue_count_wire[15][2] = prologue_count_inport[15][2]; - assign prologue_count_wire[15][3] = prologue_count_inport[15][3]; - -endmodule - - -// PyMTL Component RegisterFile Definition -// Full name: RegisterFile__Type_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__nregs_2__rd_ports_1__wr_ports_1__const_zero_False -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py - -module RegisterFile__684a25db9dbebdb9 -( - input logic [0:0] clk , - input logic [0:0] raddr [0:0], - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rdata [0:0], - input logic [0:0] reset , - input logic [0:0] waddr [0:0], - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 wdata [0:0], - input logic [0:0] wen [0:0] -); - localparam logic [0:0] __const__rd_ports_at_up_rf_read = 1'd1; - localparam logic [0:0] __const__wr_ports_at_up_rf_write = 1'd1; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 regs [0:1]; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:20 - // @update - // def up_rf_read(): - // for i in range( rd_ports ): - // s.rdata[i] @= s.regs[ s.raddr[i] ] - - always_comb begin : up_rf_read - for ( int unsigned i = 1'd0; i < 1'( __const__rd_ports_at_up_rf_read ); i += 1'd1 ) - rdata[1'(i)] = regs[raddr[1'(i)]]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/register_files.py:32 - // @update_ff - // def up_rf_write(): - // for i in range( wr_ports ): - // if s.wen[i]: - // s.regs[ s.waddr[i] ] <<= s.wdata[i] - - always_ff @(posedge clk) begin : up_rf_write - for ( int unsigned i = 1'd0; i < 1'( __const__wr_ports_at_up_rf_write ); i += 1'd1 ) - if ( wen[1'(i)] ) begin - regs[waddr[1'(i)]] <= wdata[1'(i)]; - end - end - -endmodule - - -// PyMTL Component NormalQueueDpathRTL Definition -// Full name: NormalQueueDpathRTL__EntryType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueDpathRTL__43c9394e24dc368f -( - input logic [0:0] clk , - input logic [0:0] raddr , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_msg , - input logic [0:0] reset , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_msg , - input logic [0:0] waddr , - input logic [0:0] wen -); - //------------------------------------------------------------- - // Component rf - //------------------------------------------------------------- - - logic [0:0] rf__clk; - logic [0:0] rf__raddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rf__rdata [0:0]; - logic [0:0] rf__reset; - logic [0:0] rf__waddr [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 rf__wdata [0:0]; - logic [0:0] rf__wen [0:0]; - - RegisterFile__684a25db9dbebdb9 rf - ( - .clk( rf__clk ), - .raddr( rf__raddr ), - .rdata( rf__rdata ), - .reset( rf__reset ), - .waddr( rf__waddr ), - .wdata( rf__wdata ), - .wen( rf__wen ) - ); - - //------------------------------------------------------------- - // End of component rf - //------------------------------------------------------------- - - assign rf__clk = clk; - assign rf__reset = reset; - assign rf__raddr[0] = raddr; - assign send_msg = rf__rdata[0]; - assign rf__wen[0] = wen; - assign rf__waddr[0] = waddr; - assign rf__wdata[0] = recv_msg; - -endmodule - - -// PyMTL Component NormalQueueRTL Definition -// Full name: NormalQueueRTL__EntryType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__num_entries_2 -// At /home/ajokai/cgra/VectorCGRAfork0/lib/basic/val_rdy/queues.py - -module NormalQueueRTL__43c9394e24dc368f -( - input logic [0:0] clk , - output logic [1:0] count , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component ctrl - //------------------------------------------------------------- - - logic [0:0] ctrl__clk; - logic [1:0] ctrl__count; - logic [0:0] ctrl__raddr; - logic [0:0] ctrl__recv_rdy; - logic [0:0] ctrl__recv_val; - logic [0:0] ctrl__reset; - logic [0:0] ctrl__send_rdy; - logic [0:0] ctrl__send_val; - logic [0:0] ctrl__waddr; - logic [0:0] ctrl__wen; - - NormalQueueCtrlRTL__num_entries_2 ctrl - ( - .clk( ctrl__clk ), - .count( ctrl__count ), - .raddr( ctrl__raddr ), - .recv_rdy( ctrl__recv_rdy ), - .recv_val( ctrl__recv_val ), - .reset( ctrl__reset ), - .send_rdy( ctrl__send_rdy ), - .send_val( ctrl__send_val ), - .waddr( ctrl__waddr ), - .wen( ctrl__wen ) - ); - - //------------------------------------------------------------- - // End of component ctrl - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component dpath - //------------------------------------------------------------- - - logic [0:0] dpath__clk; - logic [0:0] dpath__raddr; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 dpath__recv_msg; - logic [0:0] dpath__reset; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 dpath__send_msg; - logic [0:0] dpath__waddr; - logic [0:0] dpath__wen; - - NormalQueueDpathRTL__43c9394e24dc368f dpath - ( - .clk( dpath__clk ), - .raddr( dpath__raddr ), - .recv_msg( dpath__recv_msg ), - .reset( dpath__reset ), - .send_msg( dpath__send_msg ), - .waddr( dpath__waddr ), - .wen( dpath__wen ) - ); - - //------------------------------------------------------------- - // End of component dpath - //------------------------------------------------------------- - - assign ctrl__clk = clk; - assign ctrl__reset = reset; - assign dpath__clk = clk; - assign dpath__reset = reset; - assign dpath__wen = ctrl__wen; - assign dpath__waddr = ctrl__waddr; - assign dpath__raddr = ctrl__raddr; - assign ctrl__recv_val = recv__val; - assign recv__rdy = ctrl__recv_rdy; - assign dpath__recv_msg = recv__msg; - assign send__val = ctrl__send_val; - assign ctrl__send_rdy = send__rdy; - assign send__msg = dpath__send_msg; - assign count = ctrl__count; - -endmodule - - -// PyMTL Component ChannelRTL Definition -// Full name: ChannelRTL__PacketType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1__QueueType_NormalQueueRTL__latency_1 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/channel/ChannelRTL.py - -module ChannelRTL__694d252f21ac798b -( - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queues[0:0] - //------------------------------------------------------------- - - logic [0:0] queues__clk [0:0]; - logic [1:0] queues__count [0:0]; - logic [0:0] queues__reset [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 queues__recv__msg [0:0]; - logic [0:0] queues__recv__rdy [0:0]; - logic [0:0] queues__recv__val [0:0]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 queues__send__msg [0:0]; - logic [0:0] queues__send__rdy [0:0]; - logic [0:0] queues__send__val [0:0]; - - NormalQueueRTL__43c9394e24dc368f queues__0 - ( - .clk( queues__clk[0] ), - .count( queues__count[0] ), - .reset( queues__reset[0] ), - .recv__msg( queues__recv__msg[0] ), - .recv__rdy( queues__recv__rdy[0] ), - .recv__val( queues__recv__val[0] ), - .send__msg( queues__send__msg[0] ), - .send__rdy( queues__send__rdy[0] ), - .send__val( queues__send__val[0] ) - ); - - //------------------------------------------------------------- - // End of component queues[0:0] - //------------------------------------------------------------- - - assign queues__clk[0] = clk; - assign queues__reset[0] = reset; - assign queues__recv__msg[0] = recv__msg; - assign recv__rdy = queues__recv__rdy[0]; - assign queues__recv__val[0] = recv__val; - assign send__msg = queues__send__msg[0]; - assign queues__send__rdy[0] = send__rdy; - assign send__val = queues__send__val[0]; - -endmodule - - -// PyMTL Component LinkOrRTL Definition -// Full name: LinkOrRTL__DataType_CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/LinkOrRTL.py - -module LinkOrRTL__0fce34ff986f61fe -( - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_fu__msg , - output logic [0:0] recv_fu__rdy , - input logic [0:0] recv_fu__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_xbar__msg , - output logic [0:0] recv_xbar__rdy , - input logic [0:0] recv_xbar__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/LinkOrRTL.py:28 - // @update - // def process(): - // # Initializes the delivered message. - // s.send.msg @= DataType() - // - // # The messages from two sources (i.e., xbar and FU) won't be valid - // # simultaneously (confliction would be caused if they both are valid), - // # which is guaranteed by the compiler/software. - // s.send.msg.predicate @= s.recv_fu.msg.predicate | s.recv_xbar.msg.predicate - // s.send.msg.payload @= s.recv_xbar.msg.payload | s.recv_fu.msg.payload - // - // # FIXME: bypass won't be necessary any more with separate xbar design. - // # s.send.msg.bypass @= 0 - // # s.send.msg.delay @= s.recv_fu.msg.delay | s.recv_xbar.msg.delay - // - // # s.send.val @= s.send.rdy & (s.recv_fu.val | s.recv_xbar.val) - // s.send.val @= s.recv_fu.val | s.recv_xbar.val - // s.recv_fu.rdy @= s.send.rdy - // s.recv_xbar.rdy @= s.send.rdy - - always_comb begin : process - send__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - send__msg.predicate = recv_fu__msg.predicate | recv_xbar__msg.predicate; - send__msg.payload = recv_xbar__msg.payload | recv_fu__msg.payload; - send__val = recv_fu__val | recv_xbar__val; - recv_fu__rdy = send__rdy; - recv_xbar__rdy = send__rdy; - end - -endmodule - - -// PyMTL Component TileRTL Definition -// Full name: TileRTL__IntraCgraPktType_IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69__ctrl_mem_size_16__data_mem_size_128__num_ctrl_4__total_steps_38__num_fu_inports_4__num_fu_outports_2__num_tile_inports_4__num_tile_outports_4__num_cgras_4__num_tiles_16__num_registers_per_reg_bank_16__Fu_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ] -// At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py - -module TileRTL__78da5e3970e1cd1d -( - input logic [1:0] cgra_id , - input logic [0:0] clk , - input logic [0:0] reset , - input logic [4:0] tile_id , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 from_mem_rdata__msg , - output logic [0:0] from_mem_rdata__rdy , - input logic [0:0] from_mem_rdata__val , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data__msg [0:3] , - output logic [0:0] recv_data__rdy [0:3] , - input logic [0:0] recv_data__val [0:3] , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_controller_pkt__msg , - output logic [0:0] recv_from_controller_pkt__rdy , - input logic [0:0] recv_from_controller_pkt__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data__msg [0:3] , - input logic [0:0] send_data__rdy [0:3] , - output logic [0:0] send_data__val [0:3] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_controller_pkt__msg , - input logic [0:0] send_to_controller_pkt__rdy , - output logic [0:0] send_to_controller_pkt__val , - output logic [6:0] to_mem_raddr__msg , - input logic [0:0] to_mem_raddr__rdy , - output logic [0:0] to_mem_raddr__val , - output logic [6:0] to_mem_waddr__msg , - input logic [0:0] to_mem_waddr__rdy , - output logic [0:0] to_mem_waddr__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 to_mem_wdata__msg , - input logic [0:0] to_mem_wdata__rdy , - output logic [0:0] to_mem_wdata__val -); - localparam logic [1:0] __const__CMD_CONFIG = 2'd3; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU = 3'd4; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR = 3'd5; - localparam logic [2:0] __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR = 3'd6; - localparam logic [2:0] __const__CMD_CONFIG_TOTAL_CTRL_COUNT = 3'd7; - localparam logic [3:0] __const__CMD_CONFIG_COUNT_PER_ITER = 4'd8; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE = 5'd20; - localparam logic [4:0] __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE = 5'd21; - localparam logic [0:0] __const__CMD_LAUNCH = 1'd0; - localparam logic [3:0] __const__CMD_CONST = 4'd13; - logic [0:0] element_done; - logic [0:0] fu_crossbar_done; - logic [0:0] routing_crossbar_done; - //------------------------------------------------------------- - // Component const_mem - //------------------------------------------------------------- - - logic [0:0] const_mem__clear; - logic [0:0] const_mem__clk; - logic [0:0] const_mem__ctrl_proceed; - logic [0:0] const_mem__reset; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_mem__recv_const__msg; - logic [0:0] const_mem__recv_const__rdy; - logic [0:0] const_mem__recv_const__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 const_mem__send_const__msg; - logic [0:0] const_mem__send_const__rdy; - logic [0:0] const_mem__send_const__val; - - ConstQueueDynamicRTL__9d3397f72f19af52 const_mem - ( - .clear( const_mem__clear ), - .clk( const_mem__clk ), - .ctrl_proceed( const_mem__ctrl_proceed ), - .reset( const_mem__reset ), - .recv_const__msg( const_mem__recv_const__msg ), - .recv_const__rdy( const_mem__recv_const__rdy ), - .recv_const__val( const_mem__recv_const__val ), - .send_const__msg( const_mem__send_const__msg ), - .send_const__rdy( const_mem__send_const__rdy ), - .send_const__val( const_mem__send_const__val ) - ); - - //------------------------------------------------------------- - // End of component const_mem - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component ctrl_mem - //------------------------------------------------------------- - - logic [1:0] ctrl_mem__cgra_id; - logic [0:0] ctrl_mem__clk; - logic [3:0] ctrl_mem__ctrl_addr_outport; - logic [2:0] ctrl_mem__prologue_count_outport_fu; - logic [2:0] ctrl_mem__prologue_count_outport_fu_crossbar [0:15][0:1]; - logic [2:0] ctrl_mem__prologue_count_outport_routing_crossbar [0:15][0:3]; - logic [0:0] ctrl_mem__reset; - logic [4:0] ctrl_mem__tile_id; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a ctrl_mem__recv_from_element__msg; - logic [0:0] ctrl_mem__recv_from_element__rdy; - logic [0:0] ctrl_mem__recv_from_element__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_mem__recv_pkt_from_controller__msg; - logic [0:0] ctrl_mem__recv_pkt_from_controller__rdy; - logic [0:0] ctrl_mem__recv_pkt_from_controller__val; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 ctrl_mem__send_ctrl__msg; - logic [0:0] ctrl_mem__send_ctrl__rdy; - logic [0:0] ctrl_mem__send_ctrl__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_mem__send_pkt_to_controller__msg; - logic [0:0] ctrl_mem__send_pkt_to_controller__rdy; - logic [0:0] ctrl_mem__send_pkt_to_controller__val; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a ctrl_mem__send_to_element__msg; - logic [0:0] ctrl_mem__send_to_element__rdy; - logic [0:0] ctrl_mem__send_to_element__val; - - CtrlMemDynamicRTL__427d547b7d58aa8e ctrl_mem - ( - .cgra_id( ctrl_mem__cgra_id ), - .clk( ctrl_mem__clk ), - .ctrl_addr_outport( ctrl_mem__ctrl_addr_outport ), - .prologue_count_outport_fu( ctrl_mem__prologue_count_outport_fu ), - .prologue_count_outport_fu_crossbar( ctrl_mem__prologue_count_outport_fu_crossbar ), - .prologue_count_outport_routing_crossbar( ctrl_mem__prologue_count_outport_routing_crossbar ), - .reset( ctrl_mem__reset ), - .tile_id( ctrl_mem__tile_id ), - .recv_from_element__msg( ctrl_mem__recv_from_element__msg ), - .recv_from_element__rdy( ctrl_mem__recv_from_element__rdy ), - .recv_from_element__val( ctrl_mem__recv_from_element__val ), - .recv_pkt_from_controller__msg( ctrl_mem__recv_pkt_from_controller__msg ), - .recv_pkt_from_controller__rdy( ctrl_mem__recv_pkt_from_controller__rdy ), - .recv_pkt_from_controller__val( ctrl_mem__recv_pkt_from_controller__val ), - .send_ctrl__msg( ctrl_mem__send_ctrl__msg ), - .send_ctrl__rdy( ctrl_mem__send_ctrl__rdy ), - .send_ctrl__val( ctrl_mem__send_ctrl__val ), - .send_pkt_to_controller__msg( ctrl_mem__send_pkt_to_controller__msg ), - .send_pkt_to_controller__rdy( ctrl_mem__send_pkt_to_controller__rdy ), - .send_pkt_to_controller__val( ctrl_mem__send_pkt_to_controller__val ), - .send_to_element__msg( ctrl_mem__send_to_element__msg ), - .send_to_element__rdy( ctrl_mem__send_to_element__rdy ), - .send_to_element__val( ctrl_mem__send_to_element__val ) - ); - - //------------------------------------------------------------- - // End of component ctrl_mem - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component element - //------------------------------------------------------------- - - logic [0:0] element__clear [0:14]; - logic [0:0] element__clk; - logic [2:0] element__prologue_count_inport; - logic [0:0] element__reset; - logic [4:0] element__tile_id; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__from_mem_rdata__msg [0:14]; - logic [0:0] element__from_mem_rdata__rdy [0:14]; - logic [0:0] element__from_mem_rdata__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__recv_const__msg; - logic [0:0] element__recv_const__rdy; - logic [0:0] element__recv_const__val; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a element__recv_from_ctrl_mem__msg; - logic [0:0] element__recv_from_ctrl_mem__rdy; - logic [0:0] element__recv_from_ctrl_mem__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__recv_in__msg [0:3]; - logic [0:0] element__recv_in__rdy [0:3]; - logic [0:0] element__recv_in__val [0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 element__recv_opt__msg; - logic [0:0] element__recv_opt__rdy; - logic [0:0] element__recv_opt__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__send_out__msg [0:1]; - logic [0:0] element__send_out__rdy [0:1]; - logic [0:0] element__send_out__val [0:1]; - MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a element__send_to_ctrl_mem__msg; - logic [0:0] element__send_to_ctrl_mem__rdy; - logic [0:0] element__send_to_ctrl_mem__val; - logic [6:0] element__to_mem_raddr__msg [0:14]; - logic [0:0] element__to_mem_raddr__rdy [0:14]; - logic [0:0] element__to_mem_raddr__val [0:14]; - logic [6:0] element__to_mem_waddr__msg [0:14]; - logic [0:0] element__to_mem_waddr__rdy [0:14]; - logic [0:0] element__to_mem_waddr__val [0:14]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 element__to_mem_wdata__msg [0:14]; - logic [0:0] element__to_mem_wdata__rdy [0:14]; - logic [0:0] element__to_mem_wdata__val [0:14]; - - FlexibleFuRTL__07217382918d0fc2 element - ( - .clear( element__clear ), - .clk( element__clk ), - .prologue_count_inport( element__prologue_count_inport ), - .reset( element__reset ), - .tile_id( element__tile_id ), - .from_mem_rdata__msg( element__from_mem_rdata__msg ), - .from_mem_rdata__rdy( element__from_mem_rdata__rdy ), - .from_mem_rdata__val( element__from_mem_rdata__val ), - .recv_const__msg( element__recv_const__msg ), - .recv_const__rdy( element__recv_const__rdy ), - .recv_const__val( element__recv_const__val ), - .recv_from_ctrl_mem__msg( element__recv_from_ctrl_mem__msg ), - .recv_from_ctrl_mem__rdy( element__recv_from_ctrl_mem__rdy ), - .recv_from_ctrl_mem__val( element__recv_from_ctrl_mem__val ), - .recv_in__msg( element__recv_in__msg ), - .recv_in__rdy( element__recv_in__rdy ), - .recv_in__val( element__recv_in__val ), - .recv_opt__msg( element__recv_opt__msg ), - .recv_opt__rdy( element__recv_opt__rdy ), - .recv_opt__val( element__recv_opt__val ), - .send_out__msg( element__send_out__msg ), - .send_out__rdy( element__send_out__rdy ), - .send_out__val( element__send_out__val ), - .send_to_ctrl_mem__msg( element__send_to_ctrl_mem__msg ), - .send_to_ctrl_mem__rdy( element__send_to_ctrl_mem__rdy ), - .send_to_ctrl_mem__val( element__send_to_ctrl_mem__val ), - .to_mem_raddr__msg( element__to_mem_raddr__msg ), - .to_mem_raddr__rdy( element__to_mem_raddr__rdy ), - .to_mem_raddr__val( element__to_mem_raddr__val ), - .to_mem_waddr__msg( element__to_mem_waddr__msg ), - .to_mem_waddr__rdy( element__to_mem_waddr__rdy ), - .to_mem_waddr__val( element__to_mem_waddr__val ), - .to_mem_wdata__msg( element__to_mem_wdata__msg ), - .to_mem_wdata__rdy( element__to_mem_wdata__rdy ), - .to_mem_wdata__val( element__to_mem_wdata__val ) - ); - - //------------------------------------------------------------- - // End of component element - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component fu_crossbar - //------------------------------------------------------------- - - logic [1:0] fu_crossbar__cgra_id; - logic [0:0] fu_crossbar__clear; - logic [0:0] fu_crossbar__clk; - logic [0:0] fu_crossbar__compute_done; - logic [0:0] fu_crossbar__crossbar_id; - logic [1:0] fu_crossbar__crossbar_outport [0:7]; - logic [3:0] fu_crossbar__ctrl_addr_inport; - logic [2:0] fu_crossbar__prologue_count_inport [0:15][0:1]; - logic [0:0] fu_crossbar__reset; - logic [4:0] fu_crossbar__tile_id; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu_crossbar__recv_data__msg [0:1]; - logic [0:0] fu_crossbar__recv_data__rdy [0:1]; - logic [0:0] fu_crossbar__recv_data__val [0:1]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 fu_crossbar__recv_opt__msg; - logic [0:0] fu_crossbar__recv_opt__rdy; - logic [0:0] fu_crossbar__recv_opt__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 fu_crossbar__send_data__msg [0:7]; - logic [0:0] fu_crossbar__send_data__rdy [0:7]; - logic [0:0] fu_crossbar__send_data__val [0:7]; - - CrossbarRTL__45ee026205c61975 fu_crossbar - ( - .cgra_id( fu_crossbar__cgra_id ), - .clear( fu_crossbar__clear ), - .clk( fu_crossbar__clk ), - .compute_done( fu_crossbar__compute_done ), - .crossbar_id( fu_crossbar__crossbar_id ), - .crossbar_outport( fu_crossbar__crossbar_outport ), - .ctrl_addr_inport( fu_crossbar__ctrl_addr_inport ), - .prologue_count_inport( fu_crossbar__prologue_count_inport ), - .reset( fu_crossbar__reset ), - .tile_id( fu_crossbar__tile_id ), - .recv_data__msg( fu_crossbar__recv_data__msg ), - .recv_data__rdy( fu_crossbar__recv_data__rdy ), - .recv_data__val( fu_crossbar__recv_data__val ), - .recv_opt__msg( fu_crossbar__recv_opt__msg ), - .recv_opt__rdy( fu_crossbar__recv_opt__rdy ), - .recv_opt__val( fu_crossbar__recv_opt__val ), - .send_data__msg( fu_crossbar__send_data__msg ), - .send_data__rdy( fu_crossbar__send_data__rdy ), - .send_data__val( fu_crossbar__send_data__val ) - ); - - //------------------------------------------------------------- - // End of component fu_crossbar - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component register_cluster - //------------------------------------------------------------- - - logic [0:0] register_cluster__clk; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 register_cluster__inport_opt; - logic [0:0] register_cluster__reset; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_const__msg [0:3]; - logic [0:0] register_cluster__recv_data_from_const__rdy [0:3]; - logic [0:0] register_cluster__recv_data_from_const__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_fu_crossbar__msg [0:3]; - logic [0:0] register_cluster__recv_data_from_fu_crossbar__rdy [0:3]; - logic [0:0] register_cluster__recv_data_from_fu_crossbar__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__recv_data_from_routing_crossbar__msg [0:3]; - logic [0:0] register_cluster__recv_data_from_routing_crossbar__rdy [0:3]; - logic [0:0] register_cluster__recv_data_from_routing_crossbar__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 register_cluster__send_data_to_fu__msg [0:3]; - logic [0:0] register_cluster__send_data_to_fu__rdy [0:3]; - logic [0:0] register_cluster__send_data_to_fu__val [0:3]; - - RegisterClusterRTL__7f2febb613462546 register_cluster - ( - .clk( register_cluster__clk ), - .inport_opt( register_cluster__inport_opt ), - .reset( register_cluster__reset ), - .recv_data_from_const__msg( register_cluster__recv_data_from_const__msg ), - .recv_data_from_const__rdy( register_cluster__recv_data_from_const__rdy ), - .recv_data_from_const__val( register_cluster__recv_data_from_const__val ), - .recv_data_from_fu_crossbar__msg( register_cluster__recv_data_from_fu_crossbar__msg ), - .recv_data_from_fu_crossbar__rdy( register_cluster__recv_data_from_fu_crossbar__rdy ), - .recv_data_from_fu_crossbar__val( register_cluster__recv_data_from_fu_crossbar__val ), - .recv_data_from_routing_crossbar__msg( register_cluster__recv_data_from_routing_crossbar__msg ), - .recv_data_from_routing_crossbar__rdy( register_cluster__recv_data_from_routing_crossbar__rdy ), - .recv_data_from_routing_crossbar__val( register_cluster__recv_data_from_routing_crossbar__val ), - .send_data_to_fu__msg( register_cluster__send_data_to_fu__msg ), - .send_data_to_fu__rdy( register_cluster__send_data_to_fu__rdy ), - .send_data_to_fu__val( register_cluster__send_data_to_fu__val ) - ); - - //------------------------------------------------------------- - // End of component register_cluster - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component routing_crossbar - //------------------------------------------------------------- - - logic [1:0] routing_crossbar__cgra_id; - logic [0:0] routing_crossbar__clear; - logic [0:0] routing_crossbar__clk; - logic [0:0] routing_crossbar__compute_done; - logic [0:0] routing_crossbar__crossbar_id; - logic [2:0] routing_crossbar__crossbar_outport [0:7]; - logic [3:0] routing_crossbar__ctrl_addr_inport; - logic [2:0] routing_crossbar__prologue_count_inport [0:15][0:3]; - logic [0:0] routing_crossbar__reset; - logic [4:0] routing_crossbar__tile_id; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 routing_crossbar__recv_data__msg [0:3]; - logic [0:0] routing_crossbar__recv_data__rdy [0:3]; - logic [0:0] routing_crossbar__recv_data__val [0:3]; - CGRAConfig_7_4_2_4_4_3__49d22cda396bec88 routing_crossbar__recv_opt__msg; - logic [0:0] routing_crossbar__recv_opt__rdy; - logic [0:0] routing_crossbar__recv_opt__val; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 routing_crossbar__send_data__msg [0:7]; - logic [0:0] routing_crossbar__send_data__rdy [0:7]; - logic [0:0] routing_crossbar__send_data__val [0:7]; - - CrossbarRTL__cad4150dfdc32fbd routing_crossbar - ( - .cgra_id( routing_crossbar__cgra_id ), - .clear( routing_crossbar__clear ), - .clk( routing_crossbar__clk ), - .compute_done( routing_crossbar__compute_done ), - .crossbar_id( routing_crossbar__crossbar_id ), - .crossbar_outport( routing_crossbar__crossbar_outport ), - .ctrl_addr_inport( routing_crossbar__ctrl_addr_inport ), - .prologue_count_inport( routing_crossbar__prologue_count_inport ), - .reset( routing_crossbar__reset ), - .tile_id( routing_crossbar__tile_id ), - .recv_data__msg( routing_crossbar__recv_data__msg ), - .recv_data__rdy( routing_crossbar__recv_data__rdy ), - .recv_data__val( routing_crossbar__recv_data__val ), - .recv_opt__msg( routing_crossbar__recv_opt__msg ), - .recv_opt__rdy( routing_crossbar__recv_opt__rdy ), - .recv_opt__val( routing_crossbar__recv_opt__val ), - .send_data__msg( routing_crossbar__send_data__msg ), - .send_data__rdy( routing_crossbar__send_data__rdy ), - .send_data__val( routing_crossbar__send_data__val ) - ); - - //------------------------------------------------------------- - // End of component routing_crossbar - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component tile_in_channel[0:3] - //------------------------------------------------------------- - - logic [0:0] tile_in_channel__clk [0:3]; - logic [0:0] tile_in_channel__reset [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_in_channel__recv__msg [0:3]; - logic [0:0] tile_in_channel__recv__rdy [0:3]; - logic [0:0] tile_in_channel__recv__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_in_channel__send__msg [0:3]; - logic [0:0] tile_in_channel__send__rdy [0:3]; - logic [0:0] tile_in_channel__send__val [0:3]; - - ChannelRTL__694d252f21ac798b tile_in_channel__0 - ( - .clk( tile_in_channel__clk[0] ), - .reset( tile_in_channel__reset[0] ), - .recv__msg( tile_in_channel__recv__msg[0] ), - .recv__rdy( tile_in_channel__recv__rdy[0] ), - .recv__val( tile_in_channel__recv__val[0] ), - .send__msg( tile_in_channel__send__msg[0] ), - .send__rdy( tile_in_channel__send__rdy[0] ), - .send__val( tile_in_channel__send__val[0] ) - ); - - ChannelRTL__694d252f21ac798b tile_in_channel__1 - ( - .clk( tile_in_channel__clk[1] ), - .reset( tile_in_channel__reset[1] ), - .recv__msg( tile_in_channel__recv__msg[1] ), - .recv__rdy( tile_in_channel__recv__rdy[1] ), - .recv__val( tile_in_channel__recv__val[1] ), - .send__msg( tile_in_channel__send__msg[1] ), - .send__rdy( tile_in_channel__send__rdy[1] ), - .send__val( tile_in_channel__send__val[1] ) - ); - - ChannelRTL__694d252f21ac798b tile_in_channel__2 - ( - .clk( tile_in_channel__clk[2] ), - .reset( tile_in_channel__reset[2] ), - .recv__msg( tile_in_channel__recv__msg[2] ), - .recv__rdy( tile_in_channel__recv__rdy[2] ), - .recv__val( tile_in_channel__recv__val[2] ), - .send__msg( tile_in_channel__send__msg[2] ), - .send__rdy( tile_in_channel__send__rdy[2] ), - .send__val( tile_in_channel__send__val[2] ) - ); - - ChannelRTL__694d252f21ac798b tile_in_channel__3 - ( - .clk( tile_in_channel__clk[3] ), - .reset( tile_in_channel__reset[3] ), - .recv__msg( tile_in_channel__recv__msg[3] ), - .recv__rdy( tile_in_channel__recv__rdy[3] ), - .recv__val( tile_in_channel__recv__val[3] ), - .send__msg( tile_in_channel__send__msg[3] ), - .send__rdy( tile_in_channel__send__rdy[3] ), - .send__val( tile_in_channel__send__val[3] ) - ); - - //------------------------------------------------------------- - // End of component tile_in_channel[0:3] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component tile_out_or_link[0:3] - //------------------------------------------------------------- - - logic [0:0] tile_out_or_link__clk [0:3]; - logic [0:0] tile_out_or_link__reset [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__recv_fu__msg [0:3]; - logic [0:0] tile_out_or_link__recv_fu__rdy [0:3]; - logic [0:0] tile_out_or_link__recv_fu__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__recv_xbar__msg [0:3]; - logic [0:0] tile_out_or_link__recv_xbar__rdy [0:3]; - logic [0:0] tile_out_or_link__recv_xbar__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile_out_or_link__send__msg [0:3]; - logic [0:0] tile_out_or_link__send__rdy [0:3]; - logic [0:0] tile_out_or_link__send__val [0:3]; - - LinkOrRTL__0fce34ff986f61fe tile_out_or_link__0 - ( - .clk( tile_out_or_link__clk[0] ), - .reset( tile_out_or_link__reset[0] ), - .recv_fu__msg( tile_out_or_link__recv_fu__msg[0] ), - .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[0] ), - .recv_fu__val( tile_out_or_link__recv_fu__val[0] ), - .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[0] ), - .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[0] ), - .recv_xbar__val( tile_out_or_link__recv_xbar__val[0] ), - .send__msg( tile_out_or_link__send__msg[0] ), - .send__rdy( tile_out_or_link__send__rdy[0] ), - .send__val( tile_out_or_link__send__val[0] ) - ); - - LinkOrRTL__0fce34ff986f61fe tile_out_or_link__1 - ( - .clk( tile_out_or_link__clk[1] ), - .reset( tile_out_or_link__reset[1] ), - .recv_fu__msg( tile_out_or_link__recv_fu__msg[1] ), - .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[1] ), - .recv_fu__val( tile_out_or_link__recv_fu__val[1] ), - .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[1] ), - .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[1] ), - .recv_xbar__val( tile_out_or_link__recv_xbar__val[1] ), - .send__msg( tile_out_or_link__send__msg[1] ), - .send__rdy( tile_out_or_link__send__rdy[1] ), - .send__val( tile_out_or_link__send__val[1] ) - ); - - LinkOrRTL__0fce34ff986f61fe tile_out_or_link__2 - ( - .clk( tile_out_or_link__clk[2] ), - .reset( tile_out_or_link__reset[2] ), - .recv_fu__msg( tile_out_or_link__recv_fu__msg[2] ), - .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[2] ), - .recv_fu__val( tile_out_or_link__recv_fu__val[2] ), - .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[2] ), - .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[2] ), - .recv_xbar__val( tile_out_or_link__recv_xbar__val[2] ), - .send__msg( tile_out_or_link__send__msg[2] ), - .send__rdy( tile_out_or_link__send__rdy[2] ), - .send__val( tile_out_or_link__send__val[2] ) - ); - - LinkOrRTL__0fce34ff986f61fe tile_out_or_link__3 - ( - .clk( tile_out_or_link__clk[3] ), - .reset( tile_out_or_link__reset[3] ), - .recv_fu__msg( tile_out_or_link__recv_fu__msg[3] ), - .recv_fu__rdy( tile_out_or_link__recv_fu__rdy[3] ), - .recv_fu__val( tile_out_or_link__recv_fu__val[3] ), - .recv_xbar__msg( tile_out_or_link__recv_xbar__msg[3] ), - .recv_xbar__rdy( tile_out_or_link__recv_xbar__rdy[3] ), - .recv_xbar__val( tile_out_or_link__recv_xbar__val[3] ), - .send__msg( tile_out_or_link__send__msg[3] ), - .send__rdy( tile_out_or_link__send__rdy[3] ), - .send__val( tile_out_or_link__send__val[3] ) - ); - - //------------------------------------------------------------- - // End of component tile_out_or_link[0:3] - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:236 - // @update - // def feed_pkt(): - // s.ctrl_mem.recv_pkt_from_controller.msg @= CtrlPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) # , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // s.const_mem.recv_const.msg @= DataType(0, 0, 0, 0) - // s.ctrl_mem.recv_pkt_from_controller.val @= 0 - // s.const_mem.recv_const.val @= 0 - // s.recv_from_controller_pkt.rdy @= 0 - // - // if s.recv_from_controller_pkt.val & \ - // ((s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_FU_CROSSBAR) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_TOTAL_CTRL_COUNT) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONFIG_COUNT_PER_ITER) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_GLOBAL_REDUCE_ADD_RESPONSE) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_GLOBAL_REDUCE_MUL_RESPONSE) | \ - // (s.recv_from_controller_pkt.msg.payload.cmd == CMD_LAUNCH)): - // s.ctrl_mem.recv_pkt_from_controller.val @= 1 - // s.ctrl_mem.recv_pkt_from_controller.msg @= s.recv_from_controller_pkt.msg - // s.recv_from_controller_pkt.rdy @= s.ctrl_mem.recv_pkt_from_controller.rdy - // elif s.recv_from_controller_pkt.val & (s.recv_from_controller_pkt.msg.payload.cmd == CMD_CONST): - // s.const_mem.recv_const.val @= 1 - // s.const_mem.recv_const.msg @= s.recv_from_controller_pkt.msg.payload.data - // s.recv_from_controller_pkt.rdy @= s.const_mem.recv_const.rdy - - always_comb begin : feed_pkt - ctrl_mem__recv_pkt_from_controller__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; - const_mem__recv_const__msg = { 64'd0, 1'd0, 1'd0, 1'd0 }; - ctrl_mem__recv_pkt_from_controller__val = 1'd0; - const_mem__recv_const__val = 1'd0; - recv_from_controller_pkt__rdy = 1'd0; - if ( recv_from_controller_pkt__val & ( ( ( ( ( ( ( ( ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_FU_CROSSBAR ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_PROLOGUE_ROUTING_CROSSBAR ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_TOTAL_CTRL_COUNT ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONFIG_COUNT_PER_ITER ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_ADD_RESPONSE ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_GLOBAL_REDUCE_MUL_RESPONSE ) ) ) | ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_LAUNCH ) ) ) ) begin - ctrl_mem__recv_pkt_from_controller__val = 1'd1; - ctrl_mem__recv_pkt_from_controller__msg = recv_from_controller_pkt__msg; - recv_from_controller_pkt__rdy = ctrl_mem__recv_pkt_from_controller__rdy; - end - else if ( recv_from_controller_pkt__val & ( recv_from_controller_pkt__msg.payload.cmd == 5'( __const__CMD_CONST ) ) ) begin - const_mem__recv_const__val = 1'd1; - const_mem__recv_const__msg = recv_from_controller_pkt__msg.payload.data; - recv_from_controller_pkt__rdy = const_mem__recv_const__rdy; - end - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:292 - // @update - // def notify_const_mem(): - // s.const_mem.ctrl_proceed @= s.ctrl_mem.send_ctrl.rdy & s.ctrl_mem.send_ctrl.val - - always_comb begin : notify_const_mem - const_mem__ctrl_proceed = ctrl_mem__send_ctrl__rdy & ctrl_mem__send_ctrl__val; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:311 - // @update - // def notify_crossbars_compute_status(): - // s.routing_crossbar.compute_done @= s.element_done - // s.fu_crossbar.compute_done @= s.element_done - - always_comb begin : notify_crossbars_compute_status - routing_crossbar__compute_done = element_done; - fu_crossbar__compute_done = element_done; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:272 - // @update - // def update_opt(): - // s.element.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg - // s.routing_crossbar.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg - // s.fu_crossbar.recv_opt.msg @= s.ctrl_mem.send_ctrl.msg - // - // # FIXME: Do we still need separate element and routing_xbar? - // # FIXME: Do we need to consider reg bank here? - // s.element.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.element_done - // s.routing_crossbar.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.routing_crossbar_done - // s.fu_crossbar.recv_opt.val @= s.ctrl_mem.send_ctrl.val & ~s.fu_crossbar_done - // - // # FIXME: yo96, rename ctrl.rdy to ctrl.proceed or sth similar. - // # Allows either the FU-related go out first or routing-xbar go out first. And only - // # allows the ctrl signal proceed till all the sub-modules done their own job (once). - // s.ctrl_mem.send_ctrl.rdy @= (s.element.recv_opt.rdy | s.element_done) & \ - // (s.routing_crossbar.recv_opt.rdy | s.routing_crossbar_done) & \ - // (s.fu_crossbar.recv_opt.rdy | s.fu_crossbar_done) - - always_comb begin : update_opt - element__recv_opt__msg = ctrl_mem__send_ctrl__msg; - routing_crossbar__recv_opt__msg = ctrl_mem__send_ctrl__msg; - fu_crossbar__recv_opt__msg = ctrl_mem__send_ctrl__msg; - element__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~element_done ); - routing_crossbar__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~routing_crossbar_done ); - fu_crossbar__recv_opt__val = ctrl_mem__send_ctrl__val & ( ~fu_crossbar_done ); - ctrl_mem__send_ctrl__rdy = ( ( element__recv_opt__rdy | element_done ) & ( routing_crossbar__recv_opt__rdy | routing_crossbar_done ) ) & ( fu_crossbar__recv_opt__rdy | fu_crossbar_done ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:262 - // @update - // def update_send_out_signal(): - // s.send_to_controller_pkt.val @= 0 - // s.send_to_controller_pkt.msg @= CtrlPktType(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) # , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - // if s.ctrl_mem.send_pkt_to_controller.val: - // s.send_to_controller_pkt.val @= 1 - // s.send_to_controller_pkt.msg @= s.ctrl_mem.send_pkt_to_controller.msg - // s.ctrl_mem.send_pkt_to_controller.rdy @= s.send_to_controller_pkt.rdy - - always_comb begin : update_send_out_signal - send_to_controller_pkt__val = 1'd0; - send_to_controller_pkt__msg = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, 190'd0 }; - if ( ctrl_mem__send_pkt_to_controller__val ) begin - send_to_controller_pkt__val = 1'd1; - send_to_controller_pkt__msg = ctrl_mem__send_pkt_to_controller__msg; - end - ctrl_mem__send_pkt_to_controller__rdy = send_to_controller_pkt__rdy; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/tile/TileRTL.py:297 - // @update_ff - // def already_done(): - // if s.reset | s.ctrl_mem.send_ctrl.rdy: - // s.element_done <<= 0 - // s.fu_crossbar_done <<= 0 - // s.routing_crossbar_done <<= 0 - // else: - // if s.element.recv_opt.rdy: - // s.element_done <<= 1 - // if s.fu_crossbar.recv_opt.rdy: - // s.fu_crossbar_done <<= 1 - // if s.routing_crossbar.recv_opt.rdy: - // s.routing_crossbar_done <<= 1 - - always_ff @(posedge clk) begin : already_done - if ( reset | ctrl_mem__send_ctrl__rdy ) begin - element_done <= 1'd0; - fu_crossbar_done <= 1'd0; - routing_crossbar_done <= 1'd0; - end - else begin - if ( element__recv_opt__rdy ) begin - element_done <= 1'd1; - end - if ( fu_crossbar__recv_opt__rdy ) begin - fu_crossbar_done <= 1'd1; - end - if ( routing_crossbar__recv_opt__rdy ) begin - routing_crossbar_done <= 1'd1; - end - end - end - - assign element__clk = clk; - assign element__reset = reset; - assign const_mem__clk = clk; - assign const_mem__reset = reset; - assign routing_crossbar__clk = clk; - assign routing_crossbar__reset = reset; - assign fu_crossbar__clk = clk; - assign fu_crossbar__reset = reset; - assign register_cluster__clk = clk; - assign register_cluster__reset = reset; - assign ctrl_mem__clk = clk; - assign ctrl_mem__reset = reset; - assign tile_in_channel__clk[0] = clk; - assign tile_in_channel__reset[0] = reset; - assign tile_in_channel__clk[1] = clk; - assign tile_in_channel__reset[1] = reset; - assign tile_in_channel__clk[2] = clk; - assign tile_in_channel__reset[2] = reset; - assign tile_in_channel__clk[3] = clk; - assign tile_in_channel__reset[3] = reset; - assign tile_out_or_link__clk[0] = clk; - assign tile_out_or_link__reset[0] = reset; - assign tile_out_or_link__clk[1] = clk; - assign tile_out_or_link__reset[1] = reset; - assign tile_out_or_link__clk[2] = clk; - assign tile_out_or_link__reset[2] = reset; - assign tile_out_or_link__clk[3] = clk; - assign tile_out_or_link__reset[3] = reset; - assign element__tile_id = tile_id; - assign ctrl_mem__cgra_id = cgra_id; - assign ctrl_mem__tile_id = tile_id; - assign fu_crossbar__cgra_id = cgra_id; - assign fu_crossbar__tile_id = tile_id; - assign routing_crossbar__cgra_id = cgra_id; - assign routing_crossbar__tile_id = tile_id; - assign routing_crossbar__crossbar_id = 1'd0; - assign fu_crossbar__crossbar_id = 1'd1; - assign element__recv_const__msg = const_mem__send_const__msg; - assign const_mem__send_const__rdy = element__recv_const__rdy; - assign element__recv_const__val = const_mem__send_const__val; - assign ctrl_mem__recv_from_element__msg = element__send_to_ctrl_mem__msg; - assign element__send_to_ctrl_mem__rdy = ctrl_mem__recv_from_element__rdy; - assign ctrl_mem__recv_from_element__val = element__send_to_ctrl_mem__val; - assign element__recv_from_ctrl_mem__msg = ctrl_mem__send_to_element__msg; - assign ctrl_mem__send_to_element__rdy = element__recv_from_ctrl_mem__rdy; - assign element__recv_from_ctrl_mem__val = ctrl_mem__send_to_element__val; - assign routing_crossbar__ctrl_addr_inport = ctrl_mem__ctrl_addr_outport; - assign fu_crossbar__ctrl_addr_inport = ctrl_mem__ctrl_addr_outport; - assign element__prologue_count_inport = ctrl_mem__prologue_count_outport_fu; - assign routing_crossbar__prologue_count_inport[0][0] = ctrl_mem__prologue_count_outport_routing_crossbar[0][0]; - assign routing_crossbar__prologue_count_inport[0][1] = ctrl_mem__prologue_count_outport_routing_crossbar[0][1]; - assign routing_crossbar__prologue_count_inport[0][2] = ctrl_mem__prologue_count_outport_routing_crossbar[0][2]; - assign routing_crossbar__prologue_count_inport[0][3] = ctrl_mem__prologue_count_outport_routing_crossbar[0][3]; - assign fu_crossbar__prologue_count_inport[0][0] = ctrl_mem__prologue_count_outport_fu_crossbar[0][0]; - assign fu_crossbar__prologue_count_inport[0][1] = ctrl_mem__prologue_count_outport_fu_crossbar[0][1]; - assign routing_crossbar__prologue_count_inport[1][0] = ctrl_mem__prologue_count_outport_routing_crossbar[1][0]; - assign routing_crossbar__prologue_count_inport[1][1] = ctrl_mem__prologue_count_outport_routing_crossbar[1][1]; - assign routing_crossbar__prologue_count_inport[1][2] = ctrl_mem__prologue_count_outport_routing_crossbar[1][2]; - assign routing_crossbar__prologue_count_inport[1][3] = ctrl_mem__prologue_count_outport_routing_crossbar[1][3]; - assign fu_crossbar__prologue_count_inport[1][0] = ctrl_mem__prologue_count_outport_fu_crossbar[1][0]; - assign fu_crossbar__prologue_count_inport[1][1] = ctrl_mem__prologue_count_outport_fu_crossbar[1][1]; - assign routing_crossbar__prologue_count_inport[2][0] = ctrl_mem__prologue_count_outport_routing_crossbar[2][0]; - assign routing_crossbar__prologue_count_inport[2][1] = ctrl_mem__prologue_count_outport_routing_crossbar[2][1]; - assign routing_crossbar__prologue_count_inport[2][2] = ctrl_mem__prologue_count_outport_routing_crossbar[2][2]; - assign routing_crossbar__prologue_count_inport[2][3] = ctrl_mem__prologue_count_outport_routing_crossbar[2][3]; - assign fu_crossbar__prologue_count_inport[2][0] = ctrl_mem__prologue_count_outport_fu_crossbar[2][0]; - assign fu_crossbar__prologue_count_inport[2][1] = ctrl_mem__prologue_count_outport_fu_crossbar[2][1]; - assign routing_crossbar__prologue_count_inport[3][0] = ctrl_mem__prologue_count_outport_routing_crossbar[3][0]; - assign routing_crossbar__prologue_count_inport[3][1] = ctrl_mem__prologue_count_outport_routing_crossbar[3][1]; - assign routing_crossbar__prologue_count_inport[3][2] = ctrl_mem__prologue_count_outport_routing_crossbar[3][2]; - assign routing_crossbar__prologue_count_inport[3][3] = ctrl_mem__prologue_count_outport_routing_crossbar[3][3]; - assign fu_crossbar__prologue_count_inport[3][0] = ctrl_mem__prologue_count_outport_fu_crossbar[3][0]; - assign fu_crossbar__prologue_count_inport[3][1] = ctrl_mem__prologue_count_outport_fu_crossbar[3][1]; - assign routing_crossbar__prologue_count_inport[4][0] = ctrl_mem__prologue_count_outport_routing_crossbar[4][0]; - assign routing_crossbar__prologue_count_inport[4][1] = ctrl_mem__prologue_count_outport_routing_crossbar[4][1]; - assign routing_crossbar__prologue_count_inport[4][2] = ctrl_mem__prologue_count_outport_routing_crossbar[4][2]; - assign routing_crossbar__prologue_count_inport[4][3] = ctrl_mem__prologue_count_outport_routing_crossbar[4][3]; - assign fu_crossbar__prologue_count_inport[4][0] = ctrl_mem__prologue_count_outport_fu_crossbar[4][0]; - assign fu_crossbar__prologue_count_inport[4][1] = ctrl_mem__prologue_count_outport_fu_crossbar[4][1]; - assign routing_crossbar__prologue_count_inport[5][0] = ctrl_mem__prologue_count_outport_routing_crossbar[5][0]; - assign routing_crossbar__prologue_count_inport[5][1] = ctrl_mem__prologue_count_outport_routing_crossbar[5][1]; - assign routing_crossbar__prologue_count_inport[5][2] = ctrl_mem__prologue_count_outport_routing_crossbar[5][2]; - assign routing_crossbar__prologue_count_inport[5][3] = ctrl_mem__prologue_count_outport_routing_crossbar[5][3]; - assign fu_crossbar__prologue_count_inport[5][0] = ctrl_mem__prologue_count_outport_fu_crossbar[5][0]; - assign fu_crossbar__prologue_count_inport[5][1] = ctrl_mem__prologue_count_outport_fu_crossbar[5][1]; - assign routing_crossbar__prologue_count_inport[6][0] = ctrl_mem__prologue_count_outport_routing_crossbar[6][0]; - assign routing_crossbar__prologue_count_inport[6][1] = ctrl_mem__prologue_count_outport_routing_crossbar[6][1]; - assign routing_crossbar__prologue_count_inport[6][2] = ctrl_mem__prologue_count_outport_routing_crossbar[6][2]; - assign routing_crossbar__prologue_count_inport[6][3] = ctrl_mem__prologue_count_outport_routing_crossbar[6][3]; - assign fu_crossbar__prologue_count_inport[6][0] = ctrl_mem__prologue_count_outport_fu_crossbar[6][0]; - assign fu_crossbar__prologue_count_inport[6][1] = ctrl_mem__prologue_count_outport_fu_crossbar[6][1]; - assign routing_crossbar__prologue_count_inport[7][0] = ctrl_mem__prologue_count_outport_routing_crossbar[7][0]; - assign routing_crossbar__prologue_count_inport[7][1] = ctrl_mem__prologue_count_outport_routing_crossbar[7][1]; - assign routing_crossbar__prologue_count_inport[7][2] = ctrl_mem__prologue_count_outport_routing_crossbar[7][2]; - assign routing_crossbar__prologue_count_inport[7][3] = ctrl_mem__prologue_count_outport_routing_crossbar[7][3]; - assign fu_crossbar__prologue_count_inport[7][0] = ctrl_mem__prologue_count_outport_fu_crossbar[7][0]; - assign fu_crossbar__prologue_count_inport[7][1] = ctrl_mem__prologue_count_outport_fu_crossbar[7][1]; - assign routing_crossbar__prologue_count_inport[8][0] = ctrl_mem__prologue_count_outport_routing_crossbar[8][0]; - assign routing_crossbar__prologue_count_inport[8][1] = ctrl_mem__prologue_count_outport_routing_crossbar[8][1]; - assign routing_crossbar__prologue_count_inport[8][2] = ctrl_mem__prologue_count_outport_routing_crossbar[8][2]; - assign routing_crossbar__prologue_count_inport[8][3] = ctrl_mem__prologue_count_outport_routing_crossbar[8][3]; - assign fu_crossbar__prologue_count_inport[8][0] = ctrl_mem__prologue_count_outport_fu_crossbar[8][0]; - assign fu_crossbar__prologue_count_inport[8][1] = ctrl_mem__prologue_count_outport_fu_crossbar[8][1]; - assign routing_crossbar__prologue_count_inport[9][0] = ctrl_mem__prologue_count_outport_routing_crossbar[9][0]; - assign routing_crossbar__prologue_count_inport[9][1] = ctrl_mem__prologue_count_outport_routing_crossbar[9][1]; - assign routing_crossbar__prologue_count_inport[9][2] = ctrl_mem__prologue_count_outport_routing_crossbar[9][2]; - assign routing_crossbar__prologue_count_inport[9][3] = ctrl_mem__prologue_count_outport_routing_crossbar[9][3]; - assign fu_crossbar__prologue_count_inport[9][0] = ctrl_mem__prologue_count_outport_fu_crossbar[9][0]; - assign fu_crossbar__prologue_count_inport[9][1] = ctrl_mem__prologue_count_outport_fu_crossbar[9][1]; - assign routing_crossbar__prologue_count_inport[10][0] = ctrl_mem__prologue_count_outport_routing_crossbar[10][0]; - assign routing_crossbar__prologue_count_inport[10][1] = ctrl_mem__prologue_count_outport_routing_crossbar[10][1]; - assign routing_crossbar__prologue_count_inport[10][2] = ctrl_mem__prologue_count_outport_routing_crossbar[10][2]; - assign routing_crossbar__prologue_count_inport[10][3] = ctrl_mem__prologue_count_outport_routing_crossbar[10][3]; - assign fu_crossbar__prologue_count_inport[10][0] = ctrl_mem__prologue_count_outport_fu_crossbar[10][0]; - assign fu_crossbar__prologue_count_inport[10][1] = ctrl_mem__prologue_count_outport_fu_crossbar[10][1]; - assign routing_crossbar__prologue_count_inport[11][0] = ctrl_mem__prologue_count_outport_routing_crossbar[11][0]; - assign routing_crossbar__prologue_count_inport[11][1] = ctrl_mem__prologue_count_outport_routing_crossbar[11][1]; - assign routing_crossbar__prologue_count_inport[11][2] = ctrl_mem__prologue_count_outport_routing_crossbar[11][2]; - assign routing_crossbar__prologue_count_inport[11][3] = ctrl_mem__prologue_count_outport_routing_crossbar[11][3]; - assign fu_crossbar__prologue_count_inport[11][0] = ctrl_mem__prologue_count_outport_fu_crossbar[11][0]; - assign fu_crossbar__prologue_count_inport[11][1] = ctrl_mem__prologue_count_outport_fu_crossbar[11][1]; - assign routing_crossbar__prologue_count_inport[12][0] = ctrl_mem__prologue_count_outport_routing_crossbar[12][0]; - assign routing_crossbar__prologue_count_inport[12][1] = ctrl_mem__prologue_count_outport_routing_crossbar[12][1]; - assign routing_crossbar__prologue_count_inport[12][2] = ctrl_mem__prologue_count_outport_routing_crossbar[12][2]; - assign routing_crossbar__prologue_count_inport[12][3] = ctrl_mem__prologue_count_outport_routing_crossbar[12][3]; - assign fu_crossbar__prologue_count_inport[12][0] = ctrl_mem__prologue_count_outport_fu_crossbar[12][0]; - assign fu_crossbar__prologue_count_inport[12][1] = ctrl_mem__prologue_count_outport_fu_crossbar[12][1]; - assign routing_crossbar__prologue_count_inport[13][0] = ctrl_mem__prologue_count_outport_routing_crossbar[13][0]; - assign routing_crossbar__prologue_count_inport[13][1] = ctrl_mem__prologue_count_outport_routing_crossbar[13][1]; - assign routing_crossbar__prologue_count_inport[13][2] = ctrl_mem__prologue_count_outport_routing_crossbar[13][2]; - assign routing_crossbar__prologue_count_inport[13][3] = ctrl_mem__prologue_count_outport_routing_crossbar[13][3]; - assign fu_crossbar__prologue_count_inport[13][0] = ctrl_mem__prologue_count_outport_fu_crossbar[13][0]; - assign fu_crossbar__prologue_count_inport[13][1] = ctrl_mem__prologue_count_outport_fu_crossbar[13][1]; - assign routing_crossbar__prologue_count_inport[14][0] = ctrl_mem__prologue_count_outport_routing_crossbar[14][0]; - assign routing_crossbar__prologue_count_inport[14][1] = ctrl_mem__prologue_count_outport_routing_crossbar[14][1]; - assign routing_crossbar__prologue_count_inport[14][2] = ctrl_mem__prologue_count_outport_routing_crossbar[14][2]; - assign routing_crossbar__prologue_count_inport[14][3] = ctrl_mem__prologue_count_outport_routing_crossbar[14][3]; - assign fu_crossbar__prologue_count_inport[14][0] = ctrl_mem__prologue_count_outport_fu_crossbar[14][0]; - assign fu_crossbar__prologue_count_inport[14][1] = ctrl_mem__prologue_count_outport_fu_crossbar[14][1]; - assign routing_crossbar__prologue_count_inport[15][0] = ctrl_mem__prologue_count_outport_routing_crossbar[15][0]; - assign routing_crossbar__prologue_count_inport[15][1] = ctrl_mem__prologue_count_outport_routing_crossbar[15][1]; - assign routing_crossbar__prologue_count_inport[15][2] = ctrl_mem__prologue_count_outport_routing_crossbar[15][2]; - assign routing_crossbar__prologue_count_inport[15][3] = ctrl_mem__prologue_count_outport_routing_crossbar[15][3]; - assign fu_crossbar__prologue_count_inport[15][0] = ctrl_mem__prologue_count_outport_fu_crossbar[15][0]; - assign fu_crossbar__prologue_count_inport[15][1] = ctrl_mem__prologue_count_outport_fu_crossbar[15][1]; - assign element__to_mem_raddr__rdy[0] = 1'd0; - assign element__from_mem_rdata__val[0] = 1'd0; - assign element__from_mem_rdata__msg[0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[0] = 1'd0; - assign element__to_mem_wdata__rdy[0] = 1'd0; - assign element__to_mem_raddr__rdy[1] = 1'd0; - assign element__from_mem_rdata__val[1] = 1'd0; - assign element__from_mem_rdata__msg[1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[1] = 1'd0; - assign element__to_mem_wdata__rdy[1] = 1'd0; - assign element__to_mem_raddr__rdy[2] = 1'd0; - assign element__from_mem_rdata__val[2] = 1'd0; - assign element__from_mem_rdata__msg[2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[2] = 1'd0; - assign element__to_mem_wdata__rdy[2] = 1'd0; - assign element__to_mem_raddr__rdy[3] = 1'd0; - assign element__from_mem_rdata__val[3] = 1'd0; - assign element__from_mem_rdata__msg[3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[3] = 1'd0; - assign element__to_mem_wdata__rdy[3] = 1'd0; - assign element__to_mem_raddr__rdy[4] = 1'd0; - assign element__from_mem_rdata__val[4] = 1'd0; - assign element__from_mem_rdata__msg[4] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[4] = 1'd0; - assign element__to_mem_wdata__rdy[4] = 1'd0; - assign element__to_mem_raddr__rdy[5] = 1'd0; - assign element__from_mem_rdata__val[5] = 1'd0; - assign element__from_mem_rdata__msg[5] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[5] = 1'd0; - assign element__to_mem_wdata__rdy[5] = 1'd0; - assign element__to_mem_raddr__rdy[6] = 1'd0; - assign element__from_mem_rdata__val[6] = 1'd0; - assign element__from_mem_rdata__msg[6] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[6] = 1'd0; - assign element__to_mem_wdata__rdy[6] = 1'd0; - assign to_mem_raddr__msg = element__to_mem_raddr__msg[7]; - assign element__to_mem_raddr__rdy[7] = to_mem_raddr__rdy; - assign to_mem_raddr__val = element__to_mem_raddr__val[7]; - assign element__from_mem_rdata__msg[7] = from_mem_rdata__msg; - assign from_mem_rdata__rdy = element__from_mem_rdata__rdy[7]; - assign element__from_mem_rdata__val[7] = from_mem_rdata__val; - assign to_mem_waddr__msg = element__to_mem_waddr__msg[7]; - assign element__to_mem_waddr__rdy[7] = to_mem_waddr__rdy; - assign to_mem_waddr__val = element__to_mem_waddr__val[7]; - assign to_mem_wdata__msg = element__to_mem_wdata__msg[7]; - assign element__to_mem_wdata__rdy[7] = to_mem_wdata__rdy; - assign to_mem_wdata__val = element__to_mem_wdata__val[7]; - assign element__to_mem_raddr__rdy[8] = 1'd0; - assign element__from_mem_rdata__val[8] = 1'd0; - assign element__from_mem_rdata__msg[8] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[8] = 1'd0; - assign element__to_mem_wdata__rdy[8] = 1'd0; - assign element__to_mem_raddr__rdy[9] = 1'd0; - assign element__from_mem_rdata__val[9] = 1'd0; - assign element__from_mem_rdata__msg[9] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[9] = 1'd0; - assign element__to_mem_wdata__rdy[9] = 1'd0; - assign element__to_mem_raddr__rdy[10] = 1'd0; - assign element__from_mem_rdata__val[10] = 1'd0; - assign element__from_mem_rdata__msg[10] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[10] = 1'd0; - assign element__to_mem_wdata__rdy[10] = 1'd0; - assign element__to_mem_raddr__rdy[11] = 1'd0; - assign element__from_mem_rdata__val[11] = 1'd0; - assign element__from_mem_rdata__msg[11] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[11] = 1'd0; - assign element__to_mem_wdata__rdy[11] = 1'd0; - assign element__to_mem_raddr__rdy[12] = 1'd0; - assign element__from_mem_rdata__val[12] = 1'd0; - assign element__from_mem_rdata__msg[12] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[12] = 1'd0; - assign element__to_mem_wdata__rdy[12] = 1'd0; - assign element__to_mem_raddr__rdy[13] = 1'd0; - assign element__from_mem_rdata__val[13] = 1'd0; - assign element__from_mem_rdata__msg[13] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[13] = 1'd0; - assign element__to_mem_wdata__rdy[13] = 1'd0; - assign element__to_mem_raddr__rdy[14] = 1'd0; - assign element__from_mem_rdata__val[14] = 1'd0; - assign element__from_mem_rdata__msg[14] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign element__to_mem_waddr__rdy[14] = 1'd0; - assign element__to_mem_wdata__rdy[14] = 1'd0; - assign tile_in_channel__recv__msg[0] = recv_data__msg[0]; - assign recv_data__rdy[0] = tile_in_channel__recv__rdy[0]; - assign tile_in_channel__recv__val[0] = recv_data__val[0]; - assign routing_crossbar__recv_data__msg[0] = tile_in_channel__send__msg[0]; - assign tile_in_channel__send__rdy[0] = routing_crossbar__recv_data__rdy[0]; - assign routing_crossbar__recv_data__val[0] = tile_in_channel__send__val[0]; - assign tile_in_channel__recv__msg[1] = recv_data__msg[1]; - assign recv_data__rdy[1] = tile_in_channel__recv__rdy[1]; - assign tile_in_channel__recv__val[1] = recv_data__val[1]; - assign routing_crossbar__recv_data__msg[1] = tile_in_channel__send__msg[1]; - assign tile_in_channel__send__rdy[1] = routing_crossbar__recv_data__rdy[1]; - assign routing_crossbar__recv_data__val[1] = tile_in_channel__send__val[1]; - assign tile_in_channel__recv__msg[2] = recv_data__msg[2]; - assign recv_data__rdy[2] = tile_in_channel__recv__rdy[2]; - assign tile_in_channel__recv__val[2] = recv_data__val[2]; - assign routing_crossbar__recv_data__msg[2] = tile_in_channel__send__msg[2]; - assign tile_in_channel__send__rdy[2] = routing_crossbar__recv_data__rdy[2]; - assign routing_crossbar__recv_data__val[2] = tile_in_channel__send__val[2]; - assign tile_in_channel__recv__msg[3] = recv_data__msg[3]; - assign recv_data__rdy[3] = tile_in_channel__recv__rdy[3]; - assign tile_in_channel__recv__val[3] = recv_data__val[3]; - assign routing_crossbar__recv_data__msg[3] = tile_in_channel__send__msg[3]; - assign tile_in_channel__send__rdy[3] = routing_crossbar__recv_data__rdy[3]; - assign routing_crossbar__recv_data__val[3] = tile_in_channel__send__val[3]; - assign routing_crossbar__crossbar_outport[0] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[0]; - assign fu_crossbar__crossbar_outport[0] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[0]; - assign routing_crossbar__crossbar_outport[1] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[1]; - assign fu_crossbar__crossbar_outport[1] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[1]; - assign routing_crossbar__crossbar_outport[2] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[2]; - assign fu_crossbar__crossbar_outport[2] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[2]; - assign routing_crossbar__crossbar_outport[3] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[3]; - assign fu_crossbar__crossbar_outport[3] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[3]; - assign routing_crossbar__crossbar_outport[4] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[4]; - assign fu_crossbar__crossbar_outport[4] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[4]; - assign routing_crossbar__crossbar_outport[5] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[5]; - assign fu_crossbar__crossbar_outport[5] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[5]; - assign routing_crossbar__crossbar_outport[6] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[6]; - assign fu_crossbar__crossbar_outport[6] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[6]; - assign routing_crossbar__crossbar_outport[7] = ctrl_mem__send_ctrl__msg.routing_xbar_outport[7]; - assign fu_crossbar__crossbar_outport[7] = ctrl_mem__send_ctrl__msg.fu_xbar_outport[7]; - assign fu_crossbar__recv_data__msg[0] = element__send_out__msg[0]; - assign element__send_out__rdy[0] = fu_crossbar__recv_data__rdy[0]; - assign fu_crossbar__recv_data__val[0] = element__send_out__val[0]; - assign fu_crossbar__recv_data__msg[1] = element__send_out__msg[1]; - assign element__send_out__rdy[1] = fu_crossbar__recv_data__rdy[1]; - assign fu_crossbar__recv_data__val[1] = element__send_out__val[1]; - assign tile_out_or_link__recv_fu__msg[0] = fu_crossbar__send_data__msg[0]; - assign fu_crossbar__send_data__rdy[0] = tile_out_or_link__recv_fu__rdy[0]; - assign tile_out_or_link__recv_fu__val[0] = fu_crossbar__send_data__val[0]; - assign tile_out_or_link__recv_xbar__msg[0] = routing_crossbar__send_data__msg[0]; - assign routing_crossbar__send_data__rdy[0] = tile_out_or_link__recv_xbar__rdy[0]; - assign tile_out_or_link__recv_xbar__val[0] = routing_crossbar__send_data__val[0]; - assign send_data__msg[0] = tile_out_or_link__send__msg[0]; - assign tile_out_or_link__send__rdy[0] = send_data__rdy[0]; - assign send_data__val[0] = tile_out_or_link__send__val[0]; - assign tile_out_or_link__recv_fu__msg[1] = fu_crossbar__send_data__msg[1]; - assign fu_crossbar__send_data__rdy[1] = tile_out_or_link__recv_fu__rdy[1]; - assign tile_out_or_link__recv_fu__val[1] = fu_crossbar__send_data__val[1]; - assign tile_out_or_link__recv_xbar__msg[1] = routing_crossbar__send_data__msg[1]; - assign routing_crossbar__send_data__rdy[1] = tile_out_or_link__recv_xbar__rdy[1]; - assign tile_out_or_link__recv_xbar__val[1] = routing_crossbar__send_data__val[1]; - assign send_data__msg[1] = tile_out_or_link__send__msg[1]; - assign tile_out_or_link__send__rdy[1] = send_data__rdy[1]; - assign send_data__val[1] = tile_out_or_link__send__val[1]; - assign tile_out_or_link__recv_fu__msg[2] = fu_crossbar__send_data__msg[2]; - assign fu_crossbar__send_data__rdy[2] = tile_out_or_link__recv_fu__rdy[2]; - assign tile_out_or_link__recv_fu__val[2] = fu_crossbar__send_data__val[2]; - assign tile_out_or_link__recv_xbar__msg[2] = routing_crossbar__send_data__msg[2]; - assign routing_crossbar__send_data__rdy[2] = tile_out_or_link__recv_xbar__rdy[2]; - assign tile_out_or_link__recv_xbar__val[2] = routing_crossbar__send_data__val[2]; - assign send_data__msg[2] = tile_out_or_link__send__msg[2]; - assign tile_out_or_link__send__rdy[2] = send_data__rdy[2]; - assign send_data__val[2] = tile_out_or_link__send__val[2]; - assign tile_out_or_link__recv_fu__msg[3] = fu_crossbar__send_data__msg[3]; - assign fu_crossbar__send_data__rdy[3] = tile_out_or_link__recv_fu__rdy[3]; - assign tile_out_or_link__recv_fu__val[3] = fu_crossbar__send_data__val[3]; - assign tile_out_or_link__recv_xbar__msg[3] = routing_crossbar__send_data__msg[3]; - assign routing_crossbar__send_data__rdy[3] = tile_out_or_link__recv_xbar__rdy[3]; - assign tile_out_or_link__recv_xbar__val[3] = routing_crossbar__send_data__val[3]; - assign send_data__msg[3] = tile_out_or_link__send__msg[3]; - assign tile_out_or_link__send__rdy[3] = send_data__rdy[3]; - assign send_data__val[3] = tile_out_or_link__send__val[3]; - assign register_cluster__recv_data_from_routing_crossbar__msg[0] = routing_crossbar__send_data__msg[4]; - assign routing_crossbar__send_data__rdy[4] = register_cluster__recv_data_from_routing_crossbar__rdy[0]; - assign register_cluster__recv_data_from_routing_crossbar__val[0] = routing_crossbar__send_data__val[4]; - assign register_cluster__recv_data_from_fu_crossbar__msg[0] = fu_crossbar__send_data__msg[4]; - assign fu_crossbar__send_data__rdy[4] = register_cluster__recv_data_from_fu_crossbar__rdy[0]; - assign register_cluster__recv_data_from_fu_crossbar__val[0] = fu_crossbar__send_data__val[4]; - assign register_cluster__recv_data_from_const__msg[0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign register_cluster__recv_data_from_const__val[0] = 1'd0; - assign element__recv_in__msg[0] = register_cluster__send_data_to_fu__msg[0]; - assign register_cluster__send_data_to_fu__rdy[0] = element__recv_in__rdy[0]; - assign element__recv_in__val[0] = register_cluster__send_data_to_fu__val[0]; - assign register_cluster__inport_opt = ctrl_mem__send_ctrl__msg; - assign register_cluster__recv_data_from_routing_crossbar__msg[1] = routing_crossbar__send_data__msg[5]; - assign routing_crossbar__send_data__rdy[5] = register_cluster__recv_data_from_routing_crossbar__rdy[1]; - assign register_cluster__recv_data_from_routing_crossbar__val[1] = routing_crossbar__send_data__val[5]; - assign register_cluster__recv_data_from_fu_crossbar__msg[1] = fu_crossbar__send_data__msg[5]; - assign fu_crossbar__send_data__rdy[5] = register_cluster__recv_data_from_fu_crossbar__rdy[1]; - assign register_cluster__recv_data_from_fu_crossbar__val[1] = fu_crossbar__send_data__val[5]; - assign register_cluster__recv_data_from_const__msg[1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign register_cluster__recv_data_from_const__val[1] = 1'd0; - assign element__recv_in__msg[1] = register_cluster__send_data_to_fu__msg[1]; - assign register_cluster__send_data_to_fu__rdy[1] = element__recv_in__rdy[1]; - assign element__recv_in__val[1] = register_cluster__send_data_to_fu__val[1]; - assign register_cluster__recv_data_from_routing_crossbar__msg[2] = routing_crossbar__send_data__msg[6]; - assign routing_crossbar__send_data__rdy[6] = register_cluster__recv_data_from_routing_crossbar__rdy[2]; - assign register_cluster__recv_data_from_routing_crossbar__val[2] = routing_crossbar__send_data__val[6]; - assign register_cluster__recv_data_from_fu_crossbar__msg[2] = fu_crossbar__send_data__msg[6]; - assign fu_crossbar__send_data__rdy[6] = register_cluster__recv_data_from_fu_crossbar__rdy[2]; - assign register_cluster__recv_data_from_fu_crossbar__val[2] = fu_crossbar__send_data__val[6]; - assign register_cluster__recv_data_from_const__msg[2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign register_cluster__recv_data_from_const__val[2] = 1'd0; - assign element__recv_in__msg[2] = register_cluster__send_data_to_fu__msg[2]; - assign register_cluster__send_data_to_fu__rdy[2] = element__recv_in__rdy[2]; - assign element__recv_in__val[2] = register_cluster__send_data_to_fu__val[2]; - assign register_cluster__recv_data_from_routing_crossbar__msg[3] = routing_crossbar__send_data__msg[7]; - assign routing_crossbar__send_data__rdy[7] = register_cluster__recv_data_from_routing_crossbar__rdy[3]; - assign register_cluster__recv_data_from_routing_crossbar__val[3] = routing_crossbar__send_data__val[7]; - assign register_cluster__recv_data_from_fu_crossbar__msg[3] = fu_crossbar__send_data__msg[7]; - assign fu_crossbar__send_data__rdy[7] = register_cluster__recv_data_from_fu_crossbar__rdy[3]; - assign register_cluster__recv_data_from_fu_crossbar__val[3] = fu_crossbar__send_data__val[7]; - assign register_cluster__recv_data_from_const__msg[3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign register_cluster__recv_data_from_const__val[3] = 1'd0; - assign element__recv_in__msg[3] = register_cluster__send_data_to_fu__msg[3]; - assign register_cluster__send_data_to_fu__rdy[3] = element__recv_in__rdy[3]; - assign element__recv_in__val[3] = register_cluster__send_data_to_fu__val[3]; - assign element__clear[0] = 1'd0; - assign element__clear[1] = 1'd0; - assign element__clear[2] = 1'd0; - assign element__clear[3] = 1'd0; - assign element__clear[4] = 1'd0; - assign element__clear[5] = 1'd0; - assign element__clear[6] = 1'd0; - assign element__clear[7] = 1'd0; - assign element__clear[8] = 1'd0; - assign element__clear[9] = 1'd0; - assign element__clear[10] = 1'd0; - assign element__clear[11] = 1'd0; - assign element__clear[12] = 1'd0; - assign element__clear[13] = 1'd0; - assign element__clear[14] = 1'd0; - assign fu_crossbar__clear = 1'd0; - assign routing_crossbar__clear = 1'd0; - -endmodule - - -// PyMTL Component CgraRTL Definition -// Full name: CgraRTL__CgraPayloadType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__multi_cgra_rows_2__multi_cgra_columns_2__width_4__height_4__ctrl_mem_size_16__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_registers_per_reg_bank_16__num_ctrl_4__total_steps_38__mem_access_is_combinational_True__FunctionUnit_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ]__cgra_topology_Mesh__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__idTo2d_map_{0: (0, 0), 1: (1, 0), 2: (0, 1), 3: (1, 1)}__is_multi_cgra_True__has_ctrl_ring_True -// At /home/ajokai/cgra/VectorCGRAfork0/cgra/CgraRTL.py - -module CgraRTL__72d915b46abe89cb -( - input logic [6:0] address_lower , - input logic [6:0] address_upper , - input logic [1:0] cgra_id , - input logic [0:0] clk , - input logic [0:0] reset , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_east__msg [0:3] , - output logic [0:0] recv_data_on_boundary_east__rdy [0:3] , - input logic [0:0] recv_data_on_boundary_east__val [0:3] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_north__msg [0:3] , - output logic [0:0] recv_data_on_boundary_north__rdy [0:3] , - input logic [0:0] recv_data_on_boundary_north__val [0:3] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_south__msg [0:3] , - output logic [0:0] recv_data_on_boundary_south__rdy [0:3] , - input logic [0:0] recv_data_on_boundary_south__val [0:3] , - input CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 recv_data_on_boundary_west__msg [0:3] , - output logic [0:0] recv_data_on_boundary_west__rdy [0:3] , - input logic [0:0] recv_data_on_boundary_west__val [0:3] , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , - output logic [0:0] recv_from_cpu_pkt__rdy , - input logic [0:0] recv_from_cpu_pkt__val , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv_from_inter_cgra_noc__msg , - output logic [0:0] recv_from_inter_cgra_noc__rdy , - input logic [0:0] recv_from_inter_cgra_noc__val , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_east__msg [0:3] , - input logic [0:0] send_data_on_boundary_east__rdy [0:3] , - output logic [0:0] send_data_on_boundary_east__val [0:3] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_north__msg [0:3] , - input logic [0:0] send_data_on_boundary_north__rdy [0:3] , - output logic [0:0] send_data_on_boundary_north__val [0:3] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_south__msg [0:3] , - input logic [0:0] send_data_on_boundary_south__rdy [0:3] , - output logic [0:0] send_data_on_boundary_south__val [0:3] , - output CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 send_data_on_boundary_west__msg [0:3] , - input logic [0:0] send_data_on_boundary_west__rdy [0:3] , - output logic [0:0] send_data_on_boundary_west__val [0:3] , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , - input logic [0:0] send_to_cpu_pkt__rdy , - output logic [0:0] send_to_cpu_pkt__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send_to_inter_cgra_noc__msg , - input logic [0:0] send_to_inter_cgra_noc__rdy , - output logic [0:0] send_to_inter_cgra_noc__val -); - //------------------------------------------------------------- - // Component controller - //------------------------------------------------------------- - - logic [1:0] controller__cgra_id; - logic [0:0] controller__clk; - logic [0:0] controller__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__recv_from_cpu_pkt__msg; - logic [0:0] controller__recv_from_cpu_pkt__rdy; - logic [0:0] controller__recv_from_cpu_pkt__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__recv_from_ctrl_ring_pkt__msg; - logic [0:0] controller__recv_from_ctrl_ring_pkt__rdy; - logic [0:0] controller__recv_from_ctrl_ring_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_inter_cgra_noc__msg; - logic [0:0] controller__recv_from_inter_cgra_noc__rdy; - logic [0:0] controller__recv_from_inter_cgra_noc__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_load_request_pkt__msg; - logic [0:0] controller__recv_from_tile_load_request_pkt__rdy; - logic [0:0] controller__recv_from_tile_load_request_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_load_response_pkt__msg; - logic [0:0] controller__recv_from_tile_load_response_pkt__rdy; - logic [0:0] controller__recv_from_tile_load_response_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__recv_from_tile_store_request_pkt__msg; - logic [0:0] controller__recv_from_tile_store_request_pkt__rdy; - logic [0:0] controller__recv_from_tile_store_request_pkt__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__send_to_cpu_pkt__msg; - logic [0:0] controller__send_to_cpu_pkt__rdy; - logic [0:0] controller__send_to_cpu_pkt__val; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 controller__send_to_ctrl_ring_pkt__msg; - logic [0:0] controller__send_to_ctrl_ring_pkt__rdy; - logic [0:0] controller__send_to_ctrl_ring_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_inter_cgra_noc__msg; - logic [0:0] controller__send_to_inter_cgra_noc__rdy; - logic [0:0] controller__send_to_inter_cgra_noc__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_mem_load_request__msg; - logic [0:0] controller__send_to_mem_load_request__rdy; - logic [0:0] controller__send_to_mem_load_request__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_mem_store_request__msg; - logic [0:0] controller__send_to_mem_store_request__rdy; - logic [0:0] controller__send_to_mem_store_request__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d controller__send_to_tile_load_response__msg; - logic [0:0] controller__send_to_tile_load_response__rdy; - logic [0:0] controller__send_to_tile_load_response__val; - - ControllerRTL__e06602ce343fdc8d controller - ( - .cgra_id( controller__cgra_id ), - .clk( controller__clk ), - .reset( controller__reset ), - .recv_from_cpu_pkt__msg( controller__recv_from_cpu_pkt__msg ), - .recv_from_cpu_pkt__rdy( controller__recv_from_cpu_pkt__rdy ), - .recv_from_cpu_pkt__val( controller__recv_from_cpu_pkt__val ), - .recv_from_ctrl_ring_pkt__msg( controller__recv_from_ctrl_ring_pkt__msg ), - .recv_from_ctrl_ring_pkt__rdy( controller__recv_from_ctrl_ring_pkt__rdy ), - .recv_from_ctrl_ring_pkt__val( controller__recv_from_ctrl_ring_pkt__val ), - .recv_from_inter_cgra_noc__msg( controller__recv_from_inter_cgra_noc__msg ), - .recv_from_inter_cgra_noc__rdy( controller__recv_from_inter_cgra_noc__rdy ), - .recv_from_inter_cgra_noc__val( controller__recv_from_inter_cgra_noc__val ), - .recv_from_tile_load_request_pkt__msg( controller__recv_from_tile_load_request_pkt__msg ), - .recv_from_tile_load_request_pkt__rdy( controller__recv_from_tile_load_request_pkt__rdy ), - .recv_from_tile_load_request_pkt__val( controller__recv_from_tile_load_request_pkt__val ), - .recv_from_tile_load_response_pkt__msg( controller__recv_from_tile_load_response_pkt__msg ), - .recv_from_tile_load_response_pkt__rdy( controller__recv_from_tile_load_response_pkt__rdy ), - .recv_from_tile_load_response_pkt__val( controller__recv_from_tile_load_response_pkt__val ), - .recv_from_tile_store_request_pkt__msg( controller__recv_from_tile_store_request_pkt__msg ), - .recv_from_tile_store_request_pkt__rdy( controller__recv_from_tile_store_request_pkt__rdy ), - .recv_from_tile_store_request_pkt__val( controller__recv_from_tile_store_request_pkt__val ), - .send_to_cpu_pkt__msg( controller__send_to_cpu_pkt__msg ), - .send_to_cpu_pkt__rdy( controller__send_to_cpu_pkt__rdy ), - .send_to_cpu_pkt__val( controller__send_to_cpu_pkt__val ), - .send_to_ctrl_ring_pkt__msg( controller__send_to_ctrl_ring_pkt__msg ), - .send_to_ctrl_ring_pkt__rdy( controller__send_to_ctrl_ring_pkt__rdy ), - .send_to_ctrl_ring_pkt__val( controller__send_to_ctrl_ring_pkt__val ), - .send_to_inter_cgra_noc__msg( controller__send_to_inter_cgra_noc__msg ), - .send_to_inter_cgra_noc__rdy( controller__send_to_inter_cgra_noc__rdy ), - .send_to_inter_cgra_noc__val( controller__send_to_inter_cgra_noc__val ), - .send_to_mem_load_request__msg( controller__send_to_mem_load_request__msg ), - .send_to_mem_load_request__rdy( controller__send_to_mem_load_request__rdy ), - .send_to_mem_load_request__val( controller__send_to_mem_load_request__val ), - .send_to_mem_store_request__msg( controller__send_to_mem_store_request__msg ), - .send_to_mem_store_request__rdy( controller__send_to_mem_store_request__rdy ), - .send_to_mem_store_request__val( controller__send_to_mem_store_request__val ), - .send_to_tile_load_response__msg( controller__send_to_tile_load_response__msg ), - .send_to_tile_load_response__rdy( controller__send_to_tile_load_response__rdy ), - .send_to_tile_load_response__val( controller__send_to_tile_load_response__val ) - ); - - //------------------------------------------------------------- - // End of component controller - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component ctrl_ring - //------------------------------------------------------------- - - logic [0:0] ctrl_ring__clk; - logic [0:0] ctrl_ring__reset; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_ring__recv__msg [0:16]; - logic [0:0] ctrl_ring__recv__rdy [0:16]; - logic [0:0] ctrl_ring__recv__val [0:16]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 ctrl_ring__send__msg [0:16]; - logic [0:0] ctrl_ring__send__rdy [0:16]; - logic [0:0] ctrl_ring__send__val [0:16]; - - RingNetworkRTL__8866f4e00dbc912a ctrl_ring - ( - .clk( ctrl_ring__clk ), - .reset( ctrl_ring__reset ), - .recv__msg( ctrl_ring__recv__msg ), - .recv__rdy( ctrl_ring__recv__rdy ), - .recv__val( ctrl_ring__recv__val ), - .send__msg( ctrl_ring__send__msg ), - .send__rdy( ctrl_ring__send__rdy ), - .send__val( ctrl_ring__send__val ) - ); - - //------------------------------------------------------------- - // End of component ctrl_ring - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component data_mem - //------------------------------------------------------------- - - logic [6:0] data_mem__address_lower; - logic [6:0] data_mem__address_upper; - logic [1:0] data_mem__cgra_id; - logic [0:0] data_mem__clk; - logic [0:0] data_mem__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_load_request__msg; - logic [0:0] data_mem__recv_from_noc_load_request__rdy; - logic [0:0] data_mem__recv_from_noc_load_request__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_load_response_pkt__msg; - logic [0:0] data_mem__recv_from_noc_load_response_pkt__rdy; - logic [0:0] data_mem__recv_from_noc_load_response_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__recv_from_noc_store_request__msg; - logic [0:0] data_mem__recv_from_noc_store_request__rdy; - logic [0:0] data_mem__recv_from_noc_store_request__val; - logic [6:0] data_mem__recv_raddr__msg [0:6]; - logic [0:0] data_mem__recv_raddr__rdy [0:6]; - logic [0:0] data_mem__recv_raddr__val [0:6]; - logic [6:0] data_mem__recv_waddr__msg [0:6]; - logic [0:0] data_mem__recv_waddr__rdy [0:6]; - logic [0:0] data_mem__recv_waddr__val [0:6]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data_mem__recv_wdata__msg [0:6]; - logic [0:0] data_mem__recv_wdata__rdy [0:6]; - logic [0:0] data_mem__recv_wdata__val [0:6]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 data_mem__send_rdata__msg [0:6]; - logic [0:0] data_mem__send_rdata__rdy [0:6]; - logic [0:0] data_mem__send_rdata__val [0:6]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_load_request_pkt__msg; - logic [0:0] data_mem__send_to_noc_load_request_pkt__rdy; - logic [0:0] data_mem__send_to_noc_load_request_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_load_response_pkt__msg; - logic [0:0] data_mem__send_to_noc_load_response_pkt__rdy; - logic [0:0] data_mem__send_to_noc_load_response_pkt__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d data_mem__send_to_noc_store_pkt__msg; - logic [0:0] data_mem__send_to_noc_store_pkt__rdy; - logic [0:0] data_mem__send_to_noc_store_pkt__val; - - DataMemControllerRTL__20df9b544ed809f0 data_mem - ( - .address_lower( data_mem__address_lower ), - .address_upper( data_mem__address_upper ), - .cgra_id( data_mem__cgra_id ), - .clk( data_mem__clk ), - .reset( data_mem__reset ), - .recv_from_noc_load_request__msg( data_mem__recv_from_noc_load_request__msg ), - .recv_from_noc_load_request__rdy( data_mem__recv_from_noc_load_request__rdy ), - .recv_from_noc_load_request__val( data_mem__recv_from_noc_load_request__val ), - .recv_from_noc_load_response_pkt__msg( data_mem__recv_from_noc_load_response_pkt__msg ), - .recv_from_noc_load_response_pkt__rdy( data_mem__recv_from_noc_load_response_pkt__rdy ), - .recv_from_noc_load_response_pkt__val( data_mem__recv_from_noc_load_response_pkt__val ), - .recv_from_noc_store_request__msg( data_mem__recv_from_noc_store_request__msg ), - .recv_from_noc_store_request__rdy( data_mem__recv_from_noc_store_request__rdy ), - .recv_from_noc_store_request__val( data_mem__recv_from_noc_store_request__val ), - .recv_raddr__msg( data_mem__recv_raddr__msg ), - .recv_raddr__rdy( data_mem__recv_raddr__rdy ), - .recv_raddr__val( data_mem__recv_raddr__val ), - .recv_waddr__msg( data_mem__recv_waddr__msg ), - .recv_waddr__rdy( data_mem__recv_waddr__rdy ), - .recv_waddr__val( data_mem__recv_waddr__val ), - .recv_wdata__msg( data_mem__recv_wdata__msg ), - .recv_wdata__rdy( data_mem__recv_wdata__rdy ), - .recv_wdata__val( data_mem__recv_wdata__val ), - .send_rdata__msg( data_mem__send_rdata__msg ), - .send_rdata__rdy( data_mem__send_rdata__rdy ), - .send_rdata__val( data_mem__send_rdata__val ), - .send_to_noc_load_request_pkt__msg( data_mem__send_to_noc_load_request_pkt__msg ), - .send_to_noc_load_request_pkt__rdy( data_mem__send_to_noc_load_request_pkt__rdy ), - .send_to_noc_load_request_pkt__val( data_mem__send_to_noc_load_request_pkt__val ), - .send_to_noc_load_response_pkt__msg( data_mem__send_to_noc_load_response_pkt__msg ), - .send_to_noc_load_response_pkt__rdy( data_mem__send_to_noc_load_response_pkt__rdy ), - .send_to_noc_load_response_pkt__val( data_mem__send_to_noc_load_response_pkt__val ), - .send_to_noc_store_pkt__msg( data_mem__send_to_noc_store_pkt__msg ), - .send_to_noc_store_pkt__rdy( data_mem__send_to_noc_store_pkt__rdy ), - .send_to_noc_store_pkt__val( data_mem__send_to_noc_store_pkt__val ) - ); - - //------------------------------------------------------------- - // End of component data_mem - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component tile[0:15] - //------------------------------------------------------------- - - logic [1:0] tile__cgra_id [0:15]; - logic [0:0] tile__clk [0:15]; - logic [0:0] tile__reset [0:15]; - logic [4:0] tile__tile_id [0:15]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__from_mem_rdata__msg [0:15]; - logic [0:0] tile__from_mem_rdata__rdy [0:15]; - logic [0:0] tile__from_mem_rdata__val [0:15]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__recv_data__msg [0:15][0:3]; - logic [0:0] tile__recv_data__rdy [0:15][0:3]; - logic [0:0] tile__recv_data__val [0:15][0:3]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 tile__recv_from_controller_pkt__msg [0:15]; - logic [0:0] tile__recv_from_controller_pkt__rdy [0:15]; - logic [0:0] tile__recv_from_controller_pkt__val [0:15]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__send_data__msg [0:15][0:3]; - logic [0:0] tile__send_data__rdy [0:15][0:3]; - logic [0:0] tile__send_data__val [0:15][0:3]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 tile__send_to_controller_pkt__msg [0:15]; - logic [0:0] tile__send_to_controller_pkt__rdy [0:15]; - logic [0:0] tile__send_to_controller_pkt__val [0:15]; - logic [6:0] tile__to_mem_raddr__msg [0:15]; - logic [0:0] tile__to_mem_raddr__rdy [0:15]; - logic [0:0] tile__to_mem_raddr__val [0:15]; - logic [6:0] tile__to_mem_waddr__msg [0:15]; - logic [0:0] tile__to_mem_waddr__rdy [0:15]; - logic [0:0] tile__to_mem_waddr__val [0:15]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 tile__to_mem_wdata__msg [0:15]; - logic [0:0] tile__to_mem_wdata__rdy [0:15]; - logic [0:0] tile__to_mem_wdata__val [0:15]; - - TileRTL__78da5e3970e1cd1d tile__0 - ( - .cgra_id( tile__cgra_id[0] ), - .clk( tile__clk[0] ), - .reset( tile__reset[0] ), - .tile_id( tile__tile_id[0] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[0] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[0] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[0] ), - .recv_data__msg( tile__recv_data__msg[0] ), - .recv_data__rdy( tile__recv_data__rdy[0] ), - .recv_data__val( tile__recv_data__val[0] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[0] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[0] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[0] ), - .send_data__msg( tile__send_data__msg[0] ), - .send_data__rdy( tile__send_data__rdy[0] ), - .send_data__val( tile__send_data__val[0] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[0] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[0] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[0] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[0] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[0] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[0] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[0] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[0] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[0] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[0] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[0] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[0] ) - ); - - TileRTL__78da5e3970e1cd1d tile__1 - ( - .cgra_id( tile__cgra_id[1] ), - .clk( tile__clk[1] ), - .reset( tile__reset[1] ), - .tile_id( tile__tile_id[1] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[1] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[1] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[1] ), - .recv_data__msg( tile__recv_data__msg[1] ), - .recv_data__rdy( tile__recv_data__rdy[1] ), - .recv_data__val( tile__recv_data__val[1] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[1] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[1] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[1] ), - .send_data__msg( tile__send_data__msg[1] ), - .send_data__rdy( tile__send_data__rdy[1] ), - .send_data__val( tile__send_data__val[1] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[1] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[1] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[1] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[1] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[1] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[1] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[1] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[1] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[1] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[1] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[1] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[1] ) - ); - - TileRTL__78da5e3970e1cd1d tile__2 - ( - .cgra_id( tile__cgra_id[2] ), - .clk( tile__clk[2] ), - .reset( tile__reset[2] ), - .tile_id( tile__tile_id[2] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[2] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[2] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[2] ), - .recv_data__msg( tile__recv_data__msg[2] ), - .recv_data__rdy( tile__recv_data__rdy[2] ), - .recv_data__val( tile__recv_data__val[2] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[2] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[2] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[2] ), - .send_data__msg( tile__send_data__msg[2] ), - .send_data__rdy( tile__send_data__rdy[2] ), - .send_data__val( tile__send_data__val[2] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[2] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[2] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[2] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[2] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[2] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[2] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[2] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[2] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[2] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[2] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[2] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[2] ) - ); - - TileRTL__78da5e3970e1cd1d tile__3 - ( - .cgra_id( tile__cgra_id[3] ), - .clk( tile__clk[3] ), - .reset( tile__reset[3] ), - .tile_id( tile__tile_id[3] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[3] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[3] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[3] ), - .recv_data__msg( tile__recv_data__msg[3] ), - .recv_data__rdy( tile__recv_data__rdy[3] ), - .recv_data__val( tile__recv_data__val[3] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[3] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[3] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[3] ), - .send_data__msg( tile__send_data__msg[3] ), - .send_data__rdy( tile__send_data__rdy[3] ), - .send_data__val( tile__send_data__val[3] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[3] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[3] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[3] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[3] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[3] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[3] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[3] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[3] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[3] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[3] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[3] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[3] ) - ); - - TileRTL__78da5e3970e1cd1d tile__4 - ( - .cgra_id( tile__cgra_id[4] ), - .clk( tile__clk[4] ), - .reset( tile__reset[4] ), - .tile_id( tile__tile_id[4] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[4] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[4] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[4] ), - .recv_data__msg( tile__recv_data__msg[4] ), - .recv_data__rdy( tile__recv_data__rdy[4] ), - .recv_data__val( tile__recv_data__val[4] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[4] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[4] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[4] ), - .send_data__msg( tile__send_data__msg[4] ), - .send_data__rdy( tile__send_data__rdy[4] ), - .send_data__val( tile__send_data__val[4] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[4] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[4] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[4] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[4] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[4] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[4] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[4] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[4] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[4] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[4] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[4] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[4] ) - ); - - TileRTL__78da5e3970e1cd1d tile__5 - ( - .cgra_id( tile__cgra_id[5] ), - .clk( tile__clk[5] ), - .reset( tile__reset[5] ), - .tile_id( tile__tile_id[5] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[5] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[5] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[5] ), - .recv_data__msg( tile__recv_data__msg[5] ), - .recv_data__rdy( tile__recv_data__rdy[5] ), - .recv_data__val( tile__recv_data__val[5] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[5] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[5] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[5] ), - .send_data__msg( tile__send_data__msg[5] ), - .send_data__rdy( tile__send_data__rdy[5] ), - .send_data__val( tile__send_data__val[5] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[5] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[5] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[5] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[5] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[5] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[5] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[5] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[5] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[5] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[5] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[5] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[5] ) - ); - - TileRTL__78da5e3970e1cd1d tile__6 - ( - .cgra_id( tile__cgra_id[6] ), - .clk( tile__clk[6] ), - .reset( tile__reset[6] ), - .tile_id( tile__tile_id[6] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[6] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[6] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[6] ), - .recv_data__msg( tile__recv_data__msg[6] ), - .recv_data__rdy( tile__recv_data__rdy[6] ), - .recv_data__val( tile__recv_data__val[6] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[6] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[6] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[6] ), - .send_data__msg( tile__send_data__msg[6] ), - .send_data__rdy( tile__send_data__rdy[6] ), - .send_data__val( tile__send_data__val[6] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[6] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[6] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[6] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[6] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[6] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[6] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[6] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[6] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[6] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[6] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[6] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[6] ) - ); - - TileRTL__78da5e3970e1cd1d tile__7 - ( - .cgra_id( tile__cgra_id[7] ), - .clk( tile__clk[7] ), - .reset( tile__reset[7] ), - .tile_id( tile__tile_id[7] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[7] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[7] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[7] ), - .recv_data__msg( tile__recv_data__msg[7] ), - .recv_data__rdy( tile__recv_data__rdy[7] ), - .recv_data__val( tile__recv_data__val[7] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[7] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[7] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[7] ), - .send_data__msg( tile__send_data__msg[7] ), - .send_data__rdy( tile__send_data__rdy[7] ), - .send_data__val( tile__send_data__val[7] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[7] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[7] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[7] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[7] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[7] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[7] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[7] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[7] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[7] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[7] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[7] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[7] ) - ); - - TileRTL__78da5e3970e1cd1d tile__8 - ( - .cgra_id( tile__cgra_id[8] ), - .clk( tile__clk[8] ), - .reset( tile__reset[8] ), - .tile_id( tile__tile_id[8] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[8] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[8] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[8] ), - .recv_data__msg( tile__recv_data__msg[8] ), - .recv_data__rdy( tile__recv_data__rdy[8] ), - .recv_data__val( tile__recv_data__val[8] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[8] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[8] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[8] ), - .send_data__msg( tile__send_data__msg[8] ), - .send_data__rdy( tile__send_data__rdy[8] ), - .send_data__val( tile__send_data__val[8] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[8] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[8] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[8] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[8] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[8] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[8] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[8] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[8] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[8] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[8] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[8] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[8] ) - ); - - TileRTL__78da5e3970e1cd1d tile__9 - ( - .cgra_id( tile__cgra_id[9] ), - .clk( tile__clk[9] ), - .reset( tile__reset[9] ), - .tile_id( tile__tile_id[9] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[9] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[9] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[9] ), - .recv_data__msg( tile__recv_data__msg[9] ), - .recv_data__rdy( tile__recv_data__rdy[9] ), - .recv_data__val( tile__recv_data__val[9] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[9] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[9] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[9] ), - .send_data__msg( tile__send_data__msg[9] ), - .send_data__rdy( tile__send_data__rdy[9] ), - .send_data__val( tile__send_data__val[9] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[9] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[9] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[9] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[9] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[9] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[9] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[9] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[9] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[9] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[9] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[9] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[9] ) - ); - - TileRTL__78da5e3970e1cd1d tile__10 - ( - .cgra_id( tile__cgra_id[10] ), - .clk( tile__clk[10] ), - .reset( tile__reset[10] ), - .tile_id( tile__tile_id[10] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[10] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[10] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[10] ), - .recv_data__msg( tile__recv_data__msg[10] ), - .recv_data__rdy( tile__recv_data__rdy[10] ), - .recv_data__val( tile__recv_data__val[10] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[10] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[10] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[10] ), - .send_data__msg( tile__send_data__msg[10] ), - .send_data__rdy( tile__send_data__rdy[10] ), - .send_data__val( tile__send_data__val[10] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[10] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[10] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[10] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[10] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[10] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[10] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[10] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[10] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[10] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[10] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[10] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[10] ) - ); - - TileRTL__78da5e3970e1cd1d tile__11 - ( - .cgra_id( tile__cgra_id[11] ), - .clk( tile__clk[11] ), - .reset( tile__reset[11] ), - .tile_id( tile__tile_id[11] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[11] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[11] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[11] ), - .recv_data__msg( tile__recv_data__msg[11] ), - .recv_data__rdy( tile__recv_data__rdy[11] ), - .recv_data__val( tile__recv_data__val[11] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[11] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[11] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[11] ), - .send_data__msg( tile__send_data__msg[11] ), - .send_data__rdy( tile__send_data__rdy[11] ), - .send_data__val( tile__send_data__val[11] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[11] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[11] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[11] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[11] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[11] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[11] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[11] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[11] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[11] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[11] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[11] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[11] ) - ); - - TileRTL__78da5e3970e1cd1d tile__12 - ( - .cgra_id( tile__cgra_id[12] ), - .clk( tile__clk[12] ), - .reset( tile__reset[12] ), - .tile_id( tile__tile_id[12] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[12] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[12] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[12] ), - .recv_data__msg( tile__recv_data__msg[12] ), - .recv_data__rdy( tile__recv_data__rdy[12] ), - .recv_data__val( tile__recv_data__val[12] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[12] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[12] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[12] ), - .send_data__msg( tile__send_data__msg[12] ), - .send_data__rdy( tile__send_data__rdy[12] ), - .send_data__val( tile__send_data__val[12] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[12] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[12] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[12] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[12] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[12] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[12] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[12] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[12] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[12] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[12] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[12] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[12] ) - ); - - TileRTL__78da5e3970e1cd1d tile__13 - ( - .cgra_id( tile__cgra_id[13] ), - .clk( tile__clk[13] ), - .reset( tile__reset[13] ), - .tile_id( tile__tile_id[13] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[13] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[13] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[13] ), - .recv_data__msg( tile__recv_data__msg[13] ), - .recv_data__rdy( tile__recv_data__rdy[13] ), - .recv_data__val( tile__recv_data__val[13] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[13] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[13] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[13] ), - .send_data__msg( tile__send_data__msg[13] ), - .send_data__rdy( tile__send_data__rdy[13] ), - .send_data__val( tile__send_data__val[13] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[13] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[13] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[13] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[13] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[13] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[13] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[13] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[13] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[13] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[13] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[13] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[13] ) - ); - - TileRTL__78da5e3970e1cd1d tile__14 - ( - .cgra_id( tile__cgra_id[14] ), - .clk( tile__clk[14] ), - .reset( tile__reset[14] ), - .tile_id( tile__tile_id[14] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[14] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[14] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[14] ), - .recv_data__msg( tile__recv_data__msg[14] ), - .recv_data__rdy( tile__recv_data__rdy[14] ), - .recv_data__val( tile__recv_data__val[14] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[14] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[14] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[14] ), - .send_data__msg( tile__send_data__msg[14] ), - .send_data__rdy( tile__send_data__rdy[14] ), - .send_data__val( tile__send_data__val[14] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[14] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[14] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[14] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[14] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[14] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[14] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[14] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[14] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[14] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[14] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[14] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[14] ) - ); - - TileRTL__78da5e3970e1cd1d tile__15 - ( - .cgra_id( tile__cgra_id[15] ), - .clk( tile__clk[15] ), - .reset( tile__reset[15] ), - .tile_id( tile__tile_id[15] ), - .from_mem_rdata__msg( tile__from_mem_rdata__msg[15] ), - .from_mem_rdata__rdy( tile__from_mem_rdata__rdy[15] ), - .from_mem_rdata__val( tile__from_mem_rdata__val[15] ), - .recv_data__msg( tile__recv_data__msg[15] ), - .recv_data__rdy( tile__recv_data__rdy[15] ), - .recv_data__val( tile__recv_data__val[15] ), - .recv_from_controller_pkt__msg( tile__recv_from_controller_pkt__msg[15] ), - .recv_from_controller_pkt__rdy( tile__recv_from_controller_pkt__rdy[15] ), - .recv_from_controller_pkt__val( tile__recv_from_controller_pkt__val[15] ), - .send_data__msg( tile__send_data__msg[15] ), - .send_data__rdy( tile__send_data__rdy[15] ), - .send_data__val( tile__send_data__val[15] ), - .send_to_controller_pkt__msg( tile__send_to_controller_pkt__msg[15] ), - .send_to_controller_pkt__rdy( tile__send_to_controller_pkt__rdy[15] ), - .send_to_controller_pkt__val( tile__send_to_controller_pkt__val[15] ), - .to_mem_raddr__msg( tile__to_mem_raddr__msg[15] ), - .to_mem_raddr__rdy( tile__to_mem_raddr__rdy[15] ), - .to_mem_raddr__val( tile__to_mem_raddr__val[15] ), - .to_mem_waddr__msg( tile__to_mem_waddr__msg[15] ), - .to_mem_waddr__rdy( tile__to_mem_waddr__rdy[15] ), - .to_mem_waddr__val( tile__to_mem_waddr__val[15] ), - .to_mem_wdata__msg( tile__to_mem_wdata__msg[15] ), - .to_mem_wdata__rdy( tile__to_mem_wdata__rdy[15] ), - .to_mem_wdata__val( tile__to_mem_wdata__val[15] ) - ); - - //------------------------------------------------------------- - // End of component tile[0:15] - //------------------------------------------------------------- - - assign tile__clk[0] = clk; - assign tile__reset[0] = reset; - assign tile__clk[1] = clk; - assign tile__reset[1] = reset; - assign tile__clk[2] = clk; - assign tile__reset[2] = reset; - assign tile__clk[3] = clk; - assign tile__reset[3] = reset; - assign tile__clk[4] = clk; - assign tile__reset[4] = reset; - assign tile__clk[5] = clk; - assign tile__reset[5] = reset; - assign tile__clk[6] = clk; - assign tile__reset[6] = reset; - assign tile__clk[7] = clk; - assign tile__reset[7] = reset; - assign tile__clk[8] = clk; - assign tile__reset[8] = reset; - assign tile__clk[9] = clk; - assign tile__reset[9] = reset; - assign tile__clk[10] = clk; - assign tile__reset[10] = reset; - assign tile__clk[11] = clk; - assign tile__reset[11] = reset; - assign tile__clk[12] = clk; - assign tile__reset[12] = reset; - assign tile__clk[13] = clk; - assign tile__reset[13] = reset; - assign tile__clk[14] = clk; - assign tile__reset[14] = reset; - assign tile__clk[15] = clk; - assign tile__reset[15] = reset; - assign data_mem__clk = clk; - assign data_mem__reset = reset; - assign controller__clk = clk; - assign controller__reset = reset; - assign ctrl_ring__clk = clk; - assign ctrl_ring__reset = reset; - assign controller__cgra_id = cgra_id; - assign data_mem__cgra_id = cgra_id; - assign data_mem__address_lower = address_lower; - assign data_mem__address_upper = address_upper; - assign data_mem__recv_from_noc_load_request__msg = controller__send_to_mem_load_request__msg; - assign controller__send_to_mem_load_request__rdy = data_mem__recv_from_noc_load_request__rdy; - assign data_mem__recv_from_noc_load_request__val = controller__send_to_mem_load_request__val; - assign data_mem__recv_from_noc_store_request__msg = controller__send_to_mem_store_request__msg; - assign controller__send_to_mem_store_request__rdy = data_mem__recv_from_noc_store_request__rdy; - assign data_mem__recv_from_noc_store_request__val = controller__send_to_mem_store_request__val; - assign data_mem__recv_from_noc_load_response_pkt__msg = controller__send_to_tile_load_response__msg; - assign controller__send_to_tile_load_response__rdy = data_mem__recv_from_noc_load_response_pkt__rdy; - assign data_mem__recv_from_noc_load_response_pkt__val = controller__send_to_tile_load_response__val; - assign controller__recv_from_tile_load_request_pkt__msg = data_mem__send_to_noc_load_request_pkt__msg; - assign data_mem__send_to_noc_load_request_pkt__rdy = controller__recv_from_tile_load_request_pkt__rdy; - assign controller__recv_from_tile_load_request_pkt__val = data_mem__send_to_noc_load_request_pkt__val; - assign controller__recv_from_tile_load_response_pkt__msg = data_mem__send_to_noc_load_response_pkt__msg; - assign data_mem__send_to_noc_load_response_pkt__rdy = controller__recv_from_tile_load_response_pkt__rdy; - assign controller__recv_from_tile_load_response_pkt__val = data_mem__send_to_noc_load_response_pkt__val; - assign controller__recv_from_tile_store_request_pkt__msg = data_mem__send_to_noc_store_pkt__msg; - assign data_mem__send_to_noc_store_pkt__rdy = controller__recv_from_tile_store_request_pkt__rdy; - assign controller__recv_from_tile_store_request_pkt__val = data_mem__send_to_noc_store_pkt__val; - assign controller__recv_from_inter_cgra_noc__msg = recv_from_inter_cgra_noc__msg; - assign recv_from_inter_cgra_noc__rdy = controller__recv_from_inter_cgra_noc__rdy; - assign controller__recv_from_inter_cgra_noc__val = recv_from_inter_cgra_noc__val; - assign send_to_inter_cgra_noc__msg = controller__send_to_inter_cgra_noc__msg; - assign controller__send_to_inter_cgra_noc__rdy = send_to_inter_cgra_noc__rdy; - assign send_to_inter_cgra_noc__val = controller__send_to_inter_cgra_noc__val; - assign controller__recv_from_cpu_pkt__msg = recv_from_cpu_pkt__msg; - assign recv_from_cpu_pkt__rdy = controller__recv_from_cpu_pkt__rdy; - assign controller__recv_from_cpu_pkt__val = recv_from_cpu_pkt__val; - assign send_to_cpu_pkt__msg = controller__send_to_cpu_pkt__msg; - assign controller__send_to_cpu_pkt__rdy = send_to_cpu_pkt__rdy; - assign send_to_cpu_pkt__val = controller__send_to_cpu_pkt__val; - assign tile__tile_id[0] = 5'd0; - assign tile__cgra_id[0] = cgra_id; - assign tile__tile_id[1] = 5'd1; - assign tile__cgra_id[1] = cgra_id; - assign tile__tile_id[2] = 5'd2; - assign tile__cgra_id[2] = cgra_id; - assign tile__tile_id[3] = 5'd3; - assign tile__cgra_id[3] = cgra_id; - assign tile__tile_id[4] = 5'd4; - assign tile__cgra_id[4] = cgra_id; - assign tile__tile_id[5] = 5'd5; - assign tile__cgra_id[5] = cgra_id; - assign tile__tile_id[6] = 5'd6; - assign tile__cgra_id[6] = cgra_id; - assign tile__tile_id[7] = 5'd7; - assign tile__cgra_id[7] = cgra_id; - assign tile__tile_id[8] = 5'd8; - assign tile__cgra_id[8] = cgra_id; - assign tile__tile_id[9] = 5'd9; - assign tile__cgra_id[9] = cgra_id; - assign tile__tile_id[10] = 5'd10; - assign tile__cgra_id[10] = cgra_id; - assign tile__tile_id[11] = 5'd11; - assign tile__cgra_id[11] = cgra_id; - assign tile__tile_id[12] = 5'd12; - assign tile__cgra_id[12] = cgra_id; - assign tile__tile_id[13] = 5'd13; - assign tile__cgra_id[13] = cgra_id; - assign tile__tile_id[14] = 5'd14; - assign tile__cgra_id[14] = cgra_id; - assign tile__tile_id[15] = 5'd15; - assign tile__cgra_id[15] = cgra_id; - assign tile__recv_from_controller_pkt__msg[0] = ctrl_ring__send__msg[0]; - assign ctrl_ring__send__rdy[0] = tile__recv_from_controller_pkt__rdy[0]; - assign tile__recv_from_controller_pkt__val[0] = ctrl_ring__send__val[0]; - assign ctrl_ring__recv__msg[0] = tile__send_to_controller_pkt__msg[0]; - assign tile__send_to_controller_pkt__rdy[0] = ctrl_ring__recv__rdy[0]; - assign ctrl_ring__recv__val[0] = tile__send_to_controller_pkt__val[0]; - assign tile__recv_from_controller_pkt__msg[1] = ctrl_ring__send__msg[1]; - assign ctrl_ring__send__rdy[1] = tile__recv_from_controller_pkt__rdy[1]; - assign tile__recv_from_controller_pkt__val[1] = ctrl_ring__send__val[1]; - assign ctrl_ring__recv__msg[1] = tile__send_to_controller_pkt__msg[1]; - assign tile__send_to_controller_pkt__rdy[1] = ctrl_ring__recv__rdy[1]; - assign ctrl_ring__recv__val[1] = tile__send_to_controller_pkt__val[1]; - assign tile__recv_from_controller_pkt__msg[2] = ctrl_ring__send__msg[2]; - assign ctrl_ring__send__rdy[2] = tile__recv_from_controller_pkt__rdy[2]; - assign tile__recv_from_controller_pkt__val[2] = ctrl_ring__send__val[2]; - assign ctrl_ring__recv__msg[2] = tile__send_to_controller_pkt__msg[2]; - assign tile__send_to_controller_pkt__rdy[2] = ctrl_ring__recv__rdy[2]; - assign ctrl_ring__recv__val[2] = tile__send_to_controller_pkt__val[2]; - assign tile__recv_from_controller_pkt__msg[3] = ctrl_ring__send__msg[3]; - assign ctrl_ring__send__rdy[3] = tile__recv_from_controller_pkt__rdy[3]; - assign tile__recv_from_controller_pkt__val[3] = ctrl_ring__send__val[3]; - assign ctrl_ring__recv__msg[3] = tile__send_to_controller_pkt__msg[3]; - assign tile__send_to_controller_pkt__rdy[3] = ctrl_ring__recv__rdy[3]; - assign ctrl_ring__recv__val[3] = tile__send_to_controller_pkt__val[3]; - assign tile__recv_from_controller_pkt__msg[4] = ctrl_ring__send__msg[4]; - assign ctrl_ring__send__rdy[4] = tile__recv_from_controller_pkt__rdy[4]; - assign tile__recv_from_controller_pkt__val[4] = ctrl_ring__send__val[4]; - assign ctrl_ring__recv__msg[4] = tile__send_to_controller_pkt__msg[4]; - assign tile__send_to_controller_pkt__rdy[4] = ctrl_ring__recv__rdy[4]; - assign ctrl_ring__recv__val[4] = tile__send_to_controller_pkt__val[4]; - assign tile__recv_from_controller_pkt__msg[5] = ctrl_ring__send__msg[5]; - assign ctrl_ring__send__rdy[5] = tile__recv_from_controller_pkt__rdy[5]; - assign tile__recv_from_controller_pkt__val[5] = ctrl_ring__send__val[5]; - assign ctrl_ring__recv__msg[5] = tile__send_to_controller_pkt__msg[5]; - assign tile__send_to_controller_pkt__rdy[5] = ctrl_ring__recv__rdy[5]; - assign ctrl_ring__recv__val[5] = tile__send_to_controller_pkt__val[5]; - assign tile__recv_from_controller_pkt__msg[6] = ctrl_ring__send__msg[6]; - assign ctrl_ring__send__rdy[6] = tile__recv_from_controller_pkt__rdy[6]; - assign tile__recv_from_controller_pkt__val[6] = ctrl_ring__send__val[6]; - assign ctrl_ring__recv__msg[6] = tile__send_to_controller_pkt__msg[6]; - assign tile__send_to_controller_pkt__rdy[6] = ctrl_ring__recv__rdy[6]; - assign ctrl_ring__recv__val[6] = tile__send_to_controller_pkt__val[6]; - assign tile__recv_from_controller_pkt__msg[7] = ctrl_ring__send__msg[7]; - assign ctrl_ring__send__rdy[7] = tile__recv_from_controller_pkt__rdy[7]; - assign tile__recv_from_controller_pkt__val[7] = ctrl_ring__send__val[7]; - assign ctrl_ring__recv__msg[7] = tile__send_to_controller_pkt__msg[7]; - assign tile__send_to_controller_pkt__rdy[7] = ctrl_ring__recv__rdy[7]; - assign ctrl_ring__recv__val[7] = tile__send_to_controller_pkt__val[7]; - assign tile__recv_from_controller_pkt__msg[8] = ctrl_ring__send__msg[8]; - assign ctrl_ring__send__rdy[8] = tile__recv_from_controller_pkt__rdy[8]; - assign tile__recv_from_controller_pkt__val[8] = ctrl_ring__send__val[8]; - assign ctrl_ring__recv__msg[8] = tile__send_to_controller_pkt__msg[8]; - assign tile__send_to_controller_pkt__rdy[8] = ctrl_ring__recv__rdy[8]; - assign ctrl_ring__recv__val[8] = tile__send_to_controller_pkt__val[8]; - assign tile__recv_from_controller_pkt__msg[9] = ctrl_ring__send__msg[9]; - assign ctrl_ring__send__rdy[9] = tile__recv_from_controller_pkt__rdy[9]; - assign tile__recv_from_controller_pkt__val[9] = ctrl_ring__send__val[9]; - assign ctrl_ring__recv__msg[9] = tile__send_to_controller_pkt__msg[9]; - assign tile__send_to_controller_pkt__rdy[9] = ctrl_ring__recv__rdy[9]; - assign ctrl_ring__recv__val[9] = tile__send_to_controller_pkt__val[9]; - assign tile__recv_from_controller_pkt__msg[10] = ctrl_ring__send__msg[10]; - assign ctrl_ring__send__rdy[10] = tile__recv_from_controller_pkt__rdy[10]; - assign tile__recv_from_controller_pkt__val[10] = ctrl_ring__send__val[10]; - assign ctrl_ring__recv__msg[10] = tile__send_to_controller_pkt__msg[10]; - assign tile__send_to_controller_pkt__rdy[10] = ctrl_ring__recv__rdy[10]; - assign ctrl_ring__recv__val[10] = tile__send_to_controller_pkt__val[10]; - assign tile__recv_from_controller_pkt__msg[11] = ctrl_ring__send__msg[11]; - assign ctrl_ring__send__rdy[11] = tile__recv_from_controller_pkt__rdy[11]; - assign tile__recv_from_controller_pkt__val[11] = ctrl_ring__send__val[11]; - assign ctrl_ring__recv__msg[11] = tile__send_to_controller_pkt__msg[11]; - assign tile__send_to_controller_pkt__rdy[11] = ctrl_ring__recv__rdy[11]; - assign ctrl_ring__recv__val[11] = tile__send_to_controller_pkt__val[11]; - assign tile__recv_from_controller_pkt__msg[12] = ctrl_ring__send__msg[12]; - assign ctrl_ring__send__rdy[12] = tile__recv_from_controller_pkt__rdy[12]; - assign tile__recv_from_controller_pkt__val[12] = ctrl_ring__send__val[12]; - assign ctrl_ring__recv__msg[12] = tile__send_to_controller_pkt__msg[12]; - assign tile__send_to_controller_pkt__rdy[12] = ctrl_ring__recv__rdy[12]; - assign ctrl_ring__recv__val[12] = tile__send_to_controller_pkt__val[12]; - assign tile__recv_from_controller_pkt__msg[13] = ctrl_ring__send__msg[13]; - assign ctrl_ring__send__rdy[13] = tile__recv_from_controller_pkt__rdy[13]; - assign tile__recv_from_controller_pkt__val[13] = ctrl_ring__send__val[13]; - assign ctrl_ring__recv__msg[13] = tile__send_to_controller_pkt__msg[13]; - assign tile__send_to_controller_pkt__rdy[13] = ctrl_ring__recv__rdy[13]; - assign ctrl_ring__recv__val[13] = tile__send_to_controller_pkt__val[13]; - assign tile__recv_from_controller_pkt__msg[14] = ctrl_ring__send__msg[14]; - assign ctrl_ring__send__rdy[14] = tile__recv_from_controller_pkt__rdy[14]; - assign tile__recv_from_controller_pkt__val[14] = ctrl_ring__send__val[14]; - assign ctrl_ring__recv__msg[14] = tile__send_to_controller_pkt__msg[14]; - assign tile__send_to_controller_pkt__rdy[14] = ctrl_ring__recv__rdy[14]; - assign ctrl_ring__recv__val[14] = tile__send_to_controller_pkt__val[14]; - assign tile__recv_from_controller_pkt__msg[15] = ctrl_ring__send__msg[15]; - assign ctrl_ring__send__rdy[15] = tile__recv_from_controller_pkt__rdy[15]; - assign tile__recv_from_controller_pkt__val[15] = ctrl_ring__send__val[15]; - assign ctrl_ring__recv__msg[15] = tile__send_to_controller_pkt__msg[15]; - assign tile__send_to_controller_pkt__rdy[15] = ctrl_ring__recv__rdy[15]; - assign ctrl_ring__recv__val[15] = tile__send_to_controller_pkt__val[15]; - assign ctrl_ring__recv__msg[16] = controller__send_to_ctrl_ring_pkt__msg; - assign controller__send_to_ctrl_ring_pkt__rdy = ctrl_ring__recv__rdy[16]; - assign ctrl_ring__recv__val[16] = controller__send_to_ctrl_ring_pkt__val; - assign controller__recv_from_ctrl_ring_pkt__msg = ctrl_ring__send__msg[16]; - assign ctrl_ring__send__rdy[16] = controller__recv_from_ctrl_ring_pkt__rdy; - assign controller__recv_from_ctrl_ring_pkt__val = ctrl_ring__send__val[16]; - assign tile__recv_data__msg[4][1] = tile__send_data__msg[0][0]; - assign tile__send_data__rdy[0][0] = tile__recv_data__rdy[4][1]; - assign tile__recv_data__val[4][1] = tile__send_data__val[0][0]; - assign tile__recv_data__msg[1][2] = tile__send_data__msg[0][3]; - assign tile__send_data__rdy[0][3] = tile__recv_data__rdy[1][2]; - assign tile__recv_data__val[1][2] = tile__send_data__val[0][3]; - assign send_data_on_boundary_south__msg[0] = tile__send_data__msg[0][1]; - assign tile__send_data__rdy[0][1] = send_data_on_boundary_south__rdy[0]; - assign send_data_on_boundary_south__val[0] = tile__send_data__val[0][1]; - assign tile__recv_data__msg[0][1] = recv_data_on_boundary_south__msg[0]; - assign recv_data_on_boundary_south__rdy[0] = tile__recv_data__rdy[0][1]; - assign tile__recv_data__val[0][1] = recv_data_on_boundary_south__val[0]; - assign send_data_on_boundary_west__msg[0] = tile__send_data__msg[0][2]; - assign tile__send_data__rdy[0][2] = send_data_on_boundary_west__rdy[0]; - assign send_data_on_boundary_west__val[0] = tile__send_data__val[0][2]; - assign tile__recv_data__msg[0][2] = recv_data_on_boundary_west__msg[0]; - assign recv_data_on_boundary_west__rdy[0] = tile__recv_data__rdy[0][2]; - assign tile__recv_data__val[0][2] = recv_data_on_boundary_west__val[0]; - assign data_mem__recv_raddr__msg[0] = tile__to_mem_raddr__msg[0]; - assign tile__to_mem_raddr__rdy[0] = data_mem__recv_raddr__rdy[0]; - assign data_mem__recv_raddr__val[0] = tile__to_mem_raddr__val[0]; - assign tile__from_mem_rdata__msg[0] = data_mem__send_rdata__msg[0]; - assign data_mem__send_rdata__rdy[0] = tile__from_mem_rdata__rdy[0]; - assign tile__from_mem_rdata__val[0] = data_mem__send_rdata__val[0]; - assign data_mem__recv_waddr__msg[0] = tile__to_mem_waddr__msg[0]; - assign tile__to_mem_waddr__rdy[0] = data_mem__recv_waddr__rdy[0]; - assign data_mem__recv_waddr__val[0] = tile__to_mem_waddr__val[0]; - assign data_mem__recv_wdata__msg[0] = tile__to_mem_wdata__msg[0]; - assign tile__to_mem_wdata__rdy[0] = data_mem__recv_wdata__rdy[0]; - assign data_mem__recv_wdata__val[0] = tile__to_mem_wdata__val[0]; - assign tile__recv_data__msg[5][1] = tile__send_data__msg[1][0]; - assign tile__send_data__rdy[1][0] = tile__recv_data__rdy[5][1]; - assign tile__recv_data__val[5][1] = tile__send_data__val[1][0]; - assign tile__recv_data__msg[0][3] = tile__send_data__msg[1][2]; - assign tile__send_data__rdy[1][2] = tile__recv_data__rdy[0][3]; - assign tile__recv_data__val[0][3] = tile__send_data__val[1][2]; - assign tile__recv_data__msg[2][2] = tile__send_data__msg[1][3]; - assign tile__send_data__rdy[1][3] = tile__recv_data__rdy[2][2]; - assign tile__recv_data__val[2][2] = tile__send_data__val[1][3]; - assign send_data_on_boundary_south__msg[1] = tile__send_data__msg[1][1]; - assign tile__send_data__rdy[1][1] = send_data_on_boundary_south__rdy[1]; - assign send_data_on_boundary_south__val[1] = tile__send_data__val[1][1]; - assign tile__recv_data__msg[1][1] = recv_data_on_boundary_south__msg[1]; - assign recv_data_on_boundary_south__rdy[1] = tile__recv_data__rdy[1][1]; - assign tile__recv_data__val[1][1] = recv_data_on_boundary_south__val[1]; - assign data_mem__recv_raddr__msg[1] = tile__to_mem_raddr__msg[1]; - assign tile__to_mem_raddr__rdy[1] = data_mem__recv_raddr__rdy[1]; - assign data_mem__recv_raddr__val[1] = tile__to_mem_raddr__val[1]; - assign tile__from_mem_rdata__msg[1] = data_mem__send_rdata__msg[1]; - assign data_mem__send_rdata__rdy[1] = tile__from_mem_rdata__rdy[1]; - assign tile__from_mem_rdata__val[1] = data_mem__send_rdata__val[1]; - assign data_mem__recv_waddr__msg[1] = tile__to_mem_waddr__msg[1]; - assign tile__to_mem_waddr__rdy[1] = data_mem__recv_waddr__rdy[1]; - assign data_mem__recv_waddr__val[1] = tile__to_mem_waddr__val[1]; - assign data_mem__recv_wdata__msg[1] = tile__to_mem_wdata__msg[1]; - assign tile__to_mem_wdata__rdy[1] = data_mem__recv_wdata__rdy[1]; - assign data_mem__recv_wdata__val[1] = tile__to_mem_wdata__val[1]; - assign tile__recv_data__msg[6][1] = tile__send_data__msg[2][0]; - assign tile__send_data__rdy[2][0] = tile__recv_data__rdy[6][1]; - assign tile__recv_data__val[6][1] = tile__send_data__val[2][0]; - assign tile__recv_data__msg[1][3] = tile__send_data__msg[2][2]; - assign tile__send_data__rdy[2][2] = tile__recv_data__rdy[1][3]; - assign tile__recv_data__val[1][3] = tile__send_data__val[2][2]; - assign tile__recv_data__msg[3][2] = tile__send_data__msg[2][3]; - assign tile__send_data__rdy[2][3] = tile__recv_data__rdy[3][2]; - assign tile__recv_data__val[3][2] = tile__send_data__val[2][3]; - assign send_data_on_boundary_south__msg[2] = tile__send_data__msg[2][1]; - assign tile__send_data__rdy[2][1] = send_data_on_boundary_south__rdy[2]; - assign send_data_on_boundary_south__val[2] = tile__send_data__val[2][1]; - assign tile__recv_data__msg[2][1] = recv_data_on_boundary_south__msg[2]; - assign recv_data_on_boundary_south__rdy[2] = tile__recv_data__rdy[2][1]; - assign tile__recv_data__val[2][1] = recv_data_on_boundary_south__val[2]; - assign data_mem__recv_raddr__msg[2] = tile__to_mem_raddr__msg[2]; - assign tile__to_mem_raddr__rdy[2] = data_mem__recv_raddr__rdy[2]; - assign data_mem__recv_raddr__val[2] = tile__to_mem_raddr__val[2]; - assign tile__from_mem_rdata__msg[2] = data_mem__send_rdata__msg[2]; - assign data_mem__send_rdata__rdy[2] = tile__from_mem_rdata__rdy[2]; - assign tile__from_mem_rdata__val[2] = data_mem__send_rdata__val[2]; - assign data_mem__recv_waddr__msg[2] = tile__to_mem_waddr__msg[2]; - assign tile__to_mem_waddr__rdy[2] = data_mem__recv_waddr__rdy[2]; - assign data_mem__recv_waddr__val[2] = tile__to_mem_waddr__val[2]; - assign data_mem__recv_wdata__msg[2] = tile__to_mem_wdata__msg[2]; - assign tile__to_mem_wdata__rdy[2] = data_mem__recv_wdata__rdy[2]; - assign data_mem__recv_wdata__val[2] = tile__to_mem_wdata__val[2]; - assign tile__recv_data__msg[7][1] = tile__send_data__msg[3][0]; - assign tile__send_data__rdy[3][0] = tile__recv_data__rdy[7][1]; - assign tile__recv_data__val[7][1] = tile__send_data__val[3][0]; - assign tile__recv_data__msg[2][3] = tile__send_data__msg[3][2]; - assign tile__send_data__rdy[3][2] = tile__recv_data__rdy[2][3]; - assign tile__recv_data__val[2][3] = tile__send_data__val[3][2]; - assign send_data_on_boundary_south__msg[3] = tile__send_data__msg[3][1]; - assign tile__send_data__rdy[3][1] = send_data_on_boundary_south__rdy[3]; - assign send_data_on_boundary_south__val[3] = tile__send_data__val[3][1]; - assign tile__recv_data__msg[3][1] = recv_data_on_boundary_south__msg[3]; - assign recv_data_on_boundary_south__rdy[3] = tile__recv_data__rdy[3][1]; - assign tile__recv_data__val[3][1] = recv_data_on_boundary_south__val[3]; - assign send_data_on_boundary_east__msg[0] = tile__send_data__msg[3][3]; - assign tile__send_data__rdy[3][3] = send_data_on_boundary_east__rdy[0]; - assign send_data_on_boundary_east__val[0] = tile__send_data__val[3][3]; - assign tile__recv_data__msg[3][3] = recv_data_on_boundary_east__msg[0]; - assign recv_data_on_boundary_east__rdy[0] = tile__recv_data__rdy[3][3]; - assign tile__recv_data__val[3][3] = recv_data_on_boundary_east__val[0]; - assign data_mem__recv_raddr__msg[3] = tile__to_mem_raddr__msg[3]; - assign tile__to_mem_raddr__rdy[3] = data_mem__recv_raddr__rdy[3]; - assign data_mem__recv_raddr__val[3] = tile__to_mem_raddr__val[3]; - assign tile__from_mem_rdata__msg[3] = data_mem__send_rdata__msg[3]; - assign data_mem__send_rdata__rdy[3] = tile__from_mem_rdata__rdy[3]; - assign tile__from_mem_rdata__val[3] = data_mem__send_rdata__val[3]; - assign data_mem__recv_waddr__msg[3] = tile__to_mem_waddr__msg[3]; - assign tile__to_mem_waddr__rdy[3] = data_mem__recv_waddr__rdy[3]; - assign data_mem__recv_waddr__val[3] = tile__to_mem_waddr__val[3]; - assign data_mem__recv_wdata__msg[3] = tile__to_mem_wdata__msg[3]; - assign tile__to_mem_wdata__rdy[3] = data_mem__recv_wdata__rdy[3]; - assign data_mem__recv_wdata__val[3] = tile__to_mem_wdata__val[3]; - assign tile__recv_data__msg[0][0] = tile__send_data__msg[4][1]; - assign tile__send_data__rdy[4][1] = tile__recv_data__rdy[0][0]; - assign tile__recv_data__val[0][0] = tile__send_data__val[4][1]; - assign tile__recv_data__msg[8][1] = tile__send_data__msg[4][0]; - assign tile__send_data__rdy[4][0] = tile__recv_data__rdy[8][1]; - assign tile__recv_data__val[8][1] = tile__send_data__val[4][0]; - assign tile__recv_data__msg[5][2] = tile__send_data__msg[4][3]; - assign tile__send_data__rdy[4][3] = tile__recv_data__rdy[5][2]; - assign tile__recv_data__val[5][2] = tile__send_data__val[4][3]; - assign send_data_on_boundary_west__msg[1] = tile__send_data__msg[4][2]; - assign tile__send_data__rdy[4][2] = send_data_on_boundary_west__rdy[1]; - assign send_data_on_boundary_west__val[1] = tile__send_data__val[4][2]; - assign tile__recv_data__msg[4][2] = recv_data_on_boundary_west__msg[1]; - assign recv_data_on_boundary_west__rdy[1] = tile__recv_data__rdy[4][2]; - assign tile__recv_data__val[4][2] = recv_data_on_boundary_west__val[1]; - assign data_mem__recv_raddr__msg[4] = tile__to_mem_raddr__msg[4]; - assign tile__to_mem_raddr__rdy[4] = data_mem__recv_raddr__rdy[4]; - assign data_mem__recv_raddr__val[4] = tile__to_mem_raddr__val[4]; - assign tile__from_mem_rdata__msg[4] = data_mem__send_rdata__msg[4]; - assign data_mem__send_rdata__rdy[4] = tile__from_mem_rdata__rdy[4]; - assign tile__from_mem_rdata__val[4] = data_mem__send_rdata__val[4]; - assign data_mem__recv_waddr__msg[4] = tile__to_mem_waddr__msg[4]; - assign tile__to_mem_waddr__rdy[4] = data_mem__recv_waddr__rdy[4]; - assign data_mem__recv_waddr__val[4] = tile__to_mem_waddr__val[4]; - assign data_mem__recv_wdata__msg[4] = tile__to_mem_wdata__msg[4]; - assign tile__to_mem_wdata__rdy[4] = data_mem__recv_wdata__rdy[4]; - assign data_mem__recv_wdata__val[4] = tile__to_mem_wdata__val[4]; - assign tile__recv_data__msg[1][0] = tile__send_data__msg[5][1]; - assign tile__send_data__rdy[5][1] = tile__recv_data__rdy[1][0]; - assign tile__recv_data__val[1][0] = tile__send_data__val[5][1]; - assign tile__recv_data__msg[9][1] = tile__send_data__msg[5][0]; - assign tile__send_data__rdy[5][0] = tile__recv_data__rdy[9][1]; - assign tile__recv_data__val[9][1] = tile__send_data__val[5][0]; - assign tile__recv_data__msg[4][3] = tile__send_data__msg[5][2]; - assign tile__send_data__rdy[5][2] = tile__recv_data__rdy[4][3]; - assign tile__recv_data__val[4][3] = tile__send_data__val[5][2]; - assign tile__recv_data__msg[6][2] = tile__send_data__msg[5][3]; - assign tile__send_data__rdy[5][3] = tile__recv_data__rdy[6][2]; - assign tile__recv_data__val[6][2] = tile__send_data__val[5][3]; - assign tile__to_mem_raddr__rdy[5] = 1'd0; - assign tile__from_mem_rdata__val[5] = 1'd0; - assign tile__from_mem_rdata__msg[5] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[5] = 1'd0; - assign tile__to_mem_wdata__rdy[5] = 1'd0; - assign tile__recv_data__msg[2][0] = tile__send_data__msg[6][1]; - assign tile__send_data__rdy[6][1] = tile__recv_data__rdy[2][0]; - assign tile__recv_data__val[2][0] = tile__send_data__val[6][1]; - assign tile__recv_data__msg[10][1] = tile__send_data__msg[6][0]; - assign tile__send_data__rdy[6][0] = tile__recv_data__rdy[10][1]; - assign tile__recv_data__val[10][1] = tile__send_data__val[6][0]; - assign tile__recv_data__msg[5][3] = tile__send_data__msg[6][2]; - assign tile__send_data__rdy[6][2] = tile__recv_data__rdy[5][3]; - assign tile__recv_data__val[5][3] = tile__send_data__val[6][2]; - assign tile__recv_data__msg[7][2] = tile__send_data__msg[6][3]; - assign tile__send_data__rdy[6][3] = tile__recv_data__rdy[7][2]; - assign tile__recv_data__val[7][2] = tile__send_data__val[6][3]; - assign tile__to_mem_raddr__rdy[6] = 1'd0; - assign tile__from_mem_rdata__val[6] = 1'd0; - assign tile__from_mem_rdata__msg[6] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[6] = 1'd0; - assign tile__to_mem_wdata__rdy[6] = 1'd0; - assign tile__recv_data__msg[3][0] = tile__send_data__msg[7][1]; - assign tile__send_data__rdy[7][1] = tile__recv_data__rdy[3][0]; - assign tile__recv_data__val[3][0] = tile__send_data__val[7][1]; - assign tile__recv_data__msg[11][1] = tile__send_data__msg[7][0]; - assign tile__send_data__rdy[7][0] = tile__recv_data__rdy[11][1]; - assign tile__recv_data__val[11][1] = tile__send_data__val[7][0]; - assign tile__recv_data__msg[6][3] = tile__send_data__msg[7][2]; - assign tile__send_data__rdy[7][2] = tile__recv_data__rdy[6][3]; - assign tile__recv_data__val[6][3] = tile__send_data__val[7][2]; - assign send_data_on_boundary_east__msg[1] = tile__send_data__msg[7][3]; - assign tile__send_data__rdy[7][3] = send_data_on_boundary_east__rdy[1]; - assign send_data_on_boundary_east__val[1] = tile__send_data__val[7][3]; - assign tile__recv_data__msg[7][3] = recv_data_on_boundary_east__msg[1]; - assign recv_data_on_boundary_east__rdy[1] = tile__recv_data__rdy[7][3]; - assign tile__recv_data__val[7][3] = recv_data_on_boundary_east__val[1]; - assign tile__to_mem_raddr__rdy[7] = 1'd0; - assign tile__from_mem_rdata__val[7] = 1'd0; - assign tile__from_mem_rdata__msg[7] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[7] = 1'd0; - assign tile__to_mem_wdata__rdy[7] = 1'd0; - assign tile__recv_data__msg[4][0] = tile__send_data__msg[8][1]; - assign tile__send_data__rdy[8][1] = tile__recv_data__rdy[4][0]; - assign tile__recv_data__val[4][0] = tile__send_data__val[8][1]; - assign tile__recv_data__msg[12][1] = tile__send_data__msg[8][0]; - assign tile__send_data__rdy[8][0] = tile__recv_data__rdy[12][1]; - assign tile__recv_data__val[12][1] = tile__send_data__val[8][0]; - assign tile__recv_data__msg[9][2] = tile__send_data__msg[8][3]; - assign tile__send_data__rdy[8][3] = tile__recv_data__rdy[9][2]; - assign tile__recv_data__val[9][2] = tile__send_data__val[8][3]; - assign send_data_on_boundary_west__msg[2] = tile__send_data__msg[8][2]; - assign tile__send_data__rdy[8][2] = send_data_on_boundary_west__rdy[2]; - assign send_data_on_boundary_west__val[2] = tile__send_data__val[8][2]; - assign tile__recv_data__msg[8][2] = recv_data_on_boundary_west__msg[2]; - assign recv_data_on_boundary_west__rdy[2] = tile__recv_data__rdy[8][2]; - assign tile__recv_data__val[8][2] = recv_data_on_boundary_west__val[2]; - assign data_mem__recv_raddr__msg[5] = tile__to_mem_raddr__msg[8]; - assign tile__to_mem_raddr__rdy[8] = data_mem__recv_raddr__rdy[5]; - assign data_mem__recv_raddr__val[5] = tile__to_mem_raddr__val[8]; - assign tile__from_mem_rdata__msg[8] = data_mem__send_rdata__msg[5]; - assign data_mem__send_rdata__rdy[5] = tile__from_mem_rdata__rdy[8]; - assign tile__from_mem_rdata__val[8] = data_mem__send_rdata__val[5]; - assign data_mem__recv_waddr__msg[5] = tile__to_mem_waddr__msg[8]; - assign tile__to_mem_waddr__rdy[8] = data_mem__recv_waddr__rdy[5]; - assign data_mem__recv_waddr__val[5] = tile__to_mem_waddr__val[8]; - assign data_mem__recv_wdata__msg[5] = tile__to_mem_wdata__msg[8]; - assign tile__to_mem_wdata__rdy[8] = data_mem__recv_wdata__rdy[5]; - assign data_mem__recv_wdata__val[5] = tile__to_mem_wdata__val[8]; - assign tile__recv_data__msg[5][0] = tile__send_data__msg[9][1]; - assign tile__send_data__rdy[9][1] = tile__recv_data__rdy[5][0]; - assign tile__recv_data__val[5][0] = tile__send_data__val[9][1]; - assign tile__recv_data__msg[13][1] = tile__send_data__msg[9][0]; - assign tile__send_data__rdy[9][0] = tile__recv_data__rdy[13][1]; - assign tile__recv_data__val[13][1] = tile__send_data__val[9][0]; - assign tile__recv_data__msg[8][3] = tile__send_data__msg[9][2]; - assign tile__send_data__rdy[9][2] = tile__recv_data__rdy[8][3]; - assign tile__recv_data__val[8][3] = tile__send_data__val[9][2]; - assign tile__recv_data__msg[10][2] = tile__send_data__msg[9][3]; - assign tile__send_data__rdy[9][3] = tile__recv_data__rdy[10][2]; - assign tile__recv_data__val[10][2] = tile__send_data__val[9][3]; - assign tile__to_mem_raddr__rdy[9] = 1'd0; - assign tile__from_mem_rdata__val[9] = 1'd0; - assign tile__from_mem_rdata__msg[9] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[9] = 1'd0; - assign tile__to_mem_wdata__rdy[9] = 1'd0; - assign tile__recv_data__msg[6][0] = tile__send_data__msg[10][1]; - assign tile__send_data__rdy[10][1] = tile__recv_data__rdy[6][0]; - assign tile__recv_data__val[6][0] = tile__send_data__val[10][1]; - assign tile__recv_data__msg[14][1] = tile__send_data__msg[10][0]; - assign tile__send_data__rdy[10][0] = tile__recv_data__rdy[14][1]; - assign tile__recv_data__val[14][1] = tile__send_data__val[10][0]; - assign tile__recv_data__msg[9][3] = tile__send_data__msg[10][2]; - assign tile__send_data__rdy[10][2] = tile__recv_data__rdy[9][3]; - assign tile__recv_data__val[9][3] = tile__send_data__val[10][2]; - assign tile__recv_data__msg[11][2] = tile__send_data__msg[10][3]; - assign tile__send_data__rdy[10][3] = tile__recv_data__rdy[11][2]; - assign tile__recv_data__val[11][2] = tile__send_data__val[10][3]; - assign tile__to_mem_raddr__rdy[10] = 1'd0; - assign tile__from_mem_rdata__val[10] = 1'd0; - assign tile__from_mem_rdata__msg[10] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[10] = 1'd0; - assign tile__to_mem_wdata__rdy[10] = 1'd0; - assign tile__recv_data__msg[7][0] = tile__send_data__msg[11][1]; - assign tile__send_data__rdy[11][1] = tile__recv_data__rdy[7][0]; - assign tile__recv_data__val[7][0] = tile__send_data__val[11][1]; - assign tile__recv_data__msg[15][1] = tile__send_data__msg[11][0]; - assign tile__send_data__rdy[11][0] = tile__recv_data__rdy[15][1]; - assign tile__recv_data__val[15][1] = tile__send_data__val[11][0]; - assign tile__recv_data__msg[10][3] = tile__send_data__msg[11][2]; - assign tile__send_data__rdy[11][2] = tile__recv_data__rdy[10][3]; - assign tile__recv_data__val[10][3] = tile__send_data__val[11][2]; - assign send_data_on_boundary_east__msg[2] = tile__send_data__msg[11][3]; - assign tile__send_data__rdy[11][3] = send_data_on_boundary_east__rdy[2]; - assign send_data_on_boundary_east__val[2] = tile__send_data__val[11][3]; - assign tile__recv_data__msg[11][3] = recv_data_on_boundary_east__msg[2]; - assign recv_data_on_boundary_east__rdy[2] = tile__recv_data__rdy[11][3]; - assign tile__recv_data__val[11][3] = recv_data_on_boundary_east__val[2]; - assign tile__to_mem_raddr__rdy[11] = 1'd0; - assign tile__from_mem_rdata__val[11] = 1'd0; - assign tile__from_mem_rdata__msg[11] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[11] = 1'd0; - assign tile__to_mem_wdata__rdy[11] = 1'd0; - assign tile__recv_data__msg[8][0] = tile__send_data__msg[12][1]; - assign tile__send_data__rdy[12][1] = tile__recv_data__rdy[8][0]; - assign tile__recv_data__val[8][0] = tile__send_data__val[12][1]; - assign tile__recv_data__msg[13][2] = tile__send_data__msg[12][3]; - assign tile__send_data__rdy[12][3] = tile__recv_data__rdy[13][2]; - assign tile__recv_data__val[13][2] = tile__send_data__val[12][3]; - assign send_data_on_boundary_north__msg[0] = tile__send_data__msg[12][0]; - assign tile__send_data__rdy[12][0] = send_data_on_boundary_north__rdy[0]; - assign send_data_on_boundary_north__val[0] = tile__send_data__val[12][0]; - assign tile__recv_data__msg[12][0] = recv_data_on_boundary_north__msg[0]; - assign recv_data_on_boundary_north__rdy[0] = tile__recv_data__rdy[12][0]; - assign tile__recv_data__val[12][0] = recv_data_on_boundary_north__val[0]; - assign send_data_on_boundary_west__msg[3] = tile__send_data__msg[12][2]; - assign tile__send_data__rdy[12][2] = send_data_on_boundary_west__rdy[3]; - assign send_data_on_boundary_west__val[3] = tile__send_data__val[12][2]; - assign tile__recv_data__msg[12][2] = recv_data_on_boundary_west__msg[3]; - assign recv_data_on_boundary_west__rdy[3] = tile__recv_data__rdy[12][2]; - assign tile__recv_data__val[12][2] = recv_data_on_boundary_west__val[3]; - assign data_mem__recv_raddr__msg[6] = tile__to_mem_raddr__msg[12]; - assign tile__to_mem_raddr__rdy[12] = data_mem__recv_raddr__rdy[6]; - assign data_mem__recv_raddr__val[6] = tile__to_mem_raddr__val[12]; - assign tile__from_mem_rdata__msg[12] = data_mem__send_rdata__msg[6]; - assign data_mem__send_rdata__rdy[6] = tile__from_mem_rdata__rdy[12]; - assign tile__from_mem_rdata__val[12] = data_mem__send_rdata__val[6]; - assign data_mem__recv_waddr__msg[6] = tile__to_mem_waddr__msg[12]; - assign tile__to_mem_waddr__rdy[12] = data_mem__recv_waddr__rdy[6]; - assign data_mem__recv_waddr__val[6] = tile__to_mem_waddr__val[12]; - assign data_mem__recv_wdata__msg[6] = tile__to_mem_wdata__msg[12]; - assign tile__to_mem_wdata__rdy[12] = data_mem__recv_wdata__rdy[6]; - assign data_mem__recv_wdata__val[6] = tile__to_mem_wdata__val[12]; - assign tile__recv_data__msg[9][0] = tile__send_data__msg[13][1]; - assign tile__send_data__rdy[13][1] = tile__recv_data__rdy[9][0]; - assign tile__recv_data__val[9][0] = tile__send_data__val[13][1]; - assign tile__recv_data__msg[12][3] = tile__send_data__msg[13][2]; - assign tile__send_data__rdy[13][2] = tile__recv_data__rdy[12][3]; - assign tile__recv_data__val[12][3] = tile__send_data__val[13][2]; - assign tile__recv_data__msg[14][2] = tile__send_data__msg[13][3]; - assign tile__send_data__rdy[13][3] = tile__recv_data__rdy[14][2]; - assign tile__recv_data__val[14][2] = tile__send_data__val[13][3]; - assign send_data_on_boundary_north__msg[1] = tile__send_data__msg[13][0]; - assign tile__send_data__rdy[13][0] = send_data_on_boundary_north__rdy[1]; - assign send_data_on_boundary_north__val[1] = tile__send_data__val[13][0]; - assign tile__recv_data__msg[13][0] = recv_data_on_boundary_north__msg[1]; - assign recv_data_on_boundary_north__rdy[1] = tile__recv_data__rdy[13][0]; - assign tile__recv_data__val[13][0] = recv_data_on_boundary_north__val[1]; - assign tile__to_mem_raddr__rdy[13] = 1'd0; - assign tile__from_mem_rdata__val[13] = 1'd0; - assign tile__from_mem_rdata__msg[13] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[13] = 1'd0; - assign tile__to_mem_wdata__rdy[13] = 1'd0; - assign tile__recv_data__msg[10][0] = tile__send_data__msg[14][1]; - assign tile__send_data__rdy[14][1] = tile__recv_data__rdy[10][0]; - assign tile__recv_data__val[10][0] = tile__send_data__val[14][1]; - assign tile__recv_data__msg[13][3] = tile__send_data__msg[14][2]; - assign tile__send_data__rdy[14][2] = tile__recv_data__rdy[13][3]; - assign tile__recv_data__val[13][3] = tile__send_data__val[14][2]; - assign tile__recv_data__msg[15][2] = tile__send_data__msg[14][3]; - assign tile__send_data__rdy[14][3] = tile__recv_data__rdy[15][2]; - assign tile__recv_data__val[15][2] = tile__send_data__val[14][3]; - assign send_data_on_boundary_north__msg[2] = tile__send_data__msg[14][0]; - assign tile__send_data__rdy[14][0] = send_data_on_boundary_north__rdy[2]; - assign send_data_on_boundary_north__val[2] = tile__send_data__val[14][0]; - assign tile__recv_data__msg[14][0] = recv_data_on_boundary_north__msg[2]; - assign recv_data_on_boundary_north__rdy[2] = tile__recv_data__rdy[14][0]; - assign tile__recv_data__val[14][0] = recv_data_on_boundary_north__val[2]; - assign tile__to_mem_raddr__rdy[14] = 1'd0; - assign tile__from_mem_rdata__val[14] = 1'd0; - assign tile__from_mem_rdata__msg[14] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[14] = 1'd0; - assign tile__to_mem_wdata__rdy[14] = 1'd0; - assign tile__recv_data__msg[11][0] = tile__send_data__msg[15][1]; - assign tile__send_data__rdy[15][1] = tile__recv_data__rdy[11][0]; - assign tile__recv_data__val[11][0] = tile__send_data__val[15][1]; - assign tile__recv_data__msg[14][3] = tile__send_data__msg[15][2]; - assign tile__send_data__rdy[15][2] = tile__recv_data__rdy[14][3]; - assign tile__recv_data__val[14][3] = tile__send_data__val[15][2]; - assign send_data_on_boundary_north__msg[3] = tile__send_data__msg[15][0]; - assign tile__send_data__rdy[15][0] = send_data_on_boundary_north__rdy[3]; - assign send_data_on_boundary_north__val[3] = tile__send_data__val[15][0]; - assign tile__recv_data__msg[15][0] = recv_data_on_boundary_north__msg[3]; - assign recv_data_on_boundary_north__rdy[3] = tile__recv_data__rdy[15][0]; - assign tile__recv_data__val[15][0] = recv_data_on_boundary_north__val[3]; - assign send_data_on_boundary_east__msg[3] = tile__send_data__msg[15][3]; - assign tile__send_data__rdy[15][3] = send_data_on_boundary_east__rdy[3]; - assign send_data_on_boundary_east__val[3] = tile__send_data__val[15][3]; - assign tile__recv_data__msg[15][3] = recv_data_on_boundary_east__msg[3]; - assign recv_data_on_boundary_east__rdy[3] = tile__recv_data__rdy[15][3]; - assign tile__recv_data__val[15][3] = recv_data_on_boundary_east__val[3]; - assign tile__to_mem_raddr__rdy[15] = 1'd0; - assign tile__from_mem_rdata__val[15] = 1'd0; - assign tile__from_mem_rdata__msg[15] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign tile__to_mem_waddr__rdy[15] = 1'd0; - assign tile__to_mem_wdata__rdy[15] = 1'd0; - -endmodule - - -// PyMTL Component InputUnitRTL Definition -// Full name: InputUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_NormalQueueRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/InputUnitRTL.py - -module InputUnitRTL__8ea2cb5fb7536c6c -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - //------------------------------------------------------------- - // Component queue - //------------------------------------------------------------- - - logic [0:0] queue__clk; - logic [1:0] queue__count; - logic [0:0] queue__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__recv__msg; - logic [0:0] queue__recv__rdy; - logic [0:0] queue__recv__val; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d queue__send__msg; - logic [0:0] queue__send__rdy; - logic [0:0] queue__send__val; - - NormalQueueRTL__c7280ffb0786127e queue - ( - .clk( queue__clk ), - .count( queue__count ), - .reset( queue__reset ), - .recv__msg( queue__recv__msg ), - .recv__rdy( queue__recv__rdy ), - .recv__val( queue__recv__val ), - .send__msg( queue__send__msg ), - .send__rdy( queue__send__rdy ), - .send__val( queue__send__val ) - ); - - //------------------------------------------------------------- - // End of component queue - //------------------------------------------------------------- - - assign queue__clk = clk; - assign queue__reset = reset; - assign queue__recv__msg = recv__msg; - assign recv__rdy = queue__recv__rdy; - assign queue__recv__val = recv__val; - assign send__msg = queue__send__msg; - assign queue__send__rdy = send__rdy; - assign send__val = queue__send__val; - -endmodule - - -// PyMTL Component OutputUnitRTL Definition -// Full name: OutputUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__QueueType_None -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/OutputUnitRTL.py - -module OutputUnitRTL__e43ef936c3b236b0 -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - - assign send__msg = recv__msg; - assign recv__rdy = send__rdy; - assign send__val = recv__val; - -endmodule - - -// PyMTL Component DORYMeshRouteUnitRTL Definition -// Full name: DORYMeshRouteUnitRTL__MsgType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__num_outports_5 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py - -module DORYMeshRouteUnitRTL__cf2d804ed36fdf23 -( - input logic [0:0] clk , - input MeshPosition_2x2__pos_x_1__pos_y_1 pos , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg , - output logic [0:0] recv__rdy , - input logic [0:0] recv__val , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:4] , - input logic [0:0] send__rdy [0:4] , - output logic [0:0] send__val [0:4] -); - localparam logic [2:0] __const__num_outports_at_up_ru_routing = 3'd5; - localparam logic [2:0] __const__SELF = 3'd4; - localparam logic [0:0] __const__SOUTH = 1'd1; - localparam logic [0:0] __const__NORTH = 1'd0; - localparam logic [1:0] __const__WEST = 2'd2; - localparam logic [1:0] __const__EAST = 2'd3; - logic [2:0] out_dir; - logic [4:0] send_rdy; - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py:57 - // @update - // def up_ru_recv_rdy(): - // s.recv.rdy @= s.send_rdy[ s.out_dir ] - - always_comb begin : up_ru_recv_rdy - recv__rdy = send_rdy[out_dir]; - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/DORYMeshRouteUnitRTL.py:38 - // @update - // def up_ru_routing(): - // s.out_dir @= Bits3(0) - // for i in range( num_outports ): - // s.send[i].val @= Bits1(0) - // - // if s.recv.val: - // if (s.pos.pos_x == s.recv.msg.dst_x) & (s.pos.pos_y == s.recv.msg.dst_y): - // s.out_dir @= SELF - // elif s.recv.msg.dst_y < s.pos.pos_y: - // s.out_dir @= SOUTH - // elif s.recv.msg.dst_y > s.pos.pos_y: - // s.out_dir @= NORTH - // elif s.recv.msg.dst_x < s.pos.pos_x: - // s.out_dir @= WEST - // else: - // s.out_dir @= EAST - // s.send[ s.out_dir ].val @= Bits1(1) - - always_comb begin : up_ru_routing - out_dir = 3'd0; - for ( int unsigned i = 1'd0; i < 3'( __const__num_outports_at_up_ru_routing ); i += 1'd1 ) - send__val[3'(i)] = 1'd0; - if ( recv__val ) begin - if ( ( pos.pos_x == recv__msg.dst_x ) & ( pos.pos_y == recv__msg.dst_y ) ) begin - out_dir = 3'( __const__SELF ); - end - else if ( recv__msg.dst_y < pos.pos_y ) begin - out_dir = 3'( __const__SOUTH ); - end - else if ( recv__msg.dst_y > pos.pos_y ) begin - out_dir = 3'( __const__NORTH ); - end - else if ( recv__msg.dst_x < pos.pos_x ) begin - out_dir = 3'( __const__WEST ); - end - else - out_dir = 3'( __const__EAST ); - send__val[out_dir] = 1'd1; - end - end - - assign send__msg[0] = recv__msg; - assign send_rdy[0:0] = send__rdy[0]; - assign send__msg[1] = recv__msg; - assign send_rdy[1:1] = send__rdy[1]; - assign send__msg[2] = recv__msg; - assign send_rdy[2:2] = send__rdy[2]; - assign send__msg[3] = recv__msg; - assign send_rdy[3:3] = send__rdy[3]; - assign send__msg[4] = recv__msg; - assign send_rdy[4:4] = send__rdy[4]; - -endmodule - - -// PyMTL Component RegEnRst Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py - -module RegEnRst__Type_Bits5__reset_value_1 -( - input logic [0:0] clk , - input logic [0:0] en , - input logic [4:0] in_ , - output logic [4:0] out , - input logic [0:0] reset -); - localparam logic [0:0] __const__reset_value_at_up_regenrst = 1'd1; - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/registers.py:55 - // @update_ff - // def up_regenrst(): - // if s.reset: s.out <<= reset_value - // elif s.en: s.out <<= s.in_ - - always_ff @(posedge clk) begin : up_regenrst - if ( reset ) begin - out <= 5'( __const__reset_value_at_up_regenrst ); - end - else if ( en ) begin - out <= in_; - end - end - -endmodule - - -// PyMTL Component RoundRobinArbiterEn Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py - -module RoundRobinArbiterEn__nreqs_5 -( - input logic [0:0] clk , - input logic [0:0] en , - output logic [4:0] grants , - input logic [4:0] reqs , - input logic [0:0] reset -); - localparam logic [2:0] __const__nreqs_at_comb_reqs_int = 3'd5; - localparam logic [3:0] __const__nreqsX2_at_comb_reqs_int = 4'd10; - localparam logic [2:0] __const__nreqs_at_comb_grants = 3'd5; - localparam logic [2:0] __const__nreqs_at_comb_priority_int = 3'd5; - localparam logic [3:0] __const__nreqsX2_at_comb_priority_int = 4'd10; - localparam logic [3:0] __const__nreqsX2_at_comb_kills = 4'd10; - localparam logic [3:0] __const__nreqsX2_at_comb_grants_int = 4'd10; - logic [9:0] grants_int; - logic [10:0] kills; - logic [0:0] priority_en; - logic [9:0] priority_int; - logic [9:0] reqs_int; - //------------------------------------------------------------- - // Component priority_reg - //------------------------------------------------------------- - - logic [0:0] priority_reg__clk; - logic [0:0] priority_reg__en; - logic [4:0] priority_reg__in_; - logic [4:0] priority_reg__out; - logic [0:0] priority_reg__reset; - - RegEnRst__Type_Bits5__reset_value_1 priority_reg - ( - .clk( priority_reg__clk ), - .en( priority_reg__en ), - .in_( priority_reg__in_ ), - .out( priority_reg__out ), - .reset( priority_reg__reset ) - ); - - //------------------------------------------------------------- - // End of component priority_reg - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:118 - // @update - // def comb_grants(): - // for i in range( nreqs ): - // s.grants[i] @= s.grants_int[i] | s.grants_int[nreqs+i] - - always_comb begin : comb_grants - for ( int unsigned i = 1'd0; i < 3'( __const__nreqs_at_comb_grants ); i += 1'd1 ) - grants[3'(i)] = grants_int[4'(i)] | grants_int[4'( __const__nreqs_at_comb_grants ) + 4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:141 - // @update - // def comb_grants_int(): - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.grants_int[i] @= s.reqs_int[i] - // else: - // s.grants_int[i] @= ~s.kills[i] & s.reqs_int[i] - - always_comb begin : comb_grants_int - for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_grants_int ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - grants_int[4'(i)] = reqs_int[4'(i)]; - end - else - grants_int[4'(i)] = ( ~kills[4'(i)] ) & reqs_int[4'(i)]; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:132 - // @update - // def comb_kills(): - // s.kills[0] @= 1 - // for i in range( nreqsX2 ): - // if s.priority_int[i]: - // s.kills[i+1] @= s.reqs_int[i] - // else: - // s.kills[i+1] @= s.kills[i] | ( ~s.kills[i] & s.reqs_int[i] ) - - always_comb begin : comb_kills - kills[4'd0] = 1'd1; - for ( int unsigned i = 1'd0; i < 4'( __const__nreqsX2_at_comb_kills ); i += 1'd1 ) - if ( priority_int[4'(i)] ) begin - kills[4'(i) + 4'd1] = reqs_int[4'(i)]; - end - else - kills[4'(i) + 4'd1] = kills[4'(i)] | ( ( ~kills[4'(i)] ) & reqs_int[4'(i)] ); - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:123 - // @update - // def comb_priority_en(): - // s.priority_en @= ( s.grants != 0 ) & s.en - - always_comb begin : comb_priority_en - priority_en = ( grants != 5'd0 ) & en; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:127 - // @update - // def comb_priority_int(): - // s.priority_int[ 0:nreqs ] @= s.priority_reg.out - // s.priority_int[nreqs:nreqsX2] @= 0 - - always_comb begin : comb_priority_int - priority_int[4'd4:4'd0] = priority_reg__out; - priority_int[4'd9:4'( __const__nreqs_at_comb_priority_int )] = 5'd0; - end - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arbiters.py:113 - // @update - // def comb_reqs_int(): - // s.reqs_int [ 0:nreqs ] @= s.reqs - // s.reqs_int [nreqs:nreqsX2] @= s.reqs - - always_comb begin : comb_reqs_int - reqs_int[4'd4:4'd0] = reqs; - reqs_int[4'd9:4'( __const__nreqs_at_comb_reqs_int )] = reqs; - end - - assign priority_reg__clk = clk; - assign priority_reg__reset = reset; - assign priority_reg__en = priority_en; - assign priority_reg__in_[4:1] = grants[3:0]; - assign priority_reg__in_[0:0] = grants[4:4]; - -endmodule - - -// PyMTL Component Encoder Definition -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py - -module Encoder__in_nbits_5__out_nbits_3 -( - input logic [0:0] clk , - input logic [4:0] in_ , - output logic [2:0] out , - input logic [0:0] reset -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/encoders.py:28 - // @update - // def encode(): - // s.out @= 0 - // for i in range( s.in_nbits ): - // if s.in_[i]: - // s.out @= i - - always_comb begin : encode - out = 3'd0; - for ( int unsigned i = 1'd0; i < 3'd5; i += 1'd1 ) - if ( in_[3'(i)] ) begin - out = 3'(i); - end - end - -endmodule - - -// PyMTL Component Mux Definition -// Full name: Mux__Type_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__ninputs_5 -// At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py - -module Mux__5c29509c868f9669 -( - input logic [0:0] clk , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d in_ [0:4], - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d out , - input logic [0:0] reset , - input logic [2:0] sel -); - - // PyMTL Update Block Source - // At /home/ajokai/venv/lib/python3.10/site-packages/pymtl3/stdlib/primitive/arithmetics.py:13 - // @update - // def up_mux(): - // s.out @= s.in_[ s.sel ] - - always_comb begin : up_mux - out = in_[sel]; - end - -endmodule - - -// PyMTL Component SwitchUnitRTL Definition -// Full name: SwitchUnitRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__num_inports_5 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py - -module SwitchUnitRTL__1ccc072d8fcd170f -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:4] , - output logic [0:0] recv__rdy [0:4] , - input logic [0:0] recv__val [0:4] , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg , - input logic [0:0] send__rdy , - output logic [0:0] send__val -); - localparam logic [2:0] __const__num_inports_at_up_get_en = 3'd5; - //------------------------------------------------------------- - // Component arbiter - //------------------------------------------------------------- - - logic [0:0] arbiter__clk; - logic [0:0] arbiter__en; - logic [4:0] arbiter__grants; - logic [4:0] arbiter__reqs; - logic [0:0] arbiter__reset; - - RoundRobinArbiterEn__nreqs_5 arbiter - ( - .clk( arbiter__clk ), - .en( arbiter__en ), - .grants( arbiter__grants ), - .reqs( arbiter__reqs ), - .reset( arbiter__reset ) - ); - - //------------------------------------------------------------- - // End of component arbiter - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component encoder - //------------------------------------------------------------- - - logic [0:0] encoder__clk; - logic [4:0] encoder__in_; - logic [2:0] encoder__out; - logic [0:0] encoder__reset; - - Encoder__in_nbits_5__out_nbits_3 encoder - ( - .clk( encoder__clk ), - .in_( encoder__in_ ), - .out( encoder__out ), - .reset( encoder__reset ) - ); - - //------------------------------------------------------------- - // End of component encoder - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mux - //------------------------------------------------------------- - - logic [0:0] mux__clk; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mux__in_ [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mux__out; - logic [0:0] mux__reset; - logic [2:0] mux__sel; - - Mux__5c29509c868f9669 mux - ( - .clk( mux__clk ), - .in_( mux__in_ ), - .out( mux__out ), - .reset( mux__reset ), - .sel( mux__sel ) - ); - - //------------------------------------------------------------- - // End of component mux - //------------------------------------------------------------- - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:56 - // @update - // def up_get_en(): - // for i in range( num_inports ): - // s.recv[i].rdy @= s.send.rdy & ( s.mux.sel == i ) - - always_comb begin : up_get_en - for ( int unsigned i = 1'd0; i < 3'( __const__num_inports_at_up_get_en ); i += 1'd1 ) - recv__rdy[3'(i)] = send__rdy & ( mux__sel == 3'(i) ); - end - - // PyMTL Update Block Source - // At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/router/SwitchUnitRTL.py:51 - // @update - // def up_send_val(): - // s.send.val @= s.arbiter.grants > 0 - - always_comb begin : up_send_val - send__val = arbiter__grants > 5'd0; - end - - assign arbiter__clk = clk; - assign arbiter__reset = reset; - assign arbiter__en = 1'd1; - assign mux__clk = clk; - assign mux__reset = reset; - assign send__msg = mux__out; - assign encoder__clk = clk; - assign encoder__reset = reset; - assign encoder__in_ = arbiter__grants; - assign mux__sel = encoder__out; - assign arbiter__reqs[0:0] = recv__val[0]; - assign mux__in_[0] = recv__msg[0]; - assign arbiter__reqs[1:1] = recv__val[1]; - assign mux__in_[1] = recv__msg[1]; - assign arbiter__reqs[2:2] = recv__val[2]; - assign mux__in_[2] = recv__msg[2]; - assign arbiter__reqs[3:3] = recv__val[3]; - assign mux__in_[3] = recv__msg[3]; - assign arbiter__reqs[4:4] = recv__val[4]; - assign mux__in_[4] = recv__msg[4]; - -endmodule - - -// PyMTL Component MeshRouterRTL Definition -// Full name: MeshRouterRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__InputUnitType_InputUnitRTL__RouteUnitType_DORYMeshRouteUnitRTL__SwitchUnitType_SwitchUnitRTL -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/MeshRouterRTL.py - -module MeshRouterRTL__574f02d875fdbb92 -( - input logic [0:0] clk , - input MeshPosition_2x2__pos_x_1__pos_y_1 pos , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:4] , - output logic [0:0] recv__rdy [0:4] , - input logic [0:0] recv__val [0:4] , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:4] , - input logic [0:0] send__rdy [0:4] , - output logic [0:0] send__val [0:4] -); - //------------------------------------------------------------- - // Component input_units[0:4] - //------------------------------------------------------------- - - logic [0:0] input_units__clk [0:4]; - logic [0:0] input_units__reset [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d input_units__recv__msg [0:4]; - logic [0:0] input_units__recv__rdy [0:4]; - logic [0:0] input_units__recv__val [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d input_units__send__msg [0:4]; - logic [0:0] input_units__send__rdy [0:4]; - logic [0:0] input_units__send__val [0:4]; - - InputUnitRTL__8ea2cb5fb7536c6c input_units__0 - ( - .clk( input_units__clk[0] ), - .reset( input_units__reset[0] ), - .recv__msg( input_units__recv__msg[0] ), - .recv__rdy( input_units__recv__rdy[0] ), - .recv__val( input_units__recv__val[0] ), - .send__msg( input_units__send__msg[0] ), - .send__rdy( input_units__send__rdy[0] ), - .send__val( input_units__send__val[0] ) - ); - - InputUnitRTL__8ea2cb5fb7536c6c input_units__1 - ( - .clk( input_units__clk[1] ), - .reset( input_units__reset[1] ), - .recv__msg( input_units__recv__msg[1] ), - .recv__rdy( input_units__recv__rdy[1] ), - .recv__val( input_units__recv__val[1] ), - .send__msg( input_units__send__msg[1] ), - .send__rdy( input_units__send__rdy[1] ), - .send__val( input_units__send__val[1] ) - ); - - InputUnitRTL__8ea2cb5fb7536c6c input_units__2 - ( - .clk( input_units__clk[2] ), - .reset( input_units__reset[2] ), - .recv__msg( input_units__recv__msg[2] ), - .recv__rdy( input_units__recv__rdy[2] ), - .recv__val( input_units__recv__val[2] ), - .send__msg( input_units__send__msg[2] ), - .send__rdy( input_units__send__rdy[2] ), - .send__val( input_units__send__val[2] ) - ); - - InputUnitRTL__8ea2cb5fb7536c6c input_units__3 - ( - .clk( input_units__clk[3] ), - .reset( input_units__reset[3] ), - .recv__msg( input_units__recv__msg[3] ), - .recv__rdy( input_units__recv__rdy[3] ), - .recv__val( input_units__recv__val[3] ), - .send__msg( input_units__send__msg[3] ), - .send__rdy( input_units__send__rdy[3] ), - .send__val( input_units__send__val[3] ) - ); - - InputUnitRTL__8ea2cb5fb7536c6c input_units__4 - ( - .clk( input_units__clk[4] ), - .reset( input_units__reset[4] ), - .recv__msg( input_units__recv__msg[4] ), - .recv__rdy( input_units__recv__rdy[4] ), - .recv__val( input_units__recv__val[4] ), - .send__msg( input_units__send__msg[4] ), - .send__rdy( input_units__send__rdy[4] ), - .send__val( input_units__send__val[4] ) - ); - - //------------------------------------------------------------- - // End of component input_units[0:4] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component output_units[0:4] - //------------------------------------------------------------- - - logic [0:0] output_units__clk [0:4]; - logic [0:0] output_units__reset [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d output_units__recv__msg [0:4]; - logic [0:0] output_units__recv__rdy [0:4]; - logic [0:0] output_units__recv__val [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d output_units__send__msg [0:4]; - logic [0:0] output_units__send__rdy [0:4]; - logic [0:0] output_units__send__val [0:4]; - - OutputUnitRTL__e43ef936c3b236b0 output_units__0 - ( - .clk( output_units__clk[0] ), - .reset( output_units__reset[0] ), - .recv__msg( output_units__recv__msg[0] ), - .recv__rdy( output_units__recv__rdy[0] ), - .recv__val( output_units__recv__val[0] ), - .send__msg( output_units__send__msg[0] ), - .send__rdy( output_units__send__rdy[0] ), - .send__val( output_units__send__val[0] ) - ); - - OutputUnitRTL__e43ef936c3b236b0 output_units__1 - ( - .clk( output_units__clk[1] ), - .reset( output_units__reset[1] ), - .recv__msg( output_units__recv__msg[1] ), - .recv__rdy( output_units__recv__rdy[1] ), - .recv__val( output_units__recv__val[1] ), - .send__msg( output_units__send__msg[1] ), - .send__rdy( output_units__send__rdy[1] ), - .send__val( output_units__send__val[1] ) - ); - - OutputUnitRTL__e43ef936c3b236b0 output_units__2 - ( - .clk( output_units__clk[2] ), - .reset( output_units__reset[2] ), - .recv__msg( output_units__recv__msg[2] ), - .recv__rdy( output_units__recv__rdy[2] ), - .recv__val( output_units__recv__val[2] ), - .send__msg( output_units__send__msg[2] ), - .send__rdy( output_units__send__rdy[2] ), - .send__val( output_units__send__val[2] ) - ); - - OutputUnitRTL__e43ef936c3b236b0 output_units__3 - ( - .clk( output_units__clk[3] ), - .reset( output_units__reset[3] ), - .recv__msg( output_units__recv__msg[3] ), - .recv__rdy( output_units__recv__rdy[3] ), - .recv__val( output_units__recv__val[3] ), - .send__msg( output_units__send__msg[3] ), - .send__rdy( output_units__send__rdy[3] ), - .send__val( output_units__send__val[3] ) - ); - - OutputUnitRTL__e43ef936c3b236b0 output_units__4 - ( - .clk( output_units__clk[4] ), - .reset( output_units__reset[4] ), - .recv__msg( output_units__recv__msg[4] ), - .recv__rdy( output_units__recv__rdy[4] ), - .recv__val( output_units__recv__val[4] ), - .send__msg( output_units__send__msg[4] ), - .send__rdy( output_units__send__rdy[4] ), - .send__val( output_units__send__val[4] ) - ); - - //------------------------------------------------------------- - // End of component output_units[0:4] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component route_units[0:4] - //------------------------------------------------------------- - - logic [0:0] route_units__clk [0:4]; - MeshPosition_2x2__pos_x_1__pos_y_1 route_units__pos [0:4]; - logic [0:0] route_units__reset [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d route_units__recv__msg [0:4]; - logic [0:0] route_units__recv__rdy [0:4]; - logic [0:0] route_units__recv__val [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d route_units__send__msg [0:4][0:4]; - logic [0:0] route_units__send__rdy [0:4][0:4]; - logic [0:0] route_units__send__val [0:4][0:4]; - - DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__0 - ( - .clk( route_units__clk[0] ), - .pos( route_units__pos[0] ), - .reset( route_units__reset[0] ), - .recv__msg( route_units__recv__msg[0] ), - .recv__rdy( route_units__recv__rdy[0] ), - .recv__val( route_units__recv__val[0] ), - .send__msg( route_units__send__msg[0] ), - .send__rdy( route_units__send__rdy[0] ), - .send__val( route_units__send__val[0] ) - ); - - DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__1 - ( - .clk( route_units__clk[1] ), - .pos( route_units__pos[1] ), - .reset( route_units__reset[1] ), - .recv__msg( route_units__recv__msg[1] ), - .recv__rdy( route_units__recv__rdy[1] ), - .recv__val( route_units__recv__val[1] ), - .send__msg( route_units__send__msg[1] ), - .send__rdy( route_units__send__rdy[1] ), - .send__val( route_units__send__val[1] ) - ); - - DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__2 - ( - .clk( route_units__clk[2] ), - .pos( route_units__pos[2] ), - .reset( route_units__reset[2] ), - .recv__msg( route_units__recv__msg[2] ), - .recv__rdy( route_units__recv__rdy[2] ), - .recv__val( route_units__recv__val[2] ), - .send__msg( route_units__send__msg[2] ), - .send__rdy( route_units__send__rdy[2] ), - .send__val( route_units__send__val[2] ) - ); - - DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__3 - ( - .clk( route_units__clk[3] ), - .pos( route_units__pos[3] ), - .reset( route_units__reset[3] ), - .recv__msg( route_units__recv__msg[3] ), - .recv__rdy( route_units__recv__rdy[3] ), - .recv__val( route_units__recv__val[3] ), - .send__msg( route_units__send__msg[3] ), - .send__rdy( route_units__send__rdy[3] ), - .send__val( route_units__send__val[3] ) - ); - - DORYMeshRouteUnitRTL__cf2d804ed36fdf23 route_units__4 - ( - .clk( route_units__clk[4] ), - .pos( route_units__pos[4] ), - .reset( route_units__reset[4] ), - .recv__msg( route_units__recv__msg[4] ), - .recv__rdy( route_units__recv__rdy[4] ), - .recv__val( route_units__recv__val[4] ), - .send__msg( route_units__send__msg[4] ), - .send__rdy( route_units__send__rdy[4] ), - .send__val( route_units__send__val[4] ) - ); - - //------------------------------------------------------------- - // End of component route_units[0:4] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component switch_units[0:4] - //------------------------------------------------------------- - - logic [0:0] switch_units__clk [0:4]; - logic [0:0] switch_units__reset [0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d switch_units__recv__msg [0:4][0:4]; - logic [0:0] switch_units__recv__rdy [0:4][0:4]; - logic [0:0] switch_units__recv__val [0:4][0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d switch_units__send__msg [0:4]; - logic [0:0] switch_units__send__rdy [0:4]; - logic [0:0] switch_units__send__val [0:4]; - - SwitchUnitRTL__1ccc072d8fcd170f switch_units__0 - ( - .clk( switch_units__clk[0] ), - .reset( switch_units__reset[0] ), - .recv__msg( switch_units__recv__msg[0] ), - .recv__rdy( switch_units__recv__rdy[0] ), - .recv__val( switch_units__recv__val[0] ), - .send__msg( switch_units__send__msg[0] ), - .send__rdy( switch_units__send__rdy[0] ), - .send__val( switch_units__send__val[0] ) - ); - - SwitchUnitRTL__1ccc072d8fcd170f switch_units__1 - ( - .clk( switch_units__clk[1] ), - .reset( switch_units__reset[1] ), - .recv__msg( switch_units__recv__msg[1] ), - .recv__rdy( switch_units__recv__rdy[1] ), - .recv__val( switch_units__recv__val[1] ), - .send__msg( switch_units__send__msg[1] ), - .send__rdy( switch_units__send__rdy[1] ), - .send__val( switch_units__send__val[1] ) - ); - - SwitchUnitRTL__1ccc072d8fcd170f switch_units__2 - ( - .clk( switch_units__clk[2] ), - .reset( switch_units__reset[2] ), - .recv__msg( switch_units__recv__msg[2] ), - .recv__rdy( switch_units__recv__rdy[2] ), - .recv__val( switch_units__recv__val[2] ), - .send__msg( switch_units__send__msg[2] ), - .send__rdy( switch_units__send__rdy[2] ), - .send__val( switch_units__send__val[2] ) - ); - - SwitchUnitRTL__1ccc072d8fcd170f switch_units__3 - ( - .clk( switch_units__clk[3] ), - .reset( switch_units__reset[3] ), - .recv__msg( switch_units__recv__msg[3] ), - .recv__rdy( switch_units__recv__rdy[3] ), - .recv__val( switch_units__recv__val[3] ), - .send__msg( switch_units__send__msg[3] ), - .send__rdy( switch_units__send__rdy[3] ), - .send__val( switch_units__send__val[3] ) - ); - - SwitchUnitRTL__1ccc072d8fcd170f switch_units__4 - ( - .clk( switch_units__clk[4] ), - .reset( switch_units__reset[4] ), - .recv__msg( switch_units__recv__msg[4] ), - .recv__rdy( switch_units__recv__rdy[4] ), - .recv__val( switch_units__recv__val[4] ), - .send__msg( switch_units__send__msg[4] ), - .send__rdy( switch_units__send__rdy[4] ), - .send__val( switch_units__send__val[4] ) - ); - - //------------------------------------------------------------- - // End of component switch_units[0:4] - //------------------------------------------------------------- - - assign input_units__clk[0] = clk; - assign input_units__reset[0] = reset; - assign input_units__clk[1] = clk; - assign input_units__reset[1] = reset; - assign input_units__clk[2] = clk; - assign input_units__reset[2] = reset; - assign input_units__clk[3] = clk; - assign input_units__reset[3] = reset; - assign input_units__clk[4] = clk; - assign input_units__reset[4] = reset; - assign route_units__clk[0] = clk; - assign route_units__reset[0] = reset; - assign route_units__clk[1] = clk; - assign route_units__reset[1] = reset; - assign route_units__clk[2] = clk; - assign route_units__reset[2] = reset; - assign route_units__clk[3] = clk; - assign route_units__reset[3] = reset; - assign route_units__clk[4] = clk; - assign route_units__reset[4] = reset; - assign switch_units__clk[0] = clk; - assign switch_units__reset[0] = reset; - assign switch_units__clk[1] = clk; - assign switch_units__reset[1] = reset; - assign switch_units__clk[2] = clk; - assign switch_units__reset[2] = reset; - assign switch_units__clk[3] = clk; - assign switch_units__reset[3] = reset; - assign switch_units__clk[4] = clk; - assign switch_units__reset[4] = reset; - assign output_units__clk[0] = clk; - assign output_units__reset[0] = reset; - assign output_units__clk[1] = clk; - assign output_units__reset[1] = reset; - assign output_units__clk[2] = clk; - assign output_units__reset[2] = reset; - assign output_units__clk[3] = clk; - assign output_units__reset[3] = reset; - assign output_units__clk[4] = clk; - assign output_units__reset[4] = reset; - assign input_units__recv__msg[0] = recv__msg[0]; - assign recv__rdy[0] = input_units__recv__rdy[0]; - assign input_units__recv__val[0] = recv__val[0]; - assign route_units__recv__msg[0] = input_units__send__msg[0]; - assign input_units__send__rdy[0] = route_units__recv__rdy[0]; - assign route_units__recv__val[0] = input_units__send__val[0]; - assign route_units__pos[0] = pos; - assign input_units__recv__msg[1] = recv__msg[1]; - assign recv__rdy[1] = input_units__recv__rdy[1]; - assign input_units__recv__val[1] = recv__val[1]; - assign route_units__recv__msg[1] = input_units__send__msg[1]; - assign input_units__send__rdy[1] = route_units__recv__rdy[1]; - assign route_units__recv__val[1] = input_units__send__val[1]; - assign route_units__pos[1] = pos; - assign input_units__recv__msg[2] = recv__msg[2]; - assign recv__rdy[2] = input_units__recv__rdy[2]; - assign input_units__recv__val[2] = recv__val[2]; - assign route_units__recv__msg[2] = input_units__send__msg[2]; - assign input_units__send__rdy[2] = route_units__recv__rdy[2]; - assign route_units__recv__val[2] = input_units__send__val[2]; - assign route_units__pos[2] = pos; - assign input_units__recv__msg[3] = recv__msg[3]; - assign recv__rdy[3] = input_units__recv__rdy[3]; - assign input_units__recv__val[3] = recv__val[3]; - assign route_units__recv__msg[3] = input_units__send__msg[3]; - assign input_units__send__rdy[3] = route_units__recv__rdy[3]; - assign route_units__recv__val[3] = input_units__send__val[3]; - assign route_units__pos[3] = pos; - assign input_units__recv__msg[4] = recv__msg[4]; - assign recv__rdy[4] = input_units__recv__rdy[4]; - assign input_units__recv__val[4] = recv__val[4]; - assign route_units__recv__msg[4] = input_units__send__msg[4]; - assign input_units__send__rdy[4] = route_units__recv__rdy[4]; - assign route_units__recv__val[4] = input_units__send__val[4]; - assign route_units__pos[4] = pos; - assign switch_units__recv__msg[0][0] = route_units__send__msg[0][0]; - assign route_units__send__rdy[0][0] = switch_units__recv__rdy[0][0]; - assign switch_units__recv__val[0][0] = route_units__send__val[0][0]; - assign switch_units__recv__msg[1][0] = route_units__send__msg[0][1]; - assign route_units__send__rdy[0][1] = switch_units__recv__rdy[1][0]; - assign switch_units__recv__val[1][0] = route_units__send__val[0][1]; - assign switch_units__recv__msg[2][0] = route_units__send__msg[0][2]; - assign route_units__send__rdy[0][2] = switch_units__recv__rdy[2][0]; - assign switch_units__recv__val[2][0] = route_units__send__val[0][2]; - assign switch_units__recv__msg[3][0] = route_units__send__msg[0][3]; - assign route_units__send__rdy[0][3] = switch_units__recv__rdy[3][0]; - assign switch_units__recv__val[3][0] = route_units__send__val[0][3]; - assign switch_units__recv__msg[4][0] = route_units__send__msg[0][4]; - assign route_units__send__rdy[0][4] = switch_units__recv__rdy[4][0]; - assign switch_units__recv__val[4][0] = route_units__send__val[0][4]; - assign switch_units__recv__msg[0][1] = route_units__send__msg[1][0]; - assign route_units__send__rdy[1][0] = switch_units__recv__rdy[0][1]; - assign switch_units__recv__val[0][1] = route_units__send__val[1][0]; - assign switch_units__recv__msg[1][1] = route_units__send__msg[1][1]; - assign route_units__send__rdy[1][1] = switch_units__recv__rdy[1][1]; - assign switch_units__recv__val[1][1] = route_units__send__val[1][1]; - assign switch_units__recv__msg[2][1] = route_units__send__msg[1][2]; - assign route_units__send__rdy[1][2] = switch_units__recv__rdy[2][1]; - assign switch_units__recv__val[2][1] = route_units__send__val[1][2]; - assign switch_units__recv__msg[3][1] = route_units__send__msg[1][3]; - assign route_units__send__rdy[1][3] = switch_units__recv__rdy[3][1]; - assign switch_units__recv__val[3][1] = route_units__send__val[1][3]; - assign switch_units__recv__msg[4][1] = route_units__send__msg[1][4]; - assign route_units__send__rdy[1][4] = switch_units__recv__rdy[4][1]; - assign switch_units__recv__val[4][1] = route_units__send__val[1][4]; - assign switch_units__recv__msg[0][2] = route_units__send__msg[2][0]; - assign route_units__send__rdy[2][0] = switch_units__recv__rdy[0][2]; - assign switch_units__recv__val[0][2] = route_units__send__val[2][0]; - assign switch_units__recv__msg[1][2] = route_units__send__msg[2][1]; - assign route_units__send__rdy[2][1] = switch_units__recv__rdy[1][2]; - assign switch_units__recv__val[1][2] = route_units__send__val[2][1]; - assign switch_units__recv__msg[2][2] = route_units__send__msg[2][2]; - assign route_units__send__rdy[2][2] = switch_units__recv__rdy[2][2]; - assign switch_units__recv__val[2][2] = route_units__send__val[2][2]; - assign switch_units__recv__msg[3][2] = route_units__send__msg[2][3]; - assign route_units__send__rdy[2][3] = switch_units__recv__rdy[3][2]; - assign switch_units__recv__val[3][2] = route_units__send__val[2][3]; - assign switch_units__recv__msg[4][2] = route_units__send__msg[2][4]; - assign route_units__send__rdy[2][4] = switch_units__recv__rdy[4][2]; - assign switch_units__recv__val[4][2] = route_units__send__val[2][4]; - assign switch_units__recv__msg[0][3] = route_units__send__msg[3][0]; - assign route_units__send__rdy[3][0] = switch_units__recv__rdy[0][3]; - assign switch_units__recv__val[0][3] = route_units__send__val[3][0]; - assign switch_units__recv__msg[1][3] = route_units__send__msg[3][1]; - assign route_units__send__rdy[3][1] = switch_units__recv__rdy[1][3]; - assign switch_units__recv__val[1][3] = route_units__send__val[3][1]; - assign switch_units__recv__msg[2][3] = route_units__send__msg[3][2]; - assign route_units__send__rdy[3][2] = switch_units__recv__rdy[2][3]; - assign switch_units__recv__val[2][3] = route_units__send__val[3][2]; - assign switch_units__recv__msg[3][3] = route_units__send__msg[3][3]; - assign route_units__send__rdy[3][3] = switch_units__recv__rdy[3][3]; - assign switch_units__recv__val[3][3] = route_units__send__val[3][3]; - assign switch_units__recv__msg[4][3] = route_units__send__msg[3][4]; - assign route_units__send__rdy[3][4] = switch_units__recv__rdy[4][3]; - assign switch_units__recv__val[4][3] = route_units__send__val[3][4]; - assign switch_units__recv__msg[0][4] = route_units__send__msg[4][0]; - assign route_units__send__rdy[4][0] = switch_units__recv__rdy[0][4]; - assign switch_units__recv__val[0][4] = route_units__send__val[4][0]; - assign switch_units__recv__msg[1][4] = route_units__send__msg[4][1]; - assign route_units__send__rdy[4][1] = switch_units__recv__rdy[1][4]; - assign switch_units__recv__val[1][4] = route_units__send__val[4][1]; - assign switch_units__recv__msg[2][4] = route_units__send__msg[4][2]; - assign route_units__send__rdy[4][2] = switch_units__recv__rdy[2][4]; - assign switch_units__recv__val[2][4] = route_units__send__val[4][2]; - assign switch_units__recv__msg[3][4] = route_units__send__msg[4][3]; - assign route_units__send__rdy[4][3] = switch_units__recv__rdy[3][4]; - assign switch_units__recv__val[3][4] = route_units__send__val[4][3]; - assign switch_units__recv__msg[4][4] = route_units__send__msg[4][4]; - assign route_units__send__rdy[4][4] = switch_units__recv__rdy[4][4]; - assign switch_units__recv__val[4][4] = route_units__send__val[4][4]; - assign output_units__recv__msg[0] = switch_units__send__msg[0]; - assign switch_units__send__rdy[0] = output_units__recv__rdy[0]; - assign output_units__recv__val[0] = switch_units__send__val[0]; - assign send__msg[0] = output_units__send__msg[0]; - assign output_units__send__rdy[0] = send__rdy[0]; - assign send__val[0] = output_units__send__val[0]; - assign output_units__recv__msg[1] = switch_units__send__msg[1]; - assign switch_units__send__rdy[1] = output_units__recv__rdy[1]; - assign output_units__recv__val[1] = switch_units__send__val[1]; - assign send__msg[1] = output_units__send__msg[1]; - assign output_units__send__rdy[1] = send__rdy[1]; - assign send__val[1] = output_units__send__val[1]; - assign output_units__recv__msg[2] = switch_units__send__msg[2]; - assign switch_units__send__rdy[2] = output_units__recv__rdy[2]; - assign output_units__recv__val[2] = switch_units__send__val[2]; - assign send__msg[2] = output_units__send__msg[2]; - assign output_units__send__rdy[2] = send__rdy[2]; - assign send__val[2] = output_units__send__val[2]; - assign output_units__recv__msg[3] = switch_units__send__msg[3]; - assign switch_units__send__rdy[3] = output_units__recv__rdy[3]; - assign output_units__recv__val[3] = switch_units__send__val[3]; - assign send__msg[3] = output_units__send__msg[3]; - assign output_units__send__rdy[3] = send__rdy[3]; - assign send__val[3] = output_units__send__val[3]; - assign output_units__recv__msg[4] = switch_units__send__msg[4]; - assign switch_units__send__rdy[4] = output_units__recv__rdy[4]; - assign output_units__recv__val[4] = switch_units__send__val[4]; - assign send__msg[4] = output_units__send__msg[4]; - assign output_units__send__rdy[4] = send__rdy[4]; - assign send__val[4] = output_units__send__val[4]; - -endmodule - - -// PyMTL Component MeshNetworkRTL Definition -// Full name: MeshNetworkRTL__PacketType_InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d__PositionType_MeshPosition_2x2__pos_x_1__pos_y_1__ncols_2__nrows_2__chl_lat_1 -// At /home/ajokai/cgra/VectorCGRAfork0/noc/PyOCN/pymtl3_net/meshnet/MeshNetworkRTL.py - -module MeshNetworkRTL__4ca7f469967df194 -( - input logic [0:0] clk , - input logic [0:0] reset , - input InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d recv__msg [0:3] , - output logic [0:0] recv__rdy [0:3] , - input logic [0:0] recv__val [0:3] , - output InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d send__msg [0:3] , - input logic [0:0] send__rdy [0:3] , - output logic [0:0] send__val [0:3] -); - //------------------------------------------------------------- - // Component channels[0:7] - //------------------------------------------------------------- - - logic [0:0] channels__clk [0:7]; - logic [0:0] channels__reset [0:7]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d channels__recv__msg [0:7]; - logic [0:0] channels__recv__rdy [0:7]; - logic [0:0] channels__recv__val [0:7]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d channels__send__msg [0:7]; - logic [0:0] channels__send__rdy [0:7]; - logic [0:0] channels__send__val [0:7]; - - ChannelRTL__551ecec02ed96ac9 channels__0 - ( - .clk( channels__clk[0] ), - .reset( channels__reset[0] ), - .recv__msg( channels__recv__msg[0] ), - .recv__rdy( channels__recv__rdy[0] ), - .recv__val( channels__recv__val[0] ), - .send__msg( channels__send__msg[0] ), - .send__rdy( channels__send__rdy[0] ), - .send__val( channels__send__val[0] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__1 - ( - .clk( channels__clk[1] ), - .reset( channels__reset[1] ), - .recv__msg( channels__recv__msg[1] ), - .recv__rdy( channels__recv__rdy[1] ), - .recv__val( channels__recv__val[1] ), - .send__msg( channels__send__msg[1] ), - .send__rdy( channels__send__rdy[1] ), - .send__val( channels__send__val[1] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__2 - ( - .clk( channels__clk[2] ), - .reset( channels__reset[2] ), - .recv__msg( channels__recv__msg[2] ), - .recv__rdy( channels__recv__rdy[2] ), - .recv__val( channels__recv__val[2] ), - .send__msg( channels__send__msg[2] ), - .send__rdy( channels__send__rdy[2] ), - .send__val( channels__send__val[2] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__3 - ( - .clk( channels__clk[3] ), - .reset( channels__reset[3] ), - .recv__msg( channels__recv__msg[3] ), - .recv__rdy( channels__recv__rdy[3] ), - .recv__val( channels__recv__val[3] ), - .send__msg( channels__send__msg[3] ), - .send__rdy( channels__send__rdy[3] ), - .send__val( channels__send__val[3] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__4 - ( - .clk( channels__clk[4] ), - .reset( channels__reset[4] ), - .recv__msg( channels__recv__msg[4] ), - .recv__rdy( channels__recv__rdy[4] ), - .recv__val( channels__recv__val[4] ), - .send__msg( channels__send__msg[4] ), - .send__rdy( channels__send__rdy[4] ), - .send__val( channels__send__val[4] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__5 - ( - .clk( channels__clk[5] ), - .reset( channels__reset[5] ), - .recv__msg( channels__recv__msg[5] ), - .recv__rdy( channels__recv__rdy[5] ), - .recv__val( channels__recv__val[5] ), - .send__msg( channels__send__msg[5] ), - .send__rdy( channels__send__rdy[5] ), - .send__val( channels__send__val[5] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__6 - ( - .clk( channels__clk[6] ), - .reset( channels__reset[6] ), - .recv__msg( channels__recv__msg[6] ), - .recv__rdy( channels__recv__rdy[6] ), - .recv__val( channels__recv__val[6] ), - .send__msg( channels__send__msg[6] ), - .send__rdy( channels__send__rdy[6] ), - .send__val( channels__send__val[6] ) - ); - - ChannelRTL__551ecec02ed96ac9 channels__7 - ( - .clk( channels__clk[7] ), - .reset( channels__reset[7] ), - .recv__msg( channels__recv__msg[7] ), - .recv__rdy( channels__recv__rdy[7] ), - .recv__val( channels__recv__val[7] ), - .send__msg( channels__send__msg[7] ), - .send__rdy( channels__send__rdy[7] ), - .send__val( channels__send__val[7] ) - ); - - //------------------------------------------------------------- - // End of component channels[0:7] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component routers[0:3] - //------------------------------------------------------------- - - logic [0:0] routers__clk [0:3]; - MeshPosition_2x2__pos_x_1__pos_y_1 routers__pos [0:3]; - logic [0:0] routers__reset [0:3]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d routers__recv__msg [0:3][0:4]; - logic [0:0] routers__recv__rdy [0:3][0:4]; - logic [0:0] routers__recv__val [0:3][0:4]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d routers__send__msg [0:3][0:4]; - logic [0:0] routers__send__rdy [0:3][0:4]; - logic [0:0] routers__send__val [0:3][0:4]; - - MeshRouterRTL__574f02d875fdbb92 routers__0 - ( - .clk( routers__clk[0] ), - .pos( routers__pos[0] ), - .reset( routers__reset[0] ), - .recv__msg( routers__recv__msg[0] ), - .recv__rdy( routers__recv__rdy[0] ), - .recv__val( routers__recv__val[0] ), - .send__msg( routers__send__msg[0] ), - .send__rdy( routers__send__rdy[0] ), - .send__val( routers__send__val[0] ) - ); - - MeshRouterRTL__574f02d875fdbb92 routers__1 - ( - .clk( routers__clk[1] ), - .pos( routers__pos[1] ), - .reset( routers__reset[1] ), - .recv__msg( routers__recv__msg[1] ), - .recv__rdy( routers__recv__rdy[1] ), - .recv__val( routers__recv__val[1] ), - .send__msg( routers__send__msg[1] ), - .send__rdy( routers__send__rdy[1] ), - .send__val( routers__send__val[1] ) - ); - - MeshRouterRTL__574f02d875fdbb92 routers__2 - ( - .clk( routers__clk[2] ), - .pos( routers__pos[2] ), - .reset( routers__reset[2] ), - .recv__msg( routers__recv__msg[2] ), - .recv__rdy( routers__recv__rdy[2] ), - .recv__val( routers__recv__val[2] ), - .send__msg( routers__send__msg[2] ), - .send__rdy( routers__send__rdy[2] ), - .send__val( routers__send__val[2] ) - ); - - MeshRouterRTL__574f02d875fdbb92 routers__3 - ( - .clk( routers__clk[3] ), - .pos( routers__pos[3] ), - .reset( routers__reset[3] ), - .recv__msg( routers__recv__msg[3] ), - .recv__rdy( routers__recv__rdy[3] ), - .recv__val( routers__recv__val[3] ), - .send__msg( routers__send__msg[3] ), - .send__rdy( routers__send__rdy[3] ), - .send__val( routers__send__val[3] ) - ); - - //------------------------------------------------------------- - // End of component routers[0:3] - //------------------------------------------------------------- - - assign routers__clk[0] = clk; - assign routers__reset[0] = reset; - assign routers__clk[1] = clk; - assign routers__reset[1] = reset; - assign routers__clk[2] = clk; - assign routers__reset[2] = reset; - assign routers__clk[3] = clk; - assign routers__reset[3] = reset; - assign channels__clk[0] = clk; - assign channels__reset[0] = reset; - assign channels__clk[1] = clk; - assign channels__reset[1] = reset; - assign channels__clk[2] = clk; - assign channels__reset[2] = reset; - assign channels__clk[3] = clk; - assign channels__reset[3] = reset; - assign channels__clk[4] = clk; - assign channels__reset[4] = reset; - assign channels__clk[5] = clk; - assign channels__reset[5] = reset; - assign channels__clk[6] = clk; - assign channels__reset[6] = reset; - assign channels__clk[7] = clk; - assign channels__reset[7] = reset; - assign routers__pos[0].pos_x = 1'd0; - assign routers__pos[0].pos_y = 1'd0; - assign routers__pos[1].pos_x = 1'd1; - assign routers__pos[1].pos_y = 1'd0; - assign routers__pos[2].pos_x = 1'd0; - assign routers__pos[2].pos_y = 1'd1; - assign routers__pos[3].pos_x = 1'd1; - assign routers__pos[3].pos_y = 1'd1; - assign channels__recv__msg[0] = routers__send__msg[0][0]; - assign routers__send__rdy[0][0] = channels__recv__rdy[0]; - assign channels__recv__val[0] = routers__send__val[0][0]; - assign routers__recv__msg[2][1] = channels__send__msg[0]; - assign channels__send__rdy[0] = routers__recv__rdy[2][1]; - assign routers__recv__val[2][1] = channels__send__val[0]; - assign channels__recv__msg[1] = routers__send__msg[0][3]; - assign routers__send__rdy[0][3] = channels__recv__rdy[1]; - assign channels__recv__val[1] = routers__send__val[0][3]; - assign routers__recv__msg[1][2] = channels__send__msg[1]; - assign channels__send__rdy[1] = routers__recv__rdy[1][2]; - assign routers__recv__val[1][2] = channels__send__val[1]; - assign routers__recv__msg[0][4] = recv__msg[0]; - assign recv__rdy[0] = routers__recv__rdy[0][4]; - assign routers__recv__val[0][4] = recv__val[0]; - assign send__msg[0] = routers__send__msg[0][4]; - assign routers__send__rdy[0][4] = send__rdy[0]; - assign send__val[0] = routers__send__val[0][4]; - assign routers__send__rdy[0][1] = 1'd0; - assign routers__recv__val[0][1] = 1'd0; - assign routers__recv__msg[0][1] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign routers__send__rdy[0][2] = 1'd0; - assign routers__recv__val[0][2] = 1'd0; - assign routers__recv__msg[0][2] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign channels__recv__msg[2] = routers__send__msg[1][0]; - assign routers__send__rdy[1][0] = channels__recv__rdy[2]; - assign channels__recv__val[2] = routers__send__val[1][0]; - assign routers__recv__msg[3][1] = channels__send__msg[2]; - assign channels__send__rdy[2] = routers__recv__rdy[3][1]; - assign routers__recv__val[3][1] = channels__send__val[2]; - assign channels__recv__msg[3] = routers__send__msg[1][2]; - assign routers__send__rdy[1][2] = channels__recv__rdy[3]; - assign channels__recv__val[3] = routers__send__val[1][2]; - assign routers__recv__msg[0][3] = channels__send__msg[3]; - assign channels__send__rdy[3] = routers__recv__rdy[0][3]; - assign routers__recv__val[0][3] = channels__send__val[3]; - assign routers__recv__msg[1][4] = recv__msg[1]; - assign recv__rdy[1] = routers__recv__rdy[1][4]; - assign routers__recv__val[1][4] = recv__val[1]; - assign send__msg[1] = routers__send__msg[1][4]; - assign routers__send__rdy[1][4] = send__rdy[1]; - assign send__val[1] = routers__send__val[1][4]; - assign routers__send__rdy[1][1] = 1'd0; - assign routers__recv__val[1][1] = 1'd0; - assign routers__recv__msg[1][1] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign routers__send__rdy[1][3] = 1'd0; - assign routers__recv__val[1][3] = 1'd0; - assign routers__recv__msg[1][3] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign channels__recv__msg[4] = routers__send__msg[2][1]; - assign routers__send__rdy[2][1] = channels__recv__rdy[4]; - assign channels__recv__val[4] = routers__send__val[2][1]; - assign routers__recv__msg[0][0] = channels__send__msg[4]; - assign channels__send__rdy[4] = routers__recv__rdy[0][0]; - assign routers__recv__val[0][0] = channels__send__val[4]; - assign channels__recv__msg[5] = routers__send__msg[2][3]; - assign routers__send__rdy[2][3] = channels__recv__rdy[5]; - assign channels__recv__val[5] = routers__send__val[2][3]; - assign routers__recv__msg[3][2] = channels__send__msg[5]; - assign channels__send__rdy[5] = routers__recv__rdy[3][2]; - assign routers__recv__val[3][2] = channels__send__val[5]; - assign routers__recv__msg[2][4] = recv__msg[2]; - assign recv__rdy[2] = routers__recv__rdy[2][4]; - assign routers__recv__val[2][4] = recv__val[2]; - assign send__msg[2] = routers__send__msg[2][4]; - assign routers__send__rdy[2][4] = send__rdy[2]; - assign send__val[2] = routers__send__val[2][4]; - assign routers__send__rdy[2][0] = 1'd0; - assign routers__recv__val[2][0] = 1'd0; - assign routers__recv__msg[2][0] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign routers__send__rdy[2][2] = 1'd0; - assign routers__recv__val[2][2] = 1'd0; - assign routers__recv__msg[2][2] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign channels__recv__msg[6] = routers__send__msg[3][1]; - assign routers__send__rdy[3][1] = channels__recv__rdy[6]; - assign channels__recv__val[6] = routers__send__val[3][1]; - assign routers__recv__msg[1][0] = channels__send__msg[6]; - assign channels__send__rdy[6] = routers__recv__rdy[1][0]; - assign routers__recv__val[1][0] = channels__send__val[6]; - assign channels__recv__msg[7] = routers__send__msg[3][2]; - assign routers__send__rdy[3][2] = channels__recv__rdy[7]; - assign channels__recv__val[7] = routers__send__val[3][2]; - assign routers__recv__msg[2][3] = channels__send__msg[7]; - assign channels__send__rdy[7] = routers__recv__rdy[2][3]; - assign routers__recv__val[2][3] = channels__send__val[7]; - assign routers__recv__msg[3][4] = recv__msg[3]; - assign recv__rdy[3] = routers__recv__rdy[3][4]; - assign routers__recv__val[3][4] = recv__val[3]; - assign send__msg[3] = routers__send__msg[3][4]; - assign routers__send__rdy[3][4] = send__rdy[3]; - assign send__val[3] = routers__send__val[3][4]; - assign routers__send__rdy[3][0] = 1'd0; - assign routers__recv__val[3][0] = 1'd0; - assign routers__recv__msg[3][0] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign routers__send__rdy[3][3] = 1'd0; - assign routers__recv__val[3][3] = 1'd0; - assign routers__recv__msg[3][3] = { 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 5'd0, 5'd0, 3'd0, 8'd0, 2'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - -endmodule - - -// PyMTL Component MeshMultiCgraRTL Definition -// Full name: MeshMultiCgraRTL__CgraPayloadType_MultiCgraPayload_Cmd_Data_DataAddr_Ctrl_CtrlAddr__c5ddbab50341e13a__cgra_rows_2__cgra_columns_2__tile_rows_4__tile_columns_4__ctrl_mem_size_16__data_mem_size_global_128__data_mem_size_per_bank_16__num_banks_per_cgra_2__num_registers_per_reg_bank_16__num_ctrl_4__total_steps_38__mem_access_is_combinational_True__FunctionUnit_FlexibleFuRTL__FuList_[, , , , , , , , , , , , , , ]__per_cgra_topology_Mesh__controller2addr_map_{0: [0, 31], 1: [32, 63], 2: [64, 95], 3: [96, 127]}__support_task_switching_False -// At /home/ajokai/cgra/VectorCGRAfork0/multi_cgra/MeshMultiCgraRTL.py - -module MeshMultiCgraRTL__975ce70dc1a0740a -( - input logic [0:0] clk , - input logic [0:0] reset , - input IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 recv_from_cpu_pkt__msg , - output logic [0:0] recv_from_cpu_pkt__rdy , - input logic [0:0] recv_from_cpu_pkt__val , - output IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 send_to_cpu_pkt__msg , - input logic [0:0] send_to_cpu_pkt__rdy , - output logic [0:0] send_to_cpu_pkt__val -); - //------------------------------------------------------------- - // Component cgra[0:3] - //------------------------------------------------------------- - - logic [6:0] cgra__address_lower [0:3]; - logic [6:0] cgra__address_upper [0:3]; - logic [1:0] cgra__cgra_id [0:3]; - logic [0:0] cgra__clk [0:3]; - logic [0:0] cgra__reset [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_east__msg [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_east__rdy [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_east__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_north__msg [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_north__rdy [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_north__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_south__msg [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_south__rdy [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_south__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__recv_data_on_boundary_west__msg [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_west__rdy [0:3][0:3]; - logic [0:0] cgra__recv_data_on_boundary_west__val [0:3][0:3]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 cgra__recv_from_cpu_pkt__msg [0:3]; - logic [0:0] cgra__recv_from_cpu_pkt__rdy [0:3]; - logic [0:0] cgra__recv_from_cpu_pkt__val [0:3]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d cgra__recv_from_inter_cgra_noc__msg [0:3]; - logic [0:0] cgra__recv_from_inter_cgra_noc__rdy [0:3]; - logic [0:0] cgra__recv_from_inter_cgra_noc__val [0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_east__msg [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_east__rdy [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_east__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_north__msg [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_north__rdy [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_north__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_south__msg [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_south__rdy [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_south__val [0:3][0:3]; - CgraData_64_1_1_1__payload_64__predicate_1__bypass_1__delay_1 cgra__send_data_on_boundary_west__msg [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_west__rdy [0:3][0:3]; - logic [0:0] cgra__send_data_on_boundary_west__val [0:3][0:3]; - IntraCgraPacket_4_2x2_16_8_2_CgraPayload__d294fd7ecd3c5b69 cgra__send_to_cpu_pkt__msg [0:3]; - logic [0:0] cgra__send_to_cpu_pkt__rdy [0:3]; - logic [0:0] cgra__send_to_cpu_pkt__val [0:3]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d cgra__send_to_inter_cgra_noc__msg [0:3]; - logic [0:0] cgra__send_to_inter_cgra_noc__rdy [0:3]; - logic [0:0] cgra__send_to_inter_cgra_noc__val [0:3]; - - CgraRTL__72d915b46abe89cb cgra__0 - ( - .address_lower( cgra__address_lower[0] ), - .address_upper( cgra__address_upper[0] ), - .cgra_id( cgra__cgra_id[0] ), - .clk( cgra__clk[0] ), - .reset( cgra__reset[0] ), - .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[0] ), - .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[0] ), - .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[0] ), - .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[0] ), - .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[0] ), - .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[0] ), - .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[0] ), - .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[0] ), - .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[0] ), - .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[0] ), - .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[0] ), - .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[0] ), - .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[0] ), - .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[0] ), - .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[0] ), - .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[0] ), - .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[0] ), - .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[0] ), - .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[0] ), - .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[0] ), - .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[0] ), - .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[0] ), - .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[0] ), - .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[0] ), - .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[0] ), - .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[0] ), - .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[0] ), - .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[0] ), - .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[0] ), - .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[0] ), - .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[0] ), - .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[0] ), - .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[0] ), - .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[0] ), - .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[0] ), - .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[0] ) - ); - - CgraRTL__72d915b46abe89cb cgra__1 - ( - .address_lower( cgra__address_lower[1] ), - .address_upper( cgra__address_upper[1] ), - .cgra_id( cgra__cgra_id[1] ), - .clk( cgra__clk[1] ), - .reset( cgra__reset[1] ), - .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[1] ), - .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[1] ), - .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[1] ), - .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[1] ), - .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[1] ), - .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[1] ), - .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[1] ), - .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[1] ), - .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[1] ), - .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[1] ), - .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[1] ), - .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[1] ), - .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[1] ), - .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[1] ), - .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[1] ), - .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[1] ), - .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[1] ), - .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[1] ), - .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[1] ), - .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[1] ), - .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[1] ), - .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[1] ), - .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[1] ), - .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[1] ), - .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[1] ), - .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[1] ), - .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[1] ), - .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[1] ), - .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[1] ), - .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[1] ), - .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[1] ), - .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[1] ), - .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[1] ), - .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[1] ), - .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[1] ), - .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[1] ) - ); - - CgraRTL__72d915b46abe89cb cgra__2 - ( - .address_lower( cgra__address_lower[2] ), - .address_upper( cgra__address_upper[2] ), - .cgra_id( cgra__cgra_id[2] ), - .clk( cgra__clk[2] ), - .reset( cgra__reset[2] ), - .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[2] ), - .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[2] ), - .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[2] ), - .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[2] ), - .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[2] ), - .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[2] ), - .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[2] ), - .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[2] ), - .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[2] ), - .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[2] ), - .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[2] ), - .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[2] ), - .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[2] ), - .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[2] ), - .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[2] ), - .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[2] ), - .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[2] ), - .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[2] ), - .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[2] ), - .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[2] ), - .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[2] ), - .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[2] ), - .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[2] ), - .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[2] ), - .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[2] ), - .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[2] ), - .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[2] ), - .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[2] ), - .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[2] ), - .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[2] ), - .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[2] ), - .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[2] ), - .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[2] ), - .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[2] ), - .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[2] ), - .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[2] ) - ); - - CgraRTL__72d915b46abe89cb cgra__3 - ( - .address_lower( cgra__address_lower[3] ), - .address_upper( cgra__address_upper[3] ), - .cgra_id( cgra__cgra_id[3] ), - .clk( cgra__clk[3] ), - .reset( cgra__reset[3] ), - .recv_data_on_boundary_east__msg( cgra__recv_data_on_boundary_east__msg[3] ), - .recv_data_on_boundary_east__rdy( cgra__recv_data_on_boundary_east__rdy[3] ), - .recv_data_on_boundary_east__val( cgra__recv_data_on_boundary_east__val[3] ), - .recv_data_on_boundary_north__msg( cgra__recv_data_on_boundary_north__msg[3] ), - .recv_data_on_boundary_north__rdy( cgra__recv_data_on_boundary_north__rdy[3] ), - .recv_data_on_boundary_north__val( cgra__recv_data_on_boundary_north__val[3] ), - .recv_data_on_boundary_south__msg( cgra__recv_data_on_boundary_south__msg[3] ), - .recv_data_on_boundary_south__rdy( cgra__recv_data_on_boundary_south__rdy[3] ), - .recv_data_on_boundary_south__val( cgra__recv_data_on_boundary_south__val[3] ), - .recv_data_on_boundary_west__msg( cgra__recv_data_on_boundary_west__msg[3] ), - .recv_data_on_boundary_west__rdy( cgra__recv_data_on_boundary_west__rdy[3] ), - .recv_data_on_boundary_west__val( cgra__recv_data_on_boundary_west__val[3] ), - .recv_from_cpu_pkt__msg( cgra__recv_from_cpu_pkt__msg[3] ), - .recv_from_cpu_pkt__rdy( cgra__recv_from_cpu_pkt__rdy[3] ), - .recv_from_cpu_pkt__val( cgra__recv_from_cpu_pkt__val[3] ), - .recv_from_inter_cgra_noc__msg( cgra__recv_from_inter_cgra_noc__msg[3] ), - .recv_from_inter_cgra_noc__rdy( cgra__recv_from_inter_cgra_noc__rdy[3] ), - .recv_from_inter_cgra_noc__val( cgra__recv_from_inter_cgra_noc__val[3] ), - .send_data_on_boundary_east__msg( cgra__send_data_on_boundary_east__msg[3] ), - .send_data_on_boundary_east__rdy( cgra__send_data_on_boundary_east__rdy[3] ), - .send_data_on_boundary_east__val( cgra__send_data_on_boundary_east__val[3] ), - .send_data_on_boundary_north__msg( cgra__send_data_on_boundary_north__msg[3] ), - .send_data_on_boundary_north__rdy( cgra__send_data_on_boundary_north__rdy[3] ), - .send_data_on_boundary_north__val( cgra__send_data_on_boundary_north__val[3] ), - .send_data_on_boundary_south__msg( cgra__send_data_on_boundary_south__msg[3] ), - .send_data_on_boundary_south__rdy( cgra__send_data_on_boundary_south__rdy[3] ), - .send_data_on_boundary_south__val( cgra__send_data_on_boundary_south__val[3] ), - .send_data_on_boundary_west__msg( cgra__send_data_on_boundary_west__msg[3] ), - .send_data_on_boundary_west__rdy( cgra__send_data_on_boundary_west__rdy[3] ), - .send_data_on_boundary_west__val( cgra__send_data_on_boundary_west__val[3] ), - .send_to_cpu_pkt__msg( cgra__send_to_cpu_pkt__msg[3] ), - .send_to_cpu_pkt__rdy( cgra__send_to_cpu_pkt__rdy[3] ), - .send_to_cpu_pkt__val( cgra__send_to_cpu_pkt__val[3] ), - .send_to_inter_cgra_noc__msg( cgra__send_to_inter_cgra_noc__msg[3] ), - .send_to_inter_cgra_noc__rdy( cgra__send_to_inter_cgra_noc__rdy[3] ), - .send_to_inter_cgra_noc__val( cgra__send_to_inter_cgra_noc__val[3] ) - ); - - //------------------------------------------------------------- - // End of component cgra[0:3] - //------------------------------------------------------------- - - //------------------------------------------------------------- - // Component mesh - //------------------------------------------------------------- - - logic [0:0] mesh__clk; - logic [0:0] mesh__reset; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mesh__recv__msg [0:3]; - logic [0:0] mesh__recv__rdy [0:3]; - logic [0:0] mesh__recv__val [0:3]; - InterCgraPacket_4_2x2_16_8_4_CgraPayload__3637e8fbb068232d mesh__send__msg [0:3]; - logic [0:0] mesh__send__rdy [0:3]; - logic [0:0] mesh__send__val [0:3]; - - MeshNetworkRTL__4ca7f469967df194 mesh - ( - .clk( mesh__clk ), - .reset( mesh__reset ), - .recv__msg( mesh__recv__msg ), - .recv__rdy( mesh__recv__rdy ), - .recv__val( mesh__recv__val ), - .send__msg( mesh__send__msg ), - .send__rdy( mesh__send__rdy ), - .send__val( mesh__send__val ) - ); - - //------------------------------------------------------------- - // End of component mesh - //------------------------------------------------------------- - - assign cgra__clk[0] = clk; - assign cgra__reset[0] = reset; - assign cgra__clk[1] = clk; - assign cgra__reset[1] = reset; - assign cgra__clk[2] = clk; - assign cgra__reset[2] = reset; - assign cgra__clk[3] = clk; - assign cgra__reset[3] = reset; - assign mesh__clk = clk; - assign mesh__reset = reset; - assign cgra__recv_from_inter_cgra_noc__msg[0] = mesh__send__msg[0]; - assign mesh__send__rdy[0] = cgra__recv_from_inter_cgra_noc__rdy[0]; - assign cgra__recv_from_inter_cgra_noc__val[0] = mesh__send__val[0]; - assign mesh__recv__msg[0] = cgra__send_to_inter_cgra_noc__msg[0]; - assign cgra__send_to_inter_cgra_noc__rdy[0] = mesh__recv__rdy[0]; - assign mesh__recv__val[0] = cgra__send_to_inter_cgra_noc__val[0]; - assign cgra__recv_from_inter_cgra_noc__msg[1] = mesh__send__msg[1]; - assign mesh__send__rdy[1] = cgra__recv_from_inter_cgra_noc__rdy[1]; - assign cgra__recv_from_inter_cgra_noc__val[1] = mesh__send__val[1]; - assign mesh__recv__msg[1] = cgra__send_to_inter_cgra_noc__msg[1]; - assign cgra__send_to_inter_cgra_noc__rdy[1] = mesh__recv__rdy[1]; - assign mesh__recv__val[1] = cgra__send_to_inter_cgra_noc__val[1]; - assign cgra__recv_from_inter_cgra_noc__msg[2] = mesh__send__msg[2]; - assign mesh__send__rdy[2] = cgra__recv_from_inter_cgra_noc__rdy[2]; - assign cgra__recv_from_inter_cgra_noc__val[2] = mesh__send__val[2]; - assign mesh__recv__msg[2] = cgra__send_to_inter_cgra_noc__msg[2]; - assign cgra__send_to_inter_cgra_noc__rdy[2] = mesh__recv__rdy[2]; - assign mesh__recv__val[2] = cgra__send_to_inter_cgra_noc__val[2]; - assign cgra__recv_from_inter_cgra_noc__msg[3] = mesh__send__msg[3]; - assign mesh__send__rdy[3] = cgra__recv_from_inter_cgra_noc__rdy[3]; - assign cgra__recv_from_inter_cgra_noc__val[3] = mesh__send__val[3]; - assign mesh__recv__msg[3] = cgra__send_to_inter_cgra_noc__msg[3]; - assign cgra__send_to_inter_cgra_noc__rdy[3] = mesh__recv__rdy[3]; - assign mesh__recv__val[3] = cgra__send_to_inter_cgra_noc__val[3]; - assign cgra__cgra_id[0] = 2'd0; - assign cgra__cgra_id[1] = 2'd1; - assign cgra__cgra_id[2] = 2'd2; - assign cgra__cgra_id[3] = 2'd3; - assign cgra__address_lower[0] = 7'd0; - assign cgra__address_upper[0] = 7'd31; - assign cgra__address_lower[1] = 7'd32; - assign cgra__address_upper[1] = 7'd63; - assign cgra__address_lower[2] = 7'd64; - assign cgra__address_upper[2] = 7'd95; - assign cgra__address_lower[3] = 7'd96; - assign cgra__address_upper[3] = 7'd127; - assign cgra__recv_from_cpu_pkt__msg[0] = recv_from_cpu_pkt__msg; - assign recv_from_cpu_pkt__rdy = cgra__recv_from_cpu_pkt__rdy[0]; - assign cgra__recv_from_cpu_pkt__val[0] = recv_from_cpu_pkt__val; - assign send_to_cpu_pkt__msg = cgra__send_to_cpu_pkt__msg[0]; - assign cgra__send_to_cpu_pkt__rdy[0] = send_to_cpu_pkt__rdy; - assign send_to_cpu_pkt__val = cgra__send_to_cpu_pkt__val[0]; - assign cgra__recv_from_cpu_pkt__val[1] = 1'd0; - assign cgra__recv_from_cpu_pkt__msg[1] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign cgra__send_to_cpu_pkt__rdy[1] = 1'd0; - assign cgra__recv_from_cpu_pkt__val[2] = 1'd0; - assign cgra__recv_from_cpu_pkt__msg[2] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign cgra__send_to_cpu_pkt__rdy[2] = 1'd0; - assign cgra__recv_from_cpu_pkt__val[3] = 1'd0; - assign cgra__recv_from_cpu_pkt__msg[3] = { 5'd0, 5'd0, 2'd0, 2'd0, 1'd0, 1'd0, 1'd0, 1'd0, 8'd0, 1'd0, { 5'd0, { 64'd0, 1'd0, 1'd0, 1'd0 }, 7'd0, { 7'd0, { {3'd0, 3'd0, 3'd0, 3'd0} }, { {3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0, 3'd0} }, { {2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0, 2'd0} }, 3'd0, 1'd0, { {2'd0, 2'd0, 2'd0, 2'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} }, { {1'd0, 1'd0, 1'd0, 1'd0} }, { {4'd0, 4'd0, 4'd0, 4'd0} } }, 4'd0 } }; - assign cgra__send_to_cpu_pkt__rdy[3] = 1'd0; - assign cgra__send_data_on_boundary_south__rdy[0][0] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[0][0] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[0][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[0][1] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[0][1] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[0][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[0][2] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[0][2] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[0][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[0][3] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[0][3] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[0][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[0][0] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[0][0] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[0][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[0][1] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[0][1] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[0][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[0][2] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[0][2] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[0][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[0][3] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[0][3] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[0][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[1][0] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[1][0] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[1][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[1][1] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[1][1] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[1][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[1][2] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[1][2] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[1][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_south__rdy[1][3] = 1'd0; - assign cgra__recv_data_on_boundary_south__val[1][3] = 1'd0; - assign cgra__recv_data_on_boundary_south__msg[1][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__recv_data_on_boundary_east__msg[0][0] = cgra__send_data_on_boundary_west__msg[1][0]; - assign cgra__send_data_on_boundary_west__rdy[1][0] = cgra__recv_data_on_boundary_east__rdy[0][0]; - assign cgra__recv_data_on_boundary_east__val[0][0] = cgra__send_data_on_boundary_west__val[1][0]; - assign cgra__recv_data_on_boundary_west__msg[1][0] = cgra__send_data_on_boundary_east__msg[0][0]; - assign cgra__send_data_on_boundary_east__rdy[0][0] = cgra__recv_data_on_boundary_west__rdy[1][0]; - assign cgra__recv_data_on_boundary_west__val[1][0] = cgra__send_data_on_boundary_east__val[0][0]; - assign cgra__recv_data_on_boundary_east__msg[0][1] = cgra__send_data_on_boundary_west__msg[1][1]; - assign cgra__send_data_on_boundary_west__rdy[1][1] = cgra__recv_data_on_boundary_east__rdy[0][1]; - assign cgra__recv_data_on_boundary_east__val[0][1] = cgra__send_data_on_boundary_west__val[1][1]; - assign cgra__recv_data_on_boundary_west__msg[1][1] = cgra__send_data_on_boundary_east__msg[0][1]; - assign cgra__send_data_on_boundary_east__rdy[0][1] = cgra__recv_data_on_boundary_west__rdy[1][1]; - assign cgra__recv_data_on_boundary_west__val[1][1] = cgra__send_data_on_boundary_east__val[0][1]; - assign cgra__recv_data_on_boundary_east__msg[0][2] = cgra__send_data_on_boundary_west__msg[1][2]; - assign cgra__send_data_on_boundary_west__rdy[1][2] = cgra__recv_data_on_boundary_east__rdy[0][2]; - assign cgra__recv_data_on_boundary_east__val[0][2] = cgra__send_data_on_boundary_west__val[1][2]; - assign cgra__recv_data_on_boundary_west__msg[1][2] = cgra__send_data_on_boundary_east__msg[0][2]; - assign cgra__send_data_on_boundary_east__rdy[0][2] = cgra__recv_data_on_boundary_west__rdy[1][2]; - assign cgra__recv_data_on_boundary_west__val[1][2] = cgra__send_data_on_boundary_east__val[0][2]; - assign cgra__recv_data_on_boundary_east__msg[0][3] = cgra__send_data_on_boundary_west__msg[1][3]; - assign cgra__send_data_on_boundary_west__rdy[1][3] = cgra__recv_data_on_boundary_east__rdy[0][3]; - assign cgra__recv_data_on_boundary_east__val[0][3] = cgra__send_data_on_boundary_west__val[1][3]; - assign cgra__recv_data_on_boundary_west__msg[1][3] = cgra__send_data_on_boundary_east__msg[0][3]; - assign cgra__send_data_on_boundary_east__rdy[0][3] = cgra__recv_data_on_boundary_west__rdy[1][3]; - assign cgra__recv_data_on_boundary_west__val[1][3] = cgra__send_data_on_boundary_east__val[0][3]; - assign cgra__send_data_on_boundary_east__rdy[1][0] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[1][0] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[1][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[1][1] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[1][1] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[1][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[1][2] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[1][2] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[1][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[1][3] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[1][3] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[1][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__recv_data_on_boundary_north__msg[0][0] = cgra__send_data_on_boundary_south__msg[2][0]; - assign cgra__send_data_on_boundary_south__rdy[2][0] = cgra__recv_data_on_boundary_north__rdy[0][0]; - assign cgra__recv_data_on_boundary_north__val[0][0] = cgra__send_data_on_boundary_south__val[2][0]; - assign cgra__recv_data_on_boundary_south__msg[2][0] = cgra__send_data_on_boundary_north__msg[0][0]; - assign cgra__send_data_on_boundary_north__rdy[0][0] = cgra__recv_data_on_boundary_south__rdy[2][0]; - assign cgra__recv_data_on_boundary_south__val[2][0] = cgra__send_data_on_boundary_north__val[0][0]; - assign cgra__recv_data_on_boundary_north__msg[0][1] = cgra__send_data_on_boundary_south__msg[2][1]; - assign cgra__send_data_on_boundary_south__rdy[2][1] = cgra__recv_data_on_boundary_north__rdy[0][1]; - assign cgra__recv_data_on_boundary_north__val[0][1] = cgra__send_data_on_boundary_south__val[2][1]; - assign cgra__recv_data_on_boundary_south__msg[2][1] = cgra__send_data_on_boundary_north__msg[0][1]; - assign cgra__send_data_on_boundary_north__rdy[0][1] = cgra__recv_data_on_boundary_south__rdy[2][1]; - assign cgra__recv_data_on_boundary_south__val[2][1] = cgra__send_data_on_boundary_north__val[0][1]; - assign cgra__recv_data_on_boundary_north__msg[0][2] = cgra__send_data_on_boundary_south__msg[2][2]; - assign cgra__send_data_on_boundary_south__rdy[2][2] = cgra__recv_data_on_boundary_north__rdy[0][2]; - assign cgra__recv_data_on_boundary_north__val[0][2] = cgra__send_data_on_boundary_south__val[2][2]; - assign cgra__recv_data_on_boundary_south__msg[2][2] = cgra__send_data_on_boundary_north__msg[0][2]; - assign cgra__send_data_on_boundary_north__rdy[0][2] = cgra__recv_data_on_boundary_south__rdy[2][2]; - assign cgra__recv_data_on_boundary_south__val[2][2] = cgra__send_data_on_boundary_north__val[0][2]; - assign cgra__recv_data_on_boundary_north__msg[0][3] = cgra__send_data_on_boundary_south__msg[2][3]; - assign cgra__send_data_on_boundary_south__rdy[2][3] = cgra__recv_data_on_boundary_north__rdy[0][3]; - assign cgra__recv_data_on_boundary_north__val[0][3] = cgra__send_data_on_boundary_south__val[2][3]; - assign cgra__recv_data_on_boundary_south__msg[2][3] = cgra__send_data_on_boundary_north__msg[0][3]; - assign cgra__send_data_on_boundary_north__rdy[0][3] = cgra__recv_data_on_boundary_south__rdy[2][3]; - assign cgra__recv_data_on_boundary_south__val[2][3] = cgra__send_data_on_boundary_north__val[0][3]; - assign cgra__send_data_on_boundary_north__rdy[2][0] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[2][0] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[2][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[2][1] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[2][1] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[2][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[2][2] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[2][2] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[2][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[2][3] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[2][3] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[2][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[2][0] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[2][0] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[2][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[2][1] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[2][1] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[2][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[2][2] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[2][2] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[2][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_west__rdy[2][3] = 1'd0; - assign cgra__recv_data_on_boundary_west__val[2][3] = 1'd0; - assign cgra__recv_data_on_boundary_west__msg[2][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__recv_data_on_boundary_north__msg[1][0] = cgra__send_data_on_boundary_south__msg[3][0]; - assign cgra__send_data_on_boundary_south__rdy[3][0] = cgra__recv_data_on_boundary_north__rdy[1][0]; - assign cgra__recv_data_on_boundary_north__val[1][0] = cgra__send_data_on_boundary_south__val[3][0]; - assign cgra__recv_data_on_boundary_south__msg[3][0] = cgra__send_data_on_boundary_north__msg[1][0]; - assign cgra__send_data_on_boundary_north__rdy[1][0] = cgra__recv_data_on_boundary_south__rdy[3][0]; - assign cgra__recv_data_on_boundary_south__val[3][0] = cgra__send_data_on_boundary_north__val[1][0]; - assign cgra__recv_data_on_boundary_north__msg[1][1] = cgra__send_data_on_boundary_south__msg[3][1]; - assign cgra__send_data_on_boundary_south__rdy[3][1] = cgra__recv_data_on_boundary_north__rdy[1][1]; - assign cgra__recv_data_on_boundary_north__val[1][1] = cgra__send_data_on_boundary_south__val[3][1]; - assign cgra__recv_data_on_boundary_south__msg[3][1] = cgra__send_data_on_boundary_north__msg[1][1]; - assign cgra__send_data_on_boundary_north__rdy[1][1] = cgra__recv_data_on_boundary_south__rdy[3][1]; - assign cgra__recv_data_on_boundary_south__val[3][1] = cgra__send_data_on_boundary_north__val[1][1]; - assign cgra__recv_data_on_boundary_north__msg[1][2] = cgra__send_data_on_boundary_south__msg[3][2]; - assign cgra__send_data_on_boundary_south__rdy[3][2] = cgra__recv_data_on_boundary_north__rdy[1][2]; - assign cgra__recv_data_on_boundary_north__val[1][2] = cgra__send_data_on_boundary_south__val[3][2]; - assign cgra__recv_data_on_boundary_south__msg[3][2] = cgra__send_data_on_boundary_north__msg[1][2]; - assign cgra__send_data_on_boundary_north__rdy[1][2] = cgra__recv_data_on_boundary_south__rdy[3][2]; - assign cgra__recv_data_on_boundary_south__val[3][2] = cgra__send_data_on_boundary_north__val[1][2]; - assign cgra__recv_data_on_boundary_north__msg[1][3] = cgra__send_data_on_boundary_south__msg[3][3]; - assign cgra__send_data_on_boundary_south__rdy[3][3] = cgra__recv_data_on_boundary_north__rdy[1][3]; - assign cgra__recv_data_on_boundary_north__val[1][3] = cgra__send_data_on_boundary_south__val[3][3]; - assign cgra__recv_data_on_boundary_south__msg[3][3] = cgra__send_data_on_boundary_north__msg[1][3]; - assign cgra__send_data_on_boundary_north__rdy[1][3] = cgra__recv_data_on_boundary_south__rdy[3][3]; - assign cgra__recv_data_on_boundary_south__val[3][3] = cgra__send_data_on_boundary_north__val[1][3]; - assign cgra__send_data_on_boundary_north__rdy[3][0] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[3][0] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[3][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[3][1] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[3][1] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[3][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[3][2] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[3][2] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[3][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_north__rdy[3][3] = 1'd0; - assign cgra__recv_data_on_boundary_north__val[3][3] = 1'd0; - assign cgra__recv_data_on_boundary_north__msg[3][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__recv_data_on_boundary_east__msg[2][0] = cgra__send_data_on_boundary_west__msg[3][0]; - assign cgra__send_data_on_boundary_west__rdy[3][0] = cgra__recv_data_on_boundary_east__rdy[2][0]; - assign cgra__recv_data_on_boundary_east__val[2][0] = cgra__send_data_on_boundary_west__val[3][0]; - assign cgra__recv_data_on_boundary_west__msg[3][0] = cgra__send_data_on_boundary_east__msg[2][0]; - assign cgra__send_data_on_boundary_east__rdy[2][0] = cgra__recv_data_on_boundary_west__rdy[3][0]; - assign cgra__recv_data_on_boundary_west__val[3][0] = cgra__send_data_on_boundary_east__val[2][0]; - assign cgra__recv_data_on_boundary_east__msg[2][1] = cgra__send_data_on_boundary_west__msg[3][1]; - assign cgra__send_data_on_boundary_west__rdy[3][1] = cgra__recv_data_on_boundary_east__rdy[2][1]; - assign cgra__recv_data_on_boundary_east__val[2][1] = cgra__send_data_on_boundary_west__val[3][1]; - assign cgra__recv_data_on_boundary_west__msg[3][1] = cgra__send_data_on_boundary_east__msg[2][1]; - assign cgra__send_data_on_boundary_east__rdy[2][1] = cgra__recv_data_on_boundary_west__rdy[3][1]; - assign cgra__recv_data_on_boundary_west__val[3][1] = cgra__send_data_on_boundary_east__val[2][1]; - assign cgra__recv_data_on_boundary_east__msg[2][2] = cgra__send_data_on_boundary_west__msg[3][2]; - assign cgra__send_data_on_boundary_west__rdy[3][2] = cgra__recv_data_on_boundary_east__rdy[2][2]; - assign cgra__recv_data_on_boundary_east__val[2][2] = cgra__send_data_on_boundary_west__val[3][2]; - assign cgra__recv_data_on_boundary_west__msg[3][2] = cgra__send_data_on_boundary_east__msg[2][2]; - assign cgra__send_data_on_boundary_east__rdy[2][2] = cgra__recv_data_on_boundary_west__rdy[3][2]; - assign cgra__recv_data_on_boundary_west__val[3][2] = cgra__send_data_on_boundary_east__val[2][2]; - assign cgra__recv_data_on_boundary_east__msg[2][3] = cgra__send_data_on_boundary_west__msg[3][3]; - assign cgra__send_data_on_boundary_west__rdy[3][3] = cgra__recv_data_on_boundary_east__rdy[2][3]; - assign cgra__recv_data_on_boundary_east__val[2][3] = cgra__send_data_on_boundary_west__val[3][3]; - assign cgra__recv_data_on_boundary_west__msg[3][3] = cgra__send_data_on_boundary_east__msg[2][3]; - assign cgra__send_data_on_boundary_east__rdy[2][3] = cgra__recv_data_on_boundary_west__rdy[3][3]; - assign cgra__recv_data_on_boundary_west__val[3][3] = cgra__send_data_on_boundary_east__val[2][3]; - assign cgra__send_data_on_boundary_east__rdy[3][0] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[3][0] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[3][0] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[3][1] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[3][1] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[3][1] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[3][2] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[3][2] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[3][2] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - assign cgra__send_data_on_boundary_east__rdy[3][3] = 1'd0; - assign cgra__recv_data_on_boundary_east__val[3][3] = 1'd0; - assign cgra__recv_data_on_boundary_east__msg[3][3] = { 64'd0, 1'd0, 1'd0, 1'd0 }; - -endmodule diff --git a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v b/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v deleted file mode 100644 index 3abd9dd5..00000000 --- a/multi_cgra/test/MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v +++ /dev/null @@ -1,138 +0,0 @@ - -// VT_INPUT_DELAY, VTB_OUTPUT_ASSERT_DELAY are timestamps relative to the rising edge. -`define VTB_INPUT_DELAY 1 -`define VTB_OUTPUT_ASSERT_DELAY 3 - -// CYCLE_TIME and INTRA_CYCLE_TIME are duration of time. -`define CYCLE_TIME 4 -`define INTRA_CYCLE_TIME (`VTB_OUTPUT_ASSERT_DELAY-`VTB_INPUT_DELAY) - -`timescale 1ns/1ns - -`define T(a0,a1,a2,a3,a4,a5) \ - t(a0,a1,a2,a3,a4,a5,`__LINE__) - -// Tick one extra cycle upon an error. -`define VTB_TEST_FAIL(lineno, out, ref, port_name) \ - $display("- Timestamp : %0d (default unit: ns)", $time); \ - $display("- Cycle number : %0d (variable: cycle_count)", cycle_count); \ - $display("- line number : line %0d in MeshMultiCgraRTL__975ce70dc1a0740a_test_multi_CGRA_fir_vector_global_reduce_tb.v.cases", lineno); \ - $display("- port name : %s", port_name); \ - $display("- expected value : 0x%x", ref); \ - $display("- actual value : 0x%x", out); \ - $display(""); \ - #(`CYCLE_TIME-`INTRA_CYCLE_TIME); \ - cycle_count += 1; \ - #`CYCLE_TIME; \ - cycle_count += 1; \ - $fatal; - -`define CHECK(lineno, out, ref, port_name) \ - if ((|(out ^ out)) == 1'b0) ; \ - else begin \ - $display(""); \ - $display("The test bench received a value containing X/Z's! Please note"); \ - $display("that the VTB is pessmistic about X's and you should make sure"); \ - $display("all output ports of your DUT does not produce X's after reset."); \ - `VTB_TEST_FAIL(lineno, out, ref, port_name) \ - end \ - if (out != ref) begin \ - $display(""); \ - $display("The test bench received an incorrect value!"); \ - `VTB_TEST_FAIL(lineno, out, ref, port_name) \ - end - -module MeshMultiCgraRTL__975ce70dc1a0740a_tb; - // convention - logic clk; - logic reset; - integer cycle_count; - - logic [216:0] recv_from_cpu_pkt__msg ; - logic [0:0] recv_from_cpu_pkt__rdy ; - logic [0:0] recv_from_cpu_pkt__val ; - logic [216:0] send_to_cpu_pkt__msg ; - logic [0:0] send_to_cpu_pkt__rdy ; - logic [0:0] send_to_cpu_pkt__val ; - - task t( - input logic [216:0] inp_recv_from_cpu_pkt__msg, - input logic [0:0] ref_recv_from_cpu_pkt__rdy, - input logic [0:0] inp_recv_from_cpu_pkt__val, - input logic [216:0] ref_send_to_cpu_pkt__msg, - input logic [0:0] inp_send_to_cpu_pkt__rdy, - input logic [0:0] ref_send_to_cpu_pkt__val, - integer lineno - ); - begin - recv_from_cpu_pkt__msg = inp_recv_from_cpu_pkt__msg; - recv_from_cpu_pkt__val = inp_recv_from_cpu_pkt__val; - send_to_cpu_pkt__rdy = inp_send_to_cpu_pkt__rdy; - #`INTRA_CYCLE_TIME; - `CHECK(lineno, recv_from_cpu_pkt__rdy, ref_recv_from_cpu_pkt__rdy, "recv_from_cpu_pkt.rdy (recv_from_cpu_pkt__rdy in Verilog)"); - `CHECK(lineno, send_to_cpu_pkt__msg, ref_send_to_cpu_pkt__msg, "send_to_cpu_pkt.msg (send_to_cpu_pkt__msg in Verilog)"); - `CHECK(lineno, send_to_cpu_pkt__val, ref_send_to_cpu_pkt__val, "send_to_cpu_pkt.val (send_to_cpu_pkt__val in Verilog)"); - #(`CYCLE_TIME-`INTRA_CYCLE_TIME); - cycle_count += 1; - end - endtask - - // use 25% clock cycle, so #1 for setup #2 for sim #1 for hold - always #(`CYCLE_TIME/2) clk = ~clk; - - // DUT name - // By default we use the translated name of the Verilog component. But you can change - // that by defining the VTB_TOP_MODULE_NAME macro through the simulator command line - // options (e.g., for VCS you can do +define+VTB_TOP_MODULE_NAME=YourTopModuleName). -`ifdef VTB_TOP_MODULE_NAME - `VTB_TOP_MODULE_NAME DUT -`else - MeshMultiCgraRTL__975ce70dc1a0740a DUT -`endif - ( - .clk(clk), - .reset(reset), - .recv_from_cpu_pkt__msg(recv_from_cpu_pkt__msg), - .recv_from_cpu_pkt__rdy(recv_from_cpu_pkt__rdy), - .recv_from_cpu_pkt__val(recv_from_cpu_pkt__val), - .send_to_cpu_pkt__msg(send_to_cpu_pkt__msg), - .send_to_cpu_pkt__rdy(send_to_cpu_pkt__rdy), - .send_to_cpu_pkt__val(send_to_cpu_pkt__val) - ); - - initial begin - assert(0 <= `VTB_INPUT_DELAY) - else $fatal("\n=====\n\nVTB_INPUT_DELAY should >= 0\n\n=====\n"); - - assert(`VTB_INPUT_DELAY < `VTB_OUTPUT_ASSERT_DELAY) - else $fatal("\n=====\n\nVTB_OUTPUT_ASSERT_DELAY should be larger than VTB_INPUT_DELAY\n\n=====\n"); - - assert(`VTB_OUTPUT_ASSERT_DELAY <= `CYCLE_TIME) - else $fatal("\n=====\n\nVTB_OUTPUT_ASSERT_DELAY should be smaller than or equal to CYCLE_TIME\n\n=====\n"); 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