{"payload":{"header_redesign_enabled":false,"results":[{"id":"60740568","archived":false,"color":"#DAE1C2","followers":0,"has_funding_file":false,"hl_name":"rpennell/Verilog","hl_trunc_description":"None","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":60740568,"name":"Verilog","owner_id":5760228,"owner_login":"rpennell","updated_at":"2016-06-10T06:39:34.049Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":60,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Arpennell%252FVerilog%2B%2Blanguage%253ASystemVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/rpennell/Verilog/star":{"post":"4Q3QFpiVzTU-6l1HTTyLlt75YajR2e0r7KXWRrHR8vElrVcg1OlDB-nvwX7UyIidXiRHIgJyudJhLoX-9rtDwA"},"/rpennell/Verilog/unstar":{"post":"jxXmtcVilnOYt0jN5OM5OhjLe8Yd7Mo0g8oAL52UGX7-E8AHqSEBgW36KU8mYfz4YGM7OjUVkDzkCHHl6E5pRA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"2yCg26ERyUu-3M6vWlIsktpKWAt_8q0hK95douwryXFtUqcGbEYVU-XKdhzApg_Y_6RAFtc1O7GWrJaS5g_L3A"}}},"title":"Repository search results"}