SPIMaster - can both CS lines be active? #548
Replies: 5 comments 1 reply
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No, unfortunately the SPI master peripheral does not allow to drive two CS
lines low at the same time.
Which assertion is it? I cannot see a problem in the source code of the
CSPIMaster class.
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Can I take full control of the lines with GPIO and use ChipSelectNone on the peripheral? It would solve it for me elegantly. I assumed assertion as the kernel stops with nChipSelect=2. Is there a way to log the assertion failure? I’m using the serial log, not the screen based. |
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Workable solution, thanks! Two small concerns:
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You are welcome.
BTW. It can also be an exception. Do you have the class |
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WriteAll() solved it - thanks Rene. |
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I need to drive 3 SPI devices, so I decoded the CE0 and CE1 with an LS139, to derive 3 chip select lines. Now I can use the 0, 1 and SPIMaster's ChipSelectNone to drive nChipSelect, and it all works well (except not getting any CS with ChipSelectNone). When I fuzz ChipSelectNone the kernel stops - I assume on an assertion. Is there any way to get the ARM SPI drive both CS lines low? If I try to directly manipulate the GPIO, the logic analyzer trace shows glitches all over the CS lines. The test board is a Raspberry Pi Model B R2.
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