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1 parent 2c99e80 commit aef25a4Copy full SHA for aef25a4
src/peripheral/dcb.rs
@@ -2,7 +2,7 @@
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use volatile_register::{RW, WO};
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-use crate::peripheral::DCB;
+use crate::peripheral::{DCB, DWT, ITM};
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use core::ptr;
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const DCB_DEMCR_TRCENA: u32 = 1 << 24;
@@ -22,10 +22,7 @@ pub struct RegisterBlock {
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}
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impl DCB {
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- /// Enables TRACE. This is for example required by the
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- /// `peripheral::DWT` cycle counter to work properly.
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- /// As by STM documentation, this flag is not reset on
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- /// soft-reset, only on power reset.
+ /// Global enable for all [`DWT`] and [`ITM`] features.
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///
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/// Note: vendor-specific registers may have to be set to completely
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/// enable tracing. For example, on the STM32F401RE, `TRACE_MODE`
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