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JackcuiiJackcuii
committed
fir-complete version
1 parent 1ccfaee commit 9cc8a99

36 files changed

Lines changed: 6304 additions & 103 deletions

‎api/driver.go‎

Lines changed: 22 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,12 @@ package api
33

44
import (
55
"fmt"
6+
"log/slog"
67

78
"github.com/sarchlab/akita/v4/sim"
89
"github.com/sarchlab/akita/v4/sim/directconnection"
910
"github.com/sarchlab/zeonica/cgra"
11+
"github.com/sarchlab/zeonica/core"
1012
)
1113

1214
// Driver provides the interface to control an accelerator.
@@ -63,10 +65,6 @@ type PerPEKernels map[[2]int]string
6365

6466
func (d *driverImpl) PreloadMemory(x int, y int, data uint32, baseAddr uint32) {
6567
tile := d.device.GetTile(x, y)
66-
// fmt.Printf(
67-
// "[DEBUG] PreloadMemory(x=%d, y=%d) -> Tile: %v\n",
68-
// x, y, tile,
69-
// )
7068
tile.WriteMemory(x, y, data, baseAddr)
7169
}
7270

@@ -136,11 +134,15 @@ func (d *driverImpl) doOneFeedInTask(task *feedInTask) bool {
136134
if err != nil {
137135
panic("CGRA cannot handle the data rate")
138136
}
139-
fmt.Printf("%10f, Feed in %d to %s\n",
140-
d.Engine.CurrentTime()*1e9,
141-
task.data[task.round*task.stride+i],
142-
task.remotePorts[i])
143137

138+
core.Trace("DataFlow",
139+
"Behavior", "FeedIn",
140+
slog.Float64("Time", float64(d.Engine.CurrentTime()*1e9)),
141+
"Data", task.data[task.round*task.stride+i],
142+
"Color", task.color,
143+
"From", port.Name(),
144+
"To", task.remotePorts[i],
145+
)
144146
madeProgress = true
145147
}
146148

@@ -166,9 +168,21 @@ func (d *driverImpl) doOneCollectTask(task *collectTask) bool {
166168
return false
167169
}
168170

171+
//fmt.Printf("\033[31mCollect Task: %v\033[0m\n", task)
172+
169173
for i, port := range task.ports {
170174
msg := port.RetrieveIncoming().(*cgra.MoveMsg)
171175
task.data[task.round*task.stride+i] = msg.Data
176+
// in red
177+
178+
core.Trace("DataFlow",
179+
"Behavior", "Collect",
180+
slog.Float64("Time", float64(d.Engine.CurrentTime()*1e9)),
181+
"Data", task.data[task.round*task.stride+i],
182+
"Color", task.color,
183+
"From", task.ports[i].Name(),
184+
"To", "None",
185+
)
172186
}
173187

174188
task.round++

‎cgra/cgra.go‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,14 @@ const (
1313
East
1414
South
1515
West
16+
NorthEast
17+
NorthWest
18+
SouthEast
19+
SouthWest
20+
Router
21+
Dummy1
22+
Dummy2
23+
Dummy3
1624
)
1725

1826
// Name returns the name of the side.
@@ -26,6 +34,22 @@ func (s Side) Name() string {
2634
return "South"
2735
case East:
2836
return "East"
37+
case NorthEast:
38+
return "NorthEast"
39+
case NorthWest:
40+
return "NorthWest"
41+
case SouthEast:
42+
return "SouthEast"
43+
case SouthWest:
44+
return "SouthWest"
45+
case Router:
46+
return "Router"
47+
case Dummy1:
48+
return "Dummy1"
49+
case Dummy2:
50+
return "Dummy2"
51+
case Dummy3:
52+
return "Dummy3"
2953
default:
3054
panic("invalid side")
3155
}

‎config/config.go‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,16 @@ func (d DeviceBuilder) connectTiles(dev *device) {
108108
southTile := dev.Tiles[y+1][x]
109109
d.connectTilePorts(currentTile, cgra.South, southTile, cgra.North)
110110
}
111+
// connect to the south east tile
112+
if y < d.height-1 && x < d.width-1 {
113+
southEastTile := dev.Tiles[y+1][x+1]
114+
d.connectTilePorts(currentTile, cgra.SouthEast, southEastTile, cgra.NorthWest)
115+
}
116+
// connect to the south west tile
117+
if y < d.height-1 && x > 0 {
118+
southWestTile := dev.Tiles[y+1][x-1]
119+
d.connectTilePorts(currentTile, cgra.SouthWest, southWestTile, cgra.NorthEast)
120+
}
111121
}
112122
}
113123
}

‎config/platform.go‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,16 @@ func (t tile) GetPort(side cgra.Side) sim.Port {
3232
return t.Core.GetPortByName("South")
3333
case cgra.East:
3434
return t.Core.GetPortByName("East")
35+
case cgra.NorthEast:
36+
return t.Core.GetPortByName("NorthEast")
37+
case cgra.SouthEast:
38+
return t.Core.GetPortByName("SouthEast")
39+
case cgra.SouthWest:
40+
return t.Core.GetPortByName("SouthWest")
41+
case cgra.NorthWest:
42+
return t.Core.GetPortByName("NorthWest")
43+
case cgra.Router:
44+
return t.Core.GetPortByName("Router")
3545
default:
3646
panic("invalid side")
3747
}

‎core/builder.go‎

Lines changed: 31 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -28,28 +28,55 @@ func (b Builder) Build(name string) *Core {
2828
c := &Core{}
2929

3030
c.TickingComponent = sim.NewTickingComponent(name, b.engine, b.freq, c)
31+
c.emu = instEmulator{
32+
CareFlags: true,
33+
}
3134
c.state = coreState{
35+
SelectedBlock: nil,
36+
PCInBlock: 0,
37+
Directions: map[string]bool{
38+
"North": true,
39+
"East": true,
40+
"South": true,
41+
"West": true,
42+
"NorthEast": true,
43+
"SouthEast": true,
44+
"SouthWest": true,
45+
"NorthWest": true,
46+
"Router": true,
47+
},
3248
Registers: make([]uint32, 64),
3349
Memory: make([]uint32, 1024),
3450
RecvBufHead: make([][]uint32, 4),
3551
RecvBufHeadReady: make([][]bool, 4),
3652
SendBufHead: make([][]uint32, 4),
3753
SendBufHeadBusy: make([][]bool, 4),
54+
States: make(map[string]interface{}),
3855
}
3956

4057
for i := 0; i < 4; i++ {
41-
c.state.RecvBufHead[i] = make([]uint32, 4)
42-
c.state.RecvBufHeadReady[i] = make([]bool, 4)
43-
c.state.SendBufHead[i] = make([]uint32, 4)
44-
c.state.SendBufHeadBusy[i] = make([]bool, 4)
58+
c.state.RecvBufHead[i] = make([]uint32, 12)
59+
c.state.RecvBufHeadReady[i] = make([]bool, 12)
60+
c.state.SendBufHead[i] = make([]uint32, 12)
61+
c.state.SendBufHeadBusy[i] = make([]bool, 12)
4562
}
4663

64+
c.state.States["Phiconst"] = false
65+
4766
c.ports = make(map[cgra.Side]*portPair)
4867

4968
b.makePort(c, cgra.North)
5069
b.makePort(c, cgra.West)
5170
b.makePort(c, cgra.South)
5271
b.makePort(c, cgra.East)
72+
b.makePort(c, cgra.NorthEast)
73+
b.makePort(c, cgra.SouthEast)
74+
b.makePort(c, cgra.SouthWest)
75+
b.makePort(c, cgra.NorthWest)
76+
b.makePort(c, cgra.Router)
77+
b.makePort(c, cgra.Dummy1)
78+
b.makePort(c, cgra.Dummy2)
79+
b.makePort(c, cgra.Dummy3)
5380

5481
return c
5582
}

‎core/core.go‎

Lines changed: 48 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ package core
22

33
import (
44
"fmt"
5+
"log/slog"
56

67
"github.com/sarchlab/akita/v4/sim"
78
"github.com/sarchlab/zeonica/cgra"
@@ -40,10 +41,18 @@ func (c *Core) GetMemory(x int, y int, addr uint32) uint32 {
4041

4142
// write memory
4243
func (c *Core) WriteMemory(x int, y int, data uint32, baseAddr uint32) {
43-
fmt.Printf("Core [%d][%d] receive WriteMemory(x=%d, y=%d)\n", c.state.TileX, c.state.TileY, x, y)
44+
//fmt.Printf("Core [%d][%d] receive WriteMemory(x=%d, y=%d)\n", c.state.TileX, c.state.TileY, x, y)
4445
if x == int(c.state.TileX) && y == int(c.state.TileY) {
4546
c.state.Memory[baseAddr] = data
46-
fmt.Printf("Core [%d][%d] write memory[%d] = %d\n", c.state.TileX, c.state.TileY, baseAddr, c.state.Memory[baseAddr])
47+
//fmt.Printf("Core [%d][%d] write memory[%d] = %d\n", c.state.TileX, c.state.TileY, baseAddr, c.state.Memory[baseAddr])
48+
Trace("Memory",
49+
"Behavior", "WriteMemory",
50+
"Time", float64(c.Engine.CurrentTime()*1e9),
51+
"Data", data,
52+
"X", x,
53+
"Y", y,
54+
"Addr", baseAddr,
55+
)
4756
} else {
4857
panic(fmt.Sprintf("Invalid Tile: Expect (%d, %d)，but get (%d, %d)", c.state.TileX, c.state.TileY, x, y))
4958
}
@@ -77,7 +86,7 @@ func (c *Core) Tick() (madeProgress bool) {
7786

7887
func (c *Core) doSend() bool {
7988
madeProgress := false
80-
for i := 0; i < 4; i++ {
89+
for i := 0; i < 12; i++ {
8190
for color := 0; color < 4; color++ {
8291

8392
if !c.state.SendBufHeadBusy[color][i] {
@@ -97,11 +106,14 @@ func (c *Core) doSend() bool {
97106
continue
98107
}
99108

100-
fmt.Printf("%10f, %s, Send %d %s->%s, Color %d\n",
101-
c.Engine.CurrentTime()*1e9,
102-
c.Name(),
103-
msg.Data, msg.Src, msg.Dst,
104-
color)
109+
Trace("DataFlow",
110+
"Behavior", "Send",
111+
slog.Float64("Time", float64(c.Engine.CurrentTime()*1e9)),
112+
"Data", msg.Data,
113+
"Color", color,
114+
"Src", msg.Src,
115+
"Dst", msg.Dst,
116+
)
105117
c.state.SendBufHeadBusy[color][i] = false
106118
}
107119
}
@@ -111,7 +123,7 @@ func (c *Core) doSend() bool {
111123

112124
func (c *Core) doRecv() bool {
113125
madeProgress := false
114-
for i := 0; i < 4; i++ { //direction
126+
for i := 0; i < 12; i++ { //direction
115127
item := c.ports[cgra.Side(i)].local.PeekIncoming()
116128
if item == nil {
117129
continue
@@ -137,11 +149,14 @@ func (c *Core) doRecv() bool {
137149
c.state.RecvBufHeadReady[color][i] = true
138150
c.state.RecvBufHead[color][i] = msg.Data
139151

140-
fmt.Printf("%10f, %s, Recv %d %s->%s, Color %d\n",
141-
c.Engine.CurrentTime()*1e9,
142-
c.Name(),
143-
msg.Data, msg.Src, msg.Dst,
144-
color)
152+
Trace("DataFlow",
153+
"Behavior", "Recv",
154+
"Time", float64(c.Engine.CurrentTime()*1e9),
155+
"Data", msg.Data,
156+
"Src", msg.Src,
157+
"Dst", msg.Dst,
158+
"Color", color,
159+
)
145160

146161
c.ports[cgra.Side(i)].local.RetrieveIncoming()
147162
madeProgress = true
@@ -158,7 +173,7 @@ func (c *Core) runProgram() bool {
158173
}
159174
combInst := c.state.SelectedBlock.CombinedInsts[c.state.PCInBlock]
160175

161-
fmt.Printf("%10f, %s, inst: %v inst_length: %d\n", c.Engine.CurrentTime()*1e9, c.Name(), combInst, len(combInst.Insts))
176+
//fmt.Printf("%10f, %s, inst: %v inst_length: %d\n", c.Engine.CurrentTime()*1e9, c.Name(), combInst, len(combInst.Insts))
162177

163178
/* do not have label in codes
164179
for inst[len(inst)-1] == ':' {
@@ -174,7 +189,12 @@ func (c *Core) runProgram() bool {
174189
if prevPC == nextPC {
175190
return false
176191
}
177-
fmt.Printf("%10f, %s, Inst %v\n", c.Engine.CurrentTime()*1e9, c.Name(), combInst)
192+
Trace("Inst",
193+
"Time", float64(c.Engine.CurrentTime()*1e9),
194+
"X", c.state.TileX,
195+
"Y", c.state.TileY,
196+
"CombinedInst", combInst.String(),
197+
)
178198
//debug reg value
179199
//fmt.Printf("Core (%d, %d) Register values:\n", c.state.TileX, c.state.TileY)
180200
// for i, val := range c.state.Registers {
@@ -269,7 +289,7 @@ func (c *Core) Router(dst string, src string, color string) bool {
269289
c.state.SendBufHeadBusy[colorIndex][dstIndex] = true
270290
c.state.SendBufHead[colorIndex][dstIndex] = c.state.RecvBufHead[colorIndex][srcIndex]
271291
fmt.Printf("%10f, %s, ROUTER %d %s->%s\n",
272-
c.Engine.CurrentTime()*1e9,
292+
float64(c.Engine.CurrentTime()*1e9),
273293
c.Name(),
274294
c.state.RecvBufHead[colorIndex][srcIndex], c.Name(), dst)
275295
return true
@@ -282,7 +302,7 @@ func (c *Core) ConditionSend(dst string, src string, resister int, srcColor int,
282302
}
283303

284304
func (c *Core) RouterSrcMustBeDirection(src string) {
285-
arr := []string{"NORTH", "SOUTH", "WEST", "EAST"}
305+
arr := []string{"NORTH", "SOUTH", "WEST", "EAST", "SOUTHWEST", "SOUTHEAST", "NORTHWEST", "NORTHEAST", "ROUTER"}
286306
res := false
287307
for _, s := range arr {
288308
if s == src {
@@ -308,6 +328,16 @@ func (c *Core) getIndex(side string) int {
308328
srcIndex = int(cgra.South)
309329
case "EAST":
310330
srcIndex = int(cgra.East)
331+
case "NORTHEAST":
332+
srcIndex = int(cgra.NorthEast)
333+
case "NORTHWEST":
334+
srcIndex = int(cgra.NorthWest)
335+
case "SOUTHEAST":
336+
srcIndex = int(cgra.SouthEast)
337+
case "SOUTHWEST":
338+
srcIndex = int(cgra.SouthWest)
339+
case "ROUTER":
340+
srcIndex = int(cgra.Router)
311341
// Adding new direction
312342
default:
313343
panic("invalid side")

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