From ce9707c8147518a817e919d3047d9a428a4513c5 Mon Sep 17 00:00:00 2001
From: Saurabh Singh <saurabh.s99100@gmail.com>
Date: Tue, 20 Jul 2021 08:23:02 +0530
Subject: [PATCH 1/6] Fix: Wrong Memory Access Protocol.

Atom earlier used a wrong memory access protocol whereby a
word/half-word/byte access can be made at any address and there was
no constaint for alignment. This however never resulted in any issues
because the memory was simulated in such a way in Cpp (AtomBones).
This is fixed in this commit.

passing riscv-arch-tests

Other changes:
- Add gtkwv save files.
- default trace file using --trace CLI option : build/trace/trace.vcd
- add more scar tests
- remove scar test numberings
- separate linker script for scar
---
 Makefile                                      |   1 +
 Trace_AtomBones.gtkw                          |  70 +++++++++
 Trace_HydrogenSoC.gtkw                        |  84 +++++++++++
 a.elf                                         | Bin 0 -> 9376 bytes
 rtl/core/AtomRV.v                             | 140 ++++++++++++++----
 sim/AtomSim.cpp                               |   4 +-
 sim/Backend_AtomBones.hpp                     |  39 ++---
 t1.s                                          |  56 +++++++
 test/scar/{t7_add.S => add.S}                 |   0
 test/scar/{t8_addi.S => addi.S}               |   0
 test/scar/{t10_and.S => and.S}                |   0
 test/scar/{t11_andi.S => andi.S}              |   0
 test/scar/auipc.S                             |  24 ++-
 test/scar/beq.S                               |  67 ++++++++-
 test/scar/bge.S                               |  67 ++++++++-
 test/scar/jal.S                               |   2 +-
 test/scar/{t1_li.S => li.S}                   |   0
 test/scar/link.ld                             |  58 ++++++++
 ...t3_load_store_byte.S => load_store_byte.S} |   0
 .../{t4_load_store_hw.S => load_store_hw.S}   |  26 ++--
 test/scar/{t6_lui.S => lui.S}                 |   0
 test/scar/lw.S                                |  70 +++++++++
 test/scar/{t2_mv.S => mv.S}                   |   0
 test/scar/{t12_or.S => or.S}                  |   0
 test/scar/{t13_ori.S => ori.S}                |   0
 test/scar/scar.py                             |   2 +-
 test/scar/{t17_sll.S => sll.S}                |   0
 test/scar/{t18_slli.S => slli.S}              |   0
 test/scar/{t19_srl.S => slt.S}                |   0
 test/scar/{t20_srli.S => slti.S}              |   0
 test/scar/{t21_sra.S => sltiu.S}              |   0
 test/scar/{t22_srai.S => sltu.S}              |   0
 test/scar/{t23_slt.S => sra.S}                |   0
 test/scar/{t24_slti.S => srai.S}              |   0
 test/scar/{t25_sltu.S => srl.S}               |   0
 test/scar/{t26_sltiu.S => srli.S}             |   0
 test/scar/{t5_storew.S => storew.S}           |   0
 test/scar/{t9_sub.S => sub.S}                 |   0
 test/scar/sw.S                                | 113 ++++++++++++++
 test/scar/{t15_xor.S => xor.S}                |   0
 test/scar/{t16_xori.S => xori.S}              |   0
 41 files changed, 757 insertions(+), 66 deletions(-)
 create mode 100644 Trace_AtomBones.gtkw
 create mode 100644 Trace_HydrogenSoC.gtkw
 create mode 100755 a.elf
 create mode 100644 t1.s
 rename test/scar/{t7_add.S => add.S} (100%)
 rename test/scar/{t8_addi.S => addi.S} (100%)
 rename test/scar/{t10_and.S => and.S} (100%)
 rename test/scar/{t11_andi.S => andi.S} (100%)
 rename test/scar/{t1_li.S => li.S} (100%)
 create mode 100644 test/scar/link.ld
 rename test/scar/{t3_load_store_byte.S => load_store_byte.S} (100%)
 rename test/scar/{t4_load_store_hw.S => load_store_hw.S} (72%)
 rename test/scar/{t6_lui.S => lui.S} (100%)
 create mode 100644 test/scar/lw.S
 rename test/scar/{t2_mv.S => mv.S} (100%)
 rename test/scar/{t12_or.S => or.S} (100%)
 rename test/scar/{t13_ori.S => ori.S} (100%)
 rename test/scar/{t17_sll.S => sll.S} (100%)
 rename test/scar/{t18_slli.S => slli.S} (100%)
 rename test/scar/{t19_srl.S => slt.S} (100%)
 rename test/scar/{t20_srli.S => slti.S} (100%)
 rename test/scar/{t21_sra.S => sltiu.S} (100%)
 rename test/scar/{t22_srai.S => sltu.S} (100%)
 rename test/scar/{t23_slt.S => sra.S} (100%)
 rename test/scar/{t24_slti.S => srai.S} (100%)
 rename test/scar/{t25_sltu.S => srl.S} (100%)
 rename test/scar/{t26_sltiu.S => srli.S} (100%)
 rename test/scar/{t5_storew.S => storew.S} (100%)
 rename test/scar/{t9_sub.S => sub.S} (100%)
 create mode 100644 test/scar/sw.S
 rename test/scar/{t15_xor.S => xor.S} (100%)
 rename test/scar/{t16_xori.S => xori.S} (100%)

diff --git a/Makefile b/Makefile
index f5b70007..9f902ffd 100644
--- a/Makefile
+++ b/Makefile
@@ -175,6 +175,7 @@ $(bin_dir)/$(sim_executable): $(vobject_dir)/V$(verilog_topmodule)__ALLcls.o $(v
 #~	scar		:	verify using scar
 .PHONY: scar
 scar: $(bin_dir)/$(sim_executable)
+	@echo ">> Running SCAR"
 	cd test/scar/ && make
 
 
diff --git a/Trace_AtomBones.gtkw b/Trace_AtomBones.gtkw
new file mode 100644
index 00000000..ed87198f
--- /dev/null
+++ b/Trace_AtomBones.gtkw
@@ -0,0 +1,70 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Mon Jul 19 21:11:30 2021
+[*]
+[dumpfile] "/home/frozenalpha/git/riscv/riscv-atom/build/trace/trace.vcd"
+[dumpfile_mtime] "Mon Jul 19 20:03:50 2021"
+[dumpfile_size] 22256
+[savefile] "/home/frozenalpha/git/riscv/riscv-atom/Trace_AtomBones.gtkw"
+[timestart] 184
+[size] 1600 871
+[pos] -1 -1
+*-3.759334 563 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] TOP.
+[treeopen] TOP.AtomBones.
+[treeopen] TOP.AtomBones.atom_core.
+[sst_width] 212
+[signals_width] 230
+[sst_expanded] 1
+[sst_vpaned_height] 238
+@29
+[color] 1
+TOP.clk_i
+[color] 1
+TOP.rst_i
+@200
+-IBUS
+@22
+[color] 2
+TOP.imem_addr_o[31:0]
+@28
+[color] 2
+TOP.dmem_valid_o
+@22
+[color] 2
+TOP.imem_data_i[31:0]
+@28
+[color] 2
+TOP.imem_ack_i
+@200
+-DBUS
+@22
+[color] 3
+TOP.dmem_addr_o[31:0]
+[color] 3
+TOP.dmem_data_o[31:0]
+[color] 3
+TOP.dmem_sel_o[3:0]
+@28
+[color] 3
+TOP.dmem_we_o
+[color] 3
+TOP.dmem_valid_o
+@22
+[color] 3
+TOP.dmem_data_i[31:0]
+@28
+[color] 3
+TOP.dmem_ack_i
+@200
+-CORE
+@22
+TOP.AtomBones.atom_core.ProgramCounter[31:0]
+TOP.AtomBones.atom_core.ProgramCounter_Old[31:0]
+TOP.AtomBones.atom_core.InstructionRegister[31:0]
+@28
+TOP.AtomBones.atom_core.stall_stage1
+TOP.AtomBones.atom_core.stall_stage2
+TOP.AtomBones.atom_core.insert_bubble
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/Trace_HydrogenSoC.gtkw b/Trace_HydrogenSoC.gtkw
new file mode 100644
index 00000000..9125f90f
--- /dev/null
+++ b/Trace_HydrogenSoC.gtkw
@@ -0,0 +1,84 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Mon Jul 19 21:10:43 2021
+[*]
+[dumpfile] "/home/frozenalpha/git/riscv/riscv-atom/build/trace/trace.vcd"
+[dumpfile_mtime] "Mon Jul 19 20:03:50 2021"
+[dumpfile_size] 22256
+[savefile] "/home/frozenalpha/git/riscv/riscv-atom/Trace_HydrogenSoC.gtkw"
+[timestart] 569
+[size] 1600 871
+[pos] -1 -1
+*-3.848547 624 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] TOP.
+[treeopen] TOP.HydrogenSoC.
+[treeopen] TOP.HydrogenSoC.atom_wb_core.
+[treeopen] TOP.HydrogenSoC.atom_wb_core.atom_core.
+[sst_width] 212
+[signals_width] 230
+[sst_expanded] 1
+[sst_vpaned_height] 238
+@28
+[color] 1
+TOP.rst_i
+[color] 1
+TOP.clk_i
+@200
+-IBUS
+@22
+[color] 2
+TOP.HydrogenSoC.wb_ibus_adr_o[31:0]
+@28
+[color] 2
+TOP.HydrogenSoC.wb_ibus_stb_o
+@22
+[color] 2
+TOP.HydrogenSoC.wb_ibus_dat_i[31:0]
+@28
+[color] 2
+TOP.HydrogenSoC.wb_ibus_ack_i
+TOP.HydrogenSoC.atom_wb_core.atom_core.imem_handshake
+@200
+-DBUS
+@22
+[color] 3
+TOP.HydrogenSoC.wb_dbus_adr_o[31:0]
+@28
+[color] 3
+TOP.HydrogenSoC.wb_dbus_stb_o
+@22
+[color] 3
+TOP.HydrogenSoC.wb_dbus_sel_o[3:0]
+@28
+[color] 3
+TOP.HydrogenSoC.wb_dbus_we_o
+@22
+[color] 3
+TOP.HydrogenSoC.wb_dbus_dat_o[31:0]
+[color] 3
+TOP.HydrogenSoC.wb_dbus_dat_i[31:0]
+@28
+[color] 3
+TOP.HydrogenSoC.wb_dbus_ack_i
+TOP.HydrogenSoC.atom_wb_core.atom_core.dmem_handshake
+@200
+-CORE
+@22
+TOP.HydrogenSoC.atom_wb_core.atom_core.ProgramCounter[31:0]
+TOP.HydrogenSoC.atom_wb_core.atom_core.ProgramCounter_Old[31:0]
+TOP.HydrogenSoC.atom_wb_core.atom_core.InstructionRegister[31:0]
+@28
+TOP.HydrogenSoC.atom_wb_core.atom_core.ignore_imem_handshake
+TOP.HydrogenSoC.atom_wb_core.atom_core.jump_decision
+TOP.HydrogenSoC.atom_wb_core.atom_core.stall_stage1
+TOP.HydrogenSoC.atom_wb_core.atom_core.stall_stage2
+TOP.HydrogenSoC.atom_wb_core.atom_core.insert_bubble
+TOP.HydrogenSoC.atom_wb_core.atom_core.d_rf_we
+TOP.HydrogenSoC.atom_wb_core.atom_core.rf.Data_We_i
+TOP.HydrogenSoC.atom_wb_core.atom_core.d_rf_din_sel[2:0]
+@22
+TOP.HydrogenSoC.atom_wb_core.atom_core.rf.Data_i[31:0]
+TOP.HydrogenSoC.atom_wb_core.atom_core.rf.regs(3)[31:0]
+TOP.HydrogenSoC.atom_wb_core.atom_core.rf.regs(5)[31:0]
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/a.elf b/a.elf
new file mode 100755
index 0000000000000000000000000000000000000000..1ca4a94b62ae03dd88fcff76cd63305ecdfaff72
GIT binary patch
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diff --git a/rtl/core/AtomRV.v b/rtl/core/AtomRV.v
index cba66a16..11957552 100644
--- a/rtl/core/AtomRV.v
+++ b/rtl/core/AtomRV.v
@@ -41,7 +41,7 @@ module AtomRV
     // ========== DMEM Port ==========
     output  wire    [31:0]  dmem_addr_o,    // DMEM address
     input   wire    [31:0]  dmem_data_i,    // DMEM data in
-    output  wire    [31:0]  dmem_data_o,    // DMEM data out
+    output  reg     [31:0]  dmem_data_o,    // DMEM data out
     output  reg      [3:0]  dmem_sel_o,     // DMEM Select
     output  wire            dmem_we_o,      // DMEM Strobe
 
@@ -201,26 +201,6 @@ Decode decode
 );
 
 
-/*
-    ////// MEM_LOAD //////
-    Memload is used to chop down the input 32 bit data into signed/unsigned 
-    bytes and words fo loading into the registe file.
-*/
-reg [31:0] memload;
-
-always @(*) /* COMBINATORIAL */
-begin
-    case(d_mem_access_width)
-        3'b000:   memload = {{24{dmem_data_i[7]}}, dmem_data_i[7:0]};     // LB
-        3'b001:   memload = {{16{dmem_data_i[15]}}, dmem_data_i[15:0]};   // LH
-        3'b010:   memload = dmem_data_i;                            // LW
-        3'b100:   memload = {{24{1'b0}}, dmem_data_i[7:0]};         // LBU
-        3'b101:   memload = {{16{1'b0}}, dmem_data_i[15:0]};        // LHU
-
-        default: memload = 32'd0;
-    endcase 
-end
-
 
 /*
     ////// Regster File //////
@@ -309,24 +289,120 @@ end
 /*
     DATA MEMORY ACCESS
 */
-assign dmem_addr_o = alu_out;
-assign dmem_data_o = rf_rs2;
+wire [31:0] dmem_address = alu_out;
+wire [31:0] dmem_data_out = rf_rs2;
+
+assign dmem_addr_o = dmem_address & 32'hfffffffc; // word aligned accesses
+assign dmem_valid_o = d_mem_load_store;
 assign dmem_we_o = d_mem_we;
 
 wire dmem_handshake = dmem_ack_i & dmem_valid_o;
 wire stall_stage2 = !dmem_handshake & dmem_valid_o;
 
-// Setting the strobe_o signal
-always @(*) begin
-    case({d_mem_access_width[1:0], d_mem_we})
-        3'b00_1: dmem_sel_o = 4'b0001;   // Store byte
-        3'b01_1: dmem_sel_o = 4'b0011;   // Store Half Word
-        3'b10_1: dmem_sel_o = 4'b1111;   // Store Word
+/////////////////////////////////
+// READ
 
-        default: dmem_sel_o = 4'b1111;   // Load (Byte/HWord/Word)
-    endcase
+/*
+    ////// MEM_LOAD //////
+*/
+reg [31:0] memload;
+
+always @(*) /* COMBINATORIAL */
+begin
+    case(d_mem_access_width[1:0])
+        2'b00:  begin   // Load Byte
+                    case(dmem_address[1:0])
+                        2'b00:  memload = {{24{d_mem_access_width[2] ? 1'b0 : dmem_data_i[7]}},  dmem_data_i[7:0]};
+                        2'b01:  memload = {{24{d_mem_access_width[2] ? 1'b0 : dmem_data_i[15]}}, dmem_data_i[15:8]};
+                        2'b10:  memload = {{24{d_mem_access_width[2] ? 1'b0 : dmem_data_i[23]}}, dmem_data_i[23:16]};
+                        2'b11:  memload = {{24{d_mem_access_width[2] ? 1'b0 : dmem_data_i[31]}}, dmem_data_i[31:24]};
+                    endcase
+                end
+
+        2'b01:  begin   // Load Half Word
+                    case(dmem_address[1])
+                        1'b0:  memload = {{16{d_mem_access_width[2] ? 1'b0 : dmem_data_i[15]}}, dmem_data_i[15:0]};
+                        1'b1:  memload = {{16{d_mem_access_width[2] ? 1'b0 : dmem_data_i[31]}}, dmem_data_i[31:16]};
+                    endcase
+                end
+        
+        2'b10:  begin   // Load Word
+                    memload = dmem_data_i;
+                end
+        
+
+
+        
+        /*memload = {{24{dmem_data_i[7]}}, dmem_data_i[7:0]};     // LB
+        3'b001:   memload = {{16{dmem_data_i[15]}}, dmem_data_i[15:0]};   // LH
+        3'b010:   memload = dmem_data_i;                            // LW
+        3'b100:   memload = {{24{1'b0}}, dmem_data_i[7:0]};         // LBU
+        3'b101:   memload = {{16{1'b0}}, dmem_data_i[15:0]};        // LHU
+*/
+        default: memload = 32'h00000000;
+    endcase 
 end
 
-assign dmem_valid_o = d_mem_load_store;
+////////////////////////////////
+// WRITE
+
+// Setting the sel_o signal
+always @(*) begin /* COMBINATORIAL */
+    if (d_mem_we) begin
+        case(d_mem_access_width[1:0])
+            2'b00:  begin // Store byte
+                        case(dmem_address[1:0])
+                            2'b00:  dmem_sel_o = 4'b0001;
+                            2'b01:  dmem_sel_o = 4'b0010;
+                            2'b10:  dmem_sel_o = 4'b0100;
+                            2'b11:  dmem_sel_o = 4'b1000;
+                        endcase
+                    end
+            
+            2'b01:  begin // Store Half Word
+                        case(dmem_address[1])
+                            1'b0:  dmem_sel_o = 4'b0011;
+                            1'b1:  dmem_sel_o = 4'b1100;
+                        endcase
+                    end
+
+            2'b10: dmem_sel_o = 4'b1111;   // Store Word
+
+            default: dmem_sel_o = 4'b1111;
+        endcase
+    end
+    else
+        dmem_sel_o = 4'b1111;   // Load (Byte/HWord/Word)
+end
+
+
+// Setting the data_o signal
+always @(*) begin /* COMBINATORIAL */
+    if (d_mem_we) begin
+        case(d_mem_access_width[1:0])
+            2'b00:  begin // Store byte
+                        case(dmem_address[1:0])
+                            2'b00:  dmem_data_o = { {24{1'b0}}, dmem_data_out[7:0] };
+                            2'b01:  dmem_data_o = { {16{1'b0}}, dmem_data_out[7:0], {8{1'b0}} };
+                            2'b10:  dmem_data_o = { {8{1'b0}} , dmem_data_out[7:0], {16{1'b0}} };
+                            2'b11:  dmem_data_o = { dmem_data_out[7:0], {24{1'b0}} };
+                        endcase
+                    end
+            
+            2'b01:  begin // Store Half Word
+                        case(dmem_address[1])
+                            1'b0:  dmem_data_o = { {16{1'b0}}, dmem_data_out[15:0] };
+                            1'b1:  dmem_data_o = { dmem_data_out[15:0], {16{1'b0}} };
+                        endcase
+                    end
+
+            2'b10: dmem_data_o = dmem_data_out;   // Store Word
+
+            default: dmem_data_o = dmem_data_out;
+        endcase
+    end
+    else
+        dmem_data_o = 32'h00000000;   // Load (Byte/HWord/Word)
+end
 
 endmodule
\ No newline at end of file
diff --git a/sim/AtomSim.cpp b/sim/AtomSim.cpp
index c531dce6..4b6fd9fd 100644
--- a/sim/AtomSim.cpp
+++ b/sim/AtomSim.cpp
@@ -88,7 +88,7 @@ const std::string AtomSimBackend = "AtomBones";
 Backend_AtomBones *bkend;		
 
 // Default mem size for atomBones
-const unsigned long int default_mem_size = 134217728 + 3;	// 128MB (Code & Data) + 3 Bytes (Serial IO)
+const unsigned long int default_mem_size = 134217728 + 3 + 1;	// 128MB (Code & Data) + 3 Bytes (Serial IO) + 1 (To make word access possible)
 unsigned long int mem_size = default_mem_size;
 #endif
 
@@ -253,7 +253,7 @@ int main(int argc, char **argv)
 
 	if(trace_enabled == true)
 	{
-		std::string tracefile = trace_dir;
+		std::string tracefile = trace_dir+"/trace.vcd";
 		bkend->tb->openTrace(tracefile.c_str());
 		std::cout << "Trace enabled : \"" << tracefile << "\" opened for output.\n";
 		trace_enabled = true;
diff --git a/sim/Backend_AtomBones.hpp b/sim/Backend_AtomBones.hpp
index 32d339fb..edc6bb10 100644
--- a/sim/Backend_AtomBones.hpp
+++ b/sim/Backend_AtomBones.hpp
@@ -309,29 +309,34 @@ class Backend_AtomBones: public Backend<VAtomBones>
 		tb->m_core->imem_ack_i = 0;
 		tb->m_core->dmem_ack_i = 0;
 
-		// Imem Port Reads
+		// ===== Imem Port Reads =====
+		uint32_t iaddr = tb->m_core->imem_addr_o & 0xfffffffc;
 		if(tb->m_core->imem_valid_o == 1)
-		{	
-			tb->m_core->imem_data_i = mem->fetchWord(tb->m_core->imem_addr_o);
+		{
+			tb->m_core->imem_data_i = mem->fetchWord(iaddr);
 			tb->m_core->imem_ack_i = 1;
 		}
 
-		// Dmem Port Reads/Writes
-		if(tb->m_core->dmem_valid_o && !tb->m_core->dmem_we_o)	// Load instruction
-		{
-			tb->m_core->dmem_data_i = mem->fetchWord(tb->m_core->dmem_addr_o);
-			tb->m_core->dmem_ack_i = 1;
-		}
-		else if(tb->m_core->dmem_valid_o && tb->m_core->dmem_we_o)	// Store instruction
+		// ===== Dmem Port Reads/Writes =====
+		uint32_t daddr = tb->m_core->dmem_addr_o & 0xfffffffc;
+		if(tb->m_core->dmem_valid_o)
 		{
-			switch(tb->m_core->dmem_sel_o)
+			if(tb->m_core->dmem_we_o)	// Writes
+			{
+				// Writes are selective
+				if(tb->m_core->dmem_sel_o & 0b0001)
+					mem->storeWord(daddr, (mem->fetchWord(daddr) & 0xffffff00) | (tb->m_core->dmem_data_o & 0x000000ff));
+				if(tb->m_core->dmem_sel_o & 0b0010)
+					mem->storeWord(daddr, (mem->fetchWord(daddr) & 0xffff00ff) | (tb->m_core->dmem_data_o & 0x0000ff00));
+				if(tb->m_core->dmem_sel_o & 0b0100)
+					mem->storeWord(daddr, (mem->fetchWord(daddr) & 0xff00ffff) | (tb->m_core->dmem_data_o & 0x00ff0000));
+				if(tb->m_core->dmem_sel_o & 0b1000)
+					mem->storeWord(daddr, (mem->fetchWord(daddr) & 0x00ffffff) | (tb->m_core->dmem_data_o & 0xff000000));		
+			}
+			else	// Reads
 			{
-				case 0x1:	mem->storeByte(tb->m_core->dmem_addr_o, (uint8_t)tb->m_core->dmem_data_o);	break;
-				case 0x3:	mem->storeHalfWord(tb->m_core->dmem_addr_o, (uint16_t)tb->m_core->dmem_data_o);	break;
-				case 0xf:	mem->storeWord(tb->m_core->dmem_addr_o, (uint32_t)tb->m_core->dmem_data_o); break;
-				default: 
-					std::cout << std::hex << (int)tb->m_core->dmem_sel_o << std::endl;
-					throwError("RTL", "signal 'dmem_sel_o' has unexpected value");
+				// Read will always result in a fetch word at word boundry just before the address.
+				tb->m_core->dmem_data_i = mem->fetchWord(daddr);
 			}
 			tb->m_core->dmem_ack_i = 1;
 		}
diff --git a/t1.s b/t1.s
new file mode 100644
index 00000000..72e85407
--- /dev/null
+++ b/t1.s
@@ -0,0 +1,56 @@
+.global main
+
+.text
+main:
+    la x1, var1
+    lw x1, 0(x1)
+
+    la x2, var2
+    lw x2, 0(x2)
+
+    la x3, var3
+    lw x3, 0(x3)
+
+    la x4, var4
+    lw x4, 0(x4)
+
+    la x5, var5
+    lw x5, 0(x5)
+
+    la x6, var6
+    lw x6, 0(x6)
+
+    la x7, var7
+    lw x7, 0(x7)
+
+    la x8, var8
+    lw x8, 0(x8)
+
+    la x9, var9
+    lw x9, 0(x9)
+
+    la x10, var10
+    lw x10, 0(x10)
+
+    la x11, var11
+    lw x11, 0(x11)
+
+    la x12, var12
+    lw x12, 0(x12)
+
+    ebreak
+
+
+.data
+var1:   .word 0x12345678
+var2:   .word 0x00002020
+var3:   .word 0xf3232532
+var4:   .word 0xdea14245
+var5:   .word 0xdea12cad
+var6:   .word 0xdacadaca
+var7:   .word 0xbeefdead
+var8:   .word 0xdeadbeef
+var9:   .word 0x1beefbee
+var10:   .word 0x12deadbe
+var11:   .word 0x123deadb
+var12:   .word 0x1234dead
\ No newline at end of file
diff --git a/test/scar/t7_add.S b/test/scar/add.S
similarity index 100%
rename from test/scar/t7_add.S
rename to test/scar/add.S
diff --git a/test/scar/t8_addi.S b/test/scar/addi.S
similarity index 100%
rename from test/scar/t8_addi.S
rename to test/scar/addi.S
diff --git a/test/scar/t10_and.S b/test/scar/and.S
similarity index 100%
rename from test/scar/t10_and.S
rename to test/scar/and.S
diff --git a/test/scar/t11_andi.S b/test/scar/andi.S
similarity index 100%
rename from test/scar/t11_andi.S
rename to test/scar/andi.S
diff --git a/test/scar/auipc.S b/test/scar/auipc.S
index 8d1c8b69..762ca3fa 100644
--- a/test/scar/auipc.S
+++ b/test/scar/auipc.S
@@ -1 +1,23 @@
- 
+.global _start
+_start:
+
+auipc x1, 0x00000433
+auipc x2, 0x00000a44
+auipc x3, 0x0000032d
+auipc x4, 0x00000010
+auipc x5, 0x00000004
+auipc x6, 0x0000046b
+auipc x7, 0x00000301
+auipc x8, 0x00000128
+
+ebreak
+
+# $-ASSERTIONS-$
+# eq x1 0x00433000
+# eq x2 0x00a44004
+# eq x3 0x0032d008
+# eq x4 0x0001000c
+# eq x5 0x00004010
+# eq x6 0x0046b014
+# eq x7 0x00301018
+# eq x8 0x0012801c
diff --git a/test/scar/beq.S b/test/scar/beq.S
index 8d1c8b69..d545d253 100644
--- a/test/scar/beq.S
+++ b/test/scar/beq.S
@@ -1 +1,66 @@
- 
+.global _start
+_start:
+# --------------------
+    li x1, 55
+    li x2, 55
+
+    beq x1,x2,L1
+    ebreak
+L1:
+    li x10, 0x00000001
+
+# --------------------
+    li x1, 51
+    li x2, -45
+
+    beq x1,x2,exit
+    li x11, 0x00000002
+
+# --------------------
+    li x1, -32
+    li x2, -32
+
+    beq x1,x2,L2
+    ebreak
+L2:
+    li x12, 0x00000003
+
+# --------------------
+    li x1, 0
+    li x2, -4
+
+    beq x1,x2,exit
+    li x13, 0x00000004
+
+# --------------------
+    li x1, 0
+    li x2, 0
+
+    beq x1,x2,L3
+    ebreak
+L3:
+    li x14, 0x00000005
+
+# --------------------
+    li x1, 0xdeadbeef
+    li x2, 0xdeafbeef
+
+    beq x1,x2,exit
+    li x15, 0x00000006
+
+
+
+exit:
+    ebreak
+
+
+ebreak
+
+# $-ASSERTIONS-$
+# eq x10 0x00000001
+# eq x11 0x00000002
+# eq x12 0x00000003
+# eq x13 0x00000004
+# eq x14 0x00000005
+# eq x15 0x00000006
+
diff --git a/test/scar/bge.S b/test/scar/bge.S
index 8d1c8b69..87fdd070 100644
--- a/test/scar/bge.S
+++ b/test/scar/bge.S
@@ -1 +1,66 @@
- 
+.global _start
+_start:
+# --------------------
+    li x1, 5
+    li x2, 0
+
+    bge x1,x2,L1
+    ebreak
+L1:
+    li x10, 0x00000001
+
+# --------------------
+    li x1, -4
+    li x2, 5
+
+    bge x1,x2,exit
+    li x11, 0x00000002
+
+# --------------------
+    li x1, -2
+    li x2, -3
+
+    bge x1,x2,L2
+    ebreak
+L2:
+    li x12, 0x00000003
+
+# --------------------
+    li x1, -4
+    li x2, 0
+
+    bge x1,x2,exit
+    li x13, 0x00000004
+
+# --------------------
+    li x1, 0
+    li x2, 0
+
+    bge x1,x2,L3
+    ebreak
+L3:
+    li x14, 0x00000005
+
+# --------------------
+    li x1, 0x40
+    li x2, 0x100
+
+    bge x1,x2,exit
+    li x15, 0x00000006
+
+
+
+exit:
+    ebreak
+
+
+ebreak
+
+# $-ASSERTIONS-$
+# eq x10 0x00000001
+# eq x11 0x00000002
+# eq x12 0x00000003
+# eq x13 0x00000004
+# eq x14 0x00000005
+# eq x15 0x00000006
+
diff --git a/test/scar/jal.S b/test/scar/jal.S
index 8d1c8b69..0519ecba 100644
--- a/test/scar/jal.S
+++ b/test/scar/jal.S
@@ -1 +1 @@
- 
+ 
\ No newline at end of file
diff --git a/test/scar/t1_li.S b/test/scar/li.S
similarity index 100%
rename from test/scar/t1_li.S
rename to test/scar/li.S
diff --git a/test/scar/link.ld b/test/scar/link.ld
new file mode 100644
index 00000000..a36b1ace
--- /dev/null
+++ b/test/scar/link.ld
@@ -0,0 +1,58 @@
+/*
+    SCAR LINKER SCRIPT
+
+    @See : https://sourceware.org/binutils/docs/ld/Basic-Script-Concepts.html
+    @See : https://interrupt.memfault.com/blog/how-to-write-linker-scripts-for-firmware
+*/
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+/* MEMORY LAYOUT */
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x00000000, LENGTH = 64M    /* 64 kb @ 0x0*/
+    RAM (rwx): ORIGIN = 0x04000000, LENGTH = 64M    /* 16 kb @ 0x10000 (65536)*/
+}
+
+SECTIONS
+{
+    /* ==== ROM ==== */
+    .text : 
+    {
+        *(.text)            /* Load all text sections (from all files) */
+        *(.rodata)
+
+        . = ALIGN(4);
+        _etext = .;
+    } > ROM
+
+
+
+    /* ==== RAM ==== */
+    /* The .data section contains static variables which have an initial value at boot. */
+    .data :
+    {
+        _sdata = .;
+        *(.data*)
+        _global_pointer = . + 0x800;
+
+        . = ALIGN(4);
+        _edata = .;
+    } > RAM /*> ram AT >rom*/
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {   _sbss = .;
+        *(.bss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        _ebss = .;
+    } > RAM
+
+    _end = . ;
+}
+
+PROVIDE(_start_heap = _ebss);
+PROVIDE(_stack_pointer  = ORIGIN(RAM) + LENGTH(RAM));
\ No newline at end of file
diff --git a/test/scar/t3_load_store_byte.S b/test/scar/load_store_byte.S
similarity index 100%
rename from test/scar/t3_load_store_byte.S
rename to test/scar/load_store_byte.S
diff --git a/test/scar/t4_load_store_hw.S b/test/scar/load_store_hw.S
similarity index 72%
rename from test/scar/t4_load_store_hw.S
rename to test/scar/load_store_hw.S
index 22f127f2..c6d0be78 100644
--- a/test/scar/t4_load_store_hw.S
+++ b/test/scar/load_store_hw.S
@@ -16,15 +16,18 @@ _start:
     lh a1, 2(t0)
     lhu a2, 2(t0)
 
-    li t3, 0x9999   # misaligned store overwriting previous value in memory partially
-    sh t3, 1(t0)
+    lw s0, 0(t0)
+
+    li t3, 0xcc     # load a 1 byte value
+    sb t3, 1(t0)
+    li t3, 0xdd     # load a 1 byte value
+    sb t3, 2(t0)
 
     lh a3, 0(t0)
-    lh a4, 1(t0)
-    lh a5, 2(t0)
+    lh a4, 2(t0)
+    lw a5, 0(t0)
     lhu a6, 2(t0)
 
-
     nop
     ebreak
 
@@ -36,8 +39,11 @@ _start:
 # eq a1 0xffff8955
 # eq a2 0x00008955
 
-# eq t3 0x00009999
-# eq a3 0xffff9955
-# eq a4 0xffff9999
-# eq a5 0xffff8999
-# eq a6 0x00008999
\ No newline at end of file
+# eq s0 0x89557155
+
+# eq t3 0x000000dd
+
+# eq a3 0xffffcc55
+# eq a4 0xffff89dd
+# eq a5 0x89ddcc55
+# eq a6 0x000089dd
\ No newline at end of file
diff --git a/test/scar/t6_lui.S b/test/scar/lui.S
similarity index 100%
rename from test/scar/t6_lui.S
rename to test/scar/lui.S
diff --git a/test/scar/lw.S b/test/scar/lw.S
new file mode 100644
index 00000000..ce885ef7
--- /dev/null
+++ b/test/scar/lw.S
@@ -0,0 +1,70 @@
+.global main
+
+.text
+main:
+    la x1, var1
+    lw x1, 0(x1)
+
+    la x2, var2
+    lw x2, 0(x2)
+
+    la x3, var3
+    lw x3, 0(x3)
+
+    la x4, var4
+    lw x4, 0(x4)
+
+    la x5, var5
+    lw x5, 0(x5)
+
+    la x6, var6
+    lw x6, 0(x6)
+
+    la x7, var7
+    lw x7, 0(x7)
+
+    la x8, var8
+    lw x8, 0(x8)
+
+    la x9, var9
+    lw x9, 0(x9)
+
+    la x10, var10
+    lw x10, 0(x10)
+
+    la x11, var11
+    lw x11, 0(x11)
+
+    la x12, var12
+    lw x12, 0(x12)
+
+    ebreak
+
+
+.data
+var1:   .word 0x12345678
+var2:   .word 0x00002020
+var3:   .word 0xf3232532
+var4:   .word 0xdea14245
+var5:   .word 0xdea12cad
+var6:   .word 0xdacadaca
+var7:   .word 0xbeefdead
+var8:   .word 0xdeadbeef
+var9:   .word 0x1beefbee
+var10:   .word 0x12deadbe
+var11:   .word 0x123deadb
+var12:   .word 0x1234dead
+
+# $-ASSERTIONS-$
+# eq x1 0x12345678
+# eq x2 0x00002020
+# eq x3 0xf3232532
+# eq x4 0xdea14245
+# eq x5 0xdea12cad
+# eq x6 0xdacadaca
+# eq x7 0xbeefdead
+# eq x8 0xdeadbeef
+# eq x9 0x1beefbee
+# eq x10 0x12deadbe
+# eq x11 0x123deadb
+# eq x12 0x1234dead
\ No newline at end of file
diff --git a/test/scar/t2_mv.S b/test/scar/mv.S
similarity index 100%
rename from test/scar/t2_mv.S
rename to test/scar/mv.S
diff --git a/test/scar/t12_or.S b/test/scar/or.S
similarity index 100%
rename from test/scar/t12_or.S
rename to test/scar/or.S
diff --git a/test/scar/t13_ori.S b/test/scar/ori.S
similarity index 100%
rename from test/scar/t13_ori.S
rename to test/scar/ori.S
diff --git a/test/scar/scar.py b/test/scar/scar.py
index cd2a2c13..c8d3e0c5 100644
--- a/test/scar/scar.py
+++ b/test/scar/scar.py
@@ -7,7 +7,7 @@
 from colorama import Fore, Back, Style
 
 
-linker_script_path = '../../sw/lib/link.ld' #relative
+linker_script_path = 'link.ld' #relative
 cwd = os.getcwd()
 work_dir = cwd + '/work'
 
diff --git a/test/scar/t17_sll.S b/test/scar/sll.S
similarity index 100%
rename from test/scar/t17_sll.S
rename to test/scar/sll.S
diff --git a/test/scar/t18_slli.S b/test/scar/slli.S
similarity index 100%
rename from test/scar/t18_slli.S
rename to test/scar/slli.S
diff --git a/test/scar/t19_srl.S b/test/scar/slt.S
similarity index 100%
rename from test/scar/t19_srl.S
rename to test/scar/slt.S
diff --git a/test/scar/t20_srli.S b/test/scar/slti.S
similarity index 100%
rename from test/scar/t20_srli.S
rename to test/scar/slti.S
diff --git a/test/scar/t21_sra.S b/test/scar/sltiu.S
similarity index 100%
rename from test/scar/t21_sra.S
rename to test/scar/sltiu.S
diff --git a/test/scar/t22_srai.S b/test/scar/sltu.S
similarity index 100%
rename from test/scar/t22_srai.S
rename to test/scar/sltu.S
diff --git a/test/scar/t23_slt.S b/test/scar/sra.S
similarity index 100%
rename from test/scar/t23_slt.S
rename to test/scar/sra.S
diff --git a/test/scar/t24_slti.S b/test/scar/srai.S
similarity index 100%
rename from test/scar/t24_slti.S
rename to test/scar/srai.S
diff --git a/test/scar/t25_sltu.S b/test/scar/srl.S
similarity index 100%
rename from test/scar/t25_sltu.S
rename to test/scar/srl.S
diff --git a/test/scar/t26_sltiu.S b/test/scar/srli.S
similarity index 100%
rename from test/scar/t26_sltiu.S
rename to test/scar/srli.S
diff --git a/test/scar/t5_storew.S b/test/scar/storew.S
similarity index 100%
rename from test/scar/t5_storew.S
rename to test/scar/storew.S
diff --git a/test/scar/t9_sub.S b/test/scar/sub.S
similarity index 100%
rename from test/scar/t9_sub.S
rename to test/scar/sub.S
diff --git a/test/scar/sw.S b/test/scar/sw.S
new file mode 100644
index 00000000..6b9f1372
--- /dev/null
+++ b/test/scar/sw.S
@@ -0,0 +1,113 @@
+.global main
+
+.text
+main:
+    # Stores
+    la x31, memloc
+
+    li x1, 0x12345678
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1, 0x00002020
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1, 0xf3232532
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1, 0xdea14245
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1,0xdea12cad
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1, 0xdacadaca
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1, 0xbeefdead
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1, 0xdeadbeef
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1, 0x1beefbee
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1, 0x12deadbe
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1, 0x123deadb
+    sw x1, 0(x31)
+    addi x31, x31, 4
+
+    li x1, 0x1234dead
+    sw x1, 0(x31)
+    
+    # Loads
+    la x31, memloc
+
+    lw x1, 0(x31)
+    addi x31, x31, 4
+
+    lw x2, 0(x31)
+    addi x31, x31, 4
+
+    lw x3, 0(x31)
+    addi x31, x31, 4
+
+    lw x4, 0(x31)
+    addi x31, x31, 4
+
+    lw x5, 0(x31)
+    addi x31, x31, 4
+
+    lw x6, 0(x31)
+    addi x31, x31, 4
+
+    lw x7, 0(x31)
+    addi x31, x31, 4
+
+    lw x8, 0(x31)
+    addi x31, x31, 4
+
+    lw x9, 0(x31)
+    addi x31, x31, 4
+
+    lw x10, 0(x31)
+    addi x31, x31, 4
+
+    lw x11, 0(x31)
+    addi x31, x31, 4
+
+    lw x12, 0(x31)
+    addi x31, x31, 4
+
+
+    ebreak
+
+
+.data
+memloc:
+
+# $-ASSERTIONS-$
+# eq x1 0x12345678
+# eq x2 0x00002020
+# eq x3 0xf3232532
+# eq x4 0xdea14245
+# eq x5 0xdea12cad
+# eq x6 0xdacadaca
+# eq x7 0xbeefdead
+# eq x8 0xdeadbeef
+# eq x9 0x1beefbee
+# eq x10 0x12deadbe
+# eq x11 0x123deadb
+# eq x12 0x1234dead
\ No newline at end of file
diff --git a/test/scar/t15_xor.S b/test/scar/xor.S
similarity index 100%
rename from test/scar/t15_xor.S
rename to test/scar/xor.S
diff --git a/test/scar/t16_xori.S b/test/scar/xori.S
similarity index 100%
rename from test/scar/t16_xori.S
rename to test/scar/xori.S

From 25848e67ee8928f6e96646ba9891d544ac7a5b8d Mon Sep 17 00:00:00 2001
From: Saurabh Singh <saurabh.s99100@gmail.com>
Date: Tue, 20 Jul 2021 08:36:35 +0530
Subject: [PATCH 2/6] remove older memload code

---
 rtl/core/AtomRV.v | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/rtl/core/AtomRV.v b/rtl/core/AtomRV.v
index 11957552..00b4213d 100644
--- a/rtl/core/AtomRV.v
+++ b/rtl/core/AtomRV.v
@@ -329,16 +329,7 @@ begin
         2'b10:  begin   // Load Word
                     memload = dmem_data_i;
                 end
-        
-
 
-        
-        /*memload = {{24{dmem_data_i[7]}}, dmem_data_i[7:0]};     // LB
-        3'b001:   memload = {{16{dmem_data_i[15]}}, dmem_data_i[15:0]};   // LH
-        3'b010:   memload = dmem_data_i;                            // LW
-        3'b100:   memload = {{24{1'b0}}, dmem_data_i[7:0]};         // LBU
-        3'b101:   memload = {{16{1'b0}}, dmem_data_i[15:0]};        // LHU
-*/
         default: memload = 32'h00000000;
     endcase 
 end

From 979e205b506f3c839d522cd2c1cfef816ee056da Mon Sep 17 00:00:00 2001
From: Saurabh Singh <saurabh.s99100@gmail.com>
Date: Tue, 20 Jul 2021 08:59:28 +0530
Subject: [PATCH 3/6] Spell Corrections!

---
 README.md                 |   2 +-
 a.elf                     | Bin 9376 -> 0 bytes
 rtl/HydrogenSoC.v         |   2 +-
 rtl/core/Alu.v            |   2 +-
 rtl/core/AtomRV.v         |  22 +++++++--------
 rtl/core/Decode.v         |   6 ++--
 rtl/core/RegisterFile.v   |   2 +-
 sim/AtomSim.cpp           |   6 ++--
 sim/Backend.hpp           |   4 +--
 sim/Backend_AtomBones.hpp |   6 ++--
 sim/defs.hpp              |   8 +++---
 t1.s                      |  56 --------------------------------------
 12 files changed, 30 insertions(+), 86 deletions(-)
 delete mode 100755 a.elf
 delete mode 100644 t1.s

diff --git a/README.md b/README.md
index 2814b8a7..5a4956cf 100644
--- a/README.md
+++ b/README.md
@@ -154,7 +154,7 @@ just replace `your_path` with the path to the `riscv-atom/build/bin` directory o
 
 ### Running example programs
 
-Example programs reside in the `sw/examples` directory. Each folderr inside this directory contains an example  C/Assembly program and a shell script to compile it.
+Example programs reside in the `sw/examples` directory. Each folder inside this directory contains an example  C/Assembly program and a shell script to compile it.
 
 Let's try the banner program, Go to the banner directory
 
diff --git a/a.elf b/a.elf
deleted file mode 100755
index 1ca4a94b62ae03dd88fcff76cd63305ecdfaff72..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 9376
zcmeHNOKTHR6h6sJ(g=cm2&vXZ>_c6Y(5A5}qKuCeD@8ZjjY6EHK|>!2ld-l7v2AqW
z%0<9zt*?!A<HnU`d@lS63R!3$;G#vkbfMq5GdCSK;-(<<Uii*E-#O<#^4*!mkb5UJ
zG!O^`NVXttkYq^&uXVVYB*iF5hbTe~ZoW~DAZiV|2yqB;F+L{pI;`FU!w7T8H;$=l
zN&%&SQa~x76i^B%1(X6x0i}RaKq;UUPzr3l0?`0PTJZf}Z6dugJ3F^dMzpkzKGF+B
zkpejl1)2d2fB+{94j2FdP6!+@00JBx954U^91R>W00NvKIA8z-I010L00?jh954W)
zD(0xnIIHDHL^uz<C2(q0+mADWUzvTgQl1Y`G>CZc^orIVq$>Q%+}q{y;~+&f#I-Za
zT8Bne_?7azrScPvqB`RG*(I%0rz-r)-S^+hPj!lh5D%rkX<Z?z!mr%>@U{FbMA0zf
z;eoH(fiP{S^WXY6Os$|4PzopolmbctrGQdEDWDWk3Md8s4+W-%lg+UhQKGA3BXxSd
zw$MFa`}FzK=Y`t(;`-u3ZSCh;8@lE%-%m6z)RN7o_F&&uzLcG$z%IBUYqBqqPZat8
z{l7J>eyf1^P5^1RO~4J~Jgx~Y4L)TzM<A%vk6$~{&&bOO$VO$cmv48um=B-bbWp_I
z`I&cvN4)iz_kv^2dVN1Qt|!#_aq!(fZh*J?cnW-<kDmvR`S?ZfP9MJve#pnKfMZYf
z^-ORyY?1e&Q4u}gt>D&(-+K$a)Qj`CIpOKS`8np^e2w^h_d)#i4@BBET>p^s5qEvA
ze-3`vH{T1+`{sN32iNEoIP?*X=X=ebZ#-qQiJ`%PVJluB+cJyk+<4KRM)bm%IeLzx
zlcv?nCc&nUO_I%FHvMdlusO=+7@OW6Va1r<1f@&1nH^0R3;78<XHhz5=ca5#Go=!x
z2Zt}g9WiYa2@yfHh4l5YLdG1cj~X}g6R7YCCr02;<$0FLT-GjFMDfz}xNT<8+m_qk
zke*mCE{4W=iMV((;-+m|`OHl_S8~Pq2ixXJC+^5_edFfYGxZ)4+7F*4_TCnqV&aSt
zahoT<c=q{0;yOOVo|v1LR@U)5ftsR>bKPD^(91gRy+=`Ghho?w0=!>-26%tiGVK8T
cZ}Qc4qK}BlCg*EHz+cziL3C0Up_g^P0b2gn{{R30

diff --git a/rtl/HydrogenSoC.v b/rtl/HydrogenSoC.v
index d8e46bda..b558e732 100644
--- a/rtl/HydrogenSoC.v
+++ b/rtl/HydrogenSoC.v
@@ -7,7 +7,7 @@
 `include "core/AtomRV_wb.v"
 
 /**
- *  Hydogen SoC
+ *  Hydrogen SoC
  *  Barebone SoC housing a single atom core, imem, & dmem.
  */
 
diff --git a/rtl/core/Alu.v b/rtl/core/Alu.v
index a0b7a66d..7f413857 100644
--- a/rtl/core/Alu.v
+++ b/rtl/core/Alu.v
@@ -3,7 +3,7 @@
 //
 //  File : Alu.v
 //
-//  Desciption : Arithmetic and logic unit for Atom core
+//  Description : Arithmetic and logic unit for Atom core
 ////////////////////////////////////////////////////////////////////
 `default_nettype none
 
diff --git a/rtl/core/AtomRV.v b/rtl/core/AtomRV.v
index 00b4213d..1ed7e535 100644
--- a/rtl/core/AtomRV.v
+++ b/rtl/core/AtomRV.v
@@ -52,19 +52,19 @@ module AtomRV
 /*
     ///////////// Protocol specification //////////////
     CPU has a generic handshaking protocol interface (GHPI). Handshaking is done via means 
-    of two signals 'valid' & 'ack'. Valid signal is set by master wenever a tansaction 
+    of two signals 'valid' & 'ack'. Valid signal is set by master whenever a transaction 
     begins and slave responds by setting the 'ack' signal. When both signals are set, 
-    tansaction takes place. GHPI protocol also supports delayed transactions.
+    transaction takes place. GHPI protocol also supports delayed transactions.
 
     CPU has two GHPI ports namely imem & dmem ports. imem port is used only for reading 
     the memory while dmem pot is used for both eads and writes. The CPU ca ne configured in 
-    both harward and von-neumann fashion. In case of harwad configuration, separate instruction 
-    and data memory ae needed to be connected. In case of von-neumann mode, a bus arbiter is
+    both Harvard and Von-Neumann fashion. In case of Harvard configuration, separate instruction 
+    and data memory ae needed to be connected. In case of Von-Neumann mode, a bus arbiter is
     needed to multiplex between both ports.
 
     Reads:
     - Master sets the address, the valid signal and clears the strobe signal.
-    - Slave responds by poviding the data coresponding to that address & setting the ack signal.
+    - Slave responds by providing the data corresponding to that address & setting the ack signal.
 
     Writes:
     - Master sets the address, the data, the valid signal and the strobe signal (depending on 
@@ -91,7 +91,7 @@ always @(posedge clk_i) begin
         ProgramCounter <= `RESET_PC_ADDRESS;
 
     else if(jump_decision)
-        ProgramCounter <= {alu_out[31:1], 1'b0};    // Only jump to 16 bit aligned addrresses, also JALR enforces this
+        ProgramCounter <= {alu_out[31:1], 1'b0};    // Only jump to 16 bit aligned addresses, also JALR enforces this
 
     else if (!stall_stage1) begin
         ProgramCounter <= pc_plus_four;
@@ -141,7 +141,7 @@ always @(posedge clk_i) begin
             InstructionRegister <= `__NOP_INSTRUCTION__;
 
         else if(stall_stage1) // Stall
-            InstructionRegister <= InstructionRegister; // retain pevious value
+            InstructionRegister <= InstructionRegister; // retain previous value
             
         else
             InstructionRegister <= imem_data_i;
@@ -156,8 +156,8 @@ end
 /*
     ////// Instruction Decode //////
     Instruction decode unit decodes instruction and sets various control 
-    signals throughout the pipeline. Is also extacts immediate values 
-    from instuictions and sign extends them properly.
+    signals throughout the pipeline. Is also extracts immediate values 
+    from instructions and sign extends them properly.
 */
 wire    [4:0]   d_rd_sel;
 wire    [4:0]   d_rs1_sel;
@@ -203,7 +203,7 @@ Decode decode
 
 
 /*
-    ////// Regster File //////
+    ////// Register File //////
     Contains cpu registers (r0-31)
 */
 
@@ -261,7 +261,7 @@ Alu alu
 
 /*
     ////// Comparator //////
-    Used for all comparitive opeations
+    Used for all comparative operations
 */
 reg comparison_result;
 
diff --git a/rtl/core/Decode.v b/rtl/core/Decode.v
index 199b7a9f..7e710bac 100644
--- a/rtl/core/Decode.v
+++ b/rtl/core/Decode.v
@@ -3,7 +3,7 @@
 //
 //  File        : Decode.v
 //  Author      : Saurabh Singh (saurabh.s99100@gmail.com)
-//  Desciption  : Instruction Decoder for RISCV atom core
+//  Description  : Instruction Decoder for RISCV atom core
 ////////////////////////////////////////////////////////////////////
 `default_nettype none
 
@@ -46,11 +46,11 @@ assign  rs2_sel_o   = instr_i[24:20];
 reg    [2:0] imm_format;
 
 /*
-    Decode Immidiate
+    Decode Immediate
 */
 reg [31:0] getExtImm;
 
-always @(*) /*COMBINATIONAL*/ 
+always @(*) /*COMBINATORIAL*/ 
 begin
     case(imm_format)
             `__I_IMMIDIATE__    :   getExtImm = {{21{instr_i[31]}}, instr_i[30:25], instr_i[24:21], instr_i[20]};
diff --git a/rtl/core/RegisterFile.v b/rtl/core/RegisterFile.v
index 68bf8a2e..a32b2c2f 100644
--- a/rtl/core/RegisterFile.v
+++ b/rtl/core/RegisterFile.v
@@ -3,7 +3,7 @@
 //
 //  File        : RegisterFile.v
 //  Author      : Saurabh Singh (saurabh.s99100@gmail.com)
-//  Desciption  : Paramatrized register file for RISCV atom core
+//  Description  : Parametrized register file for RISCV atom core
 ////////////////////////////////////////////////////////////////////
 `default_nettype none
 
diff --git a/sim/AtomSim.cpp b/sim/AtomSim.cpp
index 4b6fd9fd..43668ef9 100644
--- a/sim/AtomSim.cpp
+++ b/sim/AtomSim.cpp
@@ -53,7 +53,7 @@ bool dump_regs_on_ebreak 	= false;	// Used by SCAR framework
 // Input File
 std::string ifile;
 
-// Max Iteation
+// Max Iteration
 const unsigned long int default_maxitr = 10000000;
 unsigned long int maxitr = default_maxitr;
 
@@ -100,7 +100,7 @@ unsigned long int mem_size = default_mem_size;
  */
 void ExitAtomSim(std::string message, bool exit_with_error)
 {
-	// ===== Pre-Exit Pocedure =====
+	// ===== Pre-Exit Procedure =====
 	// if trace file is open, close it before exiting
 	if(trace_enabled)
 		bkend->tb->closeTrace();
@@ -177,7 +177,7 @@ void parse_commandline_args(int argc, char**argv, std::string &infile)
 			std::string unknown_args;
 			for(unsigned int i=0; i<result.unmatched().size(); i++)
 				unknown_args = unknown_args + result.unmatched()[i] + (i==result.unmatched().size()-1 ? "" :", ");
-			throwError("CLI0", "Unrecognized aguments [" + unknown_args + "]", true);
+			throwError("CLI0", "Unrecognized arguments [" + unknown_args + "]", true);
 		}
 
 		if (result.count("help"))
diff --git a/sim/Backend.hpp b/sim/Backend.hpp
index 62e8f7dc..51a98933 100644
--- a/sim/Backend.hpp
+++ b/sim/Backend.hpp
@@ -74,7 +74,7 @@ class Backend
     }
 
 	/**
-	 * @brief probe all internal signals and regsters and 
+	 * @brief probe all internal signals and registers and 
 	 * update backend state
 	 */
 	virtual void refreshData() = 0;
@@ -117,7 +117,7 @@ class Backend
         // Print Register File
         if(verbose_flag)
         {
-            int cols = 2; // no of coloumns per rows
+            int cols = 2; // no of columns per rows
             #ifndef DEBUG_PRINT_T2B
             for(int i=0; i<32; i++)	// print in left-right fashion
             {
diff --git a/sim/Backend_AtomBones.hpp b/sim/Backend_AtomBones.hpp
index edc6bb10..fee76ec6 100644
--- a/sim/Backend_AtomBones.hpp
+++ b/sim/Backend_AtomBones.hpp
@@ -259,7 +259,7 @@ class Backend_AtomBones: public Backend<VAtomBones>
 {
 	public:
 	/**
-	 * @brief Pointer to memoy object
+	 * @brief Pointer to memory object
 	 */
 	Memory * mem;
 
@@ -344,7 +344,7 @@ class Backend_AtomBones: public Backend<VAtomBones>
 
 
 	/**
-	 * @brief probe all internal signals and regsters and 
+	 * @brief probe all internal signals and registers and 
 	 * update backend state
 	 */
 	void refreshData()
@@ -416,7 +416,7 @@ class Backend_AtomBones: public Backend<VAtomBones>
 				fWrite(fcontents, std::string(trace_dir)+"/dump.txt");
 			}
 			
-			// ==========  MEM SIGNATURE DUMP (For RISCV-Arch Tests) =============
+			// ==========  MEM SIGNATURE DUMP (For RISC-V-Arch Tests) =============
 			if(signature_file.length()!=0)	
 			{
 				// Get start and end address of signature
diff --git a/sim/defs.hpp b/sim/defs.hpp
index 0941419d..cd14a31b 100644
--- a/sim/defs.hpp
+++ b/sim/defs.hpp
@@ -42,7 +42,7 @@ const std::string  COLOR_YELLOW =  "\033[33m";
  * 
  * @param er_code error code 
  * @param message error message
- * @param exit flag that tells weather to exit immidiately
+ * @param exit flag that tells weather to exit immediately
  */
 void throwError(std::string er_code, std::string message, bool Exit = false)
 {
@@ -67,7 +67,7 @@ void throwWarning(std::string wr_code, std::string message)
 
 
 /**
- * @brief Displays a success messaage
+ * @brief Displays a success message
  * 
  * @param message Success message
  */
@@ -103,7 +103,7 @@ std::string lStrip(const std::string& s)
 
 
 /**
- * @brief removes succeding whitespaces in a string
+ * @brief removes succeeding whitespaces in a string
  * 
  * @param s string
  * @return std::string 
@@ -116,7 +116,7 @@ std::string rStrip(const std::string& s)
 
 
 /**
- * @brief removes preceding & succeding whitespaces in a string
+ * @brief removes preceding & succeeding whitespaces in a string
  * 
  * @param s string
  * @return std::string 
diff --git a/t1.s b/t1.s
deleted file mode 100644
index 72e85407..00000000
--- a/t1.s
+++ /dev/null
@@ -1,56 +0,0 @@
-.global main
-
-.text
-main:
-    la x1, var1
-    lw x1, 0(x1)
-
-    la x2, var2
-    lw x2, 0(x2)
-
-    la x3, var3
-    lw x3, 0(x3)
-
-    la x4, var4
-    lw x4, 0(x4)
-
-    la x5, var5
-    lw x5, 0(x5)
-
-    la x6, var6
-    lw x6, 0(x6)
-
-    la x7, var7
-    lw x7, 0(x7)
-
-    la x8, var8
-    lw x8, 0(x8)
-
-    la x9, var9
-    lw x9, 0(x9)
-
-    la x10, var10
-    lw x10, 0(x10)
-
-    la x11, var11
-    lw x11, 0(x11)
-
-    la x12, var12
-    lw x12, 0(x12)
-
-    ebreak
-
-
-.data
-var1:   .word 0x12345678
-var2:   .word 0x00002020
-var3:   .word 0xf3232532
-var4:   .word 0xdea14245
-var5:   .word 0xdea12cad
-var6:   .word 0xdacadaca
-var7:   .word 0xbeefdead
-var8:   .word 0xdeadbeef
-var9:   .word 0x1beefbee
-var10:   .word 0x12deadbe
-var11:   .word 0x123deadb
-var12:   .word 0x1234dead
\ No newline at end of file

From 5493915d7a5dc3fa17d31bf02fcb9a5fb8690e23 Mon Sep 17 00:00:00 2001
From: Saurabh Singh <saurabh.s99100@gmail.com>
Date: Tue, 20 Jul 2021 14:16:24 +0530
Subject: [PATCH 4/6] Bugfix: ALU shifts

- Alu SLL & SRL use only 5 LSB of B operand.
- ASR uses signed A operand.

All riscv-arch-tests passing.
---
 rtl/core/Alu.v | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/rtl/core/Alu.v b/rtl/core/Alu.v
index 7f413857..85808d1d 100644
--- a/rtl/core/Alu.v
+++ b/rtl/core/Alu.v
@@ -18,6 +18,8 @@ module Alu
     output reg [31:0] Out
 );
 
+wire signed [31:0] A_s = A;
+
 always @(*) begin
     case(Sel)
 
@@ -26,9 +28,9 @@ always @(*) begin
     `__ALU_XOR__:   Out = A ^ B;
     `__ALU_OR__ :   Out = A | B;
     `__ALU_AND__:   Out = A & B;
-    `__ALU_SLL__:   Out = A << B;
-    `__ALU_SRL__:   Out = A >> B;
-    `__ALU_SRA__:   Out = A >>> B;
+    `__ALU_SLL__:   Out = A << B[4:0];
+    `__ALU_SRL__:   Out = A >> B[4:0];
+    `__ALU_SRA__:   Out = A_s >>> B[4:0];
 
     default:    Out = 32'd0;
     endcase

From c35cdf4a2c1fc6453e0211727ad1dc0b6268f525 Mon Sep 17 00:00:00 2001
From: Saurabh Singh <saurabh.s99100@gmail.com>
Date: Tue, 20 Jul 2021 18:59:36 +0530
Subject: [PATCH 5/6] Minor code refactoring - All derved backend class will
 have same name, #ifdefs will select the correct backend. - Add getTargetName
 method to backend class. - Correct UART addresses in hello.s example.

---
 sim/AtomSim.cpp           | 36 +++++++++++++----------------------
 sim/Backend.hpp           | 27 ++++++++++++++++++++++++++
 sim/Backend_AtomBones.hpp | 40 ++++++++++++++++++++++++++++++++++++---
 sw/examples/hello/hello.s |  4 ++--
 sw/lib/link.ld            |  4 ++--
 5 files changed, 81 insertions(+), 30 deletions(-)

diff --git a/sim/AtomSim.cpp b/sim/AtomSim.cpp
index 43668ef9..1533a566 100644
--- a/sim/AtomSim.cpp
+++ b/sim/AtomSim.cpp
@@ -81,17 +81,17 @@ std::string signature_file 	= "";
 // Include Backend
 #include "Backend_AtomBones.hpp"
 
-// Backend name
-const std::string AtomSimBackend = "AtomBones";
-
-// Backend Object
-Backend_AtomBones *bkend;		
 
 // Default mem size for atomBones
-const unsigned long int default_mem_size = 134217728 + 3 + 1;	// 128MB (Code & Data) + 3 Bytes (Serial IO) + 1 (To make word access possible)
+// 128MB (Code & Data) + 3 Bytes (Serial IO) + 1 (To make word access possible on address 0x08000000)
+const unsigned long int default_mem_size = (128*1024*1024) + 3 + 1;	
 unsigned long int mem_size = default_mem_size;
 #endif
 
+
+// Backend Object
+Backend_AtomSim *bkend;
+
 /**
  * @brief Exit AtomSim
  * 
@@ -110,7 +110,7 @@ void ExitAtomSim(std::string message, bool exit_with_error)
 		std::cout << message << "\n";
 
 	// Destroy backend
-	bkend->~Backend_AtomBones();
+	bkend->~Backend_AtomSim();
 
 	// ===== Exit =====
 	if(exit_with_error)
@@ -238,7 +238,7 @@ void run(long unsigned int cycles)
 int main(int argc, char **argv)
 {
     if (verbose_flag)
-		std::cout << "AtomSim [" << AtomSimBackend << "]\n";
+		std::cout << "AtomSim [" << bkend->getTargetName() << "]\n";
 
 	// Initialize verilator
 	Verilated::commandArgs(argc, argv);
@@ -248,7 +248,7 @@ int main(int argc, char **argv)
 
 	// Create a new backend instance
 	#ifdef TARGET_ATOMBONES
-	bkend = new Backend_AtomBones(ifile, default_mem_size);
+	bkend = new Backend_AtomSim(ifile, default_mem_size);
 	#endif
 
 	if(trace_enabled == true)
@@ -342,8 +342,6 @@ int main(int argc, char **argv)
 				else
 					std::cout << "Trace was not enabled \n";
 			}
-			// ============== BACKEND SPECIFIC COMMANDS ==================
-			#ifdef TARGET_ATOMBONES
 			else if(token[0] == "mem")
 			{
 				if(token.size()<2)
@@ -358,25 +356,17 @@ int main(int argc, char **argv)
 					else										// Decimal Number
 						addr = std::stoi(token[1], nullptr, 10);
 					
-					printf("%08x : %02x %02x %02x %02x\n", addr, bkend->mem->fetchByte(addr),
-						bkend->mem->fetchByte(addr+1),bkend->mem->fetchByte(addr+2), bkend->mem->fetchByte(addr+3));
+					uint32_t data = bkend->getMemContents(addr);
+					printf("%08x : %02x %02x %02x %02x\n", addr, (data & 0x000000ff), (data & 0x0000ff00)>>8, (data & 0x00ff0000)>>16, (data & 0xff000000)>>24);
 				}
 			}
 			else if(token[0] == "dumpmem")
 			{
 				if(token.size()<2)
 					throwError("CMD1", "\"dumpmem\" command expects filename as argument\n");
-				
-				std::vector<std::string> fcontents;
-				for(unsigned int i=0; i<bkend->mem->size-4; i+=4)
-				{	
-					char hex [30];
-					sprintf(hex, "0x%08x\t:\t0x%08x", i, bkend->mem->fetchWord(i));
-					fcontents.push_back(hex);
-				}
-				fWrite(fcontents, token[1]);
+				else
+					bkend->dumpmem(token[1]);
 			}
-			#endif
 
 			else
 			{
diff --git a/sim/Backend.hpp b/sim/Backend.hpp
index 51a98933..5709a159 100644
--- a/sim/Backend.hpp
+++ b/sim/Backend.hpp
@@ -63,6 +63,13 @@ class Backend
     };
 
     public:
+
+    /**
+     * @brief Get the Target Name
+     * @return std::string 
+     */
+    virtual std::string getTargetName() = 0;
+
 	/**
 	 * @brief reset the backend
 	 */
@@ -138,6 +145,26 @@ class Backend
         }
     }
 
+    /**
+     * @brief Dump contents of memory into a file
+     * OVERRIDE THIS IN ANY DERIVED CLASSES
+     * @param file 
+     */
+    void dumpmem(std::string file)
+    {
+        throwError("", "Memory dumps not supported in current target");
+    }
+
+    /**
+     * @brief Get contents of a memory location
+     * OVERRIDE THIS IN ANY DERIVED CLASSES
+     */
+    uint32_t getMemContents(uint32_t addr)
+    {
+        throwError("", "Viewing memory content not suppoted in current target");
+        return 0;
+    }
+
 	/**
 	 * @brief Tick for one cycle
 	 * 
diff --git a/sim/Backend_AtomBones.hpp b/sim/Backend_AtomBones.hpp
index fee76ec6..dd4ba463 100644
--- a/sim/Backend_AtomBones.hpp
+++ b/sim/Backend_AtomBones.hpp
@@ -255,7 +255,7 @@ class Memory
  * Backend class encapsulates the data 
  * probing and printing operations
  */
-class Backend_AtomBones: public Backend<VAtomBones>
+class Backend_AtomSim: public Backend<VAtomBones>
 {
 	public:
 	/**
@@ -267,7 +267,7 @@ class Backend_AtomBones: public Backend<VAtomBones>
 	/**
 	 * @brief Construct a new Backend object
 	 */
-	Backend_AtomBones(std::string ifile, unsigned long mem_size)
+	Backend_AtomSim(std::string ifile, unsigned long mem_size)
 	{
         // Construct Testbench object
         tb = new Testbench<VAtomBones>();
@@ -297,12 +297,17 @@ class Backend_AtomBones: public Backend<VAtomBones>
 	/**
 	 * @brief Destroy the Backend object
 	 */
-	~Backend_AtomBones()
+	~Backend_AtomSim()
 	{
 		delete tb;
 		delete mem;
 	}
 
+	std::string getTargetName()
+	{
+		return "AtomBones";
+	}
+
 	void serviceMemoryRequest()
 	{
 		// Clear all ack signals
@@ -497,4 +502,33 @@ class Backend_AtomBones: public Backend<VAtomBones>
 		}
 		prev_tx_we = cur_tx_we;
 	}
+
+	/**
+	 * @brief Dump contents of memoy into a file
+	 * @param file 
+	 */
+	void dumpmem(std::string file)
+	{
+		if(mem->size < 1*1024*1024)	// 1MB
+		{
+			std::vector<std::string> fcontents;
+			for(unsigned int i=0; i<mem->size-4; i+=4)
+			{	
+				char hex [30];
+				sprintf(hex, "0x%08x\t:\t0x%08x", i, mem->fetchWord(i));
+				fcontents.push_back(hex);
+			}
+			fWrite(fcontents, std::string(default_dump_dir)+"/"+file);
+		}
+		else
+			throwError("","Option not available due to excessive memory size (>1MB)\n", false);
+	}
+
+	 /**
+     * @brief Get contents of a memory location
+     */
+    uint32_t getMemContents(uint32_t addr)
+    {
+        return mem->fetchWord(addr);
+    }
 };
diff --git a/sw/examples/hello/hello.s b/sw/examples/hello/hello.s
index bc8f9797..918eaa1d 100644
--- a/sw/examples/hello/hello.s
+++ b/sw/examples/hello/hello.s
@@ -1,8 +1,8 @@
 .global main
 .text
 
-.equ TX_ADDRESS, 0x00014001               
-.equ TX_ACK_ADDRESS, 0x00014002         
+.equ TX_ADDRESS, 0x08000001
+.equ TX_ACK_ADDRESS, 0x08000002
 
 main:
     la a0, msg
diff --git a/sw/lib/link.ld b/sw/lib/link.ld
index 06e1afc9..7fd0891b 100644
--- a/sw/lib/link.ld
+++ b/sw/lib/link.ld
@@ -11,8 +11,8 @@ ENTRY(_start)
 /* MEMORY LAYOUT */
 MEMORY
 {
-    ROM (rx) : ORIGIN = 0x00000000, LENGTH = 64M    /* 64 kb @ 0x0*/
-    RAM (rwx): ORIGIN = 0x04000000, LENGTH = 64M    /* 16 kb @ 0x10000 (65536)*/
+    ROM (rx) : ORIGIN = 0x00000000, LENGTH = 64M    /* 64 MB @ 0x0*/
+    RAM (rwx): ORIGIN = 0x04000000, LENGTH = 64M    /* 64 MB @ 0x10000 (0x04000000)*/
 }
 
 SECTIONS

From 5bf9ed54c0f551e5c11fda30a34e80240203b7be Mon Sep 17 00:00:00 2001
From: Saurabh Singh <saurabh.s99100@gmail.com>
Date: Tue, 20 Jul 2021 19:07:52 +0530
Subject: [PATCH 6/6] change version number

---
 sim/defs.hpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sim/defs.hpp b/sim/defs.hpp
index cd14a31b..732063e3 100644
--- a/sim/defs.hpp
+++ b/sim/defs.hpp
@@ -1,7 +1,7 @@
 /**
  * @brief Version information
  */
-const char Info_version[] = "AtomSim v1.1";
+const char Info_version[] = "AtomSim v1.2";
 
 /**
  * @brief Copyright message