Ordt should generate an error on { sw=rw; hw=w; } with no hw we.

[sdnellen]

From open-register-design-tool created by sjalloq: Juniper#68

I had a quick look in the closed issues but couldn't see a matching title so forgive me if this has been reported already.

I was just looking for a write enable for one of my hardware writeable registers and noticed there wasn't one. Further reading of the RDL spec led me to this:

c) All hardware-writable fields shall be continuously assigned unless a write enable is specified.
d) When a field is writable by software and write-only by hardware (but not write-enabled), all soft-ware writes shall be lost on the next clock cycle. This shall reported as an error.

So I think you should be generating an error in this case. Without specifying a write enable for the hardware side, you generate the following Verilog in which the software side write is lost on the next cycle.

//------- combinatorial assigns for _adc_regs__tx0_adc
  always @ (*) begin
    reg__adc_regs__tx0_adc__adc_data_next = h2l__adc_regs__tx0_adc__adc_data_w;
    if (d2l__adc_regs__tx0_adc_we) reg__adc_regs__tx0_adc__adc_data_next = d2l__adc_regs__tx0_adc_w [9:0] ;
  end
  
  //------- reg assigns for _adc_regs__tx0_adc
  always @ (posedge clk or negedge sig_reset_n) begin
    if (! sig_reset_n) begin
      rg__adc_regs__tx0_adc__adc_data <= #1 1'b0;
    end
    else begin
      rg__adc_regs__tx0_adc__adc_data <= #1  reg__adc_regs__tx0_adc__adc_data_next;
    end
  end