make seL4SharedDataWithCaps cached on RISC-V?

[axel-h]

As a follow-up from #32 and @kent-mcleod 's comment #32 (comment) it appears that this does not only apply to ARM, but also RISC-V (and other like Loongson). I wonder if this check should be that cached is used by default for all known architectures and a failure is raised for unknown architectures if nothing set manually. That would also help future porting.

[kent-mcleod]

RISCV doesn't have a way to specify the cacheability attribute of a memory region in it's virtual mapping.

[axel-h]

This calls register_shared_variable() in camkes/runner/Context.py eventually, where a physical address is passed and the caching flag. Assuming we know which physical addresses on RISC-V are cached and which are not, this might be the place to fail the operation if the caching attribute does not match.

[kent-mcleod]

The physical address is an optional parameter that would only be set if paddr is set in the configuration for the connector though.