Some way of blocking simp
from unifying schematics
#730
Labels
proof engineering
nicer, shorter, more maintainable etc proofs
proof tools
convenience, automation, productivity tools
As seen in #729 if wp or some other tool gets you into a bad situation, e.g. schematic assumption,
simp
will happily unify that withFalse
which will result in very bad outcomes inwp
proofs.clarsimp
of course prevents this problem, but it involvesclarify
and so blows up∃val. x = Some val
to introduce a free variable that a precondition schematic doesn't rely on, creating the problem forwp
andsimp
to make worse. So in these cases we needsimp
, but without having it instantiate schematics.If we have a safer
wp
, a safervcg
and a safersimp
, we have some weaponry in stabilising some of the more horrid ccorres proofs like the fastpath ones.The text was updated successfully, but these errors were encountered: