State of ZCU102 support

[StefMassin]

In the list of supported boards, the ZCU102 is still listed as "WIP". What parts are and aren't supported on this board? Is it as suggested in issue #68 only the ethernet port and thus the debug interface that is not operational?

esp/socs/README.md

Lines 18 to 20 in 8dcc9f0

	* `xilinx-zcu102-xczu9eg`: Xilinx Zynq UltraScale+ MPSoC ZCU102 (WIP)

[jzuckerman]

The Zynq boards don't have an Ethernet interface exposed to the programmable logic, which is what we use on the other boards as the primary debug link for ESP. The debug link is required for uploading binaries to the SoC, sending resets, etc. For the Zynq boards listed, the debug interface is instead implemented through the AXI interface that connects the host core of the board to the programmable logic. This is implemented, but has not been thoroughly tested, so we have not officially released the complete support for the board yet, and have not found the time to finish it up.

However, I know of some users that were able to use this preliminary support. If I recall correctly, the user was able to successfully run baremetal applications, but was not able to boot Linux on the SoC. I would say if you're interested in using the Zynq board with ESP, that it'd be worth a try. If you can report what you discover, it would be helpful for us to know and we can provide some support with resolving any issues that might arise. If you're interested, you should checkout the zynq branch of ESP and work from there.

[StefMassin]

What do you mean by "primary debug link"? Is it also possible to instead use the UART port?