Understanding the VGA timing signals and viewport location

[victorliu]

I recently just got my own Minimal 64x4 board up and running except that my monitor has trouble staying in sync with the VGA output. Therefore, I have been trying to understand the details of how the VGA signals are generated and the mode being output. Based on the VGA section of the schematic, I have gathered the following conclusions:

• /V_NEXT is a pulse at 2 MHz
• H1 is 1 MHz
• H2 is 500 kHz
• H4 is 250 kHz
• H8 is 125 kHz, repeats every 8 us
• H16 is 62.5 kHz, repeats every 16 us
• H32 is 31.25 kHz, repeats every 32 us (whole line)
• Q6 not connected means every row is duplicated (240 addressable lines).
• V1 is 7.8125 kHz, every 128 us
• V2 is every 256 us
• V4 is every 0.512 ms
• V8 is every 1.024 ms
• V16 is every 2.048 ms
• V32 is every 4.096 ms
• V64 is every 8.192 ms
• V128 is every 16.384 ms
• V256 is every 32.768 ms
• /HSYNC is H8 OR H16 OR H32: 4us low pulse every 32 us.
• /VSYNC is 64us low every count of 260, which is 16.384+0.256ms = 16.64ms

So far this appears to match the 640x480@60Hz mode timings. The stated resolution of 400x240 is achieved in the vertical direction by double-outputting each row.

Additionally:

• The whole line is 64 bytes = 512 bits.
• 640/800 of the line is the visible area, which is 409.6 bits.
• Front porch should be 16/800 of line = 10.24 bits.
• HSync should be 96/800 of line = 61.44 bits.
• Back porch should be 48/800 of line = 30.72 bits.
• HSync pulse happens at beginning of counting across a row,
so active area starts after the sync pulse and back porch, which is 92 bits = 11 bytes in.
• VSync front/pulse/back should be 10/2/33 of 525 lines.
• VSync pulse happens also at beginning of vertical counting,
so active area starts after the sync pulse and back porch, which is approximately 17 of the 260 lines in.
• The viewport is 12*64+11 bytes in.

The 400 (or 416 in os.asm) horizontal resolution is also derivable from the signal timings. My question is how to reconcile the 12-line offset of VIEWPORT (in os.asm) with where the VSYNC pulse lands, or alternatively how is the VIEWPORT offset derived?

[slu4coder]

Hi Victor,
thanks for diving this deep into the circuit. I've designed all this some time ago, so I have some difficulties recalling my descisions. Deriving the 640x480 VGA signals from a single counter "the Minimal way" does not reproduce the exact VGA spec. However Monitors tend be fairly generous in accepting this standard. For VSYNC I have used this: Vertical sync signal

interval		        16,683 ms
pulse (neg.)		0.064 ms
blank			1.048 ms
data			15.253 ms
blank			0.318 ms

translating to:

520 scanlines
2
30
480
8

The length of the blanking intervals is somewhat "negotiable". My monitor allows me to adjust the horizontal and vertical screen position and I remember an some stage, I adjusted the blanking intervals in a way that puts the viewport in the center of my screen with minitor x/y settings both at 50% and went with that. So there might be some arbitrariness to it, but it shouldn't (and so far wasn't) the source of any problems. More of a problem are "modern" monitors that are able to detect a great variety of different VGA modes. The more modes a monitor knows, the more likely it becomes that it misinterprets the Minimal due to it's "not quite on point" timing restraint. I recommend buying a cheap older VGA monitor.