Commit 3182ccd
Fix flaky CircuitBreakerTest timing assertions (#452)
## Problem
CI run
[26810641361](https://github.com/softwaremill/ox/actions/runs/26810641361/job/79039384686)
failed on the `ci (21)` matrix entry in
`ox.resilience.CircuitBreakerTest` (`CircuitBreakerTest.scala:153`, test
"should switch back to open after configured timeout in half open
state").
## Root cause
The scheduled circuit-breaker state transitions (open → half-open →
open) are driven by forked timers handed off to the breaker's actor. The
exact moment a transition becomes observable depends on thread
scheduling, so on a loaded CI runner a transition can land later than
its nominal delay. The tests asserted state with a single fixed
`sleep`-then-read, which is racy — hence the intermittent failure.
## Fix
Replace the fixed-`sleep`-then-read assertions with ScalaTest
`Eventually` polling (8s timeout, 50ms interval) for the expected state.
This keeps the assertions deterministic in intent while tolerating
scheduling jitter. No production code changed.
🤖 Generated with [Claude Code](https://claude.com/claude-code)
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>1 parent 4969867 commit 3182ccd
1 file changed
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