Increase Orch CPU utilization timeout before link flap #16187
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This change was made because in modular chassis with multi-asic LCs, the link flap test might run on the uplink LC followed by the downlink LC. In such a scenario, the downlink LC will still be hot (above 10% utilization) before we flap its interfaces. Hence, the increase in timeout. We tested it with a timeout of 500 and it failed so we are increasing it to 600 which has been passing on our local T2 testbeds.
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This change was made because in modular chassis with multi-asic LCs, the link flap test might run on the uplink LC followed by the downlink LC. Since the uplink has a lot of neighbors the downlink CPU is busy re-routing the different pathways. In such a scenario, the downlink LC will still be hot (above 10% utilization) before we flap its interfaces. Hence, the increase in timeout.
We tested it with a timeout of 500 and it failed so we are increasing it to 600 which has been passing on our local T2 testbeds.
Description of PR
Summary:
Fixes #16186
Type of change
Back port request
Approach
What is the motivation for this PR?
To make sure that the timeout for the Orchagent CPU utilization check is large enough for the test to pass.
How did you do it?
Increased the timeout from 100 to 600.
How did you verify/test it?
Ran the test on T2 testbed with a timeout of 600 (Passed) and 500 (Failed)
Any platform specific information?
Supported testbed topology if it's a new test case?
Documentation