stm32g061.mmap

0x40000000 A PERIPHERAL TIM2
0x40000000 B  REGISTER CR1 (rw): control register 1
0x40000000 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0x40000000 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40000000 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40000000 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40000000 C   FIELD 04w01 DIR (rw): Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
0x40000000 C   FIELD 05w02 CMS (rw): Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
0x40000000 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40000000 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),
0x40000000 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40000004 B  REGISTER CR2 (rw): control register 2
0x40000004 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40000004 C   FIELD 04w03 MMS (rw): Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40000004 C   FIELD 07w01 TI1S (rw): TI1 selection
0x40000008 B  REGISTER SMCR (rw): slave mode control register
0x40000008 C   FIELD 00w03 SMS1 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40000008 C   FIELD 03w01 OCCS (rw): OCREF clear selection This bit is used to select the OCREF clear source
0x40000008 C   FIELD 04w03 TS1 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40000008 C   FIELD 07w01 MSM (rw): Master/Slave mode
0x40000008 C   FIELD 08w04 ETF (rw): External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0x40000008 C   FIELD 12w02 ETPS (rw): External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
0x40000008 C   FIELD 14w01 ECE (rw): External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
0x40000008 C   FIELD 15w01 ETP (rw): External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
0x40000008 C   FIELD 16w01 SMS2 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40000008 C   FIELD 20w02 TS2 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x4000000C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4000000C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000000C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4000000C C   FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x4000000C C   FIELD 03w01 CC3IE (rw): Capture/Compare 3 interrupt enable
0x4000000C C   FIELD 04w01 CC4IE (rw): Capture/Compare 4 interrupt enable
0x4000000C C   FIELD 06w01 TIE (rw): Trigger interrupt enable
0x4000000C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4000000C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x4000000C C   FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x4000000C C   FIELD 11w01 CC3DE (rw): Capture/Compare 3 DMA request enable
0x4000000C C   FIELD 12w01 CC4DE (rw): Capture/Compare 4 DMA request enable
0x4000000C C   FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40000010 B  REGISTER SR (rw): status register
0x40000010 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40000010 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40000010 C   FIELD 02w01 CC2IF (rw): Capture/compare 2 interrupt flag
0x40000010 C   FIELD 03w01 CC3IF (rw): Capture/compare 3 interrupt flag
0x40000010 C   FIELD 04w01 CC4IF (rw): Capture/compare 4 interrupt flag
0x40000010 C   FIELD 06w01 TIF (rw): Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
0x40000010 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40000010 C   FIELD 10w01 CC2OF (rw): Capture/Compare 2 overcapture flag
0x40000010 C   FIELD 11w01 CC3OF (rw): Capture/Compare 3 overcapture flag
0x40000010 C   FIELD 12w01 CC4OF (rw): Capture/Compare 4 overcapture flag
0x40000014 B  REGISTER EGR (wo): event generation register
0x40000014 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40000014 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40000014 C   FIELD 02w01 CC2G (wo): Capture/compare 2 generation
0x40000014 C   FIELD 03w01 CC3G (wo): Capture/compare 3 generation
0x40000014 C   FIELD 04w01 CC4G (wo): Capture/compare 4 generation
0x40000014 C   FIELD 06w01 TG (wo): Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40000018 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40000018 B  REGISTER CCMR1_Output (rw): capture/compare mode register 1 (output mode)
0x40000018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40000018 C   FIELD 00w02 CC1S: Capture/Compare 1 selection
0x40000018 C   FIELD 02w01 OC1FE: Output compare 1 fast enable
0x40000018 C   FIELD 02w02 IC1PSC: Input capture 1 prescaler
0x40000018 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40000018 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40000018 C   FIELD 04w04 IC1F: Input capture 1 filter
0x40000018 C   FIELD 07w01 OC1CE (rw): Output compare 1 clear enable
0x40000018 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40000018 C   FIELD 08w02 CC2S: Capture/compare 2 selection
0x40000018 C   FIELD 10w01 OC2FE: Output compare 2 fast enable
0x40000018 C   FIELD 10w02 IC2PSC: Input capture 2 prescaler
0x40000018 C   FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40000018 C   FIELD 12w03 OC2M (rw): Output compare 2 mode
0x40000018 C   FIELD 12w04 IC2F: Input capture 2 filter
0x40000018 C   FIELD 15w01 OC2CE (rw): Output compare 2 clear enable
0x40000018 C   FIELD 16w01 OC1M_3: Output compare 1 mode, bit 3
0x40000018 C   FIELD 24w01 OC2M_3: Output compare 2 mode, bit 3
0x4000001C B  REGISTER CCMR2_Input (rw): capture/compare mode register 2 (input mode)
0x4000001C B  REGISTER CCMR2_Output (rw): capture/compare mode register 2 (output mode)
0x4000001C C   FIELD 00w02 CC3S (=TIM2.CCMR1_Output.CC%sS): Capture/Compare 3 selection
0x4000001C C   FIELD 00w02 CC3S (rw): Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
0x4000001C C   FIELD 02w01 OC3FE (=TIM2.CCMR1_Output.OC%sFE): Output compare 3 fast enable
0x4000001C C   FIELD 02w02 IC3PSC (=TIM2.CCMR1_Input.IC%sPSC): Input capture 3 prescaler
0x4000001C C   FIELD 03w01 OC3PE (=TIM2.CCMR1_Output.OC%sPE): Output compare 3 preload enable
0x4000001C C   FIELD 04w03 OC3M (=TIM2.CCMR1_Output.OC%sM): Output compare 3 mode
0x4000001C C   FIELD 04w04 IC3F (=TIM2.CCMR1_Input.IC%sF): Input capture 3 filter
0x4000001C C   FIELD 07w01 OC3CE (=TIM2.CCMR1_Output.OC%sCE): Output compare 3 clear enable
0x4000001C C   FIELD 08w02 CC4S (=TIM2.CCMR1_Output.CC%sS): Capture/Compare 4 selection
0x4000001C C   FIELD 08w02 CC4S (rw): Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
0x4000001C C   FIELD 10w01 OC4FE (=TIM2.CCMR1_Output.OC%sFE): Output compare 4 fast enable
0x4000001C C   FIELD 10w02 IC4PSC (=TIM2.CCMR1_Input.IC%sPSC): Input capture 4 prescaler
0x4000001C C   FIELD 11w01 OC4PE (=TIM2.CCMR1_Output.OC%sPE): Output compare 4 preload enable
0x4000001C C   FIELD 12w03 OC4M (=TIM2.CCMR1_Output.OC%sM): Output compare 4 mode
0x4000001C C   FIELD 12w04 IC4F (=TIM2.CCMR1_Input.IC%sF): Input capture 4 filter
0x4000001C C   FIELD 15w01 OC4CE (=TIM2.CCMR1_Output.OC%sCE): Output compare 4 clear enable
0x4000001C C   FIELD 16w01 OC3M_3 (=TIM2.CCMR1_Output.OC%sM_3): Output compare 3 mode, bit 3
0x4000001C C   FIELD 24w01 OC4M_3 (=TIM2.CCMR1_Output.OC%sM_3): Output compare 4 mode, bit 3
0x40000020 B  REGISTER CCER (rw): capture/compare enable register
0x40000020 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40000020 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40000020 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40000020 C   FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable
0x40000020 C   FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity
0x40000020 C   FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity
0x40000020 C   FIELD 08w01 CC3E (rw): Capture/Compare 3 output enable
0x40000020 C   FIELD 09w01 CC3P (rw): Capture/Compare 3 output Polarity
0x40000020 C   FIELD 11w01 CC3NP (rw): Capture/Compare 3 output Polarity
0x40000020 C   FIELD 12w01 CC4E (rw): Capture/Compare 4 output enable
0x40000020 C   FIELD 13w01 CC4P (rw): Capture/Compare 4 output Polarity
0x40000020 C   FIELD 15w01 CC4NP (rw): Capture/Compare 4 output Polarity
0x40000024 B  REGISTER CNT (rw): counter
0x40000024 B  REGISTER CNT_ALTERNATE5 (rw): counter
0x40000024 C   FIELD 00w31 CNT (rw): Most significant part counter value (TIM2) nullLeast significant part of counter value
0x40000024 C   FIELD 00w32 CNT: Counter value
0x40000024 C   FIELD 31w01 UIFCPY (rw): UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register
0x40000028 B  REGISTER PSC (rw): prescaler
0x40000028 C   FIELD 00w16 PSC: Prescaler value
0x4000002C B  REGISTER ARR (rw): auto-reload register
0x4000002C C   FIELD 00w32 ARR (rw): High auto-reload value (TIM2) nullLow Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40000034 B  REGISTER CCR1 (rw): capture/compare register
0x40000034 C   FIELD 00w32 CCR (rw): Capture/Compare value
0x40000038 B  REGISTER CCR2 (rw): capture/compare register
0x40000038 C   FIELD 00w32 CCR (rw): Capture/Compare value
0x4000003C B  REGISTER CCR3 (rw): capture/compare register
0x4000003C C   FIELD 00w32 CCR (rw): Capture/Compare value
0x40000040 B  REGISTER CCR4 (rw): capture/compare register
0x40000040 C   FIELD 00w32 CCR (rw): Capture/Compare value
0x40000048 B  REGISTER DCR (rw): DMA control register
0x40000048 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0x40000048 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
0x4000004C B  REGISTER DMAR (rw): DMA address for full transfer
0x4000004C C   FIELD 00w16 DMAB: DMA register for burst accesses
0x40000050 B  REGISTER OR1 (rw): TIM option register
0x40000050 C   FIELD 00w01 OCREF_CLR (rw): Ocref_clr source selection This bit selects the ocref_clr input source.
0x40000060 B  REGISTER AF1 (rw): TIM alternate function option register 1
0x40000060 C   FIELD 14w04 ETRSEL (rw): ETR source selection These bits select the ETR input source. Others: Reserved
0x40000068 B  REGISTER TISEL (rw): TIM alternate function option register 1
0x40000068 C   FIELD 00w04 TI1SEL (rw): TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved
0x40000068 C   FIELD 08w04 TI2SEL (rw): TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved
0x40000400 A PERIPHERAL TIM3
0x40000400 B  REGISTER CR1 (rw): control register 1
0x40000400 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0x40000400 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40000400 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40000400 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40000400 C   FIELD 04w01 DIR (rw): Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
0x40000400 C   FIELD 05w02 CMS (rw): Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
0x40000400 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40000400 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),
0x40000400 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40000404 B  REGISTER CR2 (rw): control register 2
0x40000404 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40000404 C   FIELD 04w03 MMS (rw): Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40000404 C   FIELD 07w01 TI1S (rw): TI1 selection
0x40000408 B  REGISTER SMCR (rw): slave mode control register
0x40000408 C   FIELD 00w03 SMS1 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40000408 C   FIELD 03w01 OCCS (rw): OCREF clear selection This bit is used to select the OCREF clear source
0x40000408 C   FIELD 04w03 TS1 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40000408 C   FIELD 07w01 MSM (rw): Master/Slave mode
0x40000408 C   FIELD 08w04 ETF (rw): External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0x40000408 C   FIELD 12w02 ETPS (rw): External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
0x40000408 C   FIELD 14w01 ECE (rw): External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
0x40000408 C   FIELD 15w01 ETP (rw): External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
0x40000408 C   FIELD 16w01 SMS2 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40000408 C   FIELD 20w02 TS2 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x4000040C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4000040C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000040C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4000040C C   FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x4000040C C   FIELD 03w01 CC3IE (rw): Capture/Compare 3 interrupt enable
0x4000040C C   FIELD 04w01 CC4IE (rw): Capture/Compare 4 interrupt enable
0x4000040C C   FIELD 06w01 TIE (rw): Trigger interrupt enable
0x4000040C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4000040C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x4000040C C   FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x4000040C C   FIELD 11w01 CC3DE (rw): Capture/Compare 3 DMA request enable
0x4000040C C   FIELD 12w01 CC4DE (rw): Capture/Compare 4 DMA request enable
0x4000040C C   FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40000410 B  REGISTER SR (rw): status register
0x40000410 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40000410 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40000410 C   FIELD 02w01 CC2IF (rw): Capture/compare 2 interrupt flag
0x40000410 C   FIELD 03w01 CC3IF (rw): Capture/compare 3 interrupt flag
0x40000410 C   FIELD 04w01 CC4IF (rw): Capture/compare 4 interrupt flag
0x40000410 C   FIELD 06w01 TIF (rw): Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
0x40000410 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40000410 C   FIELD 10w01 CC2OF (rw): Capture/Compare 2 overcapture flag
0x40000410 C   FIELD 11w01 CC3OF (rw): Capture/Compare 3 overcapture flag
0x40000410 C   FIELD 12w01 CC4OF (rw): Capture/Compare 4 overcapture flag
0x40000414 B  REGISTER EGR (wo): event generation register
0x40000414 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40000414 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40000414 C   FIELD 02w01 CC2G (wo): Capture/compare 2 generation
0x40000414 C   FIELD 03w01 CC3G (wo): Capture/compare 3 generation
0x40000414 C   FIELD 04w01 CC4G (wo): Capture/compare 4 generation
0x40000414 C   FIELD 06w01 TG (wo): Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40000418 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40000418 B  REGISTER CCMR1_Output (rw): capture/compare mode register 1 (output mode)
0x40000418 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40000418 C   FIELD 00w02 CC1S: Capture/Compare 1 selection
0x40000418 C   FIELD 02w01 OC1FE: Output compare 1 fast enable
0x40000418 C   FIELD 02w02 IC1PSC: Input capture 1 prescaler
0x40000418 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40000418 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40000418 C   FIELD 04w04 IC1F: Input capture 1 filter
0x40000418 C   FIELD 07w01 OC1CE (rw): Output compare 1 clear enable
0x40000418 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40000418 C   FIELD 08w02 CC2S: Capture/compare 2 selection
0x40000418 C   FIELD 10w01 OC2FE: Output compare 2 fast enable
0x40000418 C   FIELD 10w02 IC2PSC: Input capture 2 prescaler
0x40000418 C   FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40000418 C   FIELD 12w03 OC2M (rw): Output compare 2 mode
0x40000418 C   FIELD 12w04 IC2F: Input capture 2 filter
0x40000418 C   FIELD 15w01 OC2CE (rw): Output compare 2 clear enable
0x40000418 C   FIELD 16w01 OC1M_3: Output compare 1 mode, bit 3
0x40000418 C   FIELD 24w01 OC2M_3: Output compare 2 mode, bit 3
0x4000041C B  REGISTER CCMR2_Input (rw): capture/compare mode register 2 (input mode)
0x4000041C B  REGISTER CCMR2_Output (rw): capture/compare mode register 2 (output mode)
0x4000041C C   FIELD 00w02 CC3S (=TIM3.CCMR1_Output.CC%sS): Capture/Compare 3 selection
0x4000041C C   FIELD 00w02 CC3S (rw): Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
0x4000041C C   FIELD 02w01 OC3FE (=TIM3.CCMR1_Output.OC%sFE): Output compare 3 fast enable
0x4000041C C   FIELD 02w02 IC3PSC (=TIM3.CCMR1_Input.IC%sPSC): Input capture 3 prescaler
0x4000041C C   FIELD 03w01 OC3PE (=TIM3.CCMR1_Output.OC%sPE): Output compare 3 preload enable
0x4000041C C   FIELD 04w03 OC3M (=TIM3.CCMR1_Output.OC%sM): Output compare 3 mode
0x4000041C C   FIELD 04w04 IC3F (=TIM3.CCMR1_Input.IC%sF): Input capture 3 filter
0x4000041C C   FIELD 07w01 OC3CE (=TIM3.CCMR1_Output.OC%sCE): Output compare 3 clear enable
0x4000041C C   FIELD 08w02 CC4S (=TIM3.CCMR1_Output.CC%sS): Capture/Compare 4 selection
0x4000041C C   FIELD 08w02 CC4S (rw): Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
0x4000041C C   FIELD 10w01 OC4FE (=TIM3.CCMR1_Output.OC%sFE): Output compare 4 fast enable
0x4000041C C   FIELD 10w02 IC4PSC (=TIM3.CCMR1_Input.IC%sPSC): Input capture 4 prescaler
0x4000041C C   FIELD 11w01 OC4PE (=TIM3.CCMR1_Output.OC%sPE): Output compare 4 preload enable
0x4000041C C   FIELD 12w03 OC4M (=TIM3.CCMR1_Output.OC%sM): Output compare 4 mode
0x4000041C C   FIELD 12w04 IC4F (=TIM3.CCMR1_Input.IC%sF): Input capture 4 filter
0x4000041C C   FIELD 15w01 OC4CE (=TIM3.CCMR1_Output.OC%sCE): Output compare 4 clear enable
0x4000041C C   FIELD 16w01 OC3M_3 (=TIM3.CCMR1_Output.OC%sM_3): Output compare 3 mode, bit 3
0x4000041C C   FIELD 24w01 OC4M_3 (=TIM3.CCMR1_Output.OC%sM_3): Output compare 4 mode, bit 3
0x40000420 B  REGISTER CCER (rw): capture/compare enable register
0x40000420 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40000420 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40000420 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40000420 C   FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable
0x40000420 C   FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity
0x40000420 C   FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity
0x40000420 C   FIELD 08w01 CC3E (rw): Capture/Compare 3 output enable
0x40000420 C   FIELD 09w01 CC3P (rw): Capture/Compare 3 output Polarity
0x40000420 C   FIELD 11w01 CC3NP (rw): Capture/Compare 3 output Polarity
0x40000420 C   FIELD 12w01 CC4E (rw): Capture/Compare 4 output enable
0x40000420 C   FIELD 13w01 CC4P (rw): Capture/Compare 4 output Polarity
0x40000420 C   FIELD 15w01 CC4NP (rw): Capture/Compare 4 output Polarity
0x40000424 B  REGISTER CNT (rw): counter
0x40000424 B  REGISTER CNT_ALTERNATE5 (rw): counter
0x40000424 C   FIELD 00w16 CNT: Counter value
0x40000424 C   FIELD 00w31 CNT (rw): Most significant part counter value (TIM2) nullLeast significant part of counter value
0x40000424 C   FIELD 31w01 UIFCPY (rw): UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register
0x40000428 B  REGISTER PSC (rw): prescaler
0x40000428 C   FIELD 00w16 PSC: Prescaler value
0x4000042C B  REGISTER ARR (rw): auto-reload register
0x4000042C C   FIELD 00w16 ARR (rw): High auto-reload value (TIM2) nullLow Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40000434 B  REGISTER CCR1 (rw): capture/compare register
0x40000434 C   FIELD 00w32 CCR (rw): Capture/Compare value
0x40000438 B  REGISTER CCR2 (rw): capture/compare register
0x40000438 C   FIELD 00w32 CCR (rw): Capture/Compare value
0x4000043C B  REGISTER CCR3 (rw): capture/compare register
0x4000043C C   FIELD 00w32 CCR (rw): Capture/Compare value
0x40000440 B  REGISTER CCR4 (rw): capture/compare register
0x40000440 C   FIELD 00w32 CCR (rw): Capture/Compare value
0x40000448 B  REGISTER DCR (rw): DMA control register
0x40000448 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0x40000448 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
0x4000044C B  REGISTER DMAR (rw): DMA address for full transfer
0x4000044C C   FIELD 00w16 DMAB: DMA register for burst accesses
0x40000450 B  REGISTER OR1 (rw): TIM option register
0x40000450 C   FIELD 00w01 OCREF_CLR (rw): Ocref_clr source selection This bit selects the ocref_clr input source.
0x40000460 B  REGISTER AF1 (rw): TIM alternate function option register 1
0x40000460 C   FIELD 14w04 ETRSEL (rw): ETR source selection These bits select the ETR input source. Others: Reserved
0x40000468 B  REGISTER TISEL (rw): TIM alternate function option register 1
0x40000468 C   FIELD 00w04 TI1SEL (rw): TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved
0x40000468 C   FIELD 08w04 TI2SEL (rw): TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved
0x40001000 A PERIPHERAL TIM6
0x40001000 B  REGISTER CR1 (rw): control register 1
0x40001000 C   FIELD 00w01 CEN (rw): Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0x40001000 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40001000 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40001000 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40001000 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40001000 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40001004 B  REGISTER CR2 (rw): control register 2
0x40001004 C   FIELD 04w03 MMS (rw): Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x4000100C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4000100C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000100C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x40001010 B  REGISTER SR (rw): status register
0x40001010 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40001014 B  REGISTER EGR (wo): event generation register
0x40001014 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40001024 B  REGISTER CNT (rw): counter
0x40001024 C   FIELD 00w16 CNT (rw): Counter value
0x40001024 C   FIELD 31w01 UIFCPY (ro): UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.
0x40001028 B  REGISTER PSC (rw): prescaler
0x40001028 C   FIELD 00w16 PSC: Prescaler value
0x4000102C B  REGISTER ARR (rw): auto-reload register
0x4000102C C   FIELD 00w16 ARR: Prescaler value
0x40001400 A PERIPHERAL TIM7
0x40001400 B  REGISTER CR1 (rw): control register 1
0x40001400 C   FIELD 00w01 CEN (rw): Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0x40001400 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40001400 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40001400 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40001400 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40001400 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40001404 B  REGISTER CR2 (rw): control register 2
0x40001404 C   FIELD 04w03 MMS (rw): Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x4000140C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4000140C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000140C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x40001410 B  REGISTER SR (rw): status register
0x40001410 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40001414 B  REGISTER EGR (wo): event generation register
0x40001414 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40001424 B  REGISTER CNT (rw): counter
0x40001424 C   FIELD 00w16 CNT (rw): Counter value
0x40001424 C   FIELD 31w01 UIFCPY (ro): UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.
0x40001428 B  REGISTER PSC (rw): prescaler
0x40001428 C   FIELD 00w16 PSC: Prescaler value
0x4000142C B  REGISTER ARR (rw): auto-reload register
0x4000142C C   FIELD 00w16 ARR: Prescaler value
0x40002000 A PERIPHERAL TIM14
0x40002000 B  REGISTER CR1 (rw): control register 1
0x40002000 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40002000 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values.
0x40002000 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit
0x40002000 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40002000 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40002000 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),
0x40002000 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x4000200C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4000200C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4000200C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x40002010 B  REGISTER SR (rw): status register
0x40002010 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS='0' in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS='0' and UDIS='0' in the TIMx_CR1 register.
0x40002010 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40002010 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40002014 B  REGISTER EGR (wo): event generation register
0x40002014 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40002014 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40002018 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40002018 B  REGISTER CCMR1_Output (rw): capture/compare mode register 1 (output mode)
0x40002018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40002018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0x40002018 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40002018 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40002018 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40002018 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40002018 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40002018 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40002020 B  REGISTER CCER (rw): capture/compare enable register
0x40002020 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40002020 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40002020 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40002024 B  REGISTER CNT (rw): counter
0x40002024 C   FIELD 00w16 CNT: low counter value
0x40002024 C   FIELD 31w01 UIFCPY: UIF Copy
0x40002028 B  REGISTER PSC (rw): prescaler
0x40002028 C   FIELD 00w16 PSC: Prescaler value
0x4000202C B  REGISTER ARR (rw): auto-reload register
0x4000202C C   FIELD 00w16 ARR: Low Auto-reload value
0x40002034 B  REGISTER CCR1 (rw): capture/compare register
0x40002034 C   FIELD 00w16 CCR: Capture/Compare value
0x40002068 B  REGISTER TISEL (rw): TIM timer input selection register
0x40002068 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40002800 A PERIPHERAL RTC
0x40002800 B  REGISTER TR: RTC time register
0x40002800 C   FIELD 00w04 SU (rw): Second units in BCD format
0x40002800 C   FIELD 04w03 ST (rw): Second tens in BCD format
0x40002800 C   FIELD 08w04 MNU (rw): Minute units in BCD format
0x40002800 C   FIELD 12w03 MNT (rw): Minute tens in BCD format
0x40002800 C   FIELD 16w04 HU (rw): Hour units in BCD format
0x40002800 C   FIELD 20w02 HT (rw): Hour tens in BCD format
0x40002800 C   FIELD 22w01 PM (rw): AM/PM notation
0x40002804 B  REGISTER DR: RTC date register
0x40002804 C   FIELD 00w04 DU (rw): Date units in BCD format
0x40002804 C   FIELD 04w02 DT (rw): Date tens in BCD format
0x40002804 C   FIELD 08w04 MU (rw): Month units in BCD format
0x40002804 C   FIELD 12w01 MT (rw): Month tens in BCD format
0x40002804 C   FIELD 13w03 WDU (rw): Week day units ...
0x40002804 C   FIELD 16w04 YU (rw): Year units in BCD format
0x40002804 C   FIELD 20w04 YT (rw): Year tens in BCD format
0x40002808 B  REGISTER SSR: RTC sub second register
0x40002808 C   FIELD 00w16 SS (ro): Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR.
0x4000280C B  REGISTER ICSR: RTC initialization control and status register
0x4000280C C   FIELD 00w01 ALRAWF (ro): Alarm A write flag
0x4000280C C   FIELD 01w01 ALRBWF (ro): Alarm B write flag
0x4000280C C   FIELD 02w01 WUTWF (ro): Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
0x4000280C C   FIELD 03w01 SHPF (ro): Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
0x4000280C C   FIELD 04w01 INITS (ro): Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (RTC domain reset state).
0x4000280C C   FIELD 05w01 RSF (rw): Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
0x4000280C C   FIELD 06w01 INITF (ro): Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
0x4000280C C   FIELD 07w01 INIT (rw): Initialization mode
0x4000280C C   FIELD 16w01 RECALPF (ro): Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to .
0x40002810 B  REGISTER PRER: RTC prescaler register
0x40002810 C   FIELD 00w15 PREDIV_S (rw): Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
0x40002810 C   FIELD 16w07 PREDIV_A (rw): Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
0x40002814 B  REGISTER WUTR: RTC wakeup timer register
0x40002814 C   FIELD 00w16 WUT (rw): Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]+1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden.
0x40002818 B  REGISTER CR: RTC control register
0x40002818 C   FIELD 00w03 WUCKSEL (rw): ck_wut wakeup clock selection 10x: ck_spre (usually 1Hz) clock is selected 11x: ck_spre (usually 1Hz) clock is selected and 216is added to the WUT counter value
0x40002818 C   FIELD 03w01 TSEDGE (rw): Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
0x40002818 C   FIELD 04w01 REFCKON (rw): RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF.
0x40002818 C   FIELD 05w01 BYPSHAD (rw): Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
0x40002818 C   FIELD 06w01 FMT (rw): Hour format
0x40002818 C   FIELD 08w01 ALRAE (rw): Alarm A enable
0x40002818 C   FIELD 09w01 ALRBE (rw): Alarm B enable
0x40002818 C   FIELD 10w01 WUTE (rw): Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
0x40002818 C   FIELD 11w01 TSE (rw): timestamp enable
0x40002818 C   FIELD 12w01 ALRAIE (rw): Alarm A interrupt enable
0x40002818 C   FIELD 13w01 ALRBIE (rw): Alarm B interrupt enable
0x40002818 C   FIELD 14w01 WUTIE (rw): Wakeup timer interrupt enable
0x40002818 C   FIELD 15w01 TSIE (rw): Timestamp interrupt enable
0x40002818 C   FIELD 16w01 ADD1H (wo): Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.
0x40002818 C   FIELD 17w01 SUB1H (wo): Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.
0x40002818 C   FIELD 18w01 BKP (rw): Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
0x40002818 C   FIELD 19w01 COSEL (rw): Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to .
0x40002818 C   FIELD 20w01 POL (rw): Output polarity This bit is used to configure the polarity of TAMPALRM output.
0x40002818 C   FIELD 21w02 OSEL (rw): Output selection These bits are used to select the flag to be routed to TAMPALRM output.
0x40002818 C   FIELD 23w01 COE (rw): Calibration output enable This bit enables the CALIB output
0x40002818 C   FIELD 24w01 ITSE (rw): timestamp on internal event enable
0x40002818 C   FIELD 25w01 TAMPTS (rw): Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts.
0x40002818 C   FIELD 26w01 TAMPOE (rw): Tamper detection output enable on TAMPALRM
0x40002818 C   FIELD 29w01 TAMPALRM_PU (rw): TAMPALRM pull-up enable
0x40002818 C   FIELD 30w01 TAMPALRM_TYPE (rw): TAMPALRM output type
0x40002818 C   FIELD 31w01 OUT2EN (rw): RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2
0x40002824 B  REGISTER WPR: RTC write protection register
0x40002824 C   FIELD 00w08 KEY (wo): Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to for a description of how to unlock RTC register write protection.
0x40002828 B  REGISTER CALR: RTC calibration register
0x40002828 C   FIELD 00w09 CALM (rw): Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768Hz). This decreases the frequency of the calendar with a resolution of 0.9537ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See .
0x40002828 C   FIELD 13w01 CALW16 (rw): Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration.
0x40002828 C   FIELD 14w01 CALW8 (rw): Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration.
0x40002828 C   FIELD 15w01 CALP (rw): Increase frequency of RTC by 488
0x4000282C B  REGISTER SHIFTR: RTC shift control register
0x4000282C C   FIELD 00w15 SUBFS (wo): Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time.
0x4000282C C   FIELD 31w01 ADD1S (wo): Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.
0x40002830 B  REGISTER TSTR (=TR): RTC timestamp time register
0x40002834 B  REGISTER TSDR (=DR): RTC timestamp date register
0x40002838 B  REGISTER TSSSR (=SSR): RTC timestamp sub second register
0x40002840 B  REGISTER ALRMAR: Alarm A register
0x40002840 C   FIELD 00w04 SU (rw): Second units in BCD format
0x40002840 C   FIELD 04w03 ST (rw): Second tens in BCD format
0x40002840 C   FIELD 07w01 MSK1 (rw): Alarm seconds mask
0x40002840 C   FIELD 08w04 MNU (rw): Minute units in BCD format
0x40002840 C   FIELD 12w03 MNT (rw): Minute tens in BCD format
0x40002840 C   FIELD 15w01 MSK2 (rw): Alarm minutes mask
0x40002840 C   FIELD 16w04 HU (rw): Hour units in BCD format
0x40002840 C   FIELD 20w02 HT (rw): Hour tens in BCD format
0x40002840 C   FIELD 22w01 PM (rw): AM/PM notation
0x40002840 C   FIELD 23w01 MSK3 (rw): Alarm hours mask
0x40002840 C   FIELD 24w04 DU (rw): Date units or day in BCD format
0x40002840 C   FIELD 28w02 DT (rw): Date tens in BCD format
0x40002840 C   FIELD 30w01 WDSEL (rw): Week day selection
0x40002840 C   FIELD 31w01 MSK4 (rw): Alarm date mask
0x40002844 B  REGISTER ALRMASSR: Alarm A sub-second register
0x40002844 C   FIELD 00w15 SS (rw): Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
0x40002844 C   FIELD 24w04 MASKSS (rw): Mask the most-significant bits starting at this bit 2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.
0x40002848 B  REGISTER ALRMBR: Alarm B register
0x40002848 C   FIELD 00w04 SU (rw): Second units in BCD format
0x40002848 C   FIELD 04w03 ST (rw): Second tens in BCD format
0x40002848 C   FIELD 07w01 MSK1 (rw): Alarm seconds mask
0x40002848 C   FIELD 08w04 MNU (rw): Minute units in BCD format
0x40002848 C   FIELD 12w03 MNT (rw): Minute tens in BCD format
0x40002848 C   FIELD 15w01 MSK2 (rw): Alarm minutes mask
0x40002848 C   FIELD 16w04 HU (rw): Hour units in BCD format
0x40002848 C   FIELD 20w02 HT (rw): Hour tens in BCD format
0x40002848 C   FIELD 22w01 PM (rw): AM/PM notation
0x40002848 C   FIELD 23w01 MSK3 (rw): Alarm hours mask
0x40002848 C   FIELD 24w04 DU (rw): Date units or day in BCD format
0x40002848 C   FIELD 28w02 DT (rw): Date tens in BCD format
0x40002848 C   FIELD 30w01 WDSEL (rw): Week day selection
0x40002848 C   FIELD 31w01 MSK4 (rw): Alarm date mask
0x4000284C B  REGISTER ALRMBSSR: Alarm B sub-second register
0x4000284C C   FIELD 00w15 SS (rw): Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
0x4000284C C   FIELD 24w04 MASKSS (rw): Mask the most-significant bits starting at this bit 2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.
0x40002850 B  REGISTER SR: RTC status register
0x40002850 C   FIELD 00w01 ALRAF (ro): Alarm A flag
0x40002850 C   FIELD 01w01 ALRBF (ro): Alarm B flag
0x40002850 C   FIELD 02w01 WUTF (ro): Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
0x40002850 C   FIELD 03w01 TSF (ro): Timestamp flag This flag is set by hardware when a timestamp event occurs. If ITSF flag is set, TSF must be cleared together with ITSF.
0x40002850 C   FIELD 04w01 TSOVF (ro): Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
0x40002850 C   FIELD 05w01 ITSF (ro): Internal timestamp flag This flag is set by hardware when a timestamp on the internal event occurs.
0x40002854 B  REGISTER MISR: RTC masked interrupt status register
0x40002854 C   FIELD 00w01 ALRAMF (ro): Alarm A masked flag
0x40002854 C   FIELD 01w01 ALRBMF (ro): Alarm B masked flag
0x40002854 C   FIELD 02w01 WUTMF (ro): Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
0x40002854 C   FIELD 03w01 TSMF (ro): Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF.
0x40002854 C   FIELD 04w01 TSOVMF (ro): Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
0x40002854 C   FIELD 05w01 ITSMF (ro): Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised.
0x4000285C B  REGISTER SCR: RTC status clear register
0x4000285C C   FIELD 00w01 CALRAF (wo): Clear alarm A flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.
0x4000285C C   FIELD 01w01 CALRBF (wo): Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.
0x4000285C C   FIELD 02w01 CWUTF (wo): Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register.
0x4000285C C   FIELD 03w01 CTSF (wo): Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF.
0x4000285C C   FIELD 04w01 CTSOVF (wo): Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
0x4000285C C   FIELD 05w01 CITSF (wo): Clear internal timestamp flag Writing 1 in this bit clears the ITSF bit in the RTC_SR register.
0x40002C00 A PERIPHERAL WWDG
0x40002C00 B  REGISTER CR (rw): Control register
0x40002C00 C   FIELD 00w07 T (rw): 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared).
0x40002C00 C   FIELD 07w01 WDGA (rw): Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset.
0x40002C04 B  REGISTER CFR (rw): Configuration register
0x40002C04 C   FIELD 00w07 W (rw): 7-bit window value These bits contain the window value to be compared with the down-counter.
0x40002C04 C   FIELD 09w01 EWI (rw): Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset.
0x40002C04 C   FIELD 11w03 WDGTB: Timer base The timebase of the prescaler can be modified as follows:
0x40002C08 B  REGISTER SR (rw): Status register
0x40002C08 C   FIELD 00w01 EWIF: Early wakeup interrupt flag
0x40003000 A PERIPHERAL IWDG
0x40003000 B  REGISTER KR (wo): Key register
0x40003000 C   FIELD 00w16 KEY: Key value (write only, read 0x0000)
0x40003004 B  REGISTER PR (rw): Prescaler register
0x40003004 C   FIELD 00w03 PR (rw): Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset.
0x40003008 B  REGISTER RLR (rw): Reload register
0x40003008 C   FIELD 00w12 RL: Watchdog counter reload value
0x4000300C B  REGISTER SR (ro): Status register
0x4000300C C   FIELD 00w01 PVU (ro): Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset.
0x4000300C C   FIELD 01w01 RVU (ro): Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset.
0x4000300C C   FIELD 02w01 WVU (ro): Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset.
0x40003010 B  REGISTER WINR (rw): Window register
0x40003010 C   FIELD 00w12 WIN: Watchdog counter window value
0x40003800 A PERIPHERAL SPI2
0x40004400 A PERIPHERAL USART2
0x40004400 B  REGISTER CR1 (rw): Control register 1
0x40004400 C   FIELD 00w01 UE (rw): USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
0x40004400 C   FIELD 01w01 UESM (rw): USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 02w01 RE (rw): Receiver enable This bit enables the receiver. It is set and cleared by software.
0x40004400 C   FIELD 03w01 TE (rw): Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
0x40004400 C   FIELD 04w01 IDLEIE (rw): IDLE interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 05w01 RXNEIE (rw): RXFIFO not empty interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 06w01 TCIE (rw): Transmission complete interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 07w01 TXEIE (rw): TXFIFO not full interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 08w01 PEIE (rw): PE interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 09w01 PS (rw): Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE=0).
0x40004400 C   FIELD 10w01 PCE (rw): Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE=0).
0x40004400 C   FIELD 11w01 WAKE (rw): Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE=0).
0x40004400 C   FIELD 12w01 M0 (rw): Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE=0).
0x40004400 C   FIELD 13w01 MME (rw): Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0x40004400 C   FIELD 14w01 CMIE (rw): Character match interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 15w01 OVER8 (rw): Oversampling mode This bit can only be written when the USART is disabled (UE=0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
0x40004400 C   FIELD 16w05 DEDT (rw): Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 21w05 DEAT (rw): Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 26w01 RTOIE (rw): Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
0x40004400 C   FIELD 27w01 EOBIE (rw): End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004400 C   FIELD 28w01 M1 (rw): Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
0x40004400 C   FIELD 29w01 FIFOEN (rw): FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
0x40004400 C   FIELD 30w01 TXFEIE (rw): TXFIFO empty interrupt enable This bit is set and cleared by software.
0x40004400 C   FIELD 31w01 RXFFIE (rw): RXFIFO Full interrupt enable This bit is set and cleared by software.
0x40004404 B  REGISTER CR2 (rw): Control register 2
0x40004404 C   FIELD 00w01 SLVEN (rw): Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 03w01 DIS_NSS (rw): When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 04w01 ADDM7 (rw): 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
0x40004404 C   FIELD 05w01 LBDL (rw): LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 06w01 LBDIE (rw): LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 08w01 LBCL (rw): Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 09w01 CPHA (rw): Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 10w01 CPOL (rw): Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 11w01 CLKEN (rw): Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UE=0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1
0x40004404 C   FIELD 12w02 STOP (rw): stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE=0).
0x40004404 C   FIELD 14w01 LINEN (rw): LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 15w01 SWAP (rw): Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0).
0x40004404 C   FIELD 16w01 RXINV (rw): RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE=0).
0x40004404 C   FIELD 17w01 TXINV (rw): TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE=0).
0x40004404 C   FIELD 18w01 DATAINV (rw): Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0).
0x40004404 C   FIELD 19w01 MSBFIRST (rw): Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0).
0x40004404 C   FIELD 20w01 ABREN (rw): Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 21w02 ABRMOD (rw): Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 23w01 RTOEN (rw): Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004404 C   FIELD 24w08 ADD (rw): Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0).
0x40004408 B  REGISTER CR3 (rw): Control register 3
0x40004408 C   FIELD 00w01 EIE (rw): Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1 or UDR = 1 in the USART_ISR register).
0x40004408 C   FIELD 01w01 IREN (rw): IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 02w01 IRLP (rw): IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 03w01 HDSEL (rw): Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE=0).
0x40004408 C   FIELD 04w01 NACK (rw): Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 05w01 SCEN (rw): Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 06w01 DMAR (rw): DMA enable receiver This bit is set/reset by software
0x40004408 C   FIELD 07w01 DMAT (rw): DMA enable transmitter This bit is set/reset by software
0x40004408 C   FIELD 08w01 RTSE (rw): RTS enable This bit can only be written when the USART is disabled (UE=0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 09w01 CTSE (rw): CTS enable This bit can only be written when the USART is disabled (UE=0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 10w01 CTSIE (rw): CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 11w01 ONEBIT (rw): One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE=0).
0x40004408 C   FIELD 12w01 OVRDIS (rw): Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data
0x40004408 C   FIELD 13w01 DDRE (rw): DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
0x40004408 C   FIELD 14w01 DEM (rw): Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .
0x40004408 C   FIELD 15w01 DEP (rw): Driver enable polarity selection This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 17w03 SCARCNT (rw): Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE=0). When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 20w02 WUS (rw): Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE=0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page835.
0x40004408 C   FIELD 22w01 WUFIE (rw): Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page835.
0x40004408 C   FIELD 23w01 TXFTIE (rw): TXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40004408 C   FIELD 24w01 TCBGTIE (rw): Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004408 C   FIELD 25w03 RXFTCFG (rw): Receive FIFO threshold configuration Remaining combinations: Reserved
0x40004408 C   FIELD 28w01 RXFTIE (rw): RXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40004408 C   FIELD 29w03 TXFTCFG (rw): TXFIFO threshold configuration Remaining combinations: Reserved
0x4000440C B  REGISTER BRR (rw): Baud rate register
0x4000440C C   FIELD 00w16 BRR (rw): USART baud rate
0x40004410 B  REGISTER GTPR (rw): Guard time and prescaler register
0x40004410 C   FIELD 00w08 PSC (rw): Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]=Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 00100000: Divides the source clock by 32 (IrDA mode) ... 11111111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE=0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0' when the Smartcard and IrDA modes are not supported. Refer to .
0x40004410 C   FIELD 08w08 GT (rw): Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE=0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004414 B  REGISTER RTOR (rw): Receiver timeout register
0x40004414 C   FIELD 00w24 RTO: Receiver timeout value
0x40004414 C   FIELD 24w08 BLEN: Block Length
0x40004418 B  REGISTER RQR (wo): Request register
0x40004418 C   FIELD 00w01 ABRRQ (wo): Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40004418 C   FIELD 01w01 SBKRQ (wo): Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
0x40004418 C   FIELD 02w01 MMRQ (wo): Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
0x40004418 C   FIELD 03w01 RXFRQ (wo): Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition.
0x40004418 C   FIELD 04w01 TXFRQ (wo): Transmit data flush request When FIFO mode is disabled, writing '1' to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
0x4000441C B  REGISTER ISR (ro): Interrupt & status register
0x4000441C C   FIELD 00w01 PE (ro): Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4000441C C   FIELD 01w01 FE (ro): Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE=1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4000441C C   FIELD 02w01 NE (ro): Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page861). This error is associated with the character in the USART_RDR.
0x4000441C C   FIELD 03w01 ORE (ro): Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE=1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
0x4000441C C   FIELD 04w01 IDLE (ro): Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set.
0x4000441C C   FIELD 05w01 RXFNE (ro): RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE=1 in the USART_CR1 register.
0x4000441C C   FIELD 06w01 TC (ro): Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
0x4000441C C   FIELD 07w01 TXFNF (ro): TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.
0x4000441C C   FIELD 08w01 LBDF (ro): LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 09w01 CTSIF (ro): CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 10w01 CTS (ro): CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 11w01 RTOF (ro): Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 12w01 EOBF (ro): End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE=1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 13w01 UDR (ro): SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 14w01 ABRE (ro): Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 15w01 ABRF (ro): Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000441C C   FIELD 16w01 BUSY (ro): Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
0x4000441C C   FIELD 17w01 CMF (ro): Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register.
0x4000441C C   FIELD 18w01 SBKF (ro): Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
0x4000441C C   FIELD 19w01 RWU (ro): Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 20w01 WUF (ro): Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE=1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 21w01 TEACK (ro): Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period.
0x4000441C C   FIELD 22w01 REACK (ro): Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000441C C   FIELD 23w01 TXFE (ro): TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register.
0x4000441C C   FIELD 24w01 RXFF (ro): RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFOsize+1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register.
0x4000441C C   FIELD 25w01 TCBGT (ro): Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1'. Refer to on page835.
0x4000441C C   FIELD 26w01 RXFT (ro): RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101', RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
0x4000441C C   FIELD 27w01 TXFT (ro): TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register.
0x40004420 B  REGISTER ICR (wo): Interrupt flag clear register
0x40004420 C   FIELD 00w01 PECF (wo): Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
0x40004420 C   FIELD 01w01 FECF (wo): Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
0x40004420 C   FIELD 02w01 NECF (wo): Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
0x40004420 C   FIELD 03w01 ORECF (wo): Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
0x40004420 C   FIELD 04w01 IDLECF (wo): Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
0x40004420 C   FIELD 05w01 TXFECF (wo): TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
0x40004420 C   FIELD 06w01 TCCF (wo): Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
0x40004420 C   FIELD 07w01 TCBGTCF (wo): Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
0x40004420 C   FIELD 08w01 LBDCF (wo): LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004420 C   FIELD 09w01 CTSCF (wo): CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40004420 C   FIELD 11w01 RTOCF (wo): Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page835.
0x40004420 C   FIELD 12w01 EOBCF (wo): End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40004420 C   FIELD 13w01 UDRCF (wo): SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to
0x40004420 C   FIELD 17w01 CMCF (wo): Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
0x40004420 C   FIELD 20w01 WUCF (wo): Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page835.
0x40004424 B  REGISTER RDR (ro): Receive data register
0x40004424 C   FIELD 00w09 RDR: Receive data value
0x40004428 B  REGISTER TDR (rw): Transmit data register
0x40004428 C   FIELD 00w09 TDR: Transmit data value
0x4000442C B  REGISTER PRESC (rw): Prescaler register
0x4000442C C   FIELD 00w04 PRESCALER (rw): Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
0x40005400 A PERIPHERAL I2C1
0x40005400 B  REGISTER CR1 (rw): Control register 1
0x40005400 C   FIELD 00w01 PE (rw): Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
0x40005400 C   FIELD 01w01 TXIE (rw): TX Interrupt enable
0x40005400 C   FIELD 02w01 RXIE (rw): RX Interrupt enable
0x40005400 C   FIELD 03w01 ADDRIE (rw): Address match Interrupt enable (slave only)
0x40005400 C   FIELD 04w01 NACKIE (rw): Not acknowledge received Interrupt enable
0x40005400 C   FIELD 05w01 STOPIE (rw): Stop detection Interrupt enable
0x40005400 C   FIELD 06w01 TCIE (rw): Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
0x40005400 C   FIELD 07w01 ERRIE (rw): Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
0x40005400 C   FIELD 08w04 DNF (rw): Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
0x40005400 C   FIELD 12w01 ANFOFF (rw): Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
0x40005400 C   FIELD 14w01 TXDMAEN (rw): DMA transmission requests enable
0x40005400 C   FIELD 15w01 RXDMAEN (rw): DMA reception requests enable
0x40005400 C   FIELD 16w01 SBC (rw): Slave byte control This bit is used to enable hardware byte control in slave mode.
0x40005400 C   FIELD 17w01 NOSTRETCH (rw): Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
0x40005400 C   FIELD 18w01 WUPEN (rw): Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . Note: WUPEN can be set only when DNF = '0000'
0x40005400 C   FIELD 19w01 GCEN (rw): General call enable
0x40005400 C   FIELD 20w01 SMBHEN (rw): SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
0x40005400 C   FIELD 21w01 SMBDEN (rw): SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
0x40005400 C   FIELD 22w01 ALERTEN (rw): SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
0x40005400 C   FIELD 23w01 PECEN (rw): PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
0x40005404 B  REGISTER CR2 (rw): Control register 2
0x40005404 C   FIELD 00w10 SADD (rw): Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
0x40005404 C   FIELD 10w01 RD_WRN (rw): Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C   FIELD 11w01 ADD10 (rw): 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C   FIELD 12w01 HEAD10R (rw): 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C   FIELD 13w01 START (rw): Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1' to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0' to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
0x40005404 C   FIELD 14w01 STOP (rw): Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0' to this bit has no effect.
0x40005404 C   FIELD 15w01 NACK (rw): NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0' to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
0x40005404 C   FIELD 16w08 NBYTES (rw): Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
0x40005404 C   FIELD 24w01 RELOAD (rw): NBYTES reload mode This bit is set and cleared by software.
0x40005404 C   FIELD 25w01 AUTOEND (rw): Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
0x40005404 C   FIELD 26w01 PECBYTE (rw): Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0' to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
0x40005408 B  REGISTER OAR1 (rw): Own address register 1
0x40005408 C   FIELD 00w10 OA1 (rw): Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
0x40005408 C   FIELD 10w01 OA1MODE (rw): Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
0x40005408 C   FIELD 15w01 OA1EN (rw): Own Address 1 enable
0x4000540C B  REGISTER OAR2 (rw): Own address register 2
0x4000540C C   FIELD 01w07 OA2 (rw): Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0.
0x4000540C C   FIELD 08w03 OA2MSK (rw): Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches.
0x4000540C C   FIELD 15w01 OA2EN (rw): Own Address 2 enable
0x40005410 B  REGISTER TIMINGR (rw): Timing register
0x40005410 C   FIELD 00w08 SCLL: SCL low period (master mode)
0x40005410 C   FIELD 08w08 SCLH: SCL high period (master mode)
0x40005410 C   FIELD 16w04 SDADEL: Data hold time
0x40005410 C   FIELD 20w04 SCLDEL: Data setup time
0x40005410 C   FIELD 28w04 PRESC: Timing prescaler
0x40005414 B  REGISTER TIMEOUTR (rw): Status register 1
0x40005414 C   FIELD 00w12 TIMEOUTA (rw): Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0.
0x40005414 C   FIELD 12w01 TIDLE (rw): Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
0x40005414 C   FIELD 15w01 TIMOUTEN (rw): Clock timeout enable
0x40005414 C   FIELD 16w12 TIMEOUTB (rw): Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0.
0x40005414 C   FIELD 31w01 TEXTEN (rw): Extended clock timeout enable
0x40005418 B  REGISTER ISR: Interrupt and Status register
0x40005418 C   FIELD 00w01 TXE (rw): Transmit data register empty (transmitters)
0x40005418 C   FIELD 01w01 TXIS (rw): Transmit interrupt status (transmitters)
0x40005418 C   FIELD 02w01 RXNE (ro): Receive data register not empty (receivers)
0x40005418 C   FIELD 03w01 ADDR (ro): Address matched (slave mode)
0x40005418 C   FIELD 04w01 NACKF (ro): Not acknowledge received flag
0x40005418 C   FIELD 05w01 STOPF (ro): Stop detection flag
0x40005418 C   FIELD 06w01 TC (ro): Transfer Complete (master mode)
0x40005418 C   FIELD 07w01 TCR (ro): Transfer Complete Reload
0x40005418 C   FIELD 08w01 BERR (ro): Bus error
0x40005418 C   FIELD 09w01 ARLO (ro): Arbitration lost
0x40005418 C   FIELD 10w01 OVR (ro): Overrun/Underrun (slave mode)
0x40005418 C   FIELD 11w01 PECERR (ro): PEC Error in reception
0x40005418 C   FIELD 12w01 TIMEOUT (ro): Timeout or t_low detection flag
0x40005418 C   FIELD 13w01 ALERT (ro): SMBus alert
0x40005418 C   FIELD 15w01 BUSY (ro): Bus busy
0x40005418 C   FIELD 16w01 DIR (ro): Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1).
0x40005418 C   FIELD 17w07 ADDCODE (ro): Address match code (Slave mode)
0x4000541C B  REGISTER ICR (wo): Interrupt clear register
0x4000541C C   FIELD 03w01 ADDRCF: Address Matched flag clear
0x4000541C C   FIELD 04w01 NACKCF: Not Acknowledge flag clear
0x4000541C C   FIELD 05w01 STOPCF: Stop detection flag clear
0x4000541C C   FIELD 08w01 BERRCF: Bus error flag clear
0x4000541C C   FIELD 09w01 ARLOCF: Arbitration lost flag clear
0x4000541C C   FIELD 10w01 OVRCF: Overrun/Underrun flag clear
0x4000541C C   FIELD 11w01 PECCF: PEC Error flag clear
0x4000541C C   FIELD 12w01 TIMOUTCF: Timeout detection flag clear
0x4000541C C   FIELD 13w01 ALERTCF: Alert flag clear
0x40005420 B  REGISTER PECR (ro): PEC register
0x40005420 C   FIELD 00w08 PEC: Packet error checking register
0x40005424 B  REGISTER RXDR (ro): Receive data register
0x40005424 C   FIELD 00w08 RXDATA: 8-bit receive data
0x40005428 B  REGISTER TXDR (rw): Transmit data register
0x40005428 C   FIELD 00w08 TXDATA: 8-bit transmit data
0x40005800 A PERIPHERAL I2C2
0x40005800 B  REGISTER CR1 (rw): Control register 1
0x40005800 C   FIELD 00w01 PE (rw): Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
0x40005800 C   FIELD 01w01 TXIE (rw): TX Interrupt enable
0x40005800 C   FIELD 02w01 RXIE (rw): RX Interrupt enable
0x40005800 C   FIELD 03w01 ADDRIE (rw): Address match Interrupt enable (slave only)
0x40005800 C   FIELD 04w01 NACKIE (rw): Not acknowledge received Interrupt enable
0x40005800 C   FIELD 05w01 STOPIE (rw): Stop detection Interrupt enable
0x40005800 C   FIELD 06w01 TCIE (rw): Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
0x40005800 C   FIELD 07w01 ERRIE (rw): Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
0x40005800 C   FIELD 08w04 DNF (rw): Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
0x40005800 C   FIELD 12w01 ANFOFF (rw): Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
0x40005800 C   FIELD 14w01 TXDMAEN (rw): DMA transmission requests enable
0x40005800 C   FIELD 15w01 RXDMAEN (rw): DMA reception requests enable
0x40005800 C   FIELD 16w01 SBC (rw): Slave byte control This bit is used to enable hardware byte control in slave mode.
0x40005800 C   FIELD 17w01 NOSTRETCH (rw): Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
0x40005800 C   FIELD 18w01 WUPEN (rw): Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . Note: WUPEN can be set only when DNF = '0000'
0x40005800 C   FIELD 19w01 GCEN (rw): General call enable
0x40005800 C   FIELD 20w01 SMBHEN (rw): SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
0x40005800 C   FIELD 21w01 SMBDEN (rw): SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
0x40005800 C   FIELD 22w01 ALERTEN (rw): SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
0x40005800 C   FIELD 23w01 PECEN (rw): PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
0x40005804 B  REGISTER CR2 (rw): Control register 2
0x40005804 C   FIELD 00w10 SADD (rw): Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
0x40005804 C   FIELD 10w01 RD_WRN (rw): Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005804 C   FIELD 11w01 ADD10 (rw): 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005804 C   FIELD 12w01 HEAD10R (rw): 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005804 C   FIELD 13w01 START (rw): Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1' to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0' to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
0x40005804 C   FIELD 14w01 STOP (rw): Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0' to this bit has no effect.
0x40005804 C   FIELD 15w01 NACK (rw): NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0' to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
0x40005804 C   FIELD 16w08 NBYTES (rw): Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
0x40005804 C   FIELD 24w01 RELOAD (rw): NBYTES reload mode This bit is set and cleared by software.
0x40005804 C   FIELD 25w01 AUTOEND (rw): Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
0x40005804 C   FIELD 26w01 PECBYTE (rw): Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0' to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
0x40005808 B  REGISTER OAR1 (rw): Own address register 1
0x40005808 C   FIELD 00w10 OA1 (rw): Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
0x40005808 C   FIELD 10w01 OA1MODE (rw): Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
0x40005808 C   FIELD 15w01 OA1EN (rw): Own Address 1 enable
0x4000580C B  REGISTER OAR2 (rw): Own address register 2
0x4000580C C   FIELD 01w07 OA2 (rw): Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0.
0x4000580C C   FIELD 08w03 OA2MSK (rw): Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches.
0x4000580C C   FIELD 15w01 OA2EN (rw): Own Address 2 enable
0x40005810 B  REGISTER TIMINGR (rw): Timing register
0x40005810 C   FIELD 00w08 SCLL: SCL low period (master mode)
0x40005810 C   FIELD 08w08 SCLH: SCL high period (master mode)
0x40005810 C   FIELD 16w04 SDADEL: Data hold time
0x40005810 C   FIELD 20w04 SCLDEL: Data setup time
0x40005810 C   FIELD 28w04 PRESC: Timing prescaler
0x40005814 B  REGISTER TIMEOUTR (rw): Status register 1
0x40005814 C   FIELD 00w12 TIMEOUTA (rw): Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0.
0x40005814 C   FIELD 12w01 TIDLE (rw): Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
0x40005814 C   FIELD 15w01 TIMOUTEN (rw): Clock timeout enable
0x40005814 C   FIELD 16w12 TIMEOUTB (rw): Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0.
0x40005814 C   FIELD 31w01 TEXTEN (rw): Extended clock timeout enable
0x40005818 B  REGISTER ISR: Interrupt and Status register
0x40005818 C   FIELD 00w01 TXE (rw): Transmit data register empty (transmitters)
0x40005818 C   FIELD 01w01 TXIS (rw): Transmit interrupt status (transmitters)
0x40005818 C   FIELD 02w01 RXNE (ro): Receive data register not empty (receivers)
0x40005818 C   FIELD 03w01 ADDR (ro): Address matched (slave mode)
0x40005818 C   FIELD 04w01 NACKF (ro): Not acknowledge received flag
0x40005818 C   FIELD 05w01 STOPF (ro): Stop detection flag
0x40005818 C   FIELD 06w01 TC (ro): Transfer Complete (master mode)
0x40005818 C   FIELD 07w01 TCR (ro): Transfer Complete Reload
0x40005818 C   FIELD 08w01 BERR (ro): Bus error
0x40005818 C   FIELD 09w01 ARLO (ro): Arbitration lost
0x40005818 C   FIELD 10w01 OVR (ro): Overrun/Underrun (slave mode)
0x40005818 C   FIELD 11w01 PECERR (ro): PEC Error in reception
0x40005818 C   FIELD 12w01 TIMEOUT (ro): Timeout or t_low detection flag
0x40005818 C   FIELD 13w01 ALERT (ro): SMBus alert
0x40005818 C   FIELD 15w01 BUSY (ro): Bus busy
0x40005818 C   FIELD 16w01 DIR (ro): Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1).
0x40005818 C   FIELD 17w07 ADDCODE (ro): Address match code (Slave mode)
0x4000581C B  REGISTER ICR (wo): Interrupt clear register
0x4000581C C   FIELD 03w01 ADDRCF: Address Matched flag clear
0x4000581C C   FIELD 04w01 NACKCF: Not Acknowledge flag clear
0x4000581C C   FIELD 05w01 STOPCF: Stop detection flag clear
0x4000581C C   FIELD 08w01 BERRCF: Bus error flag clear
0x4000581C C   FIELD 09w01 ARLOCF: Arbitration lost flag clear
0x4000581C C   FIELD 10w01 OVRCF: Overrun/Underrun flag clear
0x4000581C C   FIELD 11w01 PECCF: PEC Error flag clear
0x4000581C C   FIELD 12w01 TIMOUTCF: Timeout detection flag clear
0x4000581C C   FIELD 13w01 ALERTCF: Alert flag clear
0x40005820 B  REGISTER PECR (ro): PEC register
0x40005820 C   FIELD 00w08 PEC: Packet error checking register
0x40005824 B  REGISTER RXDR (ro): Receive data register
0x40005824 C   FIELD 00w08 RXDATA: 8-bit receive data
0x40005828 B  REGISTER TXDR (rw): Transmit data register
0x40005828 C   FIELD 00w08 TXDATA: 8-bit transmit data
0x40007000 A PERIPHERAL PWR
0x40007000 B  REGISTER CR1 (rw): Power control register 1
0x40007000 C   FIELD 00w03 LPMS: Low-power mode selection
0x40007000 C   FIELD 03w01 FPD_STOP: Flash memory powered down during Stop mode
0x40007000 C   FIELD 04w01 FPD_LPRUN: Flash memory powered down during Low-power run mode
0x40007000 C   FIELD 05w01 FPD_LPSLP: Flash memory powered down during Low-power sleep mode
0x40007000 C   FIELD 08w01 DBP: Disable backup domain write protection
0x40007000 C   FIELD 09w02 VOS: Voltage scaling range selection
0x40007000 C   FIELD 14w01 LPR: Low-power run
0x40007004 B  REGISTER CR2 (rw): Power control register 2
0x40007004 C   FIELD 00w01 PVDE: Power voltage detector enable
0x40007004 C   FIELD 01w03 PVDFT: Power voltage detector falling threshold selection
0x40007004 C   FIELD 04w03 PVDRT: Power voltage detector rising threshold selection
0x40007004 C   FIELD 07w01 PVMENDAC: PVMENDAC
0x40007004 C   FIELD 08w01 PVMENUSB: PVMENUSB
0x40007004 C   FIELD 09w01 IOSV: IOSV
0x40007004 C   FIELD 10w01 USV: USV
0x40007008 B  REGISTER CR3 (rw): Power control register 3
0x40007008 C   FIELD 00w01 EWUP1: Enable Wakeup pin WKUP1
0x40007008 C   FIELD 01w01 EWUP2: Enable Wakeup pin WKUP2
0x40007008 C   FIELD 02w01 EWUP3: Enable Wakeup pin WKUP3
0x40007008 C   FIELD 03w01 EWUP4: Enable Wakeup pin WKUP4
0x40007008 C   FIELD 04w01 EWUP5: Enable WKUP5 wakeup pin
0x40007008 C   FIELD 05w01 EWUP6: Enable WKUP6 wakeup pin
0x40007008 C   FIELD 08w01 RRS: SRAM retention in Standby mode
0x40007008 C   FIELD 09w01 ENB_ULP: Ultra-low-power enable
0x40007008 C   FIELD 10w01 APC: Apply pull-up and pull-down configuration
0x40007008 C   FIELD 15w01 EIWUL: Enable internal wakeup line
0x4000700C B  REGISTER CR4 (rw): Power control register 4
0x4000700C C   FIELD 00w01 WP1: Wakeup pin WKUP1 polarity
0x4000700C C   FIELD 01w01 WP2: Wakeup pin WKUP2 polarity
0x4000700C C   FIELD 02w01 WP3: Wakeup pin WKUP3 polarity
0x4000700C C   FIELD 03w01 WP4: Wakeup pin WKUP4 polarity
0x4000700C C   FIELD 04w01 WP5: Wakeup pin WKUP5 polarity
0x4000700C C   FIELD 05w01 WP6: WKUP6 wakeup pin polarity
0x4000700C C   FIELD 08w01 VBE: VBAT battery charging enable
0x4000700C C   FIELD 09w01 VBRS: VBAT battery charging resistor selection
0x40007010 B  REGISTER SR1 (ro): Power status register 1
0x40007010 C   FIELD 00w01 WUF1: Wakeup flag 1
0x40007010 C   FIELD 01w01 WUF2: Wakeup flag 2
0x40007010 C   FIELD 02w01 WUF3: Wakeup flag 3
0x40007010 C   FIELD 03w01 WUF4: Wakeup flag 4
0x40007010 C   FIELD 04w01 WUF5: Wakeup flag 5
0x40007010 C   FIELD 05w01 WUF6: Wakeup flag 6
0x40007010 C   FIELD 08w01 SBF: Standby flag
0x40007010 C   FIELD 15w01 WUFI: Wakeup flag internal
0x40007014 B  REGISTER SR2 (ro): Power status register 2
0x40007014 C   FIELD 07w01 FLASH_RDY: Flash ready flag
0x40007014 C   FIELD 08w01 REGLPS: Low-power regulator started
0x40007014 C   FIELD 09w01 REGLPF: Low-power regulator flag
0x40007014 C   FIELD 10w01 VOSF: Voltage scaling flag
0x40007014 C   FIELD 11w01 PVDO: Power voltage detector output
0x40007014 C   FIELD 12w01 PVMOUSB: USB supply voltage monitoring output flag
0x40007014 C   FIELD 15w01 PVMODAC: VDDA monitoring output flag
0x40007018 B  REGISTER SCR (wo): Power status clear register
0x40007018 C   FIELD 00w01 CWUF1: Clear wakeup flag 1
0x40007018 C   FIELD 01w01 CWUF2: Clear wakeup flag 2
0x40007018 C   FIELD 02w01 CWUF3: Clear wakeup flag 3
0x40007018 C   FIELD 03w01 CWUF4: Clear wakeup flag 4
0x40007018 C   FIELD 04w01 CWUF5: Clear wakeup flag 5
0x40007018 C   FIELD 05w01 CWUF6: Clear wakeup flag 6
0x40007018 C   FIELD 08w01 CSBF: Clear standby flag
0x40007020 B  REGISTER PUCRA (rw): Power Port A pull-up control register
0x40007020 C   FIELD 00w01 PU0: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 01w01 PU1: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 02w01 PU2: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 03w01 PU3: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 04w01 PU4: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 05w01 PU5: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 06w01 PU6: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 07w01 PU7: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 08w01 PU8: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 09w01 PU9: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 10w01 PU10: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 11w01 PU11: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 12w01 PU12: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 13w01 PU13: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 14w01 PU14: Port A pull-up bit y (y=0..15)
0x40007020 C   FIELD 15w01 PU15: Port A pull-up bit y (y=0..15)
0x40007024 B  REGISTER PDCRA (rw): Power Port A pull-down control register
0x40007024 C   FIELD 00w01 PD0: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 01w01 PD1: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 02w01 PD2: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 03w01 PD3: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 04w01 PD4: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 05w01 PD5: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 06w01 PD6: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 07w01 PD7: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 08w01 PD8: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 09w01 PD9: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 10w01 PD10: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 11w01 PD11: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 12w01 PD12: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 13w01 PD13: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 14w01 PD14: Port A pull-down bit y (y=0..15)
0x40007024 C   FIELD 15w01 PD15: Port A pull-down bit y (y=0..15)
0x40007028 B  REGISTER PUCRB (rw): Power Port B pull-up control register
0x40007028 C   FIELD 00w01 PU0: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 01w01 PU1: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 02w01 PU2: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 03w01 PU3: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 04w01 PU4: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 05w01 PU5: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 06w01 PU6: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 07w01 PU7: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 08w01 PU8: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 09w01 PU9: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 10w01 PU10: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 11w01 PU11: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 12w01 PU12: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 13w01 PU13: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 14w01 PU14: Port B pull-up bit y (y=0..15)
0x40007028 C   FIELD 15w01 PU15: Port B pull-up bit y (y=0..15)
0x4000702C B  REGISTER PDCRB (rw): Power Port B pull-down control register
0x4000702C C   FIELD 00w01 PD0: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 01w01 PD1: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 02w01 PD2: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 03w01 PD3: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 04w01 PD4: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 05w01 PD5: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 06w01 PD6: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 07w01 PD7: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 08w01 PD8: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 09w01 PD9: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 10w01 PD10: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 11w01 PD11: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 12w01 PD12: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 13w01 PD13: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 14w01 PD14: Port B pull-down bit y (y=0..15)
0x4000702C C   FIELD 15w01 PD15: Port B pull-down bit y (y=0..15)
0x40007030 B  REGISTER PUCRC (rw): Power Port C pull-up control register
0x40007030 C   FIELD 00w01 PU0: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 01w01 PU1: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 02w01 PU2: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 03w01 PU3: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 04w01 PU4: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 05w01 PU5: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 06w01 PU6: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 07w01 PU7: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 08w01 PU8: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 09w01 PU9: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 10w01 PU10: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 11w01 PU11: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 12w01 PU12: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 13w01 PU13: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 14w01 PU14: Port C pull-up bit y (y=0..15)
0x40007030 C   FIELD 15w01 PU15: Port C pull-up bit y (y=0..15)
0x40007034 B  REGISTER PDCRC (rw): Power Port C pull-down control register
0x40007034 C   FIELD 00w01 PD0: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 01w01 PD1: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 02w01 PD2: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 03w01 PD3: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 04w01 PD4: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 05w01 PD5: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 06w01 PD6: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 07w01 PD7: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 08w01 PD8: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 09w01 PD9: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 10w01 PD10: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 11w01 PD11: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 12w01 PD12: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 13w01 PD13: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 14w01 PD14: Port C pull-down bit y (y=0..15)
0x40007034 C   FIELD 15w01 PD15: Port C pull-down bit y (y=0..15)
0x40007038 B  REGISTER PUCRD (rw): Power Port D pull-up control register
0x40007038 C   FIELD 00w01 PU0: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 01w01 PU1: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 02w01 PU2: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 03w01 PU3: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 04w01 PU4: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 05w01 PU5: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 06w01 PU6: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 07w01 PU7: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 08w01 PU8: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 09w01 PU9: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 10w01 PU10: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 11w01 PU11: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 12w01 PU12: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 13w01 PU13: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 14w01 PU14: Port D pull-up bit y (y=0..15)
0x40007038 C   FIELD 15w01 PU15: Port D pull-up bit y (y=0..15)
0x4000703C B  REGISTER PDCRD (rw): Power Port D pull-down control register
0x4000703C C   FIELD 00w01 PD0: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 01w01 PD1: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 02w01 PD2: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 03w01 PD3: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 04w01 PD4: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 05w01 PD5: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 06w01 PD6: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 07w01 PD7: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 08w01 PD8: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 09w01 PD9: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 10w01 PD10: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 11w01 PD11: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 12w01 PD12: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 13w01 PD13: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 14w01 PD14: Port D pull-down bit y (y=0..15)
0x4000703C C   FIELD 15w01 PD15: Port D pull-down bit y (y=0..15)
0x40007040 B  REGISTER PUCRE (rw): Power Port E pull-UP control register
0x40007040 C   FIELD 00w01 PU0: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 01w01 PU1: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 02w01 PU2: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 03w01 PU3: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 04w01 PU4: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 05w01 PU5: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 06w01 PU6: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 07w01 PU7: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 08w01 PU8: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 09w01 PU9: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 10w01 PU10: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 11w01 PU11: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 12w01 PU12: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 13w01 PU13: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 14w01 PU14: Port E pull-up bit y (y=0..15)
0x40007040 C   FIELD 15w01 PU15: Port E pull-up bit y (y=0..15)
0x40007044 B  REGISTER PDCRE (rw): Power Port E pull-down control register
0x40007044 C   FIELD 00w01 PD0: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 01w01 PD1: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 02w01 PD2: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 03w01 PD3: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 04w01 PD4: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 05w01 PD5: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 06w01 PD6: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 07w01 PD7: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 08w01 PD8: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 09w01 PD9: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 10w01 PD10: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 11w01 PD11: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 12w01 PD12: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 13w01 PD13: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 14w01 PD14: Port E pull-down bit y (y=0..15)
0x40007044 C   FIELD 15w01 PD15: Port E pull-down bit y (y=0..15)
0x40007048 B  REGISTER PUCRF (rw): Power Port F pull-up control register
0x40007048 C   FIELD 00w01 PU0: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 01w01 PU1: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 02w01 PU2: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 03w01 PU3: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 04w01 PU4: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 05w01 PU5: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 06w01 PU6: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 07w01 PU7: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 08w01 PU8: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 09w01 PU9: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 10w01 PU10: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 11w01 PU11: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 12w01 PU12: Port F pull-up bit y (y=0..15)
0x40007048 C   FIELD 13w01 PU13: Port F pull-up bit y (y=0..15)
0x4000704C B  REGISTER PDCRF (rw): Power Port F pull-down control register
0x4000704C C   FIELD 00w01 PD0: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 01w01 PD1: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 02w01 PD2: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 03w01 PD3: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 04w01 PD4: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 05w01 PD5: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 06w01 PD6: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 07w01 PD7: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 08w01 PD8: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 09w01 PD9: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 10w01 PD10: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 11w01 PD11: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 12w01 PD12: Port F pull-down bit y (y=0..15)
0x4000704C C   FIELD 13w01 PD13: Port F pull-down bit y (y=0..15)
0x40007400 A PERIPHERAL DAC
0x40007400 B  REGISTER CR (rw): DAC control register
0x40007400 C   FIELD 00w01 EN1 (rw): DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.
0x40007400 C   FIELD 01w01 TEN1 (rw): DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle.
0x40007400 C   FIELD 02w04 TSEL1 (rw): DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
0x40007400 C   FIELD 06w02 WAVE1 (rw): DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 1x: Triangle wave generation enabled Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
0x40007400 C   FIELD 08w04 MAMP1 (rw): DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. bigger or equal to 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
0x40007400 C   FIELD 12w01 DMAEN1 (rw): DAC channel1 DMA enable This bit is set and cleared by software.
0x40007400 C   FIELD 13w01 DMAUDRIE1 (rw): DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.
0x40007400 C   FIELD 14w01 CEN1 (rw): DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.
0x40007400 C   FIELD 16w01 EN2 (rw): DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. Note: These bits are available only on dual-channel DACs. Refer to implementation.
0x40007400 C   FIELD 17w01 TEN2 (rw): DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the DAC_DOR2 register takes only one dac_pclk clock cycle. These bits are available only on dual-channel DACs. Refer to implementation.
0x40007400 C   FIELD 18w04 TSEL2 (rw): DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). These bits are available only on dual-channel DACs. Refer to implementation.
0x40007400 C   FIELD 22w02 WAVE2 (rw): DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available only on dual-channel DACs. Refer to implementation.
0x40007400 C   FIELD 24w04 MAMP2 (rw): DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. bigger or equal to 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Note: These bits are available only on dual-channel DACs. Refer to implementation.
0x40007400 C   FIELD 28w01 DMAEN2 (rw): DAC channel2 DMA enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation.
0x40007400 C   FIELD 29w01 DMAUDRIE2 (rw): DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation.
0x40007400 C   FIELD 30w01 CEN2 (rw): DAC channel2 calibration enable This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. Note: This bit is available only on dual-channel DACs. Refer to implementation.
0x40007404 B  REGISTER SWTRGR (wo): DAC software trigger register
0x40007404 C   FIELD 00w01 SWTRIG1 (wo): DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.
0x40007404 C   FIELD 01w01 SWTRIG2 (wo): DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. This bit is available only on dual-channel DACs. Refer to implementation.
0x40007408 B  REGISTER DHR12R1 (rw): DAC channel1 12-bit right-aligned data holding register
0x40007408 C   FIELD 00w12 DACC1DHR (rw): DAC channel1 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel1.
0x4000740C B  REGISTER DHR12L1 (rw): DAC channel1 12-bit left aligned data holding register
0x4000740C C   FIELD 04w12 DACC1DHR (rw): DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1.
0x40007410 B  REGISTER DHR8R1 (rw): DAC channel1 8-bit right aligned data holding register
0x40007410 C   FIELD 00w08 DACC1DHR (rw): DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1.
0x40007414 B  REGISTER DHR12R2 (rw): DAC channel2 12-bit right aligned data holding register
0x40007414 C   FIELD 00w12 DACC2DHR (rw): DAC channel2 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel2.
0x40007418 B  REGISTER DHR12L2 (rw): DAC channel2 12-bit left aligned data holding register
0x40007418 C   FIELD 04w12 DACC2DHR (rw): DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.
0x4000741C B  REGISTER DHR8R2 (rw): DAC channel2 8-bit right-aligned data holding register
0x4000741C C   FIELD 00w08 DACC2DHR (rw): DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
0x40007420 B  REGISTER DHR12RD (rw): Dual DAC 12-bit right-aligned data holding register
0x40007420 C   FIELD 00w12 DACC1DHR (rw): DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
0x40007420 C   FIELD 16w12 DACC2DHR (rw): DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
0x40007424 B  REGISTER DHR12LD (rw): DUAL DAC 12-bit left aligned data holding register
0x40007424 C   FIELD 04w12 DACC1DHR (rw): DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
0x40007424 C   FIELD 20w12 DACC2DHR (rw): DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
0x40007428 B  REGISTER DHR8RD (rw): DUAL DAC 8-bit right aligned data holding register
0x40007428 C   FIELD 00w08 DACC1DHR (rw): DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.
0x40007428 C   FIELD 08w08 DACC2DHR (rw): DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
0x4000742C B  REGISTER DOR1 (ro): DAC channel1 data output register
0x4000742C C   FIELD 00w12 DACC1DOR (ro): DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.
0x40007430 B  REGISTER DOR2 (ro): DAC channel2 data output register
0x40007430 C   FIELD 00w12 DACC2DOR (ro): DAC channel2 data output These bits are read-only, they contain data output for DAC channel2.
0x40007434 B  REGISTER SR: DAC status register
0x40007434 C   FIELD 13w01 DMAUDR1 (rw): DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
0x40007434 C   FIELD 14w01 CAL_FLAG1 (ro): DAC channel1 calibration offset status This bit is set and cleared by hardware
0x40007434 C   FIELD 15w01 BWST1 (ro): DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).
0x40007434 C   FIELD 29w01 DMAUDR2 (rw): DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). Note: This bit is available only on dual-channel DACs. Refer to implementation.
0x40007434 C   FIELD 30w01 CAL_FLAG2 (ro): DAC channel2 calibration offset status This bit is set and cleared by hardware Note: This bit is available only on dual-channel DACs. Refer to implementation.
0x40007434 C   FIELD 31w01 BWST2 (ro): DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). Note: This bit is available only on dual-channel DACs. Refer to implementation.
0x40007438 B  REGISTER CCR (rw): DAC calibration control register
0x40007438 C   FIELD 00w05 OTRIM1 (rw): DAC channel1 offset trimming value
0x40007438 C   FIELD 16w05 OTRIM2 (rw): DAC channel2 offset trimming value These bits are available only on dual-channel DACs. Refer to implementation.
0x4000743C B  REGISTER MCR (rw): DAC mode control register
0x4000743C C   FIELD 00w03 MODE1 (rw): DAC channel1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel1 mode: DAC channel1 in Normal mode DAC channel1 in sample & hold mode Note: This register can be modified only when EN1=0.
0x4000743C C   FIELD 16w03 MODE2 (rw): DAC channel2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel2 mode: DAC channel2 in Normal mode DAC channel2 in Sample and hold mode Note: This register can be modified only when EN2=0. Refer to for the availability of DAC channel2.
0x40007440 B  REGISTER SHSR1 (rw): DAC Sample and Hold sample time register 1
0x40007440 C   FIELD 00w10 TSAMPLE1 (rw): DAC channel1 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST1=1, the write operation is ignored.
0x40007444 B  REGISTER SHSR2 (rw): DAC Sample and Hold sample time register 2
0x40007444 C   FIELD 00w10 TSAMPLE2 (rw): DAC channel2 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWST2 of DAC_SR register is low, if BWST2=1, the write operation is ignored.
0x40007448 B  REGISTER SHHR (rw): DAC Sample and Hold hold time register
0x40007448 C   FIELD 00w10 THOLD1 (rw): DAC channel1 hold time (only valid in Sample and hold mode) Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN1=0.
0x40007448 C   FIELD 16w10 THOLD2 (rw): DAC channel2 hold time (only valid in Sample and hold mode). Hold time= (THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation.
0x4000744C B  REGISTER SHRR (rw): DAC Sample and Hold refresh time register
0x4000744C C   FIELD 00w08 TREFRESH1 (rw): DAC channel1 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN1=0.
0x4000744C C   FIELD 16w08 TREFRESH2 (rw): DAC channel2 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation.
0x40007800 A PERIPHERAL HDMI_CEC
0x40007800 B  REGISTER CR (rw): CEC control register
0x40007800 C   FIELD 00w01 CECEN (rw): CEC enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission.
0x40007800 C   FIELD 01w01 TXSOM (rw): Tx start of message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission starts after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1. TXSOM must be set when transmission data is available into TXDR. HEADER first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR that is used only for reception.
0x40007800 C   FIELD 02w01 TXEOM (rw): Tx end of message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1. TXEOM must be set before writing transmission data to TXDR. If TXEOM is set when TXSOM=0, transmitted message consists of 1 byte (HEADER) only (PING message).
0x40007804 B  REGISTER CFGR (rw): This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.
0x40007804 C   FIELD 00w03 SFT (rw): Signal free time SFT bits are set by software. In the SFT=0x0 configuration, the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. 0x0 2.5 data-bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE=1) 4 data-bit periods if CEC is the new bus initiator 6 data-bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1)
0x40007804 C   FIELD 03w01 RXTOL (rw): Rx-tolerance
0x40007804 C   FIELD 04w01 BRESTP (rw): Rx-stop on bit rising error The BRESTP bit is set and cleared by software.
0x40007804 C   FIELD 05w01 BREGEN (rw): Generate error-bit on bit rising error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0.
0x40007804 C   FIELD 06w01 LBPEGEN (rw): Generate error-bit on long bit period error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0.
0x40007804 C   FIELD 07w01 BRDNOGEN (rw): Avoid error-bit generation in broadcast The BRDNOGEN bit is set and cleared by software. error-bit on the CEC line. LBPE detection with LBPEGEN=0 on a broadcast message generates an error-bit on the CEC line.
0x40007804 C   FIELD 08w01 SFTOP (rw): SFT option bit The SFTOPT bit is set and cleared by software.
0x40007804 C   FIELD 16w15 OAR (rw): Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received.
0x40007804 C   FIELD 31w01 LSTN (rw): Listen mode LSTN bit is set and cleared by software.
0x40007808 B  REGISTER TXDR (wo): CEC Tx data register
0x40007808 C   FIELD 00w08 TXD: Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1
0x4000780C B  REGISTER RXDR (ro): CEC Rx Data Register
0x4000780C C   FIELD 00w08 RXD: Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line.
0x40007810 B  REGISTER ISR (rw): CEC Interrupt and Status Register
0x40007810 C   FIELD 00w01 RXBR: Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1.
0x40007810 C   FIELD 01w01 RXEND: End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1.
0x40007810 C   FIELD 02w01 RXOVR: Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1.
0x40007810 C   FIELD 03w01 BRE: Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1.
0x40007810 C   FIELD 04w01 SBPE: Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1.
0x40007810 C   FIELD 05w01 LBPE: Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1.
0x40007810 C   FIELD 06w01 RXACKE: Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1.
0x40007810 C   FIELD 07w01 ARBLST: Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1.
0x40007810 C   FIELD 08w01 TXBR: Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1.
0x40007810 C   FIELD 09w01 TXEND: End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1.
0x40007810 C   FIELD 10w01 TXUDR: Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1
0x40007810 C   FIELD 11w01 TXERR: Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1.
0x40007810 C   FIELD 12w01 TXACKE: Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1.
0x40007814 B  REGISTER IER (rw): CEC interrupt enable register
0x40007814 C   FIELD 00w01 RXBRIE (rw): Rx-byte received interrupt enable The RXBRIE bit is set and cleared by software.
0x40007814 C   FIELD 01w01 RXENDIE (rw): End of reception interrupt enable The RXENDIE bit is set and cleared by software.
0x40007814 C   FIELD 02w01 RXOVRIE (rw): Rx-buffer overrun interrupt enable The RXOVRIE bit is set and cleared by software.
0x40007814 C   FIELD 03w01 BREIE (rw): Bit rising error interrupt enable The BREIE bit is set and cleared by software.
0x40007814 C   FIELD 04w01 SBPEIE (rw): Short bit period error interrupt enable The SBPEIE bit is set and cleared by software.
0x40007814 C   FIELD 05w01 LBPEIE (rw): Long bit period error interrupt enable The LBPEIE bit is set and cleared by software.
0x40007814 C   FIELD 06w01 RXACKIE (rw): Rx-missing acknowledge error interrupt enable The RXACKIE bit is set and cleared by software.
0x40007814 C   FIELD 07w01 ARBLSTIE (rw): Arbitration lost interrupt enable The ARBLSTIE bit is set and cleared by software.
0x40007814 C   FIELD 08w01 TXBRIE (rw): Tx-byte request interrupt enable The TXBRIE bit is set and cleared by software.
0x40007814 C   FIELD 09w01 TXENDIE (rw): Tx-end of message interrupt enable The TXENDIE bit is set and cleared by software.
0x40007814 C   FIELD 10w01 TXUDRIE (rw): Tx-underrun interrupt enable The TXUDRIE bit is set and cleared by software.
0x40007814 C   FIELD 11w01 TXERRIE (rw): Tx-error interrupt enable The TXERRIE bit is set and cleared by software.
0x40007814 C   FIELD 12w01 TXACKIE (rw): Tx-missing acknowledge error interrupt enable The TXACKEIE bit is set and cleared by software.
0x40007C00 A PERIPHERAL LPTIM1
0x40007C00 B  REGISTER ISR (ro): Interrupt and Status Register
0x40007C00 C   FIELD 00w01 CMPM (ro): Compare match The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register's value.
0x40007C00 C   FIELD 01w01 ARRM (ro): Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register's value reached the LPTIM_ARR register's value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
0x40007C00 C   FIELD 02w01 EXTTRIG (ro): External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
0x40007C00 C   FIELD 03w01 CMPOK (ro): Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed.
0x40007C00 C   FIELD 04w01 ARROK (ro): Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
0x40007C00 C   FIELD 05w01 UP (ro): Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40007C00 C   FIELD 06w01 DOWN (ro): Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40007C04 B  REGISTER ICR (wo): Interrupt Clear Register
0x40007C04 C   FIELD 00w01 CMPMCF (wo): Compare match clear flag Writing 1 to this bit clears the CMP flag in the LPTIM_ISR register
0x40007C04 C   FIELD 01w01 ARRMCF (wo): Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register
0x40007C04 C   FIELD 02w01 EXTTRIGCF (wo): External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register
0x40007C04 C   FIELD 03w01 CMPOKCF (wo): Compare register update OK clear flag Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register
0x40007C04 C   FIELD 04w01 ARROKCF (wo): Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register
0x40007C04 C   FIELD 05w01 UPCF (wo): Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40007C04 C   FIELD 06w01 DOWNCF (wo): Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40007C08 B  REGISTER IER (rw): Interrupt Enable Register
0x40007C08 C   FIELD 00w01 CMPMIE (rw): Compare match Interrupt Enable
0x40007C08 C   FIELD 01w01 ARRMIE (rw): Autoreload match Interrupt Enable
0x40007C08 C   FIELD 02w01 EXTTRIGIE (rw): External trigger valid edge Interrupt Enable
0x40007C08 C   FIELD 03w01 CMPOKIE (rw): Compare register update OK Interrupt Enable
0x40007C08 C   FIELD 04w01 ARROKIE (rw): Autoreload register update OK Interrupt Enable
0x40007C08 C   FIELD 05w01 UPIE (rw): Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40007C08 C   FIELD 06w01 DOWNIE (rw): Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40007C0C B  REGISTER CFGR (rw): Configuration Register
0x40007C0C C   FIELD 00w01 CKSEL (rw): Clock selector The CKSEL bit selects which clock source the LPTIM will use:
0x40007C0C C   FIELD 01w02 CKPOL (rw): Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.
0x40007C0C C   FIELD 03w02 CKFLT (rw): Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature
0x40007C0C C   FIELD 06w02 TRGFLT (rw): Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature
0x40007C0C C   FIELD 09w03 PRESC (rw): Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:
0x40007C0C C   FIELD 13w03 TRIGSEL (rw): Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: See for details.
0x40007C0C C   FIELD 17w02 TRIGEN (rw): Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:
0x40007C0C C   FIELD 19w01 TIMOUT (rw): Timeout enable The TIMOUT bit controls the Timeout feature
0x40007C0C C   FIELD 20w01 WAVE (rw): Waveform shape The WAVE bit controls the output shape
0x40007C0C C   FIELD 21w01 WAVPOL (rw): Waveform shape polarity The WAVEPOL bit controls the output polarity
0x40007C0C C   FIELD 22w01 PRELOAD (rw): Registers update mode The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality
0x40007C0C C   FIELD 23w01 COUNTMODE (rw): counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:
0x40007C0C C   FIELD 24w01 ENC (rw): Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40007C10 B  REGISTER CR (rw): Control Register
0x40007C10 C   FIELD 00w01 ENABLE (rw): LPTIM enable The ENABLE bit is set and cleared by software.
0x40007C10 C   FIELD 01w01 SNGSTRT (rw): LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.
0x40007C10 C   FIELD 02w01 CNTSTRT (rw): Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.
0x40007C10 C   FIELD 03w01 COUNTRST (rw): Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.
0x40007C10 C   FIELD 04w01 RSTARE (rw): Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content.
0x40007C14 B  REGISTER CMP (rw): Compare Register
0x40007C14 C   FIELD 00w16 CMP: Compare value
0x40007C18 B  REGISTER ARR (rw): Autoreload Register
0x40007C18 C   FIELD 00w16 ARR: Auto reload value
0x40007C1C B  REGISTER CNT (ro): Counter Register
0x40007C1C C   FIELD 00w16 CNT: Counter value
0x40007C24 B  REGISTER CFGR2 (rw): LPTIM configuration register 2
0x40007C24 C   FIELD 00w02 IN1SEL (rw): LPTIM input 1 selection The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. For connection details refer to .
0x40007C24 C   FIELD 04w02 IN2SEL (rw): LPTIM input 2 selection The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. For connection details refer to . Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to .
0x40008000 A PERIPHERAL LPUART1
0x40008000 B  REGISTER CR1: LPUART control register 1 [alternate]
0x40008000 C   FIELD 00w01 UE (rw): USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
0x40008000 C   FIELD 01w01 UESM (rw): USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
0x40008000 C   FIELD 02w01 RE (rw): Receiver enable This bit enables the receiver. It is set and cleared by software.
0x40008000 C   FIELD 03w01 TE (rw): Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
0x40008000 C   FIELD 04w01 IDLEIE (rw): IDLE interrupt enable This bit is set and cleared by software.
0x40008000 C   FIELD 05w01 RXNEIE (rw): RXFIFO not empty interrupt enable This bit is set and cleared by software.
0x40008000 C   FIELD 06w01 TCIE (rw): Transmission complete interrupt enable This bit is set and cleared by software.
0x40008000 C   FIELD 07w01 TXEIE (rw): TXFIFO not full interrupt enable This bit is set and cleared by software.
0x40008000 C   FIELD 08w01 PEIE (rw): PE interrupt enable This bit is set and cleared by software.
0x40008000 C   FIELD 09w01 PS (rw): Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE=0).
0x40008000 C   FIELD 10w01 PCE (rw): Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE=0).
0x40008000 C   FIELD 11w01 WAKE (rw): Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE=0).
0x40008000 C   FIELD 12w01 M0 (rw): Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE=0).
0x40008000 C   FIELD 13w01 MME (rw): Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0x40008000 C   FIELD 14w01 CMIE (rw): Character match interrupt enable This bit is set and cleared by software.
0x40008000 C   FIELD 15w01 OVER8 (rw): Oversampling mode This bit can only be written when the USART is disabled (UE=0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
0x40008000 C   FIELD 16w05 DEDT (rw): Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40008000 C   FIELD 21w05 DEAT (rw): Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40008000 C   FIELD 26w01 RTOIE (rw): Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
0x40008000 C   FIELD 27w01 EOBIE (rw): End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40008000 C   FIELD 28w01 M1 (rw): Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
0x40008000 C   FIELD 29w01 FIFOEN (rw): FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
0x40008000 C   FIELD 30w01 TXFEIE (rw): TXFIFO empty interrupt enable This bit is set and cleared by software.
0x40008000 C   FIELD 31w01 RXFFIE (rw): RXFIFO Full interrupt enable This bit is set and cleared by software.
0x40008004 B  REGISTER CR2: LPUART control register 2
0x40008004 C   FIELD 04w01 ADDM7 (rw): 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the LPUART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
0x40008004 C   FIELD 12w02 STOP (rw): STOP bits These bits are used for programming the stop bits. This bitfield can only be written when the LPUART is disabled (UE=0).
0x40008004 C   FIELD 15w01 SWAP (rw): Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0).
0x40008004 C   FIELD 16w01 RXINV (rw): RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the LPUART is disabled (UE=0).
0x40008004 C   FIELD 17w01 TXINV (rw): TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the LPUART is disabled (UE=0).
0x40008004 C   FIELD 18w01 DATAINV (rw): Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0).
0x40008004 C   FIELD 19w01 MSBFIRST (rw): Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0).
0x40008004 C   FIELD 24w08 ADD (rw): Address of the LPUART node ADD[7:4]: These bits give the address of the LPUART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or Stop mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the LPUART is disabled (UE=0) ADD[3:0]: These bits give the address of the LPUART node or a character code to be recognized. They are used for wakeup with address mark detection in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the LPUART is disabled (UE=0)
0x40008008 B  REGISTER CR3: LPUART control register 3
0x40008008 C   FIELD 00w01 EIE (rw): Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NE=1 in the LPUART_ISR register).
0x40008008 C   FIELD 03w01 HDSEL (rw): Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the LPUART is disabled (UE=0).
0x40008008 C   FIELD 06w01 DMAR (rw): DMA enable receiver This bit is set/reset by software
0x40008008 C   FIELD 07w01 DMAT (rw): DMA enable transmitter This bit is set/reset by software
0x40008008 C   FIELD 08w01 RTSE (rw): RTS enable This bit can only be written when the LPUART is disabled (UE=0).
0x40008008 C   FIELD 09w01 CTSE (rw): CTS enable This bit can only be written when the LPUART is disabled (UE=0)
0x40008008 C   FIELD 10w01 CTSIE (rw): CTS interrupt enable
0x40008008 C   FIELD 12w01 OVRDIS (rw): Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data.
0x40008008 C   FIELD 13w01 DDRE (rw): DMA Disable on Reception Error This bit can only be written when the LPUART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
0x40008008 C   FIELD 14w01 DEM (rw): Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the LPUART is disabled (UE=0).
0x40008008 C   FIELD 15w01 DEP (rw): Driver enable polarity selection This bit can only be written when the LPUART is disabled (UE=0).
0x40008008 C   FIELD 20w02 WUS (rw): Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the LPUART is disabled (UE=0). Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
0x40008008 C   FIELD 22w01 WUFIE (rw): Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
0x40008008 C   FIELD 23w01 TXFTIE (rw): TXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40008008 C   FIELD 25w03 RXFTCFG (rw): Receive FIFO threshold configuration Remaining combinations: Reserved.
0x40008008 C   FIELD 28w01 RXFTIE (rw): RXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40008008 C   FIELD 29w03 TXFTCFG (rw): TXFIFO threshold configuration Remaining combinations: Reserved.
0x4000800C B  REGISTER BRR: LPUART baud rate register
0x4000800C C   FIELD 00w20 BRR (rw): LPUART baud rate
0x40008018 B  REGISTER RQR: LPUART request register
0x40008018 C   FIELD 01w01 SBKRQ (wo): Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
0x40008018 C   FIELD 02w01 MMRQ (wo): Mute mode request Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag.
0x40008018 C   FIELD 03w01 RXFRQ (wo): Receive data flush request Writing 1 to this bit clears the RXNE flag. This enables discarding the received data without reading it, and avoid an overrun condition.
0x40008018 C   FIELD 04w01 TXFRQ (wo): Transmit data flush request This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
0x4000801C B  REGISTER ISR: LPUART interrupt and status register [alternate]
0x4000801C C   FIELD 00w01 PE (ro): Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4000801C C   FIELD 01w01 FE (ro): Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE=1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4000801C C   FIELD 02w01 NE (ro): Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page903). This error is associated with the character in the USART_RDR.
0x4000801C C   FIELD 03w01 ORE (ro): Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE=1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
0x4000801C C   FIELD 04w01 IDLE (ro): Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set.
0x4000801C C   FIELD 05w01 RXFNE (ro): RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE=1 in the USART_CR1 register.
0x4000801C C   FIELD 06w01 TC (ro): Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
0x4000801C C   FIELD 07w01 TXFNF (ro): TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.
0x4000801C C   FIELD 08w01 LBDF (ro): LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
0x4000801C C   FIELD 09w01 CTSIF (ro): CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000801C C   FIELD 10w01 CTS (ro): CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000801C C   FIELD 11w01 RTOF (ro): Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
0x4000801C C   FIELD 12w01 EOBF (ro): End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE=1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
0x4000801C C   FIELD 13w01 UDR (ro): SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
0x4000801C C   FIELD 14w01 ABRE (ro): Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000801C C   FIELD 15w01 ABRF (ro): Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000801C C   FIELD 16w01 BUSY (ro): Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
0x4000801C C   FIELD 17w01 CMF (ro): Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register.
0x4000801C C   FIELD 18w01 SBKF (ro): Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
0x4000801C C   FIELD 19w01 RWU (ro): Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000801C C   FIELD 20w01 WUF (ro): Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE=1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000801C C   FIELD 21w01 TEACK (ro): Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period.
0x4000801C C   FIELD 22w01 REACK (ro): Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4000801C C   FIELD 23w01 TXFE (ro): TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register.
0x4000801C C   FIELD 24w01 RXFF (ro): RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFOsize+1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register.
0x4000801C C   FIELD 25w01 TCBGT (ro): Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1'. Refer to on page877.
0x4000801C C   FIELD 26w01 RXFT (ro): RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101', RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
0x4000801C C   FIELD 27w01 TXFT (ro): TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register.
0x40008020 B  REGISTER ICR: LPUART interrupt flag clear register
0x40008020 C   FIELD 00w01 PECF (wo): Parity error clear flag Writing 1 to this bit clears the PE flag in the LPUART_ISR register.
0x40008020 C   FIELD 01w01 FECF (wo): Framing error clear flag Writing 1 to this bit clears the FE flag in the LPUART_ISR register.
0x40008020 C   FIELD 02w01 NECF (wo): Noise detected clear flag Writing 1 to this bit clears the NE flag in the LPUART_ISR register.
0x40008020 C   FIELD 03w01 ORECF (wo): Overrun error clear flag Writing 1 to this bit clears the ORE flag in the LPUART_ISR register.
0x40008020 C   FIELD 04w01 IDLECF (wo): Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register.
0x40008020 C   FIELD 06w01 TCCF (wo): Transmission complete clear flag Writing 1 to this bit clears the TC flag in the LPUART_ISR register.
0x40008020 C   FIELD 09w01 CTSCF (wo): CTS clear flag Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register.
0x40008020 C   FIELD 17w01 CMCF (wo): Character match clear flag Writing 1 to this bit clears the CMF flag in the LPUART_ISR register.
0x40008020 C   FIELD 20w01 WUCF (wo): Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the LPUART_ISR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x40008024 B  REGISTER RDR: LPUART receive data register
0x40008024 C   FIELD 00w09 RDR (ro): Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit.
0x40008028 B  REGISTER TDR: LPUART transmit data register
0x40008028 C   FIELD 00w09 TDR (rw): Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF=1.
0x4000802C B  REGISTER PRESC: LPUART prescaler register
0x4000802C C   FIELD 00w04 PRESCALER (rw): Clock prescaler The LPUART input clock can be divided by a prescaler: Remaining combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
0x40009400 A PERIPHERAL LPTIM2
0x40009400 B  REGISTER ISR (ro): Interrupt and Status Register
0x40009400 C   FIELD 00w01 CMPM (ro): Compare match The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register's value.
0x40009400 C   FIELD 01w01 ARRM (ro): Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register's value reached the LPTIM_ARR register's value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
0x40009400 C   FIELD 02w01 EXTTRIG (ro): External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
0x40009400 C   FIELD 03w01 CMPOK (ro): Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed.
0x40009400 C   FIELD 04w01 ARROK (ro): Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
0x40009400 C   FIELD 05w01 UP (ro): Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40009400 C   FIELD 06w01 DOWN (ro): Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40009404 B  REGISTER ICR (wo): Interrupt Clear Register
0x40009404 C   FIELD 00w01 CMPMCF (wo): Compare match clear flag Writing 1 to this bit clears the CMP flag in the LPTIM_ISR register
0x40009404 C   FIELD 01w01 ARRMCF (wo): Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register
0x40009404 C   FIELD 02w01 EXTTRIGCF (wo): External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register
0x40009404 C   FIELD 03w01 CMPOKCF (wo): Compare register update OK clear flag Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register
0x40009404 C   FIELD 04w01 ARROKCF (wo): Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register
0x40009404 C   FIELD 05w01 UPCF (wo): Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40009404 C   FIELD 06w01 DOWNCF (wo): Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40009408 B  REGISTER IER (rw): Interrupt Enable Register
0x40009408 C   FIELD 00w01 CMPMIE (rw): Compare match Interrupt Enable
0x40009408 C   FIELD 01w01 ARRMIE (rw): Autoreload match Interrupt Enable
0x40009408 C   FIELD 02w01 EXTTRIGIE (rw): External trigger valid edge Interrupt Enable
0x40009408 C   FIELD 03w01 CMPOKIE (rw): Compare register update OK Interrupt Enable
0x40009408 C   FIELD 04w01 ARROKIE (rw): Autoreload register update OK Interrupt Enable
0x40009408 C   FIELD 05w01 UPIE (rw): Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40009408 C   FIELD 06w01 DOWNIE (rw): Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x4000940C B  REGISTER CFGR (rw): Configuration Register
0x4000940C C   FIELD 00w01 CKSEL (rw): Clock selector The CKSEL bit selects which clock source the LPTIM will use:
0x4000940C C   FIELD 01w02 CKPOL (rw): Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.
0x4000940C C   FIELD 03w02 CKFLT (rw): Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature
0x4000940C C   FIELD 06w02 TRGFLT (rw): Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature
0x4000940C C   FIELD 09w03 PRESC (rw): Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:
0x4000940C C   FIELD 13w03 TRIGSEL (rw): Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: See for details.
0x4000940C C   FIELD 17w02 TRIGEN (rw): Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:
0x4000940C C   FIELD 19w01 TIMOUT (rw): Timeout enable The TIMOUT bit controls the Timeout feature
0x4000940C C   FIELD 20w01 WAVE (rw): Waveform shape The WAVE bit controls the output shape
0x4000940C C   FIELD 21w01 WAVPOL (rw): Waveform shape polarity The WAVEPOL bit controls the output polarity
0x4000940C C   FIELD 22w01 PRELOAD (rw): Registers update mode The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality
0x4000940C C   FIELD 23w01 COUNTMODE (rw): counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:
0x4000940C C   FIELD 24w01 ENC (rw): Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .
0x40009410 B  REGISTER CR (rw): Control Register
0x40009410 C   FIELD 00w01 ENABLE (rw): LPTIM enable The ENABLE bit is set and cleared by software.
0x40009410 C   FIELD 01w01 SNGSTRT (rw): LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.
0x40009410 C   FIELD 02w01 CNTSTRT (rw): Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.
0x40009410 C   FIELD 03w01 COUNTRST (rw): Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.
0x40009410 C   FIELD 04w01 RSTARE (rw): Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content.
0x40009414 B  REGISTER CMP (rw): Compare Register
0x40009414 C   FIELD 00w16 CMP: Compare value
0x40009418 B  REGISTER ARR (rw): Autoreload Register
0x40009418 C   FIELD 00w16 ARR: Auto reload value
0x4000941C B  REGISTER CNT (ro): Counter Register
0x4000941C C   FIELD 00w16 CNT: Counter value
0x40009424 B  REGISTER CFGR2 (rw): LPTIM configuration register 2
0x40009424 C   FIELD 00w02 IN1SEL (rw): LPTIM input 1 selection The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. For connection details refer to .
0x40009424 C   FIELD 04w02 IN2SEL (rw): LPTIM input 2 selection The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. For connection details refer to . Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to .
0x4000B000 A PERIPHERAL TAMP
0x4000B000 B  REGISTER CR1: TAMP control register 1
0x4000B000 C   FIELD 00w01 TAMP1E (rw): Tamper detection on TAMP_IN1 enable
0x4000B000 C   FIELD 01w01 TAMP2E (rw): Tamper detection on TAMP_IN2 enable
0x4000B000 C   FIELD 18w01 ITAMP3E (rw): Internal tamper 3 enable: LSE monitoring
0x4000B000 C   FIELD 19w01 ITAMP4E (rw): Internal tamper 4 enable: HSE monitoring
0x4000B000 C   FIELD 20w01 ITAMP5E (rw): Internal tamper 5 enable: RTC calendar overflow
0x4000B000 C   FIELD 21w01 ITAMP6E (rw): Internal tamper 6 enable: ST manufacturer readout
0x4000B004 B  REGISTER CR2: TAMP control register 2
0x4000B004 C   FIELD 00w01 TAMP1NOER (rw): Tamper 1 no erase
0x4000B004 C   FIELD 01w01 TAMP2NOER (rw): Tamper 2 no erase
0x4000B004 C   FIELD 16w01 TAMP1MSK (rw): Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set.
0x4000B004 C   FIELD 17w01 TAMP2MSK (rw): Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set.
0x4000B004 C   FIELD 24w01 TAMP1TRG (rw): Active level for tamper 1 input (active mode disabled) If TAMPFLT = 00 Tamper 1 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 1 input falling edge and low level triggers a tamper detection event.
0x4000B004 C   FIELD 25w01 TAMP2TRG (rw): Active level for tamper 2 input (active mode disabled) If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 2 input falling edge and low level triggers a tamper detection event.
0x4000B00C B  REGISTER FLTCR: TAMP filter control register
0x4000B00C C   FIELD 00w03 TAMPFREQ (rw): Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled.
0x4000B00C C   FIELD 03w02 TAMPFLT (rw): TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs.
0x4000B00C C   FIELD 05w02 TAMPPRCH (rw): TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs.
0x4000B00C C   FIELD 07w01 TAMPPUDIS (rw): TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample.
0x4000B02C B  REGISTER IER: TAMP interrupt enable register
0x4000B02C C   FIELD 00w01 TAMP1IE (rw): Tamper 1 interrupt enable
0x4000B02C C   FIELD 01w01 TAMP2IE (rw): Tamper 2 interrupt enable
0x4000B02C C   FIELD 18w01 ITAMP3IE (rw): Internal tamper 3 interrupt enable: LSE monitoring
0x4000B02C C   FIELD 19w01 ITAMP4IE (rw): Internal tamper 4 interrupt enable: HSE monitoring
0x4000B02C C   FIELD 20w01 ITAMP5IE (rw): Internal tamper 5 interrupt enable: RTC calendar overflow
0x4000B02C C   FIELD 21w01 ITAMP6IE (rw): Internal tamper 6 interrupt enable: ST manufacturer readout
0x4000B030 B  REGISTER SR: TAMP status register
0x4000B030 C   FIELD 00w01 TAMP1F (ro): TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP1 input.
0x4000B030 C   FIELD 01w01 TAMP2F (ro): TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP2 input.
0x4000B030 C   FIELD 18w01 ITAMP3F (ro): LSE monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3.
0x4000B030 C   FIELD 19w01 ITAMP4F (ro): HSE monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 4.
0x4000B030 C   FIELD 20w01 ITAMP5F (ro): RTC calendar overflow tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5.
0x4000B030 C   FIELD 21w01 ITAMP6F (ro): ST manufacturer readout tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6.
0x4000B034 B  REGISTER MISR: TAMP masked interrupt status register
0x4000B034 C   FIELD 00w01 TAMP1MF (ro): TAMP1 interrupt masked flag This flag is set by hardware when the tamper 1 interrupt is raised.
0x4000B034 C   FIELD 01w01 TAMP2MF (ro): TAMP2 interrupt masked flag This flag is set by hardware when the tamper 2 interrupt is raised.
0x4000B034 C   FIELD 18w01 ITAMP3MF (ro): LSE monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 3 interrupt is raised.
0x4000B034 C   FIELD 19w01 ITAMP4MF (ro): HSE monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 4 interrupt is raised.
0x4000B034 C   FIELD 20w01 ITAMP5MF (ro): RTC calendar overflow tamper interrupt masked flag This flag is set by hardware when the internal tamper 5 interrupt is raised.
0x4000B034 C   FIELD 21w01 ITAMP6MF (ro): ST manufacturer readout tamper interrupt masked flag This flag is set by hardware when the internal tamper 6 interrupt is raised.
0x4000B03C B  REGISTER SCR: TAMP status clear register
0x4000B03C C   FIELD 00w01 CTAMP1F (wo): Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register.
0x4000B03C C   FIELD 01w01 CTAMP2F (wo): Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register.
0x4000B03C C   FIELD 18w01 CITAMP3F (wo): Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register.
0x4000B03C C   FIELD 19w01 CITAMP4F (wo): Clear ITAMP4 detection flag Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register.
0x4000B03C C   FIELD 20w01 CITAMP5F (wo): Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register.
0x4000B03C C   FIELD 21w01 CITAMP6F (wo): Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register.
0x4000B100 B  REGISTER BKP0R: TAMP backup 0 register
0x4000B100 C   FIELD 00w32 BKP (rw): The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.
0x4000B104 B  REGISTER BKP1R: TAMP backup 1 register
0x4000B104 C   FIELD 00w32 BKP (rw): The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.
0x4000B108 B  REGISTER BKP2R: TAMP backup 2 register
0x4000B108 C   FIELD 00w32 BKP (rw): The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.
0x4000B10C B  REGISTER BKP3R: TAMP backup 3 register
0x4000B10C C   FIELD 00w32 BKP (rw): The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.
0x4000B110 B  REGISTER BKP4R: TAMP backup 4 register
0x4000B110 C   FIELD 00w32 BKP (rw): The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.
0x40010000 A PERIPHERAL SYSCFG
0x40010000 B  REGISTER CFGR1 (rw): SYSCFG configuration register 1
0x40010000 C   FIELD 00w02 MEM_MODE: Memory mapping selection bits
0x40010000 C   FIELD 03w01 PA11_RMP: PA11_RMP
0x40010000 C   FIELD 04w01 PA12_RMP: PA11 and PA12 remapping bit.
0x40010000 C   FIELD 05w01 IR_POL: IR output polarity selection
0x40010000 C   FIELD 06w02 IR_MOD: IR Modulation Envelope signal selection.
0x40010000 C   FIELD 08w01 BOOSTEN: I/O analog switch voltage booster enable
0x40010000 C   FIELD 09w01 UCPD1_STROBE: Strobe signal bit for UCPD1
0x40010000 C   FIELD 10w01 UCPD2_STROBE: Strobe signal bit for UCPD2
0x40010000 C   FIELD 16w01 I2C_PBx_FMP: Fast Mode Plus (FM+) driving capability activation bits
0x40010000 C   FIELD 17w01 I2C_PB7_FMP: I2C_PB7_FMP
0x40010000 C   FIELD 18w01 I2C_PB8_FMP: I2C_PB8_FMP
0x40010000 C   FIELD 19w01 I2C_PB9_FMP: I2C_PB9_FMP
0x40010000 C   FIELD 20w01 I2C1_FMP: FM+ driving capability activation for I2C1
0x40010000 C   FIELD 21w01 I2C2_FMP: FM+ driving capability activation for I2C2
0x40010000 C   FIELD 22w01 I2C_PA9_FMP: Fast Mode Plus (FM+) driving capability activation bits
0x40010000 C   FIELD 23w01 I2C_PA10_FMP: Fast Mode Plus (FM+) driving capability activation bits
0x40010000 C   FIELD 24w01 I2C3_FMP: I2C3_FMP
0x40010018 B  REGISTER CFGR2 (rw): SYSCFG configuration register 1
0x40010018 C   FIELD 00w01 LOCKUP_LOCK: Cortex-M0+ LOCKUP bit enable bit
0x40010018 C   FIELD 01w01 SRAM_PARITY_LOCK: SRAM parity lock bit
0x40010018 C   FIELD 03w01 ECC_LOCK: ECC error lock bit
0x40010018 C   FIELD 08w01 SRAM_PEF: SRAM parity error flag
0x40010030 A PERIPHERAL VREFBUF
0x40010030 B  REGISTER CSR: VREFBUF control and status register
0x40010030 C   FIELD 00w01 ENVR (rw): Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.
0x40010030 C   FIELD 01w01 HIZ (rw): High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration.
0x40010030 C   FIELD 02w01 VRS (rw): Voltage reference scale This bit selects the value generated by the voltage reference buffer.
0x40010030 C   FIELD 03w01 VRR (ro): Voltage reference buffer ready
0x40010034 B  REGISTER CCR (rw): VREFBUF calibration control register
0x40010034 C   FIELD 00w06 TRIM (rw): Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows the tuning of the internal reference buffer voltage.
0x40010080 B  REGISTER ITLINE0 (ro): interrupt line 0 status register
0x40010080 C   FIELD 00w01 WWDG: Window watchdog interrupt pending flag
0x40010088 B  REGISTER ITLINE2 (ro): interrupt line 2 status register
0x40010088 C   FIELD 00w01 TAMP: TAMP
0x40010088 C   FIELD 01w01 RTC: RTC
0x4001008C B  REGISTER ITLINE3 (ro): interrupt line 3 status register
0x4001008C C   FIELD 00w01 FLASH_ITF: FLASH_ITF
0x4001008C C   FIELD 01w01 FLASH_ECC: FLASH_ECC
0x40010090 B  REGISTER ITLINE4 (ro): interrupt line 4 status register
0x40010090 C   FIELD 00w01 RCC: RCC
0x40010090 C   FIELD 01w01 CRS: CRS
0x40010094 B  REGISTER ITLINE5 (ro): interrupt line 5 status register
0x40010094 C   FIELD 00w01 EXTI0: EXTI0
0x40010094 C   FIELD 01w01 EXTI1: EXTI1
0x40010098 B  REGISTER ITLINE6 (ro): interrupt line 6 status register
0x40010098 C   FIELD 00w01 EXTI2: EXTI2
0x40010098 C   FIELD 01w01 EXTI3: EXTI3
0x4001009C B  REGISTER ITLINE7 (ro): interrupt line 7 status register
0x4001009C C   FIELD 00w01 EXTI4: EXTI4
0x4001009C C   FIELD 01w01 EXTI5: EXTI5
0x4001009C C   FIELD 02w01 EXTI6: EXTI6
0x4001009C C   FIELD 03w01 EXTI7: EXTI7
0x4001009C C   FIELD 04w01 EXTI8: EXTI8
0x4001009C C   FIELD 05w01 EXTI9: EXTI9
0x4001009C C   FIELD 06w01 EXTI10: EXTI10
0x4001009C C   FIELD 07w01 EXTI11: EXTI11
0x4001009C C   FIELD 08w01 EXTI12: EXTI12
0x4001009C C   FIELD 09w01 EXTI13: EXTI13
0x4001009C C   FIELD 10w01 EXTI14: EXTI14
0x4001009C C   FIELD 11w01 EXTI15: EXTI15
0x400100A0 B  REGISTER ITLINE8 (ro): interrupt line 8 status register
0x400100A0 C   FIELD 00w01 UCPD1: UCPD1
0x400100A0 C   FIELD 01w01 UCPD2: UCPD2
0x400100A0 C   FIELD 02w01 USB: USB
0x400100A4 B  REGISTER ITLINE9 (ro): interrupt line 9 status register
0x400100A4 C   FIELD 00w01 DMA1_CH1: DMA1_CH1
0x400100A8 B  REGISTER ITLINE10 (ro): interrupt line 10 status register
0x400100A8 C   FIELD 00w01 DMA1_CH2: DMA1_CH1
0x400100A8 C   FIELD 01w01 DMA1_CH3: DMA1_CH3
0x400100AC B  REGISTER ITLINE11 (ro): interrupt line 11 status register
0x400100AC C   FIELD 00w01 DMAMUX: DMAMUX
0x400100AC C   FIELD 01w01 DMA1_CH4: DMA1_CH4
0x400100AC C   FIELD 02w01 DMA1_CH5: DMA1_CH5
0x400100AC C   FIELD 03w01 DMA1_CH6: DMA1_CH6
0x400100AC C   FIELD 04w01 DMA1_CH7: DMA1_CH7
0x400100B0 B  REGISTER ITLINE12 (ro): interrupt line 12 status register
0x400100B0 C   FIELD 00w01 ADC: ADC
0x400100B0 C   FIELD 01w01 COMP1: COMP1
0x400100B0 C   FIELD 02w01 COMP2: COMP2
0x400100B0 C   FIELD 03w01 COMP3: COMP3
0x400100B4 B  REGISTER ITLINE13 (ro): interrupt line 13 status register
0x400100B4 C   FIELD 00w01 TIM1_CCU: TIM1_CCU
0x400100B4 C   FIELD 01w01 TIM1_TRG: TIM1_TRG
0x400100B4 C   FIELD 02w01 TIM1_UPD: TIM1_UPD
0x400100B4 C   FIELD 03w01 TIM1_BRK: TIM1_BRK
0x400100B8 B  REGISTER ITLINE14 (ro): interrupt line 14 status register
0x400100B8 C   FIELD 00w01 TIM1_CC: TIM1_CC
0x400100BC B  REGISTER ITLINE15 (ro): interrupt line 15 status register
0x400100BC C   FIELD 00w01 TIM2: TIM2
0x400100C0 B  REGISTER ITLINE16 (ro): interrupt line 16 status register
0x400100C0 C   FIELD 00w01 TIM3: TIM3
0x400100C0 C   FIELD 01w01 TIM4: TIM4
0x400100C4 B  REGISTER ITLINE17 (ro): interrupt line 17 status register
0x400100C4 C   FIELD 00w01 TIM6: TIM6
0x400100C4 C   FIELD 01w01 DAC: DAC
0x400100C4 C   FIELD 02w01 LPTIM1: LPTIM1
0x400100C8 B  REGISTER ITLINE18 (ro): interrupt line 18 status register
0x400100C8 C   FIELD 00w01 TIM7: TIM7
0x400100C8 C   FIELD 01w01 LPTIM2: LPTIM2
0x400100CC B  REGISTER ITLINE19 (ro): interrupt line 19 status register
0x400100CC C   FIELD 00w01 TIM14: TIM14
0x400100D0 B  REGISTER ITLINE20 (ro): interrupt line 20 status register
0x400100D0 C   FIELD 00w01 TIM15: TIM15
0x400100D4 B  REGISTER ITLINE21 (ro): interrupt line 21 status register
0x400100D4 C   FIELD 00w01 TIM16: TIM16
0x400100D4 C   FIELD 01w01 FDCAN1_IT0: FDCAN1_IT0
0x400100D4 C   FIELD 02w01 FDCAN2_IT0: FDCAN2_IT0
0x400100D8 B  REGISTER ITLINE22 (ro): interrupt line 22 status register
0x400100D8 C   FIELD 00w01 TIM17: TIM17
0x400100D8 C   FIELD 01w01 FDCAN1_IT1: FDCAN1_IT1
0x400100D8 C   FIELD 02w01 FDCAN2_IT1: FDCAN2_IT1
0x400100DC B  REGISTER ITLINE23 (ro): interrupt line 23 status register
0x400100DC C   FIELD 00w01 I2C1: I2C1
0x400100E0 B  REGISTER ITLINE24 (ro): interrupt line 24 status register
0x400100E0 C   FIELD 00w01 I2C2: I2C2
0x400100E0 C   FIELD 01w01 I2C3: I2C3
0x400100E4 B  REGISTER ITLINE25 (ro): interrupt line 25 status register
0x400100E4 C   FIELD 00w01 SPI1: SPI1
0x400100E8 B  REGISTER ITLINE26 (ro): interrupt line 26 status register
0x400100E8 C   FIELD 00w01 SPI2: SPI2
0x400100E8 C   FIELD 14w01 SPI3: SPI3
0x400100EC B  REGISTER ITLINE27 (ro): interrupt line 27 status register
0x400100EC C   FIELD 00w01 USART1: USART1
0x400100F0 B  REGISTER ITLINE28 (ro): interrupt line 28 status register
0x400100F0 C   FIELD 00w01 USART2: USART2
0x400100F0 C   FIELD 01w01 LPUART2: LPUART2
0x400100F4 B  REGISTER ITLINE29 (ro): interrupt line 29 status register
0x400100F4 C   FIELD 00w01 USART3: USART3
0x400100F4 C   FIELD 01w01 USART4: USART4
0x400100F4 C   FIELD 02w01 LPUART1: LPUART1
0x400100F4 C   FIELD 03w01 USART5: USART5
0x400100F4 C   FIELD 04w01 USART6: USART6
0x400100F8 B  REGISTER ITLINE30 (ro): interrupt line 25 status register
0x400100F8 C   FIELD 00w01 CEC: CEC
0x400100FC B  REGISTER ITLINE31 (ro): interrupt line 25 status register
0x400100FC C   FIELD 00w01 RNG: RNG
0x400100FC C   FIELD 01w01 AES: AES
0x40012400 A PERIPHERAL ADC
0x40012400 B  REGISTER ISR (rw): ADC interrupt and status register
0x40012400 C   FIELD 00w01 ADRDY (rw): ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 01w01 EOSMP (rw): End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1'.
0x40012400 C   FIELD 02w01 EOC (rw): End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
0x40012400 C   FIELD 03w01 EOS (rw): End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 04w01 OVR (rw): ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 07w01 AWD1 (rw): Analog watchdog 1 flag
0x40012400 C   FIELD 08w01 AWD2 (rw): Analog watchdog 2 flag
0x40012400 C   FIELD 09w01 AWD3 (rw): Analog watchdog 3 flag
0x40012400 C   FIELD 11w01 EOCAL (rw): End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
0x40012400 C   FIELD 13w01 CCRDY (rw): Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
0x40012404 B  REGISTER IER (rw): ADC interrupt enable register
0x40012404 C   FIELD 00w01 ADRDYIE (rw): ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 01w01 EOSMPIE (rw): End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 02w01 EOCIE (rw): End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 03w01 EOSIE (rw): End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 04w01 OVRIE (rw): Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 07w01 AWD1IE (rw): Analog watchdog 1 interrupt enable
0x40012404 C   FIELD 08w01 AWD2IE (rw): Analog watchdog 2 interrupt enable
0x40012404 C   FIELD 09w01 AWD3IE (rw): Analog watchdog 3 interrupt enable
0x40012404 C   FIELD 11w01 EOCALIE (rw): End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012404 C   FIELD 13w01 CCRDYIE (rw): Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012408 B  REGISTER CR (rw): ADC control register
0x40012408 C   FIELD 00w01 ADEN (rw): ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
0x40012408 C   FIELD 01w01 ADDIS (rw): ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing)
0x40012408 C   FIELD 02w01 ADSTART (rw): ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
0x40012408 C   FIELD 04w01 ADSTP (rw): ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
0x40012408 C   FIELD 28w01 ADVREGEN (rw): ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
0x40012408 C   FIELD 31w01 ADCAL (rw): ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
0x4001240C B  REGISTER CFGR1 (rw): ADC configuration register 1
0x4001240C C   FIELD 00w01 DMAEN (rw): Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 01w01 DMACFG (rw): Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1. For more details, refer to page391 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 02w01 SCANDIR (rw): Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x4001240C C   FIELD 03w02 RES (rw): Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADEN=0.
0x4001240C C   FIELD 05w01 ALIGN (rw): Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page389 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 06w03 EXTSEL (rw): External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 10w02 EXTEN (rw): External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 12w01 OVRMOD (rw): Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 13w01 CONT (rw): Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 14w01 WAIT (rw): Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 15w01 AUTOFF (rw): Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 16w01 DISCEN (rw): Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 21w01 CHSELRMOD (rw): Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
0x4001240C C   FIELD 22w01 AWD1SGL (rw): Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 23w01 AWD1EN (rw): Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x4001240C C   FIELD 26w05 AWD1CH (rw): Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012410 B  REGISTER CFGR2 (rw): ADC configuration register 2
0x40012410 C   FIELD 00w01 OVSE (rw): Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 02w03 OVSR (rw): Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 05w04 OVSS (rw): Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 09w01 TOVS (rw): Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x40012410 C   FIELD 29w01 LFTRIG (rw): Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
0x40012410 C   FIELD 30w02 CKMODE (rw): ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
0x40012414 B  REGISTER SMPR (rw): ADC sampling time register
0x40012414 C   FIELD 00w03 SMP1 (rw): Sampling time selection 1
0x40012414 C   FIELD 04w03 SMP2 (rw): Sampling time selection 2
0x40012414 C   FIELD 08w01 SMPSEL0 (rw): Channel-0 sampling time selection
0x40012414 C   FIELD 09w01 SMPSEL1 (rw): Channel-1 sampling time selection
0x40012414 C   FIELD 10w01 SMPSEL2 (rw): Channel-2 sampling time selection
0x40012414 C   FIELD 11w01 SMPSEL3 (rw): Channel-3 sampling time selection
0x40012414 C   FIELD 12w01 SMPSEL4 (rw): Channel-4 sampling time selection
0x40012414 C   FIELD 13w01 SMPSEL5 (rw): Channel-5 sampling time selection
0x40012414 C   FIELD 14w01 SMPSEL6 (rw): Channel-6 sampling time selection
0x40012414 C   FIELD 15w01 SMPSEL7 (rw): Channel-7 sampling time selection
0x40012414 C   FIELD 16w01 SMPSEL8 (rw): Channel-8 sampling time selection
0x40012414 C   FIELD 17w01 SMPSEL9 (rw): Channel-9 sampling time selection
0x40012414 C   FIELD 18w01 SMPSEL10 (rw): Channel-10 sampling time selection
0x40012414 C   FIELD 19w01 SMPSEL11 (rw): Channel-11 sampling time selection
0x40012414 C   FIELD 20w01 SMPSEL12 (rw): Channel-12 sampling time selection
0x40012414 C   FIELD 21w01 SMPSEL13 (rw): Channel-13 sampling time selection
0x40012414 C   FIELD 22w01 SMPSEL14 (rw): Channel-14 sampling time selection
0x40012414 C   FIELD 23w01 SMPSEL15 (rw): Channel-15 sampling time selection
0x40012414 C   FIELD 24w01 SMPSEL16 (rw): Channel-16 sampling time selection
0x40012414 C   FIELD 25w01 SMPSEL17 (rw): Channel-17 sampling time selection
0x40012414 C   FIELD 26w01 SMPSEL18 (rw): Channel-18 sampling time selection
0x40012420 B  REGISTER AWD1TR (rw): ADC watchdog threshold register
0x40012420 C   FIELD 00w12 LT1 (rw): Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page395.
0x40012420 C   FIELD 16w12 HT1 (rw): Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page395.
0x40012424 B  REGISTER AWD2TR (rw): ADC watchdog threshold register
0x40012424 C   FIELD 00w12 LT2 (rw): Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page395.
0x40012424 C   FIELD 16w12 HT2 (rw): Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page395.
0x40012428 B  REGISTER CHSELR0 (rw): ADC channel selection register
0x40012428 B  REGISTER CHSELR1 (rw): ADC channel selection register
0x40012428 C   FIELD 00w01 CHSEL0 (rw): Channel-0 selection
0x40012428 C   FIELD 00w04 SQ1 (rw): 1 conversion of the sequence
0x40012428 C   FIELD 01w01 CHSEL1 (rw): Channel-1 selection
0x40012428 C   FIELD 02w01 CHSEL2 (rw): Channel-2 selection
0x40012428 C   FIELD 03w01 CHSEL3 (rw): Channel-3 selection
0x40012428 C   FIELD 04w01 CHSEL4 (rw): Channel-4 selection
0x40012428 C   FIELD 04w04 SQ2 (rw): 2 conversion of the sequence
0x40012428 C   FIELD 05w01 CHSEL5 (rw): Channel-5 selection
0x40012428 C   FIELD 06w01 CHSEL6 (rw): Channel-6 selection
0x40012428 C   FIELD 07w01 CHSEL7 (rw): Channel-7 selection
0x40012428 C   FIELD 08w01 CHSEL8 (rw): Channel-8 selection
0x40012428 C   FIELD 08w04 SQ3 (rw): 3 conversion of the sequence
0x40012428 C   FIELD 09w01 CHSEL9 (rw): Channel-9 selection
0x40012428 C   FIELD 10w01 CHSEL10 (rw): Channel-10 selection
0x40012428 C   FIELD 11w01 CHSEL11 (rw): Channel-11 selection
0x40012428 C   FIELD 12w01 CHSEL12 (rw): Channel-12 selection
0x40012428 C   FIELD 12w04 SQ4 (rw): 4 conversion of the sequence
0x40012428 C   FIELD 13w01 CHSEL13 (rw): Channel-13 selection
0x40012428 C   FIELD 14w01 CHSEL14 (rw): Channel-14 selection
0x40012428 C   FIELD 15w01 CHSEL15 (rw): Channel-15 selection
0x40012428 C   FIELD 16w01 CHSEL16 (rw): Channel-16 selection
0x40012428 C   FIELD 16w04 SQ5 (rw): 5 conversion of the sequence
0x40012428 C   FIELD 17w01 CHSEL17 (rw): Channel-17 selection
0x40012428 C   FIELD 18w01 CHSEL18 (rw): Channel-18 selection
0x40012428 C   FIELD 20w04 SQ6 (rw): 6 conversion of the sequence
0x40012428 C   FIELD 24w04 SQ7 (rw): 7 conversion of the sequence
0x40012428 C   FIELD 28w04 SQ8 (rw): 8 conversion of the sequence
0x4001242C B  REGISTER AWD3TR (rw): ADC watchdog threshold register
0x4001242C C   FIELD 00w12 LT3 (rw): Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page395.
0x4001242C C   FIELD 16w12 HT3 (rw): Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page395.
0x40012440 B  REGISTER DR (ro): ADC data register
0x40012440 C   FIELD 00w16 DATA (ro): Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page389. Just after a calibration is complete, DATA[6:0] contains the calibration factor.
0x400124A0 B  REGISTER AWD2CR (rw): ADC Analog Watchdog 2 Configuration register
0x400124A0 C   FIELD 00w01 AWD2CH0 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 01w01 AWD2CH1 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 02w01 AWD2CH2 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 03w01 AWD2CH3 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 04w01 AWD2CH4 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 05w01 AWD2CH5 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 06w01 AWD2CH6 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 07w01 AWD2CH7 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 08w01 AWD2CH8 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 09w01 AWD2CH9 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 10w01 AWD2CH10 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 11w01 AWD2CH11 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 12w01 AWD2CH12 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 13w01 AWD2CH13 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 14w01 AWD2CH14 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 15w01 AWD2CH15 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 16w01 AWD2CH16 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 17w01 AWD2CH17 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A0 C   FIELD 18w01 AWD2CH18 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 B  REGISTER AWD3CR (rw): ADC Analog Watchdog 3 Configuration register
0x400124A4 C   FIELD 00w01 AWD3CH0 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 01w01 AWD3CH1 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 02w01 AWD3CH2 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 03w01 AWD3CH3 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 04w01 AWD3CH4 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 05w01 AWD3CH5 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 06w01 AWD3CH6 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 07w01 AWD3CH7 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 08w01 AWD3CH8 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 09w01 AWD3CH9 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 10w01 AWD3CH10 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 11w01 AWD3CH11 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 12w01 AWD3CH12 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 13w01 AWD3CH13 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 14w01 AWD3CH14 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 15w01 AWD3CH15 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 16w01 AWD3CH16 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 17w01 AWD3CH17 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124A4 C   FIELD 18w01 AWD3CH18 (rw): Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x400124B4 B  REGISTER CALFACT (rw): ADC Calibration factor
0x400124B4 C   FIELD 00w07 CALFACT (rw): Calibration factor These bits are written by hardware or by software. Once a calibration is complete,they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection.
0x40012708 B  REGISTER CCR (rw): ADC common configuration register
0x40012708 C   FIELD 18w04 PRESC (rw): ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
0x40012708 C   FIELD 22w01 VREFEN (rw): VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x40012708 C   FIELD 23w01 TSEN (rw): Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
0x40012708 C   FIELD 24w01 VBATEN (rw): VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)
0x40012C00 A PERIPHERAL TIM1
0x40012C00 B  REGISTER CR1 (rw): control register 1
0x40012C00 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40012C00 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40012C00 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40012C00 C   FIELD 03w01 OPM (rw): One pulse mode
0x40012C00 C   FIELD 04w01 DIR (rw): Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
0x40012C00 C   FIELD 05w02 CMS (rw): Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed
0x40012C00 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40012C00 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT.
0x40012C00 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40012C04 B  REGISTER CR2 (rw): control register 2
0x40012C04 C   FIELD 00w01 CCPC (rw): Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0x40012C04 C   FIELD 02w01 CCUS (rw): Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
0x40012C04 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40012C04 C   FIELD 04w03 MMS (rw): Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40012C04 C   FIELD 07w01 TI1S (rw): TI1 selection
0x40012C04 C   FIELD 08w01 OIS1 (rw): Output Idle state (OC1 output)
0x40012C04 C   FIELD 09w01 OIS1N (rw): Output Idle state (OC1N output)
0x40012C04 C   FIELD 10w01 OIS2 (rw): Output Idle state (OC2 output)
0x40012C04 C   FIELD 11w01 OIS2N (rw): Output Idle state (OC2N output)
0x40012C04 C   FIELD 12w01 OIS3 (rw): Output Idle state (OC3 output)
0x40012C04 C   FIELD 13w01 OIS3N (rw): Output Idle state (OC3N output)
0x40012C04 C   FIELD 14w01 OIS4 (rw): Output Idle state (OC4 output)
0x40012C04 C   FIELD 16w01 OIS5 (rw): Output Idle state (OC5 output)
0x40012C04 C   FIELD 18w01 OIS6 (rw): Output Idle state (OC6 output)
0x40012C04 C   FIELD 20w04 MMS2 (rw): Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40012C08 B  REGISTER SMCR (rw): slave mode control register
0x40012C08 C   FIELD 00w03 SMS1 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40012C08 C   FIELD 03w01 OCCS (rw): OCREF clear selection This bit is used to select the OCREF clear source.
0x40012C08 C   FIELD 04w03 TS1 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40012C08 C   FIELD 07w01 MSM (rw): Master/slave mode
0x40012C08 C   FIELD 08w04 ETF (rw): External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0x40012C08 C   FIELD 12w02 ETPS (rw): External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
0x40012C08 C   FIELD 14w01 ECE (rw): External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
0x40012C08 C   FIELD 15w01 ETP (rw): External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
0x40012C08 C   FIELD 16w01 SMS2 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40012C08 C   FIELD 20w02 TS2 (rw): Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40012C0C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x40012C0C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x40012C0C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x40012C0C C   FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x40012C0C C   FIELD 03w01 CC3IE (rw): Capture/Compare 3 interrupt enable
0x40012C0C C   FIELD 04w01 CC4IE (rw): Capture/Compare 4 interrupt enable
0x40012C0C C   FIELD 05w01 COMIE (rw): COM interrupt enable
0x40012C0C C   FIELD 06w01 TIE (rw): Trigger interrupt enable
0x40012C0C C   FIELD 07w01 BIE (rw): Break interrupt enable
0x40012C0C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x40012C0C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x40012C0C C   FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x40012C0C C   FIELD 11w01 CC3DE (rw): Capture/Compare 3 DMA request enable
0x40012C0C C   FIELD 12w01 CC4DE (rw): Capture/Compare 4 DMA request enable
0x40012C0C C   FIELD 13w01 COMDE (rw): COM DMA request enable
0x40012C0C C   FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40012C10 B  REGISTER SR (rw): status register
0x40012C10 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40012C10 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40012C10 C   FIELD 02w01 CC2IF (rw): Capture/compare 2 interrupt flag
0x40012C10 C   FIELD 03w01 CC3IF (rw): Capture/compare 3 interrupt flag
0x40012C10 C   FIELD 04w01 CC4IF (rw): Capture/compare 4 interrupt flag
0x40012C10 C   FIELD 05w01 COMIF (rw): COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software.
0x40012C10 C   FIELD 06w01 TIF (rw): Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
0x40012C10 C   FIELD 07w01 BIF (rw): Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0x40012C10 C   FIELD 08w01 B2IF (rw): Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active.
0x40012C10 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40012C10 C   FIELD 10w01 CC2OF (rw): Capture/Compare 2 overcapture flag
0x40012C10 C   FIELD 11w01 CC3OF (rw): Capture/Compare 3 overcapture flag
0x40012C10 C   FIELD 12w01 CC4OF (rw): Capture/Compare 4 overcapture flag
0x40012C10 C   FIELD 13w01 SBIF (rw): System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation.
0x40012C10 C   FIELD 16w01 CC5IF (rw): Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output)
0x40012C10 C   FIELD 17w01 CC6IF (rw): Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output)
0x40012C14 B  REGISTER EGR (wo): event generation register
0x40012C14 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40012C14 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40012C14 C   FIELD 02w01 CC2G (wo): Capture/compare 2 generation
0x40012C14 C   FIELD 03w01 CC3G (wo): Capture/compare 3 generation
0x40012C14 C   FIELD 04w01 CC4G (wo): Capture/compare 4 generation
0x40012C14 C   FIELD 05w01 COMG (wo): Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output.
0x40012C14 C   FIELD 06w01 TG (wo): Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40012C14 C   FIELD 07w01 BG (wo): Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40012C14 C   FIELD 08w01 B2G (wo): Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40012C18 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (output mode)
0x40012C18 B  REGISTER CCMR1_Output (rw): capture/compare mode register 1 (output mode)
0x40012C18 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
0x40012C18 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40012C18 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40012C18 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40012C18 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40012C18 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40012C18 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40012C18 C   FIELD 07w01 OC1CE (rw): Output compare 1 clear enable
0x40012C18 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40012C18 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER).
0x40012C18 C   FIELD 10w01 OC2FE (rw): Output compare 2 fast enable
0x40012C18 C   FIELD 10w02 IC2PSC (rw): Input capture 2 prescaler
0x40012C18 C   FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40012C18 C   FIELD 12w03 OC2M (rw): Output compare 2 mode
0x40012C18 C   FIELD 12w04 IC2F (rw): Input capture 2 filter
0x40012C18 C   FIELD 15w01 OC2CE (rw): Output compare 2 clear enable
0x40012C18 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40012C18 C   FIELD 24w01 OC2M_3 (rw): Output compare 2 mode, bit 3
0x40012C1C B  REGISTER CCMR2_Input (rw): capture/compare mode register 2 (output mode)
0x40012C1C B  REGISTER CCMR2_Output (rw): capture/compare mode register 2 (output mode)
0x40012C1C C   FIELD 00w02 CC3S (=TIM1.CCMR1_Output.CC%sS) (rw): Capture/Compare 3 selection
0x40012C1C C   FIELD 00w02 CC3S (rw): Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER).
0x40012C1C C   FIELD 02w01 OC3FE (=TIM1.CCMR1_Output.OC%sFE) (rw): Output compare 3 fast enable
0x40012C1C C   FIELD 02w02 IC3PSC (=TIM1.CCMR1_Input.IC%sPSC) (rw): Input capture 3 prescaler
0x40012C1C C   FIELD 03w01 OC3PE (=TIM1.CCMR1_Output.OC%sPE) (rw): Output compare 3 preload enable
0x40012C1C C   FIELD 04w03 OC3M (=TIM1.CCMR1_Output.OC%sM) (rw): Output compare 3 mode
0x40012C1C C   FIELD 04w04 IC3F (=TIM1.CCMR1_Input.IC%sF) (rw): Input capture 3 filter
0x40012C1C C   FIELD 07w01 OC3CE (=TIM1.CCMR1_Output.OC%sCE) (rw): Output compare 3 clear enable
0x40012C1C C   FIELD 08w02 CC4S (=TIM1.CCMR1_Output.CC%sS) (rw): Capture/Compare 4 selection
0x40012C1C C   FIELD 08w02 CC4S (rw): Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER).
0x40012C1C C   FIELD 10w01 OC4FE (=TIM1.CCMR1_Output.OC%sFE) (rw): Output compare 4 fast enable
0x40012C1C C   FIELD 10w02 IC4PSC (=TIM1.CCMR1_Input.IC%sPSC) (rw): Input capture 4 prescaler
0x40012C1C C   FIELD 11w01 OC4PE (=TIM1.CCMR1_Output.OC%sPE) (rw): Output compare 4 preload enable
0x40012C1C C   FIELD 12w03 OC4M (=TIM1.CCMR1_Output.OC%sM) (rw): Output compare 4 mode
0x40012C1C C   FIELD 12w04 IC4F (=TIM1.CCMR1_Input.IC%sF) (rw): Input capture 4 filter
0x40012C1C C   FIELD 15w01 OC4CE (=TIM1.CCMR1_Output.OC%sCE) (rw): Output compare 4 clear enable
0x40012C1C C   FIELD 16w01 OC3M_3 (=TIM1.CCMR1_Output.OC%sM_3) (rw): Output compare 3 mode, bit 3
0x40012C1C C   FIELD 24w01 OC4M_3 (=TIM1.CCMR1_Output.OC%sM_3) (rw): Output compare 4 mode, bit 3
0x40012C20 B  REGISTER CCER (rw): capture/compare enable register
0x40012C20 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40012C20 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40012C20 C   FIELD 02w01 CC1NE (rw): Capture/Compare 1 complementary output enable
0x40012C20 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40012C20 C   FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable
0x40012C20 C   FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity
0x40012C20 C   FIELD 06w01 CC2NE (rw): Capture/Compare 2 complementary output enable
0x40012C20 C   FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity
0x40012C20 C   FIELD 08w01 CC3E (rw): Capture/Compare 3 output enable
0x40012C20 C   FIELD 09w01 CC3P (rw): Capture/Compare 3 output Polarity
0x40012C20 C   FIELD 10w01 CC3NE (rw): Capture/Compare 3 complementary output enable
0x40012C20 C   FIELD 11w01 CC3NP (rw): Capture/Compare 3 output Polarity
0x40012C20 C   FIELD 12w01 CC4E (rw): Capture/Compare 4 output enable
0x40012C20 C   FIELD 13w01 CC4P (rw): Capture/Compare 4 output Polarity
0x40012C20 C   FIELD 15w01 CC4NP (rw): Capture/Compare 4 output Polarity
0x40012C20 C   FIELD 16w01 CC5E (rw): Capture/Compare 5 output enable
0x40012C20 C   FIELD 17w01 CC5P (rw): Capture/Compare 5 output Polarity
0x40012C20 C   FIELD 20w01 CC6E (rw): Capture/Compare 6 output enable
0x40012C20 C   FIELD 21w01 CC6P (rw): Capture/Compare 6 output Polarity
0x40012C24 B  REGISTER CNT: counter
0x40012C24 C   FIELD 00w16 CNT (rw): Counter value
0x40012C24 C   FIELD 31w01 UIFCPY (ro): UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
0x40012C28 B  REGISTER PSC (rw): prescaler
0x40012C28 C   FIELD 00w16 PSC (rw): Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode').
0x40012C2C B  REGISTER ARR (rw): auto-reload register
0x40012C2C C   FIELD 00w16 ARR (rw): Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40012C30 B  REGISTER RCR (rw): repetition counter register
0x40012C30 C   FIELD 00w16 REP: Repetition counter value
0x40012C34 B  REGISTER CCR1 (rw): capture/compare register
0x40012C34 C   FIELD 00w16 CCR: Capture/Compare value
0x40012C38 B  REGISTER CCR2 (rw): capture/compare register
0x40012C38 C   FIELD 00w16 CCR: Capture/Compare value
0x40012C3C B  REGISTER CCR3 (rw): capture/compare register
0x40012C3C C   FIELD 00w16 CCR: Capture/Compare value
0x40012C40 B  REGISTER CCR4 (rw): capture/compare register
0x40012C40 C   FIELD 00w16 CCR: Capture/Compare value
0x40012C44 B  REGISTER BDTR (rw): break and dead-time register
0x40012C44 C   FIELD 00w08 DTG (rw): Dead-time generator setup
0x40012C44 C   FIELD 08w02 LOCK (rw): Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
0x40012C44 C   FIELD 10w01 OSSI (rw): Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 11w01 OSSR (rw): Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 12w01 BKE (rw): Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 13w01 BKP (rw): Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 14w01 AOE (rw): Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 15w01 MOE (rw): Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A).
0x40012C44 C   FIELD 16w04 BKF (rw): Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 20w04 BK2F (rw): Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C44 C   FIELD 24w01 BK2E (rw): Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 25w01 BK2P (rw): Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 26w01 BKDSRM (rw): Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 27w01 BK2DSRM (rw): Break2 Disarm Refer to BKDSRM description
0x40012C44 C   FIELD 28w01 BKBID (rw): Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40012C44 C   FIELD 29w01 BK2BID (rw): Break2 bidirectional Refer to BKBID description
0x40012C48 B  REGISTER DCR (rw): DMA control register
0x40012C48 C   FIELD 00w05 DBA (rw): DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
0x40012C48 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA.
0x40012C4C B  REGISTER DMAR (rw): DMA address for full transfer
0x40012C4C C   FIELD 00w32 DMAB (rw): DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
0x40012C50 B  REGISTER OR1 (rw): option register 1
0x40012C50 C   FIELD 00w01 OCREF_CLR (rw): Ocref_clr source selection This bit selects the ocref_clr input source.
0x40012C54 B  REGISTER CCMR3_Output (rw): capture/compare mode register 2 (output mode)
0x40012C54 C   FIELD 02w01 OC5FE (=TIM1.CCMR1_Output.OC%sFE): Output compare 5 fast enable
0x40012C54 C   FIELD 03w01 OC5PE (=TIM1.CCMR1_Output.OC%sPE): Output compare 5 preload enable
0x40012C54 C   FIELD 04w03 OC5M (=TIM1.CCMR1_Output.OC%sM): Output compare 5 mode
0x40012C54 C   FIELD 07w01 OC5CE (=TIM1.CCMR1_Output.OC%sCE): Output compare 5 clear enable
0x40012C54 C   FIELD 10w01 OC6FE (=TIM1.CCMR1_Output.OC%sFE): Output compare 6 fast enable
0x40012C54 C   FIELD 11w01 OC6PE (=TIM1.CCMR1_Output.OC%sPE): Output compare 6 preload enable
0x40012C54 C   FIELD 12w03 OC6M (=TIM1.CCMR1_Output.OC%sM): Output compare 6 mode
0x40012C54 C   FIELD 15w01 OC6CE (=TIM1.CCMR1_Output.OC%sCE): Output compare 6 clear enable
0x40012C54 C   FIELD 16w01 OC5M_3 (=TIM1.CCMR1_Output.OC%sM_3): Output compare 5 mode, bit 3
0x40012C54 C   FIELD 24w01 OC6M_3 (=TIM1.CCMR1_Output.OC%sM_3): Output compare 6 mode, bit 3
0x40012C58 B  REGISTER CCR5 (rw): capture/compare register
0x40012C58 C   FIELD 00w16 CCR (rw): Capture/Compare value
0x40012C58 C   FIELD 29w01 GC5C1 (rw): Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
0x40012C58 C   FIELD 30w01 GC5C2 (rw): Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
0x40012C58 C   FIELD 31w01 GC5C3 (rw): Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals.
0x40012C5C B  REGISTER CCR6 (rw): capture/compare register
0x40012C5C C   FIELD 00w16 CCR: Capture/Compare value
0x40012C60 B  REGISTER AF1 (rw): DMA address for full transfer
0x40012C60 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C60 C   FIELD 01w01 BKCMP1E (rw): BRK COMP1 enable This bit enables the COMP1 for the timer's BRK input. COMP1 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C60 C   FIELD 02w01 BKCMP2E (rw): BRK COMP2 enable This bit enables the COMP2 for the timer's BRK input. COMP2 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C60 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C60 C   FIELD 10w01 BKCMP1P (rw): BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C60 C   FIELD 11w01 BKCMP2P (rw): BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C60 C   FIELD 14w04 ETRSEL (rw): ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C64 B  REGISTER AF2 (rw): DMA address for full transfer
0x40012C64 C   FIELD 00w01 BK2INE (rw): BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer's BRK2 input. BKIN2 input is 'ORed' with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C64 C   FIELD 01w01 BK2CMP1E (rw): BRK2 COMP1 enable This bit enables the COMP1 for the timer's BRK2 input. COMP1 output is 'ORed' with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C64 C   FIELD 02w01 BK2CMP2E (rw): BRK2 COMP2 enable This bit enables the COMP2 for the timer's BRK2 input. COMP2 output is 'ORed' with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C64 C   FIELD 09w01 BK2INP (rw): BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C64 C   FIELD 10w01 BK2CMP1P (rw): BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C64 C   FIELD 11w01 BK2CMP2P (rw): BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40012C68 B  REGISTER TISEL (rw): TIM1 timer input selection register
0x40012C68 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40012C68 C   FIELD 08w04 TI2SEL (rw): selects TI2[0] to TI2[15] input Others: Reserved
0x40012C68 C   FIELD 16w04 TI3SEL (rw): selects TI3[0] to TI3[15] input Others: Reserved
0x40012C68 C   FIELD 24w04 TI4SEL (rw): selects TI4[0] to TI4[15] input Others: Reserved
0x40013000 A PERIPHERAL SPI1
0x40013000 B  REGISTER CR1: SPI control register 1
0x40013000 C   FIELD 00w01 CPHA (rw): Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.
0x40013000 C   FIELD 01w01 CPOL (rw): Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.
0x40013000 C   FIELD 02w01 MSTR (rw): Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode.
0x40013000 C   FIELD 03w03 BR (rw): Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode.
0x40013000 C   FIELD 06w01 SPE (rw): SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page1021. This bit is not used in I2S mode.
0x40013000 C   FIELD 07w01 LSBFIRST (rw): Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode.
0x40013000 C   FIELD 08w01 SSI (rw): Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode.
0x40013000 C   FIELD 09w01 SSM (rw): Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode.
0x40013000 C   FIELD 10w01 RXONLY (rw): Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode.
0x40013000 C   FIELD 11w01 CRCL (rw): CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = '0') for correct operation. This bit is not used in I2S mode.
0x40013000 C   FIELD 12w01 CRCNEXT (rw): Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI_DR register. This bit is not used in I2S mode.
0x40013000 C   FIELD 13w01 CRCEN (rw): Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = '0') for correct operation. This bit is not used in I2S mode.
0x40013000 C   FIELD 14w01 BIDIOE (rw): Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode.
0x40013000 C   FIELD 15w01 BIDIMODE (rw): Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode.
0x40013004 B  REGISTER CR2: SPI control register 2
0x40013004 C   FIELD 00w01 RXDMAEN (rw): Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set.
0x40013004 C   FIELD 01w01 TXDMAEN (rw): Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set.
0x40013004 C   FIELD 02w01 SSOE (rw): SS output enable Note: This bit is not used in I2S mode and SPI TI mode.
0x40013004 C   FIELD 03w01 NSSP (rw): NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = '1', or FRF = '1'. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode.
0x40013004 C   FIELD 04w01 FRF (rw): Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode.
0x40013004 C   FIELD 05w01 ERRIE (rw): Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode).
0x40013004 C   FIELD 06w01 RXNEIE (rw): RX buffer not empty interrupt enable
0x40013004 C   FIELD 07w01 TXEIE (rw): Tx buffer empty interrupt enable
0x40013004 C   FIELD 08w04 DS (rw): Data size These bits configure the data length for SPI transfers. If software attempts to write one of the 'Not used' values, they are forced to the value '0111' (8-bit) Note: These bits are not used in I2S mode.
0x40013004 C   FIELD 12w01 FRXTH (rw): FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode.
0x40013004 C   FIELD 13w01 LDMA_RX (rw): Last DMA transfer for reception
0x40013004 C   FIELD 14w01 LDMA_TX (rw): Last DMA transfer for transmission
0x40013008 B  REGISTER SR: SPI status register
0x40013008 C   FIELD 00w01 RXNE (ro): Receive buffer not empty
0x40013008 C   FIELD 01w01 TXE (ro): Transmit buffer empty
0x40013008 C   FIELD 02w01 CHSIDE (ro): Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode.
0x40013008 C   FIELD 03w01 UDR (ro): Underrun flag This flag is set by hardware and reset by a software sequence. Refer to page1057 for the software sequence. Note: This bit is not used in SPI mode.
0x40013008 C   FIELD 04w01 CRCERR (rw): CRC error flag Note: This flag is set by hardware and cleared by software writing 0. This bit is not used in I2S mode.
0x40013008 C   FIELD 05w01 MODF (ro): Mode fault This flag is set by hardware and reset by a software sequence. Refer to (MODF) on page1031 for the software sequence. Note: This bit is not used in I2S mode.
0x40013008 C   FIELD 06w01 OVR (ro): Overrun flag This flag is set by hardware and reset by a software sequence. Refer to page1057 for the software sequence.
0x40013008 C   FIELD 07w01 BSY (ro): Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to and .
0x40013008 C   FIELD 08w01 FRE (ro): Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to error flags and . This flag is set by hardware and reset when SPI_SR is read by software.
0x40013008 C   FIELD 09w02 FRLVL (ro): FIFO reception level
0x40013008 C   FIELD 11w02 FTLVL (ro): FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I2S mode.
0x4001300C B  REGISTER DR8 (rw): Direct 8-bit access to data register
0x4001300C B  REGISTER DR: SPI data register
0x4001300C C   FIELD 00w08 DR: Data register
0x4001300C C   FIELD 00w16 DR (rw): Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used.
0x40013010 B  REGISTER CRCPR: SPI CRC polynomial register
0x40013010 C   FIELD 00w16 CRCPOLY (rw): CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required.
0x40013014 B  REGISTER RXCRCR: SPI Rx CRC register
0x40013014 C   FIELD 00w16 RXCRC (ro): Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not used in I2S mode.
0x40013018 B  REGISTER TXCRCR: SPI Tx CRC register
0x40013018 C   FIELD 00w16 TXCRC (ro): Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode.
0x4001301C B  REGISTER I2SCFGR: SPI_I2S configuration register
0x4001301C C   FIELD 00w01 CHLEN (rw): Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode.
0x4001301C C   FIELD 01w02 DATLEN (rw): Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode.
0x4001301C C   FIELD 03w01 CKPOL (rw): Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals.
0x4001301C C   FIELD 04w02 I2SSTD (rw): I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode.
0x4001301C C   FIELD 07w01 PCMSYNC (rw): PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode.
0x4001301C C   FIELD 08w02 I2SCFG (rw): I2S configuration mode Note: These bits should be configured when the I2S is disabled. They are not used in SPI mode.
0x4001301C C   FIELD 10w01 I2SE (rw): I2S enable Note: This bit is not used in SPI mode.
0x4001301C C   FIELD 11w01 I2SMOD (rw): I2S mode selection Note: This bit should be configured when the SPI is disabled.
0x4001301C C   FIELD 12w01 ASTRTEN (rw): Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information.
0x40013020 B  REGISTER I2SPR: SPI_I2S prescaler register
0x40013020 C   FIELD 00w08 I2SDIV (rw): I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to . Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. They are not used in SPI mode.
0x40013020 C   FIELD 08w01 ODD (rw): Odd factor for the prescaler Refer to . Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode.
0x40013020 C   FIELD 09w01 MCKOE (rw): Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode.
0x40013800 A PERIPHERAL USART1
0x40013800 B  REGISTER CR1 (rw): Control register 1
0x40013800 C   FIELD 00w01 UE (rw): USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value.
0x40013800 C   FIELD 01w01 UESM (rw): USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 02w01 RE (rw): Receiver enable This bit enables the receiver. It is set and cleared by software.
0x40013800 C   FIELD 03w01 TE (rw): Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0' followed by '1') sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1'. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
0x40013800 C   FIELD 04w01 IDLEIE (rw): IDLE interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 05w01 RXNEIE (rw): RXFIFO not empty interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 06w01 TCIE (rw): Transmission complete interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 07w01 TXEIE (rw): TXFIFO not full interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 08w01 PEIE (rw): PE interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 09w01 PS (rw): Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE=0).
0x40013800 C   FIELD 10w01 PCE (rw): Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE=0).
0x40013800 C   FIELD 11w01 WAKE (rw): Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE=0).
0x40013800 C   FIELD 12w01 M0 (rw): Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE=0).
0x40013800 C   FIELD 13w01 MME (rw): Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0x40013800 C   FIELD 14w01 CMIE (rw): Character match interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 15w01 OVER8 (rw): Oversampling mode This bit can only be written when the USART is disabled (UE=0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
0x40013800 C   FIELD 16w05 DEDT (rw): Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 21w05 DEAT (rw): Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 26w01 RTOIE (rw): Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. .
0x40013800 C   FIELD 27w01 EOBIE (rw): End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013800 C   FIELD 28w01 M1 (rw): Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.
0x40013800 C   FIELD 29w01 FIFOEN (rw): FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
0x40013800 C   FIELD 30w01 TXFEIE (rw): TXFIFO empty interrupt enable This bit is set and cleared by software.
0x40013800 C   FIELD 31w01 RXFFIE (rw): RXFIFO Full interrupt enable This bit is set and cleared by software.
0x40013804 B  REGISTER CR2 (rw): Control register 2
0x40013804 C   FIELD 00w01 SLVEN (rw): Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 03w01 DIS_NSS (rw): When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 04w01 ADDM7 (rw): 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
0x40013804 C   FIELD 05w01 LBDL (rw): LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 06w01 LBDIE (rw): LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 08w01 LBCL (rw): Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 09w01 CPHA (rw): Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 10w01 CPOL (rw): Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 11w01 CLKEN (rw): Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UE=0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1
0x40013804 C   FIELD 12w02 STOP (rw): stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE=0).
0x40013804 C   FIELD 14w01 LINEN (rw): LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 15w01 SWAP (rw): Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0).
0x40013804 C   FIELD 16w01 RXINV (rw): RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE=0).
0x40013804 C   FIELD 17w01 TXINV (rw): TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE=0).
0x40013804 C   FIELD 18w01 DATAINV (rw): Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0).
0x40013804 C   FIELD 19w01 MSBFIRST (rw): Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0).
0x40013804 C   FIELD 20w01 ABREN (rw): Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 21w02 ABRMOD (rw): Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 23w01 RTOEN (rw): Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013804 C   FIELD 24w08 ADD (rw): Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0).
0x40013808 B  REGISTER CR3 (rw): Control register 3
0x40013808 C   FIELD 00w01 EIE (rw): Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NE=1 or UDR = 1 in the USART_ISR register).
0x40013808 C   FIELD 01w01 IREN (rw): IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 02w01 IRLP (rw): IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 03w01 HDSEL (rw): Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE=0).
0x40013808 C   FIELD 04w01 NACK (rw): Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 05w01 SCEN (rw): Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 06w01 DMAR (rw): DMA enable receiver This bit is set/reset by software
0x40013808 C   FIELD 07w01 DMAT (rw): DMA enable transmitter This bit is set/reset by software
0x40013808 C   FIELD 08w01 RTSE (rw): RTS enable This bit can only be written when the USART is disabled (UE=0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 09w01 CTSE (rw): CTS enable This bit can only be written when the USART is disabled (UE=0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 10w01 CTSIE (rw): CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 11w01 ONEBIT (rw): One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE=0).
0x40013808 C   FIELD 12w01 OVRDIS (rw): Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data
0x40013808 C   FIELD 13w01 DDRE (rw): DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
0x40013808 C   FIELD 14w01 DEM (rw): Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .
0x40013808 C   FIELD 15w01 DEP (rw): Driver enable polarity selection This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 17w03 SCARCNT (rw): Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE=0). When the USART is enabled (UE=1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 20w02 WUS (rw): Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE=0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page835.
0x40013808 C   FIELD 22w01 WUFIE (rw): Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page835.
0x40013808 C   FIELD 23w01 TXFTIE (rw): TXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40013808 C   FIELD 24w01 TCBGTIE (rw): Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013808 C   FIELD 25w03 RXFTCFG (rw): Receive FIFO threshold configuration Remaining combinations: Reserved
0x40013808 C   FIELD 28w01 RXFTIE (rw): RXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40013808 C   FIELD 29w03 TXFTCFG (rw): TXFIFO threshold configuration Remaining combinations: Reserved
0x4001380C B  REGISTER BRR (rw): Baud rate register
0x4001380C C   FIELD 00w16 BRR (rw): USART baud rate
0x40013810 B  REGISTER GTPR (rw): Guard time and prescaler register
0x40013810 C   FIELD 00w08 PSC (rw): Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]=Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 00100000: Divides the source clock by 32 (IrDA mode) ... 11111111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UE=0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0' when the Smartcard and IrDA modes are not supported. Refer to .
0x40013810 C   FIELD 08w08 GT (rw): Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE=0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013814 B  REGISTER RTOR (rw): Receiver timeout register
0x40013814 C   FIELD 00w24 RTO: Receiver timeout value
0x40013814 C   FIELD 24w08 BLEN: Block Length
0x40013818 B  REGISTER RQR (wo): Request register
0x40013818 C   FIELD 00w01 ABRRQ (wo): Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to .
0x40013818 C   FIELD 01w01 SBKRQ (wo): Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
0x40013818 C   FIELD 02w01 MMRQ (wo): Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
0x40013818 C   FIELD 03w01 RXFRQ (wo): Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition.
0x40013818 C   FIELD 04w01 TXFRQ (wo): Transmit data flush request When FIFO mode is disabled, writing '1' to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
0x4001381C B  REGISTER ISR (ro): Interrupt & status register
0x4001381C C   FIELD 00w01 PE (ro): Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4001381C C   FIELD 01w01 FE (ro): Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE=1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4001381C C   FIELD 02w01 NE (ro): Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page861). This error is associated with the character in the USART_RDR.
0x4001381C C   FIELD 03w01 ORE (ro): Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE=1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
0x4001381C C   FIELD 04w01 IDLE (ro): Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the Mute mode selected by the WAKE bit. If RWU=1, IDLE is not set.
0x4001381C C   FIELD 05w01 RXFNE (ro): RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE=1 in the USART_CR1 register.
0x4001381C C   FIELD 06w01 TC (ro): Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
0x4001381C C   FIELD 07w01 TXFNF (ro): TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.
0x4001381C C   FIELD 08w01 LBDF (ro): LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 09w01 CTSIF (ro): CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 10w01 CTS (ro): CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 11w01 RTOF (ro): Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE=1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 12w01 EOBF (ro): End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE=1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 13w01 UDR (ro): SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 14w01 ABRE (ro): Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 15w01 ABRF (ro): Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4001381C C   FIELD 16w01 BUSY (ro): Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
0x4001381C C   FIELD 17w01 CMF (ro): Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register.
0x4001381C C   FIELD 18w01 SBKF (ro): Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
0x4001381C C   FIELD 19w01 RWU (ro): Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 20w01 WUF (ro): Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE=1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 21w01 TEACK (ro): Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USART_CR1 register, in order to respect the TE=0 minimum period.
0x4001381C C   FIELD 22w01 REACK (ro): Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to .
0x4001381C C   FIELD 23w01 TXFE (ro): TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register.
0x4001381C C   FIELD 24w01 RXFF (ro): RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFOsize+1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register.
0x4001381C C   FIELD 25w01 TCBGT (ro): Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE=1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1'. Refer to on page835.
0x4001381C C   FIELD 26w01 RXFT (ro): RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101', RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
0x4001381C C   FIELD 27w01 TXFT (ro): TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register.
0x40013820 B  REGISTER ICR (wo): Interrupt flag clear register
0x40013820 C   FIELD 00w01 PECF (wo): Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
0x40013820 C   FIELD 01w01 FECF (wo): Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
0x40013820 C   FIELD 02w01 NECF (wo): Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
0x40013820 C   FIELD 03w01 ORECF (wo): Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
0x40013820 C   FIELD 04w01 IDLECF (wo): Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
0x40013820 C   FIELD 05w01 TXFECF (wo): TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
0x40013820 C   FIELD 06w01 TCCF (wo): Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
0x40013820 C   FIELD 07w01 TCBGTCF (wo): Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
0x40013820 C   FIELD 08w01 LBDCF (wo): LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013820 C   FIELD 09w01 CTSCF (wo): CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .
0x40013820 C   FIELD 11w01 RTOCF (wo): Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page835.
0x40013820 C   FIELD 12w01 EOBCF (wo): End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .
0x40013820 C   FIELD 13w01 UDRCF (wo): SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to
0x40013820 C   FIELD 17w01 CMCF (wo): Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
0x40013820 C   FIELD 20w01 WUCF (wo): Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page835.
0x40013824 B  REGISTER RDR (ro): Receive data register
0x40013824 C   FIELD 00w09 RDR: Receive data value
0x40013828 B  REGISTER TDR (rw): Transmit data register
0x40013828 C   FIELD 00w09 TDR: Transmit data value
0x4001382C B  REGISTER PRESC (rw): Prescaler register
0x4001382C C   FIELD 00w04 PRESCALER (rw): Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
0x40014000 A PERIPHERAL TIM15
0x40014000 B  REGISTER CR1 (rw): control register 1
0x40014000 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40014000 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40014000 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40014000 C   FIELD 03w01 OPM (rw): One-pulse mode
0x40014000 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40014000 C   FIELD 08w02 CKD (rw): Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx)
0x40014000 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40014004 B  REGISTER CR2 (rw): control register 2
0x40014004 C   FIELD 00w01 CCPC (rw): Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0x40014004 C   FIELD 02w01 CCUS (rw): Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
0x40014004 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40014004 C   FIELD 04w03 MMS (rw): Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
0x40014004 C   FIELD 07w01 TI1S (rw): TI1 selection
0x40014004 C   FIELD 08w01 OIS1 (rw): Output Idle state (OC1 output)
0x40014004 C   FIELD 09w01 OIS1N (rw): Output Idle state (OC1N output)
0x40014004 C   FIELD 10w01 OIS2 (rw): Output Idle state (OC2 output)
0x40014008 B  REGISTER SMCR (rw): slave mode control register
0x40014008 C   FIELD 00w03 SMS1 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS='00100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40014008 C   FIELD 04w03 TS1 (rw): Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40014008 C   FIELD 07w01 MSM (rw): Master/slave mode
0x40014008 C   FIELD 16w01 SMS2 (rw): Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS='00100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40014008 C   FIELD 20w02 TS2 (rw): Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x4001400C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4001400C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4001400C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4001400C C   FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x4001400C C   FIELD 05w01 COMIE (rw): COM interrupt enable
0x4001400C C   FIELD 06w01 TIE (rw): Trigger interrupt enable
0x4001400C C   FIELD 07w01 BIE (rw): Break interrupt enable
0x4001400C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4001400C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x4001400C C   FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x4001400C C   FIELD 13w01 COMDE (rw): COM DMA request enable
0x4001400C C   FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40014010 B  REGISTER SR (rw): status register
0x40014010 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40014010 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40014010 C   FIELD 02w01 CC2IF (rw): Capture/compare 2 interrupt flag
0x40014010 C   FIELD 05w01 COMIF (rw): COM interrupt flag
0x40014010 C   FIELD 06w01 TIF (rw): Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
0x40014010 C   FIELD 07w01 BIF (rw): Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0x40014010 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40014010 C   FIELD 10w01 CC2OF (rw): Capture/Compare 2 overcapture flag
0x40014014 B  REGISTER EGR (wo): event generation register
0x40014014 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40014014 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40014014 C   FIELD 02w01 CC2G (wo): Capture/compare 2 generation
0x40014014 C   FIELD 05w01 COMG (rw): Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
0x40014014 C   FIELD 06w01 TG (wo): Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40014014 C   FIELD 07w01 BG (wo): Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40014018 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40014018 B  REGISTER CCMR1_Output (rw): capture/compare mode register (output mode)
0x40014018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
0x40014018 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40014018 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40014018 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40014018 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40014018 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40014018 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40014018 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40014018 C   FIELD 08w02 CC2S (rw): Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER).
0x40014018 C   FIELD 10w01 OC2FE (rw): Output compare 2 fast enable
0x40014018 C   FIELD 10w02 IC2PSC (rw): Input capture 2 prescaler
0x40014018 C   FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40014018 C   FIELD 12w03 OC2M (rw): Output compare 2 mode
0x40014018 C   FIELD 12w04 IC2F (rw): Input capture 2 filter
0x40014018 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40014018 C   FIELD 24w01 OC2M_3 (rw): Output compare 2 mode, bit 3
0x40014020 B  REGISTER CCER (rw): capture/compare enable register
0x40014020 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40014020 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40014020 C   FIELD 02w01 CC1NE (rw): Capture/Compare 1 complementary output enable
0x40014020 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40014020 C   FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable
0x40014020 C   FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity
0x40014020 C   FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity
0x40014024 B  REGISTER CNT: counter
0x40014024 C   FIELD 00w16 CNT (rw): counter value
0x40014024 C   FIELD 31w01 UIFCPY (ro): UIF Copy
0x40014028 B  REGISTER PSC (rw): prescaler
0x40014028 C   FIELD 00w16 PSC: Prescaler value
0x4001402C B  REGISTER ARR (rw): auto-reload register
0x4001402C C   FIELD 00w16 ARR: Auto-reload value
0x40014030 B  REGISTER RCR (rw): repetition counter register
0x40014030 C   FIELD 00w08 REP: Repetition counter value
0x40014034 B  REGISTER CCR1 (rw): capture/compare register
0x40014034 C   FIELD 00w16 CCR: Capture/Compare value
0x40014038 B  REGISTER CCR2 (rw): capture/compare register
0x40014038 C   FIELD 00w16 CCR: Capture/Compare value
0x40014044 B  REGISTER BDTR (rw): break and dead-time register
0x40014044 C   FIELD 00w08 DTG (rw): Dead-time generator setup.
0x40014044 C   FIELD 08w02 LOCK (rw): Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
0x40014044 C   FIELD 10w01 OSSI (rw): Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014044 C   FIELD 11w01 OSSR (rw): Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014044 C   FIELD 12w01 BKE (rw): Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014044 C   FIELD 13w01 BKP (rw): Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014044 C   FIELD 14w01 AOE (rw): Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014044 C   FIELD 15w01 MOE (rw): Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page818).
0x40014044 C   FIELD 16w04 BKF (rw): Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014044 C   FIELD 26w01 BKDSRM (rw): Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014044 C   FIELD 28w01 BKBID (rw): Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014048 B  REGISTER DCR (rw): DMA control register
0x40014048 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
0x40014048 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
0x4001404C B  REGISTER DMAR (rw): DMA address for full transfer
0x4001404C C   FIELD 00w16 DMAB: DMA register for burst accesses
0x40014060 B  REGISTER AF1 (rw): TIM15 alternate register 1
0x40014060 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014060 C   FIELD 01w01 BKCMP1E (rw): BRK COMP1 enable This bit enables the COMP1 for the timer's BRK input. COMP1 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014060 C   FIELD 02w01 BKCMP2E (rw): BRK COMP2 enable This bit enables the COMP2 for the timer's BRK input. COMP2 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014060 C   FIELD 03w01 BKCMP3E (rw): BRK COMP3 enable This bit enables the COMP3 for the timer's BRK input. COMP3 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014060 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014060 C   FIELD 10w01 BKCMP1P (rw): BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014060 C   FIELD 11w01 BKCMP2P (rw): BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014060 C   FIELD 12w01 BKCMP3P (rw): BRK COMP3 input polarity This bit selects the COMP3 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014068 B  REGISTER TISEL (rw): input selection register
0x40014068 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40014068 C   FIELD 08w04 TI2SEL (rw): selects TI2[0] to TI2[15] input Others: Reserved
0x40014400 A PERIPHERAL TIM16
0x40014400 B  REGISTER CR1 (rw): control register 1
0x40014400 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40014400 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40014400 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40014400 C   FIELD 03w01 OPM (rw): One pulse mode
0x40014400 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40014400 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),
0x40014400 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40014404 B  REGISTER CR2 (rw): control register 2
0x40014404 C   FIELD 00w01 CCPC (rw): Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0x40014404 C   FIELD 02w01 CCUS (rw): Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
0x40014404 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40014404 C   FIELD 08w01 OIS1 (rw): Output Idle state (OC1 output)
0x40014404 C   FIELD 09w01 OIS1N (rw): Output Idle state (OC1N output)
0x4001440C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4001440C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4001440C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4001440C C   FIELD 05w01 COMIE (rw): COM interrupt enable
0x4001440C C   FIELD 07w01 BIE (rw): Break interrupt enable
0x4001440C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4001440C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x40014410 B  REGISTER SR (rw): status register
0x40014410 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40014410 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40014410 C   FIELD 05w01 COMIF (rw): COM interrupt flag
0x40014410 C   FIELD 07w01 BIF (rw): Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0x40014410 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40014414 B  REGISTER EGR (wo): event generation register
0x40014414 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40014414 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40014414 C   FIELD 05w01 COMG (wo): Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
0x40014414 C   FIELD 07w01 BG (wo): Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40014418 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40014418 B  REGISTER CCMR1_Output (rw): capture/compare mode register (output mode)
0x40014418 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
0x40014418 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40014418 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40014418 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40014418 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40014418 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40014418 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40014418 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40014420 B  REGISTER CCER (rw): capture/compare enable register
0x40014420 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40014420 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40014420 C   FIELD 02w01 CC1NE (rw): Capture/Compare 1 complementary output enable
0x40014420 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40014424 B  REGISTER CNT: counter
0x40014424 C   FIELD 00w16 CNT (rw): counter value
0x40014424 C   FIELD 31w01 UIFCPY (ro): UIF Copy
0x40014428 B  REGISTER PSC (rw): prescaler
0x40014428 C   FIELD 00w16 PSC: Prescaler value
0x4001442C B  REGISTER ARR (rw): auto-reload register
0x4001442C C   FIELD 00w16 ARR: Auto-reload value
0x40014430 B  REGISTER RCR (rw): repetition counter register
0x40014430 C   FIELD 00w08 REP: Repetition counter value
0x40014434 B  REGISTER CCR1 (rw): capture/compare register
0x40014434 C   FIELD 00w16 CCR: Capture/Compare value
0x40014444 B  REGISTER BDTR (rw): break and dead-time register
0x40014444 C   FIELD 00w08 DTG (rw): Dead-time generator setup
0x40014444 C   FIELD 08w02 LOCK (rw): Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
0x40014444 C   FIELD 10w01 OSSI (rw): Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 11w01 OSSR (rw): Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 12w01 BKE (rw): Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014444 C   FIELD 13w01 BKP (rw): Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014444 C   FIELD 14w01 AOE (rw): Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 15w01 MOE (rw): Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846).
0x40014444 C   FIELD 16w04 BKF (rw): Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014444 C   FIELD 26w01 BKDSRM (rw): Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014444 C   FIELD 28w01 BKBID (rw): Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014448 B  REGISTER DCR (rw): DMA control register
0x40014448 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0x40014448 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ...
0x4001444C B  REGISTER DMAR (rw): DMA address for full transfer
0x4001444C C   FIELD 00w16 DMAB: DMA register for burst accesses
0x40014460 B  REGISTER AF1 (rw): TIM17 option register 1
0x40014460 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014460 C   FIELD 01w01 BKCMP1E (rw): BRK COMP1 enable This bit enables the COMP1 for the timer's BRK input. COMP1 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014460 C   FIELD 02w01 BKCMP2E (rw): BRK COMP2 enable This bit enables the COMP2 for the timer's BRK input. COMP2 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014460 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014460 C   FIELD 10w01 BKCMP1P (rw): BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014460 C   FIELD 11w01 BKCMP2P (rw): BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014468 B  REGISTER TISEL (rw): input selection register
0x40014468 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40014800 A PERIPHERAL TIM17
0x40014800 B  REGISTER CR1 (rw): control register 1
0x40014800 C   FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40014800 C   FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40014800 C   FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40014800 C   FIELD 03w01 OPM (rw): One pulse mode
0x40014800 C   FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40014800 C   FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),
0x40014800 C   FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40014804 B  REGISTER CR2 (rw): control register 2
0x40014804 C   FIELD 00w01 CCPC (rw): Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
0x40014804 C   FIELD 02w01 CCUS (rw): Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
0x40014804 C   FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40014804 C   FIELD 08w01 OIS1 (rw): Output Idle state (OC1 output)
0x40014804 C   FIELD 09w01 OIS1N (rw): Output Idle state (OC1N output)
0x4001480C B  REGISTER DIER (rw): DMA/Interrupt enable register
0x4001480C C   FIELD 00w01 UIE (rw): Update interrupt enable
0x4001480C C   FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4001480C C   FIELD 05w01 COMIE (rw): COM interrupt enable
0x4001480C C   FIELD 07w01 BIE (rw): Break interrupt enable
0x4001480C C   FIELD 08w01 UDE (rw): Update DMA request enable
0x4001480C C   FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x40014810 B  REGISTER SR (rw): status register
0x40014810 C   FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40014810 C   FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40014810 C   FIELD 05w01 COMIF (rw): COM interrupt flag
0x40014810 C   FIELD 07w01 BIF (rw): Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0x40014810 C   FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40014814 B  REGISTER EGR (wo): event generation register
0x40014814 C   FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40014814 C   FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40014814 C   FIELD 05w01 COMG (wo): Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
0x40014814 C   FIELD 07w01 BG (wo): Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40014818 B  REGISTER CCMR1_Input (rw): capture/compare mode register 1 (input mode)
0x40014818 B  REGISTER CCMR1_Output (rw): capture/compare mode register (output mode)
0x40014818 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
0x40014818 C   FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40014818 C   FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40014818 C   FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40014818 C   FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40014818 C   FIELD 04w03 OC1M (rw): Output compare 1 mode
0x40014818 C   FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40014818 C   FIELD 16w01 OC1M_3 (rw): Output compare 1 mode, bit 3
0x40014820 B  REGISTER CCER (rw): capture/compare enable register
0x40014820 C   FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable
0x40014820 C   FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity
0x40014820 C   FIELD 02w01 CC1NE (rw): Capture/Compare 1 complementary output enable
0x40014820 C   FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity
0x40014824 B  REGISTER CNT: counter
0x40014824 C   FIELD 00w16 CNT (rw): counter value
0x40014824 C   FIELD 31w01 UIFCPY (ro): UIF Copy
0x40014828 B  REGISTER PSC (rw): prescaler
0x40014828 C   FIELD 00w16 PSC: Prescaler value
0x4001482C B  REGISTER ARR (rw): auto-reload register
0x4001482C C   FIELD 00w16 ARR: Auto-reload value
0x40014830 B  REGISTER RCR (rw): repetition counter register
0x40014830 C   FIELD 00w08 REP: Repetition counter value
0x40014834 B  REGISTER CCR1 (rw): capture/compare register
0x40014834 C   FIELD 00w16 CCR: Capture/Compare value
0x40014844 B  REGISTER BDTR (rw): break and dead-time register
0x40014844 C   FIELD 00w08 DTG (rw): Dead-time generator setup
0x40014844 C   FIELD 08w02 LOCK (rw): Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
0x40014844 C   FIELD 10w01 OSSI (rw): Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014844 C   FIELD 11w01 OSSR (rw): Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014844 C   FIELD 12w01 BKE (rw): Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014844 C   FIELD 13w01 BKP (rw): Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014844 C   FIELD 14w01 AOE (rw): Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014844 C   FIELD 15w01 MOE (rw): Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846).
0x40014844 C   FIELD 16w04 BKF (rw): Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014844 C   FIELD 26w01 BKDSRM (rw): Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014844 C   FIELD 28w01 BKBID (rw): Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
0x40014848 B  REGISTER DCR (rw): DMA control register
0x40014848 C   FIELD 00w05 DBA (rw): DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0x40014848 C   FIELD 08w05 DBL (rw): DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ...
0x4001484C B  REGISTER DMAR (rw): DMA address for full transfer
0x4001484C C   FIELD 00w16 DMAB: DMA register for burst accesses
0x40014860 B  REGISTER AF1 (rw): TIM17 option register 1
0x40014860 C   FIELD 00w01 BKINE (rw): BRK BKIN input enable This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014860 C   FIELD 01w01 BKCMP1E (rw): BRK COMP1 enable This bit enables the COMP1 for the timer's BRK input. COMP1 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014860 C   FIELD 02w01 BKCMP2E (rw): BRK COMP2 enable This bit enables the COMP2 for the timer's BRK input. COMP2 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014860 C   FIELD 09w01 BKINP (rw): BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014860 C   FIELD 10w01 BKCMP1P (rw): BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014860 C   FIELD 11w01 BKCMP2P (rw): BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
0x40014868 B  REGISTER TISEL (rw): input selection register
0x40014868 C   FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40015800 A PERIPHERAL DBG
0x40015800 B  REGISTER IDCODE (ro): MCU Device ID Code Register
0x40015800 C   FIELD 00w12 DEV_ID: Device Identifier
0x40015800 C   FIELD 16w16 REV_ID: Revision Identifier
0x40015804 B  REGISTER CR (rw): DBG configuration register
0x40015804 C   FIELD 01w01 DBG_STOP (rw): Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration.
0x40015804 C   FIELD 02w01 DBG_STANDBY (rw): Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode.
0x40015808 B  REGISTER APB_FZ1 (rw): DBG APB freeze register 1
0x40015808 C   FIELD 00w01 DBG_TIM2_STOP (rw): Clocking of TIM2 counter when the core is halted This bit enables/disables the clock to the counter of TIM2 when the core is halted:
0x40015808 C   FIELD 01w01 DBG_TIM3_STOP (rw): Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:
0x40015808 C   FIELD 04w01 DBG_TIM6_STOP (rw): Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted:
0x40015808 C   FIELD 05w01 DBG_TIM7_STOP (rw): Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted:
0x40015808 C   FIELD 10w01 DBG_RTC_STOP (rw): Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:
0x40015808 C   FIELD 11w01 DBG_WWDG_STOP (rw): Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:
0x40015808 C   FIELD 12w01 DBG_IWDG_STOP (rw): Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:
0x40015808 C   FIELD 21w01 DBG_I2C1_SMBUS_TIMEOUT (rw): SMBUS timeout when core is halted
0x40015808 C   FIELD 30w01 DBG_LPTIM2_STOP (rw): Clocking of LPTIMER2 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted:
0x40015808 C   FIELD 31w01 DBG_LPTIM1_STOP (rw): Clocking of LPTIMER1 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted:
0x4001580C B  REGISTER APB_FZ2 (rw): DBG APB freeze register 2
0x4001580C C   FIELD 11w01 DBG_TIM1_STOP (rw): Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:
0x4001580C C   FIELD 15w01 DBG_TIM14_STOP (rw): Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:
0x4001580C C   FIELD 16w01 DBG_TIM15_STOP (rw): Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx.
0x4001580C C   FIELD 17w01 DBG_TIM16_STOP (rw): Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:
0x4001580C C   FIELD 18w01 DBG_TIM17_STOP (rw): Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:
0x40020000 A PERIPHERAL DMA1
0x40020000 B  REGISTER ISR: DMA interrupt status register
0x40020000 C   FIELD 00w01 GIF1 (ro): Channel 1 Global interrupt flag
0x40020000 C   FIELD 01w01 TCIF1 (ro): Channel 1 Transfer Complete flag
0x40020000 C   FIELD 02w01 HTIF1 (ro): Channel 1 Half Transfer Complete flag
0x40020000 C   FIELD 03w01 TEIF1 (ro): Channel 1 Transfer Error flag
0x40020000 C   FIELD 04w01 GIF2 (ro): Channel 2 Global interrupt flag
0x40020000 C   FIELD 05w01 TCIF2 (ro): Channel 2 Transfer Complete flag
0x40020000 C   FIELD 06w01 HTIF2 (ro): Channel 2 Half Transfer Complete flag
0x40020000 C   FIELD 07w01 TEIF2 (ro): Channel 2 Transfer Error flag
0x40020000 C   FIELD 08w01 GIF3 (ro): Channel 3 Global interrupt flag
0x40020000 C   FIELD 09w01 TCIF3 (ro): Channel 3 Transfer Complete flag
0x40020000 C   FIELD 10w01 HTIF3 (ro): Channel 3 Half Transfer Complete flag
0x40020000 C   FIELD 11w01 TEIF3 (ro): Channel 3 Transfer Error flag
0x40020000 C   FIELD 12w01 GIF4 (ro): Channel 4 Global interrupt flag
0x40020000 C   FIELD 13w01 TCIF4 (ro): Channel 4 Transfer Complete flag
0x40020000 C   FIELD 14w01 HTIF4 (ro): Channel 4 Half Transfer Complete flag
0x40020000 C   FIELD 15w01 TEIF4 (ro): Channel 4 Transfer Error flag
0x40020000 C   FIELD 16w01 GIF5 (ro): Channel 5 Global interrupt flag
0x40020000 C   FIELD 17w01 TCIF5 (ro): Channel 5 Transfer Complete flag
0x40020000 C   FIELD 18w01 HTIF5 (ro): Channel 5 Half Transfer Complete flag
0x40020000 C   FIELD 19w01 TEIF5 (ro): Channel 5 Transfer Error flag
0x40020000 C   FIELD 20w01 GIF6 (ro): Channel 6 Global interrupt flag
0x40020000 C   FIELD 21w01 TCIF6 (ro): Channel 6 Transfer Complete flag
0x40020000 C   FIELD 22w01 HTIF6 (ro): Channel 6 Half Transfer Complete flag
0x40020000 C   FIELD 23w01 TEIF6 (ro): Channel 6 Transfer Error flag
0x40020000 C   FIELD 24w01 GIF7 (ro): Channel 7 Global interrupt flag
0x40020000 C   FIELD 25w01 TCIF7 (ro): Channel 7 Transfer Complete flag
0x40020000 C   FIELD 26w01 HTIF7 (ro): Channel 7 Half Transfer Complete flag
0x40020000 C   FIELD 27w01 TEIF7 (ro): Channel 7 Transfer Error flag
0x40020004 B  REGISTER IFCR: DMA interrupt flag clear register
0x40020004 C   FIELD 00w01 CGIF1 (wo): Channel 1 Global interrupt clear
0x40020004 C   FIELD 01w01 CTCIF1 (wo): Channel 1 Transfer Complete clear
0x40020004 C   FIELD 02w01 CHTIF1 (wo): Channel 1 Half Transfer clear
0x40020004 C   FIELD 03w01 CTEIF1 (wo): Channel 1 Transfer Error clear
0x40020004 C   FIELD 04w01 CGIF2 (wo): Channel 2 Global interrupt clear
0x40020004 C   FIELD 05w01 CTCIF2 (wo): Channel 2 Transfer Complete clear
0x40020004 C   FIELD 06w01 CHTIF2 (wo): Channel 2 Half Transfer clear
0x40020004 C   FIELD 07w01 CTEIF2 (wo): Channel 2 Transfer Error clear
0x40020004 C   FIELD 08w01 CGIF3 (wo): Channel 3 Global interrupt clear
0x40020004 C   FIELD 09w01 CTCIF3 (wo): Channel 3 Transfer Complete clear
0x40020004 C   FIELD 10w01 CHTIF3 (wo): Channel 3 Half Transfer clear
0x40020004 C   FIELD 11w01 CTEIF3 (wo): Channel 3 Transfer Error clear
0x40020004 C   FIELD 12w01 CGIF4 (wo): Channel 4 Global interrupt clear
0x40020004 C   FIELD 13w01 CTCIF4 (wo): Channel 4 Transfer Complete clear
0x40020004 C   FIELD 14w01 CHTIF4 (wo): Channel 4 Half Transfer clear
0x40020004 C   FIELD 15w01 CTEIF4 (wo): Channel 4 Transfer Error clear
0x40020004 C   FIELD 16w01 CGIF5 (wo): Channel 5 Global interrupt clear
0x40020004 C   FIELD 17w01 CTCIF5 (wo): Channel 5 Transfer Complete clear
0x40020004 C   FIELD 18w01 CHTIF5 (wo): Channel 5 Half Transfer clear
0x40020004 C   FIELD 19w01 CTEIF5 (wo): Channel 5 Transfer Error clear
0x40020004 C   FIELD 20w01 CGIF6 (wo): Channel 6 Global interrupt clear
0x40020004 C   FIELD 21w01 CTCIF6 (wo): Channel 6 Transfer Complete clear
0x40020004 C   FIELD 22w01 CHTIF6 (wo): Channel 6 Half Transfer clear
0x40020004 C   FIELD 23w01 CTEIF6 (wo): Channel 6 Transfer Error clear
0x40020004 C   FIELD 24w01 CGIF7 (wo): Channel 7 Global interrupt clear
0x40020004 C   FIELD 25w01 CTCIF7 (wo): Channel 7 Transfer Complete clear
0x40020004 C   FIELD 26w01 CHTIF7 (wo): Channel 7 Half Transfer clear
0x40020004 C   FIELD 27w01 CTEIF7 (wo): Channel 7 Transfer Error clear
0x40020008 B  CLUSTER CH1: Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x40020008 B  REGISTER CR1: DMA channel 1 configuration register
0x40020008 C   FIELD 00w01 EN (rw): channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
0x40020008 C   FIELD 01w01 TCIE (rw): transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020008 C   FIELD 02w01 HTIE (rw): half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020008 C   FIELD 03w01 TEIE (rw): transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020008 C   FIELD 04w01 DIR (rw): data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020008 C   FIELD 05w01 CIRC (rw): circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020008 C   FIELD 06w01 PINC (rw): peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020008 C   FIELD 07w01 MINC (rw): memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020008 C   FIELD 08w02 PSIZE (rw): peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020008 C   FIELD 10w02 MSIZE (rw): memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020008 C   FIELD 12w02 PL (rw): priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020008 C   FIELD 14w01 MEM2MEM (rw): memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002000C B  REGISTER NDTR1: DMA channel x number of data register
0x4002000C C   FIELD 00w16 NDT (rw): number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020010 B  REGISTER PAR1: DMA channel x peripheral address register
0x40020010 C   FIELD 00w32 PA (rw): peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020014 B  REGISTER MAR1: DMA channel x memory address register
0x40020014 C   FIELD 00w32 MA (rw): peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002001C B  CLUSTER CH2: Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x4002001C B  REGISTER CR2: DMA channel 1 configuration register
0x4002001C C   FIELD 00w01 EN (rw): channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
0x4002001C C   FIELD 01w01 TCIE (rw): transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002001C C   FIELD 02w01 HTIE (rw): half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002001C C   FIELD 03w01 TEIE (rw): transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002001C C   FIELD 04w01 DIR (rw): data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002001C C   FIELD 05w01 CIRC (rw): circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002001C C   FIELD 06w01 PINC (rw): peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002001C C   FIELD 07w01 MINC (rw): memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002001C C   FIELD 08w02 PSIZE (rw): peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002001C C   FIELD 10w02 MSIZE (rw): memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002001C C   FIELD 12w02 PL (rw): priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002001C C   FIELD 14w01 MEM2MEM (rw): memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020020 B  REGISTER NDTR2: DMA channel x number of data register
0x40020020 C   FIELD 00w16 NDT (rw): number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020024 B  REGISTER PAR2: DMA channel x peripheral address register
0x40020024 C   FIELD 00w32 PA (rw): peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020028 B  REGISTER MAR2: DMA channel x memory address register
0x40020028 C   FIELD 00w32 MA (rw): peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020030 B  CLUSTER CH3: Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x40020030 B  REGISTER CR3: DMA channel 1 configuration register
0x40020030 C   FIELD 00w01 EN (rw): channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
0x40020030 C   FIELD 01w01 TCIE (rw): transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020030 C   FIELD 02w01 HTIE (rw): half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020030 C   FIELD 03w01 TEIE (rw): transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020030 C   FIELD 04w01 DIR (rw): data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020030 C   FIELD 05w01 CIRC (rw): circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020030 C   FIELD 06w01 PINC (rw): peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020030 C   FIELD 07w01 MINC (rw): memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020030 C   FIELD 08w02 PSIZE (rw): peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020030 C   FIELD 10w02 MSIZE (rw): memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020030 C   FIELD 12w02 PL (rw): priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020030 C   FIELD 14w01 MEM2MEM (rw): memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020034 B  REGISTER NDTR3: DMA channel x number of data register
0x40020034 C   FIELD 00w16 NDT (rw): number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020038 B  REGISTER PAR3: DMA channel x peripheral address register
0x40020038 C   FIELD 00w32 PA (rw): peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002003C B  REGISTER MAR3: DMA channel x memory address register
0x4002003C C   FIELD 00w32 MA (rw): peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020044 B  CLUSTER CH4: Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x40020044 B  REGISTER CR4: DMA channel 1 configuration register
0x40020044 C   FIELD 00w01 EN (rw): channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
0x40020044 C   FIELD 01w01 TCIE (rw): transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020044 C   FIELD 02w01 HTIE (rw): half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020044 C   FIELD 03w01 TEIE (rw): transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020044 C   FIELD 04w01 DIR (rw): data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020044 C   FIELD 05w01 CIRC (rw): circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020044 C   FIELD 06w01 PINC (rw): peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020044 C   FIELD 07w01 MINC (rw): memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020044 C   FIELD 08w02 PSIZE (rw): peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020044 C   FIELD 10w02 MSIZE (rw): memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020044 C   FIELD 12w02 PL (rw): priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020044 C   FIELD 14w01 MEM2MEM (rw): memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020048 B  REGISTER NDTR4: DMA channel x number of data register
0x40020048 C   FIELD 00w16 NDT (rw): number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002004C B  REGISTER PAR4: DMA channel x peripheral address register
0x4002004C C   FIELD 00w32 PA (rw): peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020050 B  REGISTER MAR4: DMA channel x memory address register
0x40020050 C   FIELD 00w32 MA (rw): peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020058 B  CLUSTER CH5: Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x40020058 B  REGISTER CR5: DMA channel 1 configuration register
0x40020058 C   FIELD 00w01 EN (rw): channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
0x40020058 C   FIELD 01w01 TCIE (rw): transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020058 C   FIELD 02w01 HTIE (rw): half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020058 C   FIELD 03w01 TEIE (rw): transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020058 C   FIELD 04w01 DIR (rw): data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020058 C   FIELD 05w01 CIRC (rw): circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020058 C   FIELD 06w01 PINC (rw): peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020058 C   FIELD 07w01 MINC (rw): memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020058 C   FIELD 08w02 PSIZE (rw): peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020058 C   FIELD 10w02 MSIZE (rw): memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020058 C   FIELD 12w02 PL (rw): priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020058 C   FIELD 14w01 MEM2MEM (rw): memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002005C B  REGISTER NDTR5: DMA channel x number of data register
0x4002005C C   FIELD 00w16 NDT (rw): number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020060 B  REGISTER PAR5: DMA channel x peripheral address register
0x40020060 C   FIELD 00w32 PA (rw): peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020064 B  REGISTER MAR5: DMA channel x memory address register
0x40020064 C   FIELD 00w32 MA (rw): peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002006C B  CLUSTER CH6: Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x4002006C B  REGISTER CR6: DMA channel 1 configuration register
0x4002006C C   FIELD 00w01 EN (rw): channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
0x4002006C C   FIELD 01w01 TCIE (rw): transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002006C C   FIELD 02w01 HTIE (rw): half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002006C C   FIELD 03w01 TEIE (rw): transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002006C C   FIELD 04w01 DIR (rw): data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002006C C   FIELD 05w01 CIRC (rw): circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002006C C   FIELD 06w01 PINC (rw): peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002006C C   FIELD 07w01 MINC (rw): memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002006C C   FIELD 08w02 PSIZE (rw): peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002006C C   FIELD 10w02 MSIZE (rw): memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002006C C   FIELD 12w02 PL (rw): priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x4002006C C   FIELD 14w01 MEM2MEM (rw): memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020070 B  REGISTER NDTR6: DMA channel x number of data register
0x40020070 C   FIELD 00w16 NDT (rw): number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020074 B  REGISTER PAR6: DMA channel x peripheral address register
0x40020074 C   FIELD 00w32 PA (rw): peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020078 B  REGISTER MAR6: DMA channel x memory address register
0x40020078 C   FIELD 00w32 MA (rw): peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020080 B  CLUSTER CH7: Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
0x40020080 B  REGISTER CR7: DMA channel 1 configuration register
0x40020080 C   FIELD 00w01 EN (rw): channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
0x40020080 C   FIELD 01w01 TCIE (rw): transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020080 C   FIELD 02w01 HTIE (rw): half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020080 C   FIELD 03w01 TEIE (rw): transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020080 C   FIELD 04w01 DIR (rw): data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020080 C   FIELD 05w01 CIRC (rw): circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020080 C   FIELD 06w01 PINC (rw): peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020080 C   FIELD 07w01 MINC (rw): memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020080 C   FIELD 08w02 PSIZE (rw): peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020080 C   FIELD 10w02 MSIZE (rw): memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020080 C   FIELD 12w02 PL (rw): priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020080 C   FIELD 14w01 MEM2MEM (rw): memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020084 B  REGISTER NDTR7: DMA channel x number of data register
0x40020084 C   FIELD 00w16 NDT (rw): number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
0x40020088 B  REGISTER PAR7: DMA channel x peripheral address register
0x40020088 C   FIELD 00w32 PA (rw): peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x4002008C B  REGISTER MAR7: DMA channel x memory address register
0x4002008C C   FIELD 00w32 MA (rw): peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
0x40020800 A PERIPHERAL DMAMUX
0x40020800 B  REGISTER CCR0 (rw): DMA Multiplexer Channel 0 Control register
0x40020800 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020800 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020800 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020800 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020800 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020800 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020800 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020804 B  REGISTER CCR1 (rw): DMA Multiplexer Channel 1 Control register
0x40020804 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020804 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020804 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020804 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020804 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020804 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020804 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020808 B  REGISTER CCR2 (rw): DMA Multiplexer Channel 2 Control register
0x40020808 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020808 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020808 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020808 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020808 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020808 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020808 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x4002080C B  REGISTER CCR3 (rw): DMA Multiplexer Channel 3 Control register
0x4002080C C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x4002080C C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x4002080C C   FIELD 09w01 EGE (rw): Event generation enable
0x4002080C C   FIELD 16w01 SE (rw): Synchronization enable
0x4002080C C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x4002080C C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x4002080C C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020810 B  REGISTER CCR4 (rw): DMA Multiplexer Channel 4 Control register
0x40020810 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020810 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020810 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020810 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020810 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020810 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020810 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020814 B  REGISTER CCR5 (rw): DMA Multiplexer Channel 5 Control register
0x40020814 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020814 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020814 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020814 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020814 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020814 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020814 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020818 B  REGISTER CCR6 (rw): DMA Multiplexer Channel 6 Control register
0x40020818 C   FIELD 00w06 DMAREQ_ID (rw): DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
0x40020818 C   FIELD 08w01 SOIE (rw): Synchronization overrun interrupt enable
0x40020818 C   FIELD 09w01 EGE (rw): Event generation enable
0x40020818 C   FIELD 16w01 SE (rw): Synchronization enable
0x40020818 C   FIELD 17w02 SPOL (rw): Synchronization polarity Defines the edge polarity of the selected synchronization input:
0x40020818 C   FIELD 19w05 NBREQ (rw): Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.
0x40020818 C   FIELD 24w05 SYNC_ID (rw): Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).
0x40020880 B  REGISTER CSR (ro): DMAMUX request line multiplexer interrupt channel status register
0x40020880 C   FIELD 00w01 SOF0 (ro): Synchronization Overrun Flag 0
0x40020880 C   FIELD 01w01 SOF1 (ro): Synchronization Overrun Flag 1
0x40020880 C   FIELD 02w01 SOF2 (ro): Synchronization Overrun Flag 2
0x40020880 C   FIELD 03w01 SOF3 (ro): Synchronization Overrun Flag 3
0x40020880 C   FIELD 04w01 SOF4 (ro): Synchronization Overrun Flag 4
0x40020880 C   FIELD 05w01 SOF5 (ro): Synchronization Overrun Flag 5
0x40020880 C   FIELD 06w01 SOF6 (ro): Synchronization Overrun Flag 6
0x40020884 B  REGISTER CFR (wo): DMAMUX request line multiplexer interrupt clear flag register
0x40020884 C   FIELD 00w01 CSOF0 (wo): Synchronization Clear Overrun Flag 0
0x40020884 C   FIELD 01w01 CSOF1 (wo): Synchronization Clear Overrun Flag 1
0x40020884 C   FIELD 02w01 CSOF2 (wo): Synchronization Clear Overrun Flag 2
0x40020884 C   FIELD 03w01 CSOF3 (wo): Synchronization Clear Overrun Flag 3
0x40020884 C   FIELD 04w01 CSOF4 (wo): Synchronization Clear Overrun Flag 4
0x40020884 C   FIELD 05w01 CSOF5 (wo): Synchronization Clear Overrun Flag 5
0x40020884 C   FIELD 06w01 CSOF6 (wo): Synchronization Clear Overrun Flag 6
0x40020900 B  REGISTER RGCR0 (rw): DMAMUX request generator channel x configuration register
0x40020900 C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x40020900 C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x40020900 C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x40020900 C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x40020900 C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
0x40020904 B  REGISTER RGCR1 (rw): DMAMUX request generator channel x configuration register
0x40020904 C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x40020904 C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x40020904 C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x40020904 C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x40020904 C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
0x40020908 B  REGISTER RGCR2 (rw): DMAMUX request generator channel x configuration register
0x40020908 C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x40020908 C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x40020908 C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x40020908 C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x40020908 C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
0x4002090C B  REGISTER RGCR3 (rw): DMAMUX request generator channel x configuration register
0x4002090C C   FIELD 00w05 SIG_ID (rw): Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator
0x4002090C C   FIELD 08w01 OIE (rw): Trigger overrun interrupt enable
0x4002090C C   FIELD 16w01 GE (rw): DMA request generator channel x enable
0x4002090C C   FIELD 17w02 GPOL (rw): DMA request generator trigger polarity Defines the edge polarity of the selected trigger input
0x4002090C C   FIELD 19w05 GNBREQ (rw): Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled.
0x40020940 B  REGISTER RGSR (ro): DMAMUX request generator interrupt status register
0x40020940 C   FIELD 00w01 OF0 (ro): Generator Overrun Flag 0
0x40020940 C   FIELD 01w01 OF1 (ro): Generator Overrun Flag 1
0x40020940 C   FIELD 02w01 OF2 (ro): Generator Overrun Flag 2
0x40020940 C   FIELD 03w01 OF3 (ro): Generator Overrun Flag 3
0x40020944 B  REGISTER RGCFR (wo): DMAMUX request generator interrupt clear flag register
0x40020944 C   FIELD 00w01 COF0 (wo): Generator Clear Overrun Flag 0
0x40020944 C   FIELD 01w01 COF1 (wo): Generator Clear Overrun Flag 1
0x40020944 C   FIELD 02w01 COF2 (wo): Generator Clear Overrun Flag 2
0x40020944 C   FIELD 03w01 COF3 (wo): Generator Clear Overrun Flag 3
0x40021000 A PERIPHERAL RCC
0x40021000 B  REGISTER CR (rw): Clock control register
0x40021000 C   FIELD 08w01 HSION: HSI16 clock enable
0x40021000 C   FIELD 09w01 HSIKERON: HSI16 always enable for peripheral kernels
0x40021000 C   FIELD 10w01 HSIRDY: HSI16 clock ready flag
0x40021000 C   FIELD 11w03 HSIDIV: HSI16 clock division factor
0x40021000 C   FIELD 16w01 HSEON: HSE clock enable
0x40021000 C   FIELD 17w01 HSERDY: HSE clock ready flag
0x40021000 C   FIELD 18w01 HSEBYP: HSE crystal oscillator bypass
0x40021000 C   FIELD 19w01 CSSON: Clock security system enable
0x40021000 C   FIELD 24w01 PLLON: PLL enable
0x40021000 C   FIELD 25w01 PLLRDY: PLL clock ready flag
0x40021004 B  REGISTER ICSCR: Internal clock sources calibration register
0x40021004 C   FIELD 00w08 HSICAL (ro): HSI16 clock calibration
0x40021004 C   FIELD 08w07 HSITRIM (rw): HSI16 clock trimming
0x40021008 B  REGISTER CFGR: Clock configuration register
0x40021008 C   FIELD 00w03 SW (rw): System clock switch
0x40021008 C   FIELD 03w03 SWS (ro): System clock switch status
0x40021008 C   FIELD 08w04 HPRE (rw): AHB prescaler
0x40021008 C   FIELD 12w03 PPRE (rw): APB prescaler
0x40021008 C   FIELD 24w03 MCOSEL (rw): Microcontroller clock output
0x40021008 C   FIELD 28w03 MCOPRE (ro): Microcontroller clock output prescaler
0x4002100C B  REGISTER PLLCFGR (rw): PLL configuration register
0x4002100C C   FIELD 00w02 PLLSRC: PLL input clock source
0x4002100C C   FIELD 04w03 PLLM: Division factor M of the PLL input clock divider
0x4002100C C   FIELD 08w07 PLLN: PLL frequency multiplication factor N
0x4002100C C   FIELD 16w01 PLLPEN: PLLPCLK clock output enable
0x4002100C C   FIELD 17w05 PLLP: PLL VCO division factor P for PLLPCLK clock output
0x4002100C C   FIELD 24w01 PLLQEN: PLLQCLK clock output enable
0x4002100C C   FIELD 25w03 PLLQ: PLL VCO division factor Q for PLLQCLK clock output
0x4002100C C   FIELD 28w01 PLLREN: PLLRCLK clock output enable
0x4002100C C   FIELD 29w03 PLLR: PLL VCO division factor R for PLLRCLK clock output
0x40021018 B  REGISTER CIER (rw): Clock interrupt enable register
0x40021018 C   FIELD 00w01 LSIRDYIE: LSI ready interrupt enable
0x40021018 C   FIELD 01w01 LSERDYIE: LSE ready interrupt enable
0x40021018 C   FIELD 03w01 HSIRDYIE: HSI ready interrupt enable
0x40021018 C   FIELD 04w01 HSERDYIE: HSE ready interrupt enable
0x40021018 C   FIELD 05w01 PLLSYSRDYIE: PLL ready interrupt enable
0x4002101C B  REGISTER CIFR (ro): Clock interrupt flag register
0x4002101C C   FIELD 00w01 LSIRDYF: LSI ready interrupt flag
0x4002101C C   FIELD 01w01 LSERDYF: LSE ready interrupt flag
0x4002101C C   FIELD 03w01 HSIRDYF: HSI ready interrupt flag
0x4002101C C   FIELD 04w01 HSERDYF: HSE ready interrupt flag
0x4002101C C   FIELD 05w01 PLLSYSRDYF: PLL ready interrupt flag
0x4002101C C   FIELD 08w01 CSSF: Clock security system interrupt flag
0x4002101C C   FIELD 09w01 LSECSSF: LSE Clock security system interrupt flag
0x40021020 B  REGISTER CICR (wo): Clock interrupt clear register
0x40021020 C   FIELD 00w01 LSIRDYC: LSI ready interrupt clear
0x40021020 C   FIELD 01w01 LSERDYC: LSE ready interrupt clear
0x40021020 C   FIELD 03w01 HSIRDYC: HSI ready interrupt clear
0x40021020 C   FIELD 04w01 HSERDYC: HSE ready interrupt clear
0x40021020 C   FIELD 05w01 PLLSYSRDYC: PLL ready interrupt clear
0x40021020 C   FIELD 08w01 CSSC: Clock security system interrupt clear
0x40021020 C   FIELD 09w01 LSECSSC: LSE Clock security system interrupt clear
0x40021024 B  REGISTER IOPRSTR (rw): GPIO reset register
0x40021024 C   FIELD 00w01 IOPARST: I/O port A reset
0x40021024 C   FIELD 01w01 IOPBRST: I/O port B reset
0x40021024 C   FIELD 02w01 IOPCRST: I/O port C reset
0x40021024 C   FIELD 03w01 IOPDRST: I/O port D reset
0x40021024 C   FIELD 05w01 IOPFRST: I/O port F reset
0x40021028 B  REGISTER AHBRSTR (rw): AHB peripheral reset register
0x40021028 C   FIELD 00w01 DMARST: DMA1 reset
0x40021028 C   FIELD 08w01 FLASHRST: FLITF reset
0x40021028 C   FIELD 12w01 CRCRST: CRC reset
0x40021028 C   FIELD 16w01 AESRST: AES hardware accelerator reset
0x40021028 C   FIELD 18w01 RNGRST: Random number generator reset
0x4002102C B  REGISTER APBRSTR1 (rw): APB peripheral reset register 1
0x4002102C C   FIELD 00w01 TIM2RST: TIM2 timer reset
0x4002102C C   FIELD 01w01 TIM3RST: TIM3 timer reset
0x4002102C C   FIELD 14w01 SPI2RST: SPI2 reset
0x4002102C C   FIELD 17w01 USART2RST: USART2 reset
0x4002102C C   FIELD 20w01 LPUART1RST: LPUART1 reset
0x4002102C C   FIELD 21w01 I2C1RST: I2C1 reset
0x4002102C C   FIELD 22w01 I2C2RST: I2C2 reset
0x4002102C C   FIELD 27w01 DBGRST: Debug support reset
0x4002102C C   FIELD 28w01 PWRRST: Power interface reset
0x4002102C C   FIELD 30w01 LPTIM2RST: Low Power Timer 2 reset
0x4002102C C   FIELD 31w01 LPTIM1RST: Low Power Timer 1 reset
0x40021030 B  REGISTER APBRSTR2 (rw): APB peripheral reset register 2
0x40021030 C   FIELD 00w01 SYSCFGRST: SYSCFG, COMP and VREFBUF reset
0x40021030 C   FIELD 11w01 TIM1RST: TIM1 timer reset
0x40021030 C   FIELD 12w01 SPI1RST: SPI1 reset
0x40021030 C   FIELD 14w01 USART1RST: USART1 reset
0x40021030 C   FIELD 15w01 TIM14RST: TIM14 timer reset
0x40021030 C   FIELD 17w01 TIM16RST: TIM16 timer reset
0x40021030 C   FIELD 18w01 TIM17RST: TIM17 timer reset
0x40021030 C   FIELD 20w01 ADCRST: ADC reset
0x40021034 B  REGISTER IOPENR (rw): GPIO clock enable register
0x40021034 C   FIELD 00w01 IOPAEN: I/O port A clock enable
0x40021034 C   FIELD 01w01 IOPBEN: I/O port B clock enable
0x40021034 C   FIELD 02w01 IOPCEN: I/O port C clock enable
0x40021034 C   FIELD 03w01 IOPDEN: I/O port D clock enable
0x40021034 C   FIELD 05w01 IOPFEN: I/O port F clock enable
0x40021038 B  REGISTER AHBENR (rw): AHB peripheral clock enable register
0x40021038 C   FIELD 00w01 DMAEN: DMA clock enable
0x40021038 C   FIELD 08w01 FLASHEN: Flash memory interface clock enable
0x40021038 C   FIELD 12w01 CRCEN: CRC clock enable
0x40021038 C   FIELD 16w01 AESEN: AES hardware accelerator
0x40021038 C   FIELD 18w01 RNGEN: Random number generator clock enable
0x4002103C B  REGISTER APBENR1 (rw): APB peripheral clock enable register 1
0x4002103C C   FIELD 00w01 TIM2EN: TIM2 timer clock enable
0x4002103C C   FIELD 01w01 TIM3EN: TIM3 timer clock enable
0x4002103C C   FIELD 10w01 RTCAPBEN: RTC APB clock enable
0x4002103C C   FIELD 11w01 WWDGEN: WWDG clock enable
0x4002103C C   FIELD 14w01 SPI2EN: SPI2 clock enable
0x4002103C C   FIELD 17w01 USART2EN: USART2 clock enable
0x4002103C C   FIELD 20w01 LPUART1EN: LPUART1 clock enable
0x4002103C C   FIELD 21w01 I2C1EN: I2C1 clock enable
0x4002103C C   FIELD 22w01 I2C2EN: I2C2 clock enable
0x4002103C C   FIELD 27w01 DBGEN: Debug support clock enable
0x4002103C C   FIELD 28w01 PWREN: Power interface clock enable
0x4002103C C   FIELD 30w01 LPTIM2EN: LPTIM2 clock enable
0x4002103C C   FIELD 31w01 LPTIM1EN: LPTIM1 clock enable
0x40021040 B  REGISTER APBENR2 (rw): APB peripheral clock enable register 2
0x40021040 C   FIELD 00w01 SYSCFGEN: SYSCFG, COMP and VREFBUF clock enable
0x40021040 C   FIELD 11w01 TIM1EN: TIM1 timer clock enable
0x40021040 C   FIELD 12w01 SPI1EN: SPI1 clock enable
0x40021040 C   FIELD 14w01 USART1EN: USART1 clock enable
0x40021040 C   FIELD 15w01 TIM14EN: TIM14 timer clock enable
0x40021040 C   FIELD 17w01 TIM16EN: TIM16 timer clock enable
0x40021040 C   FIELD 18w01 TIM17EN: TIM16 timer clock enable
0x40021040 C   FIELD 20w01 ADCEN: ADC clock enable
0x40021044 B  REGISTER IOPSMENR (rw): GPIO in Sleep mode clock enable register
0x40021044 C   FIELD 00w01 IOPASMEN: I/O port A clock enable during Sleep mode
0x40021044 C   FIELD 01w01 IOPBSMEN: I/O port B clock enable during Sleep mode
0x40021044 C   FIELD 02w01 IOPCSMEN: I/O port C clock enable during Sleep mode
0x40021044 C   FIELD 03w01 IOPDSMEN: I/O port D clock enable during Sleep mode
0x40021044 C   FIELD 05w01 IOPFSMEN: I/O port F clock enable during Sleep mode
0x40021048 B  REGISTER AHBSMENR (rw): AHB peripheral clock enable in Sleep mode register
0x40021048 C   FIELD 00w01 DMASMEN: DMA clock enable during Sleep mode
0x40021048 C   FIELD 08w01 FLASHSMEN: Flash memory interface clock enable during Sleep mode
0x40021048 C   FIELD 09w01 SRAMSMEN: SRAM clock enable during Sleep mode
0x40021048 C   FIELD 12w01 CRCSMEN: CRC clock enable during Sleep mode
0x40021048 C   FIELD 16w01 AESSMEN: AES hardware accelerator clock enable during Sleep mode
0x40021048 C   FIELD 18w01 RNGSMEN: Random number generator clock enable during Sleep mode
0x4002104C B  REGISTER APBSMENR1 (rw): APB peripheral clock enable in Sleep mode register 1
0x4002104C C   FIELD 00w01 TIM2SMEN: TIM2 timer clock enable during Sleep mode
0x4002104C C   FIELD 01w01 TIM3SMEN: TIM3 timer clock enable during Sleep mode
0x4002104C C   FIELD 10w01 RTCAPBSMEN: RTC APB clock enable during Sleep mode
0x4002104C C   FIELD 11w01 WWDGSMEN: WWDG clock enable during Sleep mode
0x4002104C C   FIELD 14w01 SPI2SMEN: SPI2 clock enable during Sleep mode
0x4002104C C   FIELD 17w01 USART2SMEN: USART2 clock enable during Sleep mode
0x4002104C C   FIELD 20w01 LPUART1SMEN: LPUART1 clock enable during Sleep mode
0x4002104C C   FIELD 21w01 I2C1SMEN: I2C1 clock enable during Sleep mode
0x4002104C C   FIELD 22w01 I2C2SMEN: I2C2 clock enable during Sleep mode
0x4002104C C   FIELD 27w01 DBGSMEN: Debug support clock enable during Sleep mode
0x4002104C C   FIELD 28w01 PWRSMEN: Power interface clock enable during Sleep mode
0x4002104C C   FIELD 30w01 LPTIM2SMEN: Low Power Timer 2 clock enable during Sleep mode
0x4002104C C   FIELD 31w01 LPTIM1SMEN: Low Power Timer 1 clock enable during Sleep mode
0x40021050 B  REGISTER APBSMENR2 (rw): APB peripheral clock enable in Sleep mode register 2
0x40021050 C   FIELD 00w01 SYSCFGSMEN: SYSCFG, COMP and VREFBUF clock enable during Sleep mode
0x40021050 C   FIELD 11w01 TIM1SMEN: TIM1 timer clock enable during Sleep mode
0x40021050 C   FIELD 12w01 SPI1SMEN: SPI1 clock enable during Sleep mode
0x40021050 C   FIELD 14w01 USART1SMEN: USART1 clock enable during Sleep mode
0x40021050 C   FIELD 15w01 TIM14SMEN: TIM14 timer clock enable during Sleep mode
0x40021050 C   FIELD 17w01 TIM16SMEN: TIM16 timer clock enable during Sleep mode
0x40021050 C   FIELD 18w01 TIM17SMEN: TIM16 timer clock enable during Sleep mode
0x40021050 C   FIELD 20w01 ADCSMEN: ADC clock enable during Sleep mode
0x40021054 B  REGISTER CCIPR (rw): Peripherals independent clock configuration register
0x40021054 C   FIELD 00w02 USART1SEL: USART1 clock source selection
0x40021054 C   FIELD 10w02 LPUART1SEL: LPUART1 clock source selection
0x40021054 C   FIELD 12w02 I2C1SEL: I2C1 clock source selection
0x40021054 C   FIELD 14w02 I2S1SEL: I2S1 clock source selection
0x40021054 C   FIELD 18w02 LPTIM1SEL: LPTIM1 clock source selection
0x40021054 C   FIELD 20w02 LPTIM2SEL: LPTIM2 clock source selection
0x40021054 C   FIELD 22w01 TIM1SEL: TIM1 clock source selection
0x40021054 C   FIELD 26w02 RNGSEL: RNG clock source selection
0x40021054 C   FIELD 28w02 RNGDIV: Division factor of RNG clock divider
0x40021054 C   FIELD 30w02 ADCSEL: ADCs clock source selection
0x4002105C B  REGISTER BDCR (rw): RTC domain control register
0x4002105C C   FIELD 00w01 LSEON: LSE oscillator enable
0x4002105C C   FIELD 01w01 LSERDY: LSE oscillator ready
0x4002105C C   FIELD 02w01 LSEBYP: LSE oscillator bypass
0x4002105C C   FIELD 03w02 LSEDRV: LSE oscillator drive capability
0x4002105C C   FIELD 05w01 LSECSSON: CSS on LSE enable
0x4002105C C   FIELD 06w01 LSECSSD: CSS on LSE failure Detection
0x4002105C C   FIELD 08w02 RTCSEL: RTC clock source selection
0x4002105C C   FIELD 15w01 RTCEN: RTC clock enable
0x4002105C C   FIELD 16w01 BDRST: RTC domain software reset
0x4002105C C   FIELD 24w01 LSCOEN: Low-speed clock output (LSCO) enable
0x4002105C C   FIELD 25w01 LSCOSEL: Low-speed clock output selection
0x40021060 B  REGISTER CSR (rw): Control/status register
0x40021060 C   FIELD 00w01 LSION: LSI oscillator enable
0x40021060 C   FIELD 01w01 LSIRDY: LSI oscillator ready
0x40021060 C   FIELD 23w01 RMVF: Remove reset flags
0x40021060 C   FIELD 25w01 OBLRSTF: Option byte loader reset flag
0x40021060 C   FIELD 26w01 PINRSTF: Pin reset flag
0x40021060 C   FIELD 27w01 PWRRSTF: BOR or POR/PDR flag
0x40021060 C   FIELD 28w01 SFTRSTF: Software reset flag
0x40021060 C   FIELD 29w01 IWDGRSTF: Independent window watchdog reset flag
0x40021060 C   FIELD 30w01 WWDGRSTF: Window watchdog reset flag
0x40021060 C   FIELD 31w01 LPWRRSTF: Low-power reset flag
0x40021800 A PERIPHERAL EXTI
0x40021800 B  REGISTER RTSR1 (rw): EXTI rising trigger selection register
0x40021800 C   FIELD 00w01 TR0: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 01w01 TR1: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 02w01 TR2: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 03w01 TR3: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 04w01 TR4: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 05w01 TR5: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 06w01 TR6: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 07w01 TR7: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 08w01 TR8: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 09w01 TR9: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 10w01 TR10: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 11w01 TR11: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 12w01 TR12: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 13w01 TR13: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 14w01 TR14: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 15w01 TR15: Rising trigger event configuration bit of Configurable Event input
0x40021800 C   FIELD 16w01 TR16: Rising trigger event configuration bit of Configurable Event input
0x40021804 B  REGISTER FTSR1 (rw): EXTI falling trigger selection register
0x40021804 C   FIELD 00w01 TR0: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 01w01 TR1: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 02w01 TR2: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 03w01 TR3: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 04w01 TR4: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 05w01 TR5: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 06w01 TR6: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 07w01 TR7: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 08w01 TR8: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 09w01 TR9: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 10w01 TR10: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 11w01 TR11: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 12w01 TR12: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 13w01 TR13: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 14w01 TR14: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 15w01 TR15: Rising trigger event configuration bit of Configurable Event input
0x40021804 C   FIELD 16w01 TR16: Rising trigger event configuration bit of Configurable Event input
0x40021808 B  REGISTER SWIER1 (rw): EXTI software interrupt event register
0x40021808 C   FIELD 00w01 SWIER0: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 01w01 SWIER1: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 02w01 SWIER2: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 03w01 SWIER3: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 04w01 SWIER4: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 05w01 SWIER5: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 06w01 SWIER6: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 07w01 SWIER7: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 08w01 SWIER8: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 09w01 SWIER9: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 10w01 SWIER10: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 11w01 SWIER11: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 12w01 SWIER12: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 13w01 SWIER13: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 14w01 SWIER14: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 15w01 SWIER15: Rising trigger event configuration bit of Configurable Event input
0x40021808 C   FIELD 16w01 SWIER16: Rising trigger event configuration bit of Configurable Event input
0x4002180C B  REGISTER RPR1 (rw): EXTI rising edge pending register
0x4002180C C   FIELD 00w01 RPIF0: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 01w01 RPIF1: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 02w01 RPIF2: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 03w01 RPIF3: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 04w01 RPIF4: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 05w01 RPIF5: configurable event inputs x rising edge Pending bit
0x4002180C C   FIELD 06w01 RPIF6: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 07w01 RPIF7: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 08w01 RPIF8: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 09w01 RPIF9: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 10w01 RPIF10: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 11w01 RPIF11: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 12w01 RPIF12: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 13w01 RPIF13: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 14w01 RPIF14: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 15w01 RPIF15: configurable event inputs x rising edge Pending bit.
0x4002180C C   FIELD 16w01 RPIF16: configurable event inputs x rising edge Pending bit.
0x40021810 B  REGISTER FPR1 (rw): EXTI falling edge pending register
0x40021810 C   FIELD 00w01 FPIF0: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 01w01 FPIF1: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 02w01 FPIF2: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 03w01 FPIF3: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 04w01 FPIF4: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 05w01 FPIF5: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 06w01 FPIF6: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 07w01 FPIF7: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 08w01 FPIF8: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 09w01 FPIF9: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 10w01 FPIF10: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 11w01 FPIF11: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 12w01 FPIF12: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 13w01 FPIF13: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 14w01 FPIF14: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 15w01 FPIF15: configurable event inputs x falling edge pending bit.
0x40021810 C   FIELD 16w01 FPIF16: configurable event inputs x falling edge pending bit.
0x40021860 B  REGISTER EXTICR1 (rw): EXTI external interrupt selection register
0x40021860 C   FIELD 00w08 EXTI0: GPIO port selection
0x40021860 C   FIELD 08w08 EXTI1 (=EXTI0): GPIO port selection
0x40021860 C   FIELD 16w08 EXTI2 (=EXTI0): GPIO port selection
0x40021860 C   FIELD 24w08 EXTI3 (=EXTI0): GPIO port selection
0x40021864 B  REGISTER EXTICR2 (rw): EXTI external interrupt selection register
0x40021864 C   FIELD 00w08 EXTI4 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x40021864 C   FIELD 08w08 EXTI5 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x40021864 C   FIELD 16w08 EXTI6 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x40021864 C   FIELD 24w08 EXTI7 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x40021868 B  REGISTER EXTICR3 (rw): EXTI external interrupt selection register
0x40021868 C   FIELD 00w08 EXTI8 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x40021868 C   FIELD 08w08 EXTI9 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x40021868 C   FIELD 16w08 EXTI10 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x40021868 C   FIELD 24w08 EXTI11 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x4002186C B  REGISTER EXTICR4 (rw): EXTI external interrupt selection register
0x4002186C C   FIELD 00w08 EXTI12 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x4002186C C   FIELD 08w08 EXTI13 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x4002186C C   FIELD 16w08 EXTI14 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x4002186C C   FIELD 24w08 EXTI15 (=EXTI.EXTICR1.EXTI0): GPIO port selection
0x40021880 B  REGISTER IMR1 (rw): EXTI CPU wakeup with interrupt mask register
0x40021880 C   FIELD 00w01 IM0: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 01w01 IM1: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 02w01 IM2: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 03w01 IM3: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 04w01 IM4: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 05w01 IM5: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 06w01 IM6: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 07w01 IM7: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 08w01 IM8: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 09w01 IM9: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 10w01 IM10: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 11w01 IM11: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 12w01 IM12: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 13w01 IM13: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 14w01 IM14: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 15w01 IM15: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 16w01 IM16: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 19w01 IM19: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 20w01 IM20: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 21w01 IM21: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 22w01 IM22: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 23w01 IM23: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 24w01 IM24: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 25w01 IM25: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 26w01 IM26: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 28w01 IM28: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 29w01 IM29: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 30w01 IM30: CPU wakeup with interrupt mask on event input
0x40021880 C   FIELD 31w01 IM31: CPU wakeup with interrupt mask on event input
0x40021884 B  REGISTER EMR1 (rw): EXTI CPU wakeup with event mask register
0x40021884 C   FIELD 00w01 EM0: CPU wakeup with event mask on event input
0x40021884 C   FIELD 01w01 EM1: CPU wakeup with event mask on event input
0x40021884 C   FIELD 02w01 EM2: CPU wakeup with event mask on event input
0x40021884 C   FIELD 03w01 EM3: CPU wakeup with event mask on event input
0x40021884 C   FIELD 04w01 EM4: CPU wakeup with event mask on event input
0x40021884 C   FIELD 05w01 EM5: CPU wakeup with event mask on event input
0x40021884 C   FIELD 06w01 EM6: CPU wakeup with event mask on event input
0x40021884 C   FIELD 07w01 EM7: CPU wakeup with event mask on event input
0x40021884 C   FIELD 08w01 EM8: CPU wakeup with event mask on event input
0x40021884 C   FIELD 09w01 EM9: CPU wakeup with event mask on event input
0x40021884 C   FIELD 10w01 EM10: CPU wakeup with event mask on event input
0x40021884 C   FIELD 11w01 EM11: CPU wakeup with event mask on event input
0x40021884 C   FIELD 12w01 EM12: CPU wakeup with event mask on event input
0x40021884 C   FIELD 13w01 EM13: CPU wakeup with event mask on event input
0x40021884 C   FIELD 14w01 EM14: CPU wakeup with event mask on event input
0x40021884 C   FIELD 15w01 EM15: CPU wakeup with event mask on event input
0x40021884 C   FIELD 16w01 EM16: CPU wakeup with event mask on event input
0x40021884 C   FIELD 19w01 EM19: CPU wakeup with event mask on event input
0x40021884 C   FIELD 21w01 EM21: CPU wakeup with event mask on event input
0x40021884 C   FIELD 23w01 EM23: CPU wakeup with event mask on event input
0x40021884 C   FIELD 25w01 EM25: CPU wakeup with event mask on event input
0x40021884 C   FIELD 26w01 EM26: CPU wakeup with event mask on event input
0x40021884 C   FIELD 28w01 EM28: CPU wakeup with event mask on event input
0x40021884 C   FIELD 29w01 EM29: CPU wakeup with event mask on event input
0x40021884 C   FIELD 30w01 EM30: CPU wakeup with event mask on event input
0x40021884 C   FIELD 31w01 EM31: CPU wakeup with event mask on event input
0x40022000 A PERIPHERAL FLASH
0x40022000 B  REGISTER ACR (rw): Access control register
0x40022000 C   FIELD 00w03 LATENCY: Latency
0x40022000 C   FIELD 08w01 PRFTEN: Prefetch enable
0x40022000 C   FIELD 09w01 ICEN: Instruction cache enable
0x40022000 C   FIELD 11w01 ICRST: Instruction cache reset
0x40022000 C   FIELD 16w01 EMPTY: Flash User area empty
0x40022000 C   FIELD 18w01 DBG_SWEN: Debug access software enable
0x40022008 B  REGISTER KEYR (wo): Flash key register
0x40022008 C   FIELD 00w32 KEY: KEYR
0x4002200C B  REGISTER OPTKEYR (wo): Option byte key register
0x4002200C C   FIELD 00w32 OPTKEY: Option byte key
0x40022010 B  REGISTER SR (rw): Status register
0x40022010 C   FIELD 00w01 EOP: End of operation
0x40022010 C   FIELD 01w01 OPERR: Operation error
0x40022010 C   FIELD 03w01 PROGERR: Programming error
0x40022010 C   FIELD 04w01 WRPERR: Write protected error
0x40022010 C   FIELD 05w01 PGAERR: Programming alignment error
0x40022010 C   FIELD 06w01 SIZERR: Size error
0x40022010 C   FIELD 07w01 PGSERR: Programming sequence error
0x40022010 C   FIELD 08w01 MISSERR: Fast programming data miss error
0x40022010 C   FIELD 09w01 FASTERR: Fast programming error
0x40022010 C   FIELD 14w01 RDERR: PCROP read error
0x40022010 C   FIELD 15w01 OPTVERR: Option and Engineering bits loading validity error
0x40022010 C   FIELD 16w01 BSY: Busy
0x40022010 C   FIELD 18w01 CFGBSY: Programming or erase configuration busy.
0x40022014 B  REGISTER CR (rw): Flash control register
0x40022014 C   FIELD 00w01 PG: Programming
0x40022014 C   FIELD 01w01 PER: Page erase
0x40022014 C   FIELD 02w01 MER1: Mass erase
0x40022014 C   FIELD 03w10 PNB: Page number
0x40022014 C   FIELD 13w01 BKER: Bank selection for erase operation
0x40022014 C   FIELD 15w01 MER2: Mass erase, Bank 2
0x40022014 C   FIELD 16w01 STRT: Start
0x40022014 C   FIELD 17w01 OPTSTRT: Options modification start
0x40022014 C   FIELD 18w01 FSTPG: Fast programming
0x40022014 C   FIELD 24w01 EOPIE: End of operation interrupt enable
0x40022014 C   FIELD 25w01 ERRIE: Error interrupt enable
0x40022014 C   FIELD 26w01 RDERRIE: PCROP read error interrupt enable
0x40022014 C   FIELD 27w01 OBL_LAUNCH: Force the option byte loading
0x40022014 C   FIELD 28w01 SEC_PROT: Securable memory area protection enable
0x40022014 C   FIELD 29w01 SEC_PROT2: Securable memory area protection enable, Bank 2
0x40022014 C   FIELD 30w01 OPTLOCK: Options Lock
0x40022014 C   FIELD 31w01 LOCK: FLASH_CR Lock
0x40022018 B  REGISTER ECCR: Flash ECC register
0x40022018 C   FIELD 00w15 ADDR_ECC (ro): ECC fail address
0x40022018 C   FIELD 20w01 SYSF_ECC (ro): ECC fail for Corrected ECC Error or Double ECC Error in info block
0x40022018 C   FIELD 24w01 ECCIE (rw): ECC correction interrupt enable
0x40022018 C   FIELD 30w01 ECCC (rw): ECC correction
0x40022018 C   FIELD 31w01 ECCD (rw): ECC detection
0x4002201C B  REGISTER ECCR2: Flash ECC register 2
0x4002201C C   FIELD 00w15 ADDR_ECC (ro): ECC fail address
0x4002201C C   FIELD 20w01 SYSF_ECC (ro): ECC fail for Corrected ECC Error or Double ECC Error in info block
0x4002201C C   FIELD 24w01 ECCIE (rw): ECC correction interrupt enable
0x4002201C C   FIELD 30w01 ECCC (rw): ECC correction
0x4002201C C   FIELD 31w01 ECCD (rw): ECC detection
0x40022020 B  REGISTER OPTR (rw): Flash option register
0x40022020 C   FIELD 00w08 RDP: Read protection level
0x40022020 C   FIELD 08w01 BOREN: BOR reset Level
0x40022020 C   FIELD 09w02 BORF_LEV: These bits contain the VDD supply level threshold that activates the reset
0x40022020 C   FIELD 11w02 BORR_LEV: These bits contain the VDD supply level threshold that releases the reset.
0x40022020 C   FIELD 13w01 nRST_STOP: nRST_STOP
0x40022020 C   FIELD 14w01 nRST_STDBY: nRST_STDBY
0x40022020 C   FIELD 15w01 nRSTS_HDW: nRSTS_HDW
0x40022020 C   FIELD 16w01 IWDG_SW: Independent watchdog selection
0x40022020 C   FIELD 17w01 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0x40022020 C   FIELD 18w01 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0x40022020 C   FIELD 19w01 WWDG_SW: Window watchdog selection
0x40022020 C   FIELD 22w01 RAM_PARITY_CHECK: SRAM parity check control
0x40022020 C   FIELD 24w01 nBOOT_SEL: nBOOT_SEL
0x40022020 C   FIELD 25w01 nBOOT1: Boot configuration
0x40022020 C   FIELD 26w01 nBOOT0: nBOOT0 option bit
0x40022020 C   FIELD 27w02 NRST_MODE: NRST_MODE
0x40022020 C   FIELD 29w01 IRHEN: Internal reset holder enable bit
0x40022024 B  REGISTER PCROP1ASR (ro): Flash PCROP zone A Start address register
0x40022024 C   FIELD 00w08 PCROP1A_STRT: PCROP1A area start offset
0x40022028 B  REGISTER PCROP1AER (ro): Flash PCROP zone A End address register
0x40022028 C   FIELD 00w08 PCROP1A_END: PCROP1A area end offset
0x40022028 C   FIELD 31w01 PCROP_RDP: PCROP area preserved when RDP level decreased
0x4002202C B  REGISTER WRP1AR (rw): Flash WRP area A address register
0x4002202C C   FIELD 00w06 WRP1A_STRT: WRP area A start offset
0x4002202C C   FIELD 16w06 WRP1A_END: WRP area A end offset
0x40022030 B  REGISTER WRP1BR (rw): Flash WRP area B address register
0x40022030 C   FIELD 00w06 WRP1B_STRT: WRP area B start offset
0x40022030 C   FIELD 16w06 WRP1B_END: WRP area B end offset
0x40022034 B  REGISTER PCROP1BSR (ro): Flash PCROP zone B Start address register
0x40022034 C   FIELD 00w08 PCROP1B_STRT: PCROP1B area start offset
0x40022038 B  REGISTER PCROP1BER (rw): Flash PCROP area B End address register
0x40022038 C   FIELD 00w09 PCROP1B_END: PCROP1B area end offset
0x40022044 B  REGISTER PCROP2ASR (rw): Flash PCROP2 area A start address register
0x40022044 C   FIELD 00w09 PCROP2A_STRT: PCROP2A area start offset, bank2
0x40022048 B  REGISTER PCROP2AER (rw): Flash PCROP2 area A end address register
0x40022048 C   FIELD 00w09 PCROP2A_END: PCROP2A area end offset, bank2
0x4002204C B  REGISTER WRP2AR (rw): Flash WRP2 area A address register
0x4002204C C   FIELD 00w07 WRP2A_STRT: WRP area A start offset, Bank 2
0x4002204C C   FIELD 16w07 WRP2A_END: WRP area A end offset, Bank 2
0x40022050 B  REGISTER WRP2BR (rw): Flash WRP2 area B address register
0x40022050 C   FIELD 00w07 WRP2B_STRT: WRP area B start offset, Bank 2
0x40022050 C   FIELD 16w07 WRP2B_END: WRP area B end offset, Bank 2
0x40022054 B  REGISTER PCROP2BSR (rw): FLASH PCROP2 area B start address register
0x40022054 C   FIELD 00w09 PCROP2B_STRT: PCROP2B area start offset, Bank 2
0x40022058 B  REGISTER PCROP2BER (rw): FLASH PCROP2 area B end address register
0x40022058 C   FIELD 00w09 PCROP2B_END: PCROP2B area end offset, Bank 2
0x40022080 B  REGISTER SECR (rw): Flash Security register
0x40022080 C   FIELD 00w08 SEC_SIZE: Securable memory area size
0x40022080 C   FIELD 16w01 BOOT_LOCK: used to force boot from user area
0x40022080 C   FIELD 20w08 SEC_SIZE2: Securable memory area size
0x40023000 A PERIPHERAL CRC
0x40023000 B  REGISTER DR (rw): Data register
0x40023000 C   FIELD 00w32 DR: Data register bits
0x40023004 B  REGISTER IDR (rw): Independent data register
0x40023004 C   FIELD 00w32 IDR: General-purpose 32-bit data register bits
0x40023008 B  REGISTER CR: Control register
0x40023008 C   FIELD 00w01 RESET (wo): RESET bit
0x40023008 C   FIELD 03w02 POLYSIZE (rw): Polynomial size These bits control the size of the polynomial.
0x40023008 C   FIELD 05w02 REV_IN (rw): Reverse input data These bits control the reversal of the bit order of the input data
0x40023008 C   FIELD 07w01 REV_OUT (rw): Reverse output data This bit controls the reversal of the bit order of the output data.
0x40023010 B  REGISTER INIT (rw): Initial CRC value
0x40023010 C   FIELD 00w32 CRC_INIT: Programmable initial CRC value
0x40023014 B  REGISTER POL (rw): polynomial
0x40023014 C   FIELD 00w32 POL: Programmable polynomial
0x40025000 A PERIPHERAL RNG
0x40025000 B  REGISTER CR: control register
0x40025000 C   FIELD 02w01 RNGEN (rw): True random number generator enable
0x40025000 C   FIELD 03w01 IE (rw): Interrupt Enable
0x40025000 C   FIELD 05w01 CED (rw): Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled.
0x40025004 B  REGISTER SR: status register
0x40025004 C   FIELD 00w01 DRDY (ro): Data Ready Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. Note: The DRDY bit can rise when the peripheral is disabled (RNGEN=0 in the RNG_CR register). If IE=1 in the RNG_CR register, an interrupt is generated when DRDY=1.
0x40025004 C   FIELD 01w01 CECS (ro): Clock error current status Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0.
0x40025004 C   FIELD 02w01 SECS (ro): Seed error current status One of the noise source has provided more than 64 consecutive bits at a constant value ('0' or '1'), or more than 32 consecutive occurrence of two bit patterns ('01' or '10') Both noise sources have delivered more than 32 consecutive bits at a constant value ('0' or '1'), or more than 16 consecutive occurrence of two bit patterns ('01' or '10')
0x40025004 C   FIELD 05w01 CEIS (rw): Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.
0x40025004 C   FIELD 06w01 SEIS (rw): Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.
0x40025008 B  REGISTER DR: RNG data register
0x40025008 C   FIELD 00w32 RNDATA (ro): Random data 32-bit random data which are valid when DRDY=1. When DRDY=0 RNDATA value is zero. It is recommended to always verify that RNG_DR is different from zero. Because when it is the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare event).
0x40026000 A PERIPHERAL AES
0x40026000 B  REGISTER CR: AES control register
0x40026000 C   FIELD 00w01 EN (rw): AES enable This bit enables/disables the AES peripheral: At any moment, clearing then setting the bit re-initializes the AES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase.
0x40026000 C   FIELD 01w02 DATATYPE (rw): Data type selection This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.
0x40026000 C   FIELD 03w02 MODE (rw): AES operating mode This bitfield selects the AES operating mode: Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. Any attempt to selecting Mode 4 while either ECB or CBC chaining mode is not selected, defaults to effective selection of Mode 3. It is not possible to select a Mode 3 following a Mode 4.
0x40026000 C   FIELD 05w02 CHMOD1 (rw): Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.
0x40026000 C   FIELD 07w01 CCFC (rw): Computation complete flag clear Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register: Reading the flag always returns zero.
0x40026000 C   FIELD 08w01 ERRC (rw): Error flag clear Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register: Reading the flag always returns zero.
0x40026000 C   FIELD 09w01 CCFIE (rw): CCF interrupt enable This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set:
0x40026000 C   FIELD 10w01 ERRIE (rw): Error interrupt enable This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is set:
0x40026000 C   FIELD 11w01 DMAINEN (rw): DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by AES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended.
0x40026000 C   FIELD 12w01 DMAOUTEN (rw): DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by AES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended.
0x40026000 C   FIELD 13w02 GCMPH (rw): GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).
0x40026000 C   FIELD 16w01 CHMOD2 (rw): Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.
0x40026000 C   FIELD 18w01 KEYSIZE (rw): Key size selection This bitfield defines the length of the key used in the AES cryptographic core, in bits: Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.
0x40026000 C   FIELD 20w04 NPBLB (rw): Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ...
0x40026004 B  REGISTER SR: AES control register
0x40026004 C   FIELD 00w01 CCF (ro): Computation completed flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCFC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.
0x40026004 C   FIELD 01w01 RDERR (ro): Read error flag This flag indicates the detection of an unexpected read operation from the AES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected read returns zero.
0x40026004 C   FIELD 02w01 WRERR (ro): Write error This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register. Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register. The flag setting has no impact on the AES operation. Unexpected write is ignored.
0x40026004 C   FIELD 03w01 BUSY (ro): Busy This flag indicates whether AES is idle or busy during GCM payload encryption phase
0x40026008 B  REGISTER DINR: AES data input register
0x40026008 C   FIELD 00w32 DIN (rw): Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer. The data signification of the input data block depends on the AES operating mode: - Mode 1 (encryption): plaintext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): ciphertext The data swap operation is described in page499.
0x4002600C B  REGISTER DOUTR: AES data output register
0x4002600C C   FIELD 00w32 DOUT (ro): Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield. Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0]. The data signification of the output data block depends on the AES operating mode: - Mode 1 (encryption): ciphertext - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for output) - Mode 3 (decryption) and Mode 4 (key derivation then single decryption): plaintext The data swap operation is described in page499.
0x40026010 B  REGISTER KEYR0: AES key register 0
0x40026010 C   FIELD 00w32 KEY (rw): Cryptographic key, bits [31:0] This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single decryption): the value to write into the bitfield is the encryption key. - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. After writing the encryption key into the bitfield, its reading before enabling AES returns the same value. Its reading after enabling AES and after the CCF flag is set returns the decryption key derived from the encryption key. Note: In mode 4 (key derivation then single decryption) the bitfield always contains the encryption key. The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set). Refer to for more details.
0x40026014 B  REGISTER KEYR1: AES key register 1
0x40026014 C   FIELD 00w32 KEY (rw): Cryptographic key, bits [63:32] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
0x40026018 B  REGISTER KEYR2: AES key register 2
0x40026018 C   FIELD 00w32 KEY (rw): Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
0x4002601C B  REGISTER KEYR3: AES key register 3
0x4002601C C   FIELD 00w32 KEY (rw): Cryptographic key, bits [127:96] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
0x40026020 B  REGISTER IVR0: AES initialization vector register 0
0x40026020 C   FIELD 00w32 IVI (rw): Initialization vector input, bits [31:0] Refer to for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The AES_IVRx registers may be written only when the AES peripheral is disabled
0x40026024 B  REGISTER IVR1: AES initialization vector register 1
0x40026024 C   FIELD 00w32 IVI (rw): Initialization vector input, bits [63:32] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
0x40026028 B  REGISTER IVR2: AES initialization vector register 2
0x40026028 C   FIELD 00w32 IVI (rw): Initialization vector input, bits [95:64] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
0x4002602C B  REGISTER IVR3: AES initialization vector register 3
0x4002602C C   FIELD 00w32 IVI (rw): Initialization vector input, bits [127:96] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
0x40026030 B  REGISTER KEYR4: AES key register 4
0x40026030 C   FIELD 00w32 KEY (rw): Cryptographic key, bits [159:128] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
0x40026034 B  REGISTER KEYR5: AES key register 5
0x40026034 C   FIELD 00w32 KEY (rw): Cryptographic key, bits [191:160] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
0x40026038 B  REGISTER KEYR6: AES key register 6
0x40026038 C   FIELD 00w32 KEY (rw): Cryptographic key, bits [223:192] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
0x4002603C B  REGISTER KEYR7: AES key register 7
0x4002603C C   FIELD 00w32 KEY (rw): Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
0x40026040 B  REGISTER SUSP0R: AES suspend registers
0x40026040 C   FIELD 00w32 SUSP (rw): AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
0x40026044 B  REGISTER SUSP1R: AES suspend registers
0x40026044 C   FIELD 00w32 SUSP (rw): AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
0x40026048 B  REGISTER SUSP2R: AES suspend registers
0x40026048 C   FIELD 00w32 SUSP (rw): AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
0x4002604C B  REGISTER SUSP3R: AES suspend registers
0x4002604C C   FIELD 00w32 SUSP (rw): AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
0x40026050 B  REGISTER SUSP4R: AES suspend registers
0x40026050 C   FIELD 00w32 SUSP (rw): AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
0x40026054 B  REGISTER SUSP5R: AES suspend registers
0x40026054 C   FIELD 00w32 SUSP (rw): AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
0x40026058 B  REGISTER SUSP6R: AES suspend registers
0x40026058 C   FIELD 00w32 SUSP (rw): AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
0x4002605C B  REGISTER SUSP7R: AES suspend registers
0x4002605C C   FIELD 00w32 SUSP (rw): AES suspend Upon suspend operation, this bitfield of every AES_SUSPxR register takes the value of one of internal AES registers.
0x50000000 A PERIPHERAL GPIOA
0x50000000 B  REGISTER MODER (rw): GPIO port mode register
0x50000000 C   FIELD 00w02 MODER0: Port x configuration pin 0
0x50000000 C   FIELD 02w02 MODER1: Port x configuration pin 1
0x50000000 C   FIELD 04w02 MODER2: Port x configuration pin 2
0x50000000 C   FIELD 06w02 MODER3: Port x configuration pin 3
0x50000000 C   FIELD 08w02 MODER4: Port x configuration pin 4
0x50000000 C   FIELD 10w02 MODER5: Port x configuration pin 5
0x50000000 C   FIELD 12w02 MODER6: Port x configuration pin 6
0x50000000 C   FIELD 14w02 MODER7: Port x configuration pin 7
0x50000000 C   FIELD 16w02 MODER8: Port x configuration pin 8
0x50000000 C   FIELD 18w02 MODER9: Port x configuration pin 9
0x50000000 C   FIELD 20w02 MODER10: Port x configuration pin 10
0x50000000 C   FIELD 22w02 MODER11: Port x configuration pin 11
0x50000000 C   FIELD 24w02 MODER12: Port x configuration pin 12
0x50000000 C   FIELD 26w02 MODER13: Port x configuration pin 13
0x50000000 C   FIELD 28w02 MODER14: Port x configuration pin 14
0x50000000 C   FIELD 30w02 MODER15: Port x configuration pin 15
0x50000004 B  REGISTER OTYPER (rw): GPIO port output type register
0x50000004 C   FIELD 00w01 OT0: Port x configuration pin 0
0x50000004 C   FIELD 01w01 OT1: Port x configuration pin 1
0x50000004 C   FIELD 02w01 OT2: Port x configuration pin 2
0x50000004 C   FIELD 03w01 OT3: Port x configuration pin 3
0x50000004 C   FIELD 04w01 OT4: Port x configuration pin 4
0x50000004 C   FIELD 05w01 OT5: Port x configuration pin 5
0x50000004 C   FIELD 06w01 OT6: Port x configuration pin 6
0x50000004 C   FIELD 07w01 OT7: Port x configuration pin 7
0x50000004 C   FIELD 08w01 OT8: Port x configuration pin 8
0x50000004 C   FIELD 09w01 OT9: Port x configuration pin 9
0x50000004 C   FIELD 10w01 OT10: Port x configuration pin 10
0x50000004 C   FIELD 11w01 OT11: Port x configuration pin 11
0x50000004 C   FIELD 12w01 OT12: Port x configuration pin 12
0x50000004 C   FIELD 13w01 OT13: Port x configuration pin 13
0x50000004 C   FIELD 14w01 OT14: Port x configuration pin 14
0x50000004 C   FIELD 15w01 OT15: Port x configuration pin 15
0x50000008 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50000008 C   FIELD 00w02 OSPEEDR0: Port x configuration pin 0
0x50000008 C   FIELD 02w02 OSPEEDR1: Port x configuration pin 1
0x50000008 C   FIELD 04w02 OSPEEDR2: Port x configuration pin 2
0x50000008 C   FIELD 06w02 OSPEEDR3: Port x configuration pin 3
0x50000008 C   FIELD 08w02 OSPEEDR4: Port x configuration pin 4
0x50000008 C   FIELD 10w02 OSPEEDR5: Port x configuration pin 5
0x50000008 C   FIELD 12w02 OSPEEDR6: Port x configuration pin 6
0x50000008 C   FIELD 14w02 OSPEEDR7: Port x configuration pin 7
0x50000008 C   FIELD 16w02 OSPEEDR8: Port x configuration pin 8
0x50000008 C   FIELD 18w02 OSPEEDR9: Port x configuration pin 9
0x50000008 C   FIELD 20w02 OSPEEDR10: Port x configuration pin 10
0x50000008 C   FIELD 22w02 OSPEEDR11: Port x configuration pin 11
0x50000008 C   FIELD 24w02 OSPEEDR12: Port x configuration pin 12
0x50000008 C   FIELD 26w02 OSPEEDR13: Port x configuration pin 13
0x50000008 C   FIELD 28w02 OSPEEDR14: Port x configuration pin 14
0x50000008 C   FIELD 30w02 OSPEEDR15: Port x configuration pin 15
0x5000000C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x5000000C C   FIELD 00w02 PUPDR0: Port x configuration pin 0
0x5000000C C   FIELD 02w02 PUPDR1: Port x configuration pin 1
0x5000000C C   FIELD 04w02 PUPDR2: Port x configuration pin 2
0x5000000C C   FIELD 06w02 PUPDR3: Port x configuration pin 3
0x5000000C C   FIELD 08w02 PUPDR4: Port x configuration pin 4
0x5000000C C   FIELD 10w02 PUPDR5: Port x configuration pin 5
0x5000000C C   FIELD 12w02 PUPDR6: Port x configuration pin 6
0x5000000C C   FIELD 14w02 PUPDR7: Port x configuration pin 7
0x5000000C C   FIELD 16w02 PUPDR8: Port x configuration pin 8
0x5000000C C   FIELD 18w02 PUPDR9: Port x configuration pin 9
0x5000000C C   FIELD 20w02 PUPDR10: Port x configuration pin 10
0x5000000C C   FIELD 22w02 PUPDR11: Port x configuration pin 11
0x5000000C C   FIELD 24w02 PUPDR12: Port x configuration pin 12
0x5000000C C   FIELD 26w02 PUPDR13: Port x configuration pin 13
0x5000000C C   FIELD 28w02 PUPDR14: Port x configuration pin 14
0x5000000C C   FIELD 30w02 PUPDR15: Port x configuration pin 15
0x50000010 B  REGISTER IDR (ro): GPIO port input data register
0x50000010 C   FIELD 00w01 IDR0: Port input data pin 0
0x50000010 C   FIELD 01w01 IDR1: Port input data pin 1
0x50000010 C   FIELD 02w01 IDR2: Port input data pin 2
0x50000010 C   FIELD 03w01 IDR3: Port input data pin 3
0x50000010 C   FIELD 04w01 IDR4: Port input data pin 4
0x50000010 C   FIELD 05w01 IDR5: Port input data pin 5
0x50000010 C   FIELD 06w01 IDR6: Port input data pin 6
0x50000010 C   FIELD 07w01 IDR7: Port input data pin 7
0x50000010 C   FIELD 08w01 IDR8: Port input data pin 8
0x50000010 C   FIELD 09w01 IDR9: Port input data pin 9
0x50000010 C   FIELD 10w01 IDR10: Port input data pin 10
0x50000010 C   FIELD 11w01 IDR11: Port input data pin 11
0x50000010 C   FIELD 12w01 IDR12: Port input data pin 12
0x50000010 C   FIELD 13w01 IDR13: Port input data pin 13
0x50000010 C   FIELD 14w01 IDR14: Port input data pin 14
0x50000010 C   FIELD 15w01 IDR15: Port input data pin 15
0x50000014 B  REGISTER ODR (rw): GPIO port output data register
0x50000014 C   FIELD 00w01 ODR0: Port output data pin 0
0x50000014 C   FIELD 01w01 ODR1: Port output data pin 1
0x50000014 C   FIELD 02w01 ODR2: Port output data pin 2
0x50000014 C   FIELD 03w01 ODR3: Port output data pin 3
0x50000014 C   FIELD 04w01 ODR4: Port output data pin 4
0x50000014 C   FIELD 05w01 ODR5: Port output data pin 5
0x50000014 C   FIELD 06w01 ODR6: Port output data pin 6
0x50000014 C   FIELD 07w01 ODR7: Port output data pin 7
0x50000014 C   FIELD 08w01 ODR8: Port output data pin 8
0x50000014 C   FIELD 09w01 ODR9: Port output data pin 9
0x50000014 C   FIELD 10w01 ODR10: Port output data pin 10
0x50000014 C   FIELD 11w01 ODR11: Port output data pin 11
0x50000014 C   FIELD 12w01 ODR12: Port output data pin 12
0x50000014 C   FIELD 13w01 ODR13: Port output data pin 13
0x50000014 C   FIELD 14w01 ODR14: Port output data pin 14
0x50000014 C   FIELD 15w01 ODR15: Port output data pin 15
0x50000018 B  REGISTER BSRR (wo): GPIO port bit set/reset register
0x50000018 C   FIELD 00w01 BS0: Port x set pin 0
0x50000018 C   FIELD 01w01 BS1: Port x set pin 1
0x50000018 C   FIELD 02w01 BS2: Port x set pin 2
0x50000018 C   FIELD 03w01 BS3: Port x set pin 3
0x50000018 C   FIELD 04w01 BS4: Port x set pin 4
0x50000018 C   FIELD 05w01 BS5: Port x set pin 5
0x50000018 C   FIELD 06w01 BS6: Port x set pin 6
0x50000018 C   FIELD 07w01 BS7: Port x set pin 7
0x50000018 C   FIELD 08w01 BS8: Port x set pin 8
0x50000018 C   FIELD 09w01 BS9: Port x set pin 9
0x50000018 C   FIELD 10w01 BS10: Port x set pin 10
0x50000018 C   FIELD 11w01 BS11: Port x set pin 11
0x50000018 C   FIELD 12w01 BS12: Port x set pin 12
0x50000018 C   FIELD 13w01 BS13: Port x set pin 13
0x50000018 C   FIELD 14w01 BS14: Port x set pin 14
0x50000018 C   FIELD 15w01 BS15: Port x set pin 15
0x50000018 C   FIELD 16w01 BR0: Port x reset pin 0
0x50000018 C   FIELD 17w01 BR1: Port x reset pin 1
0x50000018 C   FIELD 18w01 BR2: Port x reset pin 2
0x50000018 C   FIELD 19w01 BR3: Port x reset pin 3
0x50000018 C   FIELD 20w01 BR4: Port x reset pin 4
0x50000018 C   FIELD 21w01 BR5: Port x reset pin 5
0x50000018 C   FIELD 22w01 BR6: Port x reset pin 6
0x50000018 C   FIELD 23w01 BR7: Port x reset pin 7
0x50000018 C   FIELD 24w01 BR8: Port x reset pin 8
0x50000018 C   FIELD 25w01 BR9: Port x reset pin 9
0x50000018 C   FIELD 26w01 BR10: Port x reset pin 10
0x50000018 C   FIELD 27w01 BR11: Port x reset pin 11
0x50000018 C   FIELD 28w01 BR12: Port x reset pin 12
0x50000018 C   FIELD 29w01 BR13: Port x reset pin 13
0x50000018 C   FIELD 30w01 BR14: Port x reset pin 14
0x50000018 C   FIELD 31w01 BR15: Port x reset pin 15
0x5000001C B  REGISTER LCKR (rw): GPIO port configuration lock register
0x5000001C C   FIELD 00w01 LCK0: Port x lock pin 0
0x5000001C C   FIELD 01w01 LCK1: Port x lock pin 1
0x5000001C C   FIELD 02w01 LCK2: Port x lock pin 2
0x5000001C C   FIELD 03w01 LCK3: Port x lock pin 3
0x5000001C C   FIELD 04w01 LCK4: Port x lock pin 4
0x5000001C C   FIELD 05w01 LCK5: Port x lock pin 5
0x5000001C C   FIELD 06w01 LCK6: Port x lock pin 6
0x5000001C C   FIELD 07w01 LCK7: Port x lock pin 7
0x5000001C C   FIELD 08w01 LCK8: Port x lock pin 8
0x5000001C C   FIELD 09w01 LCK9: Port x lock pin 9
0x5000001C C   FIELD 10w01 LCK10: Port x lock pin 10
0x5000001C C   FIELD 11w01 LCK11: Port x lock pin 11
0x5000001C C   FIELD 12w01 LCK12: Port x lock pin 12
0x5000001C C   FIELD 13w01 LCK13: Port x lock pin 13
0x5000001C C   FIELD 14w01 LCK14: Port x lock pin 14
0x5000001C C   FIELD 15w01 LCK15: Port x lock pin 15
0x5000001C C   FIELD 16w01 LCKK: Port x lock bit y (y= 0..15)
0x50000020 B  REGISTER AFRL (rw): GPIO alternate function low register
0x50000020 C   FIELD 00w04 AFREL0: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 04w04 AFREL1: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 08w04 AFREL2: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 12w04 AFREL3: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 16w04 AFREL4: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 20w04 AFREL5: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 24w04 AFREL6: Alternate function selection for port x bit y (y = 0..7)
0x50000020 C   FIELD 28w04 AFREL7: Alternate function selection for port x bit y (y = 0..7)
0x50000024 B  REGISTER AFRH (rw): GPIO alternate function high register
0x50000024 C   FIELD 00w04 AFREL8 (=GPIOA.AFRL.AFR%s): Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 04w04 AFREL9 (=GPIOA.AFRL.AFR%s): Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 08w04 AFREL10 (=GPIOA.AFRL.AFR%s): Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 12w04 AFREL11 (=GPIOA.AFRL.AFR%s): Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 16w04 AFREL12 (=GPIOA.AFRL.AFR%s): Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 20w04 AFREL13 (=GPIOA.AFRL.AFR%s): Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 24w04 AFREL14 (=GPIOA.AFRL.AFR%s): Alternate function selection for port x bit y (y = 8..15)
0x50000024 C   FIELD 28w04 AFREL15 (=GPIOA.AFRL.AFR%s): Alternate function selection for port x bit y (y = 8..15)
0x50000028 B  REGISTER BRR (wo): port bit reset register
0x50000028 C   FIELD 00w01 BR0: Port x reset pin 0
0x50000028 C   FIELD 01w01 BR1: Port x reset pin 1
0x50000028 C   FIELD 02w01 BR2: Port x reset pin 2
0x50000028 C   FIELD 03w01 BR3: Port x reset pin 3
0x50000028 C   FIELD 04w01 BR4: Port x reset pin 4
0x50000028 C   FIELD 05w01 BR5: Port x reset pin 5
0x50000028 C   FIELD 06w01 BR6: Port x reset pin 6
0x50000028 C   FIELD 07w01 BR7: Port x reset pin 7
0x50000028 C   FIELD 08w01 BR8: Port x reset pin 8
0x50000028 C   FIELD 09w01 BR9: Port x reset pin 9
0x50000028 C   FIELD 10w01 BR10: Port x reset pin 10
0x50000028 C   FIELD 11w01 BR11: Port x reset pin 11
0x50000028 C   FIELD 12w01 BR12: Port x reset pin 12
0x50000028 C   FIELD 13w01 BR13: Port x reset pin 13
0x50000028 C   FIELD 14w01 BR14: Port x reset pin 14
0x50000028 C   FIELD 15w01 BR15: Port x reset pin 15
0x50000400 A PERIPHERAL GPIOB
0x50000400 B  REGISTER MODER (rw): GPIO port mode register
0x50000400 C   FIELD 00w02 MODER0 (=GPIOA.MODER.MODER%s): Port x configuration pin 0
0x50000400 C   FIELD 02w02 MODER1 (=GPIOA.MODER.MODER%s): Port x configuration pin 1
0x50000400 C   FIELD 04w02 MODER2 (=GPIOA.MODER.MODER%s): Port x configuration pin 2
0x50000400 C   FIELD 06w02 MODER3 (=GPIOA.MODER.MODER%s): Port x configuration pin 3
0x50000400 C   FIELD 08w02 MODER4 (=GPIOA.MODER.MODER%s): Port x configuration pin 4
0x50000400 C   FIELD 10w02 MODER5 (=GPIOA.MODER.MODER%s): Port x configuration pin 5
0x50000400 C   FIELD 12w02 MODER6 (=GPIOA.MODER.MODER%s): Port x configuration pin 6
0x50000400 C   FIELD 14w02 MODER7 (=GPIOA.MODER.MODER%s): Port x configuration pin 7
0x50000400 C   FIELD 16w02 MODER8 (=GPIOA.MODER.MODER%s): Port x configuration pin 8
0x50000400 C   FIELD 18w02 MODER9 (=GPIOA.MODER.MODER%s): Port x configuration pin 9
0x50000400 C   FIELD 20w02 MODER10 (=GPIOA.MODER.MODER%s): Port x configuration pin 10
0x50000400 C   FIELD 22w02 MODER11 (=GPIOA.MODER.MODER%s): Port x configuration pin 11
0x50000400 C   FIELD 24w02 MODER12 (=GPIOA.MODER.MODER%s): Port x configuration pin 12
0x50000400 C   FIELD 26w02 MODER13 (=GPIOA.MODER.MODER%s): Port x configuration pin 13
0x50000400 C   FIELD 28w02 MODER14 (=GPIOA.MODER.MODER%s): Port x configuration pin 14
0x50000400 C   FIELD 30w02 MODER15 (=GPIOA.MODER.MODER%s): Port x configuration pin 15
0x50000404 B  REGISTER OTYPER (=GPIOA.OTYPER): GPIO port output type register
0x50000408 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50000408 C   FIELD 00w02 OSPEEDR0 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 0
0x50000408 C   FIELD 02w02 OSPEEDR1 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 1
0x50000408 C   FIELD 04w02 OSPEEDR2 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 2
0x50000408 C   FIELD 06w02 OSPEEDR3 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 3
0x50000408 C   FIELD 08w02 OSPEEDR4 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 4
0x50000408 C   FIELD 10w02 OSPEEDR5 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 5
0x50000408 C   FIELD 12w02 OSPEEDR6 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 6
0x50000408 C   FIELD 14w02 OSPEEDR7 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 7
0x50000408 C   FIELD 16w02 OSPEEDR8 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 8
0x50000408 C   FIELD 18w02 OSPEEDR9 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 9
0x50000408 C   FIELD 20w02 OSPEEDR10 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 10
0x50000408 C   FIELD 22w02 OSPEEDR11 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 11
0x50000408 C   FIELD 24w02 OSPEEDR12 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 12
0x50000408 C   FIELD 26w02 OSPEEDR13 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 13
0x50000408 C   FIELD 28w02 OSPEEDR14 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 14
0x50000408 C   FIELD 30w02 OSPEEDR15 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 15
0x5000040C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x5000040C C   FIELD 00w02 PUPDR0 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 0
0x5000040C C   FIELD 02w02 PUPDR1 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 1
0x5000040C C   FIELD 04w02 PUPDR2 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 2
0x5000040C C   FIELD 06w02 PUPDR3 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 3
0x5000040C C   FIELD 08w02 PUPDR4 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 4
0x5000040C C   FIELD 10w02 PUPDR5 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 5
0x5000040C C   FIELD 12w02 PUPDR6 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 6
0x5000040C C   FIELD 14w02 PUPDR7 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 7
0x5000040C C   FIELD 16w02 PUPDR8 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 8
0x5000040C C   FIELD 18w02 PUPDR9 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 9
0x5000040C C   FIELD 20w02 PUPDR10 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 10
0x5000040C C   FIELD 22w02 PUPDR11 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 11
0x5000040C C   FIELD 24w02 PUPDR12 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 12
0x5000040C C   FIELD 26w02 PUPDR13 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 13
0x5000040C C   FIELD 28w02 PUPDR14 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 14
0x5000040C C   FIELD 30w02 PUPDR15 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 15
0x50000410 B  REGISTER IDR (=GPIOA.IDR): GPIO port input data register
0x50000414 B  REGISTER ODR (=GPIOA.ODR): GPIO port output data register
0x50000418 B  REGISTER BSRR (=GPIOA.BSRR): GPIO port bit set/reset register
0x5000041C B  REGISTER LCKR (=GPIOA.LCKR): GPIO port configuration lock register
0x50000420 B  REGISTER AFRL (=GPIOA.AFRL): GPIO alternate function low register
0x50000424 B  REGISTER AFRH (=GPIOA.AFRH): GPIO alternate function high register
0x50000428 B  REGISTER BRR (=GPIOA.BRR): port bit reset register
0x50000800 A PERIPHERAL GPIOC
0x50000800 B  REGISTER MODER (rw): GPIO port mode register
0x50000800 C   FIELD 00w02 MODER0 (=GPIOA.MODER.MODER%s): Port x configuration pin 0
0x50000800 C   FIELD 02w02 MODER1 (=GPIOA.MODER.MODER%s): Port x configuration pin 1
0x50000800 C   FIELD 04w02 MODER2 (=GPIOA.MODER.MODER%s): Port x configuration pin 2
0x50000800 C   FIELD 06w02 MODER3 (=GPIOA.MODER.MODER%s): Port x configuration pin 3
0x50000800 C   FIELD 08w02 MODER4 (=GPIOA.MODER.MODER%s): Port x configuration pin 4
0x50000800 C   FIELD 10w02 MODER5 (=GPIOA.MODER.MODER%s): Port x configuration pin 5
0x50000800 C   FIELD 12w02 MODER6 (=GPIOA.MODER.MODER%s): Port x configuration pin 6
0x50000800 C   FIELD 14w02 MODER7 (=GPIOA.MODER.MODER%s): Port x configuration pin 7
0x50000800 C   FIELD 16w02 MODER8 (=GPIOA.MODER.MODER%s): Port x configuration pin 8
0x50000800 C   FIELD 18w02 MODER9 (=GPIOA.MODER.MODER%s): Port x configuration pin 9
0x50000800 C   FIELD 20w02 MODER10 (=GPIOA.MODER.MODER%s): Port x configuration pin 10
0x50000800 C   FIELD 22w02 MODER11 (=GPIOA.MODER.MODER%s): Port x configuration pin 11
0x50000800 C   FIELD 24w02 MODER12 (=GPIOA.MODER.MODER%s): Port x configuration pin 12
0x50000800 C   FIELD 26w02 MODER13 (=GPIOA.MODER.MODER%s): Port x configuration pin 13
0x50000800 C   FIELD 28w02 MODER14 (=GPIOA.MODER.MODER%s): Port x configuration pin 14
0x50000800 C   FIELD 30w02 MODER15 (=GPIOA.MODER.MODER%s): Port x configuration pin 15
0x50000804 B  REGISTER OTYPER (=GPIOA.OTYPER): GPIO port output type register
0x50000808 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50000808 C   FIELD 00w02 OSPEEDR0 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 0
0x50000808 C   FIELD 02w02 OSPEEDR1 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 1
0x50000808 C   FIELD 04w02 OSPEEDR2 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 2
0x50000808 C   FIELD 06w02 OSPEEDR3 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 3
0x50000808 C   FIELD 08w02 OSPEEDR4 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 4
0x50000808 C   FIELD 10w02 OSPEEDR5 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 5
0x50000808 C   FIELD 12w02 OSPEEDR6 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 6
0x50000808 C   FIELD 14w02 OSPEEDR7 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 7
0x50000808 C   FIELD 16w02 OSPEEDR8 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 8
0x50000808 C   FIELD 18w02 OSPEEDR9 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 9
0x50000808 C   FIELD 20w02 OSPEEDR10 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 10
0x50000808 C   FIELD 22w02 OSPEEDR11 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 11
0x50000808 C   FIELD 24w02 OSPEEDR12 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 12
0x50000808 C   FIELD 26w02 OSPEEDR13 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 13
0x50000808 C   FIELD 28w02 OSPEEDR14 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 14
0x50000808 C   FIELD 30w02 OSPEEDR15 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 15
0x5000080C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x5000080C C   FIELD 00w02 PUPDR0 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 0
0x5000080C C   FIELD 02w02 PUPDR1 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 1
0x5000080C C   FIELD 04w02 PUPDR2 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 2
0x5000080C C   FIELD 06w02 PUPDR3 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 3
0x5000080C C   FIELD 08w02 PUPDR4 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 4
0x5000080C C   FIELD 10w02 PUPDR5 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 5
0x5000080C C   FIELD 12w02 PUPDR6 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 6
0x5000080C C   FIELD 14w02 PUPDR7 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 7
0x5000080C C   FIELD 16w02 PUPDR8 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 8
0x5000080C C   FIELD 18w02 PUPDR9 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 9
0x5000080C C   FIELD 20w02 PUPDR10 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 10
0x5000080C C   FIELD 22w02 PUPDR11 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 11
0x5000080C C   FIELD 24w02 PUPDR12 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 12
0x5000080C C   FIELD 26w02 PUPDR13 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 13
0x5000080C C   FIELD 28w02 PUPDR14 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 14
0x5000080C C   FIELD 30w02 PUPDR15 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 15
0x50000810 B  REGISTER IDR (=GPIOA.IDR): GPIO port input data register
0x50000814 B  REGISTER ODR (=GPIOA.ODR): GPIO port output data register
0x50000818 B  REGISTER BSRR (=GPIOA.BSRR): GPIO port bit set/reset register
0x5000081C B  REGISTER LCKR (=GPIOA.LCKR): GPIO port configuration lock register
0x50000820 B  REGISTER AFRL (=GPIOA.AFRL): GPIO alternate function low register
0x50000824 B  REGISTER AFRH (=GPIOA.AFRH): GPIO alternate function high register
0x50000828 B  REGISTER BRR (=GPIOA.BRR): port bit reset register
0x50000C00 A PERIPHERAL GPIOD
0x50000C00 B  REGISTER MODER (rw): GPIO port mode register
0x50000C00 C   FIELD 00w02 MODER0 (=GPIOA.MODER.MODER%s): Port x configuration pin 0
0x50000C00 C   FIELD 02w02 MODER1 (=GPIOA.MODER.MODER%s): Port x configuration pin 1
0x50000C00 C   FIELD 04w02 MODER2 (=GPIOA.MODER.MODER%s): Port x configuration pin 2
0x50000C00 C   FIELD 06w02 MODER3 (=GPIOA.MODER.MODER%s): Port x configuration pin 3
0x50000C00 C   FIELD 08w02 MODER4 (=GPIOA.MODER.MODER%s): Port x configuration pin 4
0x50000C00 C   FIELD 10w02 MODER5 (=GPIOA.MODER.MODER%s): Port x configuration pin 5
0x50000C00 C   FIELD 12w02 MODER6 (=GPIOA.MODER.MODER%s): Port x configuration pin 6
0x50000C00 C   FIELD 14w02 MODER7 (=GPIOA.MODER.MODER%s): Port x configuration pin 7
0x50000C00 C   FIELD 16w02 MODER8 (=GPIOA.MODER.MODER%s): Port x configuration pin 8
0x50000C00 C   FIELD 18w02 MODER9 (=GPIOA.MODER.MODER%s): Port x configuration pin 9
0x50000C00 C   FIELD 20w02 MODER10 (=GPIOA.MODER.MODER%s): Port x configuration pin 10
0x50000C00 C   FIELD 22w02 MODER11 (=GPIOA.MODER.MODER%s): Port x configuration pin 11
0x50000C00 C   FIELD 24w02 MODER12 (=GPIOA.MODER.MODER%s): Port x configuration pin 12
0x50000C00 C   FIELD 26w02 MODER13 (=GPIOA.MODER.MODER%s): Port x configuration pin 13
0x50000C00 C   FIELD 28w02 MODER14 (=GPIOA.MODER.MODER%s): Port x configuration pin 14
0x50000C00 C   FIELD 30w02 MODER15 (=GPIOA.MODER.MODER%s): Port x configuration pin 15
0x50000C04 B  REGISTER OTYPER (=GPIOA.OTYPER): GPIO port output type register
0x50000C08 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50000C08 C   FIELD 00w02 OSPEEDR0 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 0
0x50000C08 C   FIELD 02w02 OSPEEDR1 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 1
0x50000C08 C   FIELD 04w02 OSPEEDR2 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 2
0x50000C08 C   FIELD 06w02 OSPEEDR3 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 3
0x50000C08 C   FIELD 08w02 OSPEEDR4 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 4
0x50000C08 C   FIELD 10w02 OSPEEDR5 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 5
0x50000C08 C   FIELD 12w02 OSPEEDR6 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 6
0x50000C08 C   FIELD 14w02 OSPEEDR7 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 7
0x50000C08 C   FIELD 16w02 OSPEEDR8 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 8
0x50000C08 C   FIELD 18w02 OSPEEDR9 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 9
0x50000C08 C   FIELD 20w02 OSPEEDR10 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 10
0x50000C08 C   FIELD 22w02 OSPEEDR11 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 11
0x50000C08 C   FIELD 24w02 OSPEEDR12 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 12
0x50000C08 C   FIELD 26w02 OSPEEDR13 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 13
0x50000C08 C   FIELD 28w02 OSPEEDR14 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 14
0x50000C08 C   FIELD 30w02 OSPEEDR15 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 15
0x50000C0C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x50000C0C C   FIELD 00w02 PUPDR0 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 0
0x50000C0C C   FIELD 02w02 PUPDR1 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 1
0x50000C0C C   FIELD 04w02 PUPDR2 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 2
0x50000C0C C   FIELD 06w02 PUPDR3 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 3
0x50000C0C C   FIELD 08w02 PUPDR4 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 4
0x50000C0C C   FIELD 10w02 PUPDR5 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 5
0x50000C0C C   FIELD 12w02 PUPDR6 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 6
0x50000C0C C   FIELD 14w02 PUPDR7 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 7
0x50000C0C C   FIELD 16w02 PUPDR8 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 8
0x50000C0C C   FIELD 18w02 PUPDR9 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 9
0x50000C0C C   FIELD 20w02 PUPDR10 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 10
0x50000C0C C   FIELD 22w02 PUPDR11 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 11
0x50000C0C C   FIELD 24w02 PUPDR12 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 12
0x50000C0C C   FIELD 26w02 PUPDR13 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 13
0x50000C0C C   FIELD 28w02 PUPDR14 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 14
0x50000C0C C   FIELD 30w02 PUPDR15 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 15
0x50000C10 B  REGISTER IDR (=GPIOA.IDR): GPIO port input data register
0x50000C14 B  REGISTER ODR (=GPIOA.ODR): GPIO port output data register
0x50000C18 B  REGISTER BSRR (=GPIOA.BSRR): GPIO port bit set/reset register
0x50000C1C B  REGISTER LCKR (=GPIOA.LCKR): GPIO port configuration lock register
0x50000C20 B  REGISTER AFRL (=GPIOA.AFRL): GPIO alternate function low register
0x50000C24 B  REGISTER AFRH (=GPIOA.AFRH): GPIO alternate function high register
0x50000C28 B  REGISTER BRR (=GPIOA.BRR): port bit reset register
0x50001000 A PERIPHERAL GPIOE
0x50001000 B  REGISTER MODER (rw): GPIO port mode register
0x50001000 C   FIELD 00w02 MODER0 (=GPIOA.MODER.MODER%s): Port x configuration pin 0
0x50001000 C   FIELD 02w02 MODER1 (=GPIOA.MODER.MODER%s): Port x configuration pin 1
0x50001000 C   FIELD 04w02 MODER2 (=GPIOA.MODER.MODER%s): Port x configuration pin 2
0x50001000 C   FIELD 06w02 MODER3 (=GPIOA.MODER.MODER%s): Port x configuration pin 3
0x50001000 C   FIELD 08w02 MODER4 (=GPIOA.MODER.MODER%s): Port x configuration pin 4
0x50001000 C   FIELD 10w02 MODER5 (=GPIOA.MODER.MODER%s): Port x configuration pin 5
0x50001000 C   FIELD 12w02 MODER6 (=GPIOA.MODER.MODER%s): Port x configuration pin 6
0x50001000 C   FIELD 14w02 MODER7 (=GPIOA.MODER.MODER%s): Port x configuration pin 7
0x50001000 C   FIELD 16w02 MODER8 (=GPIOA.MODER.MODER%s): Port x configuration pin 8
0x50001000 C   FIELD 18w02 MODER9 (=GPIOA.MODER.MODER%s): Port x configuration pin 9
0x50001000 C   FIELD 20w02 MODER10 (=GPIOA.MODER.MODER%s): Port x configuration pin 10
0x50001000 C   FIELD 22w02 MODER11 (=GPIOA.MODER.MODER%s): Port x configuration pin 11
0x50001000 C   FIELD 24w02 MODER12 (=GPIOA.MODER.MODER%s): Port x configuration pin 12
0x50001000 C   FIELD 26w02 MODER13 (=GPIOA.MODER.MODER%s): Port x configuration pin 13
0x50001000 C   FIELD 28w02 MODER14 (=GPIOA.MODER.MODER%s): Port x configuration pin 14
0x50001000 C   FIELD 30w02 MODER15 (=GPIOA.MODER.MODER%s): Port x configuration pin 15
0x50001004 B  REGISTER OTYPER (=GPIOA.OTYPER): GPIO port output type register
0x50001008 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50001008 C   FIELD 00w02 OSPEEDR0 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 0
0x50001008 C   FIELD 02w02 OSPEEDR1 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 1
0x50001008 C   FIELD 04w02 OSPEEDR2 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 2
0x50001008 C   FIELD 06w02 OSPEEDR3 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 3
0x50001008 C   FIELD 08w02 OSPEEDR4 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 4
0x50001008 C   FIELD 10w02 OSPEEDR5 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 5
0x50001008 C   FIELD 12w02 OSPEEDR6 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 6
0x50001008 C   FIELD 14w02 OSPEEDR7 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 7
0x50001008 C   FIELD 16w02 OSPEEDR8 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 8
0x50001008 C   FIELD 18w02 OSPEEDR9 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 9
0x50001008 C   FIELD 20w02 OSPEEDR10 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 10
0x50001008 C   FIELD 22w02 OSPEEDR11 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 11
0x50001008 C   FIELD 24w02 OSPEEDR12 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 12
0x50001008 C   FIELD 26w02 OSPEEDR13 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 13
0x50001008 C   FIELD 28w02 OSPEEDR14 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 14
0x50001008 C   FIELD 30w02 OSPEEDR15 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 15
0x5000100C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x5000100C C   FIELD 00w02 PUPDR0 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 0
0x5000100C C   FIELD 02w02 PUPDR1 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 1
0x5000100C C   FIELD 04w02 PUPDR2 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 2
0x5000100C C   FIELD 06w02 PUPDR3 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 3
0x5000100C C   FIELD 08w02 PUPDR4 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 4
0x5000100C C   FIELD 10w02 PUPDR5 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 5
0x5000100C C   FIELD 12w02 PUPDR6 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 6
0x5000100C C   FIELD 14w02 PUPDR7 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 7
0x5000100C C   FIELD 16w02 PUPDR8 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 8
0x5000100C C   FIELD 18w02 PUPDR9 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 9
0x5000100C C   FIELD 20w02 PUPDR10 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 10
0x5000100C C   FIELD 22w02 PUPDR11 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 11
0x5000100C C   FIELD 24w02 PUPDR12 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 12
0x5000100C C   FIELD 26w02 PUPDR13 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 13
0x5000100C C   FIELD 28w02 PUPDR14 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 14
0x5000100C C   FIELD 30w02 PUPDR15 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 15
0x50001010 B  REGISTER IDR (=GPIOA.IDR): GPIO port input data register
0x50001014 B  REGISTER ODR (=GPIOA.ODR): GPIO port output data register
0x50001018 B  REGISTER BSRR (=GPIOA.BSRR): GPIO port bit set/reset register
0x5000101C B  REGISTER LCKR (=GPIOA.LCKR): GPIO port configuration lock register
0x50001020 B  REGISTER AFRL (=GPIOA.AFRL): GPIO alternate function low register
0x50001024 B  REGISTER AFRH (=GPIOA.AFRH): GPIO alternate function high register
0x50001028 B  REGISTER BRR (=GPIOA.BRR): port bit reset register
0x50001400 A PERIPHERAL GPIOF
0x50001400 B  REGISTER MODER (rw): GPIO port mode register
0x50001400 C   FIELD 00w02 MODER0 (=GPIOA.MODER.MODER%s): Port x configuration pin 0
0x50001400 C   FIELD 02w02 MODER1 (=GPIOA.MODER.MODER%s): Port x configuration pin 1
0x50001400 C   FIELD 04w02 MODER2 (=GPIOA.MODER.MODER%s): Port x configuration pin 2
0x50001400 C   FIELD 06w02 MODER3 (=GPIOA.MODER.MODER%s): Port x configuration pin 3
0x50001400 C   FIELD 08w02 MODER4 (=GPIOA.MODER.MODER%s): Port x configuration pin 4
0x50001400 C   FIELD 10w02 MODER5 (=GPIOA.MODER.MODER%s): Port x configuration pin 5
0x50001400 C   FIELD 12w02 MODER6 (=GPIOA.MODER.MODER%s): Port x configuration pin 6
0x50001400 C   FIELD 14w02 MODER7 (=GPIOA.MODER.MODER%s): Port x configuration pin 7
0x50001400 C   FIELD 16w02 MODER8 (=GPIOA.MODER.MODER%s): Port x configuration pin 8
0x50001400 C   FIELD 18w02 MODER9 (=GPIOA.MODER.MODER%s): Port x configuration pin 9
0x50001400 C   FIELD 20w02 MODER10 (=GPIOA.MODER.MODER%s): Port x configuration pin 10
0x50001400 C   FIELD 22w02 MODER11 (=GPIOA.MODER.MODER%s): Port x configuration pin 11
0x50001400 C   FIELD 24w02 MODER12 (=GPIOA.MODER.MODER%s): Port x configuration pin 12
0x50001400 C   FIELD 26w02 MODER13 (=GPIOA.MODER.MODER%s): Port x configuration pin 13
0x50001400 C   FIELD 28w02 MODER14 (=GPIOA.MODER.MODER%s): Port x configuration pin 14
0x50001400 C   FIELD 30w02 MODER15 (=GPIOA.MODER.MODER%s): Port x configuration pin 15
0x50001404 B  REGISTER OTYPER (=GPIOA.OTYPER): GPIO port output type register
0x50001408 B  REGISTER OSPEEDR (rw): GPIO port output speed register
0x50001408 C   FIELD 00w02 OSPEEDR0 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 0
0x50001408 C   FIELD 02w02 OSPEEDR1 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 1
0x50001408 C   FIELD 04w02 OSPEEDR2 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 2
0x50001408 C   FIELD 06w02 OSPEEDR3 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 3
0x50001408 C   FIELD 08w02 OSPEEDR4 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 4
0x50001408 C   FIELD 10w02 OSPEEDR5 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 5
0x50001408 C   FIELD 12w02 OSPEEDR6 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 6
0x50001408 C   FIELD 14w02 OSPEEDR7 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 7
0x50001408 C   FIELD 16w02 OSPEEDR8 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 8
0x50001408 C   FIELD 18w02 OSPEEDR9 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 9
0x50001408 C   FIELD 20w02 OSPEEDR10 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 10
0x50001408 C   FIELD 22w02 OSPEEDR11 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 11
0x50001408 C   FIELD 24w02 OSPEEDR12 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 12
0x50001408 C   FIELD 26w02 OSPEEDR13 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 13
0x50001408 C   FIELD 28w02 OSPEEDR14 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 14
0x50001408 C   FIELD 30w02 OSPEEDR15 (=GPIOA.OSPEEDR.OSPEEDR%s): Port x configuration pin 15
0x5000140C B  REGISTER PUPDR (rw): GPIO port pull-up/pull-down register
0x5000140C C   FIELD 00w02 PUPDR0 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 0
0x5000140C C   FIELD 02w02 PUPDR1 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 1
0x5000140C C   FIELD 04w02 PUPDR2 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 2
0x5000140C C   FIELD 06w02 PUPDR3 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 3
0x5000140C C   FIELD 08w02 PUPDR4 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 4
0x5000140C C   FIELD 10w02 PUPDR5 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 5
0x5000140C C   FIELD 12w02 PUPDR6 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 6
0x5000140C C   FIELD 14w02 PUPDR7 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 7
0x5000140C C   FIELD 16w02 PUPDR8 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 8
0x5000140C C   FIELD 18w02 PUPDR9 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 9
0x5000140C C   FIELD 20w02 PUPDR10 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 10
0x5000140C C   FIELD 22w02 PUPDR11 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 11
0x5000140C C   FIELD 24w02 PUPDR12 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 12
0x5000140C C   FIELD 26w02 PUPDR13 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 13
0x5000140C C   FIELD 28w02 PUPDR14 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 14
0x5000140C C   FIELD 30w02 PUPDR15 (=GPIOA.PUPDR.PUPDR%s): Port x configuration pin 15
0x50001410 B  REGISTER IDR (=GPIOA.IDR): GPIO port input data register
0x50001414 B  REGISTER ODR (=GPIOA.ODR): GPIO port output data register
0x50001418 B  REGISTER BSRR (=GPIOA.BSRR): GPIO port bit set/reset register
0x5000141C B  REGISTER LCKR (=GPIOA.LCKR): GPIO port configuration lock register
0x50001420 B  REGISTER AFRL (=GPIOA.AFRL): GPIO alternate function low register
0x50001424 B  REGISTER AFRH (=GPIOA.AFRH): GPIO alternate function high register
0x50001428 B  REGISTER BRR (=GPIOA.BRR): port bit reset register
INTERRUPT 000: WWDG (WWDG): Window watchdog interrupt
INTERRUPT 001: PVD (EXTI): Power voltage detector interrupt
INTERRUPT 001: PVD (PWR): Power voltage detector interrupt
INTERRUPT 002: RTC_TAMP (RTC): RTC and TAMP interrupts
INTERRUPT 003: FLASH (FLASH): Flash global interrupt
INTERRUPT 004: RCC (RCC): RCC global interrupt
INTERRUPT 005: EXTI0_1 (EXTI): EXTI line 0 & 1 interrupt
INTERRUPT 006: EXTI2_3 (EXTI): EXTI line 2 & 3 interrupt
INTERRUPT 007: EXTI4_15 (EXTI): EXTI line 4 to 15 interrupt
INTERRUPT 009: DMA1_Channel1 (DMA1): DMA channel 1 interrupt
INTERRUPT 010: DMA1_Channel2_3 (DMA1): DMA channel 2 and 3 interrupts
INTERRUPT 011: DMA1_Channel4_5_6_7_DMAMUX (DMA1): interrupts for DMA1 channels 4-7 and DMAMUX
INTERRUPT 013: TIM1_BRK_UP_TRG_COM (TIM1): TIM1 break, update, trigger and commutation interrupts
INTERRUPT 014: TIM1_CC (TIM1): TIM1 Capture Compare interrupt
INTERRUPT 015: TIM2 (TIM2): TIM2 global interrupt
INTERRUPT 016: TIM3 (TIM3): TIM3 global interrupt
INTERRUPT 017: TIM6_DAC_LPTIM1 (DAC): TIM6, LPTIM1 and DAC global interrupt
INTERRUPT 018: TIM7 (TIM7): TIM7 + LPTIM2 global interrupt
INTERRUPT 019: TIM14 (TIM14): TIM14 global interrupt
INTERRUPT 020: TIM15 (TIM15): Timer 15 global interrupt
INTERRUPT 021: TIM16 (TIM16): TIM16 global interrupt
INTERRUPT 022: TIM17 (TIM17): TIM17 global interrupt
INTERRUPT 023: I2C1 (I2C1): I2C1 global interrupt
INTERRUPT 024: I2C2 (I2C2): I2C2 global interrupt
INTERRUPT 025: SPI1 (SPI1): SPI1 gloabl interrupt
INTERRUPT 026: SPI2_SPI3 (SPI2): SPI2 gloabl interrupt
INTERRUPT 027: USART1 (USART1): USART1 global interrupt
INTERRUPT 028: USART2 (USART2): USART2 global interrupt
INTERRUPT 030: CEC (HDMI_CEC): CEC global interrupt
INTERRUPT 031: AES_RNG (AES): AES and RNG global interrupts