From 89600ec0708cc9cb66c72c1b2c4b6b3a4827c7cc Mon Sep 17 00:00:00 2001 From: Torkel Danielsson Date: Thu, 23 Apr 2020 13:59:53 +0900 Subject: [PATCH] cargo fmt --- examples/adc-dma-circ.rs | 9 +- examples/adc-dma-rx.rs | 8 +- examples/adc.rs | 6 +- examples/adc_temperature.rs | 14 ++-- examples/blinky.rs | 6 +- examples/blinky_generic.rs | 8 +- examples/blinky_rtc.rs | 11 +-- examples/blinky_timer_irq.rs | 7 +- examples/delay.rs | 6 +- examples/exti.rs | 25 +++--- examples/hello.rs | 2 +- examples/itm.rs | 2 +- examples/led.rs | 23 ++++-- examples/mfrc522.rs | 8 +- examples/nojtag.rs | 5 +- examples/panics.rs | 2 +- examples/pwm.rs | 16 ++-- examples/pwm_custom.rs | 11 +-- examples/pwm_input.rs | 20 ++--- examples/rtc.rs | 6 +- examples/serial-dma-circ.rs | 6 +- examples/serial-dma-peek.rs | 4 +- examples/serial-dma-rx.rs | 4 +- examples/serial-dma-tx.rs | 4 +- examples/serial-fmt.rs | 4 +- examples/serial.rs | 7 +- examples/serial_config.rs | 5 +- examples/spi-dma.rs | 29 +++---- examples/timer-interrupt-rtfm.rs | 17 ++-- examples/usb_serial_rtfm.rs | 5 +- src/adc.rs | 136 +++++++++++++++++-------------- src/afio.rs | 21 +++-- src/dma.rs | 11 +-- src/gpio.rs | 7 +- src/i2c.rs | 17 ++-- src/lib.rs | 14 ++-- src/prelude.rs | 6 +- src/pwm.rs | 48 +++++++---- src/pwm_input.rs | 30 +++---- src/rcc.rs | 36 +++----- src/rtc.rs | 64 +++++++-------- src/serial.rs | 23 ++---- src/spi.rs | 15 ++-- src/time.rs | 2 +- src/timer.rs | 103 +++++++---------------- src/watchdog.rs | 5 +- 46 files changed, 364 insertions(+), 454 deletions(-) diff --git a/examples/adc-dma-circ.rs b/examples/adc-dma-circ.rs index 6ccc658f..dc3a3a4a 100644 --- a/examples/adc-dma-circ.rs +++ b/examples/adc-dma-circ.rs @@ -7,13 +7,8 @@ use panic_halt as _; use cortex_m::{asm, singleton}; -use stm32f1xx_hal::{ - prelude::*, - pac, - adc, - dma::Half, -}; use cortex_m_rt::entry; +use stm32f1xx_hal::{adc, dma::Half, pac, prelude::*}; #[entry] fn main() -> ! { @@ -58,4 +53,4 @@ fn main() -> ! { asm::bkpt(); loop {} -} \ No newline at end of file +} diff --git a/examples/adc-dma-rx.rs b/examples/adc-dma-rx.rs index 272b0fc7..be62425e 100644 --- a/examples/adc-dma-rx.rs +++ b/examples/adc-dma-rx.rs @@ -7,12 +7,8 @@ use panic_halt as _; use cortex_m::{asm, singleton}; -use stm32f1xx_hal::{ - prelude::*, - pac, - adc, -}; use cortex_m_rt::entry; +use stm32f1xx_hal::{adc, pac, prelude::*}; #[entry] fn main() -> ! { @@ -48,7 +44,7 @@ fn main() -> ! { // one can call the is_done method of RxDma and only call wait after that method returns true. let (_buf, adc_dma) = adc_dma.read(buf).wait(); asm::bkpt(); - + // Consumes the AdcDma struct, restores adc configuration to previous state and returns the // Adc struct in normal mode. let (_adc1, _adc_ch0, _dma_ch1) = adc_dma.split(); diff --git a/examples/adc.rs b/examples/adc.rs index ca6e2092..3979d543 100644 --- a/examples/adc.rs +++ b/examples/adc.rs @@ -4,12 +4,8 @@ use panic_semihosting as _; -use stm32f1xx_hal::{ - prelude::*, - pac, - adc, -}; use cortex_m_rt::entry; +use stm32f1xx_hal::{adc, pac, prelude::*}; use cortex_m_semihosting::hprintln; diff --git a/examples/adc_temperature.rs b/examples/adc_temperature.rs index 4aeec956..2099ecad 100644 --- a/examples/adc_temperature.rs +++ b/examples/adc_temperature.rs @@ -4,12 +4,8 @@ use panic_semihosting as _; -use stm32f1xx_hal::{ - prelude::*, - pac, - adc, -}; use cortex_m_rt::entry; +use stm32f1xx_hal::{adc, pac, prelude::*}; use cortex_m_semihosting::hprintln; @@ -20,7 +16,13 @@ fn main() -> ! { let mut flash = p.FLASH.constrain(); let mut rcc = p.RCC.constrain(); - let clocks = rcc.cfgr.use_hse(8.mhz()).sysclk(56.mhz()).pclk1(28.mhz()).adcclk(14.mhz()).freeze(&mut flash.acr); + let clocks = rcc + .cfgr + .use_hse(8.mhz()) + .sysclk(56.mhz()) + .pclk1(28.mhz()) + .adcclk(14.mhz()) + .freeze(&mut flash.acr); hprintln!("sysclk freq: {}", clocks.sysclk().0).unwrap(); hprintln!("adc freq: {}", clocks.adcclk().0).unwrap(); diff --git a/examples/blinky.rs b/examples/blinky.rs index 7b224e79..9fae270c 100644 --- a/examples/blinky.rs +++ b/examples/blinky.rs @@ -13,13 +13,9 @@ use panic_halt as _; use nb::block; -use stm32f1xx_hal::{ - prelude::*, - pac, - timer::Timer, -}; use cortex_m_rt::entry; use embedded_hal::digital::v2::OutputPin; +use stm32f1xx_hal::{pac, prelude::*, timer::Timer}; #[entry] fn main() -> ! { diff --git a/examples/blinky_generic.rs b/examples/blinky_generic.rs index 8d9d5c0a..5809d4be 100644 --- a/examples/blinky_generic.rs +++ b/examples/blinky_generic.rs @@ -8,13 +8,9 @@ use panic_halt as _; use nb::block; -use stm32f1xx_hal::{ - prelude::*, - pac, - timer::Timer, -}; use cortex_m_rt::entry; use embedded_hal::digital::v2::OutputPin; +use stm32f1xx_hal::{pac, prelude::*, timer::Timer}; #[entry] fn main() -> ! { @@ -36,7 +32,7 @@ fn main() -> ! { // Create an array of LEDS to blink let mut leds = [ gpioc.pc13.into_push_pull_output(&mut gpioc.crh).downgrade(), - gpioa.pa1.into_push_pull_output(&mut gpioa.crl).downgrade() + gpioa.pa1.into_push_pull_output(&mut gpioa.crl).downgrade(), ]; // Wait for the timer to trigger an update and change the state of the LED diff --git a/examples/blinky_rtc.rs b/examples/blinky_rtc.rs index 08ac5ff2..0cfd52d3 100644 --- a/examples/blinky_rtc.rs +++ b/examples/blinky_rtc.rs @@ -12,15 +12,11 @@ use panic_halt as _; -use stm32f1xx_hal::{ - prelude::*, - pac, - rtc::Rtc, -}; +use stm32f1xx_hal::{pac, prelude::*, rtc::Rtc}; -use nb::block; use cortex_m_rt::entry; use embedded_hal::digital::v2::OutputPin; +use nb::block; #[entry] fn main() -> ! { @@ -49,8 +45,7 @@ fn main() -> ! { if led_on { led.set_low().unwrap(); led_on = false; - } - else { + } else { led.set_high().unwrap(); led_on = true; } diff --git a/examples/blinky_timer_irq.rs b/examples/blinky_timer_irq.rs index d17d1db9..03835dfe 100644 --- a/examples/blinky_timer_irq.rs +++ b/examples/blinky_timer_irq.rs @@ -14,16 +14,13 @@ use stm32f1xx_hal as hal; use crate::hal::{ gpio::*, - prelude::*, pac::{interrupt, Interrupt, Peripherals, TIM2}, + prelude::*, timer::*, }; use core::cell::RefCell; -use cortex_m::{ - asm::wfi, - interrupt::Mutex, - peripheral::Peripherals as c_m_Peripherals}; +use cortex_m::{asm::wfi, interrupt::Mutex, peripheral::Peripherals as c_m_Peripherals}; use cortex_m_rt::entry; // NOTE You can uncomment 'hprintln' here and in the code below for a bit more diff --git a/examples/delay.rs b/examples/delay.rs index 100600c6..5e454328 100644 --- a/examples/delay.rs +++ b/examples/delay.rs @@ -6,13 +6,9 @@ use panic_halt as _; -use stm32f1xx_hal::{ - prelude::*, - pac, - delay::Delay, -}; use cortex_m_rt::entry; use embedded_hal::digital::v2::OutputPin; +use stm32f1xx_hal::{delay::Delay, pac, prelude::*}; #[entry] fn main() -> ! { diff --git a/examples/exti.rs b/examples/exti.rs index b20c0de9..c96dce8a 100644 --- a/examples/exti.rs +++ b/examples/exti.rs @@ -8,26 +8,25 @@ use panic_halt as _; -use stm32f1xx_hal::{ - prelude::*, - pac -}; +use core::mem::MaybeUninit; use cortex_m_rt::entry; use pac::interrupt; -use core::mem::MaybeUninit; use stm32f1xx_hal::gpio::*; +use stm32f1xx_hal::{pac, prelude::*}; // These two are owned by the ISR. main() may only access them during the initialization phase, // where the interrupt is not yet enabled (i.e. no concurrent accesses can occur). // After enabling the interrupt, main() may not have any references to these objects any more. // For the sake of minimalism, we do not use RTFM here, which would be the better way. -static mut LED : MaybeUninit>> = MaybeUninit::uninit(); -static mut INT_PIN : MaybeUninit>> = MaybeUninit::uninit(); +static mut LED: MaybeUninit>> = + MaybeUninit::uninit(); +static mut INT_PIN: MaybeUninit>> = + MaybeUninit::uninit(); #[interrupt] fn EXTI9_5() { - let led = unsafe { &mut *LED.as_mut_ptr()}; - let int_pin = unsafe { &mut *INT_PIN.as_mut_ptr()}; + let led = unsafe { &mut *LED.as_mut_ptr() }; + let int_pin = unsafe { &mut *INT_PIN.as_mut_ptr() }; if int_pin.check_interrupt() { led.toggle().unwrap(); @@ -50,17 +49,19 @@ fn main() -> ! { let mut gpioc = p.GPIOC.split(&mut rcc.apb2); let mut afio = p.AFIO.constrain(&mut rcc.apb2); - let led = unsafe { &mut *LED.as_mut_ptr()}; + let led = unsafe { &mut *LED.as_mut_ptr() }; *led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); - let int_pin = unsafe { &mut *INT_PIN.as_mut_ptr()}; + let int_pin = unsafe { &mut *INT_PIN.as_mut_ptr() }; *int_pin = gpioa.pa7.into_floating_input(&mut gpioa.crl); int_pin.make_interrupt_source(&mut afio); int_pin.trigger_on_edge(&p.EXTI, Edge::RISING_FALLING); int_pin.enable_interrupt(&p.EXTI); } // initialization ends here - unsafe { pac::NVIC::unmask(pac::Interrupt::EXTI9_5); } + unsafe { + pac::NVIC::unmask(pac::Interrupt::EXTI9_5); + } loop {} } diff --git a/examples/hello.rs b/examples/hello.rs index ea2e6907..4418456d 100644 --- a/examples/hello.rs +++ b/examples/hello.rs @@ -6,8 +6,8 @@ use panic_semihosting as _; -use stm32f1xx_hal as _; use cortex_m_semihosting::hprintln; +use stm32f1xx_hal as _; use cortex_m_rt::entry; diff --git a/examples/itm.rs b/examples/itm.rs index 661edd5a..a097ae8a 100644 --- a/examples/itm.rs +++ b/examples/itm.rs @@ -2,8 +2,8 @@ #![no_main] #![no_std] -use panic_itm as _; use cortex_m::iprintln; +use panic_itm as _; use stm32f1xx_hal as _; use cortex_m_rt::entry; diff --git a/examples/led.rs b/examples/led.rs index 0ebf2603..a8e443d0 100644 --- a/examples/led.rs +++ b/examples/led.rs @@ -15,12 +15,9 @@ use panic_halt as _; -use stm32f1xx_hal::{ - prelude::*, - pac, -}; use cortex_m_rt::entry; use embedded_hal::digital::v2::OutputPin; +use stm32f1xx_hal::{pac, prelude::*}; #[entry] fn main() -> ! { @@ -30,13 +27,25 @@ fn main() -> ! { let mut gpioc = p.GPIOC.split(&mut rcc.apb2); #[cfg(feature = "stm32f100")] - gpioc.pc9.into_push_pull_output(&mut gpioc.crh).set_high().unwrap(); + gpioc + .pc9 + .into_push_pull_output(&mut gpioc.crh) + .set_high() + .unwrap(); #[cfg(feature = "stm32f101")] - gpioc.pc9.into_push_pull_output(&mut gpioc.crh).set_high().unwrap(); + gpioc + .pc9 + .into_push_pull_output(&mut gpioc.crh) + .set_high() + .unwrap(); #[cfg(feature = "stm32f103")] - gpioc.pc13.into_push_pull_output(&mut gpioc.crh).set_low().unwrap(); + gpioc + .pc13 + .into_push_pull_output(&mut gpioc.crh) + .set_low() + .unwrap(); loop {} } diff --git a/examples/mfrc522.rs b/examples/mfrc522.rs index 7ae2ed04..2edaad9a 100644 --- a/examples/mfrc522.rs +++ b/examples/mfrc522.rs @@ -6,14 +6,10 @@ use panic_itm as _; use cortex_m::iprintln; -use stm32f1xx_hal::{ - prelude::*, - pac, - spi::Spi, -}; -use mfrc522::Mfrc522; use cortex_m_rt::entry; use embedded_hal::digital::{v1_compat::OldOutputPin, v2::OutputPin}; +use mfrc522::Mfrc522; +use stm32f1xx_hal::{pac, prelude::*, spi::Spi}; #[entry] fn main() -> ! { diff --git a/examples/nojtag.rs b/examples/nojtag.rs index 6024f03e..2342411f 100644 --- a/examples/nojtag.rs +++ b/examples/nojtag.rs @@ -6,11 +6,8 @@ use panic_halt as _; -use stm32f1xx_hal::{ - prelude::*, - pac, -}; use cortex_m_rt::entry; +use stm32f1xx_hal::{pac, prelude::*}; #[entry] fn main() -> ! { diff --git a/examples/panics.rs b/examples/panics.rs index b9f0efd0..27241e48 100644 --- a/examples/panics.rs +++ b/examples/panics.rs @@ -6,8 +6,8 @@ use panic_semihosting as _; //use panic_itm as _; -use stm32f1xx_hal as _; use cortex_m_semihosting::hprintln; +use stm32f1xx_hal as _; use cortex_m_rt::{entry, exception, ExceptionFrame}; diff --git a/examples/pwm.rs b/examples/pwm.rs index f224033e..ac46a8d8 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -7,14 +7,14 @@ use panic_halt as _; use cortex_m::asm; +use cortex_m_rt::entry; use stm32f1xx_hal::{ - prelude::*, pac, - timer::{Tim2NoRemap, Timer}, + prelude::*, + pwm::Channel, time::U32Ext, - pwm::Channel + timer::{Tim2NoRemap, Timer}, }; -use cortex_m_rt::entry; #[entry] fn main() -> ! { @@ -50,8 +50,11 @@ fn main() -> ! { // let c3 = gpiob.pb8.into_alternate_push_pull(&mut gpiob.crh); // let c4 = gpiob.pb9.into_alternate_push_pull(&mut gpiob.crh); - let mut pwm = Timer::tim2(p.TIM2, &clocks, &mut rcc.apb1) - .pwm::(pins, &mut afio.mapr, 1.khz()); + let mut pwm = Timer::tim2(p.TIM2, &clocks, &mut rcc.apb1).pwm::( + pins, + &mut afio.mapr, + 1.khz(), + ); //// Operations affecting all defined channels on the Timer @@ -85,7 +88,6 @@ fn main() -> ! { asm::bkpt(); - // Extract the PwmChannel for C3 let mut pwm_channel = pwm.split().2; diff --git a/examples/pwm_custom.rs b/examples/pwm_custom.rs index 46b13a54..d48f058b 100644 --- a/examples/pwm_custom.rs +++ b/examples/pwm_custom.rs @@ -7,11 +7,7 @@ use panic_halt as _; use cortex_m::asm; -use stm32f1xx_hal::{ - pac, - prelude::*, - timer::Timer, -}; +use stm32f1xx_hal::{pac, prelude::*, timer::Timer}; use cortex_m_rt::entry; @@ -33,14 +29,13 @@ fn main() -> ! { let p0 = pb4.into_alternate_push_pull(&mut gpiob.crl); let p1 = gpiob.pb5.into_alternate_push_pull(&mut gpiob.crl); - let pwm = Timer::tim3(p.TIM3, &clocks, &mut rcc.apb1) - .pwm((p0, p1), &mut afio.mapr, 1.khz()); + let pwm = Timer::tim3(p.TIM3, &clocks, &mut rcc.apb1).pwm((p0, p1), &mut afio.mapr, 1.khz()); let max = pwm.get_max_duty(); let mut pwm_channels = pwm.split(); - // Enable the individual channels + // Enable the individual channels pwm_channels.0.enable(); pwm_channels.1.enable(); diff --git a/examples/pwm_input.rs b/examples/pwm_input.rs index e4c323ed..622a7ab0 100644 --- a/examples/pwm_input.rs +++ b/examples/pwm_input.rs @@ -6,13 +6,8 @@ use panic_halt as _; -use stm32f1xx_hal::{ - prelude::*, - pac, - pwm_input::*, - timer::Timer, -}; use cortex_m_rt::entry; +use stm32f1xx_hal::{pac, prelude::*, pwm_input::*, timer::Timer}; #[entry] fn main() -> ! { @@ -32,13 +27,12 @@ fn main() -> ! { let (_pa15, _pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4); let pb5 = gpiob.pb5; - let pwm_input = Timer::tim3(p.TIM3, &clocks, &mut rcc.apb1) - .pwm_input( - (pb4, pb5), - &mut afio.mapr, - &mut dbg, - Configuration::Frequency(10.khz()), - ); + let pwm_input = Timer::tim3(p.TIM3, &clocks, &mut rcc.apb1).pwm_input( + (pb4, pb5), + &mut afio.mapr, + &mut dbg, + Configuration::Frequency(10.khz()), + ); loop { let _freq = pwm_input diff --git a/examples/rtc.rs b/examples/rtc.rs index 538bfb75..0f2b3e9e 100644 --- a/examples/rtc.rs +++ b/examples/rtc.rs @@ -8,12 +8,8 @@ use panic_semihosting as _; use cortex_m_semihosting::hprintln; -use stm32f1xx_hal::{ - prelude::*, - pac, - rtc::Rtc, -}; use cortex_m_rt::entry; +use stm32f1xx_hal::{pac, prelude::*, rtc::Rtc}; #[entry] fn main() -> ! { diff --git a/examples/serial-dma-circ.rs b/examples/serial-dma-circ.rs index e5d26a84..956bb970 100644 --- a/examples/serial-dma-circ.rs +++ b/examples/serial-dma-circ.rs @@ -8,13 +8,13 @@ use panic_halt as _; use cortex_m::{asm, singleton}; +use cortex_m_rt::entry; use stm32f1xx_hal::{ - prelude::*, + dma::Half, pac, + prelude::*, serial::{Config, Serial}, - dma::Half, }; -use cortex_m_rt::entry; #[entry] fn main() -> ! { diff --git a/examples/serial-dma-peek.rs b/examples/serial-dma-peek.rs index 9043345b..a4590636 100644 --- a/examples/serial-dma-peek.rs +++ b/examples/serial-dma-peek.rs @@ -8,12 +8,12 @@ use panic_halt as _; use cortex_m::{asm, singleton}; +use cortex_m_rt::entry; use stm32f1xx_hal::{ - prelude::*, pac, + prelude::*, serial::{Config, Serial}, }; -use cortex_m_rt::entry; #[entry] fn main() -> ! { diff --git a/examples/serial-dma-rx.rs b/examples/serial-dma-rx.rs index 926711f2..1fb33610 100644 --- a/examples/serial-dma-rx.rs +++ b/examples/serial-dma-rx.rs @@ -8,12 +8,12 @@ use panic_halt as _; use cortex_m::{asm, singleton}; +use cortex_m_rt::entry; use stm32f1xx_hal::{ - prelude::*, pac, + prelude::*, serial::{Config, Serial}, }; -use cortex_m_rt::entry; #[entry] fn main() -> ! { diff --git a/examples/serial-dma-tx.rs b/examples/serial-dma-tx.rs index 9cea5a97..98c5fc2d 100644 --- a/examples/serial-dma-tx.rs +++ b/examples/serial-dma-tx.rs @@ -8,12 +8,12 @@ use panic_halt as _; use cortex_m::asm; +use cortex_m_rt::entry; use stm32f1xx_hal::{ - prelude::*, pac, + prelude::*, serial::{Config, Serial}, }; -use cortex_m_rt::entry; #[entry] fn main() -> ! { diff --git a/examples/serial-fmt.rs b/examples/serial-fmt.rs index 5d22228d..76f8582f 100644 --- a/examples/serial-fmt.rs +++ b/examples/serial-fmt.rs @@ -9,12 +9,12 @@ use panic_halt as _; +use cortex_m_rt::entry; use stm32f1xx_hal::{ - prelude::*, pac, + prelude::*, serial::{Config, Serial}, }; -use cortex_m_rt::entry; use core::fmt::Write; diff --git a/examples/serial.rs b/examples/serial.rs index e64fa0fc..c4944baf 100644 --- a/examples/serial.rs +++ b/examples/serial.rs @@ -12,12 +12,12 @@ use cortex_m::asm; use nb::block; +use cortex_m_rt::entry; use stm32f1xx_hal::{ - prelude::*, pac, + prelude::*, serial::{Config, Serial}, }; -use cortex_m_rt::entry; #[entry] fn main() -> ! { @@ -68,7 +68,6 @@ fn main() -> ! { &mut rcc.apb1, ); - // Loopback test. Write `X` and wait until the write is successful. let sent = b'X'; block!(serial.write(sent)).ok(); @@ -82,7 +81,6 @@ fn main() -> ! { // Trigger a breakpoint to allow us to inspect the values asm::bkpt(); - // You can also split the serial struct into a receiving and a transmitting part let (mut tx, mut rx) = serial.split(); let sent = b'Y'; @@ -91,6 +89,5 @@ fn main() -> ! { assert_eq!(received, sent); asm::bkpt(); - loop {} } diff --git a/examples/serial_config.rs b/examples/serial_config.rs index cac7853d..27ae3417 100644 --- a/examples/serial_config.rs +++ b/examples/serial_config.rs @@ -10,12 +10,12 @@ use panic_halt as _; use nb::block; +use cortex_m_rt::entry; use stm32f1xx_hal::{ - prelude::*, pac, + prelude::*, serial::{self, Serial}, }; -use cortex_m_rt::entry; #[entry] fn main() -> ! { @@ -76,6 +76,5 @@ fn main() -> ! { block!(tx.write(sent)).ok(); block!(tx.write(sent)).ok(); - loop {} } diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index c200cd92..d22c8cde 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -4,15 +4,14 @@ /** Transmits data over an SPI port using DMA */ - use panic_halt as _; +use cortex_m_rt::entry; use stm32f1xx_hal::{ - prelude::*, pac, - spi::{Spi, Mode, Polarity, Phase}, + prelude::*, + spi::{Mode, Phase, Polarity, Spi}, }; -use cortex_m_rt::entry; #[entry] fn main() -> ! { @@ -32,23 +31,16 @@ fn main() -> ! { let mut gpiob = dp.GPIOB.split(&mut rcc.apb2); let pins = ( - gpiob.pb13.into_alternate_push_pull(&mut gpiob.crh), - gpiob.pb14.into_floating_input(&mut gpiob.crh), - gpiob.pb15.into_alternate_push_pull(&mut gpiob.crh), - ); + gpiob.pb13.into_alternate_push_pull(&mut gpiob.crh), + gpiob.pb14.into_floating_input(&mut gpiob.crh), + gpiob.pb15.into_alternate_push_pull(&mut gpiob.crh), + ); let spi_mode = Mode { polarity: Polarity::IdleLow, - phase: Phase::CaptureOnFirstTransition + phase: Phase::CaptureOnFirstTransition, }; - let spi = Spi::spi2( - dp.SPI2, - pins, - spi_mode, - 100.khz(), - clocks, - &mut rcc.apb1 - ); + let spi = Spi::spi2(dp.SPI2, pins, spi_mode, 100.khz(), clocks, &mut rcc.apb1); // Set up the DMA device let dma = dp.DMA1.split(&mut rcc.ahb); @@ -63,6 +55,5 @@ fn main() -> ! { // and the data being sent anb those things are returned by transfer.wait let (_buffer, _spi_dma) = transfer.wait(); - loop { - } + loop {} } diff --git a/examples/timer-interrupt-rtfm.rs b/examples/timer-interrupt-rtfm.rs index 3080cb7c..d4a9892e 100644 --- a/examples/timer-interrupt-rtfm.rs +++ b/examples/timer-interrupt-rtfm.rs @@ -13,17 +13,16 @@ use panic_halt as _; use rtfm::app; +use embedded_hal::digital::v2::OutputPin; use stm32f1xx_hal::{ - prelude::*, + gpio::{gpioc::PC13, Output, PushPull, State}, pac, - timer::{ Timer, CountDownTimer, Event }, - gpio::{ gpioc::PC13, State, Output, PushPull }, + prelude::*, + timer::{CountDownTimer, Event, Timer}, }; -use embedded_hal::digital::v2::OutputPin; #[app(device = stm32f1xx_hal::pac, peripherals = true)] const APP: () = { - struct Resources { led: PC13>, timer_handler: CountDownTimer, @@ -48,10 +47,12 @@ const APP: () = { // Configure gpio C pin 13 as a push-pull output. The `crh` register is passed to the // function in order to configure the port. For pins 0-7, crl should be passed instead - let led = gpioc.pc13.into_push_pull_output_with_state(&mut gpioc.crh, State::High); + let led = gpioc + .pc13 + .into_push_pull_output_with_state(&mut gpioc.crh, State::High); // Configure the syst timer to trigger an update every second and enables interrupt - let mut timer = Timer::tim1(cx.device.TIM1, &clocks, &mut rcc.apb2) - .start_count_down(1.hz()); + let mut timer = + Timer::tim1(cx.device.TIM1, &clocks, &mut rcc.apb2).start_count_down(1.hz()); timer.listen(Event::Update); // Init the static resources to use them later through RTFM diff --git a/examples/usb_serial_rtfm.rs b/examples/usb_serial_rtfm.rs index 62e36f72..dc8f9053 100644 --- a/examples/usb_serial_rtfm.rs +++ b/examples/usb_serial_rtfm.rs @@ -68,10 +68,7 @@ const APP: () = { .device_class(USB_CLASS_CDC) .build(); - init::LateResources { - usb_dev, - serial, - } + init::LateResources { usb_dev, serial } } #[task(binds = USB_HP_CAN_TX, resources = [usb_dev, serial])] diff --git a/src/adc.rs b/src/adc.rs index 099a6ca7..f6cd520b 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,22 +1,19 @@ //! # API for the Analog to Digital converter -use embedded_hal::adc::{Channel, OneShot}; use core::marker::PhantomData; +use embedded_hal::adc::{Channel, OneShot}; +use crate::dma::{dma1::C1, CircBuffer, Receive, RxDma, Transfer, TransferPayload, W}; use crate::gpio::Analog; use crate::gpio::{gpioa, gpiob, gpioc}; -use crate::rcc::{APB2, Clocks, Enable, Reset}; -use crate::dma::{Receive, TransferPayload, dma1::C1, CircBuffer, Transfer, W, RxDma}; +use crate::rcc::{Clocks, Enable, Reset, APB2}; use core::sync::atomic::{self, Ordering}; use cortex_m::asm::delay; use crate::pac::ADC1; #[cfg(feature = "stm32f103")] use crate::pac::ADC2; -#[cfg(all( - feature = "stm32f103", - feature = "high", -))] +#[cfg(all(feature = "stm32f103", feature = "high",))] use crate::pac::ADC3; /// Continuous mode @@ -135,9 +132,7 @@ adc_pins!(ADC1, gpioc::PC5 => 15_u8, ); -#[cfg(any( - feature = "stm32f103", -))] +#[cfg(any(feature = "stm32f103",))] adc_pins!(ADC2, gpioa::PA0 => 0_u8, gpioa::PA1 => 1_u8, @@ -471,13 +466,13 @@ impl Adc { // so use the following approximate settings // to support all ADC frequencies let sample_time = match self.clocks.adcclk().0 { - 0 ..= 1_200_000 => SampleTime::T_1, - 1_200_001 ..= 1_500_000 => SampleTime::T_7, - 1_500_001 ..= 2_400_000 => SampleTime::T_13, - 2_400_001 ..= 3_100_000 => SampleTime::T_28, - 3_100_001 ..= 4_000_000 => SampleTime::T_41, - 4_000_001 ..= 5_000_000 => SampleTime::T_55, - 5_000_001 ..= 14_000_000 => SampleTime::T_71, + 0..=1_200_000 => SampleTime::T_1, + 1_200_001..=1_500_000 => SampleTime::T_7, + 1_500_001..=2_400_000 => SampleTime::T_13, + 2_400_001..=3_100_000 => SampleTime::T_28, + 3_100_001..=4_000_000 => SampleTime::T_41, + 4_000_001..=5_000_000 => SampleTime::T_55, + 5_000_001..=14_000_000 => SampleTime::T_71, _ => SampleTime::T_239, }; @@ -513,10 +508,7 @@ adc_hal! { ADC2: (adc2), } -#[cfg(all( - feature = "stm32f103", - feature = "high", -))] +#[cfg(all(feature = "stm32f103", feature = "high",))] adc_hal! { ADC3: (adc3), } @@ -533,7 +525,7 @@ pub trait ChannelTimeSequence { /// ADC Set a Regular Channel Conversion Sequence /// /// Define a sequence of channels to be converted as a regular group. - fn set_regular_sequence (&mut self, channels: &[u8]); + fn set_regular_sequence(&mut self, channels: &[u8]); } /// Set channel sequence and sample times for custom pins @@ -593,7 +585,9 @@ impl Adc { self.rb.cr1.modify(|_, w| w.discen().clear_bit()); self.rb.cr2.modify(|_, w| w.align().bit(self.align.into())); self.set_channel_sample_time(PIN::channel(), self.sample_time); - self.rb.sqr3.modify(|_, w| unsafe { w.sq1().bits(PIN::channel()) }); + self.rb + .sqr3 + .modify(|_, w| unsafe { w.sq1().bits(PIN::channel()) }); self.rb.cr2.modify(|_, w| w.dma().set_bit()); let payload = AdcPayload { @@ -609,24 +603,26 @@ impl Adc { pub fn with_scan_dma(mut self, pins: PINS, dma_ch: C1) -> AdcDma where - Self:SetChannels + Self: SetChannels, { - self.rb.cr2.modify(|_, w| w - .adon().clear_bit() - .dma().clear_bit() - .cont().clear_bit() - .align().bit(self.align.into()) - ); - self.rb.cr1.modify(|_, w| w - .scan().set_bit() - .discen().clear_bit() - ); + self.rb.cr2.modify(|_, w| { + w.adon() + .clear_bit() + .dma() + .clear_bit() + .cont() + .clear_bit() + .align() + .bit(self.align.into()) + }); + self.rb + .cr1 + .modify(|_, w| w.scan().set_bit().discen().clear_bit()); self.set_samples(); self.set_sequence(); - self.rb.cr2.modify(|_, w| w - .dma().set_bit() - .adon().set_bit() - ); + self.rb + .cr2 + .modify(|_, w| w.dma().set_bit().adon().set_bit()); let payload = AdcPayload { adc: self, @@ -642,12 +638,12 @@ impl Adc { impl AdcDma where - Self: TransferPayload + Self: TransferPayload, { pub fn split(mut self) -> (Adc, PINS, C1) { self.stop(); - let AdcDma {payload, channel} = self; + let AdcDma { payload, channel } = self; payload.adc.rb.cr2.modify(|_, w| w.dma().clear_bit()); payload.adc.rb.cr1.modify(|_, w| w.discen().set_bit()); @@ -657,12 +653,12 @@ where impl AdcDma where - Self: TransferPayload + Self: TransferPayload, { pub fn split(mut self) -> (Adc, PINS, C1) { self.stop(); - let AdcDma {payload, channel} = self; + let AdcDma { payload, channel } = self; payload.adc.rb.cr2.modify(|_, w| w.dma().clear_bit()); payload.adc.rb.cr1.modify(|_, w| w.discen().set_bit()); payload.adc.rb.cr1.modify(|_, w| w.scan().clear_bit()); @@ -674,24 +670,32 @@ where impl crate::dma::CircReadDma for AdcDma where Self: TransferPayload, - B: as_slice::AsMutSlice, + B: as_slice::AsMutSlice, { fn circ_read(mut self, buffer: &'static mut [B; 2]) -> CircBuffer { { let buffer = buffer[0].as_mut_slice(); - self.channel.set_peripheral_address(unsafe{ &(*ADC1::ptr()).dr as *const _ as u32 }, false); - self.channel.set_memory_address(buffer.as_ptr() as u32, true); + self.channel + .set_peripheral_address(unsafe { &(*ADC1::ptr()).dr as *const _ as u32 }, false); + self.channel + .set_memory_address(buffer.as_ptr() as u32, true); self.channel.set_transfer_length(buffer.len() * 2); atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { w - .mem2mem() .clear_bit() - .pl() .medium() - .msize() .bits16() - .psize() .bits16() - .circ() .set_bit() - .dir() .clear_bit() + self.channel.ch().cr.modify(|_, w| { + w.mem2mem() + .clear_bit() + .pl() + .medium() + .msize() + .bits16() + .psize() + .bits16() + .circ() + .set_bit() + .dir() + .clear_bit() }); } @@ -704,23 +708,31 @@ where impl crate::dma::ReadDma for AdcDma where Self: TransferPayload, - B: as_slice::AsMutSlice, + B: as_slice::AsMutSlice, { fn read(mut self, buffer: &'static mut B) -> Transfer { { let buffer = buffer.as_mut_slice(); - self.channel.set_peripheral_address(unsafe{ &(*ADC1::ptr()).dr as *const _ as u32 }, false); - self.channel.set_memory_address(buffer.as_ptr() as u32, true); + self.channel + .set_peripheral_address(unsafe { &(*ADC1::ptr()).dr as *const _ as u32 }, false); + self.channel + .set_memory_address(buffer.as_ptr() as u32, true); self.channel.set_transfer_length(buffer.len()); } atomic::compiler_fence(Ordering::Release); - self.channel.ch().cr.modify(|_, w| { w - .mem2mem() .clear_bit() - .pl() .medium() - .msize() .bits16() - .psize() .bits16() - .circ() .clear_bit() - .dir() .clear_bit() + self.channel.ch().cr.modify(|_, w| { + w.mem2mem() + .clear_bit() + .pl() + .medium() + .msize() + .bits16() + .psize() + .bits16() + .circ() + .clear_bit() + .dir() + .clear_bit() }); self.start(); diff --git a/src/afio.rs b/src/afio.rs index 1cee625b..295fca4c 100644 --- a/src/afio.rs +++ b/src/afio.rs @@ -1,14 +1,12 @@ //! # Alternate Function I/Os use crate::pac::{afio, AFIO}; -use crate::rcc::{APB2, Enable, Reset}; +use crate::rcc::{Enable, Reset, APB2}; use crate::gpio::{ - Debugger, - Input, - Floating, gpioa::PA15, gpiob::{PB3, PB4}, + Debugger, Floating, Input, }; pub trait AfioExt { @@ -22,7 +20,10 @@ impl AfioExt for AFIO { Parts { evcr: EVCR { _0: () }, - mapr: MAPR { _0: (), jtag_enabled: true }, + mapr: MAPR { + _0: (), + jtag_enabled: true, + }, exticr1: EXTICR1 { _0: () }, exticr2: EXTICR2 { _0: () }, exticr3: EXTICR3 { _0: () }, @@ -63,10 +64,12 @@ impl MAPR { } pub fn modify_mapr(&mut self, mod_fn: F) - where F: for<'w> FnOnce(&afio::mapr::R, &'w mut afio::mapr::W) -> &'w mut afio::mapr::W + where + F: for<'w> FnOnce(&afio::mapr::R, &'w mut afio::mapr::W) -> &'w mut afio::mapr::W, { - let debug_bits = if self.jtag_enabled {0b000} else {0b010}; - self.mapr().modify(unsafe{ |r, w| mod_fn(r, w).swj_cfg().bits(debug_bits) }); + let debug_bits = if self.jtag_enabled { 0b000 } else { 0b010 }; + self.mapr() + .modify(unsafe { |r, w| mod_fn(r, w).swj_cfg().bits(debug_bits) }); } /// Disables the JTAG to free up pa15, pb3 and pb4 for normal use @@ -74,7 +77,7 @@ impl MAPR { &mut self, pa15: PA15, pb3: PB3, - pb4: PB4 + pb4: PB4, ) -> ( PA15>, PB3>, diff --git a/src/dma.rs b/src/dma.rs index 80238b33..9628587d 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -482,7 +482,7 @@ pub trait Transmit { pub trait CircReadDma: Receive where - B: as_slice::AsMutSlice, + B: as_slice::AsMutSlice, Self: core::marker::Sized, { fn circ_read(self, buffer: &'static mut [B; 2]) -> CircBuffer; @@ -490,18 +490,15 @@ where pub trait ReadDma: Receive where - B: as_slice::AsMutSlice, + B: as_slice::AsMutSlice, Self: core::marker::Sized, { - fn read( - self, - buffer: &'static mut B, - ) -> Transfer; + fn read(self, buffer: &'static mut B) -> Transfer; } pub trait WriteDma: Transmit where - A: as_slice::AsSlice, + A: as_slice::AsSlice, B: Static, Self: core::marker::Sized, { diff --git a/src/gpio.rs b/src/gpio.rs index 6f2102b5..3c226ea6 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -16,9 +16,9 @@ use core::marker::PhantomData; -use crate::rcc::APB2; -use crate::pac::EXTI; use crate::afio; +use crate::pac::EXTI; +use crate::rcc::APB2; /// Extension trait to split a GPIO peripheral in independent pins and registers pub trait GpioExt { @@ -29,7 +29,6 @@ pub trait GpioExt { fn split(self, apb2: &mut APB2) -> Self::Parts; } - /// Marker trait for pin mode detection. pub trait Mode {} @@ -786,7 +785,7 @@ macro_rules! impl_pxx { } } -impl_pxx!{ +impl_pxx! { (gpioa::PAx), (gpiob::PBx), (gpioc::PCx), diff --git a/src/i2c.rs b/src/i2c.rs index f5e99444..57bd3b68 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -5,14 +5,14 @@ // https://www.st.com/content/ccc/resource/technical/document/application_note/5d/ae/a3/6f/08/69/4e/9b/CD00209826.pdf/files/CD00209826.pdf/jcr:content/translations/en.CD00209826.pdf use crate::afio::MAPR; -use crate::time::Hertz; use crate::gpio::gpiob::{PB10, PB11, PB6, PB7, PB8, PB9}; use crate::gpio::{Alternate, OpenDrain}; use crate::hal::blocking::i2c::{Read, Write, WriteRead}; +use crate::pac::{DWT, I2C1, I2C2}; +use crate::rcc::{sealed::RccBus, Clocks, Enable, GetBusFreq, Reset}; +use crate::time::Hertz; use nb::Error::{Other, WouldBlock}; use nb::{Error as NbError, Result as NbResult}; -use crate::rcc::{Clocks, Enable, Reset, sealed::RccBus, GetBusFreq}; -use crate::pac::{DWT, I2C1, I2C2}; /// I2C error #[derive(Debug, Eq, PartialEq)] @@ -51,11 +51,16 @@ pub enum Mode { impl Mode { pub fn standard>(frequency: F) -> Self { - Mode::Standard{frequency: frequency.into()} + Mode::Standard { + frequency: frequency.into(), + } } pub fn fast>(frequency: F, duty_cycle: DutyCycle) -> Self { - Mode::Fast{frequency: frequency.into(), duty_cycle} + Mode::Fast { + frequency: frequency.into(), + duty_cycle, + } } pub fn get_frequency(&self) -> Hertz { @@ -157,7 +162,7 @@ impl I2c { pins: PINS, mode: Mode, clocks: Clocks, - apb: &mut ::Bus + apb: &mut ::Bus, ) -> Self where PINS: Pins, diff --git a/src/lib.rs b/src/lib.rs index 49319bd2..68ffe174 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -31,8 +31,8 @@ //! - `stm32f101` //! - `stm32f103` //! -//! You may also need to specify the density of the device with `medium`, `high` or `xl` -//! to enable certain peripherals. Generally the density can be determined by the 2nd character +//! You may also need to specify the density of the device with `medium`, `high` or `xl` +//! to enable certain peripherals. Generally the density can be determined by the 2nd character //! after the number in the device name (i.e. For STM32F103C6U, the 6 indicates a low-density //! device) but check the datasheet or CubeMX to be sure. //! * 4, 6 => low density, no feature required @@ -40,7 +40,7 @@ //! * C, D, E => `high` feature //! * F, G => `xl` feature //! -//! +//! //! //! [cortex-m-quickstart]: https://docs.rs/cortex-m-quickstart/0.3.1 //! @@ -75,7 +75,9 @@ compile_error!("Target not found. A `--features ` is required."); all(feature = "stm32f100", feature = "stm32f103"), all(feature = "stm32f101", feature = "stm32f103"), ))] -compile_error!("Multiple targets specified. Only a single `--features ` can be specified."); +compile_error!( + "Multiple targets specified. Only a single `--features ` can be specified." +); #[cfg(feature = "device-selected")] use embedded_hal as hal; @@ -90,11 +92,11 @@ pub use stm32f1::stm32f101 as pac; pub use stm32f1::stm32f103 as pac; #[cfg(feature = "device-selected")] -#[deprecated(since="0.6.0", note="please use `pac` instead")] +#[deprecated(since = "0.6.0", note = "please use `pac` instead")] pub use crate::pac as device; #[cfg(feature = "device-selected")] -#[deprecated(since="0.6.0", note="please use `pac` instead")] +#[deprecated(since = "0.6.0", note = "please use `pac` instead")] pub use crate::pac as stm32; #[cfg(feature = "device-selected")] diff --git a/src/prelude.rs b/src/prelude.rs index a6691ab1..d94d2cea 100644 --- a/src/prelude.rs +++ b/src/prelude.rs @@ -1,6 +1,9 @@ pub use crate::adc::ChannelTimeSequence as _stm32_hal_adc_ChannelTimeSequence; pub use crate::afio::AfioExt as _stm32_hal_afio_AfioExt; +pub use crate::dma::CircReadDma as _stm32_hal_dma_CircReadDma; pub use crate::dma::DmaExt as _stm32_hal_dma_DmaExt; +pub use crate::dma::ReadDma as _stm32_hal_dma_ReadDma; +pub use crate::dma::WriteDma as _stm32_hal_dma_WriteDma; pub use crate::flash::FlashExt as _stm32_hal_flash_FlashExt; pub use crate::gpio::GpioExt as _stm32_hal_gpio_GpioExt; pub use crate::hal::adc::OneShot as _embedded_hal_adc_OneShot; @@ -8,7 +11,4 @@ pub use crate::hal::digital::v2::StatefulOutputPin as _embedded_hal_digital_Stat pub use crate::hal::digital::v2::ToggleableOutputPin as _embedded_hal_digital_ToggleableOutputPin; pub use crate::hal::prelude::*; pub use crate::rcc::RccExt as _stm32_hal_rcc_RccExt; -pub use crate::dma::CircReadDma as _stm32_hal_dma_CircReadDma; -pub use crate::dma::ReadDma as _stm32_hal_dma_ReadDma; -pub use crate::dma::WriteDma as _stm32_hal_dma_WriteDma; pub use crate::time::U32Ext as _stm32_hal_time_U32Ext; diff --git a/src/pwm.rs b/src/pwm.rs index a3c93f13..c8c4de3c 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -53,8 +53,8 @@ ``` */ +use core::marker::Copy; use core::marker::PhantomData; -use core::marker::{Copy}; use core::mem; use crate::hal; @@ -137,7 +137,12 @@ pins_impl!( #[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))] impl Timer { - pub fn pwm(self, _pins: PINS, mapr: &mut MAPR, freq: T) -> Pwm + pub fn pwm( + self, + _pins: PINS, + mapr: &mut MAPR, + freq: T, + ) -> Pwm where REMAP: Remap, PINS: Pins, @@ -155,7 +160,12 @@ impl Timer { } impl Timer { - pub fn pwm(self, _pins: PINS, mapr: &mut MAPR, freq: T) -> Pwm + pub fn pwm( + self, + _pins: PINS, + mapr: &mut MAPR, + freq: T, + ) -> Pwm where REMAP: Remap, PINS: Pins, @@ -169,7 +179,12 @@ impl Timer { } impl Timer { - pub fn pwm(self, _pins: PINS, mapr: &mut MAPR, freq: T) -> Pwm + pub fn pwm( + self, + _pins: PINS, + mapr: &mut MAPR, + freq: T, + ) -> Pwm where REMAP: Remap, PINS: Pins, @@ -184,7 +199,12 @@ impl Timer { #[cfg(feature = "medium")] impl Timer { - pub fn pwm(self, _pins: PINS, mapr: &mut MAPR, freq: T) -> Pwm + pub fn pwm( + self, + _pins: PINS, + mapr: &mut MAPR, + freq: T, + ) -> Pwm where REMAP: Remap, PINS: Pins, @@ -200,7 +220,7 @@ impl Timer { pub struct Pwm where REMAP: Remap, - PINS: Pins + PINS: Pins, { clk: Hertz, _pins: PhantomData<(TIM, REMAP, P, PINS)>, @@ -209,7 +229,7 @@ where impl Pwm where REMAP: Remap, - PINS: Pins + PINS: Pins, { pub fn split(self) -> PINS::Channels { unsafe { mem::MaybeUninit::uninit().assume_init() } @@ -286,18 +306,18 @@ macro_rules! hal { _pins: PhantomData } } - + /* - The following implemention of the embedded_hal::Pwm uses Hertz as a time type. This was choosen - because of the timescales of operations being on the order of nanoseconds and not being able to + The following implemention of the embedded_hal::Pwm uses Hertz as a time type. This was choosen + because of the timescales of operations being on the order of nanoseconds and not being able to efficently represent a float on the hardware. It might be possible to change the time type to - a different time based using such as the nanosecond. The issue with doing so is that the max + a different time based using such as the nanosecond. The issue with doing so is that the max delay would then be at just a little over 2 seconds because of the 32 bit depth of the number. - Using milliseconds is also an option, however, using this as a base unit means that only there + Using milliseconds is also an option, however, using this as a base unit means that only there could be resolution issues when trying to get a specific value, because of the integer nature. - To find a middle ground, the Hertz type is used as a base here and the Into trait has been - defined for several base time units. This will allow for calling the set_period method with + To find a middle ground, the Hertz type is used as a base here and the Into trait has been + defined for several base time units. This will allow for calling the set_period method with something that is natural to both the MCU and the end user. */ impl hal::Pwm for Pwm<$TIMX, REMAP, P, PINS> where diff --git a/src/pwm_input.rs b/src/pwm_input.rs index 91d12855..ab3bb7f8 100644 --- a/src/pwm_input.rs +++ b/src/pwm_input.rs @@ -5,31 +5,29 @@ use core::marker::PhantomData; use core::mem; use crate::pac::DBGMCU as DBG; -#[cfg(any( - feature = "stm32f100", - feature = "stm32f103", - feature = "stm32f105", -))] +#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))] use crate::pac::TIM1; -use crate::pac::{TIM2, TIM3}; #[cfg(feature = "medium")] use crate::pac::TIM4; +use crate::pac::{TIM2, TIM3}; use crate::afio::MAPR; use crate::gpio::{self, Floating, Input}; -use crate::rcc::{Clocks, GetBusFreq, sealed::RccBus}; +use crate::rcc::{sealed::RccBus, Clocks, GetBusFreq}; use crate::time::Hertz; use crate::timer::Timer; pub trait Pins {} -use crate::timer::sealed::{Remap, Ch1, Ch2}; +use crate::timer::sealed::{Ch1, Ch2, Remap}; impl Pins for (P1, P2) where REMAP: Remap, P1: Ch1 + gpio::Mode>, - P2: Ch2 + gpio::Mode> {} + P2: Ch2 + gpio::Mode>, +{ +} /// PWM Input pub struct PwmInput { @@ -84,11 +82,7 @@ where RawValues { arr: u16, presc: u16 }, } -#[cfg(any( - feature = "stm32f100", - feature = "stm32f103", - feature = "stm32f105", -))] +#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))] impl Timer { pub fn pwm_input( mut self, @@ -259,7 +253,7 @@ macro_rules! hal { ReadMode::WaitForNextCapture => self.wait_for_capture(), _ => (), } - + let presc = unsafe { (*$TIMX::ptr()).psc.read().bits() as u16}; let ccr1 = unsafe { (*$TIMX::ptr()).ccr1.read().bits() as u16}; @@ -313,11 +307,7 @@ macro_rules! hal { } } -#[cfg(any( - feature = "stm32f100", - feature = "stm32f103", - feature = "stm32f105", -))] +#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))] hal! { TIM1: (tim1), } diff --git a/src/rcc.rs b/src/rcc.rs index f5795088..38c8d6d0 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -2,15 +2,14 @@ use core::cmp; +use crate::pac::{rcc, PWR, RCC}; use cast::u32; -use crate::pac::{rcc, RCC, PWR}; use crate::flash::ACR; use crate::time::Hertz; use crate::backup_domain::BackupDomain; - /// Extension trait that constrains the `RCC` peripheral pub trait RccExt { /// Constrains the `RCC` peripheral so it plays nicely with the other abstractions @@ -67,7 +66,6 @@ pub struct APB1 { _0: (), } - impl APB1 { pub(crate) fn enr(&mut self) -> &rcc::APB1ENR { // NOTE(unsafe) this proxy grants exclusive access to this register @@ -80,13 +78,10 @@ impl APB1 { } } - impl APB1 { /// Set power interface clock (PWREN) bit in RCC_APB1ENR pub fn set_pwren(&mut self) { - self.enr().modify(|_r, w| { - w.pwren().set_bit() - }) + self.enr().modify(|_r, w| w.pwren().set_bit()) } } @@ -297,12 +292,12 @@ impl CFGR { if let Some(pllmul_bits) = pllmul_bits { // enable PLL and wait for it to be ready - rcc.cfgr.modify(|_, w| + rcc.cfgr.modify(|_, w| { w.pllmul() .bits(pllmul_bits) .pllsrc() .bit(if self.hse.is_some() { true } else { false }) - ); + }); rcc.cr.modify(|_, w| w.pllon().set_bit()); @@ -334,10 +329,7 @@ impl CFGR { }) }); - #[cfg(any( - feature = "stm32f100", - feature = "stm32f101" - ))] + #[cfg(any(feature = "stm32f100", feature = "stm32f101"))] rcc.cfgr.modify(|_, w| unsafe { w.adcpre().bits(apre_bits); w.ppre2() @@ -373,28 +365,20 @@ impl CFGR { } pub struct BKP { - _0: () + _0: (), } impl BKP { /// Enables write access to the registers in the backup domain pub fn constrain(self, bkp: crate::pac::BKP, apb1: &mut APB1, pwr: &mut PWR) -> BackupDomain { // Enable the backup interface by setting PWREN and BKPEN - apb1.enr().modify(|_r, w| { - w - .bkpen().set_bit() - .pwren().set_bit() - }); + apb1.enr() + .modify(|_r, w| w.bkpen().set_bit().pwren().set_bit()); // Enable access to the backup registers - pwr.cr.modify(|_r, w| { - w - .dbp().set_bit() - }); + pwr.cr.modify(|_r, w| w.dbp().set_bit()); - BackupDomain { - _regs: bkp, - } + BackupDomain { _regs: bkp } } } diff --git a/src/rtc.rs b/src/rtc.rs index 7d3f4cfa..7e80a777 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -12,18 +12,17 @@ See examples/rtc.rs and examples/blinky_rtc.rs for usage examples. */ -use crate::pac::{RTC, RCC}; +use crate::pac::{RCC, RTC}; use crate::backup_domain::BackupDomain; use crate::time::Hertz; -use nb; use core::convert::Infallible; +use nb; // The LSE runs at at 32 768 hertz unless an external clock is provided const LSE_HERTZ: u32 = 32_768; - /** Interface to the real time clock */ @@ -37,9 +36,7 @@ impl Rtc { `Rcc.bkp.constrain()`. */ pub fn rtc(regs: RTC, bkp: &mut BackupDomain) -> Self { - let mut result = Rtc { - regs, - }; + let mut result = Rtc { regs }; Rtc::enable_rtc(bkp); @@ -62,11 +59,14 @@ impl Rtc { rcc.bdcr.modify(|_, w| { w // start the LSE oscillator - .lseon().set_bit() + .lseon() + .set_bit() // Enable the RTC - .rtcen().set_bit() + .rtcen() + .set_bit() // Set the source of the RTC to LSE - .rtcsel().lse() + .rtcsel() + .lse() }) } @@ -80,17 +80,23 @@ impl Rtc { assert!(frequency <= LSE_HERTZ / 2); let prescaler = LSE_HERTZ / frequency - 1; - self.perform_write( |s| { + self.perform_write(|s| { s.regs.prlh.write(|w| unsafe { w.bits(prescaler >> 16) }); - s.regs.prll.write(|w| unsafe { w.bits(prescaler as u16 as u32) }); + s.regs + .prll + .write(|w| unsafe { w.bits(prescaler as u16 as u32) }); }); } /// Set the current RTC counter value to the specified amount pub fn set_time(&mut self, counter_value: u32) { self.perform_write(|s| { - s.regs.cnth.write(|w| unsafe{w.bits(counter_value >> 16)}); - s.regs.cntl.write(|w| unsafe{w.bits(counter_value as u16 as u32)}); + s.regs + .cnth + .write(|w| unsafe { w.bits(counter_value >> 16) }); + s.regs + .cntl + .write(|w| unsafe { w.bits(counter_value as u16 as u32) }); }); } @@ -103,12 +109,16 @@ impl Rtc { // Set alarm time // See section 18.3.5 for explanation let alarm_value = counter_value - 1; - + // TODO: Remove this `allow` once these fields are made safe for stm32f100 - #[allow(unused_unsafe)] + #[allow(unused_unsafe)] self.perform_write(|s| { - s.regs.alrh.write(|w| unsafe{w.alrh().bits((alarm_value >> 16) as u16)}); - s.regs.alrl.write(|w| unsafe{w.alrl().bits(alarm_value as u16)}); + s.regs + .alrh + .write(|w| unsafe { w.alrh().bits((alarm_value >> 16) as u16) }); + s.regs + .alrl + .write(|w| unsafe { w.alrl().bits(alarm_value as u16) }); }); self.clear_alarm_flag(); @@ -140,30 +150,22 @@ impl Rtc { /// Enables the RTC second interrupt pub fn listen_seconds(&mut self) { - self.perform_write(|s| { - s.regs.crh.modify(|_, w| w.secie().set_bit()) - }) + self.perform_write(|s| s.regs.crh.modify(|_, w| w.secie().set_bit())) } /// Disables the RTC second interrupt pub fn unlisten_seconds(&mut self) { - self.perform_write(|s| { - s.regs.crh.modify(|_, w| w.secie().clear_bit()) - }) + self.perform_write(|s| s.regs.crh.modify(|_, w| w.secie().clear_bit())) } /// Clears the RTC second interrupt flag pub fn clear_second_flag(&mut self) { - self.perform_write(|s| { - s.regs.crl.modify(|_, w| w.secf().clear_bit()) - }) + self.perform_write(|s| s.regs.crl.modify(|_, w| w.secf().clear_bit())) } /// Clears the RTC alarm interrupt flag pub fn clear_alarm_flag(&mut self) { - self.perform_write(|s| { - s.regs.crl.modify(|_, w| w.alrf().clear_bit()) - }) + self.perform_write(|s| s.regs.crl.modify(|_, w| w.alrf().clear_bit())) } /** @@ -181,13 +183,11 @@ impl Rtc { if self.regs.crl.read().alrf().bit() == true { self.regs.crl.modify(|_, w| w.alrf().clear_bit()); Ok(()) - } - else { + } else { Err(nb::Error::WouldBlock) } } - /** The RTC registers can not be written to at any time as documented on page 485 of the manual. Performing writes using this function ensures that diff --git a/src/serial.rs b/src/serial.rs index 7d46a9d9..3f9e51d7 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -38,24 +38,24 @@ //! ``` use core::marker::PhantomData; +use core::ops::Deref; use core::ptr; use core::sync::atomic::{self, Ordering}; -use core::ops::Deref; -use nb; use crate::pac::{USART1, USART2, USART3}; use core::convert::Infallible; use embedded_hal::serial::Write; +use nb; use crate::afio::MAPR; -use crate::dma::{dma1, CircBuffer, Static, Transfer, R, W, RxDma, TxDma}; +use crate::dma::{dma1, CircBuffer, RxDma, Static, Transfer, TxDma, R, W}; use crate::gpio::gpioa::{PA10, PA2, PA3, PA9}; use crate::gpio::gpiob::{PB10, PB11, PB6, PB7}; use crate::gpio::gpioc::{PC10, PC11}; use crate::gpio::gpiod::{PD5, PD6, PD8, PD9}; use crate::gpio::{Alternate, Floating, Input, PushPull}; -use crate::rcc::{sealed::RccBus, Clocks, Enable, Reset, GetBusFreq}; -use crate::time::{U32Ext, Bps}; +use crate::rcc::{sealed::RccBus, Clocks, Enable, GetBusFreq, Reset}; +use crate::time::{Bps, U32Ext}; /// Interrupt event pub enum Event { @@ -80,7 +80,6 @@ pub enum Error { _Extensible, } - // USART REMAPPING, see: https://www.st.com/content/ccc/resource/technical/document/reference_manual/59/b9/ba/7f/11/af/43/d5/CD00171190.pdf/files/CD00171190.pdf/jcr:content/translations/en.CD00171190.pdf // Section 9.3.8 pub trait Pins { @@ -193,7 +192,7 @@ pub struct Tx { } /// Internal trait for the serial read / write logic. -trait UsartReadWrite: Deref { +trait UsartReadWrite: Deref { fn read(&self) -> nb::Result { let sr = self.sr.read(); @@ -225,9 +224,7 @@ trait UsartReadWrite: Deref { if sr.rxne().bit_is_set() { // Read the received byte // NOTE(read_volatile) see `write_volatile` below - Ok(unsafe { - ptr::read_volatile(&self.dr as *const _ as *const _) - }) + Ok(unsafe { ptr::read_volatile(&self.dr as *const _ as *const _) }) } else { Err(nb::Error::WouldBlock) } @@ -240,9 +237,7 @@ trait UsartReadWrite: Deref { if sr.txe().bit_is_set() { // NOTE(unsafe) atomic write to stateless register // NOTE(write_volatile) 8-bit write that's not possible through the svd2rust API - unsafe { - ptr::write_volatile(&self.dr as *const _ as *mut _, byte) - } + unsafe { ptr::write_volatile(&self.dr as *const _ as *mut _, byte) } Ok(()) } else { Err(nb::Error::WouldBlock) @@ -503,7 +498,7 @@ pub type Tx2 = Tx; pub type Rx3 = Rx; pub type Tx3 = Tx; -use crate::dma::{Transmit, Receive, TransferPayload}; +use crate::dma::{Receive, TransferPayload, Transmit}; macro_rules! serialdma { ($( diff --git a/src/spi.rs b/src/spi.rs index e1f888ba..d176ef39 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -35,7 +35,7 @@ use core::ptr; use nb; -pub use crate::hal::spi::{Mode, Phase, Polarity, FullDuplex}; +pub use crate::hal::spi::{FullDuplex, Mode, Phase, Polarity}; #[cfg(feature = "high")] use crate::pac::SPI3; use crate::pac::{SPI1, SPI2}; @@ -334,10 +334,11 @@ impl crate::hal::blocking::spi::transfer::Default for Spi< { } -impl crate::hal::blocking::spi::Write for Spi where - SPI: Deref +impl crate::hal::blocking::spi::Write for Spi +where + SPI: Deref, { - type Error = Error; + type Error = Error; // Implement write as per the "Transmit only procedure" page 712 // of RM0008 Rev 20. This is more than twice as fast as the @@ -362,20 +363,20 @@ impl crate::hal::blocking::spi::Write for Spi { clk: Hertz, } - pub(crate) mod sealed { pub trait Remap { type Periph; @@ -140,25 +122,16 @@ macro_rules! remap { } } -use crate::gpio::gpioa::{PA0, PA1, PA2, PA3, PA6, PA7, PA15}; -use crate::gpio::gpiob::{PB0, PB1, PB3, PB4, PB5, PB10, PB11}; +use crate::gpio::gpioa::{PA0, PA1, PA15, PA2, PA3, PA6, PA7}; +use crate::gpio::gpiob::{PB0, PB1, PB10, PB11, PB3, PB4, PB5}; use crate::gpio::gpioc::{PC6, PC7, PC8, PC9}; - -#[cfg(any( - feature = "stm32f100", - feature = "stm32f103", - feature = "stm32f105", -))] +#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))] use crate::gpio::{ - gpioa::{PA8, PA9, PA10, PA11}, - gpioe::{PE9, PE11, PE13, PE14}, + gpioa::{PA10, PA11, PA8, PA9}, + gpioe::{PE11, PE13, PE14, PE9}, }; -#[cfg(any( - feature = "stm32f100", - feature = "stm32f103", - feature = "stm32f105", -))] +#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))] remap!( Tim1NoRemap: (TIM1, 0b00, PA8, PA9, PA10, PA11), //Tim1PartialRemap: (TIM1, 0b01, PA8, PA9, PA10, PA11), @@ -170,7 +143,7 @@ remap!( Tim2PartialRemap1: (TIM2, 0b01, PA15, PB3, PA2, PA3), Tim2PartialRemap2: (TIM2, 0b10, PA0, PA1, PB10, PB11), Tim2FullRemap: (TIM2, 0b11, PA15, PB3, PB10, PB11), - + Tim3NoRemap: (TIM3, 0b00, PA6, PA7, PB0, PB1), Tim3PartialRemap: (TIM3, 0b10, PB4, PB5, PB0, PB1), Tim3FullRemap: (TIM3, 0b11, PC6, PC7, PC8, PC9), @@ -179,7 +152,7 @@ remap!( #[cfg(feature = "medium")] use crate::gpio::{ gpiob::{PB6, PB7, PB8, PB9}, - gpiod::{PD12, PD13, PD14, PD15} + gpiod::{PD12, PD13, PD14, PD15}, }; #[cfg(feature = "medium")] remap!( @@ -190,7 +163,10 @@ remap!( impl Timer { pub fn syst(mut syst: SYST, clocks: &Clocks) -> Self { syst.set_clock_source(SystClkSource::Core); - Self { tim: syst, clk: clocks.sysclk() } + Self { + tim: syst, + clk: clocks.sysclk(), + } } pub fn start_count_down(self, timeout: T) -> CountDownTimer @@ -246,8 +222,8 @@ impl CountDownTimer { /// Stops the timer pub fn stop(mut self) -> Timer { self.tim.disable_counter(); - let Self {tim, clk} = self; - Timer {tim, clk} + let Self { tim, clk } = self; + Timer { tim, clk } } /// Releases the SYST @@ -377,12 +353,12 @@ macro_rules! hal { pub fn micros_since(&self) -> u32 { let timer_clock = self.clk.0; let psc = u32(self.tim.psc.read().psc().bits()); - + // freq_divider is always bigger than 0, since (psc + 1) is always less than // timer_clock let freq_divider = u64(timer_clock / (psc + 1)); let cnt = u64(self.tim.cnt.read().cnt().bits()); - + // It is safe to make this cast, because the maximum timer period in this HAL is // 1s (1Hz), then 1 second < (2^32 - 1) microseconds u32(1_000_000 * cnt / freq_divider).unwrap() @@ -411,7 +387,7 @@ macro_rules! hal { let (psc, arr) = compute_arr_presc(timeout.into().0, self.clk.0); self.tim.psc.write(|w| w.psc().bits(psc) ); - + // TODO: Remove this `allow` once this field is made safe for stm32f100 #[allow(unused_unsafe)] self.tim.arr.write(|w| unsafe { w.arr().bits(arr) }); @@ -451,20 +427,12 @@ hal! { TIM3: (tim3, dbg_tim3_stop, tim2), } -#[cfg(any( - feature = "stm32f100", - feature = "stm32f103", - feature = "stm32f105", -))] +#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "stm32f105",))] hal! { TIM1: (tim1, dbg_tim1_stop, tim1), } -#[cfg(any( - feature = "stm32f100", - feature = "stm32f105", - feature = "high", -))] +#[cfg(any(feature = "stm32f100", feature = "stm32f105", feature = "high",))] hal! { TIM6: (tim6, dbg_tim6_stop, tim6), } @@ -472,16 +440,10 @@ hal! { #[cfg(any( all( feature = "high", - any( - feature = "stm32f101", - feature = "stm32f103", - feature = "stm32f107", - ), + any(feature = "stm32f101", feature = "stm32f103", feature = "stm32f107",), ), - any( - feature = "stm32f100", - feature = "stm32f105", -)))] + any(feature = "stm32f100", feature = "stm32f105",) +))] hal! { TIM7: (tim7, dbg_tim7_stop, tim6), } @@ -503,10 +465,7 @@ hal! { TIM5: (tim5, dbg_tim5_stop, tim2), } -#[cfg(all( - feature = "stm32f103", - feature = "high", -))] +#[cfg(all(feature = "stm32f103", feature = "high",))] hal! { TIM8: (tim8, dbg_tim8_stop, tim1), } diff --git a/src/watchdog.rs b/src/watchdog.rs index 1db2a47a..f8b7f012 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -1,8 +1,8 @@ //! Watchdog peripherals use crate::{ - pac::{IWDG, DBGMCU as DBG}, hal::watchdog::{Watchdog, WatchdogEnable}, + pac::{DBGMCU as DBG, IWDG}, time::MilliSeconds, }; @@ -18,7 +18,6 @@ const KR_ACCESS: u16 = 0x5555; const KR_RELOAD: u16 = 0xAAAA; const KR_START: u16 = 0xCCCC; - impl IndependentWatchdog { /// Wrap and start the watchdog pub fn new(iwdg: IWDG) -> Self { @@ -41,7 +40,7 @@ impl IndependentWatchdog { let rl = (timeout_ms * max_rl / max_period).min(max_rl) as u16; self.access_registers(|iwdg| { - iwdg.pr.modify(|_,w| w.pr().bits(pr)); + iwdg.pr.modify(|_, w| w.pr().bits(pr)); iwdg.rlr.modify(|_, w| w.rl().bits(rl)); }); }