From b51bf2ed53bcc857efc74dfe7465978261f1813c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 29 Apr 2024 17:13:54 +0200 Subject: [PATCH 1/3] system(WB) update STM32WBxx HAL Drivers to v1.14.2 Included in STM32CubeWB FW v1.19.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 53 ++++-- .../Inc/stm32wbxx_hal_cortex.h | 2 + .../Inc/stm32wbxx_hal_cryp.h | 3 +- .../Inc/stm32wbxx_hal_qspi.h | 6 +- .../Inc/stm32wbxx_hal_spi_ex.h | 2 +- .../Inc/stm32wbxx_hal_tim.h | 8 +- .../Inc/stm32wbxx_ll_rtc.h | 20 +-- .../Inc/stm32wbxx_ll_tim.h | 21 ++- .../Inc/stm32wbxx_ll_utils.h | 2 +- .../STM32WBxx_HAL_Driver/Release_Notes.html | 170 ++++++++++++------ .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c | 2 +- .../Src/stm32wbxx_hal_cortex.c | 82 ++++++--- .../Src/stm32wbxx_hal_crc.c | 2 +- .../Src/stm32wbxx_hal_cryp.c | 96 ++++++---- .../Src/stm32wbxx_hal_gpio.c | 6 +- .../Src/stm32wbxx_hal_i2c.c | 53 ++++-- .../Src/stm32wbxx_hal_qspi.c | 6 +- .../Src/stm32wbxx_hal_smbus.c | 7 +- .../Src/stm32wbxx_hal_spi_ex.c | 2 +- .../Src/stm32wbxx_ll_tim.c | 4 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 21 files changed, 354 insertions(+), 195 deletions(-) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 00b3dac922..b4dbed31c1 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -548,6 +548,16 @@ extern "C" { #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ /** * @} @@ -1239,10 +1249,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) +#if defined(STM32H5) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 */ +#endif /* STM32H5 || STM32H7RS */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1254,10 +1264,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1595,6 +1605,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1987,12 +1999,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ /** * @} @@ -2307,8 +2319,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2341,8 +2353,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2399,8 +2411,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2417,7 +2429,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -3642,9 +3654,12 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3746,8 +3761,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3893,8 +3910,7 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || \ - defined (STM32C0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4217,6 +4233,9 @@ extern "C" { #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cortex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cortex.h index 8664363cc9..fb1555c5d7 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cortex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cortex.h @@ -293,6 +293,8 @@ void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1U) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cryp.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cryp.h index 8dc0f14b42..07b0ec6a9d 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cryp.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cryp.h @@ -53,7 +53,8 @@ typedef struct uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of @ref CRYP_Data_Type */ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. - 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */ + 128 or 256 bit key length in TinyAES + This parameter can be a value of @ref CRYP_Key_Size */ uint32_t *pKey; /*!< The key used for encryption/decryption */ uint32_t *pInitVect; /*!< The initialization vector used also as initialization counter in CTR mode */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_qspi.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_qspi.h index ce9d99650a..54eb65fbf9 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_qspi.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_qspi.h @@ -589,13 +589,13 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); -uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); +HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi); +uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); -uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); +uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi); /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi_ex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi_ex.h index 54cc0c538a..946cbd0840 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi_ex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi_ex.h @@ -48,7 +48,7 @@ extern "C" { /** @addtogroup SPIEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h index 18a619e3f6..11b421857f 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h @@ -1023,8 +1023,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ -#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ -#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ /** * @} */ @@ -1986,8 +1986,8 @@ mode. ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rtc.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rtc.h index 0a59502d87..aeda9ddc0f 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rtc.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rtc.h @@ -1093,7 +1093,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1127,7 +1127,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1165,7 +1165,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1203,7 +1203,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1257,7 +1257,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1403,7 +1403,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll DR YT LL_RTC_DATE_GetYear\n @@ -1440,7 +1440,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1487,7 +1487,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll DR MT LL_RTC_DATE_GetMonth\n @@ -1532,7 +1532,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll DR DT LL_RTC_DATE_GetDay\n @@ -1598,7 +1598,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h index 10fab60f55..5cf89d5f03 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h @@ -748,6 +748,15 @@ typedef struct */ #endif /* USE_FULL_LL_DRIVER */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 +#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 +/** +@endcond + */ + /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode * @{ */ @@ -763,8 +772,8 @@ typedef struct #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!Purpose

Update History

- +

Main Changes

    @@ -50,6 +50,68 @@

    Main Changes

    Contents

    HAL Drivers updates

      +
    • HAL GPIO driver +
        +
      • Replace GPIO_Pin_x with GPIO_PIN_x to be compliant with macros definition
        • +
      • +
    • HAL CRYP driver +
        +
      • Update CRYP_AESGCM_Process_IT() and CRYP_AESCCM_Process_IT() to prevent ‘Computation Completed’ IRQ from firing before the DINR pointer gets incremented.
        • +
      • +
    • HAL I2C driver +
        +
      • Update HAL_I2C_Slave_Transmit to check if the received NACK is the good one
        • +
      • +
    • HAL SMBUS driver +
        +
      • Update SMBUS_ITErrorHandler to flash TXDR just in case of error
        • +
      • +
    • HAL QSPI driver +
        +
      • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers
        • +
      • Fix incorrect word ‘surcharged’ in functions headers
        • +
      • +
    • HAL CORTEX driver +
        +
      • Updated HAL_MPU_ConfigRegion() to allow the configuration of the MPU registers independently of the value of Enable/Disable field.
        • +
      • Add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion().
        • +
      • +
    • HAL TIM driver +
        +
      • Update interrupt flag is cleared when the update event is generated by software.
        • +
      • Fix typo in PWM asymmetric mode macros’ names.
        • +
      • +
    • HAL LPTIM driver +
        +
      • Removed redundant IS_LPTIM_AUTORELOAD macro.
        • +
      • +
    +


    +

    +

    LL Drivers updates

    +
      +
    • LL UTILS driver +
        +
      • Fix a note about Ticks parameter.
        • +
      • +
    +


    +

    +

    Backward Compatibility

    +

    This release is compatible with the previous versions.

    +
+
+
+ +
+

Main Changes

+
    +
  • Maintenance release of HAL and Low Layer drivers to include latest corrections
    • +
  • HAL/LL code quality enhancement
    • +
+

Contents

+

HAL Drivers updates

+
  • HAL I2C driver
    • Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice
      • @@ -83,7 +145,7 @@

      HAL Drivers updates


    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL I2C driver
        @@ -101,20 +163,20 @@

        LL Drivers updates


      -

      Backward Compatibility

      +

      Backward Compatibility

      This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Maintenance release of HAL and Low Layer drivers to include latest corrections
  • HAL/LL code quality enhancement
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL CRYP driver
      @@ -153,7 +215,7 @@

      HAL Drivers updates


    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL USB driver
        @@ -162,20 +224,20 @@

        LL Drivers updates


      -

      Backward Compatibility

      +

      Backward Compatibility

      This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Maintenance release of HAL and Low Layer drivers to include latest corrections
  • HAL/LL code quality enhancement
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL FLASH driver
      @@ -206,20 +268,20 @@

      HAL Drivers updates


    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Maintenance release of HAL and Low Layer drivers to include latest corrections
  • Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (IRDA, LPTIM, SMARTCARD, TIM, UART, USART)
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL ADC driver
      @@ -266,7 +328,7 @@

      HAL Drivers updates


    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL ADC driver
        @@ -287,20 +349,20 @@

        LL Drivers updates


      -

      Backward Compatibility

      +

      Backward Compatibility

      This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Maintenance release of HAL and Low Layer drivers to include latest corrections
  • Correct English spelling errors and typos
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL EXTI driver
      @@ -376,7 +438,7 @@

      HAL Drivers updates


    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL I2C driver
        @@ -412,19 +474,19 @@

        LL Drivers updates


      -

      Backward Compatibility

      +

      Backward Compatibility

      This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Patch release of HAL and Low Layer drivers
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL COMP driver
      @@ -433,7 +495,7 @@

      HAL Drivers updates


    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL COMP driver
        @@ -442,21 +504,21 @@

        LL Drivers updates


      -

      Backward Compatibility

      +

      Backward Compatibility

      This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Maintenance release of HAL and Low Layer drivers to include latest corrections
  • All source files: update disclaimer to add reference to the new license agreement
  • Correct English spelling errors and typos
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL ADC driver
      @@ -527,7 +589,7 @@

      HAL Drivers updates


    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL ADC driver
        @@ -542,14 +604,14 @@

        LL Drivers updates


      -

      Backward Compatibility

      +

      Backward Compatibility

      This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Maintenance release of HAL and Low Layer drivers to include latest corrections
  • Update of HAL SMBUS driver to introduce fast mode and fast mode plus @@ -563,8 +625,8 @@

    Main Changes


-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL CORTEX driver
      @@ -640,7 +702,7 @@

      HAL Drivers updates


    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL DMA driver
        @@ -667,14 +729,14 @@

        LL Drivers updates


      -

      Backward Compatibility

      +

      Backward Compatibility

      This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

Add support for STM32WB15xx and STM32WB10xx

@@ -810,14 +872,14 @@

Add support for STM32WB15xx

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

Maitenance release

All peripheral

@@ -890,14 +952,14 @@

Maitenance release

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

Maitenance release

All peripheral

@@ -1002,14 +1064,14 @@

Maitenance release

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product

This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.

Added features:

@@ -1054,14 +1116,14 @@

Introduct -

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

Maitenance release

@@ -1105,7 +1167,7 @@

Maitenance release

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

Dependencies

This software release is compatible with:

@@ -1115,7 +1177,7 @@

Dependencies

-

Main Changes

+

Main Changes

Maitenance release

@@ -1187,7 +1249,7 @@

Maitenance release

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

Dependencies

This software release is compatible with:

@@ -1197,7 +1259,7 @@

Dependencies

-

Main Changes

+

Main Changes

STM32WB50xx introduction and maintenance release

First release for STM32WBxx HAL drivers introducing stm32wb50xx devices.

@@ -1266,7 +1328,7 @@

STM32WB50xx introducti

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

Dependencies

This software release is compatible with:

@@ -1276,7 +1338,7 @@

Dependencies

-

Main Changes

+

Main Changes

Maintenance release

Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.

@@ -1330,7 +1392,7 @@

Maintenance release

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

Dependencies

This software release is compatible with:

@@ -1340,7 +1402,7 @@

Dependencies

-

Main Changes

+

Main Changes

First release

First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.

diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c index ec62ac72f5..e19fb9a97a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c @@ -56,7 +56,7 @@ */ #define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32WBxx_HAL_VERSION_SUB1 (0x0EU) /*!< [23:16] sub1 version */ -#define __STM32WBxx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32WBxx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\ |(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c index 3e2384ed35..5c34a39ae0 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c @@ -415,6 +415,38 @@ void HAL_MPU_Enable(uint32_t MPU_Control) __ISB(); } +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + /** * @brief Initialize and configure the Region and the memory to be protected. * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains @@ -426,38 +458,32 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; - if ((MPU_Init->Enable) != 0U) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - MPU->RBAR = MPU_Init->BaseAddress; - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); - } - else - { - MPU->RBAR = 0x00U; - MPU->RASR = 0x00U; - } + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); } #endif /* __MPU_PRESENT */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc.c index d1b1b63362..d7882aacb5 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc.c @@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + CLEAR_REG(hcrc->Instance->IDR); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c index e668b5fe57..620a032392 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c @@ -30,7 +30,8 @@ The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows: (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral + (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE() + or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT()) (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() @@ -58,8 +59,10 @@ (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication algorithms) is in words or bytes. (##) The Header used only in AES GCM and CCM Algorithm for authentication. - (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field. - (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes. + (##) The HeaderSize providing the size of the header buffer in words or bytes, + depending upon HeaderWidthUnit field. + (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) + is in words or bytes. (##) The B0 block is the first authentication block used only in AES CCM mode. (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below). @@ -316,7 +319,8 @@ * @{ */ #define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey + is 299 clock cycles.*/ #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/ #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */ @@ -350,7 +354,8 @@ * @{ */ -#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__)) +#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR,\ + AES_CR_GCMPH, (uint32_t)(__PHASE__)) /** * @} @@ -923,8 +928,6 @@ void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp) hcryp->SuspendRequest = HAL_CRYP_SUSPEND; } - - /** * @brief CRYP processing suspension and peripheral internal parameters storage. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -977,7 +980,8 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) hcryp->CrypOutCount_saved = hcryp->CrypOutCount; hcryp->Phase_saved = hcryp->Phase; hcryp->State_saved = hcryp->State; - hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size / 4U) : hcryp->Size); + hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? \ + (hcryp->Size / 4U) : hcryp->Size); hcryp->SizesSum_saved = hcryp->SizesSum; hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation; hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount; @@ -1068,14 +1072,16 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) hcryp->ResumingFlag = 1U; if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) { - if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \ + hcryp->pCrypOutBuffPtr_saved) != HAL_OK) { return HAL_ERROR; } } else { - if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \ + hcryp->pCrypOutBuffPtr_saved) != HAL_OK) { return HAL_ERROR; } @@ -1708,7 +1714,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu hcryp->Phase = CRYP_PHASE_PROCESS; /* Start DMA process transfer for AES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), \ + (uint32_t)(hcryp->pCrypOutBuffPtr)); status = HAL_OK; break; @@ -1861,25 +1868,27 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { + uint32_t itsource = hcryp->Instance->CR; + uint32_t itflag = hcryp->Instance->SR; /* Check if error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET) + if ((itsource & CRYP_IT_ERRIE) == CRYP_IT_ERRIE) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET) + if ((itflag & CRYP_IT_WRERR) == CRYP_IT_WRERR) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET) + if ((itflag & CRYP_IT_RDERR) == CRYP_IT_RDERR) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; } } - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) + if ((itflag & CRYP_IT_CCF) == CRYP_IT_CCF) { - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + if ((itsource & CRYP_IT_CCFIE) == CRYP_IT_CCFIE) { /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2685,7 +2694,8 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) /*Read the output block from the output FIFO */ for (count = 0U; count < 4U; count++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[count] = hcryp->Instance->DOUTR; } @@ -2896,7 +2906,8 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer*/ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUTR; @@ -2925,7 +2936,8 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) if (hcryp->State == HAL_CRYP_STATE_BUSY) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer*/ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUTR; @@ -3251,7 +3263,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUTR; } for (index = 0U; index < lastwordsize; index++) @@ -3535,10 +3548,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) header has already been processed; only process here message payload */ { - - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); @@ -3575,6 +3584,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); } else /* Size < 16Bytes : first block is the last block*/ { @@ -3623,6 +3635,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) /*Call legacy weak Input complete callback*/ HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); } } @@ -3918,7 +3933,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t for (loopcounter = 0U; loopcounter < 4U; loopcounter++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[loopcounter] = hcryp->Instance->DOUTR; } for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) @@ -4078,14 +4094,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) } else if (hcryp->Size >= 16U) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { @@ -4191,14 +4207,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) { /* Write the first input header block in the Input FIFO, the following header data will be fed after interrupt occurrence */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U); }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/ } /* end of if (dokeyivconfig == 1U) */ else /* Key and IV have already been configured, @@ -4219,14 +4235,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) } else if (hcryp->Size >= 16U) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { @@ -4412,7 +4428,8 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) /***************************** Payload phase *******************************/ - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer*/ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUTR; @@ -4651,7 +4668,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUTR; } for (index = 0U; index < lastwordsize; index++) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c index 90af8eafb3..564acc3c4c 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c @@ -420,9 +420,9 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin * accesses. * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WLxx family * @param PinReset specifies the port bits to be reset - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) or zero. * @param PinSet specifies the port bits to be set - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) or zero. * @note Both PinReset and PinSet combinations shall not get any common bit, else * assert would be triggered. * @note At least one of the two parameters used to set or reset shall be different from zero. @@ -469,7 +469,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) * until the next reset. * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBxx family * @param GPIO_Pin specifies the port bits to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c index 05f58e6e54..de3805e869 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c @@ -1385,6 +1385,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1478,31 +1480,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until AF flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } - return HAL_ERROR; + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c index 3ea9c7f49c..fc71c19a3e 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c @@ -2219,7 +2219,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS * @param hqspi QSPI handle * @retval HAL state */ -HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) +HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi) { /* Return QSPI handle state */ return hqspi->State; @@ -2230,7 +2230,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) * @param hqspi QSPI handle * @retval QSPI Error Code */ -uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) +uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi) { return hqspi->ErrorCode; } @@ -2410,7 +2410,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t * @param hqspi QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ -uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) +uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi) { return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); } diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c index 84f93293fa..9751bdbd13 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c @@ -2619,8 +2619,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); + if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) + { + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + } /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c index f51957d8d4..f8a8a9fc0b 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c @@ -76,7 +76,7 @@ * the configuration information for the specified SPI module. * @retval HAL status */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) { __IO uint32_t tmpreg; uint8_t count = 0U; diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c index 643b2d8d8b..dbfeea3943 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_tim.c @@ -66,8 +66,8 @@ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index d96b4b1876..611f1f43f4 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -17,7 +17,7 @@ * STM32L5: 1.0.6 * STM32MP1: 1.6.0 * STM32U5: 1.5.0 - * STM32WB: 1.14.1 + * STM32WB: 1.14.2 * STM32WBA: 1.2.0 * STM32WL: 1.3.0 From 0a9730c8326b1f62f0898265c84b8e331554b88f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 29 Apr 2024 17:13:55 +0200 Subject: [PATCH 2/3] system(WB): update STM32WBxx CMSIS Drivers to v1.12.1 Included in STM32CubeWB FW v1.19.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32WBxx/Include/stm32wbxx.h | 2 +- .../ST/STM32WBxx/{License.md => LICENSE.md} | 0 .../Device/ST/STM32WBxx/Release_Notes.html | 61 +++++++++++-------- .../Templates/gcc/startup_stm32wb10xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb15xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb1mxx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb30xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb35xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb50xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb55xx_cm4.s | 3 +- .../Templates/gcc/startup_stm32wb5mxx_cm4.s | 3 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 12 files changed, 55 insertions(+), 34 deletions(-) rename system/Drivers/CMSIS/Device/ST/STM32WBxx/{License.md => LICENSE.md} (100%) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h index 8f4bfc1686..e43460630e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h @@ -69,7 +69,7 @@ extern "C" { */ #define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32WBxx_CMSIS_VERSION_SUB1 (0x0CU) /*!< [23:16] sub1 version */ -#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\ |(__STM32WBxx_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/License.md b/system/Drivers/CMSIS/Device/ST/STM32WBxx/LICENSE.md similarity index 100% rename from system/Drivers/CMSIS/Device/ST/STM32WBxx/License.md rename to system/Drivers/CMSIS/Device/ST/STM32WBxx/LICENSE.md diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Release_Notes.html index 2d94d716e1..ebceb5e4e1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Release_Notes.html @@ -90,15 +90,28 @@

STM32WB15xx, STM32WB10xx and ST

Update History

- +

Main Changes

    +
  • Update declaration of g_pfnVectors size in gcc/startup files
    • +
+

Supported Devices and boards

+
    +
  • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx and STM32WB1Mxx devices.
    • +
+
+
+
+ +
+

Main Changes

+
  • Fix incorrect USB_BASE and USB_PMAADDR addresses
  • Fix initialization missing of data in RAM2 memory
  • Add specific LSE_VALUE for STM32WB5Mxx
-

Supported Devices and boards

+

Supported Devices and boards

  • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx and STM32WB1Mxx devices.
@@ -107,11 +120,11 @@

Supported Devices and boards

-

Main Changes

+

Main Changes

  • Add support for the upcoming STM32WB1M device
-

Supported Devices and boards

+

Supported Devices and boards

  • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx and STM32WB1Mxx devices.
@@ -120,11 +133,11 @@

Supported Devices and boards

-

Main Changes

+

Main Changes

  • Align ADC registers naming on Reference Manual (For STM32WB15xx & STM32WB10xx)
-

Supported Devices and boards

+

Supported Devices and boards

  • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.
@@ -133,13 +146,13 @@

Supported Devices and boards

-

Main Changes

+

Main Changes

  • Update CMSIS devices drivers for all value lines not supporting SMPS
  • All source files and templates: update disclaimer to add reference to the new license agreement
  • Correct English spelling typos and remove non UTF-8 characters in comments
-

Supported Devices and boards

+

Supported Devices and boards

  • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.
@@ -148,7 +161,7 @@

Supported Devices and boards

-

Main Changes

+

Main Changes

  • Add atomic register access services:
      @@ -162,7 +175,7 @@

      Main Changes

    • Add define LSI_STARTUP_TIME used in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT)
    • Add define FLASH_ECCR_CPUID bits for new macro __HAL_FLASH_ECC_CPUID() macro
    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.
    @@ -171,7 +184,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Add support for STM32WB15xx and STM32WB10xx

    • Change how to adapt VTOR for user
      • @@ -182,7 +195,7 @@

      Development Toolchains and Compile
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
    • System Workbench STM32 (SW4STM32) toolchain V2.7

    -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.
    @@ -191,7 +204,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Maintenance release

    Maintenance release for STM32WBxx devices (stm32wb55xx, stm32wb50xx, stm32wb35xx and stm32wb30xx devices)

    @@ -221,7 +234,7 @@

    Development Toolchains and Compi
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7
    • -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.
    @@ -230,7 +243,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Maintenance release

    Maintenance release for STM32WBxx devices (stm32wb55xx, stm32wb50xx, stm32wb35xx and stm32wb30xx devices)

    @@ -269,7 +282,7 @@

    Development Toolchains and Compi
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7
    • -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.
    @@ -278,7 +291,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Introduction of STM32WB35xx, STM32WB30xx and STM32WB5Mxx product

    This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.

    Added features:

    @@ -296,7 +309,7 @@

    Development Toolchains and Compi
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7
    • -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.
    @@ -305,7 +318,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Maintenance release for STM32WBxx devices (stm32wb55xx and stm32wb50xx devices)

    @@ -334,7 +347,7 @@

    Development Toolchains and Compi
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7
    • -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx, STM32WB50xx devices
    @@ -343,7 +356,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Introduction of STM32WB50xx device

    First release for STM32WBxx CMSIS introducing stm32wb50xx devices.

    Contents

    @@ -354,7 +367,7 @@

    Development Toolchains and Compi
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
  • System Workbench STM32 (SW4STM32) toolchain V2.7
    • -

    Supported Devices and boards

    +

    Supported Devices and boards

    • STM32WB55xx and STM32WB50xx devices
    @@ -363,7 +376,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Maintenance release

    Maintenance release for STM32WBxx devices (stm32wb55xx devices)

    @@ -387,7 +400,7 @@

    Maintenance release

    -

    Main Changes

    +

    Main Changes

    First release

    Add support of STM32WB55xx.

    diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb10xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb10xx_cm4.s index 60cf8067df..574328547e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb10xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb10xx_cm4.s @@ -137,7 +137,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -221,6 +220,8 @@ g_pfnVectors: .word 0 .word DMAMUX1_OVR_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb15xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb15xx_cm4.s index 2c6949eb10..d1c47c5d36 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb15xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb15xx_cm4.s @@ -137,7 +137,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -221,6 +220,8 @@ g_pfnVectors: .word 0 .word DMAMUX1_OVR_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb1mxx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb1mxx_cm4.s index 11a9ac3a90..7f47359fcb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb1mxx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb1mxx_cm4.s @@ -137,7 +137,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -221,6 +220,8 @@ g_pfnVectors: .word 0 .word DMAMUX1_OVR_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s index 4c848f92be..f9fe62f436 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb30xx_cm4.s @@ -137,7 +137,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -221,6 +220,8 @@ g_pfnVectors: .word 0 .word DMAMUX1_OVR_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s index 65ead5ec1c..3125a7978f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb35xx_cm4.s @@ -137,7 +137,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -221,6 +220,8 @@ g_pfnVectors: .word DMA2_Channel7_IRQHandler .word DMAMUX1_OVR_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb50xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb50xx_cm4.s index ccf0f19840..1a74417242 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb50xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb50xx_cm4.s @@ -138,7 +138,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -222,6 +221,8 @@ g_pfnVectors: .word 0 .word DMAMUX1_OVR_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb55xx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb55xx_cm4.s index d7f99eaac7..8f391be727 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb55xx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb55xx_cm4.s @@ -137,7 +137,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -221,6 +220,8 @@ g_pfnVectors: .word DMA2_Channel7_IRQHandler .word DMAMUX1_OVR_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s index 68434a2cb0..d05c8e7c2c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s @@ -137,7 +137,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -221,6 +220,8 @@ g_pfnVectors: .word DMA2_Channel7_IRQHandler .word DMAMUX1_OVR_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index e33baf123b..459142c384 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -17,7 +17,7 @@ * STM32L5: 1.0.6 * STM32MP1: 1.6.0 * STM32U5: 1.4.0 - * STM32WB: 1.12.0 + * STM32WB: 1.12.1 * STM32WBA: 1.2.0 * STM32WL: 1.2.0 From 1f1cc2f6b8d43f31b1e8b230a2b93058d4990971 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 29 Apr 2024 17:17:01 +0200 Subject: [PATCH 3/3] chore(wb): update variants against CubeMX DB release 6.0.110 Signed-off-by: Frederic Pillon --- variants/STM32WBxx/WB10CCU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCUxE/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCY/PeripheralPins.c | 2 +- variants/STM32WBxx/WB1MMCH/PeripheralPins.c | 2 +- variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c | 2 +- variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c | 2 +- variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c | 2 +- variants/STM32WBxx/WB5MMGH/PeripheralPins.c | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/variants/STM32WBxx/WB10CCU/PeripheralPins.c b/variants/STM32WBxx/WB10CCU/PeripheralPins.c index e0543b4e17..31583f3d28 100644 --- a/variants/STM32WBxx/WB10CCU/PeripheralPins.c +++ b/variants/STM32WBxx/WB10CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB10CCUx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCU/PeripheralPins.c b/variants/STM32WBxx/WB15CCU/PeripheralPins.c index ad349abd82..6aadb0d0c4 100644 --- a/variants/STM32WBxx/WB15CCU/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCUx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c b/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c index 47ab8161ea..74d7897b16 100644 --- a/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCUxE.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCY/PeripheralPins.c b/variants/STM32WBxx/WB15CCY/PeripheralPins.c index 9be97a67bf..906574b05b 100644 --- a/variants/STM32WBxx/WB15CCY/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCYx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB1MMCH/PeripheralPins.c b/variants/STM32WBxx/WB1MMCH/PeripheralPins.c index bb0451a965..d2220b845f 100644 --- a/variants/STM32WBxx/WB1MMCH/PeripheralPins.c +++ b/variants/STM32WBxx/WB1MMCH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB1MMCHx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c index 1822c2d5dd..a1036ea9d2 100644 --- a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c +++ b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB30CEUxA.xml, STM32WB50CGUx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c index 3b638b6e7b..5121def2f6 100644 --- a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c +++ b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB35C(C-E)UxA.xml, STM32WB55CCUx.xml * STM32WB55CEUx.xml, STM32WB55CGUx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c b/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c index a6c1249483..243058f1ba 100644 --- a/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c +++ b/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB55RCVx.xml, STM32WB55REVx.xml * STM32WB55RGVx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c index da0fac23a8..fc518199ca 100644 --- a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c +++ b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WB55VEQx.xml, STM32WB55VEYx.xml * STM32WB55VGQx.xml, STM32WB55VGYx.xml * STM32WB55VYYx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB5MMGH/PeripheralPins.c b/variants/STM32WBxx/WB5MMGH/PeripheralPins.c index a564445d13..853e24d0c3 100644 --- a/variants/STM32WBxx/WB5MMGH/PeripheralPins.c +++ b/variants/STM32WBxx/WB5MMGH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB5MMGHx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h"