From c793bc140502887625cc32e78867066237221607 Mon Sep 17 00:00:00 2001 From: Kazuki Ota Date: Sun, 6 Aug 2023 02:45:11 +0900 Subject: [PATCH 1/3] variant(H5): add generic generic H503RBTx support Signed-off-by: dojyorin Co-authored-by: Frederic Pillon --- README.md | 1 + boards.txt | 8 + variants/STM32H5xx/H503RBT/generic_clock.c | 51 +++++- variants/STM32H5xx/H503RBT/ldscript.ld | 175 +++++++++++++++++++++ 4 files changed, 233 insertions(+), 2 deletions(-) create mode 100644 variants/STM32H5xx/H503RBT/ldscript.ld diff --git a/README.md b/README.md index 5d7d776bfe..66062bd05a 100644 --- a/README.md +++ b/README.md @@ -521,6 +521,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | +| :yellow_heart: | STM32H503RB | Generic Board | **2.7.0** | | | :green_heart: | STM32H563IIKxQ | Generic Board | *2.6.0* | | | :green_heart: | STM32H563ZG
STM32H563ZI | Generic Board | *2.6.0* | | | :green_heart: | STM32H573IIKxQ | Generic Board | *2.6.0* | | diff --git a/boards.txt b/boards.txt index 6e9b145ce5..edf8d77138 100644 --- a/boards.txt +++ b/boards.txt @@ -7204,6 +7204,14 @@ GenH5.build.flash_offset=0x0 GenH5.upload.maximum_size=0 GenH5.upload.maximum_data_size=0 +# Generic H503RBTx +GenH5.menu.pnum.GENERIC_H503RBTX=Generic H503RBTx +GenH5.menu.pnum.GENERIC_H503RBTX.upload.maximum_size=131072 +GenH5.menu.pnum.GENERIC_H503RBTX.upload.maximum_data_size=32768 +GenH5.menu.pnum.GENERIC_H503RBTX.build.board=GENERIC_H503RBTX +GenH5.menu.pnum.GENERIC_H503RBTX.build.product_line=STM32H503xx +GenH5.menu.pnum.GENERIC_H503RBTX.build.variant=STM32H5xx/H503RBT + # Generic H563IIKxQ GenH5.menu.pnum.GENERIC_H563IIKXQ=Generic H563IIKxQ GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152 diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index f30dcfb8df..5b4c0c3e26 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -20,8 +20,55 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /* Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + /* Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { + Error_Handler(); + } + + /* Initializes the peripherals clock */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_CSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H503RBT/ldscript.ld b/variants/STM32H5xx/H503RBT/ldscript.ld new file mode 100644 index 0000000000..3f85cdba2e --- /dev/null +++ b/variants/STM32H5xx/H503RBT/ldscript.ld @@ -0,0 +1,175 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H503RBTx Device from STM32H5 series +** 128Kbytes FLASH +** 32Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2021 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY { + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH ( rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS { + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } > FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } > FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } > FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } > FLASH + + .preinit_array : { + . = ALIGN(4); + PROVIDE_HIDDEN(__preinit_array_start = .); + KEEP(*(.preinit_array*)) + PROVIDE_HIDDEN(__preinit_array_end = .); + . = ALIGN(4); + } > FLASH + + .init_array : { + . = ALIGN(4); + PROVIDE_HIDDEN(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array*)) + PROVIDE_HIDDEN(__init_array_end = .); + . = ALIGN(4); + } > FLASH + + .fini_array : { + . = ALIGN(4); + PROVIDE_HIDDEN(__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array*)) + PROVIDE_HIDDEN(__fini_array_end = .); + . = ALIGN(4); + } > FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } > RAM AT > FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } > RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : { + . = ALIGN(8); + PROVIDE(end = .); + PROVIDE(_end = .); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } > RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { + *(.ARM.attributes) + } +} \ No newline at end of file From b60768abc6fa238edebe22be9c60404ba34b8858 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Mon, 28 Aug 2023 16:36:29 +0200 Subject: [PATCH 2/3] variant(H5): add Nucleo H503RB support Signed-off-by: dojyorin Co-authored-by: Frederic Pillon --- README.md | 1 + boards.txt | 13 ++ .../H503RBT/variant_NUCLEO_H503RB.cpp | 167 +++++++++++++++ .../STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h | 193 ++++++++++++++++++ 4 files changed, 374 insertions(+) create mode 100644 variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp create mode 100644 variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h diff --git a/README.md b/README.md index 66062bd05a..955c77e511 100644 --- a/README.md +++ b/README.md @@ -125,6 +125,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32G0B1RE | [Nucleo G0B1RE](https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html) | *2.1.0* | | | :green_heart: | STM32G431RB | [Nucleo G431RB](https://www.st.com/en/evaluation-tools/nucleo-g431rb.html) | *1.7.0* | | | :green_heart: | STM32G474RE | [Nucleo G474RE](https://www.st.com/en/evaluation-tools/nucleo-g474re.html) | *1.7.0* | | +| :yellow_heart: | STM32H503RB | [Nucleo H503RB](https://www.st.com/en/evaluation-tools/nucleo-h503rb.html) | **2.7.0** | | | :green_heart: | STM32L010RB | [Nucleo L010RB](https://www.st.com/en/evaluation-tools/nucleo-l010rb.html) | *2.1.0* | | | :green_heart: | STM32L053R8 | [Nucleo L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html) | *0.1.0* | | | :green_heart: | STM32L073RZ | [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) | *1.4.0* | | diff --git a/boards.txt b/boards.txt index edf8d77138..abd71c2dc7 100644 --- a/boards.txt +++ b/boards.txt @@ -488,6 +488,19 @@ Nucleo_64.menu.pnum.NUCLEO_G474RE.build.series=STM32G4xx Nucleo_64.menu.pnum.NUCLEO_G474RE.build.product_line=STM32G474xx Nucleo_64.menu.pnum.NUCLEO_G474RE.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET +# NUCLEO H503RB +Nucleo_64.menu.pnum.NUCLEO_H503RB=Nucleo H503RB +Nucleo_64.menu.pnum.NUCLEO_H503RB.node=NOD_H503RB +Nucleo_64.menu.pnum.NUCLEO_H503RB.upload.maximum_size=131072 +Nucleo_64.menu.pnum.NUCLEO_H503RB.upload.maximum_data_size=32768 +Nucleo_64.menu.pnum.NUCLEO_H503RB.build.mcu=cortex-m33 +Nucleo_64.menu.pnum.NUCLEO_H503RB.build.fpu=-mfpu=fpv4-sp-d16 +Nucleo_64.menu.pnum.NUCLEO_H503RB.build.float-abi=-mfloat-abi=hard +Nucleo_64.menu.pnum.NUCLEO_H503RB.build.board=NUCLEO_H503RB +Nucleo_64.menu.pnum.NUCLEO_H503RB.build.series=STM32H5xx +Nucleo_64.menu.pnum.NUCLEO_H503RB.build.product_line=STM32H503xx +Nucleo_64.menu.pnum.NUCLEO_H503RB.build.variant=STM32H5xx/H503RBT + # NUCLEO_L010RB board Nucleo_64.menu.pnum.NUCLEO_L010RB=Nucleo L010RB Nucleo_64.menu.pnum.NUCLEO_L010RB.node=NODE_L010RB diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp new file mode 100644 index 0000000000..70bc7e584e --- /dev/null +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -0,0 +1,167 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#if defined(ARDUINO_NUCLEO_H503RB) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PB_15, // D0 + PB_14, // D1 + PA_10, // D2 + PB_3, // D3 + PB_5, // D4 + PB_4, // D5 + PB_10, // D6 + PA_8, // D7 + PC_7, // D8 + PC_6, // D9 + PC_9, // D10 + PA_7, // D11/A11 + PA_6, // D12/A12 + PA_5, // D13/A13 + PB_7, // D14 + PB_6, // D15 + // CN7 odd pins + PC_10, // D16 + PC_12, // D17 + PA_13, // D18 + PA_14, // D19 + PA_15, // D20 + PC_13, // D21 + PC_14, // D22 + PC_15, // D23 + PH_0, // D24 + PH_1, // D25 + PC_2, // D26/A6 + PC_3, // D27/A7 + // CN7 even pins + PC_11, // D28 + PD_2, // D29 + PA_0, // D30/A0 + PA_1, // D31/A1 + PA_2, // D32/A2 + PB_0, // D33/A3 + PC_1, // D34/A4 + PC_0, // D35/A5 + // CN10 odd pins are D0-D15 + // CN10 even pins + PC_8, // D36 + PC_5, // D37/A8 + PA_12, // D38 + PA_11, // D39 + PB_12, // D40 + PB_2, // D41 + PB_1, // D42/A9 + PB_15, // D43 + PB_14, // D44 + PB_13, // D45 + PC_4, // D46/A10 + PB_8, // D47 + // Other + PA_3, // D48/A14 + PA_4, // D49/A15 + PA_9 // D50 // USB_VBUS +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 30, // A0, PA0 + 31, // A1, PA1 + 32, // A2, PA2 + 33, // A3, PB0 + 34, // A4, PC1 + 35, // A5, PC0 + 26, // A6, PC2 + 27, // A7, PC3 + 37, // A8, PC5 + 42, // A9, PB1 + 46, // A10, PC4 + 11, // A11, PA7 + 12, // A12, PA6 + 13, // A13, PA5 + 48, // A14, PA3 + 49 // A15, PA4 +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /* Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE + | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLN = 250; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /* Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { + Error_Handler(); + } + + /* Initializes the peripherals clock */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_CSI; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif + +#endif /* ARDUINO_NUCLEO_H503RB */ \ No newline at end of file diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h new file mode 100644 index 0000000000..f9b1282e19 --- /dev/null +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h @@ -0,0 +1,193 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PB15 0 +#define PB14 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PC7 8 +#define PC6 9 +#define PC9 10 +#define PA7 PIN_A11 +#define PA6 PIN_A12 +#define PA5 PIN_A13 +#define PB7 14 +#define PB6 15 +// CN7 odd pins +#define PC10 16 +#define PC12 17 +// PA13 and PA14 are shared with SWD signals connected to STLINK-V3EC. +// It is not recommended to use them as I/O pins. +// By default, they are used as SWD signals (SB40 and SB41 ON). +#define PA13 18 +#define PA14 19 +#define PA15 20 +#define PC13 21 +#define PC14 22 +#define PC15 23 +#define PH0 24 +#define PH1 25 +#define PC2 PIN_A6 +#define PC3 PIN_A7 +// CN7 even pins +#define PC11 28 +#define PD2 29 +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PB0 PIN_A3 +#define PC1 PIN_A4 +#define PC0 PIN_A5 +// CN10 odd pins are D0-D15 +// CN10 even pins +#define PC8 36 +#define PC5 PIN_A8 +#define PA12 38 +#define PA11 39 +#define PB12 40 +#define PB2 41 +#define PB1 PIN_A9 +// 43 is PB15 (0) +// 44 is PB14 (1) +#define PB13 45 +#define PC4 PIN_A10 +#define PB8 47 +// Other +#define PA3 PIN_A14 +#define PA4 PIN_A15 +#define PA9 50 // USB_VBUS + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA13_ALT1 (PA13 | ALT1) +#define PA14_ALT1 (PA14 | ALT1) +#define PA14_ALT2 (PA14 | ALT2) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 51 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#define LED_GREEN PA5 +#ifndef LED_BUILTIN + #define LED_BUILTIN LED_GREEN +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 3 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA_3_ALT1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA4 +#endif + +#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */ + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif \ No newline at end of file From 4677fab5467fbb0cfbedce425b73fc842e77e47b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 28 Aug 2023 17:46:47 +0200 Subject: [PATCH 3/3] chore(cmake): update files Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 170 ++++++++++++++++++++++ variants/STM32H5xx/H503RBT/CMakeLists.txt | 1 + 2 files changed, 171 insertions(+) diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index b4044e87ff..b2873ed3bf 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -71230,6 +71230,91 @@ target_compile_options(GENERIC_G4A1VETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H503RBTX +# ----------------------------------------------------------------------------- + +set(GENERIC_H503RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503RBT") +set(GENERIC_H503RBTX_MAXSIZE 131072) +set(GENERIC_H503RBTX_MAXDATASIZE 32768) +set(GENERIC_H503RBTX_MCU cortex-m33) +set(GENERIC_H503RBTX_FPCONF "-") +add_library(GENERIC_H503RBTX INTERFACE) +target_compile_options(GENERIC_H503RBTX INTERFACE + "SHELL:-DSTM32H503xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H503RBTX_MCU} +) +target_compile_definitions(GENERIC_H503RBTX INTERFACE + "STM32H5xx" + "ARDUINO_GENERIC_H503RBTX" + "BOARD_NAME=\"GENERIC_H503RBTX\"" + "BOARD_ID=GENERIC_H503RBTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H503RBTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ + ${GENERIC_H503RBTX_VARIANT_PATH} +) + +target_link_options(GENERIC_H503RBTX INTERFACE + "LINKER:--default-script=${GENERIC_H503RBTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H503RBTX_MCU} +) +target_link_libraries(GENERIC_H503RBTX INTERFACE + arm_ARMv8MMLlfsp_math +) + +add_library(GENERIC_H503RBTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H503RBTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H503RBTX_serial_generic INTERFACE) +target_compile_options(GENERIC_H503RBTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H503RBTX_serial_none INTERFACE) +target_compile_options(GENERIC_H503RBTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H503RBTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H503RBTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H503RBTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H503RBTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H503RBTX_usb_HID INTERFACE) +target_compile_options(GENERIC_H503RBTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H503RBTX_usb_none INTERFACE) +target_compile_options(GENERIC_H503RBTX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H503RBTX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H503RBTX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H503RBTX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H503RBTX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H503RBTX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H503RBTX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H563IIKXQ # ----------------------------------------------------------------------------- @@ -98518,6 +98603,91 @@ target_compile_options(NUCLEO_G474RE_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_H503RB +# ----------------------------------------------------------------------------- + +set(NUCLEO_H503RB_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503RBT") +set(NUCLEO_H503RB_MAXSIZE 131072) +set(NUCLEO_H503RB_MAXDATASIZE 32768) +set(NUCLEO_H503RB_MCU cortex-m33) +set(NUCLEO_H503RB_FPCONF "fpv4-sp-d16-hard") +add_library(NUCLEO_H503RB INTERFACE) +target_compile_options(NUCLEO_H503RB INTERFACE + "SHELL:-DSTM32H503xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_H503RB_MCU} +) +target_compile_definitions(NUCLEO_H503RB INTERFACE + "STM32H5xx" + "ARDUINO_NUCLEO_H503RB" + "BOARD_NAME=\"NUCLEO_H503RB\"" + "BOARD_ID=NUCLEO_H503RB" + "VARIANT_H=\"variant_NUCLEO_H503RB.h\"" +) +target_include_directories(NUCLEO_H503RB INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ + ${NUCLEO_H503RB_VARIANT_PATH} +) + +target_link_options(NUCLEO_H503RB INTERFACE + "LINKER:--default-script=${NUCLEO_H503RB_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_H503RB_MCU} +) +target_link_libraries(NUCLEO_H503RB INTERFACE + +) + +add_library(NUCLEO_H503RB_serial_disabled INTERFACE) +target_compile_options(NUCLEO_H503RB_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_H503RB_serial_generic INTERFACE) +target_compile_options(NUCLEO_H503RB_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_H503RB_serial_none INTERFACE) +target_compile_options(NUCLEO_H503RB_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_H503RB_usb_CDC INTERFACE) +target_compile_options(NUCLEO_H503RB_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_H503RB_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_H503RB_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_H503RB_usb_HID INTERFACE) +target_compile_options(NUCLEO_H503RB_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_H503RB_usb_none INTERFACE) +target_compile_options(NUCLEO_H503RB_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_H503RB_xusb_FS INTERFACE) +target_compile_options(NUCLEO_H503RB_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_H503RB_xusb_HS INTERFACE) +target_compile_options(NUCLEO_H503RB_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_H503RB_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_H503RB_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_H563ZI # ----------------------------------------------------------------------------- diff --git a/variants/STM32H5xx/H503RBT/CMakeLists.txt b/variants/STM32H5xx/H503RBT/CMakeLists.txt index 2a4d55b6b1..e0f94897af 100644 --- a/variants/STM32H5xx/H503RBT/CMakeLists.txt +++ b/variants/STM32H5xx/H503RBT/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_NUCLEO_H503RB.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage)