From 20c7989a41d7588e397c5d7496046c118f9c4264 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 21 May 2021 14:36:46 +0200 Subject: [PATCH] variant: G0: add Nucleo-G0B1RE Signed-off-by: Frederic Pillon --- README.md | 1 + boards.txt | 13 ++ .../variant_NUCLEO_G0B1RE.cpp | 169 +++++++++++++++ .../variant_NUCLEO_G0B1RE.h | 194 ++++++++++++++++++ 4 files changed, 377 insertions(+) create mode 100644 variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/variant_NUCLEO_G0B1RE.cpp create mode 100644 variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/variant_NUCLEO_G0B1RE.h diff --git a/README.md b/README.md index a8a4672b7b..a3470b1a70 100644 --- a/README.md +++ b/README.md @@ -105,6 +105,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F411RE | [Nucleo F411RE](http://www.st.com/en/evaluation-tools/nucleo-f411re.html) | *0.2.1* | | | :green_heart: | STM32F446RE | [Nucleo F446RE](http://www.st.com/en/evaluation-tools/nucleo-f446re.html) | *1.1.1* | | | :green_heart: | STM32G071RB | [Nucleo G071RB](https://www.st.com/en/evaluation-tools/nucleo-g071rb.html) | *1.6.0* | | +| :yellow_heart: | STM32G0B1RE | [Nucleo G0B1RE](https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html) | **2.1.0** | | | :green_heart: | STM32G431RB | [Nucleo G431RB](https://www.st.com/en/evaluation-tools/nucleo-g431rb.html) | *1.7.0* | | | :green_heart: | STM32G474RE | [Nucleo G474RE](https://www.st.com/en/evaluation-tools/nucleo-g474re.html) | *1.7.0* | | | :yellow_heart: | STM32L010RB | [Nucleo L010RB](https://www.st.com/en/evaluation-tools/nucleo-l010rb.html) | **2.1.0** | | diff --git a/boards.txt b/boards.txt index 0d158a873e..30b17271ea 100644 --- a/boards.txt +++ b/boards.txt @@ -347,6 +347,19 @@ Nucleo_64.menu.pnum.NUCLEO_G071RB.build.variant=STM32G0xx/G071R(6-8)T_G071RB(I-T Nucleo_64.menu.pnum.NUCLEO_G071RB.build.cmsis_lib_gcc=arm_cortexM0l_math Nucleo_64.menu.pnum.NUCLEO_G071RB.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 +# NUCLEO_G0B1RE board +Nucleo_64.menu.pnum.NUCLEO_G0B1RE=Nucleo G0B1RE +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.node=NOD_G0B1RE +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.upload.maximum_size=262144 +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.upload.maximum_data_size=147456 +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.mcu=cortex-m0plus +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.board=NUCLEO_G0B1RE +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.series=STM32G0xx +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.product_line=STM32G0B1xx +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.cmsis_lib_gcc=arm_cortexM0l_math +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 + # NUCLEO_G431RB board Nucleo_64.menu.pnum.NUCLEO_G431RB=Nucleo G431RB Nucleo_64.menu.pnum.NUCLEO_G431RB.node="NODE_G431RB,NOD_G431RB" diff --git a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/variant_NUCLEO_G0B1RE.cpp b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/variant_NUCLEO_G0B1RE.cpp new file mode 100644 index 0000000000..52fb476887 --- /dev/null +++ b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/variant_NUCLEO_G0B1RE.cpp @@ -0,0 +1,169 @@ +/* + ******************************************************************************* + * Copyright (c) 2021, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#if defined(ARDUINO_NUCLEO_G0B1RE) +#include "pins_arduino.h" + +// Pin number +const PinName digitalPin[] = { + PC_5, + PC_4, + PA_10, + PB_3, + PB_5, + PB_4, + PB_14, + PA_8, + PA_9, + PC_7, + PB_0, + PA_7, + PA_6, + PA_5, + PB_9, + PB_8, + // ST Morpho + // CN7 Left Side + PC_10, + PC_12, + PA_14, + PD_0, + PD_3, + PA_13, + PD_4, + PA_15, + PB_7, + PC_13, + PC_14, + PC_15, + PF_0, + PF_1, + PC_2, + PC_3, + // CN7 Right Side + PC_11, + PD_2, + PD_1, + PD_5, + // CN10 Left Side + PC_9, + // CN10 Right side + PC_8, + PC_6, + PA_3, + PD_6, + PA_12, + PA_11, + PC_1, + PC_0, + PB_2, + PB_6, + PB_15, + PB_10, + PB_13, + PA_2, + PD_8, + PD_9, + PA_0, + PA_1, + PA_4, + PB_1, + PB_11, + PB_12, + PF_2, + PA_9_R, + PA_10_R +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 53, //A0 + 54, //A1 + 55, //A2 + 56, //A3 + 57, //A4 + 58, //A5 + 11, //A6 + 12, //A7 + 45, //A8 + 48, //A9 + 0, //A10 + 1, //A11 + 10, //A12 + 13, //A13 - LED + 39, //A14 - STLINK RX + 50 //A15 - STLINK TX +}; + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; + RCC_OscInitStruct.PLL.PLLN = 8; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + Error_Handler(); + } + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_NUCLEO_G0B1RE */ diff --git a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/variant_NUCLEO_G0B1RE.h b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/variant_NUCLEO_G0B1RE.h new file mode 100644 index 0000000000..6afce45fe5 --- /dev/null +++ b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/variant_NUCLEO_G0B1RE.h @@ -0,0 +1,194 @@ +/* + ******************************************************************************* + * Copyright (c) 2021, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PC5 PIN_A10 +#define PC4 PIN_A11 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB14 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB0 PIN_A12 +#define PA7 PIN_A6 +#define PA6 PIN_A7 +#define PA5 PIN_A13 // LED +#define PB9 14 +#define PB8 15 +// ST Morpho +// CN7 Left Side +#define PC10 16 +#define PC12 17 +#define PA14 18 // SWD +#define PD0 19 +#define PD3 20 +#define PA13 21 // SWD +#define PD4 22 +#define PA15 23 +#define PB7 24 +#define PC13 25 +#define PC14 26 +#define PC15 27 +#define PF0 28 +#define PF1 29 +#define PC2 30 +#define PC3 31 +// CN7 Right Side +#define PC11 32 +#define PD2 33 +#define PD1 34 +#define PD5 35 +// CN10 Left Side +#define PC9 36 +// CN10 Right side +#define PC8 37 +#define PC6 38 +#define PA3 PIN_A14 +#define PD6 40 +#define PA12 41 +#define PA11 42 +#define PC1 43 +#define PC0 44 +#define PB2 PIN_A8 +#define PB6 46 +#define PB15 47 +#define PB10 PIN_A9 +#define PB13 49 +#define PA2 PIN_A15 +#define PD8 51 +#define PD9 52 +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA4 PIN_A2 +#define PB1 PIN_A3 +#define PB11 PIN_A4 +#define PB12 PIN_A5 +#define PF2 59 +#define PA9_R 60 +#define PA10_R 61 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA6_ALT2 (PA6 | ALT2) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA9_R_ALT1 (PA9_R | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA10_R_ALT1 (PA10_R | ALT1) +#define PA14_ALT1 (PA14 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PD4_ALT1 (PD4 | ALT1) + +#define NUM_DIGITAL_PINS 62 +#define NUM_REMAP_PINS 2 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PA5 +#endif +#define LED_GREEN LED_BUILTIN + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 //Connected to ST-Link +#endif + +// Default pin used for 'Serial' instance (ex: ST-Link) +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #define SERIAL_PORT_MONITOR Serial + #define SERIAL_PORT_HARDWARE Serial2 +#endif