diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h
index cddbae10c0..0f7b82a572 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h
@@ -16066,7 +16066,7 @@ typedef struct
/****************** Bit definition for SYSCFG_CSLCKR register ***************/
#define SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos (0U)
#define SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos)/*!< 0x00000001 */
-#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vectror table address, handling of system faults */
+#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */
#define SYSCFG_CSLCKR_LOCKSMPU_Pos (1U)
#define SYSCFG_CSLCKR_LOCKSMPU_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */
#define SYSCFG_CSLCKR_LOCKSMPU SYSCFG_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l562xx.h b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l562xx.h
index 4fbb2bc811..03bc23f9ea 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l562xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l562xx.h
@@ -16805,7 +16805,7 @@ typedef struct
/****************** Bit definition for SYSCFG_CSLCKR register ***************/
#define SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos (0U)
#define SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos)/*!< 0x00000001 */
-#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vectror table address, handling of system faults */
+#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */
#define SYSCFG_CSLCKR_LOCKSMPU_Pos (1U)
#define SYSCFG_CSLCKR_LOCKSMPU_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */
#define SYSCFG_CSLCKR_LOCKSMPU SYSCFG_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l5xx.h b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l5xx.h
index 05aa446d20..c558ff45bb 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l5xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l5xx.h
@@ -78,7 +78,7 @@
*/
#define __STM32L5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32L5_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
-#define __STM32L5_CMSIS_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
+#define __STM32L5_CMSIS_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
#define __STM32L5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32L5_CMSIS_VERSION ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\
|(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Release_Notes.html
index 04c9169e72..78a8275361 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Release_Notes.html
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Release_Notes.html
@@ -43,12 +43,41 @@
Purpose
Update History
-
+
Main Changes
Maintenance release
Contents
+
Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.
+
Add the READONLY tag to sections containing lookup tables to avoid GCC12 linker warnings if a segment is marked RWX.
+
+
Notes
+
Reminder:
+
+
When TrustZone is enabled in the system (Flash option bit TZEN=1)
+
+
template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core).
+
default Security Attribute Unit (SAU) configuration in the partition_stm32l552xx.h and partition_stm32l562xx.h:
+
+
SAU region 0: 0x0C03E000-0x0C03FFFF (Secure, Non-Secure Callable)
+
SAU region 1: 0x08040000-0x0807FFFF (Non-Secure FLASH Bank2 (256 Kbytes))
+
SAU region 2: 0x20018000-0x2003FFFF (Non-Secure RAM (2nd half SRAM1 + SRAM2 (160 Kbytes)))
+
SAU region 3: 0x40000000-0x4FFFFFFF (Non-Secure Peripheral mapped memory)
+
SAU region 4: 0x60000000-0x9FFFFFFF (Non-Secure external memories)
+
SAU region 5: 0x0BF90000-0x0BFA8FFF (Non-Secure System memory)
+
+
+
+
+
+
+
+
+
Main Changes
+
Maintenance release
+
Contents
+
General updates to fix known defects and implementation enhancements.
All source files: update disclaimer to add reference to the new license agreement.
Add new atomic register access macros in stm32l5xx.h file.
@@ -56,7 +85,7 @@
Contents
Add missing parameter after @param in order to fix warning in generated documentation
Change addresses of ROM symbols in sram.icf template files to code region alias in order to increase performance while running code from SRAM
-
Notes
+
Notes
Reminder:
When TrustZone is enabled in the system (Flash option bit TZEN=1)
@@ -78,9 +107,9 @@
Notes
-
Main Changes
+
Main Changes
Maintenance release
-
Contents
+
Contents
Maintenance release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices
stm32l552xx.h and stm32l562xx.h updates
@@ -89,7 +118,7 @@
Contents
Fix I2C4_EV_IRQn and I2C4_ER_IRQn order in IRQn_Type
-
Notes
+
Notes
Reminder:
When TrustZone is enabled in the system (Flash option bit TZEN=1)
@@ -111,9 +140,9 @@
Notes
-
Main Changes
+
Main Changes
Fourth release
-
Contents
+
Contents
Fourth release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices
stm32l552xx.h and stm32l562xx.h updates
@@ -129,7 +158,7 @@
Contents
Add README.md and License.md files for GitHub publication
Misspelled words corrections in driver descriptions
-
Notes
+
Notes
Reminder:
When TrustZone is enabled in the system (Flash option bit TZEN=1)
@@ -151,9 +180,9 @@
Notes
-
Main Changes
+
Main Changes
Third release
-
Contents
+
Contents
Third official release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices
stm32l552xx.h and stm32l562xx.h updates
@@ -163,7 +192,7 @@
Contents
Align DBGMCU_APB2FZR register and bits definitions with RM0438
-
Notes
+
Notes
Reminder:
When TrustZone is enabled in the system (Flash option bit TZEN=1)
@@ -185,9 +214,9 @@
Notes
-
Main Changes
+
Main Changes
Second release
-
Contents
+
Contents
Second official release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices
Templates system_stm32l5xx.c, system_stm32l5xx_s.c and system_stm32l5xx_ns.c
@@ -195,7 +224,7 @@
Contents
Add vector table relocation capability with conditional USER_VECT_TAB_ADDRESS
-
Notes
+
Notes
Reminder:
When TrustZone is enabled in the system (Flash option bit TZEN=1)
@@ -217,9 +246,9 @@
Notes
-
Main Changes
+
Main Changes
First release
-
Contents
+
Contents
First official release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices
Templates
@@ -237,7 +266,7 @@
Contents
Linker files for 256 and 512 Kbytes Flash device configurations
-
Notes
+
Notes
When TrustZone is enabled in the system (Flash option bit TZEN=1), template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH.ld
index 1ec9e7e3ae..7ee9e3f596 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH.ld
@@ -87,13 +87,15 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >ROM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -101,7 +103,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -110,7 +112,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -120,7 +122,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH_ns.ld
index be0c7bf17a..c30c545df0 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH_ns.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH_ns.ld
@@ -86,13 +86,15 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >ROM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -100,7 +102,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -109,7 +111,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -119,7 +121,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH_s.ld
index 81997f6aac..612fa0e574 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH_s.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xC_FLASH_s.ld
@@ -88,13 +88,15 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >ROM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -102,7 +104,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -111,7 +113,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -121,7 +123,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH.ld
index 68e5b5cb81..722b908050 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH.ld
@@ -87,13 +87,15 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >ROM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -101,7 +103,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -110,7 +112,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -120,7 +122,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH_ns.ld
index 9960e338e0..da2358621a 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH_ns.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH_ns.ld
@@ -86,13 +86,15 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >ROM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -100,7 +102,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -109,7 +111,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -119,7 +121,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH_s.ld
index 082bb7fdca..cfcf621cd0 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH_s.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xE_FLASH_s.ld
@@ -88,13 +88,15 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >ROM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -102,7 +104,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -111,7 +113,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -121,7 +123,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM.ld
index defba7c5b2..5af607c74a 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM.ld
@@ -85,13 +85,15 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >RAM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -99,7 +101,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -108,7 +110,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -118,7 +120,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM_ns.ld
index cbac7c2a7c..276b34037c 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM_ns.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM_ns.ld
@@ -84,13 +84,15 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >RAM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -98,7 +100,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -107,7 +109,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -117,7 +119,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM_s.ld
index a456d2f3b2..012a04c913 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM_s.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L552xx_RAM_s.ld
@@ -86,13 +86,15 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >RAM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -100,7 +102,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -109,7 +111,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -119,7 +121,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH.ld
index 68e5b5cb81..722b908050 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH.ld
@@ -87,13 +87,15 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >ROM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -101,7 +103,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -110,7 +112,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -120,7 +122,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH_ns.ld
index 9960e338e0..da2358621a 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH_ns.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH_ns.ld
@@ -86,13 +86,15 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >ROM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -100,7 +102,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -109,7 +111,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -119,7 +121,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH_s.ld
index 082bb7fdca..cfcf621cd0 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH_s.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xE_FLASH_s.ld
@@ -88,13 +88,15 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >ROM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -102,7 +104,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -111,7 +113,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -121,7 +123,7 @@ SECTIONS
. = ALIGN(8);
} >ROM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM.ld
index defba7c5b2..5af607c74a 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM.ld
@@ -85,13 +85,15 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >RAM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -99,7 +101,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -108,7 +110,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -118,7 +120,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM_ns.ld
index cbac7c2a7c..276b34037c 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM_ns.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM_ns.ld
@@ -84,13 +84,15 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >RAM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -98,7 +100,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -107,7 +109,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -117,7 +119,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM_s.ld
index a456d2f3b2..012a04c913 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM_s.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/linker/STM32L562xx_RAM_s.ld
@@ -86,13 +86,15 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .ARM.extab : {
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(8);
} >RAM
- .ARM : {
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
. = ALIGN(8);
__exidx_start = .;
*(.ARM.exidx*)
@@ -100,7 +102,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .preinit_array :
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -109,7 +111,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .init_array :
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__init_array_start = .);
@@ -119,7 +121,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
- .fini_array :
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
{
. = ALIGN(8);
PROVIDE_HIDDEN (__fini_array_start = .);
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/startup_stm32l552xx.s b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/startup_stm32l552xx.s
index b89c8de2bd..e595eef79f 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/startup_stm32l552xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/startup_stm32l552xx.s
@@ -124,7 +124,6 @@ Infinite_Loop:
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
@@ -254,6 +253,7 @@ g_pfnVectors:
.word ICACHE_IRQHandler
.word 0
+ .size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/startup_stm32l562xx.s b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/startup_stm32l562xx.s
index df4b621912..1c6e35a626 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/startup_stm32l562xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/startup_stm32l562xx.s
@@ -124,7 +124,6 @@ Infinite_Loop:
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
@@ -254,6 +253,7 @@ g_pfnVectors:
.word ICACHE_IRQHandler
.word OTFDEC1_IRQHandler
+ .size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
index 8b5055d8db..13fff7038b 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
+++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
@@ -14,7 +14,7 @@
* STM32L0: 1.9.3
* STM32L1: 2.3.3
* STM32L4: 1.7.3
- * STM32L5: 1.0.5
+ * STM32L5: 1.0.6
* STM32MP1: 1.6.0
* STM32U5: 1.3.1
* STM32WB: 1.12.0
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index ca13bba17f..e4e114e98c 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -37,16 +37,12 @@ extern "C" {
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
+#if defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
-#if defined(STM32U5)
-#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
-#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
-#endif /* STM32U5 */
-#endif /* STM32U5 || STM32H7 || STM32MP1 */
+#endif /* STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -113,6 +109,9 @@ extern "C" {
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
#endif /* STM32U5 */
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
/**
* @}
*/
@@ -140,7 +139,8 @@ extern "C" {
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
+ input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
@@ -239,10 +239,12 @@ extern "C" {
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
-#if defined(STM32C0)
+#if defined(STM32H5) || defined(STM32C0)
#else
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
+ inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
+ inter STM32 series compatibility */
#endif
/**
* @}
@@ -273,7 +275,7 @@ extern "C" {
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
@@ -285,7 +287,13 @@ extern "C" {
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
#endif
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
+ defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -350,7 +358,8 @@ extern "C" {
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
+ defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
@@ -582,6 +591,106 @@ extern "C" {
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII SBS_ETH_MII
+#define SYSCFG_ETH_RMII SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU SBS_SAU
+#define SYSCFG_MPU_SEC SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK SBS_CLK
+#define SYSCFG_CLASSB SBS_CLASSB
+#define SYSCFG_FPU SBS_FPU
+#define SYSCFG_ALL SBS_ALL
+
+#define SYSCFG_SEC SBS_SEC
+#define SYSCFG_NSEC SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+
/**
* @}
*/
@@ -649,14 +758,16 @@ extern "C" {
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
+ STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
+ defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
@@ -678,8 +789,10 @@ extern "C" {
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
-#if defined(STM32U5)
+#if defined(STM32U5) || defined(STM32H5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */
@@ -694,7 +807,23 @@ extern "C" {
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
#endif /* STM32U5 */
-
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
/**
* @}
*/
@@ -875,7 +1004,8 @@ extern "C" {
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
+ defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@@ -1109,6 +1239,26 @@ extern "C" {
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H5)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 */
+
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+
+#if defined(STM32H5) || defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA */
+
#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
@@ -1119,12 +1269,12 @@ extern "C" {
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#endif /* STM32H7 */
-#if defined(STM32F7) || defined(STM32H7)
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
-#endif /* STM32F7 || STM32H7 */
+#endif /* STM32F7 || STM32H7 || STM32L0 */
/**
* @}
@@ -1291,7 +1441,7 @@ extern "C" {
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
-#if defined(STM32U5) || defined(STM32MP2)
+#if defined(STM32U5)
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
#endif
@@ -1404,30 +1554,40 @@ extern "C" {
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
+ the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
+ MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
+ or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
+ of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
+ transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
+ frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
+ de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
+ activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
+ (or time-stamp) */
#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
+ status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
@@ -1435,6 +1595,8 @@ extern "C" {
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
+
/**
* @}
*/
@@ -1598,7 +1760,8 @@ extern "C" {
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
- )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
+ HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1607,8 +1770,10 @@ extern "C" {
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
+ HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
+ defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
@@ -1642,16 +1807,21 @@ extern "C" {
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
- )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
+ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
+ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
+ defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+ defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
+ STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
+ defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
@@ -1776,6 +1946,17 @@ extern "C" {
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
+
+
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
@@ -1784,6 +1965,8 @@ extern "C" {
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
+
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
@@ -1794,6 +1977,7 @@ extern "C" {
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
#endif
@@ -1802,6 +1986,20 @@ extern "C" {
* @}
*/
+/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32WBA)
+#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA */
+
+/**
+ * @}
+ */
+
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
@@ -1827,7 +2025,8 @@ extern "C" {
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
+ defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@@ -2084,7 +2283,8 @@ extern "C" {
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
+ defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
@@ -2256,8 +2456,10 @@ extern "C" {
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
/**
* @}
*/
@@ -2416,7 +2618,9 @@ extern "C" {
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -2425,8 +2629,12 @@ extern "C" {
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
+ HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
+ } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
+ HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
+ } while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@@ -2462,8 +2670,8 @@ extern "C" {
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
+ HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -3436,7 +3644,8 @@ extern "C" {
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+ defined(STM32WL) || defined(STM32C0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3581,6 +3790,92 @@ extern "C" {
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
#endif /* STM32U5 */
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
+
+
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3597,9 +3892,9 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
- defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
- defined (STM32C0)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
+ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+ defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3634,6 +3929,13 @@ extern "C" {
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
+#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
+ defined (STM32H7) || \
+ defined (STM32L0) || defined (STM32L1) || \
+ defined (STM32WB)
+#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
+#endif
+
#define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER
@@ -3652,6 +3954,11 @@ extern "C" {
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3910,6 +4217,9 @@ extern "C" {
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+
+#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_comp.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_comp.h
index d84f3dabb9..28941f8857 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_comp.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_comp.h
@@ -50,7 +50,8 @@ typedef struct
uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances
(2 consecutive instances odd and even COMP and COMP).
- Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
+ Note: HAL COMP driver allows to set window mode from any COMP
+ instance of the pair of COMP instances composing window mode.
This parameter can be a value of @ref COMP_WindowMode */
uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed.
@@ -151,15 +152,25 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @}
*/
+
/** @defgroup COMP_WindowMode COMP Window Mode
* @{
*/
-#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
-#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators
+ instances pair COMP1 and COMP2 are
+ independent */
+#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances
+ pair COMP1 and COMP2 have their input
+ plus connected together.
+ The common input is COMP1 input plus
+ (COMP2 input plus is no more accessible).
+ */
/**
* @}
*/
+
+
/** @defgroup COMP_PowerMode COMP power mode
* @{
*/
@@ -302,14 +313,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __HANDLE__ COMP handle
* @retval None
*/
-#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
/**
* @brief Disable the specified comparator.
* @param __HANDLE__ COMP handle
* @retval None
*/
-#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
/**
* @brief Lock the specified comparator configuration.
@@ -320,14 +331,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __HANDLE__ COMP handle
* @retval None
*/
-#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
+#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
/**
* @brief Check whether the specified comparator is locked.
* @param __HANDLE__ COMP handle
* @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
*/
-#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
+#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
/**
* @}
@@ -336,7 +347,6 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** @defgroup COMP_Exti_Management COMP external interrupt line management
* @{
*/
-
/**
* @brief Enable the COMP1 EXTI line rising edge trigger.
* @retval None
@@ -365,19 +375,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
- LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
- } while(0)
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
+ LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
+ } while(0)
/**
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
- LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
- } while(0)
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
+ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\
+ } while(0)
/**
* @brief Enable the COMP1 EXTI line in interrupt mode.
@@ -461,19 +471,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
- LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
- } while(0)
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
+ LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
+ } while(0)
/**
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
- LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
- } while(0)
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
+ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\
+ } while(0)
/**
* @brief Enable the COMP2 EXTI line in interrupt mode.
@@ -609,7 +619,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
-/* compatibility with other STM32 families. */
+/* compatibility with other STM32 series. */
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
@@ -628,7 +638,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
((__POL__) == COMP_OUTPUTPOL_INVERTED))
#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \
- ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \
+ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \
@@ -638,17 +648,17 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
)
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- ((((__INSTANCE__) == COMP1) && \
+ ((((__INSTANCE__) == COMP1) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \
- || \
- (((__INSTANCE__) == COMP2) && \
- (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
+ || \
+ (((__INSTANCE__) == COMP2) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cortex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cortex.h
index 49618fae54..92637832f7 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cortex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cortex.h
@@ -277,11 +277,15 @@ void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
+void HAL_MPU_EnableRegion(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit);
void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit);
#ifdef MPU_NS
void HAL_MPU_Enable_NS(uint32_t MPU_Control);
void HAL_MPU_Disable_NS(void);
+void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit);
void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit);
#endif /* MPU_NS */
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_crc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_crc.h
index ba06e3ebfe..f9785e732a 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_crc.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_crc.h
@@ -318,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp.h
index 8f11c49f8e..c4b9a39158 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp.h
@@ -53,7 +53,8 @@ typedef struct
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
- 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
+ 128 or 256 bit key length in TinyAES
+ This parameter can be a value of @ref CRYP_Key_Size */
uint32_t *pKey; /*!< The key used for encryption/decryption */
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
@@ -96,7 +97,7 @@ typedef enum
{
HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */
HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */
-}HAL_SuspendTypeDef;
+} HAL_SuspendTypeDef;
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
/**
@@ -407,7 +408,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
* @arg CRYP_FLAG_OFFU: Output FIFO is full
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The state of __FLAG__ (TRUE or FALSE).
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define CRYP_FLAG_MASK 0x0000001FU
@@ -434,7 +435,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
* @retval State of interruption (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR &\
+ (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Check whether the specified CRYP interrupt is set or not.
* @param __HANDLE__ specifies the CRYP handle.
@@ -503,7 +505,8 @@ void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+ pCRYP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
@@ -520,8 +523,10 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
*/
/* encryption/decryption ***********************************/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
@@ -579,11 +584,11 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
- (((((ALGO) == CRYP_AES_CTR)) && \
- ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
- (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
- (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
- ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
+ (((((ALGO) == CRYP_AES_CTR)) && \
+ ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
+ (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
+ (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
+ ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp_ex.h
index df09b0200b..238cc06022 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp_ex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp_ex.h
@@ -73,8 +73,8 @@ extern "C" {
*/
/**
- * @}
- */
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac.h
index 14fe07ad65..f91e1883d1 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac.h
@@ -78,19 +78,19 @@ typedef struct
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
- void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac);
+ void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
@@ -130,7 +130,7 @@ typedef struct
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
- uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
+ uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
@@ -276,9 +276,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
* @{
*/
-#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
-#define DAC_CHIPCONNECT_INTERNAL (1UL << 1)
-#define DAC_CHIPCONNECT_BOTH (1UL << 2)
+#define DAC_CHIPCONNECT_DISABLE (0x00000000UL)
+#define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0)
/**
* @}
@@ -479,7 +478,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
@@ -505,8 +504,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA
* @{
*/
/* Peripheral Control functions ***********************************************/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
+ const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
@@ -515,8 +515,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
* @{
*/
/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
+uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
/**
* @}
@@ -552,5 +552,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
#endif /* STM32L5xx_HAL_DAC_H */
-
-
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac_ex.h
index b01a4b595c..ba0fda190f 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac_ex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac_ex.h
@@ -81,6 +81,7 @@ extern "C" {
* @}
*/
+
/**
* @}
*/
@@ -122,9 +123,8 @@ extern "C" {
#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
-#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
- ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
- ((CONNECT) == DAC_CHIPCONNECT_BOTH))
+#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
+ ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
((TRIMMING) == DAC_TRIMMING_USER))
@@ -174,16 +174,18 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
- uint32_t Alignment);
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
+ const uint32_t *pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
+uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
+
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
+
/**
* @}
*/
@@ -196,7 +198,7 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue);
-uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
/**
* @}
@@ -235,4 +237,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
#endif
#endif /* STM32L5xx_HAL_DAC_EX_H */
-
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_def.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_def.h
index a722eb5519..034c7fb938 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_def.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_def.h
@@ -59,7 +59,9 @@ typedef enum
/* Exported macros -----------------------------------------------------------*/
+#if !defined(UNUSED)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+#endif /* UNUSED */
#define HAL_MAX_DELAY 0xFFFFFFFFU
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_fdcan.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_fdcan.h
index 2464c3c76e..789547a6e5 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_fdcan.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_fdcan.h
@@ -318,53 +318,55 @@ typedef struct
typedef struct
{
uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
- This parameter can be a value of @ref FDCAN_protocol_error_code */
+ This parameter can be a value of @ref FDCAN_protocol_error_code */
uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
of a CAN FD format frame with its BRS flag set.
- This parameter can be a value of @ref FDCAN_protocol_error_code */
+ This parameter can be a value of @ref FDCAN_protocol_error_code */
uint32_t Activity; /*!< Specifies the FDCAN module communication state.
- This parameter can be a value of @ref FDCAN_communication_state */
+ This parameter can be a value of @ref FDCAN_communication_state */
uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
This parameter can be:
- 0 : The FDCAN is in Error_Active state
- - 1 : The FDCAN is in Error_Passive state */
+ - 1 : The FDCAN is in Error_Passive state */
uint32_t Warning; /*!< Specifies the FDCAN module warning status.
This parameter can be:
- - 0 : error counters (RxErrorCnt and TxErrorCnt)
- are below the Error_Warning limit of 96
- - 1 : at least one of error counters has reached the Error_Warning limit of 96 */
+ - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the
+ Error_Warning limit of 96
+ - 1 : at least one of error counters has reached the Error_Warning
+ limit of 96 */
uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
This parameter can be:
- 0 : The FDCAN is not in Bus_Off state
- - 1 : The FDCAN is in Bus_Off state */
+ - 1 : The FDCAN is in Bus_Off state */
uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
This parameter can be:
- 0 : Last received CAN FD message did not have its ESI flag set
- - 1 : Last received CAN FD message had its ESI flag set */
+ - 1 : Last received CAN FD message had its ESI flag set */
uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
This parameter can be:
- 0 : Last received CAN FD message did not have its BRS flag set
- - 1 : Last received CAN FD message had its BRS flag set */
+ - 1 : Last received CAN FD message had its BRS flag set */
uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received
- since last protocol status.This parameter can be:
+ since last protocol status.
+ This parameter can be:
- 0 : No CAN FD message received
- - 1 : CAN FD message received */
+ - 1 : CAN FD message received */
uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
This parameter can be:
- 0 : No protocol exception event occurred since last read access
- - 1 : Protocol exception event occurred */
+ - 1 : Protocol exception event occurred */
uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
- This parameter can be a number between 0 and 127 */
+ This parameter can be a number between 0 and 127 */
} FDCAN_ProtocolStatusTypeDef;
@@ -374,22 +376,24 @@ typedef struct
typedef struct
{
uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
- This parameter can be a number between 0 and 255 */
+ This parameter can be a number between 0 and 255 */
uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
- This parameter can be a number between 0 and 127 */
+ This parameter can be a number between 0 and 127 */
uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
This parameter can be:
- - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
- - 1 : The Receive Error Counter (RxErrorCnt)
- has reached the error passive level of 128 */
+ - 0 : The Receive Error Counter (RxErrorCnt) is below the error
+ passive level of 128
+ - 1 : The Receive Error Counter (RxErrorCnt) has reached the error
+ passive level of 128 */
uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
This parameter can be a number between 0 and 255.
- This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
- or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
- TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
+ This counter is incremented each time when a FDCAN protocol error causes
+ the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255;
+ the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag
+ FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
} FDCAN_ErrorCountersTypeDef;
@@ -604,21 +608,21 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan,
* @{
*/
#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
-#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
-#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
-#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
-#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
-#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
-#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
-#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
-#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
-#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
-#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
-#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
-#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
-#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
-#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
-#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
+#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */
+#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */
+#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */
+#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */
+#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */
+#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */
+#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */
+#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
/**
* @}
*/
@@ -1040,7 +1044,7 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan,
* @retval None
*/
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
-#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
@@ -1167,7 +1171,7 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h
* @{
*/
/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig);
HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
uint32_t RejectRemoteExt);
@@ -1177,13 +1181,13 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint3
HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
-uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
uint32_t TimeoutPeriod);
HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
uint32_t TdcFilter);
@@ -1203,21 +1207,23 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
/* Control functions **********************************************************/
HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
- uint8_t *pTxData);
-uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+ const uint8_t *pTxData);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
-HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
-HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
-HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
-uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
-uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
-uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
-uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_ErrorCountersTypeDef *ErrorCounters);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
/**
* @}
@@ -1259,8 +1265,8 @@ void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorSt
* @{
*/
/* Peripheral State functions *************************************************/
-uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
-HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan);
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_i2c.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_i2c.h
index 78ee9b6333..b6c59c9e75 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_i2c.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_i2c.h
@@ -118,8 +118,6 @@ typedef enum
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
- HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
- HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
@@ -207,6 +205,7 @@ typedef struct __I2C_HandleTypeDef
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
@@ -709,9 +708,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
/**
* @}
@@ -804,8 +803,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
- (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
- (~I2C_CR2_RD_WRN)))
+ (I2C_CR2_ADD10) | (I2C_CR2_START) | \
+ (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_icache.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_icache.h
index 419c2d5562..769e524bce 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_icache.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_icache.h
@@ -27,6 +27,7 @@ extern "C" {
/* Includes -----------------------------------------------------------------*/
#include "stm32l5xx_hal_def.h"
+#if defined(ICACHE)
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
@@ -284,6 +285,7 @@ HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region);
/**
* @}
*/
+#endif /* ICACHE */
#ifdef __cplusplus
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_lptim.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_lptim.h
index 05475dae12..0e1a57eb1a 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_lptim.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_lptim.h
@@ -453,6 +453,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @brief Write the passed parameter in the Autoreload register.
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value
+ * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF.
* @retval None
* @note The ARR register can only be modified when the LPTIM instance is enabled.
*/
@@ -780,7 +781,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_
* @{
*/
/* Peripheral State functions ************************************************/
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
@@ -873,9 +874,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\
- ((__AUTORELOAD__) <= 0x0000FFFFUL))
-
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc.h
index 556d17dd74..3f4914d076 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc.h
@@ -30,6 +30,7 @@ extern "C" {
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
+#if defined (SDMMC1) || defined (SDMMC2)
/** @addtogroup MMC
* @{
@@ -121,7 +122,7 @@ typedef struct
HAL_LockTypeDef Lock; /*!< MMC locking object */
- uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
@@ -135,6 +136,8 @@ typedef struct
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
+ __IO uint16_t RPMBErrorCode; /*!< MMC RPMB Area Error codes */
+
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
uint32_t CSD[4U]; /*!< MMC card specific data table */
@@ -276,45 +279,55 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc);
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
* @{
*/
-#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
-#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
-#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
-#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
-#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
-#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
-#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
-#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */
+#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
+#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
+#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
+#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
+#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
+#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
+#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
+#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
+#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */
/*!< number of transferred bytes does not match the block length */
-#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
-#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
-#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */
+#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
+#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
+#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
+#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */
/*!< command or if there was an attempt to access a locked card */
-#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
-#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
-#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
-#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
-#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
-#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
-#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
-#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
-#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
-#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */
+#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
+#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
+#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
+#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
+#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
+#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
+#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
+#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
+#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
+#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
+#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */
/*!< of erase sequence command was received */
-#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
-#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
-#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
-#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
-#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
-#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
-#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
-#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
-#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
+#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
+#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
+#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
+#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
+#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
+#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
+#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
+#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+/*!< response results after operating with RPMB partition */
+#define HAL_MMC_ERROR_RPMB_OPERATION_OK 0x0000U /*!< Operation OK */
+#define HAL_MMC_ERROR_RPMB_GENERAL_FAILURE 0x0001U /*!< General failure */
+#define HAL_MMC_ERROR_RPMB_AUTHENTICATION_FAILURE 0x0002U /*!< Authentication failure */
+#define HAL_MMC_ERROR_RPMB_COUNTER_FAILURE 0x0003U /*!< Counter failure */
+#define HAL_MMC_ERROR_RPMB_ADDRESS_FAILURE 0x0004U /*!< Address failure */
+#define HAL_MMC_ERROR_RPMB_WRITE_FAILURE 0x0005U /*!< Write failure */
+#define HAL_MMC_ERROR_RPMB_READ_FAILURE 0x0006U /*!< Read failure */
+#define HAL_MMC_ERROR_RPMB_KEY_NOT_YET_PROG 0x0007U /*!< Authentication Key not yet programmed */
+#define HAL_MMC_ERROR_RPMB_COUNTER_EXPIRED 0x0080U /*!< Write Counter has expired i.e. reached its max value */
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
+#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @}
@@ -399,6 +412,19 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc);
* @}
*/
+/** @defgroup MMC_Exported_Constansts_Group7 MMC Partitions types
+ * @{
+ */
+typedef uint32_t HAL_MMC_PartitionTypeDef;
+
+#define HAL_MMC_USER_AREA_PARTITION 0x00000000U /*!< User area partition */
+#define HAL_MMC_BOOT_PARTITION1 0x00000100U /*!< Boot partition 1 */
+#define HAL_MMC_BOOT_PARTITION2 0x00000200U /*!< Boot partition 2 */
+#define HAL_MMC_RPMB_PARTITION 0x00000300U /*!< RPMB partition */
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -647,19 +673,20 @@ void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
- uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
@@ -685,6 +712,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca
*/
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode);
+HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition);
/**
* @}
*/
@@ -704,8 +732,9 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
* @{
*/
-HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
-uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
+HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc);
+uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc);
+uint32_t HAL_MMC_GetRPMBError(const MMC_HandleTypeDef *hmmc);
/**
* @}
*/
@@ -739,6 +768,29 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
+
+/** @defgroup MMC_Exported_Functions_Group9 Replay Protected Memory Block management
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pKey,
+ uint32_t Timeout);
+uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout);
+uint32_t HAL_MMC_RPMB_GetWriteCounter_IT(MMC_HandleTypeDef *hmmc, uint8_t *pNonce);
+HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd,
+ uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd,
+ uint16_t NumberOfBlocks, const uint8_t *pMAC);
+HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd,
+ uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd,
+ uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC);
+
+/**
+ * @}
+ */
+
/* Private types -------------------------------------------------------------*/
/** @defgroup MMC_Private_Types MMC Private Types
* @{
@@ -811,6 +863,7 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
+#endif /* SDMMC1 || SDMMC2 */
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc_ex.h
index 6d03782f7b..26c783b2c2 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc_ex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc_ex.h
@@ -30,7 +30,7 @@ extern "C" {
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
-
+#if defined (SDMMC1) || defined (SDMMC2)
/** @addtogroup MMCEx
* @brief SD HAL extended module driver
* @{
@@ -100,6 +100,7 @@ void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
+#endif /* SDMMC1 || SDMMC2 */
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nand.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nand.h
index 8c06a85543..3b2bf58cc2 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nand.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nand.h
@@ -104,9 +104,8 @@ typedef struct
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
parameter is mandatory for some NAND parts after the read
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
- Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
- Please check the Read Mode sequnece in the NAND device datasheet */
+ Please check the Read Mode sequence in the NAND device datasheet */
} NAND_DeviceConfigTypeDef;
/**
@@ -126,7 +125,7 @@ typedef struct
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
- NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
+ NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
@@ -214,27 +213,27 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
@@ -264,8 +263,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
* @{
*/
/* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nor.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nor.h
index bae5d189dc..2846393339 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nor.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nor.h
@@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
*/
/* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_ospi.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_ospi.h
index 3b0ed8ce83..d8c73b0370 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_ospi.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_ospi.h
@@ -21,7 +21,7 @@
#define STM32L5xx_HAL_OSPI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -86,7 +86,7 @@ typedef struct
uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every
Refresh+1 clock cycles.
This parameter can be a value between 0 and 0xFFFFFFFF */
-}OSPI_InitTypeDef;
+} OSPI_InitTypeDef;
/**
* @brief HAL OSPI Handle Structure definition
@@ -107,21 +107,21 @@ typedef struct
__IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */
uint32_t Timeout; /*!< Timeout used for the OSPI external device access */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
- void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
+ void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
- void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi);
-
- void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi);
+ void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi);
+
+ void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
-}OSPI_HandleTypeDef;
+} OSPI_HandleTypeDef;
/**
* @brief HAL OSPI Regular Command Structure definition
@@ -172,7 +172,7 @@ typedef struct
This parameter can be a value of @ref OSPI_DQSMode */
uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
This parameter can be a value of @ref OSPI_SIOOMode */
-}OSPI_RegularCmdTypeDef;
+} OSPI_RegularCmdTypeDef;
/**
* @brief HAL OSPI Hyperbus Configuration Structure definition
@@ -187,7 +187,7 @@ typedef struct
This parameter can be a value of @ref OSPI_WriteZeroLatency */
uint32_t LatencyMode; /*!< It configures the latency mode.
This parameter can be a value of @ref OSPI_LatencyMode */
-}OSPI_HyperbusCfgTypeDef;
+} OSPI_HyperbusCfgTypeDef;
/**
* @brief HAL OSPI Hyperbus Command Structure definition
@@ -206,7 +206,7 @@ typedef struct
In case of autopolling mode, this parameter can be any value between 1 and 4 */
uint32_t DQSMode; /*!< It enables or not the data strobe management.
This parameter can be a value of @ref OSPI_DQSMode */
-}OSPI_HyperbusCmdTypeDef;
+} OSPI_HyperbusCmdTypeDef;
/**
* @brief HAL OSPI Auto Polling mode configuration structure definition
@@ -223,7 +223,7 @@ typedef struct
This parameter can be a value of @ref OSPI_AutomaticStop */
uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases.
This parameter can be any value between 0 and 0xFFFF */
-}OSPI_AutoPollingTypeDef;
+} OSPI_AutoPollingTypeDef;
/**
* @brief HAL OSPI Memory Mapped mode configuration structure definition
@@ -234,7 +234,7 @@ typedef struct
This parameter can be a value of @ref OSPI_TimeOutActivation */
uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select.
This parameter can be any value between 0 and 0xFFFF */
-}OSPI_MemoryMappedTypeDef;
+} OSPI_MemoryMappedTypeDef;
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
@@ -256,7 +256,7 @@ typedef enum
HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */
HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */
-}HAL_OSPI_CallbackIDTypeDef;
+} HAL_OSPI_CallbackIDTypeDef;
/**
* @brief HAL OSPI Callback pointer definition
@@ -744,10 +744,10 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
/** @addtogroup OSPI_Exported_Functions_Group1
* @{
*/
-HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi);
/**
* @}
@@ -758,7 +758,7 @@ void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi);
* @{
*/
/* OSPI IRQ handler function */
-void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi);
/* OSPI command configuration functions */
HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
@@ -779,25 +779,25 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoP
HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
/* OSPI memory-mapped mode functions */
-HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
+HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
/* Callback functions in non-blocking modes ***********************************/
-void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi);
void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
/* OSPI indirect mode functions */
-void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
/* OSPI status flag polling mode functions */
-void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi);
/* OSPI memory-mapped mode functions */
-void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi);
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/* OSPI callback registering/unregistering */
@@ -813,13 +813,13 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL
/** @addtogroup OSPI_Exported_Functions_Group3
* @{
*/
-HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold);
-uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout);
-uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi);
-uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold);
+uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout);
+uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi);
+uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi);
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_otfdec.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_otfdec.h
index 7c97f353b7..d95d23a88f 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_otfdec.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_otfdec.h
@@ -349,14 +349,14 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32
HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey);
HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode);
HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
- OTFDEC_RegionConfigTypeDef *Config, uint32_t lock);
-uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey);
+ const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock);
+uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey);
HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
HAL_StatusTypeDef HAL_OTFDEC_ConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t Attributes);
HAL_StatusTypeDef HAL_OTFDEC_EnableEnciphering(OTFDEC_HandleTypeDef *hotfdec);
HAL_StatusTypeDef HAL_OTFDEC_DisableEnciphering(OTFDEC_HandleTypeDef *hotfdec);
-HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *input,
+HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, const uint32_t *input,
uint32_t *output, uint32_t size, uint32_t start_address);
/**
* @}
@@ -365,9 +365,9 @@ HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t Regi
/** @addtogroup @addtogroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions
* @{
*/
-HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec);
+HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec);
HAL_StatusTypeDef HAL_OTFDEC_GetConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t *Attributes);
-uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
+uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
OTFDEC_RegionConfigTypeDef *Config);
/**
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd.h
index 897e2f0ef0..cd6c952200 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd.h
@@ -339,7 +339,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
/**
* @}
*/
@@ -348,7 +348,7 @@ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
/**
* @}
*/
@@ -806,20 +806,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
\
*(pdwReg) &= 0x3FFU; \
\
- if ((wCount) > 62U) \
+ if ((wCount) == 0U) \
{ \
- PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
+ *(pdwReg) |= USB_CNTRX_BLSIZE; \
+ } \
+ else if ((wCount) <= 62U) \
+ { \
+ PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
- if ((wCount) == 0U) \
- { \
- *(pdwReg) |= USB_CNTRX_BLSIZE; \
- } \
- else \
- { \
- PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
- } \
+ PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pka.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pka.h
index 627fa20113..bd642cf56d 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pka.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pka.h
@@ -541,8 +541,8 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka);
* @{
*/
/* Peripheral State and Error functions ***************************************/
-HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka);
-uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka);
+HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka);
+uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka);
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc.h
index 7892f24459..d949e973f6 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc.h
@@ -2935,25 +2935,36 @@ typedef struct
* This parameter can be one of the following values:
* @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
* 6 LSE oscillator clock cycles.
- * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
- * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
+ * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC.
+ * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral.
+ * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC.
+ * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral.
* @retval None
*/
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
do { \
- if((__STATE__) == RCC_LSE_ON) \
+ if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \
{ \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \
+ } \
+ else if((__STATE__) == RCC_LSE_ON) \
+ { \
+ SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \
+ } \
+ else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \
} \
else \
{ \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0)
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng.h
index 23bc320ce1..e91d76274d 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng.h
@@ -317,7 +317,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng);
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
@@ -330,8 +330,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
* @{
*/
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
+HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng);
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng_ex.h
index 30497d548c..967b2d6326 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng_ex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng_ex.h
@@ -196,14 +196,14 @@ typedef struct
*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
+/** @addtogroup RNG_Ex_Exported_Functions
* @{
*/
/** @addtogroup RNG_Ex_Exported_Functions_Group1
* @{
*/
-HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf);
HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd.h
index 2736371d9a..0bb5216581 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd.h
@@ -33,6 +33,7 @@ extern "C" {
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
+#if defined (SDMMC1) || defined (SDMMC2)
/** @defgroup SD SD
* @brief SD HAL module driver
@@ -126,7 +127,7 @@ typedef struct
HAL_LockTypeDef Lock; /*!< SD locking object */
- uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint32_t TxXferSize; /*!< SD Tx Transfer size */
@@ -315,12 +316,12 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */
- /*!< number of transferred bytes does not match the block length */
+/*!< number of transferred bytes does not match the block length */
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */
- /*!< command or if there was an attempt to access a locked card */
+/*!< command or if there was an attempt to access a locked card */
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
@@ -332,7 +333,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */
- /*!< of erase sequence command was received */
+/*!< of erase sequence command was received */
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
@@ -634,18 +635,18 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
- uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks);
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
@@ -701,8 +702,8 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInf
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
* @{
*/
-HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
+HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd);
+uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd);
/**
* @}
*/
@@ -787,6 +788,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
/**
* @}
*/
+#endif /* SDMMC1 || SDMMC2 */
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd_ex.h
index a1ffdfdffa..d85ad9b2e4 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd_ex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd_ex.h
@@ -30,6 +30,7 @@ extern "C" {
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
+#if defined (SDMMC1) || defined (SDMMC2)
/** @addtogroup SDEx
* @brief SD HAL extended module driver
@@ -98,6 +99,7 @@ void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd);
/**
* @}
*/
+#endif /* SDMMC1 || SDMMC2 */
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_smbus.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_smbus.h
index 577a9994f7..83f7bf2d6c 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_smbus.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_smbus.h
@@ -100,8 +100,6 @@ typedef struct
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
-#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
@@ -751,8 +749,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
*/
/* Peripheral State and Errors functions **************************************************/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_spi_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_spi_ex.h
index eff46ee0c7..bec870a521 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_spi_ex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_spi_ex.h
@@ -48,7 +48,7 @@ extern "C" {
/** @addtogroup SPIEx_Exported_Functions_Group1
* @{
*/
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sram.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sram.h
index 19ed6281fb..6c9857a5d0 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sram.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sram.h
@@ -204,7 +204,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
*/
/* SRAM State functions ******************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim.h
index cef5fbea74..842ae715fb 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim.h
@@ -402,29 +402,28 @@ typedef struct
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
@@ -1022,8 +1021,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
-#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
-#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
+#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
+#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
/**
* @}
*/
@@ -1838,6 +1837,10 @@ mode.
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
((__PRESCALER__) == TIM_ICPSC_DIV8))
+#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
+ ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
+ ((__CHANNEL__) != (TIM_CHANNEL_6)))
+
#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
((__MODE__) == TIM_OPMODE_REPETITIVE))
@@ -1858,8 +1861,9 @@ mode.
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
-#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
- ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
+ (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
+ ((__PERIOD__) > 0U))
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
@@ -1912,7 +1916,6 @@ mode.
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
-
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE))
@@ -1979,8 +1982,8 @@ mode.
((__MODE__) == TIM_OCMODE_PWM2) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
((__MODE__) == TIM_OCMODE_ACTIVE) || \
@@ -2260,7 +2263,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
* @{
*/
/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
@@ -2309,7 +2312,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim_ex.h
index de238d2aa9..1f796f2281 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim_ex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim_ex.h
@@ -332,7 +332,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
-HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput);
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tsc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tsc.h
index 64b563a22b..8cca483113 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tsc.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tsc.h
@@ -677,7 +677,8 @@ when the selected signal is detected on the SYNC input pin) */
((__VALUE__) == TSC_PG_PRESC_DIV128))
#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \
- ((__CTPL__) > TSC_CTPL_2CYCLES)) || \
+ (((__CTPL__) == TSC_CTPL_1CYCLE) || \
+ ((__CTPL__) > TSC_CTPL_2CYCLES))) || \
(((__PGPSC__) == TSC_PG_PRESC_DIV2) && \
((__CTPL__) > TSC_CTPL_1CYCLE)) || \
(((__PGPSC__) > TSC_PG_PRESC_DIV2) && \
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_uart_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_uart_ex.h
index 0eaa3d7d9f..3acb774c53 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_uart_ex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_uart_ex.h
@@ -178,7 +178,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
/**
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart.h
index 123cde4bb1..e614c81737 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart.h
@@ -142,7 +142,7 @@ typedef struct __USART_HandleTypeDef
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
- uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
+ uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value
of @ref USARTEx_Slave_Mode */
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart_ex.h
index 3a4c9c6d7c..594c37bafd 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart_ex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart_ex.h
@@ -45,7 +45,7 @@ extern "C" {
* @{
*/
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_wwdg.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_wwdg.h
index c162ea80c1..2182fa79c7 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_wwdg.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_wwdg.h
@@ -191,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__ WWDG handle
+ * @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_adc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_adc.h
index add395f501..5c5d4c9340 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_adc.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_adc.h
@@ -7857,7 +7857,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
*/
/* Initialization of some features of ADC common parameters and multimode */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_comp.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_comp.h
index 5f0e5ff3a1..6452b3e194 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_comp.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_comp.h
@@ -73,33 +73,33 @@ typedef struct
{
uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed.
This parameter can be a value of @ref COMP_LL_EC_POWERMODE
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_COMP_SetPowerMode(). */
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_COMP_SetInputPlus(). */
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_COMP_SetInputMinus(). */
uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_COMP_SetInputHysteresis(). */
uint32_t OutputPolarity; /*!< Set comparator output polarity.
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_COMP_SetOutputPolarity(). */
uint32_t OutputBlankingSource; /*!< Set comparator blanking source.
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_COMP_SetOutputBlankingSource(). */
} LL_COMP_InitTypeDef;
@@ -113,6 +113,7 @@ typedef struct
* @{
*/
+
/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
* @{
*/
@@ -122,6 +123,8 @@ typedef struct
* @}
*/
+
+
/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
* @{
*/
@@ -272,8 +275,7 @@ typedef struct
* @param __COMPx__ COMP instance
* @retval COMP common instance or value "0" if there is no COMP common instance.
*/
-#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
- (COMP12_COMMON)
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
/**
* @}
@@ -288,10 +290,12 @@ typedef struct
* @{
*/
-/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
+/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration
+ * of COMP hierarchical scope: common to several COMP instances
* @{
*/
+
/**
* @brief Set window mode of a pair of comparators instances
* (2 consecutive COMP instances COMP and COMP).
@@ -325,6 +329,8 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *
return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WINMODE));
}
+
+
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_cortex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_cortex.h
index 4260a3e562..9dc17b6512 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_cortex.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_cortex.h
@@ -154,7 +154,7 @@ extern "C" {
* @{
*/
#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos)
-#define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos)
+#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos)
#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos)
/**
* @}
@@ -501,14 +501,15 @@ __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
{
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
+
/* Enable the MPU*/
MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
- /* Ensure MPU settings take effects */
- __DSB();
-
- /* Sequence instruction fetches using update settings */
- __ISB();
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -520,10 +521,15 @@ __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
- /* Make sure outstanding transfers are done */
- __DMB();
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
+
/* Disable MPU */
WRITE_REG(MPU->CTRL, 0U);
+
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -899,14 +905,15 @@ __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
*/
__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
{
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
+
/* Enable the MPU*/
MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
- /* Ensure MPU settings take effects */
- __DSB();
-
- /* Sequence instruction fetches using update settings */
- __ISB();
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -918,10 +925,15 @@ __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
*/
__STATIC_INLINE void LL_MPU_Disable_NS(void)
{
- /* Make sure outstanding transfers are done */
- __DMB();
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
+
/* Disable MPU*/
WRITE_REG(MPU_NS->CTRL, 0U);
+
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_crc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_crc.h
index fdde485433..c1e288019b 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_crc.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_crc.h
@@ -184,7 +184,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySi
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
*/
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
}
@@ -215,7 +215,7 @@ __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
*/
-__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
}
@@ -242,7 +242,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
*/
-__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
}
@@ -270,7 +270,7 @@ __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
* @param CRCx CRC Instance
* @retval Value programmed in Programmable initial CRC value register
*/
-__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->INIT));
}
@@ -301,7 +301,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t Polyno
* @param CRCx CRC Instance
* @retval Value programmed in Programmable Polynomial value register
*/
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->POL));
}
@@ -359,7 +359,7 @@ __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
*/
-__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->DR));
}
@@ -371,7 +371,7 @@ __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
*/
-__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
{
return (uint16_t)READ_REG(CRCx->DR);
}
@@ -383,7 +383,7 @@ __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
*/
-__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
{
return (uint8_t)READ_REG(CRCx->DR);
}
@@ -395,7 +395,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
*/
-__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
{
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
}
@@ -407,7 +407,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
* @param CRCx CRC Instance
* @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
*/
-__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->IDR));
}
@@ -433,7 +433,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
* @{
*/
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx);
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_dac.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_dac.h
index 02b90b607d..8f653b33dc 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_dac.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_dac.h
@@ -366,11 +366,8 @@ typedef struct
/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
* @{
*/
-#define LL_DAC_OUTPUT_CONNECT_EXTERNAL (1UL << 0) /*!< The selected DAC channel output is connected to external pin */
-#define LL_DAC_OUTPUT_CONNECT_INTERNAL (1UL << 1) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
-#define LL_DAC_OUTPUT_CONNECT_BOTH (1UL << 2) /*!< The selected DAC channel output is connected to extrenan and to on-chip peripherals via internal paths. */
-
-#define LL_DAC_OUTPUT_CONNECT_GPIO LL_DAC_OUTPUT_CONNECT_EXTERNAL /*!< kept for legacy purpose */
+#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
+#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
/**
* @}
*/
@@ -538,12 +535,10 @@ typedef struct
* @arg @ref LL_DAC_RESOLUTION_8B
* @retval DAC conversion data (unit: digital value)
*/
-#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
- __DAC_VOLTAGE__,\
- __DAC_RESOLUTION__) \
-((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- / (__VREFANALOG_VOLTAGE__) \
-)
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
+ ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+ )
/**
* @}
@@ -583,7 +578,7 @@ __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t Hig
* @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
* @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
*/
-__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(const DAC_TypeDef *DACx)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_HFSEL));
}
@@ -591,6 +586,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx)
* @}
*/
+
/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
* @{
*/
@@ -629,7 +625,7 @@ __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uin
* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
* @arg @ref LL_DAC_MODE_CALIBRATION
*/
-__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -668,7 +664,7 @@ __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Cha
* @arg @ref LL_DAC_CHANNEL_2
* @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
*/
-__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -737,7 +733,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
* @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
*/
-__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -780,7 +776,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
*/
-__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -846,7 +842,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
*/
-__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -913,7 +909,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
*/
-__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1011,7 +1007,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
*/
-__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1054,7 +1050,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
*/
-__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1113,7 +1109,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
*/
-__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1155,7 +1151,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
@@ -1193,7 +1189,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1230,7 +1226,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1292,7 +1288,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1331,7 +1327,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
* @retval DAC register address
*/
-__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
{
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
/* DAC channel selected. */
@@ -1392,7 +1388,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1450,7 +1446,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1623,7 +1619,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
@@ -1645,7 +1641,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
}
@@ -1657,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
}
@@ -1669,7 +1665,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
}
@@ -1680,7 +1676,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
}
@@ -1692,7 +1688,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
}
@@ -1704,7 +1700,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
}
@@ -1796,7 +1792,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
}
@@ -1808,7 +1804,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
}
@@ -1823,8 +1819,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
* @{
*/
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
+ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
/**
@@ -1851,4 +1847,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
#endif
#endif /* STM32L5xx_LL_DAC_H */
-
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_i2c.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_i2c.h
index 9996028184..34401a0ea2 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_i2c.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_i2c.h
@@ -451,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
}
@@ -500,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
}
@@ -535,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
}
@@ -568,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
}
@@ -601,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
}
@@ -616,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
{
uint32_t data_reg_addr;
@@ -664,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
}
@@ -697,7 +697,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
}
@@ -737,7 +737,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
}
@@ -772,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
}
@@ -800,7 +800,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
*/
-__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
}
@@ -849,7 +849,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
}
@@ -905,7 +905,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
}
@@ -930,7 +930,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
}
@@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
}
@@ -952,7 +952,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
}
@@ -963,7 +963,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
}
@@ -974,7 +974,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
}
@@ -1011,7 +1011,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
*/
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
}
@@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
}
@@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
}
@@ -1150,7 +1150,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
}
@@ -1182,7 +1182,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
}
@@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
}
@@ -1264,7 +1264,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
(ClockTimeout)) ? 1UL : 0UL);
@@ -1306,7 +1306,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
}
@@ -1339,7 +1339,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
}
@@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
}
@@ -1405,7 +1405,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
}
@@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
}
@@ -1477,7 +1477,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
}
@@ -1528,7 +1528,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
}
@@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
}
@@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
}
@@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
}
@@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
}
@@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
}
@@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
}
@@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
}
@@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
}
@@ -1653,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
}
@@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
}
@@ -1679,7 +1679,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
}
@@ -1694,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
}
@@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
}
@@ -1725,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
}
@@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
}
@@ -1899,7 +1899,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
}
@@ -1934,7 +1934,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
}
@@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
}
@@ -2035,7 +2035,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
}
@@ -2063,7 +2063,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans
* @arg @ref LL_I2C_REQUEST_WRITE
* @arg @ref LL_I2C_REQUEST_READ
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
}
@@ -2087,7 +2087,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0x3F
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
}
@@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
+ ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
+ (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
+
+ /* update CR2 register */
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
- SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
+ tmp);
}
/**
@@ -2150,7 +2157,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr
* @arg @ref LL_I2C_DIRECTION_WRITE
* @arg @ref LL_I2C_DIRECTION_READ
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
}
@@ -2161,7 +2168,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
*/
-__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
}
@@ -2191,7 +2198,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
}
@@ -2204,7 +2211,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
}
@@ -2215,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
{
return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
}
@@ -2241,8 +2248,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
* @{
*/
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_icache.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_icache.h
index eef0ca1a41..37342d421d 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_icache.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_icache.h
@@ -555,6 +555,7 @@ __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region)
/**
* @brief Select the memory remapped region base address.
+ * @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
@@ -567,12 +568,13 @@ __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region)
__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
- ICACHE_CRRx_BASEADDR, (((Address & 0x1FFFFFFFU) >> 21U) & ICACHE_CRRx_BASEADDR));
+ ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U));
}
/**
* @brief Get the memory remapped region base address.
* @note The base address is the alias in the Code region.
+ * @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
@@ -584,18 +586,19 @@ __STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Ad
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
- ICACHE_CRRx_BASEADDR));
+ ICACHE_CRRx_BASEADDR) << 21U);
}
/**
- * @brief Select the memory remapped region remap address.
+ * @brief Select the memory remapped region address.
+ * @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
- * @param Address External memory address
+ * @param Address Memory address to remap
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address)
@@ -605,14 +608,15 @@ __STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t A
}
/**
- * @brief Get the memory remapped region base address.
+ * @brief Get the memory remapped region address.
+ * @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
- * @retval Address External memory address
+ * @retval Address Remapped memory address
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region)
{
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lptim.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lptim.h
index 7eb465696c..b19057d8bd 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lptim.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lptim.h
@@ -348,7 +348,7 @@ typedef struct
* @{
*/
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
+ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lpuart.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lpuart.h
index ae027eaaad..11140a1b4d 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lpuart.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lpuart.h
@@ -2605,6 +2605,21 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
}
+/**
+ * @brief Request a Transmit data FIFO flush
+ * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This
+ * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register).
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_pka.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_pka.h
index 1363e57382..89d13b427c 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_pka.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_pka.h
@@ -223,7 +223,7 @@ __STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *PKAx)
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_PKA_IsEnabled(PKA_TypeDef *PKAx)
+__STATIC_INLINE uint32_t LL_PKA_IsEnabled(const PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL);
}
@@ -282,7 +282,7 @@ __STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode)
* @arg @ref LL_PKA_MODE_MODULAR_SUB
* @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
*/
-__STATIC_INLINE uint32_t LL_PKA_GetMode(PKA_TypeDef *PKAx)
+__STATIC_INLINE uint32_t LL_PKA_GetMode(const PKA_TypeDef *PKAx)
{
return (uint32_t)(READ_BIT(PKAx->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
}
@@ -379,7 +379,7 @@ __STATIC_INLINE void LL_PKA_DisableIT_PROCEND(PKA_TypeDef *PKAx)
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx)
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(const PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL);
}
@@ -390,7 +390,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx)
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx)
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(const PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL);
}
@@ -402,7 +402,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx)
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx)
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(const PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL);
}
@@ -421,7 +421,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx)
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx)
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(const PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL);
}
@@ -432,7 +432,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx)
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx)
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(const PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL);
}
@@ -444,7 +444,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx)
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx)
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(const PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL);
}
@@ -455,7 +455,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx)
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(PKA_TypeDef *PKAx)
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL);
}
@@ -504,7 +504,7 @@ __STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *PKAx)
* @{
*/
-ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx);
+ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx);
ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct);
void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rcc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rcc.h
index f526f6e521..55e04d35fe 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rcc.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rcc.h
@@ -414,18 +414,18 @@ typedef struct
/** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection
* @{
*/
-#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
-#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
-#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
-#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
-#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
-#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
-#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
-#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C3SEL_Pos << 16U) | (RCC_CCIPR1_I2C3SEL_0 >> RCC_CCIPR1_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
-#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C3SEL_Pos << 16U) | (RCC_CCIPR1_I2C3SEL_1 >> RCC_CCIPR1_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
-#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
-#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
-#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C3SEL_Pos << 16U) | (RCC_CCIPR1_I2C3SEL_0 >> RCC_CCIPR1_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C3SEL_Pos << 16U) | (RCC_CCIPR1_I2C3SEL_1 >> RCC_CCIPR1_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
+#define LL_RCC_I2C4_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
/**
* @}
*/
@@ -587,10 +587,10 @@ typedef struct
/** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source
* @{
*/
-#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
-#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
-#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C3SEL_Pos << 16U) | (RCC_CCIPR1_I2C3SEL >> RCC_CCIPR1_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
-#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
+#define LL_RCC_I2C1_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
+#define LL_RCC_I2C2_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
+#define LL_RCC_I2C3_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C3SEL_Pos << 16U) | (RCC_CCIPR1_I2C3SEL >> RCC_CCIPR1_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
+#define LL_RCC_I2C4_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rng.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rng.h
index 340fbdb0c3..7e43e84520 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rng.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rng.h
@@ -217,7 +217,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
}
@@ -230,7 +230,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
{
- CLEAR_BIT(RNGx->CR, RNG_CR_CED);
+ MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -241,7 +242,8 @@ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
{
- SET_BIT(RNGx->CR, RNG_CR_CED);
+ MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -250,7 +252,7 @@ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
}
@@ -283,7 +285,7 @@ __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
}
@@ -305,7 +307,7 @@ __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
}
@@ -318,7 +320,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
{
- CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
+ MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -329,7 +332,8 @@ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
{
- SET_BIT(RNGx->CR, RNG_CR_NISTC);
+ MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -338,7 +342,7 @@ __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
}
@@ -352,7 +356,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
{
- MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
+ MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -361,7 +366,7 @@ __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
* @param RNGx RNG Instance
* @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
*/
-__STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
}
@@ -375,7 +380,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
{
- MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
+ MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -384,7 +390,7 @@ __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
* @param RNGx RNG Instance
* @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
*/
-__STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
}
@@ -398,7 +404,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
{
- MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
+ MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -407,7 +414,7 @@ __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
* @param RNGx RNG Instance
* @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
*/
-__STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
}
@@ -437,7 +444,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
{
- MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
+ MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -462,7 +470,7 @@ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
* @arg @ref LL_RNG_CLKDIV_BY_16384
* @arg @ref LL_RNG_CLKDIV_BY_32768
*/
-__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx)
{
return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
}
@@ -480,7 +488,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
}
@@ -491,7 +499,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
}
@@ -502,7 +510,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
}
@@ -513,7 +521,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
}
@@ -524,7 +532,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
}
@@ -590,7 +598,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
}
@@ -609,7 +617,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
* @param RNGx RNG Instance
* @retval Generated 32-bit random value
*/
-__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_REG(RNGx->DR));
}
@@ -660,9 +668,9 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
* @{
*/
-ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct);
void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
-ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
+ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rtc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rtc.h
index 9dfae52b1c..4aa6afd661 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rtc.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rtc.h
@@ -1352,7 +1352,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma
/**
* @brief Get time format (AM or PM notation)
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1386,7 +1386,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
/**
* @brief Get Hours in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1421,7 +1421,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
/**
* @brief Get Minutes in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1456,7 +1456,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
/**
* @brief Get Seconds in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1506,7 +1506,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24,
/**
* @brief Get time (hour, minute and second) in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1652,7 +1652,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
/**
* @brief Get Year in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
* @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n
@@ -1686,7 +1686,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
/**
* @brief Get Week day
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay
* @param RTCx RTC Instance
@@ -1733,7 +1733,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
/**
* @brief Get Month in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
* @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n
@@ -1775,7 +1775,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
/**
* @brief Get Day in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n
@@ -1837,7 +1837,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin
/**
* @brief Get date (WeekDay, Day, Month and Year) in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
* and __LL_RTC_GET_DAY are available to get independently each parameter.
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_sdmmc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_sdmmc.h
index 53507812ee..47df027b8d 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_sdmmc.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_sdmmc.h
@@ -30,7 +30,7 @@ extern "C" {
/** @addtogroup STM32L5xx_Driver
* @{
*/
-
+#if defined (SDMMC1) || defined (SDMMC2)
/** @addtogroup SDMMC_LL
* @{
*/
@@ -279,6 +279,7 @@ typedef struct
#define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U)
#define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U)
#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
+#define SDMMC_SDR12_SWITCH_PATTERN ((uint32_t)0x80FFFF00U)
#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
@@ -290,9 +291,14 @@ typedef struct
#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
-#ifndef SDMMC_DATATIMEOUT
+#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */
#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
#endif /* SDMMC_DATATIMEOUT */
+
+#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */
+#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT
+#endif /* SDMMC_SWDATATIMEOUT */
+
#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
@@ -302,6 +308,8 @@ typedef struct
#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
+/* SDMMC FIFO Size */
+#define SDMMC_FIFO_SIZE 32U
/**
* @brief Command Class supported
*/
@@ -356,12 +364,15 @@ typedef struct
#define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U)
#define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U)
#define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U)
+#define SDMMC_SPEED_MODE_ULTRA_SDR104 SDMMC_SPEED_MODE_ULTRA
#define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U)
+#define SDMMC_SPEED_MODE_ULTRA_SDR50 ((uint32_t)0x00000005U)
-#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \
- ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
- ((MODE) == SDMMC_SPEED_MODE_HIGH) || \
- ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \
+#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \
+ ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
+ ((MODE) == SDMMC_SPEED_MODE_HIGH) || \
+ ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \
+ ((MODE) == SDMMC_SPEED_MODE_ULTRA_SDR50) || \
((MODE) == SDMMC_SPEED_MODE_DDR))
/**
@@ -539,9 +550,11 @@ typedef struct
* @{
*/
#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
+#define SDMMC_TRANSFER_MODE_SDIO SDMMC_DCTRL_DTMODE_0
#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
+ ((MODE) == SDMMC_TRANSFER_MODE_SDIO) || \
((MODE) == SDMMC_TRANSFER_MODE_STREAM))
/**
* @}
@@ -1005,7 +1018,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
/** @addtogroup HAL_SDMMC_LL_Group2
* @{
*/
-uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx);
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
/**
* @}
@@ -1018,17 +1031,17 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx);
/* Command path state machine (CPSM) management functions */
HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
-uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
+uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response);
/* Data path state machine (DPSM) management functions */
HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data);
-uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx);
/* SDMMC Cards mode management functions */
HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
@@ -1069,6 +1082,7 @@ uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount);
/**
* @}
*/
@@ -1102,7 +1116,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
/**
* @}
*/
-
+#endif /* SDMMC1 || SDMMC2 */
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_tim.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_tim.h
index a15bb19544..3febf156f5 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_tim.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_tim.h
@@ -154,8 +154,6 @@ static const uint8_t SHIFT_TAB_OISx[] =
@endcond
*/
-#define OCREF_CLEAR_SELECT_Pos (16U)
-#define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x00010000 */
/**
* @}
*/
@@ -667,10 +665,10 @@ typedef struct
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
* @{
*/
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
-/**
- * @}
- */
-
-
/**
* @}
*/
@@ -1883,6 +1895,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
}
+/**
+ * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+ * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
@@ -2027,7 +2050,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
{
return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
}
@@ -2113,8 +2136,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
@@ -2153,8 +2176,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
{
@@ -2368,7 +2391,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2444,7 +2467,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2529,7 +2552,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -3078,7 +3101,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
}
@@ -3531,18 +3554,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
}
-/**
- * @brief Re-arm the break input (when it operates in bidirectional mode).
- * @note The Break input is automatically armed as soon as MOE bit is set.
- * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
-}
-
/**
* @brief Enable the break 2 function.
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
@@ -3632,18 +3643,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
}
-/**
- * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
- * @note The Break 2 input is automatically armed as soon as MOE bit is set.
- * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
-}
-
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
@@ -4986,7 +4985,7 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
* @{
*/
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_ucpd.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_ucpd.h
index ffa72dbefd..2727a43bac 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_ucpd.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_ucpd.h
@@ -1833,7 +1833,7 @@ __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
*/
ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
-ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct);
+ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct);
void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
/**
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usart.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usart.h
index 748761471d..8d5bdcc2fc 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usart.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usart.h
@@ -1566,7 +1566,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
*/
-__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usb.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usb.h
index 1c70873f0c..0d44bc08cd 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usb.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usb.h
@@ -53,26 +53,26 @@ typedef enum
*/
typedef struct
{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
+ uint8_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref PCD_Speed/HCD_Speed
- (HCD_SPEED_xxx, HCD_SPEED_xxx) */
+ uint8_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
+ uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
+ uint8_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+ uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
+ uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
- uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+ uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+ uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
} USB_CfgTypeDef;
typedef struct
@@ -192,6 +192,9 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num);
+
#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
@@ -205,14 +208,14 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
-uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
+uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
+void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
+void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
/**
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_utils.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_utils.h
index 9c01e468f8..53927d1820 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_utils.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_utils.h
@@ -274,7 +274,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void)
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
+ * @param Ticks Frequency of Ticks (Hz)
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_wwdg.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_wwdg.h
index 361bc7533a..c74297f801 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_wwdg.h
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_wwdg.h
@@ -135,7 +135,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
@@ -162,7 +162,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Counter value
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
@@ -203,7 +203,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale
* @arg @ref LL_WWDG_PRESCALER_64
* @arg @ref LL_WWDG_PRESCALER_128
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
@@ -235,7 +235,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Window value
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
@@ -256,7 +256,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
@@ -298,7 +298,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/License.md b/system/Drivers/STM32L5xx_HAL_Driver/LICENSE.md
similarity index 100%
rename from system/Drivers/STM32L5xx_HAL_Driver/License.md
rename to system/Drivers/STM32L5xx_HAL_Driver/LICENSE.md
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32L5xx_HAL_Driver/Release_Notes.html
index 60d4d15c5c..3ab30419f2 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Release_Notes.html
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Release_Notes.html
@@ -41,17 +41,179 @@
Purpose
Update History
-
+
Main Changes
Maintenance release
Contents
General updates to fix known defects and implementation enhancements.
-
All source files: update disclaimer to add reference to the new license agreement.
HAL Drivers updates
+
HAL code quality enhancement for MISRA-C2012 Rule-8.13 by adding const qualifiers.
+
HAL Generic
+
+
Allow redefinition of macro UNUSED(x).
+
Update of HAL_GetTickFreq() API brief.
+
+
HAL/LL RCC
+
+
Fix HAL_RCC_GetOscConfig() API to return oscillator state based on xxxRDY bit status.
+
Add uint32_t cast to shift left operands constants defined with ‘U’ suffix in case MISRAC2012-Rule-12.2 violated.
+
Invoke UNUSED() macro to avoid compilation warnings due to unused parameter(s).
+
Correct LSE config macro regarding LSESYS handling.
+
+
HAL PWR
+
+
Update HAL_PWR_EnterSTANDBYMode() and HAL_PWREx_EnterSHUTDOWNMode() APIs to remove call to the __force_stores() intrinsic API:
+
+
No longer need to call __force_stores() with MDK-ARM V5.6.0 version and later.
+
+
Invoke UNUSED() macro in HAL_PWR_ConfigAttributes() and HAL_PWR_GetConfigAttributes() APIs to avoid compilation warnings due to unused parameter.
+
+
HAL GPIO
+
+
Update HAL_GPIO_LockPin() API description to return HAL status instead of None.
+
Optimize the implementation of HAL_GPIO_ConfigPinAttributes() API.
+
Replace GPIO_Pin_x with GPIO_PIN_x to be compliant with macros definition.
+
+
HAL SAI
+
+
Improve audio quality (avoid potential glitch).
+
+
HAL/LL CORTEX
+
+
Align MPU Enable/Disable APIs with ARM’s last recommendations in the usage of Data Memory and Data/Instruction Synchronization barriers.
+
Align LL_MPU_ACCESS_OUTER_SHAREABLE defined value with ARMv8-M Architecture documentation.
+
Update HAL_MPU_ConfigRegion() API to allow the configuration of the MPU registers independently of the value of Enable/Disable field.
+
Add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion().
+
+
HAL ICACHE
+
+
Update HAL_ICACHE_DeInit to set registers to reset value.
+
Update HAL_ICACHE_Invalidate() to prevent launching an invalidation if one has already been launched.
+
Update “How to use” for HAL_ICACHE_Enable() API.
+
+
HAL HASH
+
+
Read the last remaining bytes (3 or 2 or 1) of the data in a temporary variable (taking into account swap mode) and enter this variable into the HASH->DIN when the data is not a multiple of 4 bytes.
+
HAL code quality enhancement for MISRA-C2012 Rule-12.1, Rule-10.7, Rule-10.6 and Rule-10.4.
+
+
HAL DAC
+
+
Updated DAC buffer calibration according to RM.
+
+
LL RTC
+
+
Correct misleading note about shadow registers.
+
+
HAL/LL TIM
+
+
Remove multiple volatile reads or writes in interrupt handler for better performance.
+
Improve HAL TIM driver’s operational behavior.
+
Assert check for the right channels.
+
Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init() API.
+
Remove useless check on IS_TIM_ADVANCED_INSTANCE() within LL_TIM_BDTR_Init() API to fix Break Filter configuration problem with specific TIM instances.
+
Improve period configuration parameter check.
+
Fix typo in PWM symmetric mode related constants names.
+
+
HAL LPTIM
+
+
Remove redundant IS_LPTIM_AUTORELOAD macro.
+
+
HAL UART
+
+
Update initialisation sequence for TXINV, RXINV and TXRXSWAP settings.
+
Fix incorrect gState check in HAL_UART_RegisterRxEventCallback()/HAL_UART_UnRegisterRxEventCallback() APIs to allow user Rx Event Callback registration when a transmit is ongoing.
+
Avoid RTOF flag to be cleared by a transmit process in polling mode.
+
Add LL LPUART API allowing TX FIFO flush request.
+
+
HAL USART
+
+
Improve the visibility of the SPI function support in HAL USART description.
+
+
HAL CRYP
+
+
Update AES GCM in interrupt mode to avoid Computation Completed IRQ fires before the DINR pointer increment.
+
Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before the DINR pointer increment.
+
HAL code quality enhancement for MISRA-C2012 Rule-10.4.
+
+
HAL FDCAN
+
+
Fix GetIndex issue in HAL_FDCAN_GetRxMessage() API.
+
Remove shift from ‘FDCAN_DLC_BYTES_X’ definitions so that values taken by ‘DataLength’ structure member comply to the definition of a DLC.
+
+
HAL SPI
+
+
Fix driver to don’t update state in case of error. (HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT).
+
Update HAL_SPI_TransmitReceive() API to set the bit CRCNEXT in case of one byte transaction.
+
Update IT API to enable interrupts after process unlock.
+
+
HAL TSC
+
+
Update IS_TSC_PG_PRESC_VS_CTPL() assert macro: Add parameter assertion depends on Duration time restriction link to product.
+
+
HAL/LL I2C
+
+
Update HAL_I2C_IsDeviceReady() API to support 10_bit addressing mode: Update done on the macro I2C_GENERATE_START.
+
Update HAL I2C driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.
+
Update HAL I2C driver to disable all interrupts after end of transaction.
+
Update HAL_I2C_Init() API to clear ADD10 bit in 7 bit addressing mode.
+
Update HAL_I2C_Mem_Write_IT() API to initialize XferSize at 0.
+
Update I2C_Slave_ISR_IT(), I2C_Slave_ISR_DMA() and I2C_ITSlaveCplt() APIs to prevent the call of HAL_I2C_ListenCpltCallback twice.
+
Update I2C_WaitOnRXNEFlagUntilTimeout() API to check I2C_FLAG_AF independently from I2C_FLAG_RXNE.
+
Remove the unusable code in HAL_I2C_IsDeviceReady() API.
+
Update LL_I2C_HandleTranfer() API to prevent undefined behavior of volatile usage before updating the CR2 register.
+
Update I2C_WaitOnFlagUntilTimeout() API to handle error case.
+
Add a temporary variable to get the value to check before comparison.
+
Add abort memory management to HAL_I2C_Master_Abort_IT() API.
+
Move the prefetch process in HAL_I2C_Slave_Transmit() API.
+
+
HAL SMBUS
+
+
Update HAL SMBUS driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.
+
+
HAL SMARTCARD
+
+
Update SMARTCARD_SetConfig() API to fix CONSTANT_EXPRESSION_RESULT Coverity warning.
+
+
HAL SDMMC
+
+
Update HAL_SD_ConfigSpeedBusOperation() API to add support of switch to Default Speed.
+
Fix CodeSonar Division by Zero and Empty while Statement warnings.
+
Remove __HAL_LOCK() API from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback() APIs.
+
Improve the abort mechanism for specific cases.
+
Fix Misra-C 2012 warnings MISRAC2012-Rule-15.6_e and MISRAC2012-Rule-15.7.
+
Fix typos in constants used for variable assignments : MMC instead of SD.
Add HAL_MMC_BOOT_PARTITION1 and HAL_MMC_BOOT_PARTITION2 macros.
+
Add configurable HW/SW Timeout.
+
+
LL UTILS
+
+
Update LL_InitTick() API documentation: update “Ticks” parameter description.
+
+
+
Notes
+
For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.
+
For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.
+
+
+
+
+
+
Main Changes
+
Maintenance release
+
Contents
+
+
General updates to fix known defects and implementation enhancements.
+
All source files: update disclaimer to add reference to the new license agreement.
+
+
HAL Drivers updates
+
HAL Generic
HAL code quality enhancement for MISRA-C2012 rules 2.2_C, 13.2 and 13.3.
@@ -248,7 +410,7 @@
HAL Drivers updates
Update the way to declare licenses.
-
Notes
+
Notes
For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.
For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.
@@ -256,12 +418,12 @@
Notes
-
Main Changes
+
Main Changes
Maintenance release
-
Contents
+
Contents
Maintenance release of HAL and Low Layer drivers for STM32L552xx/STM32L562xx devices
Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)
-
HAL Drivers updates
+
HAL Drivers updates
HAL ADC driver
@@ -410,7 +572,7 @@
LL Drivers updates
Remove useless IS_LL_USART_BRR_MAX() macro
-
Notes
+
Notes
For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.
For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.
@@ -418,12 +580,12 @@
Notes
-
Main Changes
+
Main Changes
Fourth release
-
Contents
+
Contents
Fourth release of HAL and Low Layer drivers for STM32L552xx/STM32L562xx devices
Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)
-
HAL Drivers updates
+
HAL Drivers updates
Global removal of ‘register’ storage class qualifier deprecated since C++ 11
HAL generic driver
@@ -537,7 +699,7 @@
LL Drivers updates
Change default CFGR1 register values in LL_UCPD_StructInit()
-
Notes
+
Notes
For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.
For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.
@@ -545,12 +707,12 @@
Notes
-
Main Changes
+
Main Changes
Third release
-
Contents
+
Contents
Third official release of HAL and Low Layer drivers for STM32L552xx/STM32L562xx devices
Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)
-
HAL Drivers updates
+
HAL Drivers updates
HAL FLASH driver
@@ -583,7 +745,7 @@
LL Drivers updates
-
Notes
+
Notes
For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.
For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.
Known Limitations
@@ -598,12 +760,12 @@
Known Limitations
-
Main Changes
+
Main Changes
Second release
-
Contents
+
Contents
Second official release of HAL and Low Layer drivers for STM32L552xx/STM32L562xx devices
Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)
-
HAL Drivers updates
+
HAL Drivers updates
HAL FLASH driver
@@ -662,7 +824,7 @@
LL Drivers updates
Add LL_SetFlashLatency() API
-
Notes
+
Notes
For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.
For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.
@@ -670,9 +832,9 @@
Notes
-
Main Changes
+
Main Changes
First release
-
Contents
+
Contents
First official release of HAL and Low Layer drivers for STM32L552xx/STM32L562xx devices
Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)
For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.
For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal.c
index 8a1df2ed21..e2fc0fc0cb 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal.c
@@ -53,7 +53,7 @@
*/
#define STM32L5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L5XX_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
-#define STM32L5XX_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
+#define STM32L5XX_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
#define STM32L5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L5XX_HAL_VERSION ((STM32L5XX_HAL_VERSION_MAIN << 24U)\
|(STM32L5XX_HAL_VERSION_SUB1 << 16U)\
@@ -354,7 +354,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
/**
* @brief Return tick frequency.
- * @retval tick period in Hz
+ * @retval Tick frequency.
+ * Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_comp.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_comp.c
index 3688f138a6..89904ff882 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_comp.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_comp.c
@@ -21,9 +21,9 @@
*
******************************************************************************
@verbatim
-================================================================================
+ ==============================================================================
##### COMP Peripheral features #####
-================================================================================
+ ==============================================================================
[..]
The STM32L5xx device family integrates two analog comparators instances:
@@ -47,7 +47,7 @@
using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
##### How to use this driver #####
-================================================================================
+ ==============================================================================
[..]
This driver provides functions to configure and program the comparator instances
of STM32L5xx devices.
@@ -153,7 +153,6 @@
@endverbatim
******************************************************************************
-
*/
/* Includes ------------------------------------------------------------------*/
@@ -183,7 +182,7 @@
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
-#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */
+#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */
/* Delay for COMP voltage scaler stabilization time. */
/* Literal set to maximum value (refer to device datasheet, */
@@ -236,11 +235,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
- if(hcomp == NULL)
+ if (hcomp == NULL)
{
status = HAL_ERROR;
}
- else if(__HAL_COMP_IS_LOCKED(hcomp))
+ else if (__HAL_COMP_IS_LOCKED(hcomp))
{
status = HAL_ERROR;
}
@@ -255,9 +254,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
+
assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
- if(hcomp->State == HAL_COMP_STATE_RESET)
+
+ if (hcomp->State == HAL_COMP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcomp->Lock = HAL_UNLOCKED;
@@ -265,7 +266,6 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
/* Set COMP error code to none */
COMP_CLEAR_ERRORCODE(hcomp);
-
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Init the COMP Callback settings */
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
@@ -293,7 +293,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN);
/* Set COMP parameters */
- tmp_csr = ( hcomp->Init.InputMinus
+ tmp_csr = (hcomp->Init.InputMinus
| hcomp->Init.InputPlus
| hcomp->Init.BlankingSrce
| hcomp->Init.Hysteresis
@@ -310,11 +310,12 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
tmp_csr
);
+
/* Set window mode */
/* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */
/* instances. Therefore, this function can update another COMP */
/* instance that the one currently selected. */
- if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
+ if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
{
SET_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
}
@@ -323,17 +324,18 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
}
+
/* Delay for COMP scaler bridge voltage stabilization */
/* Apply the delay if voltage scaler bridge is required and not already enabled */
if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) &&
- (comp_voltage_scaler_initialized == 0UL) )
+ (comp_voltage_scaler_initialized == 0UL))
{
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
- while(wait_loop_index != 0UL)
+ while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
@@ -343,10 +345,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
/* Manage EXTI settings */
- if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
+ if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
{
/* Configure EXTI rising edge */
- if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
+ if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
{
LL_EXTI_EnableRisingTrig_0_31(exti_line);
}
@@ -356,7 +358,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
}
/* Configure EXTI falling edge */
- if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
+ if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
{
LL_EXTI_EnableFallingTrig_0_31(exti_line);
}
@@ -370,7 +372,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
LL_EXTI_ClearFallingFlag_0_31(exti_line);
/* Configure EXTI event mode */
- if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
+ if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
{
LL_EXTI_EnableEvent_0_31(exti_line);
}
@@ -380,7 +382,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
}
/* Configure EXTI interrupt mode */
- if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
+ if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
{
LL_EXTI_EnableIT_0_31(exti_line);
}
@@ -422,11 +424,11 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
- if(hcomp == NULL)
+ if (hcomp == NULL)
{
status = HAL_ERROR;
}
- else if(__HAL_COMP_IS_LOCKED(hcomp))
+ else if (__HAL_COMP_IS_LOCKED(hcomp))
{
status = HAL_ERROR;
}
@@ -505,7 +507,8 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
+ pCOMP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -681,11 +684,11 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
- if(hcomp == NULL)
+ if (hcomp == NULL)
{
status = HAL_ERROR;
}
- else if(__HAL_COMP_IS_LOCKED(hcomp))
+ else if (__HAL_COMP_IS_LOCKED(hcomp))
{
status = HAL_ERROR;
}
@@ -694,7 +697,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
- if(hcomp->State == HAL_COMP_STATE_READY)
+ if (hcomp->State == HAL_COMP_STATE_READY)
{
/* Enable the selected comparator */
SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
@@ -708,7 +711,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
- while(wait_loop_index != 0UL)
+ while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
@@ -732,11 +735,11 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
- if(hcomp == NULL)
+ if (hcomp == NULL)
{
status = HAL_ERROR;
}
- else if(__HAL_COMP_IS_LOCKED(hcomp))
+ else if (__HAL_COMP_IS_LOCKED(hcomp))
{
status = HAL_ERROR;
}
@@ -747,7 +750,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
/* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */
/* (all states except HAL_COMP_STATE_RESET and except locked status. */
- if(hcomp->State != HAL_COMP_STATE_RESET)
+ if (hcomp->State != HAL_COMP_STATE_RESET)
{
/* Disable the selected comparator */
CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
@@ -775,10 +778,10 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
/* Check COMP EXTI flag */
- if(LL_EXTI_IsActiveRisingFlag_0_31(exti_line) != 0UL)
+ if (LL_EXTI_IsActiveRisingFlag_0_31(exti_line) != 0UL)
{
/* Check whether comparator is in independent or window mode */
- if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0UL)
+ if (READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0UL)
{
/* Clear COMP EXTI line pending bit of the pair of comparators */
/* in window mode. */
@@ -802,10 +805,10 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
HAL_COMP_TriggerCallback(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
- else if(LL_EXTI_IsActiveFallingFlag_0_31(exti_line) != 0UL)
+ else if (LL_EXTI_IsActiveFallingFlag_0_31(exti_line) != 0UL)
{
/* Check whether comparator is in independent or window mode */
- if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0UL)
+ if (READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0UL)
{
/* Clear COMP EXTI line pending bit of the pair of comparators */
/* in window mode. */
@@ -866,11 +869,11 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
- if(hcomp == NULL)
+ if (hcomp == NULL)
{
status = HAL_ERROR;
}
- else if(__HAL_COMP_IS_LOCKED(hcomp))
+ else if (__HAL_COMP_IS_LOCKED(hcomp))
{
status = HAL_ERROR;
}
@@ -880,7 +883,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
/* Set HAL COMP handle state */
- switch(hcomp->State)
+ switch (hcomp->State)
{
case HAL_COMP_STATE_RESET:
hcomp->State = HAL_COMP_STATE_RESET_LOCKED;
@@ -892,10 +895,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
break;
}
- }
- if(status == HAL_OK)
- {
/* Set the lock bit corresponding to selected comparator */
__HAL_COMP_LOCK(hcomp);
}
@@ -973,7 +973,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp)
{
/* Check the COMP handle allocation */
- if(hcomp == NULL)
+ if (hcomp == NULL)
{
return HAL_COMP_STATE_RESET;
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cortex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cortex.c
index b17dd7438b..590a0a2e59 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cortex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cortex.c
@@ -426,6 +426,8 @@ __weak void HAL_SYSTICK_Callback(void)
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
+
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
@@ -433,9 +435,9 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Follow ARM recommendation with */
- /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
- __DMB(); /* Force memory writes before continuing */
- __ISB(); /* Flush and refill pipeline with updated permissions */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -446,8 +448,48 @@ void HAL_MPU_Disable(void)
{
__DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
+}
+
+/**
+ * @brief Enable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Enable the Region */
+ SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
+}
+
+/**
+ * @brief Disable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
}
/**
@@ -486,6 +528,8 @@ void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesIn
*/
void HAL_MPU_Enable_NS(uint32_t MPU_Control)
{
+ __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
+
/* Enable the MPU */
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
@@ -493,9 +537,9 @@ void HAL_MPU_Enable_NS(uint32_t MPU_Control)
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Follow ARM recommendation with */
- /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
- __DMB(); /* Force memory writes before continuing */
- __ISB(); /* Flush and refill pipeline with updated permissions */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
/**
@@ -506,8 +550,48 @@ void HAL_MPU_Disable_NS(void)
{
__DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+ /* Disable fault exceptions */
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
/* Disable the MPU */
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+
+ /* Follow ARM recommendation with */
+ /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
+ __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
+ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
+}
+
+/**
+ * @brief Enable the non-secure MPU Region.
+ * @retval None
+ */
+void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU_NS->RNR = RegionNumber;
+
+ /* Enable the Region */
+ SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
+}
+
+/**
+ * @brief Disable the non-secure MPU Region.
+ * @retval None
+ */
+void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU_NS->RNR = RegionNumber;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
}
/**
@@ -538,11 +622,6 @@ void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_Attribute
/**
* @}
*/
-
-/**
- * @}
- */
-
/* Private functions ---------------------------------------------------------*/
/** @addtogroup CORTEX_Private_Functions
* @{
@@ -555,6 +634,9 @@ static void MPU_ConfigRegion(MPU_Type* MPUx, MPU_Region_InitTypeDef *MPU_RegionI
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_RegionInit->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_RegionInit->Enable));
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_RegionInit->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_RegionInit->AccessPermission));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_RegionInit->IsShareable));
/* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
__DMB();
@@ -562,27 +644,18 @@ static void MPU_ConfigRegion(MPU_Type* MPUx, MPU_Region_InitTypeDef *MPU_RegionI
/* Set the Region number */
MPUx->RNR = MPU_RegionInit->Number;
- if (MPU_RegionInit->Enable != MPU_REGION_DISABLE)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_RegionInit->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_RegionInit->AccessPermission));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_RegionInit->IsShareable));
-
- MPUx->RBAR = (((uint32_t)MPU_RegionInit->BaseAddress & 0xFFFFFFE0U) |
- ((uint32_t)MPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
- ((uint32_t)MPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
- ((uint32_t)MPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
-
- MPUx->RLAR = (((uint32_t)MPU_RegionInit->LimitAddress & 0xFFFFFFE0U) |
- ((uint32_t)MPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
- ((uint32_t)MPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
- }
- else
- {
- MPUx->RLAR = 0U;
- MPUx->RBAR = 0U;
- }
+ /* Disable the Region */
+ CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk);
+
+ /* Apply configuration */
+ MPUx->RBAR = (((uint32_t)MPU_RegionInit->BaseAddress & 0xFFFFFFE0U) |
+ ((uint32_t)MPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
+ ((uint32_t)MPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
+ ((uint32_t)MPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
+
+ MPUx->RLAR = (((uint32_t)MPU_RegionInit->LimitAddress & 0xFFFFFFE0U) |
+ ((uint32_t)MPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
+ ((uint32_t)MPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
}
static void MPU_ConfigMemoryAttributes(MPU_Type* MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit)
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc.c
index 1205934e8c..58770ef64c 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc.c
@@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
- CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+ CLEAR_REG(hcrc->Instance->IDR);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
@@ -403,7 +403,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
* @param hcrc CRC handle
* @retval HAL state
*/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc_ex.c
index 4b72a8d89b..bc42e53836 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc_ex.c
@@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
}
-
-
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp.c
index 689ba22673..daa48ef5b5 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp.c
@@ -30,7 +30,8 @@
The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows:
(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
- (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
+ or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral
(##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
@@ -58,8 +59,10 @@
(##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication
algorithms) is in words or bytes.
(##) The Header used only in AES GCM and CCM Algorithm for authentication.
- (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field.
- (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes.
+ (##) The HeaderSize providing the size of the header buffer in words or bytes,
+ depending upon HeaderWidthUnit field.
+ (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms)
+ is in words or bytes.
(##) The B0 block is the first authentication block used only in AES CCM mode.
(##) The KeyIVConfigSkip used to process several messages in a row (please see more information below).
@@ -78,7 +81,7 @@
the CRYP peripheral is configured and processes the buffer in input.
At second call, no need to Initialize the CRYP, user have to get current configuration via
HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
- new parametres, finally user can start encryption/decryption.
+ new parameters, finally user can start encryption/decryption.
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
@@ -200,7 +203,7 @@
(##) To perform message payload encryption or decryption AES is configured in CTR mode.
(##) For authentication two phases are performed :
- Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
- only cleartext payload (not the ciphertext payload) is used and no outpout.
+ only cleartext payload (not the ciphertext payload) is used and no output.
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
*** Callback registration ***
@@ -316,7 +319,8 @@
* @{
*/
#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
-#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey
+ is 299 clock cycles.*/
#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
@@ -350,7 +354,8 @@
* @{
*/
-#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR,\
+ AES_CR_GCMPH, (uint32_t)(__PHASE__))
/**
* @}
@@ -390,12 +395,12 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
-static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output);
-static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input);
-static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output);
-static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input);
-static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize);
-static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize);
+static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output);
+static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input);
+static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output);
+static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input);
+static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize);
+static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize);
static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp);
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
@@ -488,7 +493,8 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
/* Set the key size (This bit field is do not care in the DES or TDES modes), data type and Algorithm */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
/* Reset Error Code field */
hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
@@ -511,7 +517,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
{
/* Check the CRYP handle allocation */
@@ -600,7 +606,8 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD
hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
/* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
/*clear error flags*/
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
@@ -733,7 +740,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+ pCRYP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -920,8 +928,6 @@ void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
}
-
-
/**
* @brief CRYP processing suspension and peripheral internal parameters storage.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
@@ -954,14 +960,14 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
/* If authentication algorithms on-going, carry out first saving steps
before disable the peripheral */
if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \
- (hcryp->Init.Algorithm == CRYP_AES_CCM))
+ (hcryp->Init.Algorithm == CRYP_AES_CCM))
{
- /* Save Suspension registers */
- CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
- /* Save Key */
- CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
- /* Save IV */
- CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
+ /* Save Suspension registers */
+ CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
+ /* Save Key */
+ CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
+ /* Save IV */
+ CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
}
/* Disable AES */
__HAL_CRYP_DISABLE(hcryp);
@@ -974,7 +980,8 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
hcryp->CrypOutCount_saved = hcryp->CrypOutCount;
hcryp->Phase_saved = hcryp->Phase;
hcryp->State_saved = hcryp->State;
- hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size /4U) : hcryp->Size);
+ hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? \
+ (hcryp->Size / 4U) : hcryp->Size);
hcryp->SizesSum_saved = hcryp->SizesSum;
hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation;
hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount;
@@ -1032,7 +1039,7 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
hcryp->AutoKeyDerivation = hcryp->AutoKeyDerivation_saved;
if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
- (hcryp->Init.Algorithm == CRYP_AES_CTR))
+ (hcryp->Init.Algorithm == CRYP_AES_CTR))
{
hcryp->Init.pInitVect = hcryp->IV_saved;
}
@@ -1065,14 +1072,16 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
hcryp->ResumingFlag = 1U;
if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
- if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
+ if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \
+ hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
{
return HAL_ERROR;
}
}
else
{
- if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
+ if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \
+ hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
{
return HAL_ERROR;
}
@@ -1200,7 +1209,8 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
* @param Timeout Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout)
{
uint32_t algo;
HAL_StatusTypeDef status;
@@ -1300,7 +1310,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
* @param Timeout Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout)
{
HAL_StatusTypeDef status;
uint32_t algo;
@@ -1420,26 +1431,26 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
- if (hcryp->ResumingFlag == 1U)
- {
- hcryp->ResumingFlag = 0U;
- if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
- {
- hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
- hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
- }
- else
- {
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
- }
- }
- else
+ if (hcryp->ResumingFlag == 1U)
+ {
+ hcryp->ResumingFlag = 0U;
+ if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
+ {
+ hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
+ hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
+ }
+ else
+ {
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ }
+ }
+ else
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
- {
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
- }
+ {
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ }
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
@@ -1530,26 +1541,26 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
- if (hcryp->ResumingFlag == 1U)
- {
- hcryp->ResumingFlag = 0U;
- if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
- {
- hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
- hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
- }
- else
- {
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
- }
- }
- else
+ if (hcryp->ResumingFlag == 1U)
+ {
+ hcryp->ResumingFlag = 0U;
+ if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
+ {
+ hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
+ hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
+ }
+ else
+ {
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ }
+ }
+ else
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
- {
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
- }
+ {
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ }
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
@@ -1703,7 +1714,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Start DMA process transfer for AES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), \
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
status = HAL_OK;
break;
@@ -1856,49 +1868,51 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
*/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
{
+ uint32_t itsource = hcryp->Instance->CR;
+ uint32_t itflag = hcryp->Instance->SR;
/* Check if error occurred */
- if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET)
+ if ((itsource & CRYP_IT_ERRIE) == CRYP_IT_ERRIE)
{
/* If write Error occurred */
- if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET)
+ if ((itflag & CRYP_IT_WRERR) == CRYP_IT_WRERR)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
}
/* If read Error occurred */
- if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET)
+ if ((itflag & CRYP_IT_RDERR) == CRYP_IT_RDERR)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
}
}
- if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
- {
- if(__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
+ if ((itflag & CRYP_IT_CCF) == CRYP_IT_CCF)
{
- /* Clear computation complete flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
+ if ((itsource & CRYP_IT_CCFIE) == CRYP_IT_CCFIE)
{
+ /* Clear computation complete flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* if header phase */
- if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
+ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
{
- CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+
+ /* if header phase */
+ if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
+ {
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ }
}
- else /* if payload phase */
+ else /* AES Algorithm ECB,CBC or CTR*/
{
- CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ CRYP_AES_IT(hcryp);
}
}
- else /* AES Algorithm ECB,CBC or CTR*/
- {
- CRYP_AES_IT(hcryp);
- }
}
}
-}
/**
* @brief Return the CRYP error code.
@@ -2106,15 +2120,17 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ /* Increment the pointer before writing the input block in the IN FIFO to make sure that
+ when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
+ and it is ready for the next operation. */
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
}
else
{
@@ -2134,7 +2150,7 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
* @param hcryp pointer to a CRYP_HandleTypeDef structure
* @param Timeout Specify Timeout value
* @retval HAL status
-*/
+ */
static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint16_t incount; /* Temporary CrypInCount Value */
@@ -2307,8 +2323,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -2352,15 +2367,17 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ /* Increment the pointer before writing the input block in the IN FIFO to make sure that
+ when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
+ and it is ready for the next operation. */
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
}
else
{
@@ -2436,8 +2453,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -2504,8 +2520,9 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
uint32_t headersize_in_bytes;
uint32_t tmp;
static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
/* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
@@ -2587,7 +2604,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
This case can only occur for GCM and CCM with a payload length
not a multiple of 16 bytes */
if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \
- (((hcryp->Size) % 16U) != 0U)))
+ (((hcryp->Size) % 16U) != 0U)))
{
/* Call input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -2677,12 +2694,13 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
/*Read the output block from the output FIFO */
for (count = 0U; count < 4U; count++)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer */
temp[count] = hcryp->Instance->DOUTR;
}
count = 0U;
- while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U))
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count];
hcryp->CrypOutCount++;
@@ -2690,7 +2708,8 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
}
}
- if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
+ if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
+ && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
{
/* Disable CRYP (not allowed in GCM)*/
__HAL_CRYP_DISABLE(hcryp);
@@ -2887,13 +2906,14 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
}
- i= 0U;
- while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
@@ -2916,19 +2936,20 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
if (hcryp->State == HAL_CRYP_STATE_BUSY)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
}
- i= 0U;
- while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
i++;
}
- if (hcryp->CrypOutCount == (hcryp->Size / 4U))
+ if (hcryp->CrypOutCount == (hcryp->Size / 4U))
{
/* Disable Computation Complete flag and errors interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
@@ -2964,13 +2985,13 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
/* reset SuspendRequest */
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
/* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_SUSPENDED;
/* Mark that the payload phase is suspended */
hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hcryp);
}
else
@@ -2986,7 +3007,7 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ if (hcryp->CrypInCount == (hcryp->Size / 4U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3242,7 +3263,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
/*Read the output block from the output FIFO */
for (index = 0U; index < 4U; index++)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer */
temp[index] = hcryp->Instance->DOUTR;
}
for (index = 0U; index < lastwordsize; index++)
@@ -3272,8 +3294,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
uint32_t headersize_in_bytes;
uint32_t tmp;
static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
@@ -3358,8 +3381,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -3408,7 +3430,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3499,10 +3521,10 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
loopcounter++;
hcryp->CrypHeaderCount++ ;
/* Pad the data with zeros to have a complete block */
- while (loopcounter < 4U)
- {
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
hcryp->CrypHeaderCount++;
}
}
@@ -3526,10 +3548,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
header has already been processed;
only process here message payload */
{
-
- /* Enable computation complete flag and error interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
-
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
@@ -3555,7 +3573,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3566,6 +3584,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
}
else /* Size < 16Bytes : first block is the last block*/
{
@@ -3614,6 +3635,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
}
}
@@ -3696,8 +3720,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -3842,7 +3865,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
@@ -3910,10 +3933,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer */
temp[loopcounter] = hcryp->Instance->DOUTR;
}
- for (loopcounter = 0U; loopcounterpCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter];
hcryp->CrypOutCount++;
@@ -3942,8 +3966,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
uint32_t headersize_in_bytes;
uint32_t tmp;
static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
@@ -4016,8 +4041,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -4070,16 +4094,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
}
else if (hcryp->Size >= 16U)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
- if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -4164,12 +4188,12 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
hcryp->CrypHeaderCount++;
loopcounter++;
/* Pad the data with zeros to have a complete block */
- while (loopcounter < 4U)
- {
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
- }
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
@@ -4183,14 +4207,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
/* Write the first input header block in the Input FIFO,
the following header data will be fed after interrupt occurrence */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
}/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/
} /* end of if (dokeyivconfig == 1U) */
else /* Key and IV have already been configured,
@@ -4211,16 +4235,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
}
else if (hcryp->Size >= 16U)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
- if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -4358,8 +4382,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -4405,13 +4428,14 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
/***************************** Payload phase *******************************/
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
}
- i= 0U;
- while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
@@ -4419,15 +4443,15 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
}
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
- if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size))
+ if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size))
{
- /* When in CCM with Key and IV configuration skipped, don't disable interruptions */
- if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U)))
- {
+ /* When in CCM with Key and IV configuration skipped, don't disable interruptions */
+ if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U)))
+ {
/* Disable computation complete flag and errors interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
- }
+ }
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
@@ -4459,40 +4483,40 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
/* reset SuspendRequest */
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
/* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_SUSPENDED;
/* Mark that the payload phase is suspended */
hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hcryp);
}
else
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
{
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
- {
- /* Call input transfer complete callback */
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ {
+ /* Call input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
}
- }
else /* Last block of payload < 128bit*/
{
/* Compute the number of padding bytes in last block of payload */
@@ -4528,13 +4552,13 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
- /* Call input transfer complete callback */
+ /* Call input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
@@ -4579,9 +4603,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr
npblb = 16U - (uint32_t)hcryp->Size;
/* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/
- reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE);
- if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\
- (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT)))
+ reg = hcryp->Instance->CR & (AES_CR_CHMOD | AES_CR_MODE);
+ if ((reg == (CRYP_AES_GCM_GMAC | CRYP_OPERATINGMODE_ENCRYPT)) || \
+ (reg == (CRYP_AES_CCM | CRYP_OPERATINGMODE_DECRYPT)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
@@ -4636,8 +4660,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -4645,7 +4668,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr
/*Read the output block from the output FIFO */
for (index = 0U; index < 4U; index++)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer */
temp[index] = hcryp->Instance->DOUTR;
}
for (index = 0U; index < lastwordsize; index++)
@@ -4660,13 +4684,13 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr
/* Process unlocked */
__HAL_UNLOCK(hcryp);
- /* Call Output transfer complete callback */
+ /* Call Output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered Output complete callback*/
- hcryp->OutCpltCallback(hcryp);
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
#else
- /*Call legacy weak Output complete callback*/
- HAL_CRYP_OutCpltCallback(hcryp);
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
@@ -4686,8 +4710,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
uint32_t size_in_bytes;
uint32_t tmp;
static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
@@ -4789,17 +4814,17 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
}
else
{
- /* Enter last bytes, padded with zeros */
- tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
- hcryp->Instance->DINR = tmp;
- loopcounter++;
- /* Pad the data with zeros to have a complete block */
- while (loopcounter < 4U)
- {
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
- }
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
@@ -4846,8 +4871,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
uint32_t headersize_in_bytes;
uint32_t tmp;
static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
@@ -4874,7 +4900,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
if (headersize_in_bytes >= 16U)
{
/* Initiate header DMA transfer */
- if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK)
+ if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header),
+ (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4967,8 +4994,9 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
uint32_t headersize_in_bytes;
uint32_t tmp;
static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
- 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
- 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+ }; /* 8-bit data type */
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
@@ -5019,7 +5047,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call the input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -5089,28 +5117,28 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
/* reset SuspendRequest */
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
/* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_SUSPENDED;
/* Mark that the payload phase is suspended */
hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hcryp);
}
else
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
{
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++;
- }
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ }
}
else /* Write last header block (4 words), padded with zeros if needed */
{
@@ -5140,10 +5168,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
loopcounter++;
hcryp->CrypHeaderCount++;
/* Pad the data with zeros to have a complete block */
- while (loopcounter < 4U)
- {
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
hcryp->CrypHeaderCount++;
}
}
@@ -5207,15 +5235,14 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout
hcryp->State = HAL_CRYP_STATE_READY;
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -5231,17 +5258,17 @@ static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout
* as soon as the suspended processing has to be resumed.
* @retval None
*/
-static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output)
+static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output)
{
uint32_t outputaddr = (uint32_t)Output;
- *(uint32_t*)(outputaddr) = hcryp->Instance->IVR3;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->IVR2;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->IVR1;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->IVR0;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->IVR3;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->IVR2;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->IVR1;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->IVR0;
}
/**
@@ -5254,17 +5281,17 @@ static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output)
* @note AES must be disabled when reconfiguring the IV values.
* @retval None
*/
-static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input)
+static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input)
{
uint32_t ivaddr = (uint32_t)Input;
- hcryp->Instance->IVR3 = *(uint32_t*)(ivaddr);
- ivaddr+=4U;
- hcryp->Instance->IVR2 = *(uint32_t*)(ivaddr);
- ivaddr+=4U;
- hcryp->Instance->IVR1 = *(uint32_t*)(ivaddr);
- ivaddr+=4U;
- hcryp->Instance->IVR0 = *(uint32_t*)(ivaddr);
+ hcryp->Instance->IVR3 = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->IVR2 = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->IVR1 = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->IVR0 = *(uint32_t *)(ivaddr);
}
/**
@@ -5277,52 +5304,52 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input)
* as soon as the suspended processing has to be resumed.
* @retval None
*/
-static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output)
+static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output)
{
uint32_t outputaddr = (uint32_t)Output;
__IO uint32_t count = 0U;
/* In case of GCM payload phase encryption, check that suspension can be carried out */
- if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0U))
+ if (READ_BIT(hcryp->Instance->CR,
+ (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | AES_CR_GCMPH_1 | 0x0U))
{
- /* Wait for BUSY flag to be cleared */
- count = 0xFFF;
- do
+ /* Wait for BUSY flag to be cleared */
+ count = 0xFFF;
+ do
+ {
+ count-- ;
+ if (count == 0U)
{
- count-- ;
- if(count == 0U)
- {
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- return;
- }
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ HAL_CRYP_ErrorCallback(hcryp);
+ return;
}
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY));
+ } while (HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY));
}
- *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP7R;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP6R;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP5R;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP4R;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP3R;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP2R;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP1R;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP0R;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP7R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP6R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP5R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP4R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP3R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP2R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP1R;
+ outputaddr += 4U;
+ *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP0R;
}
/**
@@ -5335,25 +5362,25 @@ static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Outp
* @note AES must be disabled when reconfiguring the suspend registers.
* @retval None
*/
-static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input)
+static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input)
{
uint32_t ivaddr = (uint32_t)Input;
- hcryp->Instance->SUSP7R = *(uint32_t*)(ivaddr);
- ivaddr+=4U;
- hcryp->Instance->SUSP6R = *(uint32_t*)(ivaddr);
- ivaddr+=4U;
- hcryp->Instance->SUSP5R = *(uint32_t*)(ivaddr);
- ivaddr+=4U;
- hcryp->Instance->SUSP4R = *(uint32_t*)(ivaddr);
- ivaddr+=4U;
- hcryp->Instance->SUSP3R = *(uint32_t*)(ivaddr);
- ivaddr+=4U;
- hcryp->Instance->SUSP2R = *(uint32_t*)(ivaddr);
- ivaddr+=4U;
- hcryp->Instance->SUSP1R = *(uint32_t*)(ivaddr);
- ivaddr+=4U;
- hcryp->Instance->SUSP0R = *(uint32_t*)(ivaddr);
+ hcryp->Instance->SUSP7R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP6R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP5R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP4R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP3R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP2R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP1R = *(uint32_t *)(ivaddr);
+ ivaddr += 4U;
+ hcryp->Instance->SUSP0R = *(uint32_t *)(ivaddr);
}
/**
@@ -5366,37 +5393,37 @@ static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Inp
* as soon as the suspended processing has to be resumed.
* @retval None
*/
-static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize)
+static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t KeySize)
{
uint32_t keyaddr = (uint32_t)Output;
switch (KeySize)
{
case CRYP_KEYSIZE_256B:
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U);
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U);
break;
case CRYP_KEYSIZE_128B:
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
+ keyaddr += 4U;
+ *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
break;
default:
break;
@@ -5414,29 +5441,29 @@ static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output,
* @note AES must be disabled when reconfiguring the Key registers.
* @retval None
*/
-static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize)
+static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t KeySize)
{
uint32_t keyaddr = (uint32_t)Input;
if (KeySize == CRYP_KEYSIZE_256B)
{
- hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr);
- keyaddr+=4U;
- hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr);
- keyaddr+=4U;
- hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr);
- keyaddr+=4U;
- hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr);
- keyaddr+=4U;
+ hcryp->Instance->KEYR7 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR6 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR5 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR4 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
}
- hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr);
- keyaddr+=4U;
- hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr);
- keyaddr+=4U;
- hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr);
- keyaddr+=4U;
- hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr);
+ hcryp->Instance->KEYR3 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR2 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR1 = *(uint32_t *)(keyaddr);
+ keyaddr += 4U;
+ hcryp->Instance->KEYR0 = *(uint32_t *)(keyaddr);
}
/**
@@ -5464,7 +5491,7 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
/* Case of header phase resumption =================================================*/
if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
{
- /* Set the phase */
+ /* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Select header phase */
@@ -5473,24 +5500,24 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
{
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}
else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
{
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
+ for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
- while(loopcounter <4U )
+ while (loopcounter < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
@@ -5513,18 +5540,18 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
- if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
+ if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
{
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
@@ -5539,32 +5566,32 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
else /* Last block of payload < 128bit*/
{
/* Compute the number of padding bytes in last block of payload */
- npblb = (((hcryp->Size/16U)+1U)*16U) - (hcryp->Size);
+ npblb = (((hcryp->Size / 16U) + 1U) * 16U) - (hcryp->Size);
cr_temp = hcryp->Instance->CR;
- if((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
- (((cr_temp& AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+ if ((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
+ (((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb)<< 20U);
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb) << 20U);
}
/* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) ==0U)
+ if ((npblb % 4U) == 0U)
{
- lastwordsize = (16U-npblb)/4U;
+ lastwordsize = (16U - npblb) / 4U;
}
else
{
- lastwordsize = ((16U-npblb)/4U) +1U;
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
- while(loopcounter < 4U )
+ while (loopcounter < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
@@ -5588,5 +5615,5 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
*/
/**
- * @}
- */
+ * @}
+ */
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp_ex.c
index c07e3d49ec..a4ef77d1b5 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp_ex.c
@@ -71,8 +71,8 @@
*/
/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
- * @brief Extended processing functions.
- *
+ * @brief Extended processing functions.
+ *
@verbatim
==============================================================================
##### Extended AES processing functions #####
@@ -161,7 +161,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if (((HAL_GetTick() - tickstart) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
@@ -267,7 +267,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac.c
index a6b2620c97..bd96dc769c 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac.c
@@ -66,15 +66,6 @@
(@) Refer to the device datasheet for more details about output
impedance value with and without output buffer.
- *** DAC connect feature ***
- ===============================
- [..]
- Each DAC channel can be connected internally.
- To connect, use
- sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
- or
- sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH;
-
*** GPIO configurations guidelines ***
=====================
[..]
@@ -253,7 +244,7 @@
and a pointer to the user callback function.
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
@@ -268,9 +259,9 @@
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
+ reset to the legacy weak (overridden) functions in the HAL_DAC_Init
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -285,7 +276,7 @@
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
@@ -365,7 +356,7 @@
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
{
- /* Check DAC handle */
+ /* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
@@ -426,7 +417,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
*/
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
{
- /* Check DAC handle */
+ /* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
@@ -529,6 +520,12 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -584,6 +581,12 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -614,11 +617,17 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
HAL_StatusTypeDef status;
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg;
+
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -655,12 +664,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
break;
- case DAC_ALIGN_8B_R:
+ default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
break;
- default:
- break;
}
}
@@ -689,17 +696,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
/* Get DHR12L2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
break;
- case DAC_ALIGN_8B_R:
+ default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
break;
- default:
- break;
}
}
-
- /* Enable the DMA channel */
if (Channel == DAC_CHANNEL_1)
{
/* Enable the DAC DMA underrun interrupt */
@@ -748,6 +751,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -796,10 +805,13 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
{
- if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ uint32_t itsource = hdac->Instance->CR;
+ uint32_t itflag = hdac->Instance->SR;
+
+ if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
{
/* Check underrun flag of DAC channel 1 */
- if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
@@ -811,7 +823,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
/* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -823,10 +835,10 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
}
- if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
+ if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
{
/* Check underrun flag of DAC channel 2 */
- if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
@@ -838,7 +850,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
/* Disable the selected DAC channel2 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -871,6 +883,12 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui
{
__IO uint32_t tmp = 0UL;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
@@ -988,10 +1006,13 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
+uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
uint32_t result;
+ /* Check the DAC peripheral handle */
+ assert_param(hdac != NULL);
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -1025,13 +1046,20 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
+ const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpreg1;
uint32_t tmpreg2;
uint32_t tickstart;
- uint32_t hclkfreq;
- uint32_t connectOnChip;
+ uint32_t pclk1freq;
+
+ /* Check the DAC peripheral handle and channel configuration struct */
+ if ((hdac == NULL) || (sConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
/* Check the DAC parameters */
assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency));
@@ -1073,7 +1101,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* New check to avoid false timeout detection in case of preemption */
- if(((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
+ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
@@ -1085,7 +1113,6 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
}
}
}
- HAL_Delay(1UL);
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
@@ -1098,7 +1125,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* New check to avoid false timeout detection in case of preemption */
- if(((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
+ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
@@ -1110,7 +1137,6 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
}
}
}
- HAL_Delay(1UL);
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
@@ -1145,26 +1171,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
/* Clear DAC_MCR_MODEx bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
- if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
- {
- connectOnChip = 0x00000000UL;
- }
- else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
- {
- connectOnChip = DAC_MCR_MODE1_0;
- }
- else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
- {
- if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
- {
- connectOnChip = DAC_MCR_MODE1_0;
- }
- else
- {
- connectOnChip = 0x00000000UL;
- }
- }
- tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
+ tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
/* Calculate MCR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
/* Write to DAC MCR */
@@ -1194,15 +1201,15 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
}
else /* Automatic selection */
{
- hclkfreq = HAL_RCC_GetHCLKFreq();
- if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ)
+ pclk1freq = HAL_RCC_GetPCLK1Freq();
+ if (pclk1freq > HFSEL_ENABLE_THRESHOLD_80MHZ)
{
- /* High frequency enable when HCLK frequency higher than 80 */
+ /* High frequency enable when PCLK frequency higher than 80 */
tmpreg1 |= DAC_CR_HFSEL;
}
else
{
- /* High frequency disable when HCLK frequency higher than 80 */
+ /* High frequency disable when PCLK frequency higher than 80 */
tmpreg1 &= ~(DAC_CR_HFSEL);
}
}
@@ -1219,7 +1226,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
__HAL_UNLOCK(hdac);
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1248,7 +1255,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
* the configuration information for the specified DAC.
* @retval HAL state
*/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
+HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
{
/* Return DAC handle state */
return hdac->State;
@@ -1261,7 +1268,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
* the configuration information for the specified DAC.
* @retval DAC Error Code
*/
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
{
return hdac->ErrorCode;
}
@@ -1284,7 +1291,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (overridden) predefined callback
+ * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
+ * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1308,6 +1317,12 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
{
HAL_StatusTypeDef status = HAL_OK;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
if (pCallback == NULL)
{
/* Update the error code */
@@ -1315,9 +1330,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hdac);
-
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
@@ -1388,14 +1400,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hdac);
return status;
}
/**
* @brief Unregister a User DAC Callback
- * DAC Callback is redirected to the weak (surcharged) predefined callback
+ * DAC Callback is redirected to the weak (overridden) predefined callback
+ * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
+ * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1416,8 +1428,11 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hdac);
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
if (hdac->State == HAL_DAC_STATE_READY)
{
@@ -1503,8 +1518,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hdac);
return status;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
@@ -1590,8 +1603,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
#endif /* DAC1 */
#endif /* HAL_DAC_MODULE_ENABLED */
-
/**
* @}
*/
-
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac_ex.c
index efaf3a630e..de24089e54 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac_ex.c
@@ -23,7 +23,6 @@
##### How to use this driver #####
==============================================================================
[..]
-
*** Dual mode IO operation ***
==============================
[..]
@@ -45,7 +44,6 @@
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
Channel 1 and Channel 2.
-
*** Signal generation operation ***
===================================
[..]
@@ -81,6 +79,16 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+
+/* Delay for DAC minimum trimming time. */
+/* Note: minimum time needed between two calibration steps */
+/* The delay below is specified under conditions: */
+/* - DAC channel output buffer enabled */
+/* Literal set to maximum value (refer to device datasheet, */
+/* electrical characteristics, parameter "tTRIM"). */
+/* Unit: us */
+#define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -120,6 +128,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
{
uint32_t tmp_swtrig = 0UL;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Process locked */
__HAL_LOCK(hdac);
@@ -161,6 +175,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
*/
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
@@ -190,12 +210,18 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
- uint32_t Alignment)
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
+ const uint32_t *pData, uint32_t Length, uint32_t Alignment)
{
HAL_StatusTypeDef status;
uint32_t tmpreg = 0UL;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
@@ -303,6 +329,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann
{
HAL_StatusTypeDef status;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Disable the selected DAC channel DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
@@ -374,6 +406,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann
*/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
@@ -424,6 +462,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32
*/
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
@@ -469,6 +513,12 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Align
uint32_t data;
uint32_t tmp;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
assert_param(IS_DAC_DATA(Data1));
@@ -576,9 +626,9 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
{
HAL_StatusTypeDef status = HAL_OK;
- __IO uint32_t tmp;
uint32_t trimmingvalue;
uint32_t delta;
+ __IO uint32_t wait_loop_index;
/* store/restore channel configuration structure purpose */
uint32_t oldmodeconfiguration;
@@ -588,7 +638,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
/* Check the DAC handle allocation */
/* Check if DAC running */
- if (hdac == NULL)
+ if ((hdac == NULL) || (sConfig == NULL))
{
status = HAL_ERROR;
}
@@ -610,20 +660,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
/* Set mode in MCR for calibration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
- /* Set DAC Channel1 DHR register to the middle value */
- tmp = (uint32_t)hdac->Instance;
-
- if (Channel == DAC_CHANNEL_1)
- {
- tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
- }
- else
- {
- tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
- }
-
- *(__IO uint32_t *) tmp = 0x0800UL;
-
/* Enable the selected DAC channel calibration */
/* i.e. set DAC_CR_CENx bit */
SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
@@ -637,9 +673,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
- /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
- /* i.e. minimum time needed between two calibration steps */
- HAL_Delay(1UL);
+ /* Wait minimum time needed between two calibration steps (OTRIM) */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
+ /* 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
{
@@ -659,9 +701,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
- /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
- /* i.e. minimum time needed between two calibration steps */
- HAL_Delay(1UL);
+ /* Wait minimum time needed between two calibration steps (OTRIM) */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
+ /* 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
@@ -709,8 +757,8 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
- /* Check the DAC handle allocation */
- if (hdac == NULL)
+ /* Check the DAC handle and channel configuration struct allocation */
+ if ((hdac == NULL) || (sConfig == NULL))
{
status = HAL_ERROR;
}
@@ -742,7 +790,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel
* @retval Trimming value : range: 0->31
*
*/
-uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameter */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -776,7 +824,7 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
+uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
{
uint32_t tmp = 0UL;
@@ -877,4 +925,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
/**
* @}
*/
-
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_exti.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_exti.c
index 55ccc4c86b..36a2216ad6 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_exti.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_exti.c
@@ -65,7 +65,7 @@
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
- (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+ (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
@@ -76,7 +76,7 @@
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
- (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+ (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_fdcan.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_fdcan.c
index c2cdab02c0..94f91bdb8c 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_fdcan.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_fdcan.c
@@ -96,7 +96,7 @@
*** Callback registration ***
=============================================
- The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
+ The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
to register an interrupt callback.
@@ -114,7 +114,7 @@
For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated
- register callbacks : respectively HAL_FDCAN_RegisterTxEventFifoCallback(),
+ register callbacks: respectively HAL_FDCAN_RegisterTxEventFifoCallback(),
HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback()
and HAL_FDCAN_RegisterErrorStatusCallback().
@@ -134,7 +134,7 @@
For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated
- unregister callbacks : respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(),
+ unregister callbacks: respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(),
HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(),
HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback()
and HAL_FDCAN_UnRegisterErrorStatusCallback().
@@ -249,9 +249,15 @@ static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24,
*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FDCAN_Private_Functions_Prototypes
+ * @{
+ */
static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
-static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
- uint32_t BufferIndex);
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+ const uint8_t *pTxData, uint32_t BufferIndex);
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
@@ -324,22 +330,17 @@ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
hfdcan->Lock = HAL_UNLOCKED;
/* Reset callbacks to legacy functions */
- hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
- hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
- hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
- hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
- hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak
- TxBufferCompleteCallback */
- hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak
- TxBufferAbortCallback */
- hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak
- HighPriorityMessageCallback */
- hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak
- TimestampWraparoundCallback */
- hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak
- TimeoutOccurredCallback */
- hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */
- hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
+ hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* TxEventFifoCallback */
+ hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* RxFifo0Callback */
+ hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* RxFifo1Callback */
+ hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* TxFifoEmptyCallback */
+ hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* TxBufferCompleteCallback */
+ hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* TxBufferAbortCallback */
+ hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */
+ hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */
+ hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* TimeoutOccurredCallback */
+ hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* ErrorCallback */
+ hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* ErrorStatusCallback */
if (hfdcan->MspInitCallback == NULL)
{
@@ -575,7 +576,7 @@ __weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_MspInit could be implemented in the user file
*/
}
@@ -590,7 +591,7 @@ __weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_MspDeInit could be implemented in the user file
*/
}
@@ -1285,7 +1286,7 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h
* contains the filter configuration information
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig)
{
uint32_t FilterElementW1;
uint32_t FilterElementW2;
@@ -1410,7 +1411,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param Mask Extended ID Mask.
- This parameter must be a number between 0 and 0x1FFFFFFF
+ * This parameter must be a number between 0 and 0x1FFFFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
@@ -1600,7 +1601,7 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
* the configuration information for the specified FDCAN.
* @retval Timestamp counter value
*/
-uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan)
{
return (uint16_t)(hfdcan->Instance->TSCV);
}
@@ -1723,7 +1724,7 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
* the configuration information for the specified FDCAN.
* @retval Timeout counter value
*/
-uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan)
{
return (uint16_t)(hfdcan->Instance->TOCV);
}
@@ -2096,8 +2097,8 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
* @param pTxData pointer to a buffer containing the payload of the Tx frame.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
- uint8_t *pTxData)
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+ const uint8_t *pTxData)
{
uint32_t PutIndex;
@@ -2164,7 +2165,7 @@ HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDC
* - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
* - 0 if no Tx FIFO/Queue request have been submitted.
*/
-uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan)
{
/* Return Last Tx FIFO/Queue Request Buffer */
return hfdcan->LatestTxFifoQRequest;
@@ -2216,7 +2217,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
uint32_t *RxAddress;
uint8_t *pData;
uint32_t ByteCounter;
- uint32_t GetIndex;
+ uint32_t GetIndex = 0;
HAL_FDCAN_StateTypeDef state = hfdcan->State;
/* Check function parameters */
@@ -2236,8 +2237,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
}
else
{
+ /* Check that the Rx FIFO 0 is full & overwrite mode is on */
+ if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U)
+ {
+ if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+ {
+ /* When overwrite status is on discard first message in FIFO */
+ GetIndex = 1U;
+ }
+ }
+
+ /* Calculate Rx FIFO 0 element index */
+ GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+
/* Calculate Rx FIFO 0 element address */
- GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE));
}
}
@@ -2253,8 +2266,19 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
}
else
{
+ /* Check that the Rx FIFO 1 is full & overwrite mode is on */
+ if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U)
+ {
+ if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+ {
+ /* When overwrite status is on discard first message in FIFO */
+ GetIndex = 1U;
+ }
+ }
+
+ /* Calculate Rx FIFO 1 element index */
+ GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
/* Calculate Rx FIFO 1 element address */
- GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE));
}
}
@@ -2285,7 +2309,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
/* Retrieve DataLength */
- pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
+ pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
/* Retrieve BitRateSwitch */
pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
@@ -2304,7 +2328,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
/* Retrieve Rx payload */
pData = (uint8_t *)RxAddress;
- for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U]; ByteCounter++)
+ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++)
{
pRxData[ByteCounter] = pData[ByteCounter];
}
@@ -2386,7 +2410,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven
pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
/* Retrieve DataLength */
- pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
+ pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
/* Retrieve BitRateSwitch */
pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
@@ -2422,7 +2446,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven
* @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
{
HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
@@ -2441,7 +2465,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hf
* @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
{
uint32_t StatusReg;
@@ -2472,7 +2497,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN
* @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_ErrorCountersTypeDef *ErrorCounters)
{
uint32_t CountersReg;
@@ -2496,10 +2522,10 @@ HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_
* @param TxBufferIndex Tx buffer index.
* This parameter can be any combination of @arg FDCAN_Tx_location.
* @retval Status
- * - 0 : No pending transmission request on TxBufferIndex list
+ * - 0 : No pending transmission request on TxBufferIndex list.
* - 1 : Pending transmission request on TxBufferIndex.
*/
-uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
{
/* Check function parameters */
assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex));
@@ -2522,7 +2548,7 @@ uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_
* @arg FDCAN_RX_FIFO1: Rx FIFO 1
* @retval Rx FIFO fill level.
*/
-uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
{
uint32_t FillLevel;
@@ -2549,7 +2575,7 @@ uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
* the configuration information for the specified FDCAN.
* @retval Tx FIFO free level.
*/
-uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan)
{
uint32_t FreeLevel;
@@ -2567,7 +2593,7 @@ uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
* - 0 : Normal FDCAN operation.
* - 1 : Restricted Operation Mode active.
*/
-uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan)
{
uint32_t OperationMode;
@@ -3138,7 +3164,7 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
* @brief Tx Event callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
- * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signalled.
+ * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
* This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
* @retval None
*/
@@ -3148,7 +3174,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
UNUSED(hfdcan);
UNUSED(TxEventFifoITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
*/
}
@@ -3157,7 +3183,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
* @brief Rx FIFO 0 callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
- * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signalled.
+ * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
* This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
* @retval None
*/
@@ -3167,7 +3193,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
UNUSED(hfdcan);
UNUSED(RxFifo0ITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
*/
}
@@ -3176,7 +3202,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
* @brief Rx FIFO 1 callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
- * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled.
+ * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
* This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
* @retval None
*/
@@ -3186,7 +3212,7 @@ __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
UNUSED(hfdcan);
UNUSED(RxFifo1ITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
*/
}
@@ -3202,7 +3228,7 @@ __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
*/
}
@@ -3221,7 +3247,7 @@ __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint
UNUSED(hfdcan);
UNUSED(BufferIndexes);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
*/
}
@@ -3240,7 +3266,7 @@ __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_
UNUSED(hfdcan);
UNUSED(BufferIndexes);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
*/
}
@@ -3256,7 +3282,7 @@ __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
*/
}
@@ -3272,7 +3298,7 @@ __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
*/
}
@@ -3288,7 +3314,7 @@ __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
*/
}
@@ -3304,7 +3330,7 @@ __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ErrorCallback could be implemented in the user file
*/
}
@@ -3323,7 +3349,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
UNUSED(hfdcan);
UNUSED(ErrorStatusITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
*/
}
@@ -3353,7 +3379,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
* the configuration information for the specified FDCAN.
* @retval HAL state
*/
-HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan)
{
/* Return FDCAN state */
return hfdcan->State;
@@ -3365,7 +3391,7 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
* the configuration information for the specified FDCAN.
* @retval FDCAN Error Code
*/
-uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
+uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan)
{
/* Return FDCAN error code */
return hfdcan->ErrorCode;
@@ -3434,8 +3460,8 @@ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
* @param BufferIndex index of the buffer to be configured.
* @retval none
*/
-static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
- uint32_t BufferIndex)
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+ const uint8_t *pTxData, uint32_t BufferIndex)
{
uint32_t TxElementW1;
uint32_t TxElementW2;
@@ -3463,7 +3489,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy
pTxHeader->TxEventFifoControl |
pTxHeader->FDFormat |
pTxHeader->BitRateSwitch |
- pTxHeader->DataLength);
+ (pTxHeader->DataLength << 16U));
/* Calculate Tx element address */
TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE));
@@ -3475,7 +3501,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy
TxAddress++;
/* Write Tx payload to the message RAM */
- for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U]; ByteCounter += 4U)
+ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U)
{
*TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_gpio.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_gpio.c
index 022b272f95..1d2c29c2fb 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_gpio.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_gpio.c
@@ -361,7 +361,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
* @brief Read the specified input port pin.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L5 family
* @param GPIO_Pin specifies the port bit to read.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
@@ -391,7 +391,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
*
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L5 family
* @param GPIO_Pin specifies the port bit to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
@@ -418,7 +418,7 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
* @brief Toggle the specified GPIO pin.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L5 family
* @param GPIO_Pin specifies the pin to be toggled.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
@@ -443,8 +443,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
* until the next reset.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L5 family
* @param GPIO_Pin specifies the port bits to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ * @retval HAL Status.
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
@@ -556,8 +556,6 @@ __weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
*/
void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes)
{
- uint32_t position = 0U;
- uint32_t iocurrent;
uint32_t temp;
/* Check the parameters */
@@ -565,21 +563,15 @@ void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ATTRIBUTES(PinAttributes));
- temp = GPIOx->SECCFGR;
-
/* Configure the port pins */
- while ((GPIO_Pin >> position) != 0U)
+ temp = GPIOx->SECCFGR;
+ if (PinAttributes != GPIO_PIN_NSEC)
{
- /* Get current io position */
- iocurrent = GPIO_Pin & (1UL << position);
-
- if (iocurrent != 0U)
- {
- /* Configure the IO secure attribute */
- temp &= ~(GPIO_SECCFGR_SEC0 << position) ;
- temp |= (PinAttributes << position);
- }
- position++;
+ temp |= (uint32_t)GPIO_Pin;
+ }
+ else
+ {
+ temp &= ~((uint32_t)GPIO_Pin);
}
/* Set secure attributes */
@@ -597,9 +589,6 @@ void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32
*/
HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes)
{
- uint32_t position = 0U;
- uint32_t iocurrent;
-
/* Check null pointer */
if (pPinAttributes == NULL)
{
@@ -611,26 +600,13 @@ HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t
assert_param(IS_GPIO_PIN(GPIO_Pin) && (GPIO_Pin != GPIO_PIN_All));
/* Get secure attribute of the port pin */
- while ((GPIO_Pin >> position) != 0U)
+ if ((GPIOx->SECCFGR & GPIO_Pin) != 0x00U)
{
- /* Get current io position */
- iocurrent = GPIO_Pin & (1UL << position);
-
- if (iocurrent != 0U)
- {
- /* Get the IO secure attribute */
- if ((GPIOx->SECCFGR & (GPIO_SECCFGR_SEC0 << position)) != 0U)
- {
- *pPinAttributes = GPIO_PIN_SEC;
- }
- else
- {
- *pPinAttributes = GPIO_PIN_NSEC;
- }
-
- break;
- }
- position++;
+ *pPinAttributes = GPIO_PIN_SEC;
+ }
+ else
+ {
+ *pPinAttributes = GPIO_PIN_NSEC;
}
return HAL_OK;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash.c
index 2e274b0ed1..7e02640d2e 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash.c
@@ -123,7 +123,7 @@
(#) HAL in interruption mode (interruptions driven)
(##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
- This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
+ This is why, for driver implementation simplicity s sake, user is requested to enter a message the
length of which is a multiple of 4 bytes.
(##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
@@ -1825,8 +1825,9 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
{
uint32_t buffercounter;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
+ uint32_t tmp;
- for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U)
+ for (buffercounter = 0U; buffercounter < (Size / 4U); buffercounter++)
{
/* Write input data 4 bytes at a time */
HASH->DIN = *(uint32_t *)inputaddr;
@@ -1834,8 +1835,16 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
- if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size))
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (((buffercounter * 4U) + 4U) < Size))
{
+ /* wait for flag BUSY not set before Wait for DINIS = 1*/
+ if ((buffercounter * 4U) >= 64U)
+ {
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
/* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
in the input buffer */
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
@@ -1850,14 +1859,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
- hhash->HashInCount = Size - (buffercounter + 4U);
+ hhash->HashInCount = Size - ((buffercounter * 4U) + 4U);
}
else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
- hhash->HashKeyCount = Size - (buffercounter + 4U);
+ hhash->HashKeyCount = Size - ((buffercounter * 4U) + 4U);
}
else
{
@@ -1876,6 +1885,52 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
} /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
/* At this point, all the data have been entered to the Peripheral: exit */
+
+ if ((Size % 4U) != 0U)
+ {
+ if (hhash->Init.DataType == HASH_DATATYPE_16B)
+ {
+ /* Write remaining input data */
+
+ if ((Size % 4U) <= 2U)
+ {
+ HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
+ }
+ if ((Size % 4U) == 3U)
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ }
+
+ }
+ else if ((hhash->Init.DataType == HASH_DATATYPE_8B)
+ || (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */
+ {
+ /* Write remaining input data */
+ if ((Size % 4U) == 1U)
+ {
+ HASH->DIN = (uint32_t) * (uint8_t *)inputaddr;
+ }
+ if ((Size % 4U) == 2U)
+ {
+ HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
+ }
+ if ((Size % 4U) == 3U)
+ {
+ tmp = *(uint8_t *)inputaddr;
+ tmp |= (uint32_t)*(uint8_t *)(inputaddr + 1U) << 8U;
+ tmp |= (uint32_t)*(uint8_t *)(inputaddr + 2U) << 16U;
+ HASH->DIN = tmp;
+ }
+
+ }
+ else
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ }
+ /*hhash->HashInCount += 4U;*/
+ }
+
+
return HAL_OK;
}
@@ -3446,7 +3501,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
/* Enable the DMA In DMA channel */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
(((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \
- : (inputSize / 4U)));
+ : (inputSize / 4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_i2c.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_i2c.c
index 394cd85aff..b1038d6836 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_i2c.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_i2c.c
@@ -90,7 +90,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@@ -156,7 +156,7 @@
HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
@@ -214,7 +214,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@@ -400,9 +400,15 @@
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Macro
+ * @{
+ */
/* Macro to get remaining data to transfer on DMA side */
#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
+/**
+ * @}
+ */
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -418,6 +424,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
/* Private functions to handle IT transfer */
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
@@ -601,7 +608,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
- hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+ }
+ else
+ {
+ /* Clear the I2C ADD10 bit */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
@@ -1108,6 +1120,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
+ uint32_t xfermode;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1131,18 +1144,39 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- I2C_GENERATE_START_WRITE);
+ xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
+ I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
I2C_GENERATE_START_WRITE);
}
@@ -1345,6 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
uint32_t Timeout)
{
uint32_t tickstart;
+ uint16_t tmpXferCount;
+ HAL_StatusTypeDef error;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1371,14 +1407,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
- /* Wait until ADDR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
/* Preload TX data if no stretch enable */
if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
{
@@ -1392,6 +1420,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
hi2c->XferCount--;
}
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ return HAL_ERROR;
+ }
+
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
@@ -1403,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
return HAL_ERROR;
}
@@ -1415,6 +1459,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
return HAL_ERROR;
}
@@ -1438,31 +1486,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
/* Wait until AF flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
+
+ if (error != HAL_OK)
{
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+
+ tmpXferCount = hi2c->XferCount;
+ if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+ {
+ /* Reset ErrorCode to NONE */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
}
+ else
+ {
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
- /* Wait until STOP flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
- return HAL_ERROR;
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
@@ -1665,7 +1730,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+ if (hi2c->XferSize > 0U)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
+ I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
+ I2C_GENERATE_START_WRITE);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1888,6 +1972,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
+ uint32_t sizetoxfer = 0U;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1920,6 +2005,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
xfermode = I2C_AUTOEND_MODE;
}
+ if (hi2c->XferSize > 0U)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ sizetoxfer = hi2c->XferSize;
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
if (hi2c->XferSize > 0U)
{
if (hi2c->hdmatx != NULL)
@@ -1935,8 +2034,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+ (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
}
else
{
@@ -1957,7 +2056,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
+ xfermode, I2C_GENERATE_START_WRITE);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -1996,7 +2096,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
I2C_GENERATE_START_WRITE);
/* Process Unlocked */
@@ -2152,11 +2252,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
}
return HAL_OK;
@@ -2406,6 +2506,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
return HAL_BUSY;
}
}
+
/**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2720,6 +2821,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
+ hi2c->XferSize = 0U;
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@@ -2841,11 +2943,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
}
@@ -2854,6 +2956,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
return HAL_BUSY;
}
}
+
/**
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -3250,22 +3353,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials == Trials)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
/* Increment Trials */
I2C_Trials++;
} while (I2C_Trials < Trials);
@@ -3304,6 +3391,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+ uint32_t sizetoxfer = 0U;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3335,6 +3423,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
xfermode = hi2c->XferOptions;
}
+ if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+ (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ sizetoxfer = hi2c->XferSize;
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
@@ -3356,7 +3459,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
}
/* Send Slave Address and set NBYTES to write */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+ if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3396,6 +3506,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
HAL_StatusTypeDef dmaxferstatus;
+ uint32_t sizetoxfer = 0U;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3427,6 +3538,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
xfermode = hi2c->XferOptions;
}
+ if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+ (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ sizetoxfer = hi2c->XferSize;
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
@@ -3462,8 +3588,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+ (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
}
else
{
@@ -3483,7 +3609,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address and set NBYTES to write */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+ if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+ }
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -3522,8 +3655,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_GENERATE_START_WRITE);
+ if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3786,11 +3925,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
}
return HAL_OK;
@@ -4425,7 +4564,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
@@ -4434,7 +4573,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{
- if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
+
+ if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -4494,7 +4635,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
* the configuration information for the specified I2C.
* @retval None
*/
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Get current IT Flags and IT sources value */
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
@@ -4747,7 +4888,7 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
* the configuration information for the specified I2C.
* @retval HAL state
*/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
{
/* Return I2C handle state */
return hi2c->State;
@@ -4759,7 +4900,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
* the configuration information for I2C module
* @retval HAL mode
*/
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
{
return hi2c->Mode;
}
@@ -4770,7 +4911,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
* the configuration information for the specified I2C.
* @retval I2C Error Code
*/
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
{
return hi2c->ErrorCode;
}
@@ -4833,17 +4974,22 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
+ ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
{
/* Write data to TXDR */
- hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+ if (hi2c->XferCount != 0U)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
- hi2c->XferSize--;
- hi2c->XferCount--;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
@@ -5030,6 +5176,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
+ /* Disable Interrupt related to address step */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
direction = I2C_GENERATE_START_READ;
@@ -5094,9 +5246,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
-
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -5396,6 +5547,9 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
+ /* Disable Interrupt related to address step */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
/* Enable only Error interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
@@ -5438,6 +5592,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
+ /* Disable Interrupt related to address step */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Enable only Error and NACK interrupt for data transfer */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
direction = I2C_GENERATE_START_READ;
@@ -5515,9 +5675,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
-
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -6116,6 +6275,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
+ uint32_t tmpoptions = hi2c->XferOptions;
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
@@ -6132,6 +6292,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
+ else if (tmpstate == HAL_I2C_STATE_LISTEN)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_NONE;
+ }
else
{
/* Do nothing */
@@ -6198,6 +6363,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hi2c->XferCount == 0U)
+ {
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, tmpITFlags);
+ }
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ }
+ }
+
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@@ -6325,6 +6541,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
uint32_t tmppreviousstate;
/* Reset handle parameters */
@@ -6381,6 +6598,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* Abort DMA TX transfer if any */
tmppreviousstate = hi2c->PreviousState;
+
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
@@ -6555,6 +6773,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
}
}
+
/**
* @brief DMA I2C slave transmit process complete callback.
* @param hdma DMA handle
@@ -6583,6 +6802,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
}
}
+
/**
* @brief DMA I2C master receive process complete callback.
* @param hdma DMA handle
@@ -6633,6 +6853,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
}
}
+
/**
* @brief DMA I2C slave receive process complete callback.
* @param hdma DMA handle
@@ -6661,6 +6882,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
}
}
+
/**
* @brief DMA I2C communication error callback.
* @param hdma DMA handle
@@ -6678,6 +6900,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
}
+
/**
* @brief DMA I2C communication abort callback
* (To be called at end of DMA Abort procedure).
@@ -6702,6 +6925,7 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
I2C_TreatErrorCallback(hi2c);
}
+
/**
* @brief This function handles I2C Communication Timeout. It waits
* until a flag is no longer in the specified status.
@@ -6718,6 +6942,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
@@ -6829,16 +7059,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ HAL_StatusTypeDef status = HAL_OK;
+
+ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
/* Check if a STOPF is detected */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
{
/* Check if an RXNE is pending */
/* Store Last receive data if any */
@@ -6846,19 +7078,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
{
/* Return HAL_OK */
/* The Reading of data from RXDR will be done in caller function */
- return HAL_OK;
+ status = HAL_OK;
}
- else
+
+ /* Check a no-acknowledge have been detected */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- {
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@@ -6872,12 +7099,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
}
/* Check for the Timeout */
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
{
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
{
@@ -6887,11 +7118,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ status = HAL_ERROR;
}
}
}
- return HAL_OK;
+ return status;
}
/**
@@ -7074,8 +7305,9 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
- if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
- (hi2c->XferISR == I2C_Slave_ISR_DMA))
+ if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
+ (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
+ (hi2c->XferISR != I2C_Mem_ISR_DMA))
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
@@ -7083,6 +7315,18 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ }
+
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
@@ -7092,32 +7336,27 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
- tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
- }
-
- if (InterruptRequest == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
+ tmpisr |= I2C_IT_STOPI;
}
}
+
else
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
- /* Enable ERR, STOP, NACK, and ADDR interrupts */
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
- /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
- /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
@@ -7130,7 +7369,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+ }
+
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
}
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_icache.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_icache.c
index 76ee82affa..ed58d88077 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_icache.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_icache.c
@@ -45,30 +45,35 @@
The ICACHE HAL driver can be used as follows:
(#) Optionally configure the Instruction Cache mode with
- @ref HAL_ICACHE_ConfigAssociativityMode() if the default configuration
+ HAL_ICACHE_ConfigAssociativityMode() if the default configuration
does not suit the application requirements.
(#) Enable and disable the Instruction Cache with respectively
- @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable().
- Use @ref HAL_ICACHE_IsEnabled() to get the Instruction Cache status.
+ HAL_ICACHE_Enable() and HAL_ICACHE_Disable().
+ Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status.
+ To ensure a deterministic cache behavior after power on, system reset or after
+ a call to @ref HAL_ICACHE_Disable(), the application must call
+ @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset
+ or cache disable, an automatic cache invalidation procedure is launched and the
+ cache is bypassed until the operation completes.
(#) Initiate the cache maintenance invalidation procedure with either
- @ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT()
+ HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT()
(interrupt mode). When interrupt mode is used, the callback function
- @ref HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate
- procedure is complete. The function @ref HAL_ICACHE_WaitForInvalidateComplete()
+ HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate
+ procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete()
may be called to wait for the end of the invalidate procedure automatically
- initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable().
+ initiated when disabling the Instruction Cache with HAL_ICACHE_Disable().
The cache operation is bypassed during the invalidation procedure.
(#) Use the performance monitoring counters for Hit and Miss with the following
- functions: @ref HAL_ICACHE_Monitor_Start(), @ref HAL_ICACHE_Monitor_Stop(),
- @ref HAL_ICACHE_Monitor_Reset(), @ref HAL_ICACHE_Monitor_GetHitValue() and
- @ref HAL_ICACHE_Monitor_GetMissValue()
+ functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(),
+ HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and
+ HAL_ICACHE_Monitor_GetMissValue()
(#) Enable and disable up to four regions to remap input address from external
memories to the internal Code region for execution with
- @ref HAL_ICACHE_EnableRemapRegion() and @ref HAL_ICACHE_DisableRemapRegion()
+ HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion()
@endverbatim
*/
@@ -84,7 +89,7 @@
* @brief HAL ICACHE module driver
* @{
*/
-#ifdef HAL_ICACHE_MODULE_ENABLED
+#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED)
/* Private typedef -----------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -183,32 +188,32 @@ HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode)
/**
* @brief DeInitialize the Instruction Cache.
- * @retval HAL status (HAL_OK/HAL_TIMEOUT)
+ * @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_DeInit(void)
{
- HAL_StatusTypeDef status;
+ /* Reset interrupt enable value */
+ WRITE_REG(ICACHE->IER, 0U);
- /* Disable cache with reset value for 2-ways set associative mode */
+ /* Clear any pending flags */
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);
+
+ /* Disable cache then set default associative mode value */
+ CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);
/* Stop monitor and reset monitor values */
- (void)HAL_ICACHE_Monitor_Stop(ICACHE_MONITOR_HIT_MISS);
- (void)HAL_ICACHE_Monitor_Reset(ICACHE_MONITOR_HIT_MISS);
+ CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS);
+ SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));
+ CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));
- /* No remapped regions */
- (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_0);
- (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_1);
- (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_2);
- (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_3);
+ /* Reset regions configuration values */
+ WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
+ WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
+ WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
+ WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
- /* Wait for end of invalidate cache procedure */
- status = HAL_ICACHE_WaitForInvalidateComplete();
-
- /* Clear any pending flags */
- WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);
-
- return status;
+ return HAL_OK;
}
/**
@@ -281,22 +286,15 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate(void)
{
HAL_StatusTypeDef status;
- /* Check no ongoing operation */
- if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
- {
- status = HAL_ERROR;
- }
- else
+ /* Check if no ongoing operation */
+ if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U)
{
- /* Make sure BSYENDF is reset before to start cache invalidation */
- WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
-
/* Launch cache invalidation */
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
-
- status = HAL_ICACHE_WaitForInvalidateComplete();
}
+ status = HAL_ICACHE_WaitForInvalidateComplete();
+
return status;
}
@@ -642,7 +640,7 @@ HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region)
* @}
*/
-#endif /* HAL_ICACHE_MODULE_ENABLED */
+#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_irda.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_irda.c
index 29d417da34..01a330e709 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_irda.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_irda.c
@@ -142,7 +142,7 @@
[..]
Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -159,10 +159,10 @@
[..]
By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
+ reset to the legacy weak functions in the HAL_IRDA_Init()
and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -179,7 +179,7 @@
[..]
When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
******************************************************************************
@@ -462,7 +462,7 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User IRDA Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
* to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
@@ -2426,7 +2426,6 @@ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
hirda->gState = HAL_IRDA_STATE_READY;
}
-
/**
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_lptim.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_lptim.c
index a1bb862124..2885d783c3 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_lptim.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_lptim.c
@@ -204,7 +204,7 @@
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
+static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag);
/* Exported functions --------------------------------------------------------*/
@@ -382,10 +382,10 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
}
else
{
- /* Check LPTIM2 and LPTIM3 Input1 source */
+ /* Check LPTIM Input1 source */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
- /* Configure LPTIM2 and LPTIM3 Input1 source */
+ /* Configure LPTIM Input1 source */
hlptim->Instance->OR = hlptim->Init.Input1Source;
}
@@ -2447,7 +2447,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
* @param hlptim LPTIM handle
* @retval HAL state
*/
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim)
{
/* Return LPTIM handle state */
return hlptim->State;
@@ -2496,7 +2496,7 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
* @param flag The lptim flag
* @retval HAL status
*/
-static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
+static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc.c
index aea3da942a..048cd48b53 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc.c
@@ -56,7 +56,6 @@
(#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
-
*** MMC Card Initialization and configuration ***
================================================
[..]
@@ -93,6 +92,7 @@
(#) Select the corresponding MMC Card according to the address read with the step 2.
(#) Configure the MMC Card in wide bus mode: 4-bits data.
+ (#) Select the MMC Card partition using HAL_MMC_SwitchPartition()
*** MMC Card Read operation ***
==============================
@@ -169,6 +169,64 @@
(+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
Some of the CID parameters are useful for card initialization and identification.
+ *** MMC Card Reply Protected Memory Block (RPMB) Key Programming operation ***
+ ==============================
+ [..]
+ (+) You can program the authentication key of RPMB area in polling mode by using function
+ HAL_MMC_RPMB_ProgramAuthenticationKey().
+ This function is only used once during the life of an MMC card.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetRPMBError() function for operation state.
+ (+) You can program the authentication key of RPMB area in Interrupt mode by using function
+ HAL_MMC_RPMB_ProgramAuthenticationKey_IT().
+ This function is only used once during the life of an MMC card.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetRPMBError() function for operation state.
+
+ *** MMC Card Reply Protected Memory Block (RPMB) write counter operation ***
+ ==============================
+ [..]
+ (+) You can get the write counter value of RPMB area in polling mode by using function
+ HAL_MMC_RPMB_GetWriteCounter().
+ (+) You can get the write counter value of RPMB area in Interrupt mode by using function
+ HAL_MMC_RPMB_GetWriteCounter_IT().
+
+ *** MMC Card Reply Protected Memory Block (RPMB) write operation ***
+ ==============================
+ [..]
+ (+) You can write to the RPMB area of MMC card in polling mode by using function
+ HAL_MMC_WriteBlocks().
+ This function supports the one, two, or thirty two blocks write operation
+ (with 512-bytes block length).
+ You can choose the number of blocks at the multiple block read operation by adjusting
+ the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetRPMBError() function for operation state.
+ (+) You can write to the RPMB area of MMC card in Interrupt mode by using function
+ HAL_MMC_WriteBlocks_IT().
+ This function supports the one, two, or thirty two blocks write operation
+ (with 512-bytes block length).
+ You can choose the number of blocks at the multiple block read operation by adjusting
+ the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetRPMBError() function for operation state.
+
+ *** MMC Card Reply Protected Memory Block (RPMB) read operation ***
+ ==============================
+ [..]
+ (+) You can read from the RPMB area of MMC card in polling mode by using function
+ HAL_MMC_RPMB_ReadBlocks().
+ The block size should be chosen as multiple of 512 bytes.
+ You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetRPMBError() function for MMC card state.
+ (+) You can read from the RPMB area of MMC card in Interrupt mode by using function
+ HAL_MMC_RPMB_ReadBlocks_IT().
+ The block size should be chosen as multiple of 512 bytes.
+ You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetRPMBError() function for MMC card state.
+
*** MMC HAL driver macros list ***
==================================
[..]
@@ -204,7 +262,7 @@
and a pointer to the user callback function.
Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
(+) ErrorCallback : callback when error occurs.
@@ -218,9 +276,9 @@
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_MMC_Init
+ reset to the legacy weak (overridden) functions in the HAL_MMC_Init
and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -235,7 +293,7 @@
When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -253,6 +311,7 @@
* @{
*/
+#if defined (SDMMC1) || defined (SDMMC2)
#ifdef HAL_MMC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
@@ -290,6 +349,12 @@
/* Frequencies used in the driver for clock divider calculation */
#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */
#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */
+
+/* The Data elements' postitions in the frame Frame for RPMB area */
+#define MMC_RPMB_KEYMAC_POSITION 196U
+#define MMC_RPMB_DATA_POSITION 228U
+#define MMC_RPMB_NONCE_POSITION 484U
+#define MMC_RPMB_WRITE_COUNTER_POSITION 500U
/**
* @}
*/
@@ -435,7 +500,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
/* Init Clock should be less or equal to 400Khz*/
- sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
if (sdmmc_clk == 0U)
{
hmmc->State = HAL_MMC_STATE_READY;
@@ -456,8 +521,15 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
/* wait 74 Cycles: required power up waiting time before starting
the MMC initialization sequence */
- sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
- HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+ if (Init.ClockDiv != 0U)
+ {
+ sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+ }
+
+ if (sdmmc_clk != 0U)
+ {
+ HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+ }
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
@@ -531,7 +603,6 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
return HAL_OK;
}
-
/**
* @brief Initializes the MMC MSP.
* @param hmmc: Pointer to MMC handle
@@ -594,7 +665,8 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
- uint32_t NumberOfBlocks, uint32_t Timeout)
+ uint32_t NumberOfBlocks,
+ uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -647,7 +719,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- add *= 512U;
+ add *= MMC_BLOCKSIZE;
}
/* Configure the MMC DPSM (Data Path State Machine) */
@@ -689,10 +761,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
while (!__HAL_MMC_GET_FLAG(hmmc,
SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
{
/* Read data from SDMMC Rx FIFO */
- for (count = 0U; count < 8U; count++)
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
{
data = SDMMC_ReadFIFO(hmmc->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
@@ -704,7 +776,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
*tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
tempbuff++;
}
- dataremaining -= 32U;
+ dataremaining -= SDMMC_FIFO_SIZE;
}
if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
@@ -789,7 +861,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
@@ -799,7 +871,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
uint32_t data;
uint32_t dataremaining;
uint32_t add = BlockAdd;
- uint8_t *tempbuff = pData;
+ const uint8_t *tempbuff = pData;
if (NULL == pData)
{
@@ -842,7 +914,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- add *= 512U;
+ add *= MMC_BLOCKSIZE;
}
/* Configure the MMC DPSM (Data Path State Machine) */
@@ -884,10 +956,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
while (!__HAL_MMC_GET_FLAG(hmmc,
SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
{
/* Write data to SDMMC Tx FIFO */
- for (count = 0U; count < 8U; count++)
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
{
data = (uint32_t)(*tempbuff);
tempbuff++;
@@ -899,7 +971,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
tempbuff++;
(void)SDMMC_WriteFIFO(hmmc->Instance, &data);
}
- dataremaining -= 32U;
+ dataremaining -= SDMMC_FIFO_SIZE;
}
if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
@@ -985,8 +1057,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
- uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -1036,7 +1108,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- add *= 512U;
+ add *= MMC_BLOCKSIZE;
}
/* Configure the MMC DPSM (Data Path State Machine) */
@@ -1098,7 +1170,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
@@ -1149,7 +1221,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- add *= 512U;
+ add *= MMC_BLOCKSIZE;
}
/* Configure the MMC DPSM (Data Path State Machine) */
@@ -1212,8 +1284,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
- uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -1263,7 +1335,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- add *= 512U;
+ add *= MMC_BLOCKSIZE;
}
/* Configure the MMC DPSM (Data Path State Machine) */
@@ -1327,7 +1399,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
@@ -1378,7 +1450,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- add *= 512U;
+ add *= MMC_BLOCKSIZE;
}
/* Configure the MMC DPSM (Data Path State Machine) */
@@ -1496,8 +1568,8 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd,
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- start_add *= 512U;
- end_add *= 512U;
+ start_add *= MMC_BLOCKSIZE;
+ end_add *= MMC_BLOCKSIZE;
}
/* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
@@ -1785,7 +1857,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
* @param hmmc: Pointer to mmc handle
* @retval HAL state
*/
-HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
+HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc)
{
return hmmc->State;
}
@@ -1796,7 +1868,7 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
* the configuration information.
* @retval MMC Error Code
*/
-uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
+uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc)
{
return hmmc->ErrorCode;
}
@@ -1864,7 +1936,10 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User MMC Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (overridden) predefined callback
+ * @note The HAL_MMC_RegisterCallback() may be called before HAL_MMC_Init() in
+ * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID
+ * and HAL_MMC_MSP_DEINIT_CB_ID.
* @param hmmc : MMC handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1893,9 +1968,6 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hmmc);
-
if (hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
@@ -1964,14 +2036,15 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hmmc);
return status;
}
/**
* @brief Unregister a User MMC Callback
- * MMC Callback is redirected to the weak (surcharged) predefined callback
+ * MMC Callback is redirected to the weak (overridden) predefined callback
+ * @note The HAL_MMC_UnRegisterCallback() may be called before HAL_MMC_Init() in
+ * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID
+ * and HAL_MMC_MSP_DEINIT_CB_ID.
* @param hmmc : MMC handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1991,9 +2064,6 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hmmc);
-
if (hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
@@ -2062,8 +2132,6 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hmmc);
return status;
}
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
@@ -2181,14 +2249,14 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp
hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
- hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
- hmmc->MmcCard.LogBlockSize = 512U;
+ hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / MMC_BLOCKSIZE);
+ hmmc->MmcCard.LogBlockSize = MMC_BLOCKSIZE;
}
else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
{
hmmc->MmcCard.BlockNbr = block_nbr;
hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
- hmmc->MmcCard.BlockSize = 512U;
+ hmmc->MmcCard.BlockSize = MMC_BLOCKSIZE;
hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize;
}
else
@@ -2296,7 +2364,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 512U;
+ config.DataLength = MMC_BLOCKSIZE;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
@@ -2322,7 +2390,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
{
/* Read data from SDMMC Rx FIFO */
- for (count = 0U; count < 8U; count++)
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
{
*tmp_buf = SDMMC_ReadFIFO(hmmc->Instance);
tmp_buf++;
@@ -2692,35 +2760,93 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
{
- HAL_MMC_CardStateTypeDef CardState;
+ uint32_t error_code;
+ uint32_t tickstart;
- /* DIsable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
- SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+ if (hmmc->State == HAL_MMC_STATE_BUSY)
+ {
+ /* DIsable All interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
- /* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+ /*we will send the CMD12 in all cases in order to stop the data transfers*/
+ /*In case the data transfer just finished, the external memory will not respond
+ and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/
+ /*In case the data transfer aborted , the external memory will respond and will return HAL_MMC_ERROR_NONE*/
+ /*Other scenario will return HAL_ERROR*/
- /* If IDMA Context, disable Internal DMA */
- hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+ hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
+ error_code = hmmc->ErrorCode;
+ if ((error_code != HAL_MMC_ERROR_NONE) && (error_code != HAL_MMC_ERROR_CMD_RSP_TIMEOUT))
+ {
+ return HAL_ERROR;
+ }
- hmmc->State = HAL_MMC_STATE_READY;
+ tickstart = HAL_GetTick();
+ if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD)
+ {
+ if (hmmc->ErrorCode == HAL_MMC_ERROR_NONE)
+ {
+ while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
- /* Initialize the MMC operation */
- hmmc->Context = MMC_CONTEXT_NONE;
+ if (hmmc->ErrorCode == HAL_MMC_ERROR_CMD_RSP_TIMEOUT)
+ {
+ while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)
+ {
+ while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do*/
+ }
- CardState = HAL_MMC_GetCardState(hmmc);
- if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
- {
- hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
- }
- if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
- {
- return HAL_ERROR;
+ /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear
+ the appropriate flags that will be set depending of the abort/non abort of the memory */
+ /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result
+ in next SDMMC read/write operation to fail */
+
+ /*SDMMC ready for clear data flags*/
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+ /* If IDMA Context, disable Internal DMA */
+ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Initialize the MMC operation */
+ hmmc->Context = MMC_CONTEXT_NONE;
}
return HAL_OK;
}
-
/**
* @brief Abort the current transfer and disable the MMC (IT mode).
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
@@ -2843,8 +2969,8 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT
/* In case of low capacity card, the address is not block number but bytes */
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- start_add *= 512U;
- end_add *= 512U;
+ start_add *= MMC_BLOCKSIZE;
+ end_add *= MMC_BLOCKSIZE;
}
/* Send CMD35 MMC_ERASE_GRP_START with start address as argument */
@@ -3503,7 +3629,6 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc)
* @{
*/
-
/**
* @brief Initializes the mmc card.
* @param hmmc: Pointer to MMC handle
@@ -3587,7 +3712,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
hmmc->ErrorCode |= errorstate;
}
-
/* Get Extended CSD parameters */
if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK)
{
@@ -3730,7 +3854,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 512U;
+ config.DataLength = MMC_BLOCKSIZE;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
@@ -3755,7 +3879,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
{
/* Read data from SDMMC Rx FIFO */
- for (count = 0U; count < 8U; count++)
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
{
tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
/* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
@@ -3837,10 +3961,10 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
tmp = hmmc->pRxBuffPtr;
- if (hmmc->RxXferSize >= 32U)
+ if (hmmc->RxXferSize >= SDMMC_FIFO_SIZE)
{
/* Read data from SDMMC Rx FIFO */
- for (count = 0U; count < 8U; count++)
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
{
data = SDMMC_ReadFIFO(hmmc->Instance);
*tmp = (uint8_t)(data & 0xFFU);
@@ -3854,7 +3978,7 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
}
hmmc->pRxBuffPtr = tmp;
- hmmc->RxXferSize -= 32U;
+ hmmc->RxXferSize -= SDMMC_FIFO_SIZE;
}
}
@@ -3868,14 +3992,14 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
{
uint32_t count;
uint32_t data;
- uint8_t *tmp;
+ const uint8_t *tmp;
tmp = hmmc->pTxBuffPtr;
- if (hmmc->TxXferSize >= 32U)
+ if (hmmc->TxXferSize >= SDMMC_FIFO_SIZE)
{
/* Write data to SDMMC Tx FIFO */
- for (count = 0U; count < 8U; count++)
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
{
data = (uint32_t)(*tmp);
tmp++;
@@ -3889,7 +4013,7 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
}
hmmc->pTxBuffPtr = tmp;
- hmmc->TxXferSize -= 32U;
+ hmmc->TxXferSize -= SDMMC_FIFO_SIZE;
}
}
@@ -4217,6 +4341,1554 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3
return errorstate;
}
+/**
+ * @brief Used to select the partition.
+ * @param hmmc: Pointer to MMC handle
+ * @param Partition: Partition type
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition)
+{
+ uint32_t errorstate;
+ uint32_t response = 0U;
+ uint32_t count;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t arg = Partition | 0x03B30000U;
+
+ /* Check the state of the driver */
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Index : 179 - Value : partition */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, arg);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Wait that the device is ready by checking the D0 line */
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
+ {
+ errorstate = HAL_MMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Manage errors */
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Allows to program the authentication key within the RPMB partition
+ * @param hmmc: Pointer to MMC handle
+ * @param pKey: pointer to the authentication key (32 bytes)
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t byte_count = 0;
+ uint32_t data;
+ uint32_t dataremaining;
+ uint8_t tail_pack[12] = {0};
+ uint8_t zero_pack[4] = {0};
+ const uint8_t *rtempbuff;
+ uint8_t *tempbuff;
+
+ tail_pack[11] = 0x01;
+
+ if (NULL == pKey)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x80000001U);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+ {
+ hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0);
+ }
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write block(s) in polling mode */
+ rtempbuff = zero_pack;
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+ {
+ /* Write data to SDMMC Tx FIFO */
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+ {
+ data = (uint32_t)(*rtempbuff);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 8U);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 16U);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 24U);
+ rtempbuff++;
+ byte_count++;
+ (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+ if (byte_count < MMC_RPMB_KEYMAC_POSITION)
+ {
+ rtempbuff = zero_pack;
+ }
+ else if (byte_count == MMC_RPMB_KEYMAC_POSITION)
+ {
+ rtempbuff = pKey;
+ }
+ else if ((byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) && \
+ (byte_count >= MMC_RPMB_DATA_POSITION))
+ {
+ rtempbuff = zero_pack;
+ }
+ else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ rtempbuff = tail_pack;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ }
+ dataremaining -= SDMMC_FIFO_SIZE;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Read Response Packet */
+ errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+ hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0);
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+ /* Poll on SDMMC flags */
+ tempbuff = zero_pack;
+ byte_count = 0;
+
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+ {
+ data = SDMMC_ReadFIFO(hmmc->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ tempbuff = zero_pack;
+ }
+ else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ tempbuff = tail_pack;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ dataremaining -= SDMMC_FIFO_SIZE;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Check result of operation */
+ if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x01U))
+ {
+ hmmc->RPMBErrorCode |= tail_pack[9];
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Allows to get the value of write counter within the RPMB partition.
+ * @param hmmc: Pointer to MMC handle
+ * @param Nonce: pointer to the value of nonce (16 bytes)
+ * @param Timeout: Specify timeout value
+ * @retval write counter value.
+ */
+uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t byte_count = 0;
+ uint32_t data;
+ uint32_t dataremaining;
+ uint8_t tail_pack[12] = {0};
+ uint8_t zero_pack[4] = {0};
+ uint8_t echo_nonce[16] = {0};
+ uint8_t *tempbuff = zero_pack;
+
+ tail_pack[11] = 0x02;
+
+ if (NULL == pNonce)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+
+ /* Send Request Packet */
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+ hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0);
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+
+ /* Write block(s) in polling mode */
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+ {
+
+ /* Write data to SDMMC Tx FIFO */
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+ {
+ data = (uint32_t)(*tempbuff);
+ tempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*tempbuff) << 8U);
+ tempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*tempbuff) << 16U);
+ tempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*tempbuff) << 24U);
+ tempbuff++;
+ byte_count++;
+ (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+ if (byte_count < MMC_RPMB_NONCE_POSITION)
+ {
+ tempbuff = zero_pack;
+ }
+ else if (byte_count == MMC_RPMB_NONCE_POSITION)
+ {
+ tempbuff = (uint8_t *)pNonce;
+ }
+ else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ tempbuff = tail_pack;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ }
+ dataremaining -= SDMMC_FIFO_SIZE;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Read Response Packt */
+ errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+ hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0);
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+ /* Poll on SDMMC flags */
+ tempbuff = zero_pack;
+
+ byte_count = 0;
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+ {
+ data = SDMMC_ReadFIFO(hmmc->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ if (byte_count < MMC_RPMB_NONCE_POSITION)
+ {
+ tempbuff = zero_pack;
+ }
+ else if (byte_count == MMC_RPMB_NONCE_POSITION)
+ {
+ tempbuff = echo_nonce;
+ }
+ else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ tempbuff = tail_pack;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ dataremaining -= SDMMC_FIFO_SIZE;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ for (uint8_t i = 0; i < 16U; i++)
+ {
+ if (pNonce[i] != echo_nonce[i])
+ {
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+ }
+
+ return ((uint32_t)tail_pack[3] | ((uint32_t)tail_pack[2] << 8) | ((uint32_t)tail_pack[1] << 16) | \
+ ((uint32_t)tail_pack[0] << 24));
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+ return 0;
+ }
+}
+
+/**
+ * @brief Allows to write block(s) to a specified address in the RPMB partition. The Data
+ * transfer is managed by polling mode.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
+ * @param pMAC: Pointer to the authentication MAC buffer
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd,
+ uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout)
+{
+
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t byte_count = 0;
+ uint32_t data;
+ uint32_t dataremaining;
+ uint8_t tail_pack[12] = {0};
+ uint8_t zero_pack[4] = {0};
+ uint8_t echo_nonce[16] = {0};
+ const uint8_t local_nonce[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x00, 0x01, 0x02,
+ 0x03, 0x04, 0x00, 0x01, 0x02, 0x03, 0x04, 0x08
+ };
+ const uint8_t *rtempbuff;
+ uint8_t *tempbuff;
+ uint32_t arg = 0x80000000U;
+ uint32_t offset = 0;
+
+ if ((NumberOfBlocks != 0x1U) && (NumberOfBlocks != 0x2U) && (NumberOfBlocks != 0x20U))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if ((NULL == pData) || (NULL == pMAC))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ tail_pack[11] = 0x02;
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send Request Packet */
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+ hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0);
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write block(s) in polling mode */
+ rtempbuff = zero_pack;
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+ {
+
+ /* Write data to SDMMC Tx FIFO */
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+ {
+ data = (uint32_t)(*rtempbuff);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 8U);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 16U);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 24U);
+ rtempbuff++;
+ byte_count++;
+ (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+ if (byte_count < MMC_RPMB_NONCE_POSITION)
+ {
+ rtempbuff = zero_pack;
+ }
+ else if (byte_count == MMC_RPMB_NONCE_POSITION)
+ {
+ rtempbuff = local_nonce;
+ }
+ else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ rtempbuff = tail_pack;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ dataremaining -= SDMMC_FIFO_SIZE;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Read Response Packt */
+ errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+ hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0);
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+ /* Poll on SDMMC flags */
+ tempbuff = zero_pack;
+
+ byte_count = 0;
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+ {
+ data = SDMMC_ReadFIFO(hmmc->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ if (byte_count < MMC_RPMB_NONCE_POSITION)
+ {
+ tempbuff = zero_pack;
+ }
+ else if (byte_count == MMC_RPMB_NONCE_POSITION)
+ {
+ tempbuff = echo_nonce;
+ }
+ else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ tempbuff = tail_pack;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ dataremaining -= SDMMC_FIFO_SIZE;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ for (uint8_t i = 0; i < 16U; i++)
+ {
+ if (local_nonce[i] != echo_nonce[i])
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+ tail_pack[11] = 0x03;
+ tail_pack[10] = 0x00;
+ tail_pack[7] = (uint8_t)(NumberOfBlocks) & 0xFFU;
+ tail_pack[6] = (uint8_t)(NumberOfBlocks >> 8) & 0xFFU;
+ tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU;
+ tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU;
+
+ rtempbuff = zero_pack;
+ byte_count = 0;
+ arg |= NumberOfBlocks;
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send Request Packet */
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+
+ {
+ hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0);
+ }
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+
+ /* Write block(s) in polling mode */
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+ {
+
+ /* Write data to SDMMC Tx FIFO */
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+ {
+ data = (uint32_t)(*rtempbuff);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 8U);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 16U);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 24U);
+ rtempbuff++;
+ byte_count++;
+ (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+ if (byte_count == MMC_RPMB_KEYMAC_POSITION)
+ {
+ rtempbuff = pMAC;
+ }
+ if (byte_count == MMC_RPMB_DATA_POSITION)
+ {
+ rtempbuff = &pData[offset];
+ }
+ if ((byte_count >= MMC_RPMB_NONCE_POSITION) && \
+ (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION))
+ {
+ rtempbuff = zero_pack;
+ }
+ if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ rtempbuff = tail_pack;
+ }
+ else if (byte_count == MMC_BLOCKSIZE)
+ {
+ offset += (uint32_t)256U;
+ byte_count = 0;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ dataremaining -= SDMMC_FIFO_SIZE;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Response Packet */
+
+ errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+
+ {
+ hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0);
+ }
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+ /* Poll on SDMMC flags */
+ tempbuff = zero_pack;
+ byte_count = 0;
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+ {
+ data = SDMMC_ReadFIFO(hmmc->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ tempbuff = zero_pack;
+ }
+ else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ tempbuff = tail_pack;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ dataremaining -= SDMMC_FIFO_SIZE;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Check result of operation */
+ if (((tail_pack[9] & (uint8_t)0xFEU) != 0x00U) || (tail_pack[10] != 0x03U))
+ {
+ hmmc->RPMBErrorCode |= tail_pack[9];
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Allows to read block(s) to a specified address in the RPMB partition. The Data
+ * transfer is managed by polling mode.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
+ * @param pNonce: Pointer to the buffer that will contain the nonce to transmit
+ * @param pMAC: Pointer to the authentication MAC buffer
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd,
+ uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC,
+ uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t byte_count = 0;
+ uint32_t data;
+ uint8_t tail_pack[12] = {0};
+ uint8_t zero_pack[4] = {0};
+ uint8_t echo_nonce[16] = {0};
+ uint32_t dataremaining;
+ const uint8_t *rtempbuff;
+ uint8_t *tempbuff;
+ uint32_t arg = 0;
+ uint32_t offset = 0;
+
+ arg |= NumberOfBlocks;
+
+ tail_pack[11] = 0x04;
+ tail_pack[10] = 0x00;
+ tail_pack[7] = 0x00;
+ tail_pack[6] = 0x00;
+ tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU;
+ tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU;
+ tail_pack[3] = 0x00;
+ tail_pack[2] = 0x00;
+ tail_pack[1] = 0x00;
+ tail_pack[0] = 0x00;
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 1);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send Request Packet */
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+ hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0);
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write block(s) in polling mode */
+ rtempbuff = zero_pack;
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+ {
+
+ /* Write data to SDMMC Tx FIFO */
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+ {
+ data = (uint32_t)(*rtempbuff);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 8U);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 16U);
+ rtempbuff++;
+ byte_count++;
+ data |= ((uint32_t)(*rtempbuff) << 24U);
+ rtempbuff++;
+ byte_count++;
+ (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+ if (byte_count < MMC_RPMB_NONCE_POSITION)
+ {
+ rtempbuff = zero_pack;
+ }
+ else if (byte_count == MMC_RPMB_NONCE_POSITION)
+ {
+ rtempbuff = pNonce;
+ }
+ else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ rtempbuff = tail_pack;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ dataremaining -= SDMMC_FIFO_SIZE;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Read Response Packet */
+ errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Write Blocks in Polling mode */
+ hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0);
+
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+ /* Poll on SDMMC flags */
+ tempbuff = zero_pack;
+ byte_count = 0;
+
+ dataremaining = config.DataLength;
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+ {
+ data = SDMMC_ReadFIFO(hmmc->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ byte_count++;
+ if (byte_count < MMC_RPMB_KEYMAC_POSITION)
+ {
+ tempbuff = zero_pack;
+ }
+ else if (byte_count == MMC_RPMB_KEYMAC_POSITION)
+ {
+ tempbuff = (uint8_t *)pMAC;
+ }
+ else if (byte_count == MMC_RPMB_DATA_POSITION)
+ {
+ tempbuff = &pData[offset];
+ }
+ else if (byte_count == MMC_RPMB_NONCE_POSITION)
+ {
+ tempbuff = echo_nonce;
+ }
+ else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+ {
+ tempbuff = tail_pack;
+ }
+ else if (byte_count == MMC_BLOCKSIZE)
+ {
+ byte_count = 0;
+ offset += (uint32_t)256U;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ dataremaining -= SDMMC_FIFO_SIZE;
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ for (uint8_t i = 0; i < 16U; i++)
+ {
+ if (pNonce[i] != echo_nonce[i])
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check result of operation */
+ if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x04U))
+ {
+ hmmc->RPMBErrorCode |= tail_pack[9];
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+
/**
* @brief Read DMA Buffer 0 Transfer completed callbacks
* @param hmmc: MMC handle
@@ -4282,6 +5954,7 @@ __weak void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc)
*/
#endif /* HAL_MMC_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc_ex.c
index 5cce62bbcf..8c0ccd5fbf 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc_ex.c
@@ -45,6 +45,7 @@
* @{
*/
+#if defined (SDMMC1) || defined (SDMMC2)
#ifdef HAL_MMC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
@@ -343,6 +344,7 @@ HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_D
*/
#endif /* HAL_MMC_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nand.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nand.c
index 846ae918c0..954a068f40 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nand.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nand.c
@@ -77,15 +77,15 @@
and a pointer to the user callback function.
Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_NAND_Init
+ reset to the legacy weak (overridden) functions in the HAL_NAND_Init
and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -100,7 +100,7 @@
When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -514,8 +514,8 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -672,8 +672,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -840,8 +840,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
@@ -849,7 +849,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
- uint8_t *buff = pBuffer;
+ const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -993,8 +993,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1002,7 +1002,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
- uint16_t *buff = pBuffer;
+ const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1157,8 +1157,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumSpareAreaToRead)
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -1322,7 +1322,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
@@ -1487,8 +1487,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1497,7 +1497,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
- uint8_t *buff = pBuffer;
+ const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1650,8 +1650,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1660,7 +1660,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
- uint16_t *buff = pBuffer;
+ const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1811,7 +1811,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
* @param pAddress pointer to NAND address structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress)
{
uint32_t deviceaddress;
@@ -1867,7 +1867,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t status = NAND_VALID_ADDRESS;
@@ -1898,7 +1898,7 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NAND Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1918,9 +1918,6 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hnand);
-
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
@@ -1962,14 +1959,12 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnand);
return status;
}
/**
* @brief Unregister a User NAND Callback
- * NAND Callback is redirected to the weak (surcharged) predefined callback
+ * NAND Callback is redirected to the weak predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1982,9 +1977,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hnand);
-
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
@@ -2026,8 +2018,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnand);
return status;
}
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
@@ -2178,7 +2168,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
* the configuration information for NAND module.
* @retval HAL state
*/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand)
{
return hnand->State;
}
@@ -2189,7 +2179,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
* the configuration information for NAND module.
* @retval NAND status
*/
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand)
{
uint32_t data;
uint32_t deviceaddress;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nor.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nor.c
index fcd54b84f0..f7a864ba8a 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nor.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nor.c
@@ -74,15 +74,15 @@
and a pointer to the user callback function.
Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_NOR_Init
+ reset to the legacy weak (overridden) functions in the HAL_NOR_Init
and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -97,7 +97,7 @@
When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -126,6 +126,11 @@
*/
/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA
+#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA
+#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA
+
#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
@@ -263,7 +268,8 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
(void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
/* Initialize NOR extended mode timing Interface */
- (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+ (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming,
+ hnor->Init.NSBank, hnor->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
@@ -309,7 +315,16 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
else
{
/* Get the value of the command set */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
+ NOR_CMD_DATA_CFI);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+ }
+
hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
status = HAL_NOR_ReturnToReadMode(hnor);
@@ -471,9 +486,22 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
/* Send read ID command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_AUTO_SELECT);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_AUTO_SELECT);
+ }
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -640,9 +668,22 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_READ_RESET);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_READ_RESET);
+ }
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -721,9 +762,21 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
/* Send program data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_PROGRAM);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ }
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -813,9 +866,22 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_READ_RESET);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_READ_RESET);
+ }
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -908,10 +974,20 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- /* Issue unlock command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ }
+ else
+ {
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ }
/* Write Buffer Load Command */
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
@@ -1011,14 +1087,26 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
/* Send block erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ }
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
@@ -1096,15 +1184,28 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
/* Send NOR chip erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH),
+ NOR_CMD_DATA_CHIP_ERASE);
+ }
}
else
{
@@ -1175,8 +1276,15 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
}
/* Send read CFI query command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
-
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
+ NOR_CMD_DATA_CFI);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+ }
/* read the NOR CFI information */
pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
@@ -1200,7 +1308,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NOR Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1220,9 +1328,6 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hnor);
-
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
@@ -1246,14 +1351,12 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnor);
return status;
}
/**
* @brief Unregister a User NOR Callback
- * NOR Callback is redirected to the weak (surcharged) predefined callback
+ * NOR Callback is redirected to the weak predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1266,9 +1369,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
- /* Process locked */
- __HAL_LOCK(hnor);
-
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
@@ -1292,8 +1392,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnor);
return status;
}
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
@@ -1410,7 +1508,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
* the configuration information for NOR module.
* @retval NOR controller state
*/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor)
{
return hnor->State;
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_opamp.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_opamp.c
index ffd3a8040f..b49b182ec5 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_opamp.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_opamp.c
@@ -129,7 +129,7 @@
and a pointer to the user callback function.
(++) Use function HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+++) MspInitCallback : OPAMP MspInit.
(+++) MspDeInitCallback : OPAMP MspdeInit.
(+++) All Callbacks
@@ -1017,7 +1017,7 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User OPAMP Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (overridden) predefined callback
* @param hopamp : OPAMP handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1083,7 +1083,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_O
/**
* @brief Unregister a User OPAMP Callback
- * OPAMP Callback is redirected to the weak (surcharged) predefined callback
+ * OPAMP Callback is redirected to the weak (overridden) predefined callback
* @param hopamp : OPAMP handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_ospi.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_ospi.c
index 223567aa27..05f88360ef 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_ospi.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_ospi.c
@@ -52,7 +52,7 @@
and the CS boundary using the HAL_OSPI_Init() function.
[..]
When using Hyperbus, configure the RW recovery time, the access time,
- the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
+ the write latency and the latency mode using the HAL_OSPI_HyperbusCfg()
function.
*** Indirect functional mode ***
@@ -185,7 +185,7 @@
[..]
Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) FifoThresholdCallback : callback when the fifo threshold is reached.
@@ -203,9 +203,9 @@
[..]
By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_OSPI_Init()
+ reset to the legacy weak (overridden) functions in the HAL_OSPI_Init()
and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -222,7 +222,7 @@
[..]
When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -267,13 +267,13 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static void OSPI_DMACplt (DMA_HandleTypeDef *hdma);
-static void OSPI_DMAHalfCplt (DMA_HandleTypeDef *hdma);
-static void OSPI_DMAError (DMA_HandleTypeDef *hdma);
-static void OSPI_DMAAbortCplt (DMA_HandleTypeDef *hdma);
+static void OSPI_DMACplt(DMA_HandleTypeDef *hdma);
+static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma);
+static void OSPI_DMAError(DMA_HandleTypeDef *hdma);
+static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
uint32_t Tickstart, uint32_t Timeout);
-static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
+static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
/**
@endcond
*/
@@ -306,7 +306,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hosp
* @param hospi : OSPI handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
+HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart = HAL_GetTick();
@@ -320,19 +320,19 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
else
{
/* Check the parameters of the initialization structure */
- assert_param(IS_OSPI_FIFO_THRESHOLD (hospi->Init.FifoThreshold));
- assert_param(IS_OSPI_DUALQUAD_MODE (hospi->Init.DualQuad));
- assert_param(IS_OSPI_MEMORY_TYPE (hospi->Init.MemoryType));
- assert_param(IS_OSPI_DEVICE_SIZE (hospi->Init.DeviceSize));
- assert_param(IS_OSPI_CS_HIGH_TIME (hospi->Init.ChipSelectHighTime));
- assert_param(IS_OSPI_FREE_RUN_CLK (hospi->Init.FreeRunningClock));
- assert_param(IS_OSPI_CLOCK_MODE (hospi->Init.ClockMode));
- assert_param(IS_OSPI_WRAP_SIZE (hospi->Init.WrapSize));
- assert_param(IS_OSPI_CLK_PRESCALER (hospi->Init.ClockPrescaler));
+ assert_param(IS_OSPI_FIFO_THRESHOLD(hospi->Init.FifoThreshold));
+ assert_param(IS_OSPI_DUALQUAD_MODE(hospi->Init.DualQuad));
+ assert_param(IS_OSPI_MEMORY_TYPE(hospi->Init.MemoryType));
+ assert_param(IS_OSPI_DEVICE_SIZE(hospi->Init.DeviceSize));
+ assert_param(IS_OSPI_CS_HIGH_TIME(hospi->Init.ChipSelectHighTime));
+ assert_param(IS_OSPI_FREE_RUN_CLK(hospi->Init.FreeRunningClock));
+ assert_param(IS_OSPI_CLOCK_MODE(hospi->Init.ClockMode));
+ assert_param(IS_OSPI_WRAP_SIZE(hospi->Init.WrapSize));
+ assert_param(IS_OSPI_CLK_PRESCALER(hospi->Init.ClockPrescaler));
assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting));
- assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle));
- assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary));
- assert_param(IS_OSPI_DLYBYP (hospi->Init.DelayBlockBypass));
+ assert_param(IS_OSPI_DHQC(hospi->Init.DelayHoldQuarterCycle));
+ assert_param(IS_OSPI_CS_BOUNDARY(hospi->Init.ChipSelectBoundary));
+ assert_param(IS_OSPI_DLYBYP(hospi->Init.DelayBlockBypass));
/* Initialize error code */
hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
@@ -353,7 +353,7 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
- if(hospi->MspInitCallback == NULL)
+ if (hospi->MspInitCallback == NULL)
{
hospi->MspInitCallback = HAL_OSPI_MspInit;
}
@@ -396,14 +396,14 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
{
/* Configure clock prescaler */
MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER,
- ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
+ ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
/* Configure Dual Quad mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
/* Configure sample shifting and delay hold quarter cycle */
MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC),
- (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
+ (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
/* Enable OctoSPI */
__HAL_OSPI_ENABLE(hospi);
@@ -463,27 +463,27 @@ HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi)
}
else
{
- /* Disable OctoSPI */
- __HAL_OSPI_DISABLE(hospi);
+ /* Disable OctoSPI */
+ __HAL_OSPI_DISABLE(hospi);
- /* Disable free running clock if needed : must be done after OSPI disable */
- CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+ /* Disable free running clock if needed : must be done after OSPI disable */
+ CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
- if(hospi->MspDeInitCallback == NULL)
- {
- hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
- }
+ if (hospi->MspDeInitCallback == NULL)
+ {
+ hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+ }
- /* DeInit the low level hardware */
- hospi->MspDeInitCallback(hospi);
+ /* DeInit the low level hardware */
+ hospi->MspDeInitCallback(hospi);
#else
- /* De-initialize the low-level hardware */
- HAL_OSPI_MspDeInit(hospi);
+ /* De-initialize the low-level hardware */
+ HAL_OSPI_MspDeInit(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
- /* Reset the driver state */
- hospi->State = HAL_OSPI_STATE_RESET;
+ /* Reset the driver state */
+ hospi->State = HAL_OSPI_STATE_RESET;
}
return status;
@@ -589,7 +589,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi)
hospi->pBuffPtr++;
hospi->XferCount--;
}
- else if(hospi->XferCount == 0U)
+ else if (hospi->XferCount == 0U)
{
/* Clear flag */
hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
@@ -782,21 +782,21 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp
assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
{
- assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize));
+ assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize));
assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
}
assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
{
- assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
+ assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
}
assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
{
- assert_param(IS_OSPI_ALT_BYTES_SIZE (cmd->AlternateBytesSize));
+ assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize));
assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
}
@@ -805,20 +805,20 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp
{
if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
{
- assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData));
+ assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
}
assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
- assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles));
+ assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles));
}
- assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
+ assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
/* Check the state of the driver */
state = hospi->State;
if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) ||
((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
- || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
+ || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) ||
(cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))))
{
@@ -913,33 +913,33 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd
assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
{
- assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize));
+ assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize));
assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
}
assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
{
- assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
+ assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
}
assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
{
- assert_param(IS_OSPI_ALT_BYTES_SIZE (cmd->AlternateBytesSize));
+ assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize));
assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
}
assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
if (cmd->DataMode != HAL_OSPI_DATA_NONE)
{
- assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData));
+ assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
- assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles));
+ assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles));
}
- assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
+ assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
/* Check the state of the driver */
@@ -963,7 +963,7 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd
if (status == HAL_OK)
{
/* Update the state */
- hospi->State = HAL_OSPI_STATE_BUSY_CMD;
+ hospi->State = HAL_OSPI_STATE_BUSY_CMD;
/* Enable the transfer complete and transfer error interrupts */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_TE);
@@ -994,10 +994,10 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC
uint32_t tickstart = HAL_GetTick();
/* Check the parameters of the hyperbus configuration structure */
- assert_param(IS_OSPI_RW_RECOVERY_TIME (cfg->RWRecoveryTime));
- assert_param(IS_OSPI_ACCESS_TIME (cfg->AccessTime));
+ assert_param(IS_OSPI_RW_RECOVERY_TIME(cfg->RWRecoveryTime));
+ assert_param(IS_OSPI_ACCESS_TIME(cfg->AccessTime));
assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency));
- assert_param(IS_OSPI_LATENCY_MODE (cfg->LatencyMode));
+ assert_param(IS_OSPI_LATENCY_MODE(cfg->LatencyMode));
/* Check the state of the driver */
state = hospi->State;
@@ -1041,9 +1041,9 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC
/* Check the parameters of the hyperbus command structure */
assert_param(IS_OSPI_ADDRESS_SPACE(cmd->AddressSpace));
- assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
- assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData));
- assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
+ assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
+ assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
+ assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
/* Check the state of the driver */
if ((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS))
@@ -1227,7 +1227,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui
*hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
hospi->pBuffPtr++;
hospi->XferCount--;
- } while(hospi->XferCount > 0U);
+ } while (hospi->XferCount > 0U);
if (status == HAL_OK)
{
@@ -1469,21 +1469,21 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat
hospi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction);
- /* Enable the transmit DMA Channel */
- if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize) == HAL_OK)
- {
- /* Enable the transfer error interrupt */
- __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+ /* Enable the transmit DMA Channel */
+ if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize) == HAL_OK)
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
- /* Enable the DMA transfer by setting the DMAEN bit */
- SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
- }
- else
- {
- status = HAL_ERROR;
- hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
- hospi->State = HAL_OSPI_STATE_READY;
- }
+ /* Enable the DMA transfer by setting the DMAEN bit */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
}
}
else
@@ -1593,38 +1593,38 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData
hospi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction);
- /* Enable the transmit DMA Channel */
- if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize) == HAL_OK)
- {
- /* Enable the transfer error interrupt */
- __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+ /* Enable the transmit DMA Channel */
+ if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize) == HAL_OK)
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
- /* Trig the transfer by re-writing address or instruction register */
- if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ /* Trig the transfer by re-writing address or instruction register */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
- if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
- {
- WRITE_REG(hospi->Instance->AR, addr_reg);
- }
- else
- {
- WRITE_REG(hospi->Instance->IR, ir_reg);
- }
+ WRITE_REG(hospi->Instance->IR, ir_reg);
}
-
- /* Enable the DMA transfer by setting the DMAEN bit */
- SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
- }
- else
- {
- status = HAL_ERROR;
- hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
- hospi->State = HAL_OSPI_STATE_READY;
}
+
+ /* Enable the DMA transfer by setting the DMAEN bit */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
}
}
else
@@ -1657,10 +1657,10 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli
#endif /* USE_FULL_ASSERT */
/* Check the parameters of the autopolling configuration structure */
- assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode));
- assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop));
- assert_param(IS_OSPI_INTERVAL (cfg->Interval));
- assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U));
+ assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode));
+ assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+ assert_param(IS_OSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
/* Check the state */
if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE))
@@ -1671,10 +1671,10 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli
if (status == HAL_OK)
{
/* Configure registers */
- WRITE_REG (hospi->Instance->PSMAR, cfg->Match);
- WRITE_REG (hospi->Instance->PSMKR, cfg->Mask);
- WRITE_REG (hospi->Instance->PIR, cfg->Interval);
- MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
+ WRITE_REG(hospi->Instance->PSMAR, cfg->Match);
+ WRITE_REG(hospi->Instance->PSMKR, cfg->Mask);
+ WRITE_REG(hospi->Instance->PIR, cfg->Interval);
+ MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
(cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
/* Trig the transfer by re-writing address or instruction register */
@@ -1735,10 +1735,10 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo
#endif /* USE_FULL_ASSERT */
/* Check the parameters of the autopolling configuration structure */
- assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode));
- assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop));
- assert_param(IS_OSPI_INTERVAL (cfg->Interval));
- assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U));
+ assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode));
+ assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+ assert_param(IS_OSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
@@ -1749,10 +1749,10 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo
if (status == HAL_OK)
{
/* Configure registers */
- WRITE_REG (hospi->Instance->PSMAR, cfg->Match);
- WRITE_REG (hospi->Instance->PSMKR, cfg->Mask);
- WRITE_REG (hospi->Instance->PIR, cfg->Interval);
- MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
+ WRITE_REG(hospi->Instance->PSMAR, cfg->Match);
+ WRITE_REG(hospi->Instance->PSMKR, cfg->Mask);
+ WRITE_REG(hospi->Instance->PIR, cfg->Interval);
+ MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
(cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
/* Clear flags related to interrupt */
@@ -1927,7 +1927,7 @@ __weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi)
* @param hospi : OSPI handle
* @retval None
*/
- __weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
+__weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
@@ -2000,7 +2000,7 @@ __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi)
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User OSPI Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hospi : OSPI handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -2024,77 +2024,77 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
- if(hospi->State == HAL_OSPI_STATE_READY)
+ if (hospi->State == HAL_OSPI_STATE_READY)
{
switch (CallbackID)
{
- case HAL_OSPI_ERROR_CB_ID :
- hospi->ErrorCallback = pCallback;
- break;
- case HAL_OSPI_ABORT_CB_ID :
- hospi->AbortCpltCallback = pCallback;
- break;
- case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
- hospi->FifoThresholdCallback = pCallback;
- break;
- case HAL_OSPI_CMD_CPLT_CB_ID :
- hospi->CmdCpltCallback = pCallback;
- break;
- case HAL_OSPI_RX_CPLT_CB_ID :
- hospi->RxCpltCallback = pCallback;
- break;
- case HAL_OSPI_TX_CPLT_CB_ID :
- hospi->TxCpltCallback = pCallback;
- break;
- case HAL_OSPI_RX_HALF_CPLT_CB_ID :
- hospi->RxHalfCpltCallback = pCallback;
- break;
- case HAL_OSPI_TX_HALF_CPLT_CB_ID :
- hospi->TxHalfCpltCallback = pCallback;
- break;
- case HAL_OSPI_STATUS_MATCH_CB_ID :
- hospi->StatusMatchCallback = pCallback;
- break;
- case HAL_OSPI_TIMEOUT_CB_ID :
- hospi->TimeOutCallback = pCallback;
- break;
- case HAL_OSPI_MSP_INIT_CB_ID :
- hospi->MspInitCallback = pCallback;
- break;
- case HAL_OSPI_MSP_DEINIT_CB_ID :
- hospi->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_OSPI_ERROR_CB_ID :
+ hospi->ErrorCallback = pCallback;
+ break;
+ case HAL_OSPI_ABORT_CB_ID :
+ hospi->AbortCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
+ hospi->FifoThresholdCallback = pCallback;
+ break;
+ case HAL_OSPI_CMD_CPLT_CB_ID :
+ hospi->CmdCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_RX_CPLT_CB_ID :
+ hospi->RxCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_TX_CPLT_CB_ID :
+ hospi->TxCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_RX_HALF_CPLT_CB_ID :
+ hospi->RxHalfCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_TX_HALF_CPLT_CB_ID :
+ hospi->TxHalfCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_STATUS_MATCH_CB_ID :
+ hospi->StatusMatchCallback = pCallback;
+ break;
+ case HAL_OSPI_TIMEOUT_CB_ID :
+ hospi->TimeOutCallback = pCallback;
+ break;
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = pCallback;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hospi->State == HAL_OSPI_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_OSPI_MSP_INIT_CB_ID :
- hospi->MspInitCallback = pCallback;
- break;
- case HAL_OSPI_MSP_DEINIT_CB_ID :
- hospi->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = pCallback;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -2110,7 +2110,7 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_
/**
* @brief Unregister a User OSPI Callback
- * OSPI Callback is redirected to the weak (surcharged) predefined callback
+ * OSPI Callback is redirected to the weak predefined callback
* @param hospi : OSPI handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -2128,74 +2128,74 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_
* @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
- if(hospi->State == HAL_OSPI_STATE_READY)
+ if (hospi->State == HAL_OSPI_STATE_READY)
{
switch (CallbackID)
{
- case HAL_OSPI_ERROR_CB_ID :
- hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
- break;
- case HAL_OSPI_ABORT_CB_ID :
- hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
- break;
- case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
- hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
- break;
- case HAL_OSPI_CMD_CPLT_CB_ID :
- hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
- break;
- case HAL_OSPI_RX_CPLT_CB_ID :
- hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
- break;
- case HAL_OSPI_TX_CPLT_CB_ID :
- hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
- break;
- case HAL_OSPI_RX_HALF_CPLT_CB_ID :
- hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
- break;
- case HAL_OSPI_TX_HALF_CPLT_CB_ID :
- hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
- break;
- case HAL_OSPI_STATUS_MATCH_CB_ID :
- hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
- break;
- case HAL_OSPI_TIMEOUT_CB_ID :
- hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
- break;
- case HAL_OSPI_MSP_INIT_CB_ID :
- hospi->MspInitCallback = HAL_OSPI_MspInit;
- break;
- case HAL_OSPI_MSP_DEINIT_CB_ID :
- hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
- break;
- default :
- /* Update the error code */
- hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_OSPI_ERROR_CB_ID :
+ hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
+ break;
+ case HAL_OSPI_ABORT_CB_ID :
+ hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
+ break;
+ case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
+ hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
+ break;
+ case HAL_OSPI_CMD_CPLT_CB_ID :
+ hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
+ break;
+ case HAL_OSPI_RX_CPLT_CB_ID :
+ hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
+ break;
+ case HAL_OSPI_TX_CPLT_CB_ID :
+ hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
+ break;
+ case HAL_OSPI_RX_HALF_CPLT_CB_ID :
+ hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
+ break;
+ case HAL_OSPI_TX_HALF_CPLT_CB_ID :
+ hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
+ break;
+ case HAL_OSPI_STATUS_MATCH_CB_ID :
+ hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
+ break;
+ case HAL_OSPI_TIMEOUT_CB_ID :
+ hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
+ break;
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = HAL_OSPI_MspInit;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hospi->State == HAL_OSPI_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_OSPI_MSP_INIT_CB_ID :
- hospi->MspInitCallback = HAL_OSPI_MspInit;
- break;
- case HAL_OSPI_MSP_DEINIT_CB_ID :
- hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
- break;
- default :
- /* Update the error code */
- hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = HAL_OSPI_MspInit;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -2234,10 +2234,10 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OS
*/
/**
-* @brief Abort the current transmission.
-* @param hospi : OSPI handle
-* @retval HAL status
-*/
+ * @brief Abort the current transmission.
+ * @param hospi : OSPI handle
+ * @retval HAL status
+ */
HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -2302,10 +2302,10 @@ HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi)
}
/**
-* @brief Abort the current transmission (non-blocking function)
-* @param hospi : OSPI handle
-* @retval HAL status
-*/
+ * @brief Abort the current transmission (non-blocking function)
+ * @param hospi : OSPI handle
+ * @retval HAL status
+ */
HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -2395,7 +2395,7 @@ HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t
hospi->Init.FifoThreshold = Threshold;
/* Configure new fifo threshold */
- MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1U) << OCTOSPI_CR_FTHRES_Pos));
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos));
}
else
@@ -2412,7 +2412,7 @@ HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t
* @param hospi : OSPI handle.
* @retval Fifo threshold
*/
-uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi)
+uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi)
{
return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U);
}
@@ -2429,11 +2429,11 @@ HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeou
}
/**
-* @brief Return the OSPI error code.
-* @param hospi : OSPI handle
-* @retval OSPI Error Code
-*/
-uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi)
+ * @brief Return the OSPI error code.
+ * @param hospi : OSPI handle
+ * @retval OSPI Error Code
+ */
+uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi)
{
return hospi->ErrorCode;
}
@@ -2443,7 +2443,7 @@ uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi)
* @param hospi : OSPI handle
* @retval HAL state
*/
-uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi)
+uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi)
{
/* Return OSPI handle state */
return hospi->State;
@@ -2464,7 +2464,7 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi)
*/
static void OSPI_DMACplt(DMA_HandleTypeDef *hdma)
{
- OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent);
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
hospi->XferCount = 0;
/* Disable the DMA transfer on the OctoSPI side */
@@ -2484,7 +2484,7 @@ static void OSPI_DMACplt(DMA_HandleTypeDef *hdma)
*/
static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma)
{
- OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent);
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
hospi->XferCount = (hospi->XferCount >> 1);
if (hospi->State == HAL_OSPI_STATE_BUSY_RX)
@@ -2512,7 +2512,7 @@ static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma)
*/
static void OSPI_DMAError(DMA_HandleTypeDef *hdma)
{
- OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent);
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
hospi->XferCount = 0;
hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
@@ -2544,7 +2544,7 @@ static void OSPI_DMAError(DMA_HandleTypeDef *hdma)
*/
static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
{
- OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent);
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
hospi->XferCount = 0;
/* Check the state */
@@ -2603,12 +2603,12 @@ static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hosp
FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is in expected state */
- while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State)
+ while ((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hospi->State = HAL_OSPI_STATE_ERROR;
hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
@@ -2675,7 +2675,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
/* Configure the CCR register with alternate bytes communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE),
- (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize));
+ (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize));
}
/* Configure the TCR register with the number of dummy cycles */
@@ -2702,9 +2702,9 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
- (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
- cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
- cmd->DataMode | cmd->DataDtrMode));
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+ cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
+ cmd->DataMode | cmd->DataDtrMode));
}
else
{
@@ -2713,8 +2713,8 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
- (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
- cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+ cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
/* The DHQC bit is linked with DDTR bit which should be activated */
if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
@@ -2739,8 +2739,8 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
- (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
- cmd->DataMode | cmd->DataDtrMode));
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+ cmd->DataMode | cmd->DataDtrMode));
}
else
{
@@ -2748,7 +2748,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE),
- (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
/* The DHQC bit is linked with DDTR bit which should be activated */
if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
@@ -2774,8 +2774,8 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
- (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
- cmd->DataMode | cmd->DataDtrMode));
+ (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | cmd->DataMode |
+ cmd->DataDtrMode));
}
else
{
@@ -2783,7 +2783,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
- (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
+ (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
}
/* Configure the AR register with the instruction value */
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_otfdec.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_otfdec.c
index bc011ca340..343f70d338 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_otfdec.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_otfdec.c
@@ -73,11 +73,11 @@
The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
- Use Functions HAL_OTFDEC_RegisterCallback()
+ Use Functions @ref HAL_OTFDEC_RegisterCallback()
to register an interrupt callback.
[..]
- Function HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
+ Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : OTFDEC error callback
(+) MspInitCallback : OTFDEC Msp Init callback
(+) MspDeInitCallback : OTFDEC Msp DeInit callback
@@ -85,11 +85,11 @@
and a pointer to the user callback function.
[..]
- Use function HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
+ Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
weak function.
[..]
- HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ @ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : OTFDEC error callback
@@ -97,27 +97,27 @@
(+) MspDeInitCallback : OTFDEC Msp DeInit callback
[..]
- By default, after the HAL_OTFDEC_Init() and when the state is HAL_OTFDEC_STATE_RESET
+ By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET
all callbacks are set to the corresponding weak functions:
- example HAL_OTFDEC_ErrorCallback().
+ example @ref HAL_OTFDEC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the HAL_OTFDEC_Init()HAL_OTFDEC_DeInit() only when
+ reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
- If MspInit or MspDeInit are not null, the HAL_OTFDEC_Init()/HAL_OTFDEC_DeInit()
+ If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in HAL_OTFDEC_STATE_READY state only.
+ Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in HAL_OTFDEC_STATE_READY or HAL_OTFDEC_STATE_RESET state,
+ in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
- using HAL_OTFDEC_RegisterCallback() before calling HAL_OTFDEC_DeInit()
- or HAL_OTFDEC_Init() function.
+ using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit()
+ or @ref HAL_OTFDEC_Init() function.
[..]
When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or
@@ -693,7 +693,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
- OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
+ const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
{
OTFDEC_Region_TypeDef *region;
uint32_t address;
@@ -780,16 +780,16 @@ HAL_StatusTypeDef HAL_OTFDEC_ConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uin
* @param pKey pointer at set of keys
* @retval CRC value
*/
-uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
+uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey)
{
uint8_t crc7_poly = 0x7;
- uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U};
+ const uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U};
uint8_t i;
uint8_t crc = 0;
uint32_t j;
uint32_t keyval;
uint32_t k;
- uint32_t *temp = pKey;
+ const uint32_t *temp = pKey;
for (j = 0U; j < 4U; j++)
{
@@ -879,20 +879,17 @@ HAL_StatusTypeDef HAL_OTFDEC_DisableEnciphering(OTFDEC_HandleTypeDef *hotfdec)
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
- uint32_t *input, uint32_t *output, uint32_t size, uint32_t start_address)
+ const uint32_t *input, uint32_t *output, uint32_t size, uint32_t start_address)
{
uint32_t j;
__IO uint32_t *extMem_ptr = (uint32_t *)start_address;
- uint32_t *in_ptr = input;
+ const uint32_t *in_ptr = input;
uint32_t *out_ptr = output;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
- /* Prevent unused argument(s) compilation warning */
- UNUSED(RegionIndex);
-
if ((input == NULL) || (output == NULL) || (size == 0U))
{
return HAL_ERROR;
@@ -1025,7 +1022,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32
* the configuration information for OTFDEC module
* @retval HAL state
*/
-HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec)
+HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec)
{
return hotfdec->State;
}
@@ -1064,9 +1061,9 @@ HAL_StatusTypeDef HAL_OTFDEC_GetConfigAttributes(OTFDEC_HandleTypeDef *hotfdec,
* @param RegionIndex index of region the keys CRC of which is read
* @retval Key CRC
*/
-uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
+uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
- OTFDEC_Region_TypeDef *region;
+ const OTFDEC_Region_TypeDef *region;
uint32_t address;
uint32_t keycrc;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd.c
index 14a8b1234e..4d116938fc 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd.c
@@ -1481,7 +1481,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
* @param ep_addr endpoint address
* @retval Data Size
*/
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
{
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
}
@@ -1621,9 +1621,18 @@ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(ep_addr);
+ __HAL_LOCK(hpcd);
+
+ if ((ep_addr & 0x80U) == 0x80U)
+ {
+ (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
+ }
+ else
+ {
+ (void)USB_FlushRxFifo(hpcd->Instance);
+ }
+
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -1672,7 +1681,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
* @param hpcd PCD handle
* @retval HAL state
*/
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd)
{
return hpcd->State;
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pka.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pka.c
index 9bbe5a6b35..db3078c7a6 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pka.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pka.c
@@ -277,9 +277,9 @@
/** @defgroup PKA_Private_Functions PKA Private Functions
* @{
*/
-uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka);
-HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart);
-uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode);
+uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka);
+HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart);
+uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode);
uint32_t PKA_GetBitSize_u8(uint32_t byteNumber);
uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb);
uint32_t PKA_GetBitSize_u32(uint32_t wordNumber);
@@ -787,7 +787,6 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i
{
/* Set input parameter in PKA RAM */
PKA_ModExp_Set(hpka, in);
-
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout);
}
@@ -802,7 +801,6 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef
{
/* Set input parameter in PKA RAM */
PKA_ModExp_Set(hpka, in);
-
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP);
}
@@ -818,7 +816,6 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast
{
/* Set input parameter in PKA RAM */
PKA_ModExpFastMode_Set(hpka, in);
-
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout);
}
@@ -833,7 +830,6 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF
{
/* Set input parameter in PKA RAM */
PKA_ModExpFastMode_Set(hpka, in);
-
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE);
}
@@ -867,7 +863,6 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType
{
/* Set input parameter in PKA RAM */
PKA_ECDSASign_Set(hpka, in);
-
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout);
}
@@ -882,7 +877,6 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT
{
/* Set input parameter in PKA RAM */
PKA_ECDSASign_Set(hpka, in);
-
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE);
}
@@ -1059,7 +1053,6 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i
{
/* Set input parameter in PKA RAM */
PKA_ECCMul_Set(hpka, in);
-
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
}
@@ -1074,7 +1067,6 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef
{
/* Set input parameter in PKA RAM */
PKA_ECCMul_Set(hpka, in);
-
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
}
@@ -1571,12 +1563,11 @@ void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka)
void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
{
uint32_t mode = PKA_GetMode(hpka);
- FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR);
- FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR);
- FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND);
+ uint32_t itsource = READ_REG(hpka->Instance->CR);
+ uint32_t flag = READ_REG(hpka->Instance->SR);
/* Address error interrupt occurred */
- if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET))
+ if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR))
{
hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR;
@@ -1585,7 +1576,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
}
/* RAM access error interrupt occurred */
- if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET))
+ if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR))
{
hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR;
@@ -1613,7 +1604,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
}
/* End Of Operation interrupt occurred */
- if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET))
+ if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND))
{
/* Clear PROCEND flag */
__HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND);
@@ -1682,7 +1673,7 @@ __weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka)
* @param hpka PKA handle
* @retval HAL status
*/
-HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka)
+HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka)
{
/* Return PKA handle state */
return hpka->State;
@@ -1693,7 +1684,7 @@ HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka)
* @param hpka PKA handle
* @retval PKA error code
*/
-uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka)
+uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka)
{
/* Return PKA handle error code */
return hpka->ErrorCode;
@@ -1716,7 +1707,7 @@ uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka)
* @param hpka PKA handle
* @retval Return the current mode
*/
-uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka)
+uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka)
{
/* return the shifted PKA_CR_MODE value */
return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
@@ -1729,7 +1720,7 @@ uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka)
* @param Tickstart Tick start value
* @retval HAL status
*/
-HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
+HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
{
/* Wait for the end of operation or timeout */
while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL)
@@ -1752,7 +1743,7 @@ HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeo
* @param mode PKA operating mode
* @retval error code
*/
-uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode)
+uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode)
{
uint32_t err = HAL_PKA_ERROR_NONE;
@@ -2109,8 +2100,8 @@ void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
- * @note If the modulus size is bigger than the hash size (with a curve SECP521R1 when using a SHA256 hash for example)
- * the hash value should be written at the end of the buffer with zeros padding at beginning.
+ * @note If the modulus size is bigger than the hash size (with a curve SECP521R1 when using a SHA256 hash
+ * for example)the hash value should be written at the end of the buffer with zeros padding at beginning.
*/
void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
{
@@ -2323,7 +2314,6 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
}
-
/**
* @brief Set input parameters.
* @param hpka PKA handle
@@ -2403,7 +2393,7 @@ void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
/* Move the input parameters modulus value n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize);
- __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL));
+ __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + ((in->modSize + 3UL) / 4UL));
}
/**
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr.c
index 8bbf0473d5..9c4f258c6c 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr.c
@@ -560,10 +560,6 @@ void HAL_PWR_EnterSTANDBYMode(void)
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
- /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
- __force_stores();
-#endif
/* Request Wait For Interrupt */
__WFI();
}
@@ -674,7 +670,6 @@ __weak void HAL_PWR_PVDCallback(void)
void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes)
{
/* Check the parameters */
- assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
assert_param(IS_PWR_ATTRIBUTES(Attributes));
/* Privilege/non-privilege attribute */
@@ -694,6 +689,9 @@ void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Check the parameters */
+ assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
+
/* Secure/non-secure attribute */
if ((Attributes & PWR_SEC) == PWR_SEC)
{
@@ -708,6 +706,11 @@ void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes)
/* do nothing */
}
+#else
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Item);
+
#endif /* __ARM_FEATURE_CMSE */
}
@@ -729,9 +732,6 @@ HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut
return HAL_ERROR;
}
- /* Check the parameters */
- assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
-
/* Get privilege or non-privilege attribute */
if (READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV) != 0x00U)
{
@@ -744,6 +744,9 @@ HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Check the parameters */
+ assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
+
/* Get the secure or non-secure attribute state */
if ((PWR_S->SECCFGR & Item) == Item)
{
@@ -754,6 +757,11 @@ HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut
attributes |= PWR_NSEC;
}
+#else
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Item);
+
#endif /* __ARM_FEATURE_CMSE */
/* return value */
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr_ex.c
index 868c54e5c7..7e543ab2c4 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr_ex.c
@@ -1037,10 +1037,6 @@ void HAL_PWREx_EnterSHUTDOWNMode(void)
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
- /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
- __force_stores();
-#endif
/* Request Wait For Interrupt */
__WFI();
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc.c
index a7a319c21b..12d2191e94 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc.c
@@ -1377,8 +1377,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
{
GPIO_InitTypeDef GPIO_InitStruct;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(RCC_MCOx);
+
/* Check the parameters */
- assert_param(IS_RCC_MCO(RCC_MCOx));
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
@@ -1546,8 +1549,8 @@ uint32_t HAL_RCC_GetPCLK2Freq(void)
}
/**
- * @brief Configure the RCC_OscInitStruct according to the internal
- * RCC configuration registers.
+ * @brief Return the oscillators and main PLL configuration in RCC_OscInitStruct
+ * according to the internal RCC configuration registers.
* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
* will be configured.
* @retval None
@@ -1562,13 +1565,16 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
/* Get the HSE configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
- }
- else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
+ if ((RCC->CR & RCC_CR_HSERDY) == RCC_CR_HSERDY)
{
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
}
else
{
@@ -1576,7 +1582,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the MSI configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION)
+ if ((RCC->CR & RCC_CR_MSIRDY) == RCC_CR_MSIRDY)
{
RCC_OscInitStruct->MSIState = RCC_MSI_ON;
}
@@ -1589,7 +1595,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_CR_MSIRANGE));
/* Get the HSI configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
+ if ((RCC->CR & RCC_CR_HSIRDY) == RCC_CR_HSIRDY)
{
RCC_OscInitStruct->HSIState = RCC_HSI_ON;
}
@@ -1601,26 +1607,29 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
/* Get the LSE configuration -----------------------------------------------*/
- if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ if ((RCC->BDCR & RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY)
{
- if ((RCC->BDCR & RCC_BDCR_LSESYSEN) == RCC_BDCR_LSESYSEN)
+ if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
- }
- else
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY;
- }
- }
- else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
- {
- if ((RCC->BDCR & RCC_BDCR_LSESYSEN) == RCC_BDCR_LSESYSEN)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ if ((RCC->BDCR & RCC_BDCR_LSESYSEN) == RCC_BDCR_LSESYSEN)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY;
+ }
}
else
{
- RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY;
+ if ((RCC->BDCR & RCC_BDCR_LSESYSEN) == RCC_BDCR_LSESYSEN)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY;
+ }
}
}
else
@@ -1629,7 +1638,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the LSI configuration -----------------------------------------------*/
- if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
+ if ((RCC->CSR & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY)
{
RCC_OscInitStruct->LSIState = RCC_LSI_ON;
}
@@ -1648,7 +1657,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the HSI48 configuration ---------------------------------------------*/
- if ((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
+ if ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY)
{
RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
}
@@ -1658,7 +1667,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Get the PLL configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
+ if ((RCC->CR & RCC_CR_PLLRDY) == RCC_CR_PLLRDY)
{
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
}
@@ -1675,8 +1684,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/**
- * @brief Configure the RCC_ClkInitStruct according to the internal
- * RCC configuration registers.
+ * @brief Return the clocks configuration in RCC_ClkInitStruct according to the
+ * internal RCC configuration registers as well as the current FLASH latency.
* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
@@ -1805,7 +1814,6 @@ uint32_t HAL_RCC_GetResetSource(void)
void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes)
{
/* Check the parameters */
- assert_param(IS_RCC_ITEMS_ATTRIBUTES(Item));
assert_param(IS_RCC_ATTRIBUTES(Attributes));
/* Privilege/non-privilege attribute */
@@ -1824,6 +1832,9 @@ void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Check the parameters */
+ assert_param(IS_RCC_ITEMS_ATTRIBUTES(Item));
+
/* Secure/non-secure attribute */
if ((Attributes & RCC_SEC) == RCC_SEC)
{
@@ -1838,6 +1849,11 @@ void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes)
/* do nothing */
}
+#else
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Item);
+
#endif /* __ARM_FEATURE_CMSE */
}
@@ -1859,8 +1875,6 @@ HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut
return HAL_ERROR;
}
- /* Check the parameters */
- assert_param(IS_RCC_ITEMS_ATTRIBUTES(Item));
/* Get privilege or non-privilege attribute */
if (READ_BIT(RCC->CR, RCC_CR_PRIV) != 0U)
@@ -1874,6 +1888,9 @@ HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ /* Check the parameters */
+ assert_param(IS_RCC_ITEMS_ATTRIBUTES(Item));
+
/* Get the secure or non-secure attribute state */
if ((RCC_S->SECCFGR & Item) == Item)
{
@@ -1884,6 +1901,11 @@ HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut
attributes |= RCC_NSEC;
}
+#else
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Item);
+
#endif /* __ARM_FEATURE_CMSE */
/* return value */
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng.c
index 5cad7de944..ca33d9f7a6 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng.c
@@ -52,7 +52,7 @@
[..]
Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak (overridden) function.
HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -66,10 +66,10 @@
[..]
By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak (overridden) functions:
example HAL_RNG_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_RNG_Init()
+ reset to the legacy weak (overridden) functions in the HAL_RNG_Init()
and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -86,7 +86,7 @@
[..]
When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -208,7 +208,6 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
/* Clock Error Detection Configuration when CONDRT bit is set to 1 */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
-
#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
/*!< magic number must be written immediately before to RNG_HTCRG */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
@@ -249,7 +248,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
/* Get tick */
tickstart = HAL_GetTick();
/* Check if data register contains valid random data */
- while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
+ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET)
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
@@ -690,8 +689,6 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
/* Update the error code and status */
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
status = HAL_ERROR;
- /* Clear bit DRDY */
- CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY);
}
else /* No seed error */
{
@@ -769,18 +766,19 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
uint32_t rngclockerror = 0U;
+ uint32_t itflag = hrng->Instance->SR;
/* RNG clock error interrupt occurred */
- if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
+ if ((itflag & RNG_IT_CEI) == RNG_IT_CEI)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U;
}
- else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI)
{
/* Check if Seed Error Current Status (SECS) is set */
- if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+ if ((itflag & RNG_FLAG_SECS) != RNG_FLAG_SECS)
{
/* RNG IP performed the reset automatically (auto-reset) */
/* Clear bit SEIS */
@@ -820,7 +818,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
}
/* Check RNG data ready interrupt occurred */
- if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+ if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY)
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
@@ -852,7 +850,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
* the configuration information for RNG.
* @retval random value
*/
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng)
{
return (hrng->RandomNumber);
}
@@ -919,7 +917,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
* the configuration information for RNG.
* @retval HAL state
*/
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng)
{
return hrng->State;
}
@@ -929,7 +927,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
* @param hrng: pointer to a RNG_HandleTypeDef structure.
* @retval RNG Error Code
*/
-uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
+uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng)
{
/* Return RNG Error Code */
return hrng->ErrorCode;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng_ex.c
index c19f9d5a41..19171ae0e3 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng_ex.c
@@ -62,11 +62,11 @@
/* Private functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RNG_Ex_Exported_Functions
+/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
* @{
*/
-/** @addtogroup RNG_Ex_Exported_Functions_Group1
+/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions
* @brief Configuration functions
*
@verbatim
@@ -86,12 +86,12 @@
* RNG_ConfigTypeDef.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains
+ * @param pConf pointer to a RNG_ConfigTypeDef structure that contains
* the configuration information for RNG module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf)
{
uint32_t tickstart;
uint32_t cr_value;
@@ -185,7 +185,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef
* RNG_ConfigTypeDef.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains
+ * @param pConf pointer to a RNG_ConfigTypeDef structure that contains
* the configuration information for RNG module
* @retval HAL status
@@ -279,12 +279,12 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng)
* @}
*/
-/** @addtogroup RNG_Ex_Exported_Functions_Group2
+/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function
* @brief Recover from seed error function
*
@verbatim
===============================================================================
- ##### Configuration and lock functions #####
+ ##### Recover from seed error function #####
===============================================================================
[..] This section provide function allowing to:
(+) Recover from a seed error
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sai.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sai.c
index 0d5a2c6866..c1b617a8a4 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sai.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sai.c
@@ -169,7 +169,7 @@
[..]
Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
@@ -184,10 +184,10 @@
[..]
By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ all callbacks are reset to the corresponding legacy weak functions:
examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+ reset to the legacy weak functions in the HAL_SAI_Init
and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -204,7 +204,7 @@
[..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
*/
@@ -1377,6 +1377,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
/* Process Locked */
__HAL_LOCK(hsai);
+ /* Disable SAI peripheral */
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+
/* Disable the SAI DMA request */
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
@@ -1396,12 +1402,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
(void) HAL_DMA_Abort(hsai->hdmarx);
}
- /* Disable SAI peripheral */
- if (SAI_Disable(hsai) != HAL_OK)
- {
- status = HAL_ERROR;
- }
-
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
@@ -1427,6 +1427,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
/* Process Locked */
__HAL_LOCK(hsai);
+ /* Disable SAI peripheral */
+ if (SAI_Disable(hsai) != HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+
/* Check SAI DMA is enabled or not */
if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
{
@@ -1454,12 +1460,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
hsai->Instance->IMR = 0;
hsai->Instance->CLRFR = 0xFFFFFFFFU;
- /* Disable SAI peripheral */
- if (SAI_Disable(hsai) != HAL_OK)
- {
- status = HAL_ERROR;
- }
-
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd.c
index 7ef6d11ba6..4b9279fde7 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd.c
@@ -56,7 +56,6 @@
(#) At this stage, you can perform SD read/write/erase operations after SD card initialization
-
*** SD Card Initialization and configuration ***
================================================
[..]
@@ -211,7 +210,7 @@
respectively HAL_SD_RegisterTransceiverCallback().
Use function HAL_SD_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
(+) ErrorCallback : callback when error occurs.
@@ -227,9 +226,9 @@
respectively HAL_SD_UnRegisterTransceiverCallback().
By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SD_Init
+ reset to the legacy weak (overridden) functions in the HAL_SD_Init
and HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -244,7 +243,7 @@
When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -261,6 +260,7 @@
* @{
*/
+#if defined (SDMMC1) || defined (SDMMC2)
#ifdef HAL_SD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
@@ -300,9 +300,9 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
static void SD_PowerOFF(SD_HandleTypeDef *hsd);
static void SD_Write_IT(SD_HandleTypeDef *hsd);
static void SD_Read_IT(SD_HandleTypeDef *hsd);
-static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd);
+static uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode);
#if (USE_SD_TRANSCEIVER != 0U)
-static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd);
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode);
static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd);
#endif /* USE_SD_TRANSCEIVER */
/**
@@ -439,7 +439,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
tickstart = HAL_GetTick();
while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
{
- if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
@@ -479,7 +479,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
/* Init Clock should be less or equal to 400Khz*/
- sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
if (sdmmc_clk == 0U)
{
hsd->State = HAL_SD_STATE_READY;
@@ -509,8 +509,15 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
/* wait 74 Cycles: required power up waiting time before starting
the SD initialization sequence */
- sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
- HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+ if (Init.ClockDiv != 0U)
+ {
+ sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+ }
+
+ if (sdmmc_clk != 0U)
+ {
+ HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+ }
/* Identify card operating voltage */
errorstate = SD_PowerON(hsd);
@@ -600,7 +607,6 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
return HAL_OK;
}
-
/**
* @brief Initializes the SD MSP.
* @param hsd: Pointer to SD handle
@@ -697,7 +703,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- add *= 512U;
+ add *= BLOCKSIZE;
}
/* Configure the SD DPSM (Data Path State Machine) */
@@ -739,10 +745,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
dataremaining = config.DataLength;
while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
{
/* Read data from SDMMC Rx FIFO */
- for (count = 0U; count < 8U; count++)
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
{
data = SDMMC_ReadFIFO(hsd->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
@@ -754,7 +760,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
*tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
tempbuff++;
}
- dataremaining -= 32U;
+ dataremaining -= SDMMC_FIFO_SIZE;
}
if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
@@ -847,8 +853,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
- uint32_t Timeout)
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -857,7 +863,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
uint32_t data;
uint32_t dataremaining;
uint32_t add = BlockAdd;
- uint8_t *tempbuff = pData;
+ const uint8_t *tempbuff = pData;
if (NULL == pData)
{
@@ -882,7 +888,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- add *= 512U;
+ add *= BLOCKSIZE;
}
/* Configure the SD DPSM (Data Path State Machine) */
@@ -925,10 +931,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
SDMMC_FLAG_DATAEND))
{
- if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
{
/* Write data to SDMMC Tx FIFO */
- for (count = 0U; count < 8U; count++)
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
{
data = (uint32_t)(*tempbuff);
tempbuff++;
@@ -940,7 +946,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
tempbuff++;
(void)SDMMC_WriteFIFO(hsd->Instance, &data);
}
- dataremaining -= 32U;
+ dataremaining -= SDMMC_FIFO_SIZE;
}
if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
@@ -1067,7 +1073,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- add *= 512U;
+ add *= BLOCKSIZE;
}
/* Configure the SD DPSM (Data Path State Machine) */
@@ -1129,7 +1135,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
@@ -1162,7 +1168,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u
if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- add *= 512U;
+ add *= BLOCKSIZE;
}
/* Configure the SD DPSM (Data Path State Machine) */
@@ -1259,7 +1265,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- add *= 512U;
+ add *= BLOCKSIZE;
}
/* Configure the SD DPSM (Data Path State Machine) */
@@ -1303,7 +1309,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
/* Enable transfer interrupts */
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
-
return HAL_OK;
}
else
@@ -1325,7 +1330,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
@@ -1358,7 +1363,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- add *= 512U;
+ add *= BLOCKSIZE;
}
/* Configure the SD DPSM (Data Path State Machine) */
@@ -1370,7 +1375,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
-
__SDMMC_CMDTRANS_ENABLE(hsd->Instance);
hsd->Instance->IDMABASE0 = (uint32_t) pData ;
@@ -1467,8 +1471,8 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui
/* Get start and end block for high capacity cards */
if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- start_add *= 512U;
- end_add *= 512U;
+ start_add *= BLOCKSIZE;
+ end_add *= BLOCKSIZE;
}
/* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
@@ -1758,7 +1762,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
* @param hsd: Pointer to sd handle
* @retval HAL state
*/
-HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
+HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd)
{
return hsd->State;
}
@@ -1769,7 +1773,7 @@ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
* the configuration information.
* @retval SD Error Code
*/
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
+uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd)
{
return hsd->ErrorCode;
}
@@ -1853,7 +1857,10 @@ __weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User SD Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (overridden) predefined callback
+ * @note The HAL_SD_RegisterCallback() may be called before HAL_SD_Init() in
+ * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID
+ * and HAL_SD_MSP_DEINIT_CB_ID.
* @param hsd : SD handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1882,9 +1889,6 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsd);
-
if (hsd->State == HAL_SD_STATE_READY)
{
switch (CallbackID)
@@ -1953,14 +1957,15 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsd);
return status;
}
/**
* @brief Unregister a User SD Callback
- * SD Callback is redirected to the weak (surcharged) predefined callback
+ * SD Callback is redirected to the weak (overridden) predefined callback
+ * @note The HAL_SD_UnRegisterCallback() may be called before HAL_SD_Init() in
+ * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID
+ * and HAL_SD_MSP_DEINIT_CB_ID.
* @param hsd : SD handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1980,9 +1985,6 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsd);
-
if (hsd->State == HAL_SD_STATE_READY)
{
switch (CallbackID)
@@ -2051,15 +2053,13 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsd);
return status;
}
#if (USE_SD_TRANSCEIVER != 0U)
/**
* @brief Register a User SD Transceiver Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (overridden) predefined callback
* @param hsd : SD handle
* @param pCallback : pointer to the Callback function
* @retval status
@@ -2097,7 +2097,7 @@ HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_
/**
* @brief Unregister a User SD Transceiver Callback
- * SD Callback is redirected to the weak (surcharged) predefined callback
+ * SD Callback is redirected to the weak (overridden) predefined callback
* @param hsd : SD handle
* @retval status
*/
@@ -2233,8 +2233,8 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef
hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
- hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
- hsd->SdCard.LogBlockSize = 512U;
+ hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / BLOCKSIZE);
+ hsd->SdCard.LogBlockSize = BLOCKSIZE;
}
else if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
{
@@ -2243,7 +2243,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef
hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
- hsd->SdCard.BlockSize = 512U;
+ hsd->SdCard.BlockSize = BLOCKSIZE;
hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
}
else
@@ -2360,7 +2360,6 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
status = HAL_ERROR;
}
-
return status;
}
@@ -2401,6 +2400,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
SDMMC_InitTypeDef Init;
uint32_t errorstate;
uint32_t sdmmc_clk;
+
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
@@ -2435,7 +2435,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
}
else
{
- /* MMC Card does not support this feature */
+ /* SD Card does not support this feature */
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
@@ -2583,9 +2583,9 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
{
hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
/* Enable Ultra High Speed */
- if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
{
- if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
@@ -2595,7 +2595,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
{
/* Enable High Speed */
- if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
@@ -2607,13 +2607,33 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
}
break;
}
- case SDMMC_SPEED_MODE_ULTRA:
+ case SDMMC_SPEED_MODE_ULTRA_SDR104:
+ {
+ if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ {
+ /* Enable UltraHigh Speed */
+ if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
+ }
+ else
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+ break;
+ }
+ case SDMMC_SPEED_MODE_ULTRA_SDR50:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable UltraHigh Speed */
- if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ if (SD_UltraHighSpeed(hsd, SDMMC_SDR50_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
@@ -2654,7 +2674,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
- if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
@@ -2668,7 +2688,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
break;
}
case SDMMC_SPEED_MODE_DEFAULT:
+ {
+ /* Switch to default Speed */
+ if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+
break;
+ }
default:
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
status = HAL_ERROR;
@@ -2686,7 +2715,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
- if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
@@ -2705,7 +2734,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
- if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
@@ -2719,7 +2748,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
break;
}
case SDMMC_SPEED_MODE_DEFAULT:
+ {
+ /* Switch to default Speed */
+ if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+
break;
+ }
case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
default:
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
@@ -2737,7 +2775,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
- if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
@@ -2756,7 +2794,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
- if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+ if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
@@ -2770,7 +2808,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
break;
}
case SDMMC_SPEED_MODE_DEFAULT:
+ {
+ /* Switch to default Speed */
+ if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ status = HAL_ERROR;
+ }
+
break;
+ }
case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
default:
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
@@ -2783,7 +2830,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
tickstart = HAL_GetTick();
while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
{
- if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
@@ -2836,31 +2883,90 @@ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
*/
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
{
- HAL_SD_CardStateTypeDef CardState;
+ uint32_t error_code;
+ uint32_t tickstart;
- /* DIsable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
- SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+ if (hsd->State == HAL_SD_STATE_BUSY)
+ {
+ /* DIsable All interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+ /*we will send the CMD12 in all cases in order to stop the data transfers*/
+ /*In case the data transfer just finished , the external memory will not respond
+ and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/
+ /*In case the data transfer aborted , the external memory will respond and will return HAL_SD_ERROR_NONE*/
+ /*Other scenario will return HAL_ERROR*/
- /* If IDMA Context, disable Internal DMA */
- hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+ hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+ error_code = hsd->ErrorCode;
+ if ((error_code != HAL_SD_ERROR_NONE) && (error_code != HAL_SD_ERROR_CMD_RSP_TIMEOUT))
+ {
+ return HAL_ERROR;
+ }
- hsd->State = HAL_SD_STATE_READY;
+ tickstart = HAL_GetTick();
+ if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD)
+ {
+ if (hsd->ErrorCode == HAL_SD_ERROR_NONE)
+ {
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
- /* Initialize the SD operation */
- hsd->Context = SD_CONTEXT_NONE;
+ if (hsd->ErrorCode == HAL_SD_ERROR_CMD_RSP_TIMEOUT)
+ {
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)
+ {
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND))
+ {
+ if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do*/
+ }
- CardState = HAL_SD_GetCardState(hsd);
- if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
- }
- if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
- return HAL_ERROR;
+ /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear
+ the appropriate flags that will be set depending of the abort/non abort of the memory */
+ /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared
+ and will result in next SDMMC read/write operation to fail */
+
+ /*SDMMC ready for clear data flags*/
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_BUSYD0END);
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+ /* If IDMA Context, disable Internal DMA */
+ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ /* Initialize the SD operation */
+ hsd->Context = SD_CONTEXT_NONE;
}
return HAL_OK;
}
@@ -2922,7 +3028,6 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
* @{
*/
-
/**
* @brief Initializes the sd card.
* @param hsd: Pointer to SD handle
@@ -3128,7 +3233,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
/* Check to CKSTOP */
while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
{
- if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3158,7 +3263,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
/* Check VSWEND Flag */
while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
{
- if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3266,7 +3371,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
}
}
- if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3294,7 +3399,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
*pData = SDMMC_ReadFIFO(hsd->Instance);
pData++;
- if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3429,7 +3534,6 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
}
}
-
/**
* @brief Finds the SD card SCR register value.
* @param hsd: Pointer to SD handle
@@ -3484,8 +3588,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
index++;
}
-
- if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3515,11 +3618,11 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
- *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \
- ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24U) | ((tempscr[1] & SDMMC_8TO15BITS) << 8U) | \
+ ((tempscr[1] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24U));
scr++;
- *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \
- ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+ *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24U) | ((tempscr[0] & SDMMC_8TO15BITS) << 8U) | \
+ ((tempscr[0] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24U));
}
@@ -3540,10 +3643,10 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd)
tmp = hsd->pRxBuffPtr;
- if (hsd->RxXferSize >= 32U)
+ if (hsd->RxXferSize >= SDMMC_FIFO_SIZE)
{
/* Read data from SDMMC Rx FIFO */
- for (count = 0U; count < 8U; count++)
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
{
data = SDMMC_ReadFIFO(hsd->Instance);
*tmp = (uint8_t)(data & 0xFFU);
@@ -3557,7 +3660,7 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd)
}
hsd->pRxBuffPtr = tmp;
- hsd->RxXferSize -= 32U;
+ hsd->RxXferSize -= SDMMC_FIFO_SIZE;
}
}
@@ -3571,14 +3674,14 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd)
{
uint32_t count;
uint32_t data;
- uint8_t *tmp;
+ const uint8_t *tmp;
tmp = hsd->pTxBuffPtr;
- if (hsd->TxXferSize >= 32U)
+ if (hsd->TxXferSize >= SDMMC_FIFO_SIZE)
{
/* Write data to SDMMC Tx FIFO */
- for (count = 0U; count < 8U; count++)
+ for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
{
data = (uint32_t)(*tmp);
tmp++;
@@ -3592,7 +3695,7 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd)
}
hsd->pTxBuffPtr = tmp;
- hsd->TxXferSize -= 32U;
+ hsd->TxXferSize -= SDMMC_FIFO_SIZE;
}
}
@@ -3600,11 +3703,12 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd)
* @brief Switches the SD card to High Speed mode.
* This API must be used after "Transfer State"
* @note This operation should be followed by the configuration
- * of PLL to have SDMMCCK clock between 50 and 120 MHz
+ * of PLL to have SDMMCCK clock between 25 and 50 MHz
* @param hsd: SD handle
+ * @param SwitchSpeedMode: SD speed mode( SDMMC_SDR12_SWITCH_PATTERN, SDMMC_SDR25_SWITCH_PATTERN)
* @retval SD Card error state
*/
-uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
+uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode)
{
uint32_t errorstate = HAL_SD_ERROR_NONE;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
@@ -3619,7 +3723,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
- if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+ if (hsd->SdCard.CardSpeed >= CARD_HIGH_SPEED)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
@@ -3640,8 +3744,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
(void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
-
- errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN);
+ errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode);
if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
@@ -3658,8 +3761,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
}
loop ++;
}
-
- if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
@@ -3715,9 +3817,10 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
* @note This operation should be followed by the configuration
* of PLL to have SDMMCCK clock between 50 and 120 MHz
* @param hsd: SD handle
+ * @param UltraHighSpeedMode: SD speed mode( SDMMC_SDR50_SWITCH_PATTERN, SDMMC_SDR104_SWITCH_PATTERN)
* @retval SD Card error state
*/
-static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode)
{
uint32_t errorstate = HAL_SD_ERROR_NONE;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
@@ -3756,7 +3859,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
}
- errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN);
+ errorstate = SDMMC_CmdSwitch(hsd->Instance, UltraHighSpeedMode);
if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
@@ -3774,7 +3877,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
loop ++;
}
- if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
@@ -3904,7 +4007,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
loop ++;
}
- if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
@@ -4031,12 +4134,12 @@ __weak void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd)
*/
}
-
/**
* @}
*/
#endif /* HAL_SD_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd_ex.c
index 9d9d3e74ca..22bbc9d22d 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd_ex.c
@@ -44,6 +44,7 @@
* @{
*/
+#if defined (SDMMC1) || defined (SDMMC2)
#ifdef HAL_SD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
@@ -303,6 +304,7 @@ HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABu
*/
#endif /* HAL_SD_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smartcard.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smartcard.c
index 9943c5f4a1..c164814e6d 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smartcard.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smartcard.c
@@ -136,7 +136,7 @@
[..]
Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -153,10 +153,10 @@
[..]
By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
+ reset to the legacy weak functions in the HAL_SMARTCARD_Init()
and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -173,7 +173,7 @@
[..]
When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -467,7 +467,7 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User SMARTCARD Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
* in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
* and HAL_SMARTCARD_MSPDEINIT_CB_ID
@@ -2406,7 +2406,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
}
- MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
+ WRITE_REG(hsmartcard->Instance->RTOR, tmpreg);
/*-------------------------- USART BRR Configuration -----------------------*/
SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus.c
index 5830ad1c65..e3e88b3f62 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus.c
@@ -926,6 +926,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
+ uint32_t sizetoxfer;
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -958,11 +959,35 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
hsmbus->XferSize = Size;
}
+ sizetoxfer = hsmbus->XferSize;
+ if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) ||
+ (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
+ (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) ||
+ (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
+ {
+ if (hsmbus->pBuffPtr != NULL)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ hsmbus->XferCount--;
+ hsmbus->XferSize--;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+ if ((sizetoxfer < hsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer,
SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
SMBUS_GENERATE_START_WRITE);
}
@@ -977,7 +1002,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
(IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions,
SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
@@ -987,7 +1012,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer,
hsmbus->XferOptions,
SMBUS_GENERATE_START_WRITE);
}
@@ -996,8 +1021,15 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
- hsmbus->XferSize--;
- hsmbus->XferCount--;
+ if (hsmbus->XferSize > 0U)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
}
}
@@ -1813,7 +1845,7 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
* the configuration information for the specified SMBUS.
* @retval HAL state
*/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus)
{
/* Return SMBUS handle state */
return hsmbus->State;
@@ -1825,7 +1857,7 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
* the configuration information for the specified SMBUS.
* @retval SMBUS Error Code
*/
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus)
{
return hsmbus->ErrorCode;
}
@@ -2587,8 +2619,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
- /* Flush TX register */
- SMBUS_Flush_TXDR(hsmbus);
+ if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+ {
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+ }
/* Store current volatile hsmbus->ErrorCode, misra rule */
tmperror = hsmbus->ErrorCode;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus_ex.c
index afac88816c..e5a2d75085 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus_ex.c
@@ -6,6 +6,8 @@
* This file provides firmware functions to manage the following
* functionalities of SMBUS Extended peripheral:
* + Extended features functions
+ * + WakeUp Mode Functions
+ * + FastModePlus Functions
*
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi.c
index 418a022d09..12c3b4d215 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi.c
@@ -908,6 +908,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -957,6 +958,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -986,9 +988,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
{
errorcode = HAL_ERROR;
}
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ }
error:
- hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
@@ -1013,6 +1018,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1026,12 +1037,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
@@ -1109,6 +1114,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1132,6 +1138,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1226,9 +1233,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
{
errorcode = HAL_ERROR;
}
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ }
error :
- hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -1349,6 +1359,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
@@ -1387,6 +1411,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1407,6 +1432,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
}
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
@@ -1469,6 +1507,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1538,8 +1577,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ }
+
error :
- hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -1559,8 +1606,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
if ((pData == NULL) || (Size == 0U))
{
@@ -1574,6 +1619,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
goto error;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1613,10 +1661,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
}
#endif /* USE_SPI_CRC */
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
@@ -1624,8 +1668,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
-error :
+ /* Process Unlocked */
__HAL_UNLOCK(hspi);
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+error :
return errorcode;
}
@@ -1641,6 +1689,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
{
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1648,14 +1703,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
}
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
if ((pData == NULL) || (Size == 0U))
{
@@ -1663,6 +1710,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
goto error;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1715,9 +1765,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
}
#endif /* USE_SPI_CRC */
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
/* Note : The SPI must be enabled after unlocking current process
to avoid the risk of SPI interrupt handle execution before current
process unlock */
@@ -1729,9 +1776,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
__HAL_SPI_ENABLE(hspi);
}
-error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
+ /* Enable RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+error :
return errorcode;
}
@@ -1753,9 +1803,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process locked */
- __HAL_LOCK(hspi);
-
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
@@ -1773,6 +1820,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
goto error;
}
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -1829,8 +1879,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1839,9 +1887,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
__HAL_SPI_ENABLE(hspi);
}
-error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+error :
return errorcode;
}
@@ -1945,7 +1996,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
@@ -1985,6 +2035,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Check rx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1999,12 +2055,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Process Locked */
__HAL_LOCK(hspi);
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
@@ -2090,7 +2140,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
@@ -2258,7 +2307,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
@@ -2280,7 +2328,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi_ex.c
index c340a8e0d7..ca938fd46f 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi_ex.c
@@ -76,7 +76,7 @@
* the configuration information for the specified SPI module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
{
__IO uint32_t tmpreg;
uint8_t count = 0U;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sram.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sram.c
index 8aba3821af..77951fb06a 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sram.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sram.c
@@ -83,15 +83,15 @@
and a pointer to the user callback function.
Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : SRAM MspInit.
(+) MspDeInitCallback : SRAM MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init
+ reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -106,7 +106,7 @@
When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -736,7 +736,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User SRAM Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -756,9 +756,6 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsram);
-
state = hsram->State;
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
{
@@ -782,14 +779,12 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsram);
return status;
}
/**
* @brief Unregister a User SRAM Callback
- * SRAM Callback is redirected to the weak (surcharged) predefined callback
+ * SRAM Callback is redirected to the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -804,9 +799,6 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
- /* Process locked */
- __HAL_LOCK(hsram);
-
state = hsram->State;
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
@@ -852,14 +844,12 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsram);
return status;
}
/**
* @brief Register a User SRAM Callback for DMA transfers
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1023,7 +1013,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
* the configuration information for SRAM module.
* @retval HAL state
*/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
{
return hsram->State;
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim.c
index 5c96d62248..5b35a84848 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim.c
@@ -888,7 +888,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@@ -980,7 +980,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -1059,7 +1059,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Set the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@@ -1221,7 +1221,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -1557,7 +1557,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@@ -1649,7 +1649,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -1728,7 +1728,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Set the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@@ -1889,7 +1889,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -2133,7 +2133,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@@ -2181,7 +2181,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
@@ -2217,7 +2217,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@@ -2305,7 +2305,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -2381,7 +2381,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
/* Set the TIM channel state */
@@ -2536,7 +2536,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
/* Disable the Input Capture channel */
@@ -3027,7 +3027,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
{
uint32_t tmpsmcr;
uint32_t tmpccmr1;
@@ -3833,13 +3833,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
+ uint32_t itsource = htim->Instance->DIER;
+ uint32_t itflag = htim->Instance->SR;
+
/* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+ if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
{
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
@@ -3867,11 +3870,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+ if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@@ -3897,11 +3900,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+ if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@@ -3927,11 +3930,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+ if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@@ -3957,11 +3960,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+ if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
@@ -3970,11 +3973,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+ ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
@@ -3983,9 +3987,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Break2 input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -3996,11 +4000,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+ if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
@@ -4009,11 +4013,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+ if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
@@ -4564,7 +4568,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength)
{
HAL_StatusTypeDef status;
@@ -6958,6 +6963,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
+
+ /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+ {
+ /* Clear the update flag */
+ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ }
}
/**
@@ -6972,11 +6984,12 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7047,11 +7060,12 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7080,7 +7094,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
-
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
@@ -7123,11 +7136,12 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7197,11 +7211,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7258,11 +7273,12 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
@@ -7311,11 +7327,12 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
@@ -7499,9 +7516,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC1E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Select the Input */
if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
@@ -7589,9 +7606,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr1 &= ~TIM_CCMR1_CC2S;
@@ -7628,9 +7645,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
@@ -7672,9 +7689,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer;
/* Disable the Channel 3: Reset the CC3E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC3E;
tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC3S;
@@ -7720,9 +7737,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer;
/* Disable the Channel 4: Reset the CC4E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC4E;
tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC4S;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim_ex.c
index 52414836a9..f65c6888f8 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim_ex.c
@@ -847,7 +847,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -1093,17 +1093,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
(+) Stop the Complementary PWM and disable interrupts.
(+) Start the Complementary PWM and enable DMA transfers.
(+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
@endverbatim
* @{
*/
@@ -1329,7 +1318,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -2064,6 +2053,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+ assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
/* Check input state */
__HAL_LOCK(htim);
@@ -2080,15 +2070,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
-
- if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
- {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
-
- /* Set BREAK AF mode */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
- }
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
{
@@ -2096,20 +2078,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+ assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
-
- if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
- {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
-
- /* Set BREAK2 AF mode */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
- }
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
}
/* Set TIMx_BDTR */
@@ -2133,7 +2108,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
uint32_t BreakInput,
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
-
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmporx;
@@ -2428,7 +2402,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B
uint32_t tmpbdtr;
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_BREAKINPUT(BreakInput));
switch (BreakInput)
@@ -2445,7 +2419,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B
}
break;
}
-
case TIM_BREAKINPUT_BRK2:
{
/* Check initial conditions */
@@ -2477,13 +2450,13 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B
* @note Break input is automatically armed as soon as MOE bit is set.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_BREAKINPUT(BreakInput));
switch (BreakInput)
@@ -2562,7 +2535,7 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br
*/
/**
- * @brief Hall commutation changed callback in non-blocking mode
+ * @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2576,7 +2549,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
*/
}
/**
- * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @brief Commutation half complete callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2591,7 +2564,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
}
/**
- * @brief Hall Break detection callback in non-blocking mode
+ * @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2606,7 +2579,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
}
/**
- * @brief Hall Break2 detection callback in non blocking mode
+ * @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
@@ -2757,15 +2730,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
else
{
/* nothing to do */
@@ -2834,13 +2798,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
{
uint32_t tmp;
- tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
/* Reset the CCxNE Bit */
TIMx->CCER &= ~tmp;
/* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
}
/**
* @}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart.c
index 78ef7e8734..7b5907a0ac 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart.c
@@ -107,7 +107,7 @@
[..]
Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -131,10 +131,10 @@
[..]
By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+ reset to the legacy weak functions in the HAL_UART_Init()
and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -151,7 +151,7 @@
[..]
When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -197,8 +197,8 @@
/** @addtogroup UART_Private_Functions
* @{
*/
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
@@ -348,15 +348,17 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
__HAL_UART_DISABLE(huart);
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
- return HAL_ERROR;
+ UART_AdvFeatureConfig(huart);
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
{
- UART_AdvFeatureConfig(huart);
+ return HAL_ERROR;
}
/* In asynchronous mode, the following bits must be kept cleared:
@@ -413,15 +415,17 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
__HAL_UART_DISABLE(huart);
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
- return HAL_ERROR;
+ UART_AdvFeatureConfig(huart);
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
{
- UART_AdvFeatureConfig(huart);
+ return HAL_ERROR;
}
/* In half-duplex mode, the following bits must be kept cleared:
@@ -499,15 +503,17 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
__HAL_UART_DISABLE(huart);
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
- return HAL_ERROR;
+ UART_AdvFeatureConfig(huart);
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
{
- UART_AdvFeatureConfig(huart);
+ return HAL_ERROR;
}
/* In LIN mode, the following bits must be kept cleared:
@@ -583,15 +589,17 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
__HAL_UART_DISABLE(huart);
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
- return HAL_ERROR;
+ UART_AdvFeatureConfig(huart);
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
{
- UART_AdvFeatureConfig(huart);
+ return HAL_ERROR;
}
/* In multiprocessor mode, the following bits must be kept cleared:
@@ -696,7 +704,7 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User UART Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
* HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
* callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
@@ -963,10 +971,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
huart->RxEventCallback = pCallback;
}
@@ -977,9 +982,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(huart);
-
return status;
}
@@ -993,10 +995,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
}
@@ -1007,8 +1006,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(huart);
return status;
}
@@ -3229,6 +3226,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
{
@@ -3250,13 +3254,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
}
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- }
-
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
{
@@ -3382,24 +3379,24 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
return HAL_TIMEOUT;
}
- if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
{
- /* Clear Overrun Error flag*/
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ /* Clear Overrun Error flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts if ongoing */
- UART_EndRxTransfer(huart);
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
- huart->ErrorCode = HAL_UART_ERROR_ORE;
+ huart->ErrorCode = HAL_UART_ERROR_ORE;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
- return HAL_ERROR;
+ return HAL_ERROR;
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
{
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart_ex.c
index 4ffe2b75b7..d1b96667c6 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart_ex.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart_ex.c
@@ -211,15 +211,17 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
- return HAL_ERROR;
+ UART_AdvFeatureConfig(huart);
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
{
- UART_AdvFeatureConfig(huart);
+ return HAL_ERROR;
}
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
@@ -833,7 +835,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef status;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
@@ -847,24 +849,20 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
huart->RxEventType = HAL_UART_RXEVENT_TC;
- status = UART_Start_Receive_IT(huart, pData, Size);
+ (void)UART_Start_Receive_IT(huart, pData, Size);
- /* Check Rx process has been successfully started */
- if (status == HAL_OK)
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- }
- else
- {
- /* In case of errors already pending when reception is started,
- Interrupts may have already been raised and lead to reception abortion.
- (Overrun error for instance).
- In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
- status = HAL_ERROR;
- }
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
}
return status;
@@ -960,7 +958,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
* @param huart UART handle.
* @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
*/
-HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
{
/* Return Rx Event type value, as stored in UART handle */
return (huart->RxEventType);
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_usart.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_usart.c
index 2fc0a11824..9fcccfbe94 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_usart.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_usart.c
@@ -91,7 +91,7 @@
[..]
Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -109,10 +109,10 @@
[..]
By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_USART_Init()
+ reset to the legacy weak functions in the HAL_USART_Init()
and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -129,7 +129,7 @@
[..]
When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -144,7 +144,7 @@
*/
/** @defgroup USART USART
- * @brief HAL USART Synchronous module driver
+ * @brief HAL USART Synchronous SPI module driver
* @{
*/
@@ -225,8 +225,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
+ in synchronous SPI master/slave mode.
+ (+) For the synchronous SPI mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length
(++) Stop Bit
@@ -238,7 +238,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
(++) Receiver/transmitter modes
[..]
- The HAL_USART_Init() function follows the USART synchronous configuration
+ The HAL_USART_Init() function follows the USART synchronous SPI configuration
procedure (details for the procedure are available in reference manual).
@endverbatim
@@ -316,7 +316,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
return HAL_ERROR;
}
- /* In Synchronous mode, the following bits must be kept cleared:
+ /* In Synchronous SPI mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register.
*/
@@ -406,7 +406,7 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User USART Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
* to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
* @param husart usart handle
@@ -657,11 +657,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
===============================================================================
##### IO operation functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART synchronous
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI
data transfers.
- [..] The USART supports master mode only: it cannot receive or send data related to an input
- clock (SCLK is always an output).
+ [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input).
[..]
@@ -2908,7 +2907,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
/* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:
* set CPOL bit according to husart->Init.CLKPolarity value
* set CPHA bit according to husart->Init.CLKPhase value
- * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
+ * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only)
* set STOP[13:12] bits according to husart->Init.StopBits value */
tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
tmpreg |= (uint32_t)husart->Init.CLKLastBit;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_wwdg.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_wwdg.c
index adeac0cc3b..dffa0c3fe4 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_wwdg.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_wwdg.c
@@ -122,7 +122,6 @@
(+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_adc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_adc.c
index 5531304a30..73eb8d77ff 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_adc.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_adc.c
@@ -306,7 +306,7 @@
* - SUCCESS: ADC common registers are de-initialized
* - ERROR: not applicable
*/
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
{
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
@@ -465,11 +465,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
/* Disable ADC instance if not already disabled. */
if (LL_ADC_IsEnabled(ADCx) == 1UL)
{
- /* Set ADC group regular trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-
/* Stop potential ADC conversion on going on ADC group regular. */
if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
{
@@ -479,11 +474,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
}
}
- /* Set ADC group injected trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-
/* Stop potential ADC conversion on going on ADC group injected. */
if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
{
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_comp.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_comp.c
index 3753bd10cc..2b04dba011 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_comp.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_comp.c
@@ -15,6 +15,7 @@
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
@@ -49,26 +50,26 @@
/* COMP instance. */
#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
- ( ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \
+ (((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
)
#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
((__COMP_INSTANCE__ == COMP1) \
- ? ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ ? (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
|| ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
|| ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \
) \
- : \
- ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
- || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
- ) \
+ : \
+ (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
+ ) \
)
#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
- ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
@@ -79,29 +80,29 @@
)
#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
- ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \
+ (((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \
|| ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \
|| ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \
|| ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \
)
#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \
- ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \
+ (((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \
|| ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
)
#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
((((__COMP_INSTANCE__) == COMP1) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \
|| \
(((__COMP_INSTANCE__) == COMP2) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2))) \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2))) \
)
/**
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_crc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_crc.c
index 40ac0c55a2..7d2e081297 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_crc.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_crc.c
@@ -59,7 +59,7 @@
* - SUCCESS: CRC registers are de-initialized
* - ERROR: CRC registers are not de-initialized
*/
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx)
{
ErrorStatus status = SUCCESS;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_dac.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_dac.c
index 147eb7abf3..a2e8df135f 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_dac.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_dac.c
@@ -46,12 +46,12 @@
* @{
*/
#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \
- ( ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
- || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
+ (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
)
#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \
+ (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
@@ -66,55 +66,55 @@
)
#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
- ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+ (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
)
#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \
( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
- && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \
+ && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \
) \
||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
- && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \
+ && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \
) \
)
#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
- ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
- || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
+ (((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
+ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
)
#define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \
- ( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \
- || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
+ (((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \
+ || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
)
#define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \
- ( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \
- || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
+ (((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \
+ || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
)
/**
@@ -141,7 +141,7 @@
* - SUCCESS: DAC registers are de-initialized
* - ERROR: not applicable
*/
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(DACx));
@@ -180,12 +180,10 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
* - SUCCESS: DAC registers are initialized
* - ERROR: DAC registers are not initialized
*/
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct)
{
ErrorStatus status = SUCCESS;
- uint32_t connectOnChip;
-
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(DACx));
assert_param(IS_LL_DAC_CHANNEL(DAC_Channel));
@@ -236,25 +234,6 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
- if (DAC_InitStruct->OutputConnection == LL_DAC_OUTPUT_CONNECT_EXTERNAL)
- {
- connectOnChip = 0x00000000UL;
- }
- else if (DAC_InitStruct->OutputConnection == LL_DAC_OUTPUT_CONNECT_INTERNAL)
- {
- connectOnChip = DAC_MCR_MODE1_0;
- }
- else /* (DAC_InitStruct->OutputConnection == LL_DAC_OUTPUT_CONNECT_BOTH) */
- {
- if (DAC_InitStruct->OutputBuffer == LL_DAC_OUTPUT_BUFFER_ENABLE)
- {
- connectOnChip = DAC_MCR_MODE1_0;
- }
- else
- {
- connectOnChip = 0x00000000UL;
- }
- }
MODIFY_REG(DACx->MCR,
(DAC_MCR_MODE1_1
| DAC_MCR_MODE1_0
@@ -262,7 +241,7 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
,
(DAC_InitStruct->OutputBuffer
- | connectOnChip
+ | DAC_InitStruct->OutputConnection
| DAC_InitStruct->OutputMode
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
@@ -313,4 +292,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
*/
#endif /* USE_FULL_LL_DRIVER */
-
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_fmc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_fmc.c
index 1e20d167e7..37ccb8a184 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_fmc.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_fmc.c
@@ -58,7 +58,8 @@
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
-#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) \
+ || defined(HAL_SRAM_MODULE_ENABLED)
/** @defgroup FMC_LL FMC Low Layer
* @brief FMC driver modules
@@ -375,14 +376,15 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
assert_param(IS_FMC_NORSRAM_BANK(Bank));
/* Set FMC_NORSRAM device timing parameters */
- MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
- ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
- ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
- ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
- ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
- (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
- (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
- (Timing->AccessMode)));
+ Device->BTCR[Bank + 1U] =
+ (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) |
+ (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) |
+ (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) |
+ (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) |
+ (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) |
+ ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) |
+ ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) |
+ Timing->AccessMode;
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
@@ -602,10 +604,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
UNUSED(Bank);
/* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
- ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
- ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
- ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)));
+ Device->PMEM =(Timing->SetupTime |
+ ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
+ ((Timing->HoldSetupTime )<< FMC_PMEM_MEMHOLD_Pos) |
+ ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos));
return HAL_OK;
}
@@ -633,10 +635,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
UNUSED(Bank);
/* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
- ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
- ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
- ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)));
+ Device->PATT =(Timing->SetupTime |
+ ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
+ ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
+ ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos));
return HAL_OK;
}
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_i2c.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_i2c.c
index 2b979b93ff..9a8a0e3b0c 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_i2c.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_i2c.c
@@ -83,7 +83,7 @@
* - SUCCESS: I2C registers are de-initialized
* - ERROR: I2C registers are not de-initialized
*/
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx)
{
ErrorStatus status = SUCCESS;
@@ -139,7 +139,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
* - SUCCESS: I2C registers are initialized
* - ERROR: Not applicable
*/
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
{
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_lptim.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_lptim.c
index 0bf574182f..27ce9be31d 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_lptim.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_lptim.c
@@ -92,7 +92,7 @@
* - SUCCESS: LPTIMx registers are de-initialized
* - ERROR: invalid LPTIMx instance
*/
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
+ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx)
{
ErrorStatus result = SUCCESS;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_pka.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_pka.c
index e94999ed83..ce61417f8c 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_pka.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_pka.c
@@ -84,7 +84,7 @@
* - SUCCESS: PKA registers are de-initialized
* - ERROR: PKA registers are not de-initialized
*/
-ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx)
+ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx)
{
ErrorStatus status = SUCCESS;
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_rng.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_rng.c
index fd0e3e2150..9273728e5a 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_rng.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_rng.c
@@ -79,7 +79,7 @@
* - SUCCESS: RNG registers are de-initialized
* - ERROR: not applicable
*/
-ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
+ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx)
{
ErrorStatus status = SUCCESS;
@@ -110,7 +110,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
* - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
* - ERROR: not applicable
*/
-ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct)
{
/* Check the parameters */
assert_param(IS_RNG_ALL_INSTANCE(RNGx));
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_sdmmc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_sdmmc.c
index 97dc2ed88d..b7d27dd076 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_sdmmc.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_sdmmc.c
@@ -162,6 +162,7 @@
* @{
*/
+#if defined (SDMMC1) || defined (SDMMC2)
#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED)
/* Private typedef -----------------------------------------------------------*/
@@ -248,7 +249,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
* @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
-uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx)
{
/* Read data from Rx FIFO */
return (SDMMCx->FIFO);
@@ -335,7 +336,7 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
* - 0x02: Power UP
* - 0x03: Power ON
*/
-uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx)
{
return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
}
@@ -378,7 +379,7 @@ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef
* @param SDMMCx: Pointer to SDMMC register base
* @retval Command index of the last command response received
*/
-uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
+uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx)
{
return (uint8_t)(SDMMCx->RESPCMD);
}
@@ -395,7 +396,7 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
* @arg SDMMC_RESP4: Response Register 4
* @retval The Corresponding response register value
*/
-uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
+uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response)
{
uint32_t tmp;
@@ -451,7 +452,7 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef
* @param SDMMCx: Pointer to SDMMC register base
* @retval Number of remaining data bytes to be transferred
*/
-uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx)
{
return (SDMMCx->DCOUNT);
}
@@ -461,7 +462,7 @@ uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
* @param SDMMCx: Pointer to SDMMC register base
* @retval Data received
*/
-uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx)
{
return (SDMMCx->FIFO);
}
@@ -529,6 +530,30 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
return errorstate;
}
+/**
+ * @brief Send the Data Block number command and check the response
+ * @param SDMMCx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)BlockCount;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCK_COUNT;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCK_COUNT, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
/**
* @brief Send the Read Single Block command and check the response
* @param SDMMCx: Pointer to SDMMC register base
@@ -1635,6 +1660,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
*/
#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
/**
* @}
*/
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_tim.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_tim.c
index c68b110c35..8b0d397f63 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_tim.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_tim.c
@@ -66,8 +66,8 @@
|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+ || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
|| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
@@ -219,7 +219,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: invalid TIMx instance
*/
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
{
ErrorStatus result = SUCCESS;
@@ -729,6 +729,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T
assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
@@ -741,9 +743,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
- assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
- assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
@@ -797,8 +796,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 1: Reset the CC1E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
@@ -826,8 +823,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
@@ -876,8 +875,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
@@ -905,8 +902,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
@@ -955,8 +954,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 3: Reset the CC3E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
@@ -984,8 +981,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
@@ -1034,8 +1033,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
/* Disable the Channel 4: Reset the CC4E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
@@ -1063,7 +1060,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
/* Set the Output Idle state */
@@ -1330,7 +1326,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM
(TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
- /* Select the Polarity and set the CC2E Bit */
+ /* Select the Polarity and set the CC4E Bit */
MODIFY_REG(TIMx->CCER,
(TIM_CCER_CC4P | TIM_CCER_CC4NP),
((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_ucpd.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_ucpd.c
index db7674db85..4801cb8052 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_ucpd.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_ucpd.c
@@ -112,7 +112,7 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx)
* the configuration information for the UCPD peripheral.
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
*/
-ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
+ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct)
{
/* Check the ucpd Instance UCPDx*/
assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_usb.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_usb.c
index 91aa104523..a9eef24dc3 100644
--- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_usb.c
+++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_usb.c
@@ -172,6 +172,47 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
return HAL_OK;
}
+/**
+ * @brief USB_FlushTxFifo : Flush a Tx FIFO
+ * @param USBx : Selected device
+ * @param num : FIFO number
+ * This parameter can be a value from 1 to 15
+ 15 means Flush all Tx FIFOs
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(num);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_FlushRxFifo : Flush Rx FIFO
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+
#if defined (HAL_PCD_MODULE_ENABLED)
/**
* @brief Activate and configure an endpoint
@@ -751,7 +792,7 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
-uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
+uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx)
{
uint32_t tmpreg;
@@ -791,7 +832,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
@@ -826,7 +867,7 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = (uint32_t)wNBytes >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md
index 101a5722e8..7b5f1fe2d1 100644
--- a/system/Drivers/STM32YYxx_HAL_Driver_version.md
+++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md
@@ -14,7 +14,7 @@
* STM32L0: 1.10.6
* STM32L1: 1.4.5
* STM32L4: 1.13.4
- * STM32L5: 1.0.5
+ * STM32L5: 1.0.6
* STM32MP1: 1.6.0
* STM32U5: 1.4.0
* STM32WB: 1.14.1