From 713a020afe6f7b7c39c62262076829558d1f90ee Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 8 Apr 2024 09:23:35 +0200 Subject: [PATCH 1/6] system(H5) update STM32H5xx HAL Drivers to v1.2.0 Included in STM32CubeH5 FW v1.2.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 58 +- .../STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h | 14 +- .../Inc/stm32h5xx_hal_adc.h | 24 + .../Inc/stm32h5xx_hal_conf_template.h | 2 +- .../Inc/stm32h5xx_hal_cordic.h | 21 +- .../Inc/stm32h5xx_hal_cortex.h | 16 +- .../Inc/stm32h5xx_hal_dma.h | 11 +- .../Inc/stm32h5xx_hal_dma_ex.h | 20 +- .../Inc/stm32h5xx_hal_eth.h | 24 +- .../Inc/stm32h5xx_hal_eth_ex.h | 14 +- .../Inc/stm32h5xx_hal_exti.h | 72 ++ .../Inc/stm32h5xx_hal_flash.h | 6 +- .../Inc/stm32h5xx_hal_flash_ex.h | 88 ++- .../Inc/stm32h5xx_hal_fmac.h | 12 +- .../Inc/stm32h5xx_hal_gpio.h | 17 + .../Inc/stm32h5xx_hal_gpio_ex.h | 54 +- .../Inc/stm32h5xx_hal_gtzc.h | 8 +- .../Inc/stm32h5xx_hal_hcd.h | 12 +- .../Inc/stm32h5xx_hal_i2c.h | 2 - .../Inc/stm32h5xx_hal_i3c.h | 58 +- .../Inc/stm32h5xx_hal_irda_ex.h | 170 ++++ .../Inc/stm32h5xx_hal_lptim.h | 44 +- .../Inc/stm32h5xx_hal_nand.h | 2 +- .../Inc/stm32h5xx_hal_nor.h | 2 +- .../Inc/stm32h5xx_hal_pcd.h | 2 +- .../Inc/stm32h5xx_hal_pka.h | 17 + .../Inc/stm32h5xx_hal_pssi.h | 30 +- .../Inc/stm32h5xx_hal_pwr_ex.h | 28 +- .../Inc/stm32h5xx_hal_ramcfg.h | 8 +- .../Inc/stm32h5xx_hal_rcc.h | 1 - .../Inc/stm32h5xx_hal_rcc_ex.h | 37 +- .../Inc/stm32h5xx_hal_rng_ex.h | 38 +- .../Inc/stm32h5xx_hal_rtc.h | 97 ++- .../Inc/stm32h5xx_hal_rtc_ex.h | 138 ++-- .../Inc/stm32h5xx_hal_sdram.h | 2 +- .../Inc/stm32h5xx_hal_smartcard.h | 116 +++ .../Inc/stm32h5xx_hal_smbus.h | 2 - .../Inc/stm32h5xx_hal_sram.h | 2 +- .../Inc/stm32h5xx_hal_tim.h | 49 +- .../Inc/stm32h5xx_hal_tim_ex.h | 24 +- .../Inc/stm32h5xx_hal_uart_ex.h | 36 + .../Inc/stm32h5xx_hal_usart.h | 116 +++ .../Inc/stm32h5xx_ll_adc.h | 39 +- .../Inc/stm32h5xx_ll_bus.h | 16 +- .../Inc/stm32h5xx_ll_cordic.h | 28 +- .../Inc/stm32h5xx_ll_cortex.h | 20 +- .../Inc/stm32h5xx_ll_dac.h | 2 +- .../Inc/stm32h5xx_ll_dcache.h | 16 +- .../Inc/stm32h5xx_ll_dma.h | 70 +- .../Inc/stm32h5xx_ll_exti.h | 157 +++- .../Inc/stm32h5xx_ll_fmac.h | 6 - .../Inc/stm32h5xx_ll_fmc.h | 2 +- .../Inc/stm32h5xx_ll_gpio.h | 39 +- .../Inc/stm32h5xx_ll_i2c.h | 9 +- .../Inc/stm32h5xx_ll_icache.h | 16 +- .../Inc/stm32h5xx_ll_lpuart.h | 15 + .../Inc/stm32h5xx_ll_opamp.h | 6 - .../Inc/stm32h5xx_ll_pwr.h | 85 +- .../Inc/stm32h5xx_ll_rcc.h | 4 + .../Inc/stm32h5xx_ll_rng.h | 12 +- .../Inc/stm32h5xx_ll_rtc.h | 38 +- .../Inc/stm32h5xx_ll_spi.h | 2 +- .../Inc/stm32h5xx_ll_system.h | 14 +- .../Inc/stm32h5xx_ll_tim.h | 127 ++- .../Inc/stm32h5xx_ll_usb.h | 55 +- .../Inc/stm32h5xx_ll_utils.h | 10 + .../Inc/stm32h5xx_util_i3c.h | 6 +- system/Drivers/STM32H5xx_HAL_Driver/README.md | 28 +- .../STM32H5xx_HAL_Driver/Release_Notes.html | 195 ++++- .../STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c | 59 +- .../Src/stm32h5xx_hal_cordic.c | 10 +- .../Src/stm32h5xx_hal_cortex.c | 175 ++++- .../Src/stm32h5xx_hal_crc.c | 2 +- .../Src/stm32h5xx_hal_cryp.c | 18 +- .../Src/stm32h5xx_hal_dcache.c | 22 +- .../Src/stm32h5xx_hal_dma.c | 63 +- .../Src/stm32h5xx_hal_dma_ex.c | 24 +- .../Src/stm32h5xx_hal_eth.c | 305 ++++---- .../Src/stm32h5xx_hal_eth_ex.c | 214 +++-- .../Src/stm32h5xx_hal_fdcan.c | 4 +- .../Src/stm32h5xx_hal_flash.c | 12 + .../Src/stm32h5xx_hal_flash_ex.c | 224 +++++- .../Src/stm32h5xx_hal_fmac.c | 15 +- .../Src/stm32h5xx_hal_gpio.c | 36 +- .../Src/stm32h5xx_hal_gtzc.c | 197 ++--- .../Src/stm32h5xx_hal_hash.c | 47 +- .../Src/stm32h5xx_hal_hcd.c | 227 +++--- .../Src/stm32h5xx_hal_i2c.c | 198 +++-- .../Src/stm32h5xx_hal_i2s.c | 15 +- .../Src/stm32h5xx_hal_i3c.c | 728 +++++++++++++----- .../Src/stm32h5xx_hal_icache.c | 54 +- .../Src/stm32h5xx_hal_mmc.c | 5 - .../Src/stm32h5xx_hal_nand.c | 2 +- .../Src/stm32h5xx_hal_nor.c | 2 +- .../Src/stm32h5xx_hal_pcd.c | 17 +- .../Src/stm32h5xx_hal_pka.c | 109 ++- .../Src/stm32h5xx_hal_pssi.c | 12 +- .../Src/stm32h5xx_hal_pwr_ex.c | 48 +- .../Src/stm32h5xx_hal_ramcfg.c | 71 +- .../Src/stm32h5xx_hal_rcc.c | 6 +- .../Src/stm32h5xx_hal_rcc_ex.c | 15 +- .../Src/stm32h5xx_hal_rng.c | 4 +- .../Src/stm32h5xx_hal_rng_ex.c | 10 +- .../Src/stm32h5xx_hal_rtc.c | 30 - .../Src/stm32h5xx_hal_rtc_ex.c | 167 +--- .../Src/stm32h5xx_hal_sai.c | 8 +- .../Src/stm32h5xx_hal_sd.c | 18 +- .../Src/stm32h5xx_hal_sdram.c | 2 +- .../Src/stm32h5xx_hal_smartcard.c | 2 +- .../Src/stm32h5xx_hal_smbus.c | 7 +- .../Src/stm32h5xx_hal_smbus_ex.c | 2 + .../Src/stm32h5xx_hal_spi.c | 403 +++++----- .../Src/stm32h5xx_hal_sram.c | 2 +- .../Src/stm32h5xx_hal_tim.c | 96 +-- .../Src/stm32h5xx_hal_tim_ex.c | 98 +-- .../Src/stm32h5xx_hal_timebase_tim_template.c | 11 +- .../Src/stm32h5xx_hal_uart.c | 17 +- .../Src/stm32h5xx_hal_xspi.c | 16 +- .../Src/stm32h5xx_ll_adc.c | 10 - .../Src/stm32h5xx_ll_crs.c | 1 - .../Src/stm32h5xx_ll_dma.c | 29 +- .../Src/stm32h5xx_ll_exti.c | 2 + .../Src/stm32h5xx_ll_fmac.c | 2 - .../Src/stm32h5xx_ll_fmc.c | 35 +- .../Src/stm32h5xx_ll_rcc.c | 391 +++++----- .../Src/stm32h5xx_ll_rng.c | 2 +- .../Src/stm32h5xx_ll_spi.c | 5 +- .../Src/stm32h5xx_ll_tim.c | 34 +- .../Src/stm32h5xx_ll_usart.c | 2 +- .../Src/stm32h5xx_ll_usb.c | 72 +- .../Src/stm32h5xx_ll_utils.c | 52 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 132 files changed, 4651 insertions(+), 2328 deletions(-) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 71e35d5cf7..d10f6f6f89 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -275,7 +275,7 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -548,6 +548,16 @@ extern "C" { #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ /** * @} @@ -1239,10 +1249,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) +#if defined(STM32H5) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 */ +#endif /* STM32H5 || STM32H7RS */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1254,10 +1264,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1595,6 +1605,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1987,12 +1999,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ /** * @} @@ -2307,8 +2319,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2341,8 +2353,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2399,8 +2411,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2417,7 +2429,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -3642,8 +3654,12 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) + defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3745,8 +3761,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3892,7 +3910,7 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3929,7 +3947,8 @@ extern "C" { #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ defined (STM32H7) || \ - defined (STM32L0) || defined (STM32L1) + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG #endif @@ -4214,6 +4233,9 @@ extern "C" { #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h index 66c540f990..bfbbe410f5 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h @@ -202,8 +202,8 @@ extern HAL_TickFreqTypeDef uwTickFreq; /** @defgroup SBS_EPOCH_Selection EPOCH Selection * @{ */ -#define SBS_EPOCH_SEL_SECURE 0x0UL /*!< EPOCH secure selected */ -#define SBS_EPOCH_SEL_NONSECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH non secure selected */ +#define SBS_EPOCH_SEL_NONSECURE 0x0UL /*!< EPOCH non secure selected */ +#define SBS_EPOCH_SEL_SECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH secure selected */ #define SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */ #define IS_SBS_EPOCH_SELECTION(SELECT) (((SELECT) == SBS_EPOCH_SEL_SECURE) || \ @@ -231,9 +231,9 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @{ */ #define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */ -#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 0 */ -#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 0 */ -#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 0 */ +#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */ +#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */ +#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */ /** * @} */ @@ -278,8 +278,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define SBS_CLK SBS_SECCFGR_SBSSEC /*!< SBS clock control */ #define SBS_CLASSB SBS_SECCFGR_CLASSBSEC /*!< Class B */ #define SBS_FPU SBS_SECCFGR_FPUSEC /*!< FPU */ -#define SBS_SMPS SBS_SECCFGR_SDCE_SEC_EN /*!< SMPS */ -#define SBS_ALL (SBS_CLK | SBS_CLASSB | SBS_FPU | SBS_SMPS) /*!< All */ +#define SBS_ALL (SBS_CLK | SBS_CLASSB | SBS_FPU) /*!< All */ /** * @} */ @@ -667,7 +666,6 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define IS_SBS_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SBS_CLK) == SBS_CLK) || \ (((__ITEM__) & SBS_CLASSB) == SBS_CLASSB) || \ (((__ITEM__) & SBS_FPU) == SBS_FPU) || \ - (((__ITEM__) & SBS_SMPS) == SBS_SMPS) || \ (((__ITEM__) & ~(SBS_ALL)) == 0U)) #define IS_SBS_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SBS_SEC) ||\ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h index 1f02c328a3..2028ae1f68 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h @@ -1754,6 +1754,30 @@ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ (__ADC_DATA__),\ (__ADC_RESOLUTION__)) +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value) + * in differential ended mode. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) + /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_conf_template.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_conf_template.h index c453c736ee..b210ebe130 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_conf_template.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_conf_template.h @@ -142,7 +142,7 @@ The real value may vary depending on the variations in voltage and temperature.*/ #if !defined (LSI_STARTUP_TIME) -#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */ +#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in us */ #endif /* LSI_STARTUP_TIME */ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cordic.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cordic.h index 652621d6b9..0015bad2e5 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cordic.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cordic.h @@ -149,7 +149,6 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants * @{ @@ -166,6 +165,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + /** * @} */ @@ -183,6 +183,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ #define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ #define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ + /** * @} */ @@ -212,6 +213,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ |CORDIC_CSR_PRECISION_0)) + /** * @} */ @@ -229,6 +231,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) #define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) #define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) + /** * @} */ @@ -237,6 +240,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ + /** * @} */ @@ -245,6 +249,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ + /** * @} */ @@ -253,6 +258,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ + /** * @} */ @@ -288,6 +294,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ #define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ + /** * @} */ @@ -297,6 +304,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ #define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ + /** * @} */ @@ -305,6 +313,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ + /** * @} */ @@ -316,6 +325,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */ #define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */ #define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */ + /** * @} */ @@ -336,9 +346,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -416,7 +426,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ -/* Private macros --------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup CORDIC_Private_Macros CORDIC Private Macros * @{ */ @@ -584,6 +594,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); /* Peripheral State functions *************************************************/ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); + /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h index 10efb0483c..d6fe1ea256 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h @@ -157,7 +157,7 @@ typedef struct * @{ */ #define MPU_ACCESS_NOT_SHAREABLE 0U /*!< MPU region not shareable */ -#define MPU_ACCESS_OUTER_SHAREABLE 1U /*!< MPU region outer shareable */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< MPU region outer shareable */ #define MPU_ACCESS_INNER_SHAREABLE 3U /*!< MPU region inner shareable */ /** * @} @@ -282,6 +282,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); /* SYSTICK functions ***********************************************/ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); /** @@ -295,12 +296,16 @@ void HAL_SYSTICK_Callback(void); /* MPU functions ***********************************************/ void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit); void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* MPU_NS Control functions ***********************************************/ void HAL_MPU_Enable_NS(uint32_t MPU_Control); void HAL_MPU_Disable_NS(void); +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber); +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber); void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit); void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); #endif /* __ARM_FEATURE_CMSE */ @@ -368,6 +373,15 @@ void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const p ((NUMBER) == MPU_REGION_NUMBER9) || \ ((NUMBER) == MPU_REGION_NUMBER10)|| \ ((NUMBER) == MPU_REGION_NUMBER11)) + +#define IS_MPU_REGION_NUMBER_NS(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) #else #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ ((NUMBER) == MPU_REGION_NUMBER1) || \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h index 854dd3d17b..daa87261b6 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h @@ -663,7 +663,7 @@ typedef struct __DMA_HandleTypeDef #endif /* I3C2 */ /* Software request */ -#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ +#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ /** * @} */ @@ -807,7 +807,6 @@ typedef struct __DMA_HandleTypeDef */ - /** * @} */ @@ -1017,11 +1016,11 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co #if defined (DMA_RCFGLOCKR_LOCK0) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState); -#endif /* defined (DMA_RCFGLOCKR_LOCK0) */ +#endif /* DMA_RCFGLOCKR_LOCK0 */ /** * @} @@ -1137,12 +1136,12 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ (((INSTANCE)->SMISR & (GLOBAL_FLAG))) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ (((INSTANCE)->MISR & (GLOBAL_FLAG))) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h index 916d610f75..6c7750f911 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h @@ -150,7 +150,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t SrcSecure; /*!< Specifies the source security attribute */ uint32_t DestSecure; /*!< Specifies the destination security attribute */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ } DMA_NodeConfTypeDef; @@ -235,11 +235,9 @@ typedef struct __DMA_QListTypeDef => Left Aligned Right Truncated down to the destination data width */ #define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width - => Packed at the destination data width - (Available only for GPDMA) */ + => Packed at the destination data width */ #define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width - => Unpacked at the destination data width - (Available only for GPDMA) */ + => Unpacked at the destination data width */ /** * @} */ @@ -345,9 +343,9 @@ typedef struct __DMA_QListTypeDef #if defined (COMP1) #define GPDMA1_TRIGGER_COMP1_OUT 44U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ #endif /* COMP1 */ -#if defined (STM32H503xx) -#define GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ -#endif /* STM32H503xx */ +#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx) +#define GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is EVENTOUT */ +#endif /* STM32H503xx || STM32H523xx || STM32H533xx */ /* GPDMA2 triggers */ #define GPDMA2_TRIGGER_EXTI_LINE0 0U /*!< GPDMA2 HW Trigger signal is EXTI_LINE0 */ @@ -409,9 +407,9 @@ typedef struct __DMA_QListTypeDef #if defined (COMP1) #define GPDMA2_TRIGGER_COMP1_OUT 44U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */ #endif /* COMP1 */ -#if defined (STM32H503xx) -#define GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */ -#endif /* STM32H503xx */ +#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx) +#define GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is EVENTOUT */ +#endif /* STM32H503xx || STM32H523xx || STM32H533xx */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h index 7cab4dab15..c32b34c6ac 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h @@ -24,7 +24,6 @@ extern "C" { #endif - /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_hal_def.h" @@ -160,7 +159,7 @@ typedef struct void *pData; /*!< Specifies Application packet pointer to save */ -} ETH_TxPacketConfig; +} ETH_TxPacketConfigTypeDef; /** * */ @@ -792,7 +791,6 @@ typedef struct #define ETH_DMATXNDESCWBF_DB 0x00000002U /*!< Deferred Bit */ #define ETH_DMATXNDESCWBF_IHE 0x00000004U /*!< IP Header Error */ - /* DMA Tx Context Descriptor ----------------------------------------------------------------------------------------------- @@ -843,7 +841,6 @@ typedef struct * @} */ - /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition * @{ */ @@ -942,7 +939,6 @@ typedef struct #define ETH_DMARXNDESCWBF_VF 0x00008000U /*!< VLAN Filter Status */ #define ETH_DMARXNDESCWBF_ARPNR 0x00000400U /*!< ARP Reply Not Generated */ - /** * @brief Bit definition of Rx normal descriptor register 3 write back format */ @@ -1487,11 +1483,12 @@ typedef struct /** @defgroup ETH_PTP_Config_Status ETH PTP Config Status * @{ */ -#define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */ -#define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */ +#define HAL_ETH_PTP_NOT_CONFIGURED 0x00000000U /*!< ETH PTP Configuration not done */ +#define HAL_ETH_PTP_CONFIGURED 0x00000001U /*!< ETH PTP Configuration done */ /** * @} */ + /** * @} */ @@ -1632,7 +1629,6 @@ typedef struct */ #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->RPR2 = (__EXTI_LINE__)) - /** * @brief enable rising edge interrupt on selected EXTI line. * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. @@ -1719,7 +1715,7 @@ HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode); +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode); HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); @@ -1738,8 +1734,8 @@ HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_tx HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); #endif /* HAL_ETH_USE_PTP */ -HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); -HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout); +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig); HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue); @@ -1766,8 +1762,8 @@ void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *ti */ /* Peripheral Control functions **********************************************/ /* MAC & DMA Configuration APIs **********************************************/ -HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); -HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); @@ -1777,7 +1773,7 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t uint32_t VLANIdentifier); /* MAC L2 Packet Filtering APIs **********************************************/ -HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig); HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth_ex.h index b532d26f3f..397ec092fc 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth_ex.h @@ -314,25 +314,25 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t /* MAC L3 L4 Filtering APIs ***************************************************/ void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth); void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, +HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig); -HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, +HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig); HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, - ETH_L3FilterConfigTypeDef *pL3FilterConfig); + const ETH_L3FilterConfigTypeDef *pL3FilterConfig); HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, - ETH_L4FilterConfigTypeDef *pL4FilterConfig); + const ETH_L4FilterConfigTypeDef *pL4FilterConfig); /* MAC VLAN Processing APIs ************************************************/ void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth); void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); +HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable); -HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, +HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag, ETH_TxVLANConfigTypeDef *pVlanConfig); HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, - ETH_TxVLANConfigTypeDef *pVlanConfig); + const ETH_TxVLANConfigTypeDef *pVlanConfig); void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier); /* Energy Efficient Ethernet APIs *********************************************/ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h index 0751486d77..f08c45ee75 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h @@ -105,48 +105,89 @@ typedef struct #define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU) #define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U) #define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | 0x11U) +#if defined(EXTI_IMR1_IM18) #define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12U) +#endif /* EXTI_IMR1_IM18 */ #define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13U) +#if defined(EXTI_IMR1_IM20) #define EXTI_LINE_20 (EXTI_DIRECT | EXTI_REG1 | 0x14U) +#endif /* EXTI_IMR1_IM20 */ #define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15U) #define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16U) +#if defined(EXTI_IMR1_IM23) #define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17U) +#endif /* EXTI_IMR1_IM23 */ #define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18U) #define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19U) #define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1AU) #define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1BU) #define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1CU) #define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1DU) +#if defined(EXTI_IMR1_IM30) #define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1EU) +#endif /* EXTI_IMR1_IM30 */ #define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1FU) +#if defined(EXTI_IMR2_IM32) #define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00U) +#endif /* EXTI_IMR2_IM32 */ +#if defined(EXTI_IMR2_IM33) #define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01U) +#endif /* EXTI_IMR2_IM33 */ +#if defined(EXTI_IMR2_IM34) #define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02U) +#endif /* EXTI_IMR2_IM34 */ +#if defined(EXTI_IMR2_IM35) #define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03U) +#endif /* EXTI_IMR2_IM35 */ +#if defined(EXTI_IMR2_IM36) #define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04U) +#endif /* EXTI_IMR2_IM36 */ #define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05U) #define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06U) #define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07U) #define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | 0x08U) #define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | 0x09U) #define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0AU) +#if defined(EXTI_IMR2_IM43) #define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0BU) +#endif /* EXTI_IMR2_IM43 */ +#if defined(EXTI_IMR2_IM44) #define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0CU) +#endif /* EXTI_IMR2_IM44 */ +#if defined(EXTI_IMR2_IM45) +#endif /* EXTI_IMR2_IM45 */ #define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0DU) #if defined(ETH) #define EXTI_LINE_46 (EXTI_CONFIG | EXTI_REG2 | 0x0EU) #endif /* ETH */ #define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | 0x0FU) +#if defined(EXTI_IMR2_IM48) #define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10U) +#endif /* EXTI_IMR2_IM48 */ #define EXTI_LINE_49 (EXTI_DIRECT | EXTI_REG2 | 0x11U) #define EXTI_LINE_50 (EXTI_CONFIG | EXTI_REG2 | 0x12U) +#if defined(EXTI_IMR2_IM51) #define EXTI_LINE_51 (EXTI_DIRECT | EXTI_REG2 | 0x13U) +#endif /* EXTI_IMR2_IM51 */ +#if defined(EXTI_IMR2_IM52) #define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | 0x14U) +#endif /* EXTI_IMR2_IM52 */ #define EXTI_LINE_53 (EXTI_CONFIG | EXTI_REG2 | 0x15U) +#if defined(EXTI_IMR2_IM54) #define EXTI_LINE_54 (EXTI_DIRECT | EXTI_REG2 | 0x16U) +#endif /* EXTI_IMR2_IM54 */ +#if defined(EXTI_IMR2_IM55) #define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | 0x17U) +#endif /* EXTI_IMR2_IM55 */ +#if defined(EXTI_IMR2_IM56) #define EXTI_LINE_56 (EXTI_DIRECT | EXTI_REG2 | 0x18U) +#endif /* EXTI_IMR2_IM56 */ +#if defined(EXTI_IMR2_IM57) #define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | 0x19U) +#endif /* EXTI_IMR2_IM57 */ +#if defined(EXTI_IMR2_IM58) +#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | 0x1AU) +#endif /* EXTI_IMR2_IM58 */ /** * @} @@ -181,11 +222,19 @@ typedef struct #define EXTI_GPIOB 0x00000001U #define EXTI_GPIOC 0x00000002U #define EXTI_GPIOD 0x00000003U +#if defined(GPIOE) #define EXTI_GPIOE 0x00000004U +#endif /* GPIOE */ +#if defined(GPIOF) #define EXTI_GPIOF 0x00000005U +#endif /* GPIOF */ +#if defined(GPIOG) #define EXTI_GPIOG 0x00000006U +#endif /* GPIOG */ #define EXTI_GPIOH 0x00000007U +#if defined(GPIOI) #define EXTI_GPIOI 0x00000008U +#endif /* GPIOI */ /** * @} */ @@ -271,7 +320,13 @@ typedef struct /** * @brief EXTI Line number */ +#if defined(EXTI_IMR2_IM58) +#define EXTI_LINE_NB 59U +#elif defined(EXTI_IMR2_IM57) #define EXTI_LINE_NB 58U +#else +#define EXTI_LINE_NB 54U +#endif /* EXTI_IMR2_IM58 */ /** * @brief EXTI Mask for secure & privilege attributes @@ -304,6 +359,7 @@ typedef struct #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) +#if defined(GPIOI) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ @@ -313,6 +369,22 @@ typedef struct ((__PORT__) == EXTI_GPIOG) || \ ((__PORT__) == EXTI_GPIOH) || \ ((__PORT__) == EXTI_GPIOI)) +#elif defined(GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOH)) +#endif /* GPIOI */ #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h index b3d937d341..1849b6dcfd 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h @@ -251,7 +251,7 @@ typedef struct #define FLASH_SECTOR_5 5U /*!< Sector Number 5 */ #define FLASH_SECTOR_6 6U /*!< Sector Number 6 */ #define FLASH_SECTOR_7 7U /*!< Sector Number 7 */ -#if (FLASH_SECTOR_NB == 128) +#if (FLASH_SECTOR_NB >= 32) #define FLASH_SECTOR_8 8U /*!< Sector Number 8 */ #define FLASH_SECTOR_9 9U /*!< Sector Number 9 */ #define FLASH_SECTOR_10 10U /*!< Sector Number 10 */ @@ -276,6 +276,8 @@ typedef struct #define FLASH_SECTOR_29 29U /*!< Sector Number 29 */ #define FLASH_SECTOR_30 30U /*!< Sector Number 30 */ #define FLASH_SECTOR_31 31U /*!< Sector Number 31 */ +#endif /* (FLASH_SECTOR_NB >= 32) */ +#if (FLASH_SECTOR_NB >= 128) #define FLASH_SECTOR_32 32U /*!< Sector Number 32 */ #define FLASH_SECTOR_33 33U /*!< Sector Number 33 */ #define FLASH_SECTOR_34 34U /*!< Sector Number 34 */ @@ -372,7 +374,7 @@ typedef struct #define FLASH_SECTOR_125 125U /*!< Sector Number 125 */ #define FLASH_SECTOR_126 126U /*!< Sector Number 126 */ #define FLASH_SECTOR_127 127U /*!< Sector Number 127 */ -#endif /* (FLASH_SECTOR_NB == 128) */ +#endif /* (FLASH_SECTOR_NB >= 128) */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h index 17e1bf094e..6968de725b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h @@ -89,7 +89,7 @@ typedef struct @ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_BKPRAM_ECC, @ref FLASH_OB_USER_SRAM3_ECC, @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM1_RST, @ref FLASH_OB_USER_SRAM1_ECC, - @ref FLASH_OB_USER_TZEN */ + @ref FLASH_OB_USER_USBPD_DIS, @ref FLASH_OB_USER_TZEN */ uint32_t Banks; /*!< Select banks for WRP , HDP and secure area configuration. This parameter must be a value of @ref FLASH_Banks */ @@ -171,6 +171,19 @@ typedef struct This parameter can be a value between 1 and max number of sectors in the bank */ } FLASH_HDPExtensionTypeDef; +/** + * @brief ECC Info Structure definition + */ +typedef struct +{ + uint32_t Area; /*!< Area from which an ECC was detected. + This parameter can be a value of @ref FLASHEx_ECC_Area */ + + uint32_t Address; /*!< ECC error address */ + + uint32_t Data; /*!< ECC failing data */ +} FLASH_EccInfoTypeDef; + /** * @} */ @@ -206,6 +219,25 @@ typedef struct activation */ #endif /* FLASH_SR_OBKERR */ #endif /* __ARM_FEATURE_CMSE */ + +/** @defgroup FLASH_ECC_Area FLASH ECC Area + * @brief FLASH ECC Area + * @{ + */ +#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */ +#define FLASH_ECC_AREA_USER_BANK2 FLASH_ECCR_BK_ECC /*!< FLASH bank 2 area */ +#define FLASH_ECC_AREA_SYSTEM FLASH_ECCR_SYSF_ECC /*!< System FLASH area */ +#if defined (FLASH_SR_OBKERR) +#define FLASH_ECC_AREA_OBK FLASH_ECCR_OBK_ECC /*!< FLASH OBK area */ +#endif /* FLASH_SR_OBKERR */ +#define FLASH_ECC_AREA_OTP FLASH_ECCR_OTP_ECC /*!< FLASH OTP area */ +#if defined (FLASH_EDATAR_EDATA_EN) +#define FLASH_ECC_AREA_EDATA FLASH_ECCR_DATA_ECC /*!< FLASH high-cycle data area */ +#endif /* FLASH_EDATAR_EDATA_EN */ +/** + * @} + */ + /** * @} */ @@ -276,24 +308,28 @@ byte configuration */ #define OB_USER_SRAM3_ECC 0x00008000U /*!< SRAM3 ECC detection and correction enable */ #define OB_USER_SRAM2_ECC 0x00010000U /*!< SRAM2 ECC detection and correction enable */ #define OB_USER_SRAM1_ECC 0x00020000U /*!< SRAM1 ECC detection and correction enable */ +#if defined (FLASH_OPTSR2_USBPD_DIS) +#define OB_USER_USBPD_DIS 0x00040000U /*!< USB power delivery configuration enable */ +#endif /*FLASH_OPTSR2_USBPD_DIS*/ #if defined (FLASH_OPTSR2_TZEN) #define OB_USER_TZEN 0x00080000U /*!< Global TrustZone security enable */ #endif /* FLASH_OPTSR2_TZEN */ -#if defined (FLASH_OPTSR2_SRAM1_3_RST) && defined (FLASH_OPTSR_BOOT_UBE) +#if defined (FLASH_OPTSR2_SRAM1_3_RST) && defined (FLASH_OPTSR_BOOT_UBE) && defined (FLASH_OPTSR2_USBPD_DIS) #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ OB_USER_IWDG_STDBY | OB_USER_BOOT_UBE | OB_USER_SWAP_BANK |\ OB_USER_SRAM1_3_RST | OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC |\ - OB_USER_SRAM3_ECC | OB_USER_SRAM2_ECC | OB_USER_TZEN) + OB_USER_SRAM3_ECC | OB_USER_SRAM2_ECC | OB_USER_USBPD_DIS |\ + OB_USER_TZEN) #else #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ OB_USER_IWDG_STDBY | OB_USER_SWAP_BANK | OB_USER_SRAM1_RST |\ OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC | OB_USER_SRAM3_ECC |\ - OB_USER_SRAM2_ECC | OB_USER_SRAM1_ECC) + OB_USER_SRAM2_ECC | OB_USER_SRAM1_ECC) #endif /* FLASH_OPTSR2_SRAM1_3_RST && FLASH_OPTSR_BOOT_UBE */ /** * @} @@ -302,9 +338,9 @@ byte configuration */ /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH BOR Reset Level * @{ */ -#define OB_BOR_LEVEL_1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level 1 threshold */ -#define OB_BOR_LEVEL_2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level 2 threshold */ -#define OB_BOR_LEVEL_3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level 3 threshold */ +#define OB_BOR_LEVEL_1 0U /*!< Reset level 1 threshold */ +#define OB_BOR_LEVEL_2 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level 2 threshold */ +#define OB_BOR_LEVEL_3 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level 3 threshold */ /** * @} */ @@ -500,6 +536,16 @@ byte configuration */ * @} */ +/** @defgroup OB_USER_USBPD_DIS FLASH Option Bytes USB power delivery configuration + * @{ + */ +#if defined (FLASH_OPTSR2_USBPD_DIS) +#define OB_USBPD_DIS_ENABLE 0x00000000U /*!< USB power delivery check enable */ +#define OB_USBPD_DIS_DISABLE FLASH_OPTSR2_USBPD_DIS /*!< USB power delivery check disable */ +#endif /* FLASH_OPTSR2_USBPD_DIS */ +/** + * @} + */ /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes Global TrustZone * @{ */ @@ -558,6 +604,16 @@ byte configuration */ #define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ #define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ #define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ +#elif (FLASH_SECTOR_NB == 32) +#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ +#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ +#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ +#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ +#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ +#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ +#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ +#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ +#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ #else #define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ #define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ @@ -835,6 +891,19 @@ HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef * @} */ +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group3 + * @{ + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void); +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void); +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData); +void HAL_FLASHEx_ECCD_IRQHandler(void); +__weak void HAL_FLASHEx_EccDetectionCallback(void); +__weak void HAL_FLASHEx_EccCorrectionCallback(void); /** * @} */ @@ -845,6 +914,8 @@ HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef * @{ */ #define FLASH_TYPEPROGRAM_OB (0x00008000U | FLASH_NON_SECURE_MASK) /*!< Program Option Bytes operation type */ +#define FLASH_ADDRESS_OFFSET_OTP (0x00000600U) /*!< Flash address offset of OTP area */ +#define FLASH_ADDRESS_OFFSET_EDATA (0x0000F000U) /*!< Flash address offset of EDATA area */ /** * @} */ @@ -937,6 +1008,9 @@ HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef #define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE)) +#if defined(FLASH_OPTSR2_USBPD_DIS) +#define IS_OB_USER_USBPD_DIS(VALUE) (((VALUE) == OB_USBPD_DIS_ENABLE) || ((VALUE) == OB_USBPD_DIS_DISABLE)) +#endif /* FLASH_OPTSR2_USBPD_DIS */ #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) #define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fmac.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fmac.h index 21881e79c5..b42dc45ab1 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fmac.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fmac.h @@ -243,10 +243,7 @@ typedef struct * @} */ - /* Exported constants --------------------------------------------------------*/ - - /** @defgroup FMAC_Exported_Constants FMAC Exported Constants * @{ */ @@ -357,7 +354,6 @@ typedef struct * @} */ - /* Exported variables --------------------------------------------------------*/ /** @defgroup FMAC_Exported_variables FMAC Exported variables * @{ @@ -499,7 +495,7 @@ typedef struct * @} */ -/* Private Macros-----------------------------------------------------------*/ +/* Private Macros-------------------------------------------------------------*/ /** @addtogroup FMAC_Private_Macros FMAC Private Macros * @{ */ @@ -578,9 +574,9 @@ typedef struct * @param __FUNCTION__ ID of the filter function. * @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid) */ -#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ - (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ - (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) +#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX)))) /** * @brief Verify the FMAC filter parameter R. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h index a139c5391f..b41cccfaf1 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h @@ -278,6 +278,23 @@ typedef enum #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\ + ((__PIN__) == GPIO_PIN_1) ||\ + ((__PIN__) == GPIO_PIN_2) ||\ + ((__PIN__) == GPIO_PIN_3) ||\ + ((__PIN__) == GPIO_PIN_4) ||\ + ((__PIN__) == GPIO_PIN_5) ||\ + ((__PIN__) == GPIO_PIN_6) ||\ + ((__PIN__) == GPIO_PIN_7) ||\ + ((__PIN__) == GPIO_PIN_8) ||\ + ((__PIN__) == GPIO_PIN_9) ||\ + ((__PIN__) == GPIO_PIN_10) ||\ + ((__PIN__) == GPIO_PIN_11) ||\ + ((__PIN__) == GPIO_PIN_12) ||\ + ((__PIN__) == GPIO_PIN_13) ||\ + ((__PIN__) == GPIO_PIN_14) ||\ + ((__PIN__) == GPIO_PIN_15)) + #define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h index 3e3bd18574..10fe04f3d7 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h @@ -68,9 +68,9 @@ extern "C" { #if defined(TIM17) #define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ #endif /* TIM17 */ -#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx)) +#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx) #define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */ +#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */ /** * @brief AF 2 selection @@ -91,6 +91,9 @@ extern "C" { #if defined(TIM5) #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ #endif /* TIM5 */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ #if defined(TIM12) #define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */ #endif /* TIM12 */ @@ -112,9 +115,9 @@ extern "C" { #if defined(OCTOSPI1) #define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */ #endif /* OCTOSPI1 */ -#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx)) +#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx) #define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */ -#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */ +#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */ #if defined(TIM8) #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #endif /* TIM8 */ @@ -140,6 +143,9 @@ extern "C" { #define GPIO_AF4_LPTIM1 ((uint8_t)0x04) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */ #define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF4_SPI3 ((uint8_t)0x04) /* SPI3 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ #if defined(TIM15) #define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */ #endif /* TIM15 */ @@ -154,10 +160,10 @@ extern "C" { #if defined(CEC) #define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */ #endif /* CEC */ -#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx)) +#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx) #define GPIO_AF5_I3C1 ((uint8_t)0x05) /* I3C1 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ -#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */ +#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */ #define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ @@ -183,10 +189,10 @@ extern "C" { #if defined(SAI1) #define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ #endif /* SAI1 */ -#if defined(STM32H503xx) +#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx)) #define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ #define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ -#endif /* STM32H503xx */ +#endif /* STM32H503xx || STM32H533xx || STM32H523xx */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ #if defined(SPI4) #define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */ @@ -194,6 +200,9 @@ extern "C" { #if defined(UART4) #define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ #endif /* UART4 */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF6_USART6 ((uint8_t)0x06) /* USART6 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ #if defined(UART12) #define GPIO_AF6_UART12 ((uint8_t)0x06) /* UART12 Alternate Function mapping */ #endif /* UART12 */ @@ -291,6 +300,10 @@ extern "C" { #define GPIO_AF9_USART2 ((uint8_t)0x09) /* USART2 Alternate Function mapping */ #define GPIO_AF9_USART3 ((uint8_t)0x09) /* USART3 Alternate Function mapping */ #endif /* STM32H503xx */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ +#define GPIO_AF9_I3C2 ((uint8_t)0x09) /* I3C2 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ /** * @brief AF 10 selection @@ -298,9 +311,11 @@ extern "C" { #define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */ #if defined(STM32H503xx) #define GPIO_AF10_I3C1 ((uint8_t)0x0A) /* I3C1 Alternate Function mapping */ -#define GPIO_AF10_I3C2 ((uint8_t)0x0A) /* I3C2 Alternate Function mapping */ #define GPIO_AF10_SPI3 ((uint8_t)0x0A) /* SPI3 Alternate Function mapping */ #endif /* STM32H503xx */ +#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF10_I3C2 ((uint8_t)0x0A) /* I3C2 Alternate Function mapping */ +#endif /* STM32H503xx || STM32H533xx || STM32H523xx */ #if defined(FMC_BANK1) #define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */ #endif /* FMC_BANK1 */ @@ -310,6 +325,9 @@ extern "C" { #if defined(SAI2) #define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ #endif /* SAI2 */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF10_SDMMC1 ((uint8_t)0x0A) /* SDMMC1 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ #if defined(SDMMC2) #define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */ #endif /* SDMMC2 */ @@ -330,6 +348,9 @@ extern "C" { #if defined(OCTOSPI1) #define GPIO_AF11_OCTOSPI1 ((uint8_t)0x0B) /* OCTOSPI1 Alternate Function mapping */ #endif /* OCTOSPI1 */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF11_SDMMC1 ((uint8_t)0x0B) /* SDMMC1 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ #if defined(SDMMC2) #define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ #endif /* SDMMC2 */ @@ -403,12 +424,15 @@ extern "C" { #if defined(LPTIM6) #define GPIO_AF14_LPTIM6 ((uint8_t)0x0E) /* LPTIM6 Alternate Function mapping */ #endif /* LPTIM6 */ -#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx)) +#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx) #define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */ +#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */ #if defined(UART5) #define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */ #endif /* UART5 */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF14_USART6 ((uint8_t)0x0E) /* USART6 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ /** * @brief AF 15 selection @@ -438,11 +462,11 @@ extern "C" { /* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */ -#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H503xx)) +#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \ + defined(STM32H523xx) || defined(STM32H503xx) #define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10) -#endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H503xx)) */ - - +#endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \ + defined(STM32H523xx) || defined(STM32H503xx)) */ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gtzc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gtzc.h index 86c29d9248..a8eab08f03 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gtzc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gtzc.h @@ -147,10 +147,10 @@ typedef struct /** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values * @{ */ - +#if defined(GTZC_MPCBB_CR_SRWILADIS_Pos) #define GTZC_MPCBB_SRWILADIS_ENABLE (0U) #define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) - +#endif /* GTZC_MPCBB_CR_SRWILADIS_Pos */ /** * @} */ @@ -158,10 +158,10 @@ typedef struct /** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values * @{ */ - +#if defined(GTZC_MPCBB_CR_INVSECSTATE_Pos) #define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) #define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) - +#endif /* GTZC_MPCBB_CR_INVSECSTATE_Pos */ /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hcd.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hcd.h index e2854aa655..c73f5e17b8 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hcd.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hcd.h @@ -359,12 +359,15 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); /** @defgroup HCD_ENDP_Kind HCD Endpoint Kind * @{ */ -#define HCD_SNG_BUF 0U -#define HCD_DBL_BUF 1U +#define HCD_SNG_BUF 0U +#define HCD_DBL_BUF 1U /** * @} */ +/* Powerdown exit count */ +#define HCD_PDWN_EXIT_CNT 0x100U + /* Set Channel */ #define HCD_SET_CHANNEL USB_DRD_SET_CHEP @@ -495,15 +498,16 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); __STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum) { uint32_t HostCoreSpeed; + uint32_t ep_reg = USB_DRD_GET_CHEP(Instance, bChNum); __IO uint32_t count = 10U; /* Get Host core Speed */ HostCoreSpeed = USB_GetHostSpeed(Instance); /* Count depends on device LS */ - if (HostCoreSpeed == USB_DRD_SPEED_LS) + if ((HostCoreSpeed == USB_DRD_SPEED_LS) || ((ep_reg & USB_CHEP_LSEP) == USB_CHEP_LSEP)) { - count = (63U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U; + count = (70U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U; } if (count > 15U) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h index 692d125dcc..49d262e582 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h @@ -118,8 +118,6 @@ typedef enum HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h index 1d2fdeccad..a1265e942d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i3c.h @@ -338,6 +338,56 @@ typedef struct * @} */ +/** @defgroup I3C_BCRTypeDef_Structure_definition I3C BCRTypeDef Structure definition + * @brief I3C BCRTypeDef Structure definition + * @{ + */ +typedef struct +{ + FunctionalState MaxDataSpeedLimitation; /*!< Max data speed limitation */ + FunctionalState IBIRequestCapable; /*!< IBI request capable */ + FunctionalState IBIPayload; /*!< IBI payload data */ + FunctionalState OfflineCapable; /*!< Offline capable */ + FunctionalState VirtualTargetSupport; /*!< Virtual target support */ + FunctionalState AdvancedCapabilities; /*!< Advanced capabilities */ + FunctionalState DeviceRole; /*!< Device role */ + +} I3C_BCRTypeDef; +/** + * @} + */ + +/** @defgroup I3C_PIDTypeDef_Structure_definition I3C PIDTypeDef Structure definition + * @brief I3C_PIDTypeDef Structure definition + * @{ + */ +typedef struct +{ + uint16_t MIPIMID; /*!< MIPI Manufacturer ID */ + uint8_t IDTSEL; /*!< Provisioned ID Type Selector */ + uint16_t PartID; /*!< Part ID device vendor to define */ + uint8_t MIPIID; /*!< Instance ID */ + +} I3C_PIDTypeDef; +/** + * @} + */ + +/** @defgroup I3C_ENTDAAPayloadTypeDef_Structure_definition I3C ENTDAAPayloadTypeDef Structure definition + * @brief I3C ENTDAAPayloadTypeDef Structure definition + * @{ + */ +typedef struct +{ + I3C_BCRTypeDef BCR; /*!< Bus Characteristics Register */ + uint32_t DCR; /*!< Device Characteristics Register */ + I3C_PIDTypeDef PID; /*!< Provisioned ID */ + +} I3C_ENTDAAPayloadTypeDef; +/** + * @} + */ + /** @defgroup I3C_PrivateTypeDef_Structure_definition I3C PrivateTypeDef Structure definition * @brief I3C PrivateTypeDef Structure definition * @{ @@ -419,8 +469,7 @@ typedef struct __I3C_HandleTypeDef __IO uint32_t ErrorCode; /*!< I3C Error code */ HAL_StatusTypeDef(*XferISR)(struct __I3C_HandleTypeDef *hi3c, - uint32_t itFlags, - uint32_t itSources); /*!< I3C transfer IRQ handler function pointer */ + uint32_t itMasks); /*!< I3C transfer IRQ handler function pointer */ void(*ptrTxFunc)(struct __I3C_HandleTypeDef *hi3c); /*!< I3C transmit function pointer */ @@ -914,7 +963,7 @@ typedef void (*pI3C_TgtReqDynamicAddrCallbackTypeDef)(I3C_HandleTypeDef *hi3c, /** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD * @{ */ -#define HAL_I3C_BCR_IN_PAYLOAD_SHIFT 48 /*!< BCR field in target payload */ +#define HAL_I3C_BCR_IN_PAYLOAD_SHIFT 48 /*!< BCR field in target payload */ /** * @} */ @@ -1193,6 +1242,9 @@ uint32_t HAL_I3C_GetError(const I3C_HandleTypeDef *hi3c); HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c, uint32_t notifyId, I3C_CCCInfoTypeDef *pCCCInfo); +HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c, + uint64_t ENTDAA_payload, + I3C_ENTDAAPayloadTypeDef *pENTDAA_payload); /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_irda_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_irda_ex.h index 6eb66d5ac5..7cb4b1f497 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_irda_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_irda_ex.h @@ -401,6 +401,176 @@ extern "C" { (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#elif (defined(STM32H523xx) || defined(STM32H533xx)) +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART2CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART3CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + case RCC_UART4CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_UART4CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ + case RCC_UART5CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART5CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART5CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART5CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + case RCC_UART5CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_UART5CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART6CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART6CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) #else #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h index 1b44d0d088..228003eb58 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_lptim.h @@ -1125,7 +1125,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_LPTIM1_CH2)))) -#else +#elif defined(LPTIM3) && defined(LPTIM4) && defined(LPTIM5) && defined(LPTIM6) #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ ((((__INSTANCE__) == LPTIM1) || \ ((__INSTANCE__) == LPTIM2) || \ @@ -1134,6 +1134,11 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); ((__INSTANCE__) == LPTIM5) || \ ((__INSTANCE__) == LPTIM6)) && \ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO))) +#else +#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO))) #endif /* STM32H503xx */ #if defined(STM32H503xx) @@ -1141,7 +1146,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); ((((__INSTANCE__) == LPTIM1) || \ ((__INSTANCE__) == LPTIM2)) && \ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO))) -#else +#elif defined(LPTIM3) && defined(LPTIM5) && defined(LPTIM6) #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ ((((__INSTANCE__) == LPTIM1) || \ ((__INSTANCE__) == LPTIM2) || \ @@ -1149,6 +1154,11 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); ((__INSTANCE__) == LPTIM5) || \ ((__INSTANCE__) == LPTIM6)) && \ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO))) +#else +#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO))) #endif /* STM32H503xx */ #if defined(STM32H503xx) @@ -1177,7 +1187,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); ((__SOURCE__) == LPTIM_IC2SOURCE_HSI_1024) || \ ((__SOURCE__) == LPTIM_IC2SOURCE_CSI_128) || \ ((__SOURCE__) == LPTIM_IC2SOURCE_HSI_8)))) -#else +#elif defined(LPTIM3) && defined(LPTIM5) && defined(LPTIM6) #define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \ ((((__INSTANCE__) == LPTIM1) || \ ((__INSTANCE__) == LPTIM2) || \ @@ -1206,6 +1216,23 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); || \ (((__INSTANCE__) == LPTIM6) && \ ((__SOURCE__) == LPTIM_IC2SOURCE_GPIO))) +#else +#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO))) + +#define IS_LPTIM_IC2_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_LSI) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_LSE))) \ + || \ + (((__INSTANCE__) == LPTIM2) && \ + (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_HSI_1024) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_CSI_128) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_HSI_8)))) #endif /* STM32H503xx */ #define LPTIM_CHANNEL_STATE_GET(__INSTANCE__, __CHANNEL__)\ @@ -1232,7 +1259,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); (((__INSTANCE__) == LPTIM2_NS) && \ (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ ((__CHANNEL__) == LPTIM_CHANNEL_2)))) -#else +#elif defined(LPTIM3) && defined(LPTIM4) && defined(LPTIM5) && defined(LPTIM6) #define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \ (((((__INSTANCE__) == LPTIM1_NS) || ((__INSTANCE__) == LPTIM1_S)) && \ (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ @@ -1256,6 +1283,15 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); ((((__INSTANCE__) == LPTIM6_NS) || ((__INSTANCE__) == LPTIM6_S)) && \ (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ ((__CHANNEL__) == LPTIM_CHANNEL_2)))) +#else +#define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \ + (((((__INSTANCE__) == LPTIM1_NS) || ((__INSTANCE__) == LPTIM1_S)) && \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ + ((__CHANNEL__) == LPTIM_CHANNEL_2))) \ + || \ + ((((__INSTANCE__) == LPTIM2_NS) || ((__INSTANCE__) == LPTIM2_S)) && \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ + ((__CHANNEL__) == LPTIM_CHANNEL_2)))) #endif /* STM32H503xx */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h index 7b9b067abf..8f3fc4e219 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nand.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nor.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nor.h index 98b2ff9d11..c3ffb15c48 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nor.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_nor.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h index 244606938b..ca798235ae 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h @@ -330,7 +330,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h index 92396b00fa..a96befc261 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h @@ -147,6 +147,21 @@ typedef struct const uint8_t *primeOrder; /*!< pointer to order of the curve */ } PKA_ECCMulInTypeDef; +typedef struct +{ + uint32_t primeOrderSize; /*!< Number of element in primeOrder array */ + uint32_t scalarMulSize; /*!< Number of element in scalarMul array */ + uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< pointer to curve coefficient b */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ + const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */ + const uint8_t *primeOrder; /*!< pointer to order of the curve */ +} PKA_ECCMulExInTypeDef; + typedef struct { uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */ @@ -572,6 +587,8 @@ uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka); HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout); HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out); HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pssi.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pssi.h index c4d22a4ddf..a8225efc42 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pssi.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pssi.h @@ -53,12 +53,18 @@ extern "C" { */ typedef struct { - uint32_t DataWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */ - uint32_t BusWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */ - uint32_t ControlSignal; /* !< Configures Data enable and Data ready */ - uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity */ - uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */ - uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity */ + uint32_t DataWidth; /* !< Configures the data width. + This parameter can be a value of @ref PSSI_DATA_WIDTH. */ + uint32_t BusWidth; /* !< Configures the parallel bus width. + This parameter can be a value of @ref PSSI_BUS_WIDTH. */ + uint32_t ControlSignal; /* !< Configures Data enable and Data ready. + This parameter can be a value of @ref ControlSignal_Configuration. */ + uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity. + This parameter can be a value of @ref Clock_Polarity. */ + uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity. + This parameter can be a value of @ref Data_Enable_Polarity. */ + uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity. + This parameter can be a value of @ref Ready_Polarity. */ } PSSI_InitTypeDef; @@ -216,7 +222,7 @@ typedef enum /** * @} */ -/** @defgroup Reday_Polarity Reday Polarity +/** @defgroup Ready_Polarity Ready Polarity * @{ */ #define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */ @@ -230,8 +236,6 @@ typedef enum */ #define HAL_PSSI_FALLING_EDGE 0x0U /*!< Fallling Edge */ #define HAL_PSSI_RISING_EDGE 0x1U /*!< Rising Edge */ - - /** * @} */ @@ -257,7 +261,6 @@ typedef enum #define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/ - /** * @} */ @@ -274,7 +277,6 @@ typedef enum */ - /** * @} */ @@ -325,7 +327,6 @@ typedef enum #define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) - /* Interrupt & Flag management */ /** * @brief Get the PSSI pending flags. @@ -394,7 +395,6 @@ typedef enum ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE )) - /** * @brief Check whether the PSSI Bus Width is valid. * @param __BUSWIDTH__ PSSI Bush width @@ -432,6 +432,7 @@ typedef enum #define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \ ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH )) + /** * @} */ @@ -486,7 +487,7 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); /* Peripheral State functions ***************************************************/ HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi); -uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi); +uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi); /** * @} @@ -507,7 +508,6 @@ void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); */ - /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h index c5dc670e04..2ee7fba843 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h @@ -181,15 +181,23 @@ typedef struct /** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection * @{ */ +#define PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO /*!< RAM1 shut-off control in Stop mode */ #if defined (PWR_PMCR_SRAM2_16SO) -#define PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO /*!< Ethernet shut-off control in Stop mode */ -#define PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO /*!< RAM3 shut-off control in Stop mode */ -#define PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO /*!< RAM2 16k byte shut-off control in Stop mode */ -#define PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO /*!< RAM2 48k byte shut-off control in Stop mode */ +#define PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO /*!< RAM2 16k byte shut-off control in Stop mode */ +#define PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO /*!< RAM2 48k byte shut-off control in Stop mode */ +#elif defined (PWR_PMCR_SRAM2_16LSO) +#define PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO /*!< RAM2 low 16k byte shut-off control in Stop mode */ +#define PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO /*!< RAM2 High 16k byte shut-off control in Stop mode */ +#define PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO /*!< RAM2 48k byte shut-off control in Stop mode */ #else -#define PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO /*!< RAM2 48k byte shut-off control in Stop mode */ +#define PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO /*!< RAM2 shut-off control in Stop mode */ #endif /* PWR_PMCR_SRAM2_16SO */ -#define PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO /*!< RAM1 shut-off control in Stop mode */ +#if defined (PWR_PMCR_SRAM3SO) +#define PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO /*!< RAM3 shut-off control in Stop mode */ +#endif /* PWR_PMCR_SRAM3SO */ +#if defined (PWR_PMCR_ETHERNETSO) +#define PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO /*!< Ethernet shut-off control in Stop mode */ +#endif /* PWR_PMCR_ETHERNETSO */ /** * @} @@ -413,13 +421,19 @@ typedef struct #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) -#if defined (PWR_PMCR_SRAM2_16SO) /* Check memory block parameter */ +#if defined (PWR_PMCR_SRAM2_16SO) #define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_ETHERNET_MEMORY_BLOCK) || \ ((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \ ((BLOCK) == PWR_RAM2_16_MEMORY_BLOCK) || \ ((BLOCK) == PWR_RAM2_48_MEMORY_BLOCK) || \ ((BLOCK) == PWR_RAM1_MEMORY_BLOCK)) +#elif defined (PWR_PMCR_SRAM2_16LSO) +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_LOW_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_HIGH_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_48_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_MEMORY_BLOCK)) #else #define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_RAM2_MEMORY_BLOCK) || \ ((BLOCK) == PWR_RAM1_MEMORY_BLOCK)) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_ramcfg.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_ramcfg.h index ddd267d1de..334d483ed7 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_ramcfg.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_ramcfg.h @@ -152,8 +152,6 @@ typedef struct /** * @} */ - - /** * @} */ @@ -254,7 +252,6 @@ typedef struct * @} */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup RAMCFG_Exported_Functions RAMCFG Exported Functions @@ -335,6 +332,7 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg) * @} */ + /** * @} */ @@ -361,7 +359,11 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg) (((INTERRUPT) != 0U) && (((INTERRUPT) & ~(RAMCFG_IT_SINGLEERR | RAMCFG_IT_DOUBLEERR | RAMCFG_IT_NMIERR)) == 0U)) +#if defined (RAMCFG_WPR3_P64WP) +#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 80U) +#else #define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 64U) +#endif /* RAMCFG_WPR3_P64WP*/ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h index 294ba30c26..23ed1016d8 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h @@ -3000,7 +3000,6 @@ typedef struct */ - /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h index 1a0c6c8ca6..4a7f1aaba0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h @@ -892,7 +892,11 @@ typedef struct * @{ */ #define RCC_I3C2CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) +#if defined(RCC_CR_PLL3ON) +#define RCC_I3C2CLKSOURCE_PLL3R RCC_CCIPR4_I3C2SEL_0 +#else #define RCC_I3C2CLKSOURCE_PLL2R RCC_CCIPR4_I3C2SEL_0 +#endif /* RCC_CR_PLL3ON */ #define RCC_I3C2CLKSOURCE_HSI RCC_CCIPR4_I3C2SEL_1 /** * @} @@ -3137,11 +3141,11 @@ typedef struct RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SDMMC2 | \ - RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | \ RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | \ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) -#elif defined(RCC_CR_PLL3ON) +#elif defined(UART7) #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ @@ -3152,9 +3156,20 @@ typedef struct RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_I3C1 | \ - RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ - RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SPI1 | \ + RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | \ + RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_OSPI | \ + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_CKPER) +#elif defined(USART6) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SPI1 | \ + RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | \ RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | \ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) #else @@ -3163,9 +3178,8 @@ typedef struct RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | RCC_PERIPHCLK_TIM | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \ RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ - RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_CKPER) + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) #endif /*FDCAN2 && SDMMC2 */ /** * @} @@ -3448,10 +3462,17 @@ typedef struct #endif /* RCC_CR_PLL3ON */ #if defined(I3C2) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) +#else #define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL2R) || \ ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) +#endif /* PLL3 */ #endif /* I3C2 */ #if defined(SAI1) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng_ex.h index 301458b837..b5f275a480 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,11 +55,11 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs - value of @ref RNG_Ex_Auto_Reset */ + value of @ref RNGEx_Auto_Reset */ uint32_t HealthTest; /*!< RNG health test control must be a value between 0x0FFCABFF and 0x00005200 */ } RNG_ConfigTypeDef; @@ -69,11 +69,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -112,7 +112,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -121,7 +121,7 @@ typedef struct /** * @} */ -/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration +/** @defgroup RNGEx_Auto_Reset Auto Reset configuration * @{ */ #define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ @@ -136,7 +136,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -145,7 +145,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -154,7 +154,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -163,7 +163,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -202,7 +202,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -211,11 +211,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -226,7 +226,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc.h index d56ee340ea..5f58312b86 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc.h @@ -503,35 +503,22 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @} */ -/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) for __HAL_RTC_GET_FLAG() +/** @defgroup RTC_Flags_Definitions RTC Flag Mask (5bits) for __HAL_RTC_GET_FLAG() * @{ */ -#define RTC_FLAG_MASK 0x001FU /*!< RTC flags mask (5bits) */ -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions RTC Flags Definitions - * Elements values convention: 000000XX000YYYYYb - * - YYYYY : Interrupt flag position in the XX register (5bits) - * - XX : Interrupt status register (2bits) - * - 01: ICSR register - * - 10: SR or SCR or MISR or SMISR registers - * @{ - */ -#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending flag */ -#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */ -#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */ -#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */ -#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */ -#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */ -#define RTC_FLAG_SSRUF (0x00000200U | RTC_SR_SSRUF_Pos) /*!< Clear SSR underflow flag */ -#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Clear Internal Time-stamp flag */ -#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Clear Time-stamp overflow flag */ -#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Clear Time-stamp flag */ -#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Clear Wakeup timer flag */ -#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Clear Alarm B flag */ -#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Clear Alarm A flag */ +#define RTC_FLAG_RECALPF (1U) /*!< Recalibration pending flag */ +#define RTC_FLAG_INITF (2U) /*!< Initialization flag */ +#define RTC_FLAG_RSF (3U) /*!< Registers synchronization flag */ +#define RTC_FLAG_INITS (4U) /*!< Initialization status flag */ +#define RTC_FLAG_SHPF (5U) /*!< Shift operation pending flag */ +#define RTC_FLAG_WUTWF (6U) /*!< Wakeup timer write flag */ +#define RTC_FLAG_SSRUF (7U) /*!< Clear SSR underflow flag */ +#define RTC_FLAG_ITSF (8U) /*!< Clear Internal Time-stamp flag */ +#define RTC_FLAG_TSOVF (9U) /*!< Clear Time-stamp overflow flag */ +#define RTC_FLAG_TSF (10U) /*!< Clear Time-stamp flag */ +#define RTC_FLAG_WUTF (11U) /*!< Clear Wakeup timer flag */ +#define RTC_FLAG_ALRBF (12U) /*!< Clear Alarm B flag */ +#define RTC_FLAG_ALRAF (13U) /*!< Clear Alarm A flag */ /** * @} */ @@ -669,7 +656,12 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ?\ + (SET_BIT(RTC->CR, RTC_CR_ALRAIE)):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ?\ + (SET_BIT(RTC->CR, RTC_CR_ALRBIE)):\ + (0U)) /*!< Dummy action because is an invalid parameter value */ /** * @brief Disable the RTC Alarm interrupt. @@ -680,7 +672,12 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ?\ + (CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE)):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ?\ + (CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE)):\ + (0U)) /*!< Dummy action because is an invalid parameter value */ /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. @@ -689,10 +686,14 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * This parameter can be: * @arg @ref RTC_IT_ALRA Alarm A interrupt * @arg @ref RTC_IT_ALRB Alarm B interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) \ - ? 1UL : 0UL) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ?\ + (READ_BIT(RTC->MISR, RTC_MISR_ALRAMF) == RTC_MISR_ALRAMF):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ?\ + (READ_BIT(RTC->MISR, RTC_MISR_ALRBMF) == RTC_MISR_ALRBMF):\ + (0U)) /*!< Return 0 because it is an invalid parameter value */ /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. @@ -701,10 +702,14 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * This parameter can be: * @arg @ref RTC_IT_ALRA Alarm A interrupt * @arg @ref RTC_IT_ALRB Alarm B interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) \ - ? 1UL : 0UL) +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ?\ + (READ_BIT(RTC->CR, RTC_CR_ALRAIE) == RTC_CR_ALRAIE):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ?\ + (READ_BIT(RTC->CR, RTC_CR_ALRBIE) == RTC_CR_ALRBIE):\ + (0U)) /*!< Return 0 because it is an invalid parameter value */ /** * @brief Get the selected RTC Alarms flag status. @@ -713,9 +718,14 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * This parameter can be: * @arg @ref RTC_FLAG_ALRAF * @arg @ref RTC_FLAG_ALRBF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_ALRAF) ?\ + (READ_BIT(RTC->SR, RTC_SR_ALRAF) == RTC_SR_ALRAF):\ + ((__FLAG__) == RTC_FLAG_ALRBF) ?\ + (READ_BIT(RTC->SR, RTC_SR_ALRBF) == RTC_SR_ALRBF):\ + (0U)) /*!< Return 0 because it is an invalid parameter value */ /** * @brief Clear the RTC Alarms pending flags. @@ -726,16 +736,19 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) \ - ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) :\ - (RTC->SCR = (RTC_CLEAR_ALRBF))) +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_ALRAF) ?\ + (SET_BIT(RTC->SCR, RTC_SCR_CALRAF)):\ + ((__FLAG__) == RTC_FLAG_ALRBF) ?\ + (SET_BIT(RTC->SCR, RTC_SCR_CALRBF)):\ + (0U)) /*!< Dummy action because is an invalid parameter value */ /** * @brief Check whether if the RTC Calendar is initialized. * @param __HANDLE__ specifies the RTC handle. - * @retval None + * @retval The state of RTC Calendar initialization (TRUE or FALSE). */ -#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U) +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS)) /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h index 006bc66197..e4ff1c700d 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rtc_ex.h @@ -942,11 +942,49 @@ typedef struct * @arg @ref RTC_FLAG_WUTF Wakeup timer flag * @arg @ref RTC_FLAG_ALRBF Alarm B flag * @arg @ref RTC_FLAG_ALRAF Alarm A flag - * @retval None - */ -#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? \ - (RTC->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \ - (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK)))) + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_RECALPF) ? \ + (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) == \ + RTC_ICSR_RECALPF) : \ + ((__FLAG__) == RTC_FLAG_INITF) ? \ + (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == \ + RTC_ICSR_INITF) : \ + ((__FLAG__) == RTC_FLAG_RSF) ? \ + (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == \ + RTC_ICSR_RSF) : \ + ((__FLAG__) == RTC_FLAG_INITS) ? \ + (READ_BIT(RTC->ICSR, RTC_ICSR_INITS) == \ + RTC_ICSR_INITS) : \ + ((__FLAG__) == RTC_FLAG_SHPF) ? \ + (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == \ + RTC_ICSR_SHPF) : \ + ((__FLAG__) == RTC_FLAG_WUTWF) ? \ + (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == \ + RTC_ICSR_WUTWF) : \ + ((__FLAG__) == RTC_FLAG_SSRUF) ? \ + (READ_BIT(RTC->SR, RTC_SR_SSRUF) == \ + RTC_SR_SSRUF) : \ + ((__FLAG__) == RTC_FLAG_ITSF) ? \ + (READ_BIT(RTC->SR, RTC_SR_ITSF) == \ + RTC_SR_ITSF) : \ + ((__FLAG__) == RTC_FLAG_TSOVF) ? \ + (READ_BIT(RTC->SR, RTC_SR_TSOVF) == \ + RTC_SR_TSOVF) : \ + ((__FLAG__) == RTC_FLAG_TSF) ? \ + (READ_BIT(RTC->SR, RTC_SR_TSF) == \ + RTC_SR_TSF): \ + ((__FLAG__) == RTC_FLAG_WUTF) ? \ + (READ_BIT(RTC->SR, RTC_SR_WUTF) == \ + RTC_SR_WUTF): \ + ((__FLAG__) == RTC_FLAG_ALRBF) ? \ + (READ_BIT(RTC->SR, RTC_SR_ALRBF) == \ + RTC_SR_ALRBF) : \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? \ + (READ_BIT(RTC->SR, RTC_SR_ALRAF) == \ + RTC_SR_ALRAF) : \ + (0U)) /*!< Return 0 because it is an invalid parameter value */ /* ---------------------------------WAKEUPTIMER---------------------------------*/ /** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer @@ -975,7 +1013,7 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_WUTIE)) /** * @brief Disable the RTC WakeUpTimer interrupt. @@ -985,7 +1023,7 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_WUTIE)) /** * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. @@ -993,10 +1031,9 @@ typedef struct * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. * This parameter can be: * @arg @ref RTC_IT_WUT WakeUpTimer interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) !=\ - 0UL) ? 1UL : 0UL) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_WUTMF)) != 0U) /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. @@ -1004,10 +1041,9 @@ typedef struct * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: * @arg @ref RTC_IT_WUT WakeUpTimer interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != \ - 0UL) ? 1UL : 0UL) +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_WUTIE)) != 0U) /** * @brief Get the selected RTC WakeUpTimers flag status. @@ -1016,9 +1052,14 @@ typedef struct * This parameter can be: * @arg @ref RTC_FLAG_WUTF * @arg @ref RTC_FLAG_WUTWF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_WUTF) ?\ + (READ_BIT(RTC->SR, RTC_SR_WUTF) == RTC_SR_WUTF):\ + ((__FLAG__) == RTC_FLAG_WUTWF) ?\ + (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == RTC_ICSR_WUTWF):\ + (0U)) /*!< Return 0 because it is an invalid parameter value */ /** * @brief Clear the RTC Wake Up timers pending flags. @@ -1028,7 +1069,8 @@ typedef struct * @arg @ref RTC_FLAG_WUTF * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF)) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CWUTF)) + /** * @} */ @@ -1060,7 +1102,7 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_TSIE)) /** * @brief Disable the RTC TimeStamp interrupt. @@ -1070,7 +1112,7 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_TSIE)) /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. @@ -1078,10 +1120,9 @@ typedef struct * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. * This parameter can be: * @arg @ref RTC_IT_TS TimeStamp interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != \ - 0U) ? 1UL : 0UL) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_TSMF)) != 0U) /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. @@ -1089,10 +1130,9 @@ typedef struct * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. * This parameter can be: * @arg @ref RTC_IT_TS TimeStamp interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ?\ - 1UL : 0UL) +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_TSIE)) != 0U) /** * @brief Get the selected RTC TimeStamps flag status. @@ -1101,9 +1141,14 @@ typedef struct * This parameter can be: * @arg @ref RTC_FLAG_TSF * @arg @ref RTC_FLAG_TSOVF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE) or 255 if invalid parameter. */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_TSF) ?\ + (READ_BIT(RTC->SR, RTC_SR_TSF) == RTC_SR_TSF):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ?\ + (READ_BIT(RTC->SR, RTC_SR_TSOVF) == RTC_SR_TSOVF):\ + (0U)) /*!< Return 0 because it is an invalid parameter value */ /** * @brief Clear the RTC Time Stamps pending flags. @@ -1114,7 +1159,12 @@ typedef struct * @arg @ref RTC_FLAG_TSOVF * @retval None */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_TSF) ?\ + (SET_BIT(RTC->SCR, RTC_SCR_CTSF)):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ?\ + (SET_BIT(RTC->SCR, RTC_SCR_CTSOVF)):\ + (0U)) /*!< Dummy action because is an invalid parameter value */ /** * @brief Enable the RTC internal TimeStamp peripheral. @@ -1138,8 +1188,7 @@ typedef struct * @arg @ref RTC_FLAG_ITSF * @retval None */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),\ - (__FLAG__))) +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_ITSF) == RTC_SR_ITSF)) /** * @brief Clear the RTC Internal Time Stamps pending flags. @@ -1149,8 +1198,7 @@ typedef struct * @arg @ref RTC_FLAG_ITSF * @retval None */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__),\ - RTC_CLEAR_ITSF)) +#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CITSF)) /** * @brief Enable the RTC TimeStamp on Tamper detection. @@ -1207,7 +1255,6 @@ typedef struct */ #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_COE)) - /** * @brief Enable the clock reference detection. * @param __HANDLE__ specifies the RTC handle. @@ -1222,21 +1269,19 @@ typedef struct */ #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_REFCKON)) - /** * @brief Get the selected RTC shift operations flag status. * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: * @arg @ref RTC_FLAG_SHPF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE) */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == RTC_ICSR_SHPF)) /** * @} */ - /* ------------------------------Tamper----------------------------------*/ /** @defgroup RTCEx_Tamper RTCEx tamper * @{ @@ -1409,7 +1454,7 @@ typedef struct * @arg RTC_FLAG_INT_TAMP_12: Internal Tamper12 flag * @arg RTC_FLAG_INT_TAMP_13: Internal Tamper13 flag * @arg RTC_FLAG_INT_TAMP_15: Internal Tamper15 flag - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE) */ #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0U) @@ -1461,7 +1506,7 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_SSRUIE)) /** * @brief Disable the RTC SSRU interrupt. @@ -1471,7 +1516,7 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_SSRUIE)) /** @@ -1480,19 +1525,18 @@ typedef struct * @param __INTERRUPT__ specifies the RTC SSRU interrupt to check. * This parameter can be: * @arg @ref RTC_IT_SSRU SSRU interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE) */ -#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) \ - ? 1U : 0U) +#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & (RTC_MISR_SSRUMF)) != 0U) ? 1U : 0U) /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: * @arg @ref RTC_IT_SSRU SSRU interrupt - * @retval None + * @retval The state of __INTERRUPT__ (TRUE or FALSE) */ -#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (RTC_CR_SSRUIE)) != 0U) ? 1U : 0U) /** * @brief Get the selected RTC SSRU's flag status. @@ -1500,9 +1544,9 @@ typedef struct * @param __FLAG__ specifies the RTC SSRU Flag is pending or not. * This parameter can be: * @arg @ref RTC_FLAG_SSRUF - * @retval None + * @retval The state of __FLAG__ (TRUE or FALSE) */ -#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_SSRUF) == RTC_SR_SSRUF)) /** * @brief Clear the RTC Wake Up timer's pending flags. @@ -1512,7 +1556,7 @@ typedef struct * @arg @ref RTC_FLAG_SSRUF * @retval None */ -#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_SSRUF)) +#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CSSRUF)) /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h index 68a51ae328..a3d9094206 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sdram.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smartcard.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smartcard.h index 2b5e49eae4..f311a5c34b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smartcard.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smartcard.h @@ -1037,6 +1037,122 @@ typedef enum (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#elif (defined(STM32H523xx) || defined(STM32H533xx)) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART2CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART3CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART6CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART6CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) #else #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smbus.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smbus.h index bad5113f95..377821f0e6 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smbus.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smbus.h @@ -100,8 +100,6 @@ typedef struct #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h index 2f26fb89ee..b329f87ec6 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_sram.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h index efaad2c6db..9aca3c85fb 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h @@ -416,29 +416,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -507,6 +506,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_DMABASE_TISEL 0x00000017U #define TIM_DMABASE_AF1 0x00000018U #define TIM_DMABASE_AF2 0x00000019U +#define TIM_DMABASE_OR1 0x0000001AU /** * @} */ @@ -1066,8 +1066,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ -#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ -#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ /** @@ -1958,8 +1958,9 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ - ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -2022,7 +2023,6 @@ mode. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) @@ -2091,8 +2091,8 @@ mode. ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ @@ -2416,7 +2416,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h index e81d82f316..ca46864e66 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h @@ -118,20 +118,23 @@ typedef struct #if defined(COMP1) #define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ #endif /* COMP1 */ -#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to LSE */ +#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ #if defined(SAI1) #define TIM_TIM2_ETR_SAI1_FSA TIM1_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */ -#define TIM_TIM2_ETR_SAI1_FSB (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_2) /*!< TIM2_ETR is connected to SAI1 */ +#define TIM_TIM2_ETR_SAI1_FSB (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 */ #endif /* SAI1 */ -#define TIM_TIM2_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_3) /*!< TIM2_ETR is connected to TIM3 ETR */ +#define TIM_TIM2_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM3 ETR */ #if defined(TIM4) -#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_3) /*!< TIM2_ETR is connected to TIM4 ETR */ +#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM4 ETR */ #endif /* TIM4 */ #if defined(TIM5) -#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_3 ) /*!< TIM2_ETR is connected to TIM5 ETR */ +#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM5 ETR */ #endif /* TIM5 */ +#if defined(USB_DRD_FS) +#define TIM_TIM2_ETR_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to USB SOF */ +#endif /* USB_DRD_FS */ #if defined(ETH_NS) -#define TIM_TIM2_ETR_ETH_PPS (TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< TIM2_ETR is connected to ETH PPS */ +#define TIM_TIM2_ETR_ETH_PPS (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to ETH PPS */ #endif /* ETH_NS */ #define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ @@ -163,6 +166,9 @@ typedef struct #define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to TIM2 ETR */ #define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM3 ETR */ #define TIM_TIM5_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to TIM4 ETR */ +#if defined(USB_DRD_FS) +#define TIM_TIM5_ETR_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to USB SOF */ +#endif /* USB_DRD_FS */ #endif /* TIM5 */ #if defined(TIM8) @@ -716,7 +722,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ - || \ + || \ (((INSTANCE) == TIM12) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ @@ -1005,6 +1011,10 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)))) + +#if defined(TIM17) +#define IS_TIM_RTCPREEN_SELECTION(__SELECTION__) ((__SELECTION__) == TIM_TIM17_TI1_HSE_1MHZ) +#endif /* TIM17 */ #endif /* STM32H503xx */ #define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h index 8cfaef2553..f05424b1b0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h @@ -261,6 +261,42 @@ HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef * (__CLOCKSOURCE__) = 0U; \ } \ } while(0U) +#elif (defined(STM32H523xx) || defined(STM32H533xx)) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) #else #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h index f9e48be433..d1721e25f0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h @@ -898,6 +898,122 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#elif (defined(STM32H523xx) || defined(STM32H533xx)) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART2CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART3CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART6CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART6CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) #else #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h index 968068d28f..d34a40a6d9 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h @@ -81,8 +81,6 @@ extern "C" { #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos) #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos) - - /* Internal mask for ADC group injected sequencer: */ /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ /* - data register offset */ @@ -107,8 +105,6 @@ extern "C" { #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos) #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos) - - /* Internal mask for ADC group regular trigger: */ /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ /* - regular trigger source */ @@ -137,8 +133,6 @@ extern "C" { #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos) #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos) - - /* Internal mask for ADC group injected trigger: */ /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ /* - injected trigger source */ @@ -167,11 +161,6 @@ extern "C" { #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos) #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos) - - - - - /* Internal mask for ADC channel: */ /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ /* - channel identifier defined by number */ @@ -397,7 +386,6 @@ extern "C" { * @} */ - /* Private macros ------------------------------------------------------------*/ /** @defgroup ADC_LL_Private_Macros ADC Private Macros * @{ @@ -418,7 +406,6 @@ extern "C" { * @} */ - /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure @@ -2786,6 +2773,32 @@ typedef struct / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ ) +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value) in + * differential ended mode. + * @note ADC data from ADC data register is unsigned and centered around + * middle code in. Converted voltage can be positive or negative + * depending on differential input voltages. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__)\ +((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\ + / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\ + - (int32_t)(__VREFANALOG_VOLTAGE__)) + /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h index 509336822c..97871a6f29 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h @@ -92,6 +92,8 @@ extern "C" { */ #if defined(CORDIC) #define LL_AHB1_GRP1_PERIPH_ALL 0xF13AD103U +#elif defined(DCACHE) +#define LL_AHB1_GRP1_PERIPH_ALL 0xF1021103U #else #define LL_AHB1_GRP1_PERIPH_ALL 0x91021103U #endif /* CORDIC */ @@ -125,8 +127,10 @@ extern "C" { /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH * @{ */ -#if defined(GPIOE) +#if defined(GPIOI) #define LL_AHB2_GRP1_PERIPH_ALL 0xC01F1DFFU +#elif defined(GPIOE) +#define LL_AHB2_GRP1_PERIPH_ALL 0xC01F1CFFU #else #define LL_AHB2_GRP1_PERIPH_ALL 0x40060C8FU #endif /* GPIOE */ @@ -193,8 +197,10 @@ extern "C" { /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH * @{ */ -#if defined(TIM4) +#if defined(USART11) #define LL_APB1_GRP1_PERIPH_ALL 0xDFFEC9FFU +#elif defined(USART6) +#define LL_APB1_GRP1_PERIPH_ALL 0x13FEC87FU #else #define LL_APB1_GRP1_PERIPH_ALL 0x01E7E833U #endif /* TIM4 */ @@ -288,8 +294,10 @@ extern "C" { /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH * @{ */ -#if defined(TIM8) +#if defined(TIM16) #define LL_APB2_GRP1_PERIPH_ALL 0x017F7800U +#elif defined(TIM8) +#define LL_APB2_GRP1_PERIPH_ALL 0x01097800U #else #define LL_APB2_GRP1_PERIPH_ALL 0x01005800U #endif /* TIM8 */ @@ -330,6 +338,8 @@ extern "C" { */ #if defined(SPI5) #define LL_APB3_GRP1_PERIPH_ALL 0x0030F9E2U +#elif defined(I2C4) +#define LL_APB3_GRP1_PERIPH_ALL 0x00300AC2U #else #define LL_APB3_GRP1_PERIPH_ALL 0x00200A42U #endif /* SPI5 */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cordic.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cordic.h index d7a99d3eeb..93d54c5c78 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cordic.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cordic.h @@ -131,12 +131,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE * @{ */ -#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two - 16-bit data input (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input - (Q1.31 format) */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bits data input (Q1.31 format), or two + 16-bits data input (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ /** * @} */ @@ -144,12 +144,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBREAD NBREAD * @{ */ -#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data output (Q1.31 format), or two - 16-bit data output (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output - (Q1.31 format) */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bits data output (Q1.31 format), or two + 16-bits data output (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ /** * @} */ @@ -218,9 +218,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions * @{ */ @@ -749,8 +747,6 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h index e8bdd8fe6e..83282d7440 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h @@ -21,7 +21,9 @@ [..] The LL CORTEX driver contains a set of generic APIs that can be used by user: - (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick with + HCLK source or @ref LL_Init1msTick_HCLK_Div8, @ref LL_Init1msTick_LSI or + @ref LL_Init1msTick_LSE with external source functions (+) Low power mode configuration (SCB register of Cortex-MCU) (+) API to access to MCU info (CPUID register) @@ -74,10 +76,15 @@ extern "C" { /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source * @{ */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick +#define LL_SYSTICK_CLKSOURCE_EXTERNAL 0x00000000U /*!< External clock source selected as SysTick clock source */ #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source */ +/** Legacy definitions for backward compatibility purpose + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 LL_SYSTICK_CLKSOURCE_EXTERNAL +/** + */ /** * @} */ @@ -154,7 +161,7 @@ extern "C" { * @{ */ #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< MPU region not shareable */ -#define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos) /*!< MPU region outer shareable */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< MPU region outer shareable */ #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< MPU region inner shareable */ /** * @} @@ -238,7 +245,7 @@ __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) * @brief Configures the SysTick clock source * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK * @retval None */ @@ -258,7 +265,7 @@ __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) * @brief Get the SysTick clock source * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK */ __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) @@ -814,9 +821,6 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, u /* Set region index */ WRITE_REG(MPU->RNR, Region); - /* Set base address */ - MPU->RBAR |= Attributes; - /* Set region base address and region access attributes */ WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dac.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dac.h index 4cc02a242b..7cd989f0ee 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dac.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dac.h @@ -561,7 +561,7 @@ typedef struct * @arg @ref LL_DAC_RESOLUTION_8B * @retval DAC conversion data (unit: digital value) */ -#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ / (__VREFANALOG_VOLTAGE__) \ ) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dcache.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dcache.h index f12262406d..38699cdd4a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dcache.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dcache.h @@ -405,44 +405,44 @@ __STATIC_INLINE void LL_DCACHE_ResetMonitors(DCACHE_TypeDef *DCACHEx, uint32_t M /** * @brief Get the Read Hit monitor Value - * @rmtoll RHMONR LL_DCACHE_Monitor_GetReadHitValue + * @rmtoll RHMONR RHITMON LL_DCACHE_Monitor_GetReadHitValue * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->RHMONR; } /** * @brief Get the Read Miss monitor Value - * @rmtoll RMMONR LL_DCACHE_Monitor_GetReadMissValue + * @rmtoll RMMONR RMISSMON LL_DCACHE_Monitor_GetReadMissValue * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->RMMONR; } /** * @brief Get the Write Hit monitor Value - * @rmtoll WHMONR LL_DCACHE_Monitor_GetWriteHitValue + * @rmtoll WHMONR WHITMON LL_DCACHE_Monitor_GetWriteHitValue * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->WHMONR; } /** * @brief Get the Write Miss monitor Value - * @rmtoll WMMONR LL_DCACHE_Monitor_GetWriteMissValue + * @rmtoll WMMONR WMISSMON LL_DCACHE_Monitor_GetWriteMissValue * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteMissValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->WMMONR; } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h index bbca461908..46c5440416 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h @@ -367,7 +367,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t DestSecure; /*!< This field specify the destination secure. This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */ @@ -390,7 +390,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t SrcSecure; /*!< This field specify the source secure. This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */ @@ -441,7 +441,7 @@ typedef struct This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */ uint32_t Mode; /*!< This field DMA Transfer Mode. - This parameter can be a value of @ref DMA_Transfer_Mode. */ + This parameter can be a value of @ref DMA_LL_TRANSFER_MODE. */ /* CBR1 register fields ****************************************************** If any CBR1 fields need to be updated comparing to previous node, it is @@ -573,14 +573,14 @@ typedef struct */ typedef struct { - __IO uint32_t LinkRegisters[8]; + __IO uint32_t LinkRegisters[8U]; } LL_DMA_LinkNodeTypeDef; /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ @@ -609,7 +609,7 @@ typedef struct #define LL_DMA_CHANNEL_15 (0x0FU) #if defined (USE_FULL_LL_DRIVER) #define LL_DMA_CHANNEL_ALL (0x10U) -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /** * @} */ @@ -629,7 +629,7 @@ typedef struct /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level * @{ @@ -912,7 +912,7 @@ typedef struct /** * @} */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type * @{ @@ -1431,9 +1431,9 @@ typedef struct #if defined (COMP1) #define LL_GPDMA1_TRIGGER_COMP1_OUT 44U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ #endif /* COMP1 */ -#if defined (STM32H503xx) -#define LL_GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ -#endif /* STM32H503xx */ +#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx) +#define LL_GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is EVENTOUT */ +#endif /* STM32H503xx || STM32H523xx || STM32H533xx */ /* GPDMA2 Hardware Triggers */ #define LL_GPDMA2_TRIGGER_EXTI_LINE0 0U /*!< GPDMA2 HW Trigger signal is EXTI_LINE0 */ @@ -1495,9 +1495,9 @@ typedef struct #if defined (COMP1) #define LL_GPDMA2_TRIGGER_COMP1_OUT 44U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */ #endif /* COMP1 */ -#if defined (STM32H503xx) -#define LL_GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */ -#endif /* STM32H503xx */ +#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx) +#define LL_GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is EVENTOUT */ +#endif /* STM32H503xx || STM32H523xx || STM32H533xx */ /** * @} */ @@ -2109,7 +2109,7 @@ __STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Chan uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel)); MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, - (DMA_CTR1_DSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); + (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); } /** @@ -2155,7 +2155,9 @@ __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, ui uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined (DMA_SECCFGR_SEC0) /** * @brief Check security attribute of the DMA transfer to the destination. * @note This API is used for all available DMA channels. @@ -2178,7 +2180,9 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DM return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC) == (DMA_CTR1_DSEC)) ? 1UL : 0UL); } +#endif /* DMA_SECCFGR_SEC0 */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Enable security attribute of the DMA transfer from the source. * @note This API is used for all available DMA channels. @@ -2222,7 +2226,9 @@ __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uin uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined (DMA_SECCFGR_SEC0) /** * @brief Check security attribute of the DMA transfer from the source. * @note This API is used for all available DMA channels. @@ -2245,7 +2251,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMA return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) == (DMA_CTR1_SSEC)) ? 1UL : 0UL); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* DMA_SECCFGR_SEC0 */ /** * @brief Set destination allocated port. @@ -2839,7 +2845,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_ * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n - * CTR2 SWREQ LL_DMA_ConfigChannelTransfer + * CTR2 SWREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 PFREQ LL_DMA_ConfigChannelTransfer * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 @@ -2853,13 +2860,14 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_ * @param Configuration This parameter must be a combination of all the following values: * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER - * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_HWREQUEST_BLK - * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_TRIG_POLARITY_RISING or + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or * @ref LL_DMA_TRIG_POLARITY_FALLING * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_NORMAL or @ref LL_DMA_PFCTRL *@retval None. */ __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) @@ -4079,7 +4087,7 @@ __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint * @param BlkDataLength Block transfer length Value between 0 to 0x0000FFFF * @param BlkRptCount Block repeat counter - * Value between 0 to 0x00000EFF + * Value between 0 to 0x000007FF *@retval None. */ __STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength, @@ -4253,7 +4261,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param BlkRptCount Block repeat counter - * Value between 0 to 0x00000EFF + * Value between 0 to 0x000007FF * @retval None. */ __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount) @@ -4271,7 +4279,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Cha * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between 0 to 0x00000EFF + * @retval Between 0 to 0x000007FF */ __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel) { @@ -4659,7 +4667,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *D * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels) * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels) * @arg @ref LL_DMA_UPDATE_CLLR - * @param LinkedListAddrOffset Between 0 to 0x0000FFFC + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. * @retval None. */ __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate, @@ -5185,7 +5193,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uin * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 - * @param LinkedListAddrOffset Between 0 to 0x0000FFFC + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. * @retval None. */ __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel, @@ -5283,7 +5291,9 @@ __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Cha { CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined (DMA_SECCFGR_SEC0) /** * @brief Check if DMA channel secure is enabled. * @note This API is used for all available DMA channels. @@ -5305,7 +5315,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* DMA_SECCFGR_SEC0 */ /** * @brief Enable the DMA channel privilege attribute. @@ -5392,7 +5402,7 @@ __STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32 { SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #if defined (DMA_RCFGLOCKR_LOCK0) /** @@ -5417,7 +5427,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } -#endif /* defined (DMA_RCFGLOCKR_LOCK0) */ +#endif /* DMA_RCFGLOCKR_LOCK0 */ /** * @} */ @@ -5808,7 +5818,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint3 return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} */ @@ -6311,7 +6321,7 @@ void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32 /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /** * @} @@ -6321,7 +6331,7 @@ void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32 * @} */ -#endif /* defined (GPDMA1) */ +#endif /* GPDMA1 */ /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h index 5ac480d5d3..339d86dcb0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h @@ -106,50 +106,93 @@ typedef struct #define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ #define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ #define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR1_IM18) #define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#endif /* EXTI_IMR1_IM18 */ #define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR1_IM20) #define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#endif /* EXTI_IMR1_IM20 */ #define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ #define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#if defined(EXTI_IMR1_IM23) #define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#endif /* EXTI_IMR1_IM23 */ #define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ #define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ #define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ #define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ #define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ #define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#if defined(EXTI_IMR1_IM30) #define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#endif /* EXTI_IMR1_IM30 */ +#if defined(EXTI_IMR1_IM31) #define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#endif /* EXTI_IMR1_IM31 */ #define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved */ +#if defined(EXTI_IMR2_IM32) #define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#endif /* EXTI_IMR2_IM32 */ +#if defined(EXTI_IMR2_IM33) #define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#endif /* EXTI_IMR2_IM33 */ +#if defined(EXTI_IMR2_IM34) #define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#endif /* EXTI_IMR2_IM34 */ +#if defined(EXTI_IMR2_IM35) #define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#endif /* EXTI_IMR2_IM35 */ +#if defined(EXTI_IMR2_IM36) #define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#endif /* EXTI_IMR2_IM36 */ #define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ #define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ #define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ #define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ #define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ #define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ +#if defined(EXTI_IMR2_IM43) #define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ +#endif /* EXTI_IMR2_IM43 */ +#if defined(EXTI_IMR2_IM44) #define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ +#endif /* EXTI_IMR2_IM44 */ +#if defined(EXTI_IMR2_IM45) #define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */ +#endif /* EXTI_IMR2_IM45 */ #if defined(ETH) #define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ #endif /* ETH */ #define LL_EXTI_LINE_47 EXTI_IMR2_IM47 /*!< Extended line 47 */ +#if defined(EXTI_IMR2_IM48) #define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ +#endif /* EXTI_IMR2_IM48 */ #define LL_EXTI_LINE_49 EXTI_IMR2_IM49 /*!< Extended line 49 */ #define LL_EXTI_LINE_50 EXTI_IMR2_IM50 /*!< Extended line 50 */ +#if defined(EXTI_IMR2_IM51) #define LL_EXTI_LINE_51 EXTI_IMR2_IM51 /*!< Extended line 51 */ +#endif /* EXTI_IMR2_IM51 */ +#if defined(EXTI_IMR2_IM52) #define LL_EXTI_LINE_52 EXTI_IMR2_IM52 /*!< Extended line 52 */ +#endif /* EXTI_IMR2_IM52 */ #define LL_EXTI_LINE_53 EXTI_IMR2_IM53 /*!< Extended line 53 */ +#if defined(EXTI_IMR2_IM54) #define LL_EXTI_LINE_54 EXTI_IMR2_IM54 /*!< Extended line 54 */ +#endif /* EXTI_IMR2_IM54 */ +#if defined(EXTI_IMR2_IM55) #define LL_EXTI_LINE_55 EXTI_IMR2_IM55 /*!< Extended line 55 */ +#endif /* EXTI_IMR2_IM55 */ +#if defined(EXTI_IMR2_IM56) #define LL_EXTI_LINE_56 EXTI_IMR2_IM56 /*!< Extended line 56 */ +#endif /* EXTI_IMR2_IM56 */ +#if defined(EXTI_IMR2_IM57) #define LL_EXTI_LINE_57 EXTI_IMR2_IM57 /*!< Extended line 57 */ +#endif /* EXTI_IMR2_IM57 */ +#if defined(EXTI_IMR2_IM58) +#define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */ +#endif /* EXTI_IMR2_IM58 */ #define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< ALL Extended line */ #define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ @@ -165,11 +208,19 @@ typedef struct #define LL_EXTI_EXTI_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ #define LL_EXTI_EXTI_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ #define LL_EXTI_EXTI_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */ +#if defined(GPIOE) #define LL_EXTI_EXTI_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */ +#endif /* GPIO E */ +#if defined(GPIOF) #define LL_EXTI_EXTI_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */ +#endif /* GPIO F */ +#if defined(GPIOG) #define LL_EXTI_EXTI_PORTG (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */ +#endif /* GPIO G */ #define LL_EXTI_EXTI_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */ +#if defined(GPIOI) #define LL_EXTI_EXTI_PORTI EXTI_EXTICR1_EXTI0_3 /*!< EXTI PORT I */ +#endif /* GPIO I */ /** * @} @@ -265,7 +316,6 @@ typedef struct */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions * @{ @@ -339,6 +389,7 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 @@ -350,10 +401,11 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 * - * (*) value not defined in all devices. + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) @@ -427,6 +479,7 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 @@ -438,10 +491,10 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 - * - * (*) value not defined in all devices. + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) @@ -516,6 +569,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 @@ -527,10 +581,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 - * - * (*) value not defined in all devices. + * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) @@ -609,6 +663,7 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_43 * @arg @ref LL_EXTI_LINE_44 * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_45 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 @@ -619,10 +674,10 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 - * - * (*) value not defined in all devices. + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) @@ -691,8 +746,8 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_41 * @arg @ref LL_EXTI_LINE_42 * @arg @ref LL_EXTI_LINE_43 - * @arg @ref LL_EXTI_LINE_44 (*) - * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_47 * @arg @ref LL_EXTI_LINE_48 * @arg @ref LL_EXTI_LINE_49 @@ -703,10 +758,10 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 - * - * (*) value not defined in all devices. + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) @@ -787,10 +842,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 - * - * (*) value not defined in all devices. + * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) @@ -834,6 +889,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) @@ -854,7 +910,8 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 - * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_53 + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) @@ -890,6 +947,7 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) @@ -911,7 +969,8 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 - * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_53 + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) @@ -940,6 +999,7 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) @@ -954,7 +1014,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 - * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_53 + * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) @@ -1020,7 +1081,8 @@ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 - * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_53 + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) @@ -1076,7 +1138,8 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 - * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_53 + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) @@ -1120,7 +1183,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 - * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_53 + * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) @@ -1182,7 +1246,8 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 * @arg @ref LL_EXTI_LINE_50 - * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_53 + * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) @@ -1518,11 +1583,11 @@ __STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_EXTI_PORTB * @arg @ref LL_EXTI_EXTI_PORTC * @arg @ref LL_EXTI_EXTI_PORTD - * @arg @ref LL_EXTI_EXTI_PORTE - * @arg @ref LL_EXTI_EXTI_PORTF - * @arg @ref LL_EXTI_EXTI_PORTG + * @arg @ref LL_EXTI_EXTI_PORTE (*) + * @arg @ref LL_EXTI_EXTI_PORTF (*) + * @arg @ref LL_EXTI_EXTI_PORTG (*) * @arg @ref LL_EXTI_EXTI_PORTH - * @arg @ref LL_EXTI_EXTI_PORTI + * @arg @ref LL_EXTI_EXTI_PORTI (*) * * (*) value not defined in all devices * @param Line This parameter can be one of the following values: @@ -1590,11 +1655,13 @@ __STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) * @arg @ref LL_EXTI_EXTI_PORTB * @arg @ref LL_EXTI_EXTI_PORTC * @arg @ref LL_EXTI_EXTI_PORTD - * @arg @ref LL_EXTI_EXTI_PORTE - * @arg @ref LL_EXTI_EXTI_PORTF - * @arg @ref LL_EXTI_EXTI_PORTG + * @arg @ref LL_EXTI_EXTI_PORTE (*) + * @arg @ref LL_EXTI_EXTI_PORTF (*) + * @arg @ref LL_EXTI_EXTI_PORTG (*) * @arg @ref LL_EXTI_EXTI_PORTH - * @arg @ref LL_EXTI_EXTI_PORTI + * @arg @ref LL_EXTI_EXTI_PORTI (*) + * + * (*) value not defined in all devices */ __STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) { @@ -1685,7 +1752,8 @@ __STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1768,7 +1836,8 @@ __STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1780,6 +1849,7 @@ __STATIC_INLINE void LL_EXTI_DisableSecure_32_63(uint32_t ExtiLine) #endif /* __ARM_FEATURE_CMSE */ +#if defined(EXTI_SECENR1_SEC0) /** * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 0 to 31 * @rmtoll SECCFGR1 SECx LL_EXTI_IsEnabledSecure_0_31 @@ -1853,7 +1923,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). @@ -1862,6 +1933,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_32_63(uint32_t ExtiLine) { return ((READ_BIT(EXTI->SECCFGR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } +#endif /* EXTI_SECENR1_SEC0 */ /** * @} @@ -1944,7 +2016,8 @@ __STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -2027,7 +2100,8 @@ __STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -2110,7 +2184,8 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_54 * @arg @ref LL_EXTI_LINE_55 * @arg @ref LL_EXTI_LINE_56 - * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmac.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmac.h index bc5b4edf40..603b3321b1 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmac.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmac.h @@ -38,7 +38,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants * @{ @@ -147,9 +146,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions * @{ */ @@ -1033,8 +1030,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -1042,7 +1037,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); - /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h index e406764d43..233859af52 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_fmc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h index a9c6a159b1..72db31d699 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h @@ -282,7 +282,8 @@ typedef struct */ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { - MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)), + (Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))); } /** @@ -316,8 +317,8 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 */ __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->MODER, - (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); + return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)); } /** @@ -422,8 +423,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uin */ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) { - MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)), - (Speed << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)), + (Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))); } /** @@ -459,8 +460,9 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint */ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, - (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << \ + (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)); } /** @@ -493,7 +495,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t */ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) { - MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)), + (Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))); } /** @@ -525,8 +528,8 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 */ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->PUPDR, - (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); + return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)); } /** @@ -565,8 +568,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t */ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), - (Alternate << (POSITION_VAL(Pin) * 4U))); + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)), + (Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))); } /** @@ -602,8 +605,8 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin */ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->AFR[0], - (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); + return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)); } /** @@ -642,8 +645,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_ */ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), - (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)), + (Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))); } /** @@ -680,8 +683,8 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui */ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); + return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))) >> \ + (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)); } /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h index e4b4932e84..230fd48d22 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h @@ -2234,11 +2234,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h index 13ebce80da..ce663d680c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h @@ -560,6 +560,7 @@ __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) /** * @brief Select the memory remapped region base address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress * @param Region This parameter can be one of the following values: * @arg @ref LL_ICACHE_REGION_0 @@ -572,12 +573,13 @@ __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) __STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address) { MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_BASEADDR, (((Address & 0x1FFFFFFFU) >> 21U) & ICACHE_CRRx_BASEADDR)); + ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U)); } /** * @brief Get the memory remapped region base address. * @note The base address is the alias in the Code region. + * @note The useful bits depends on RSIZE as described in the Reference Manual. * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress * @param Region This parameter can be one of the following values: * @arg @ref LL_ICACHE_REGION_0 @@ -589,18 +591,19 @@ __STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Ad __STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region) { return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_BASEADDR)); + ICACHE_CRRx_BASEADDR) << 21U); } /** - * @brief Select the memory remapped region remap address. + * @brief Select the memory remapped region address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress * @param Region This parameter can be one of the following values: * @arg @ref LL_ICACHE_REGION_0 * @arg @ref LL_ICACHE_REGION_1 * @arg @ref LL_ICACHE_REGION_2 * @arg @ref LL_ICACHE_REGION_3 - * @param Address External memory address + * @param Address Memory address to remap * @retval None */ __STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address) @@ -610,14 +613,15 @@ __STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t A } /** - * @brief Get the memory remapped region base address. + * @brief Get the memory remapped region address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress * @param Region This parameter can be one of the following values: * @arg @ref LL_ICACHE_REGION_0 * @arg @ref LL_ICACHE_REGION_1 * @arg @ref LL_ICACHE_REGION_2 * @arg @ref LL_ICACHE_REGION_3 - * @retval Address External memory address + * @retval Address Remapped memory address */ __STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h index ebe78379b5..68a6b9af49 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h @@ -2605,6 +2605,21 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_opamp.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_opamp.h index 2212dc2741..8f0857e5da 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_opamp.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_opamp.h @@ -70,7 +70,6 @@ extern "C" { * @} */ - /* Private macros ----------------------------------------------------------------------------------------------------*/ /** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros * @{ @@ -87,13 +86,10 @@ extern "C" { #define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) \ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U)))) - - /** * @} */ - /* Exported types ----------------------------------------------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure @@ -243,8 +239,6 @@ typedef struct * @} */ - - /** @defgroup OPAMP_LL_EC_POWER_MODE OPAMP PowerMode * @{ */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h index 72294ae911..4c992b2879 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h @@ -529,7 +529,73 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_16K_ShutOff(void) { return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO) == (PWR_PMCR_SRAM2_16SO)) ? 1UL : 0UL); } -#else +#endif /* PWR_PMCR_SRAM2_16SO */ + +#if defined(PWR_PMCR_SRAM2_16HSO) +/** + * @brief Enable the AHB RAM2 high 16K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_16HSO LL_PWR_EnableAHBRAM2_High_16K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2_High_16K_ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO); +} + +/** + * @brief Disable the AHB RAM2 high 16K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_16HSO LL_PWR_DisableAHBRAM2_High_16K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2_High_16K_ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO); +} + +/** + * @brief Check if the high AHB RAM2 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM2_16HSO LL_PWR_IsEnabledAHBRAM2_16K_ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_High_16K_ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO) == (PWR_PMCR_SRAM2_16HSO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM2_16HSO */ + +#if defined(PWR_PMCR_SRAM2_16LSO) +/** + * @brief Enable the AHB RAM2 low 16K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_16LSO LL_PWR_EnableAHBRAM2_Low_16K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2_Low_16K_ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO); +} + +/** + * @brief Disable the AHB RAM2 low 16K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_16LSO LL_PWR_DisableAHBRAM2_Low_16K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2_Low_16K_ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO); +} + +/** + * @brief Check if the low 16K AHB RAM2 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM2_16LSO LL_PWR_IsEnabledAHBRAM2_Low_16K_ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_Low_16K_ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO) == (PWR_PMCR_SRAM2_16LSO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM2_16LSO */ + +#if defined (PWR_PMCR_SRAM2SO) /** * @brief Enable the AHB RAM2 shut-off in Stop mode * @rmtoll PMCR SRAM2SO LL_PWR_EnableAHBRAM2ShutOff @@ -559,7 +625,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void) { return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO) == (PWR_PMCR_SRAM2SO)) ? 1UL : 0UL); } -#endif /* PWR_PMCR_SRAM2_16SO */ +#endif /* PWR_PMCR_SRAM2SO */ #if defined (PWR_PMCR_SRAM3SO) /** @@ -1092,33 +1158,36 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void) /** * @brief Enable the independent USB supply. - * @rmtoll USBSCR USB33SV LL_PWR_EnableVDDUSB + * @rmtoll USBSCR USB33SV LL_PWR_EnableVddUSB * @retval None */ -__STATIC_INLINE void LL_PWR_EnableVDDUSB(void) +__STATIC_INLINE void LL_PWR_EnableVddUSB(void) { SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV); } +#define LL_PWR_EnableVDDUSB LL_PWR_EnableVddUSB /* for API backward compatibility */ /** * @brief Disable the independent USB supply. - * @rmtoll USBSCR USB33SV LL_PWR_DisableVDDUSB + * @rmtoll USBSCR USB33SV LL_PWR_DisableVddUSB * @retval None */ -__STATIC_INLINE void LL_PWR_DisableVDDUSB(void) +__STATIC_INLINE void LL_PWR_DisableVddUSB(void) { CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV); } +#define LL_PWR_DisableVDDUSB LL_PWR_DisableVddUSB /* for API backward compatibility */ /** * @brief Check if the independent USB supply is enabled. - * @rmtoll USBSCR USB33SV LL_PWR_IsEnabledVDDUSB + * @rmtoll USBSCR USB33SV LL_PWR_IsEnabledVddUSB * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDUSB(void) +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) { return ((READ_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV) == (PWR_USBSCR_USB33SV)) ? 1UL : 0UL); } +#define LL_PWR_IsEnabledVDDUSB LL_PWR_IsEnabledVddUSB /* for API backward compatibility */ #endif /* PWR_USBSCR_USB33DEN */ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h index 71a1ac5b72..56c7fad086 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h @@ -726,7 +726,11 @@ typedef struct #if defined(I3C2) #define LL_RCC_I3C2_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as I3C2 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_I3C2_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_0) /*!< PLL3 R clock used as I3C2 clock source */ +#else #define LL_RCC_I3C2_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_0) /*!< PLL2 R clock used as I3C2 clock source */ +#endif /* PLL3 */ #define LL_RCC_I3C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_1) /*!< HSI clock used as I3C2 clock source */ #define LL_RCC_I3C2_CLKSOURCE_NONE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL) /*!< NONE clock used as I3C2 clock source */ #endif /* I3C2 */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h index d0a531cc76..600b92d56e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h @@ -230,7 +230,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) { - CLEAR_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -241,7 +242,8 @@ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) { - SET_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -331,7 +333,7 @@ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) { MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); - CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);; + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -442,7 +444,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) { - MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, (Divider << RNG_CR_CLKDIV_Pos) | RNG_CR_CONDRST); + MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST); CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } @@ -693,7 +695,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h index 2a32e36572..2f31329834 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rtc.h @@ -640,14 +640,16 @@ typedef struct /** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK * @{ */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2048 (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/2048 */ + /** * @} */ @@ -1588,7 +1590,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1622,7 +1624,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1657,7 +1659,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1692,7 +1694,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1746,7 +1748,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1895,7 +1897,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n @@ -1929,7 +1931,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1976,7 +1978,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n @@ -2018,7 +2020,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n @@ -2084,7 +2086,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_spi.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_spi.h index 9418b3ebef..88b6e715e0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_spi.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_spi.h @@ -836,7 +836,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll) { - MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll); + MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll); } /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h index 1654520d5a..fce911fa32 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h @@ -149,8 +149,8 @@ extern "C" { /** @defgroup SYSTEM_LL_SBS_EPOCH_Selection EPOCH Selection * @{ */ -#define LL_SBS_EPOCH_SEL_SECURE 0x0UL /*!< EPOCH secure selected */ -#define LL_SBS_EPOCH_SEL_NONSECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH non secure selected */ +#define LL_SBS_EPOCH_SEL_NONSECURE 0x0UL /*!< EPOCH non secure selected */ +#define LL_SBS_EPOCH_SEL_SECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH secure selected */ #define LL_SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */ /** @@ -982,14 +982,12 @@ __STATIC_INLINE uint32_t LL_SBS_GetSecureLock(void) * @note Only available from secure state when system implements security (TZEN=1) * @rmtoll SECCFGR SBSSEC LL_SBS_ConfigSecure\n * SECCFGR CLASSBSEC LL_SBS_ConfigSecure\n - * SECCFGR FPUSEC LL_SBS_ConfigSecure\n - * SECCFGR SDCE_SEC_EN LL_SBS_ConfigSecure + * SECCFGR FPUSEC LL_SBS_ConfigSecure * @param Configuration This parameter shall be the full combination * of the following values: * @arg @ref LL_SBS_CLOCK_SEC or LL_SBS_CLOCK_NSEC * @arg @ref LL_SBS_CLASSB_SEC or LL_SBS_CLASSB_NSEC * @arg @ref LL_SBS_FPU_SEC or LL_SBS_FPU_NSEC - * @arg @ref LL_SBS_SMPS_SEC or LL_SBS_SMPS_NSEC * @retval None */ __STATIC_INLINE void LL_SBS_ConfigSecure(uint32_t Configuration) @@ -1002,17 +1000,15 @@ __STATIC_INLINE void LL_SBS_ConfigSecure(uint32_t Configuration) * @note Only available when system implements security (TZEN=1) * @rmtoll SECCFGR SBSSEC LL_SBS_ConfigSecure\n * SECCFGR CLASSBSEC LL_SBS_ConfigSecure\n - * SECCFGR FPUSEC LL_SBS_ConfigSecure\n - * SECCFGR SDCE_SEC_EN LL_SBS_ConfigSecure + * SECCFGR FPUSEC LL_SBS_ConfigSecure * @retval Returned value is the combination of the following values: * @arg @ref LL_SBS_CLOCK_SEC or LL_SBS_CLOCK_NSEC * @arg @ref LL_SBS_CLASSB_SEC or LL_SBS_CLASSB_NSEC * @arg @ref LL_SBS_FPU_SEC or LL_SBS_FPU_NSEC - * @arg @ref LL_SBS_SMPS_SEC or LL_SBS_SMPS_NSEC */ __STATIC_INLINE uint32_t LL_SBS_GetConfigSecure(void) { - return (uint32_t)(READ_BIT(SBS->SECCFGR, LL_SBS_CLOCK_SEC | LL_SBS_CLASSB_SEC | LL_SBS_FPU_SEC | LL_SBS_SMPS_SEC)); + return (uint32_t)(READ_BIT(SBS->SECCFGR, LL_SBS_CLOCK_SEC | LL_SBS_CLASSB_SEC | LL_SBS_FPU_SEC)); } #endif /* __ARM_FEATURE_CMSE && __ARM_FEATURE_CMSE == 3U */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h index bae316791b..eb74d71439 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h @@ -682,10 +682,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR2, TIM_CR2_CCPC); } +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check @@ -2464,8 +2500,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) * @retval None @@ -2506,8 +2542,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) */ @@ -3911,6 +3947,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_USB_SOF (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_ETH_PPS (*) * @@ -3938,6 +3975,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR + * @arg @ref LL_TIM_TIM5_ETRSOURCE_USB_SOF (*) * * TIM8: any combination of ETR_RMP where (**) * @@ -4122,18 +4160,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); } -/** - * @brief Re-arm the break input (when it operates in bidirectional mode). - * @note The Break input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); -} - /** * @brief Enable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not @@ -4223,18 +4249,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); } -/** - * @brief Re-arm the break 2 input (when it operates in bidirectional mode). - * @note The Break 2 input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); -} - /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -4568,6 +4582,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 * @param DMABurstLength This parameter can be one of the following values: * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS @@ -4962,6 +4977,42 @@ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap); } +/** + * @brief Enable request for HSE 1MHz clock used for TISEL remap. + * @note Only TIM17 support HSE 1MHz remap + * @rmtoll OR1 RTCPREEN LL_TIM_EnableRTCPRE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableRTCPRE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->OR1, TIM_OR1_RTCPREEN); +} + +/** + * @brief Disable request for HSE 1MHz clock used for TISEL remap. + * @note Only TIM17 support HSE 1MHz remap + * @rmtoll OR1 RTCPREEN LL_TIM_DisableRTCPRE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableRTCPRE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->OR1, TIM_OR1_RTCPREEN); +} + +/** + * @brief Indicate whether request for HSE 1MHz clock is enabled. + * @note Only TIM17 support HSE 1MHz remap + * @rmtoll OR1 RTCPREEN LL_TIM_IsEnabledRTCPRE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledRTCPRE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->OR1, TIM_OR1_RTCPREEN) == (TIM_OR1_RTCPREEN)) ? 1UL : 0UL); +} + /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h index 8835a2126d..b310e7ee41 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h @@ -37,6 +37,9 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ +#ifndef HAL_USB_TIMEOUT +#define HAL_USB_TIMEOUT 0xF000000U +#endif /* define HAL_USB_TIMEOUT */ /** * @brief USB Mode definition @@ -84,39 +87,39 @@ typedef enum */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t Host_channels; /*!< Host Channels number. + uint8_t Host_channels; /*!< Host Channels number. This parameter Depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t dma_enable; /*!< USB DMA state. + uint8_t dma_enable; /*!< USB DMA state. If DMA is not supported this parameter shall be set by default to zero */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - uint32_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ + uint8_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ - uint32_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ + uint8_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ } USB_CfgTypeDef; typedef struct @@ -683,20 +686,17 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; \ (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ \ - if ((wCount) > 62U) \ + if ((wCount) == 0U) \ { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + (pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - if ((wCount) == 0U) \ - { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else \ - { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ + USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ @@ -846,6 +846,9 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode); +HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num); + #if defined (HAL_PCD_MODULE_ENABLED) HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h index aa4d45216e..86bcdd01aa 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h @@ -202,6 +202,9 @@ typedef struct #define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000EU /*!< UFBGA169 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_WLCSP25 0x0000000FU /*!< WLCSP25 package type */ #define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000010U /*!< UFQFPN48 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP39 0x00000011U /*!< WLCSP39 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000014U /*!< UFBGA100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000015U /*!< UFBGA144 package type */ /** * @} */ @@ -278,6 +281,10 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP25 * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP39 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 + * @note Refer to product datasheet for availability of package on a specific device */ __STATIC_INLINE uint32_t LL_GetPackageType(void) { @@ -310,6 +317,9 @@ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) } void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency); +void LL_Init1msTick_LSE(void); +void LL_Init1msTick_LSI(void); void LL_mDelay(uint32_t Delay); /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h index 23fd087b0d..aec9c62184 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h +++ b/system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_util_i3c.h @@ -27,10 +27,12 @@ extern "C" { /* Includes ----------------------------------------------------------------------------------------------------------*/ #if defined (USE_HAL_DRIVER) #include "stm32h5xx_hal.h" -#else -#include "stm32h5xx_ll_i3c.h" #endif /* USE_HAL_DRIVER */ +#if defined (USE_FULL_LL_DRIVER) +#include "stm32h5xx_ll_i3c.h" +#endif /* USE_FULL_LL_DRIVER */ + /** @addtogroup STM32H5xx_UTIL_Driver * @{ */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/README.md b/system/Drivers/STM32H5xx_HAL_Driver/README.md index c21c24048a..f270685613 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/README.md +++ b/system/Drivers/STM32H5xx_HAL_Driver/README.md @@ -1,19 +1,21 @@ # STM32CubeH5 HAL Driver MCU Component +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32h5xx_hal_driver.svg?color=brightgreen) + ## Overview -**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. +**STM32Cube** is a STMicroelectronics original initiative aimed at making life easier for developers by reducing effort, time and cost. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product - * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio - * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series - * A consistent set of middlewares components such as FileX, ThreadX, NetXDuo ... - * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers of each evaluation, demonstration, or nucleo board provided for this STM32 series. + * A consistent set of middleware libraries such as FileX, ThreadX, NetXDuo ... + * A full set of software projects (basic examples, applications, and demonstrations) for each board, each project developed in three flavors using three toolchains (EWARM, MDK-ARM, and STM32CubeIDE). Two models of publication are proposed for the STM32Cube embedded software: - * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) - * The **MCU component** : progressively from March 2023, each STM32Cube software module being part of the STM32Cube MCU Package are delivered as an individual repo, allowing the user to select and get only the required software functions. + * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). + * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. ## Description @@ -21,16 +23,14 @@ This **stm32h5xx_hal_driver** MCU component repo is one element of the STM32Cube ## Release note -Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32h5xx_hal_driver/blob/master/Release_Notes.html). +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32h5xx_hal_driver/blob/main/Release_Notes.html). ## Compatibility information -It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeH5/blob/main/Release_Notes.html) release note. +It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeH5/blob/main/Release_Notes.html) release note. The full **STM32CubeH5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH5). ## Troubleshooting -If you have any issue with the software content of this repository, you can file an issue [here](https://github.com/STMicroelectronics/stm32h5xx_hal_driver/issues/new/choose). - -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html index 0b35839fc3..6dd7eea432 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32H5xx_HAL_Driver/Release_Notes.html @@ -40,10 +40,193 @@

Purpose

Update History

- +

Main Changes

    +

  • First offiicial release of HAL and LL drivers to support STM32H533xx and STM32H523xx devices

    +
      +
    • HAL drivers : +
        +
      • HAL GENERIC driver: +
          +
        • Update HAL_InitTick() API to manage multiple SysTick clock source (Ticket 167747).
          • +
        • +
      • HAL CORTEX driver: +
          +
        • Add new API HAL_SYSTICK_GetCLKSourceConfig() to get SysTick clock source.
          • +
        • Update HAL_SYSTICK_Config() API to manage multiple SysTick clock source (Ticket 167747).
          • +
        • +
      • HAL RCC driver: +
          +
        • Update HAL_RCC_NMI_IRQHandler() to clear flag before callback (Ticket 158329).
          • +
        • Correct RCC_PERIPHCLOCK_ALL define value for H5-512K.
          • +
        • +
      • HAL GPIO driver: +
          +
        • Add missing AFs in H5-512K : GPIO_AF2_TIM8, GPIO_AF4_SPI3 and GPIO_AF6_USART6.
          • +
        • +
      • HAL EXTI driver: +
          +
        • Correct EXTI_LINE_NB define for all H5 derivatives.
          • +
        • +
      • HAL ADC driver: +
          +
        • Add new Helper macro (__HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE()) for differential mode raw data to voltage conversion (Ticket 155612).
          • +
        • +
      • HAL DMA driver: +
          +
        • Add peripheral flow control check PFREQ (early termination) in HAL_DMA_Init() API.
          • +
        • +
      • HAL ETH driver: +
          +
        • Rename ETH_TxPacketConfig to ETH_TxPacketConfigTypeDef
          • +
        • Update ETH_Start_IT sequence (Ticket 154251)
          • +
        • Fix PTP APIs (Ticket 137427)
          • +
        • Add condition to get the TimeStamp only when it was captured (Ticket 157128)
          • +
        • Update ReadData() API to use real latest buffer length received instead of predefined ethernet frame length (Tickets 152028 & 157139)
          • +
        • Update HAL_ETH_SetMDIOClockRange API (Ticket 159046 & 157253)
          • +
        • Update HAL_ETH_IRQHandler API : Remove multiple volatile reads or writes (Ticket 111542)
          • +
        • Update HAL_ETH_Init() API : Disable of unwanted interrupts section moved from HAL_ETH_Start_IT() to HAL_ETH_Init() (Ticket 159576)
          • +
        • Update ETH_Prepare_Tx_Descriptors() API to avoid enabling unwanted global interrupts (Ticket 125056)
          • +
        • Update ETH_UpdateDescriptor() to avoid that ETH DMA peripheral reads incorrect Rx buffer address (Ticket 159272)
          • +
        • Update on MAC L4/L3 Set/Get Filter config functions to avoid code coverage issues
          • +
        • Update on HAL_ETH_ReleaseTxPacket() to use the right way to increment descriptors (Ticket 155726)
          • +
        • Rename PTP configuration state defines : +
            +
          • HAL_ETH_PTP_NOT_CONFIGURATED to HAL_ETH_PTP_NOT_CONFIGURED
            • +
          • HAL_ETH_PTP_CONFIGURATED to HAL_ETH_PTP_CONFIGURED
            • +
          • +
        • +
      • HAL FLASH driver: +
          +
        • Add ECC operations APIs: +
            +
          • HAL_FLASHEx_EnableEccCorrectionInterrupt()
            • +
          • HAL_FLASHEx_DisableEccCorrectionInterrupt()
            • +
          • HAL_FLASHEx_GetEccInfo()
            • +
          • HAL_FLASHEx_ECCD_IRQHandler()
            • +
          • HAL_FLASHEx_EccDetectionCallback()
            • +
          • HAL_FLASHEx_EccCorrectionCallback()
            • +
          • +
        • Update HAL_FLASH_IRQHandler() to handle ECC interrupt.
          • +
        • Correct OB_BOR_LEVEL_X defines values (Ticket 158618).
          • +
        • Add missing User OBs for USB power delivery configuration.
          • +
        • Update FLASH_OB_GetEDATA() API to give correct EDATASize (Ticket 167670)
          • +
        • +
      • HAL HCD driver: +
          +
        • Update HCD_HC_IN_IRQHandler() to Prevent auto start of periodic interrupt channel during NAK (Ticket 151335).
          • +
        • Fix in RX count formula in HCD_GET_CH_RX_CNT().
          • +
        • +
      • HAL I2C driver: +
          +
        • Fix HAL_I2C_Slave_Transmit returning HAL error when checking the NACK flag (Ticket 162945).
          • +
        • Move Prefetch process to function HAL_I2C_Slave_Transmit (Ticket 167073).
          • +
        • Fix Error management during HAL_I2C_Mem_Read polling process (Ticket 155722).
          • +
        • +
      • HAL I3C driver: +
          +
        • Add HAL_I3C_Get_ENTDAA_Payload_Info() API and macro to retrieve the different part of the ENTDAA payload:
          • +
        • Add private ISR functions to HAL to solve the “IBI or HJ or CR event notification can be lost” problem.
          • +
        • Fix Ticket 169111 - Undefined LL TypeDefs in stm32h5xx_util_i3c.h
          • +
        • +
      • HAL RAMCFG driver: +
          +
        • Update HAL_RAMCFG_EnableWriteProtection() to support H5-512K.
          • +
        • +
      • HAL RTC driver: +
          +
        • Remove useless RTC_ICSR_WUTWF bit polling inside HAL_RTCEx_DeactivateWakeUpTimer (Ticket 153540).
          • +
        • +
      • HAL SMBUS driver: +
          +
        • Fix TXDR flush when no error is occurred (Ticket 163156).
          • +
        • +
      • HAL SPI/I2S driver: +
          +
        • Fix misplaced HAL_UNLOCK in IT functions (Ticket 156258).
          • +
        • +
      • HAL TIM driver: +
          +
        • Add HSE divider control capability for TIM17 (Ticket 164073).
          • +
        • Remove irrelevant state management in DMA callbacks (Ticket 167896).
          • +
        • Fix typo in some macros (ASYMMETRIC instead of ASSYMETRIC) (Ticket 165438).
          • +
        • Add USB related ETR defines.
          • +
        • +
      • HAL UART driver: +
          +
        • Add support of H5-512K devices.
          • +
        • +
      • HAL USART driver: +
          +
        • Add support of H5-512K devices.
          • +
        • +
      • +
    • LL drivers : +
        +
      • LL CORTEX driver: +
          +
        • Replace LL_SYSTICK_CLKSOURCE_HCLK_DIV8 by LL_SYSTICK_CLKSOURCE_EXTERNAL define (Ticket 167747).
          • +
        • +
      • LL RCC Driver: +
          +
        • Update RCC_GetSystemClockFreq() and LL_RCC_GetPPPClockFreq() APIs with PPP = {UART, USART, SPI, I2C, I3C, LPUART, ADCDAC} to consider the HSI division(Ticket 161846).
          • +
        • +
      • LL BUS Driver: +
          +
        • Correct LL_APBx_PERIPH_ALL defines values for H5-512K.
          • +
        • +
      • LL UTILS Driver: +
          +
        • Add new APIs to manage multiple SysTick clock source (Ticket 167747) : +
            +
          • LL_Init1msTick_HCLK_Div8()
            • +
          • LL_Init1msTick_LSE()
            • +
          • LL_Init1msTick_LSI()
            • +
          • +
        • +
      • LL EXTI driver: +
          +
        • Update LL_EXTI_DeInit() with correct IMR2 reset value for H5-512K.
          • +
        • +
      • LL ADC driver: +
          +
        • Add new Helper macro (__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE()) for differential mode raw data to voltage conversion (Ticket 155612).
          • +
        • Update LL_ADC_DeInit() to resolve conflict with RM (Ticket 157398)
          • +
        • +
      • LL DMA driver: +
          +
        • Add peripheral flow control check PFREQ (early termination) in LL_DMA_Init() API.
          • +
        • +
      • LL I2C driver: +
          +
        • Update LL_I2C_HandleTransfer() to prevent writing to I2C_CR2 reserved bits (Ticket 160951)
          • +
        • +
      • LL TIM driver: +
          +
        • Add HSE divider control capability for TIM17 (Ticket 164073).
          • +
        • Fix typo in some macros (ASYMMETRIC instead of ASSYMETRIC) (Ticket 165438).
          • +
        • +
      • +
    • +
+

Note: HAL/LL Backward compatibility ensured by legacy defines.

+

Known Limitations

+
    +
  • None
    • +
+

Backward compatibility

+
    +
  • No compatibility break
    • +
+
+
+
+ +
+

Main Changes

+

  • Maintenance Release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx devices

    • HAL drivers : @@ -114,11 +297,11 @@

      Main Changes

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • No compatibility break
@@ -127,15 +310,15 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • First official release of HAL and LL drivers for STM32H573xx / STM32H563xx / STM32H562xx / STM32H503xx devices
-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • Not Applicable
diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c index b07887a4df..8d80e46101 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c @@ -48,10 +48,10 @@ /* Private typedef ---------------------------------------------------------------------------------------------------*/ /* Private define ----------------------------------------------------------------------------------------------------*/ /** - * @brief STM32H5xx HAL Driver version number 1.1.0 + * @brief STM32H5xx HAL Driver version number 1.2.0 */ #define __STM32H5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32H5XX_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32H5XX_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32H5XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32H5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32H5XX_HAL_VERSION ((__STM32H5XX_HAL_VERSION_MAIN << 24U)\ @@ -132,8 +132,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ * @note HAL_Init() function is called at the beginning of program after reset and before * the clock configuration. * - * @note In the default implementation the System Timer (Systick) is used as source of time base. - * The Systick configuration is based on HSI clock, as HSI is the clock + * @note In the default implementation the System Timer (SysTick) is used as source of time base. + * The SysTick configuration is based on HSI clock, as HSI is the clock * used after a system Reset and the NVIC configuration is set to Priority group 4. * Once done, time base tick starts incrementing: the tick variable counter is incremented * each 1ms in the SysTick_Handler() interrupt handler. @@ -153,6 +153,9 @@ HAL_StatusTypeDef HAL_Init(void) /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + /* Select HCLK as SysTick clock source */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { @@ -241,29 +244,57 @@ __weak void HAL_MspDeInit(void) */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + uint32_t ticknumber = 0U; + uint32_t systicksel; + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if ((uint32_t)uwTickFreq == 0UL) { return HAL_ERROR; } - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) + /* Check Clock source to calculate the tickNumber */ + if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) == SysTick_CTRL_CLKSOURCE_Msk) { - return HAL_ERROR; + /* HCLK selected as SysTick clock source */ + ticknumber = SystemCoreClock / (1000UL / (uint32_t)uwTickFreq); } - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + else { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; + systicksel = HAL_SYSTICK_GetCLKSourceConfig(); + switch (systicksel) + { + /* HCLK_DIV8 selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_HCLK_DIV8: + /* Calculate tick value */ + ticknumber = (SystemCoreClock / (8000UL / (uint32_t)uwTickFreq)); + break; + /* LSI selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_LSI: + /* Calculate tick value */ + ticknumber = (LSI_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + /* LSE selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_LSE: + /* Calculate tick value */ + ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + default: + /* Nothing to do */ + break; + } } - else + + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(ticknumber) > 0U) { return HAL_ERROR; } + /* Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + /* Return function status */ return HAL_OK; } @@ -296,7 +327,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. + * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cordic.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cordic.c index 05cad67415..8fc7324839 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cordic.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cordic.c @@ -164,12 +164,12 @@ static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); + /** * @} */ /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions * @{ */ @@ -1141,7 +1141,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic) /*Call registered callback*/ hcordic->CalculateCpltCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_CalculateCpltCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } @@ -1282,7 +1282,7 @@ static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma) /*Call registered callback*/ hcordic->CalculateCpltCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_CalculateCpltCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } @@ -1311,7 +1311,7 @@ static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma) /*Call registered callback*/ hcordic->CalculateCpltCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_CalculateCpltCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } @@ -1336,7 +1336,7 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma) /*Call registered callback*/ hcordic->ErrorCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_ErrorCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c index 996430e2cb..624abb2b62 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c @@ -392,7 +392,23 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - return SysTick_Config(TicksNumb); + if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + /* Reload value impossible */ + return (1UL); + } + + /* Set reload register */ + WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL)); + + /* Load the SysTick Counter Value */ + WRITE_REG(SysTick->VAL, 0UL); + + /* Enable SysTick IRQ and SysTick Timer */ + SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk)); + + /* Function successful */ + return (0UL); } /** @@ -436,6 +452,52 @@ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) } } +/** + * @brief Get the SysTick clock source configuration. + * @retval SysTick clock source that can be one of the following values: + * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + */ +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void) +{ + uint32_t systick_source; + uint32_t systick_rcc_source; + + /* Read SysTick->CTRL register for internal or external clock source */ + if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U) + { + /* Internal clock source */ + systick_source = SYSTICK_CLKSOURCE_HCLK; + } + else + { + /* External clock source, check the selected one in RCC */ + systick_rcc_source = READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL); + + switch (systick_rcc_source) + { + case (0x00000000U): + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + + case (RCC_CCIPR4_SYSTICKSEL_0): + systick_source = SYSTICK_CLKSOURCE_LSI; + break; + + case (RCC_CCIPR4_SYSTICKSEL_1): + systick_source = SYSTICK_CLKSOURCE_LSE; + break; + + default: + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + } + } + return systick_source; +} + /** * @brief Handle SYSTICK interrupt request. * @retval None @@ -573,6 +635,82 @@ void HAL_MPU_Disable_NS(void) } #endif /* __ARM_FEATURE_CMSE */ +/** + * @brief Enable the MPU Region. + * @param RegionNumber Specifies the index of the region to enable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the MPU_NS Region. + * @param RegionNumber Specifies the index of the region to enable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + * @retval None + */ +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER_NS(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable the MPU Region. + * @param RegionNumber Specifies the index of the region to disable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable the MPU_NS Region. + * @param RegionNumber Specifies the index of the region to disable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + * @retval None + */ +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER_NS(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /* __ARM_FEATURE_CMSE */ + /** * @brief Initialize and configure the Region and the memory to be protected. * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains @@ -650,6 +788,9 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const #endif /* __ARM_FEATURE_CMSE */ assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number)); assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ __DMB(); @@ -657,27 +798,17 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const /* Set the Region number */ MPUx->RNR = pMPU_RegionInit->Number; - if (pMPU_RegionInit->Enable != MPU_REGION_DISABLE) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); - assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); - - MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) | - ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | - ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | - ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); - - MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | - ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | - ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); - } - else - { - MPUx->RLAR = 0U; - MPUx->RBAR = 0U; - } + /* Disable the Region */ + CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk); + + MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | + ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | + ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); + + MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | + ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); } /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c index 279007d82d..0b280ef1ff 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c @@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + CLEAR_REG(hcrc->Instance->IDR); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c index e712ccc5e6..179643cf84 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c @@ -2005,26 +2005,30 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { + uint32_t itsource = hcryp->Instance->IER; + uint32_t itflagsr = hcryp->Instance->SR; + uint32_t itflagisr = hcryp->Instance->ISR; + /* Check if Read or write error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET) + if ((itsource & CRYP_IT_RWEIE) != 0U) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET) + if ((itflagsr & CRYP_FLAG_WRERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET) + if ((itflagsr & CRYP_FLAG_RDERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } } /* Check if Key error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET) + if ((itsource & CRYP_IT_KEIE) != 0U) { - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET) + if ((itflagisr & CRYP_FLAG_KEIF) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF); @@ -2033,9 +2037,9 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) } } - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET) + if ((itflagisr & CRYP_FLAG_CCF) != 0U) { - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + if ((itsource & CRYP_IT_CCFIE) != 0U) { /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dcache.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dcache.c index 5fd484fa6f..4e5881f3d7 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dcache.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dcache.c @@ -943,6 +943,22 @@ uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_HandleTypeDef *hdcach return hdcache->Instance->WMMONR; } +/** + * @} + */ + +/** @addtogroup DCACHE_Exported_Functions_Group3 + * +@verbatim + ============================================================================== + ##### DCACHE IRQ Handler and Callback functions ##### + ============================================================================== + [..] + This section provides functions allowing to treat ISR and provide user callback +@endverbatim + * @{ + */ + /** * @brief Handle the Data Cache interrupt request. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains @@ -1321,7 +1337,7 @@ __weak void HAL_DCACHE_ErrorCallback(DCACHE_HandleTypeDef *hdcache) * @} */ -/** @addtogroup DCACHE_Exported_Functions_Group3 +/** @addtogroup DCACHE_Exported_Functions_Group4 * @verbatim =============================================================================== @@ -1359,6 +1375,10 @@ uint32_t HAL_DCACHE_GetError(const DCACHE_HandleTypeDef *hdcache) return hdcache->ErrorCode; } +/** + * @} + */ + /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c index 98f3c89a5a..e29c115476 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c @@ -22,7 +22,7 @@ ********************************************************************************************************************** @verbatim ====================================================================================================================== - ############### How to use this driver ############### + ##### How to use this driver ##### ====================================================================================================================== @@ -96,8 +96,9 @@ (++) can be a value of DMA_Transfer_Event_Mode (+) Mode : Specifies the transfer mode for the DMA channel - (++) can be a value of DMA_Transfer_Mode - + (++) can be one of the following modes : + (+++) DMA_NORMAL : Normal Mode + (+++) DMA_PFCTRL : Peripheral Flow Control (peripheral early termination) Mode *** Polling mode IO operation *** ================================= @@ -218,7 +219,7 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma); * @verbatim ====================================================================================================================== - ############### Initialization and de-initialization functions ############### + ##### Initialization and de-initialization functions ##### ====================================================================================================================== [..] This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode. @@ -252,7 +253,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - if ((hdma->Init.Direction == DMA_MEMORY_TO_PERIPH) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)) + if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) { assert_param(IS_DMA_REQUEST(hdma->Init.Request)); } @@ -264,6 +265,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); + if (hdma->Init.Mode == DMA_PFCTRL) + { + assert_param(IS_DMA_PFREQ_INSTANCE(hdma->Instance)); + } /* Check DMA channel instance */ if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) { @@ -379,7 +384,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Clear secure attribute */ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | @@ -423,7 +428,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### IO operation functions ############### + ##### IO operation functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -892,14 +897,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Global Interrupt Flag management *********************************************************************************/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) #else if (global_active_flag_ns == 0U) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { return; /* the global interrupt flag for the current channel is down , nothing to do */ } @@ -996,16 +1001,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /* Reset the channel internal state and reset the FIFO */ hdma->Instance->CCR |= DMA_CCR_RESET; - if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - } - else - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - } + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; /* Check DMA channel transfer mode */ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) @@ -1097,16 +1094,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /* Reset the channel internal state and reset the FIFO */ hdma->Instance->CCR |= DMA_CCR_RESET; - if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - } - else - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - } + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; /* Check DMA channel transfer mode */ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) @@ -1303,7 +1292,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, * @verbatim ====================================================================================================================== - ############### State and Errors functions ############### + ##### State and Errors functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1349,7 +1338,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma) * @verbatim ====================================================================================================================== - ############### DMA Attributes functions ############### + ##### DMA Attributes functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1456,7 +1445,7 @@ HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); } } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ return HAL_OK; } @@ -1490,7 +1479,7 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co /* Get DMA channel privilege attribute */ attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined (DMA_SECCFGR_SEC0) /* Get DMA channel security attribute */ attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; @@ -1499,8 +1488,8 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co /* Get DMA channel destination security attribute */ attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC; +#endif /* DMA_SECCFGR_SEC0 */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* return value */ *pChannelAttributes = attributes; @@ -1538,7 +1527,7 @@ HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const h return HAL_OK; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Get the security and privilege attribute lock state of a DMA channel. @@ -1571,7 +1560,7 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons return HAL_OK; } -#endif /* defined (DMA_RCFGLOCKR_LOCK0) */ +#endif /* DMA_RCFGLOCKR_LOCK0 */ /** * @} */ @@ -1647,7 +1636,7 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma) MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); #else WRITE_REG(hdma->Instance->CTR1, tmpreg); -#endif /* defined (DMA_CTR1_SSEC) */ +#endif /* DMA_CTR1_SSEC */ /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/ tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c index af64585273..21d339b5b0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c @@ -25,7 +25,7 @@ ********************************************************************************************************************** @verbatim ====================================================================================================================== - ############### How to use this driver ############### + ##### How to use this driver ##### ====================================================================================================================== [..] Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as @@ -581,7 +581,7 @@ static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList); * @verbatim ====================================================================================================================== - ############### Linked-List Initialization and De-Initialization Functions ############### + ##### Linked-List Initialization and De-Initialization Functions ##### ====================================================================================================================== [..] This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode. @@ -676,7 +676,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) /* Get DMA instance */ DMA_TypeDef *p_dma_instance; - /* Get tick number */ uint32_t tickstart = HAL_GetTick(); @@ -693,7 +692,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) /* Get DMA instance */ p_dma_instance = GET_DMA_INSTANCE(hdma); - /* Disable the selected DMA Channel */ __HAL_DMA_DISABLE(hdma); @@ -738,7 +736,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Clear secure attribute */ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | @@ -790,7 +788,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Linked-List IO Operation Functions ############### + ##### Linked-List IO Operation Functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -956,7 +954,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Linked-List Management Functions ############### + ##### Linked-List Management Functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1103,7 +1101,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure)); assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure)); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Build the DMA channel node */ DMA_List_BuildNode(pNodeConfig, pNode); @@ -3223,7 +3221,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Data handling, repeated block and trigger configuration functions ############### + ##### Data handling, repeated block and trigger configuration functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -3449,7 +3447,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, * @verbatim ====================================================================================================================== - ############### Suspend and resume operation functions ############### + ##### Suspend and resume operation functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -3612,7 +3610,7 @@ HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Fifo status function ############### + ##### Fifo status function ##### ====================================================================================================================== [..] This section provides function allowing to get DMA channel FIFO level. @@ -3734,7 +3732,7 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, { pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Add parameters related to DMA configuration */ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) @@ -3972,7 +3970,7 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, { pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*********************************************************************************** CTR1 fields values are updated */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c index 6f650307a9..d04ecc6f43 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth.c @@ -250,12 +250,13 @@ /** @defgroup ETH_Private_Functions ETH Private Functions * @{ */ -static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); -static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf); +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf); static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth); static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth); static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth); -static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode); +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, + uint32_t ItMode); static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) @@ -336,7 +337,6 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) __HAL_RCC_SBS_CLK_ENABLE(); - if (heth->Init.MediaInterface == HAL_ETH_MII_MODE) { HAL_SBS_ETHInterfaceSelect(SBS_ETH_MII); @@ -411,6 +411,14 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]); + /* Disable Rx MMC Interrupts */ + SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \ + ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM); + + /* Disable Tx MMC Interrupts */ + SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \ + ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM); + heth->ErrorCode = HAL_ETH_ERROR_NONE; heth->gState = HAL_ETH_STATE_READY; @@ -712,7 +720,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) { heth->gState = HAL_ETH_STATE_BUSY; - /* Set nombre of descriptors to build */ + /* Set number of descriptors to build */ heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; /* Build all descriptors */ @@ -760,29 +768,13 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) /* save IT mode to ETH Handle */ heth->RxDescList.ItMode = 1U; - /* Disable Rx MMC Interrupts */ - SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \ - ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM); - /* Disable Tx MMC Interrupts */ - SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \ - ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM); - - /* Set nombre of descriptors to build */ + /* Set number of descriptors to build */ heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; /* Build all descriptors */ ETH_UpdateDescriptor(heth); - /* Enable the MAC transmission */ - SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); - - /* Enable the MAC reception */ - SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); - - /* Set the Flush Transmit FIFO bit */ - SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); - /* Enable the DMA transmission */ SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); @@ -791,6 +783,16 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) /* Clear Tx and Rx process stopped flags */ heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS); + + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + /* Enable ETH DMA interrupts: - Tx complete interrupt - Rx complete interrupt @@ -914,7 +916,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) * @param Timeout: timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout) +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout) { uint32_t tickstart; ETH_DMADescTypeDef *dmatxdesc; @@ -989,7 +991,7 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig * * @param pTxConfig: Hold the configuration of packet to be transmitted * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig) +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig) { if (pTxConfig == NULL) { @@ -1079,12 +1081,12 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) heth->RxDescList.RxDataLength = 0; } + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; + /* Check if last descriptor */ - bufflength = heth->Init.RxBuffLen; if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET) { - bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; - /* Save Last descriptor index */ heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3; @@ -1150,6 +1152,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) { uint32_t descidx; + uint32_t tailidx; uint32_t desccount; ETH_DMADescTypeDef *dmarxdesc; uint8_t *buff = NULL; @@ -1185,8 +1188,6 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (allocStatus != 0U) { - /* Ensure rest of descriptor is written to RAM before the OWN bit */ - __DMB(); if (heth->RxDescList.ItMode != 0U) { @@ -1207,8 +1208,14 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (heth->RxDescList.RxBuildDescCnt != desccount) { + /* Set the tail pointer index */ + tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + + /* DMB instruction to avoid race condition */ + __DMB(); + /* Set the Tail pointer address */ - WRITE_REG(heth->Instance->DMACRDTPR, 0U); + WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (tailidx)))); heth->RxDescList.RxBuildDescIdx = descidx; heth->RxDescList.RxBuildDescCnt = desccount; @@ -1327,7 +1334,7 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth) * @param pErrorCode: pointer to uint32_t to hold the error code * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode) +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode) { /* Get error bits. */ *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK); @@ -1410,7 +1417,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) if (dmatxdesclist->PacketAddress[idx] == NULL) { /* No packet in use, skip to next. */ - idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + INCR_TX_DESC_INDEX(idx, 1U); pktInUse = 0U; } @@ -1420,20 +1427,32 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U) { #ifdef HAL_ETH_USE_PTP + /* Disable Ptp transmission */ CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U)); - /* Get timestamp low */ - timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0; - /* Get timestamp high */ - timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1; + if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD) + && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS)) + { + /* Get timestamp low */ + timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1; + } + else + { + timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX; + } #endif /* HAL_ETH_USE_PTP */ #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /*Call registered callbacks*/ #ifdef HAL_ETH_USE_PTP /* Handle Ptp */ - heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); + if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX) + { + heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); + } #endif /* HAL_ETH_USE_PTP */ /* Release the packet. */ heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]); @@ -1441,7 +1460,10 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) /* Call callbacks */ #ifdef HAL_ETH_USE_PTP /* Handle Ptp */ - HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); + if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX) + { + HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); + } #endif /* HAL_ETH_USE_PTP */ /* Release the packet. */ HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); @@ -1451,7 +1473,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) dmatxdesclist->PacketAddress[idx] = NULL; /* Update the transmit relesae index and number of buffers in use. */ - idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + INCR_TX_DESC_INDEX(idx, 1U); dmatxdesclist->BuffersInUse = numOfBuf; dmatxdesclist->releaseIndex = idx; } @@ -1511,25 +1533,24 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT if (ptpconfig->TimestampAddendUpdate == ENABLE) { SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG); - while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0) {} - } + while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0) + { - /* Enable Update mode */ - if (ptpconfig->TimestampUpdateMode == ENABLE) - { - SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT); + } } - /* Initialize Time */ - time.Seconds = 0; - time.NanoSeconds = 0; - HAL_ETH_PTP_SetTime(heth, &time); - /* Ptp Init */ SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); /* Set PTP Configuration done */ - heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURATED; + heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED; + + /* Set Seconds */ + time.Seconds = heth->Instance->MACSTSR; + /* Set NanoSeconds */ + time.NanoSeconds = heth->Instance->MACSTNR; + + HAL_ETH_PTP_SetTime(heth, &time); /* Return function status */ return HAL_OK; @@ -1589,13 +1610,13 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT * @brief Set Seconds and Nanoseconds for the Ethernet PTP registers. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param heth: pointer to a ETH_TimeTypeDef structure that contains + * @param time: pointer to a ETH_TimeTypeDef structure that contains * time to set * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) { - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) { /* Set Seconds */ heth->Instance->MACSTSUR = time->Seconds; @@ -1603,6 +1624,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef * /* Set NanoSeconds */ heth->Instance->MACSTNUR = time->NanoSeconds; + /* the system time is updated */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT); + /* Return function status */ return HAL_OK; } @@ -1617,19 +1641,18 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef * * @brief Get Seconds and Nanoseconds for the Ethernet PTP registers. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param heth: pointer to a ETH_TimeTypeDef structure that contains + * @param time: pointer to a ETH_TimeTypeDef structure that contains * time to get * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) { - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) { /* Get Seconds */ - time->Seconds = heth->Instance->MACSTSUR; - + time->Seconds = heth->Instance->MACSTSR; /* Get NanoSeconds */ - time->NanoSeconds = heth->Instance->MACSTNUR; + time->NanoSeconds = heth->Instance->MACSTNR; /* Return function status */ return HAL_OK; @@ -1645,14 +1668,14 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef * * @brief Update time for the Ethernet PTP registers. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param timeupdate: pointer to a ETH_TIMEUPDATETypeDef structure that contains + * @param timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains * the time update information * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, ETH_TimeTypeDef *timeoffset) { - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) { if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE) { @@ -1678,6 +1701,8 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda heth->Instance->MACSTNUR = timeoffset->NanoSeconds; } + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT); + /* Return function status */ return HAL_OK; } @@ -1692,7 +1717,6 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda * @brief Insert Timestamp in transmission. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param txtimestampconf: Enable or Disable timestamp in transmission * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth) @@ -1701,7 +1725,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth) uint32_t descidx = dmatxdesclist->CurTxDesc; ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) { /* Enable Time Stamp transmission */ SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE); @@ -1730,7 +1754,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeSt uint32_t idx = dmatxdesclist->releaseIndex; ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx]; - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) { /* Get timestamp low */ timestamp->TimeStampLow = dmatxdesc->DESC0; @@ -1757,7 +1781,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeSt */ HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) { - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) { /* Get timestamp low */ timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow; @@ -1811,6 +1835,8 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth) /** * @brief Tx Ptp callback. * @param buff: pointer to application buffer + * @param timestamp: pointer to ETH_TimeStampTypeDef structure that contains + * transmission timestamp * @retval None */ __weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) @@ -1831,87 +1857,79 @@ __weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestam */ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) { - uint32_t macirqenable; + uint32_t mac_flag = READ_REG(heth->Instance->MACISR); + uint32_t dma_flag = READ_REG(heth->Instance->DMACSR); + uint32_t dma_itsource = READ_REG(heth->Instance->DMACIER); + uint32_t exti_flag = READ_REG(EXTI->RPR2); /* Packet received */ - if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI)) + if (((dma_flag & ETH_DMACSR_RI) != 0U) && ((dma_itsource & ETH_DMACIER_RIE) != 0U)) { - if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE)) - { - /* Clear the Eth DMA Rx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS); + /* Clear the Eth DMA Rx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered Receive complete callback*/ - heth->RxCpltCallback(heth); + /*Call registered Receive complete callback*/ + heth->RxCpltCallback(heth); #else - /* Receive complete callback */ - HAL_ETH_RxCpltCallback(heth); + /* Receive complete callback */ + HAL_ETH_RxCpltCallback(heth); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - } } /* Packet transmitted */ - if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI)) + if (((dma_flag & ETH_DMACSR_TI) != 0U) && ((dma_itsource & ETH_DMACIER_TIE) != 0U)) { - if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE)) - { - /* Clear the Eth DMA Tx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS); + /* Clear the Eth DMA Tx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered Transmit complete callback*/ - heth->TxCpltCallback(heth); + /*Call registered Transmit complete callback*/ + heth->TxCpltCallback(heth); #else - /* Transfer complete callback */ - HAL_ETH_TxCpltCallback(heth); + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback(heth); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - } } /* ETH DMA Error */ - if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS)) + if (((dma_flag & ETH_DMACSR_AIS) != 0U) && ((dma_itsource & ETH_DMACIER_AIE) != 0U)) { - if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE)) + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + /* if fatal bus error occurred */ + if ((dma_flag & ETH_DMACSR_FBE) != 0U) { - heth->ErrorCode |= HAL_ETH_ERROR_DMA; - /* if fatal bus error occurred */ - if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE)) - { - /* Get DMA error code */ - heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS)); + /* Get DMA error code */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS)); - /* Disable all interrupts */ - __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE); + /* Disable all interrupts */ + __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE); - /* Set HAL state to ERROR */ - heth->gState = HAL_ETH_STATE_ERROR; - } - else - { - /* Get DMA error status */ - heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | - ETH_DMACSR_RBU | ETH_DMACSR_AIS)); + /* Set HAL state to ERROR */ + heth->gState = HAL_ETH_STATE_ERROR; + } + else + { + /* Get DMA error status */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | + ETH_DMACSR_RBU | ETH_DMACSR_AIS)); - /* Clear the interrupt summary flag */ - __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | - ETH_DMACSR_RBU | ETH_DMACSR_AIS)); - } + /* Clear the interrupt summary flag */ + __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | + ETH_DMACSR_RBU | ETH_DMACSR_AIS)); + } #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /* Call registered Error callback*/ - heth->ErrorCallback(heth); + /* Call registered Error callback*/ + heth->ErrorCallback(heth); #else - /* Ethernet DMA Error callback */ - HAL_ETH_ErrorCallback(heth); + /* Ethernet DMA Error callback */ + HAL_ETH_ErrorCallback(heth); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - } } /* ETH MAC Error IT */ - macirqenable = heth->Instance->MACIER; - if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \ - ((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE)) + if (((mac_flag & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \ + ((mac_flag & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE)) { heth->ErrorCode |= HAL_ETH_ERROR_MAC; @@ -1931,7 +1949,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) } /* ETH PMT IT */ - if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT)) + if ((mac_flag & ETH_MAC_PMT_IT) != 0U) { /* Get MAC Wake-up source and clear the status register pending bit */ heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD)); @@ -1948,7 +1966,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) } /* ETH EEE IT */ - if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT)) + if ((mac_flag & ETH_MAC_LPI_IT) != 0U) { /* Get MAC LPI interrupt source and clear the status register pending bit */ heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU); @@ -1965,7 +1983,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) } /* check ETH WAKEUP exti flag */ - if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + if ((exti_flag & ETH_WAKEUP_EXTI_LINE) != 0U) { /* Clear ETH WAKEUP Exti pending bit */ __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); @@ -2124,7 +2142,6 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA return HAL_OK; } - /** * @brief Writes to a PHY register. * @param heth: pointer to a ETH_HandleTypeDef structure that contains @@ -2206,7 +2223,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32 * the configuration of the MAC. * @retval HAL Status */ -HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) { if (macconf == NULL) { @@ -2278,7 +2295,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp * the configuration of the ETH DMA. * @retval HAL Status */ -HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) { if (dmaconf == NULL) { @@ -2301,7 +2318,6 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE; dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL); - return HAL_OK; } @@ -2380,34 +2396,34 @@ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) hclk = HAL_RCC_GetHCLKFreq(); /* Set CR bits depending on hclk value */ - if ((hclk >= 20000000U) && (hclk < 35000000U)) + if (hclk < 35000000U) { - /* CSR Clock Range between 20-35 MHz */ + /* CSR Clock Range between 0-35 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16; } - else if ((hclk >= 35000000U) && (hclk < 60000000U)) + else if (hclk < 60000000U) { /* CSR Clock Range between 35-60 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26; } - else if ((hclk >= 60000000U) && (hclk < 100000000U)) + else if (hclk < 100000000U) { /* CSR Clock Range between 60-100 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; } - else if ((hclk >= 100000000U) && (hclk < 150000000U)) + else if (hclk < 150000000U) { /* CSR Clock Range between 100-150 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62; } - else if ((hclk >= 150000000U) && (hclk <= 250000000U)) + else if (hclk < 250000000U) { - /* CSR Clock Range between 150-200 MHz */ + /* CSR Clock Range between 150-250 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102; } - else /*(hclk >= 250000000U) && (hclk <= 300000000U)*/ + else /* (hclk >= 250000000U) */ { - /* CSR Clock Range between 250-300 MHz */ + /* CSR Clock >= 250 MHz */ tmpreg |= (uint32_t)(ETH_MACMDIOAR_CR_DIV124); } @@ -2457,7 +2473,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_ * the configuration of the ETH MAC filters. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) { if (pFilterConfig == NULL) { @@ -2730,8 +2746,7 @@ uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth) * @{ */ - -static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf) { uint32_t macregval; @@ -2778,7 +2793,6 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac /* Write to MACWTR */ MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval); - /*------------------------ MACTFCR Configuration --------------------*/ macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | macconf->PauseLowThreshold | @@ -2809,7 +2823,7 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval); } -static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf) { uint32_t dmaregval; @@ -2916,7 +2930,6 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) ETH_SetDMAConfig(heth, &dmaDefaultConf); } - /** * @brief Initializes the DMA Tx descriptors. * called by HAL_ETH_Init() API. @@ -2978,7 +2991,6 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) WRITE_REG(dmarxdesc->BackupAddr0, 0x0U); WRITE_REG(dmarxdesc->BackupAddr1, 0x0U); - /* Set Rx descritors addresses */ WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); @@ -3009,7 +3021,8 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) * @param ItMode: Enable or disable Tx EOT interrept * @retval Status */ -static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode) +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, + uint32_t ItMode) { ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; uint32_t descidx = dmatxdesclist->CurTxDesc; @@ -3020,6 +3033,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; uint32_t bd_count = 0; + uint32_t primask_bit; /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) @@ -3277,14 +3291,15 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; dmatxdesclist->CurTxDesc = descidx; - /* disable the interrupt */ - __disable_irq(); - dmatxdesclist->BuffersInUse += bd_count + 1U; + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1); - /* Enable interrupts back */ - __enable_irq(); + dmatxdesclist->BuffersInUse += bd_count + 1U; + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); /* Return function status */ return HAL_ETH_ERROR_NONE; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c index 0a22cc5ae2..e4fa9d76df 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_eth_ex.c @@ -56,6 +56,9 @@ #define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \ ETH_MACVIR_VLP | ETH_MACVIR_VLC) + +#define ETH_MAC_L4_SRSP_MASK 0x0000FFFFU +#define ETH_MAC_L4_DSTP_MASK 0xFFFF0000U /** * @} */ @@ -133,25 +136,34 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress) * @retval HAL status */ HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, - ETH_L4FilterConfigTypeDef *pL4FilterConfig) + const ETH_L4FilterConfigTypeDef *pL4FilterConfig) { - __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)); - if (pL4FilterConfig == NULL) { return HAL_ERROR; } - /* Write configuration to (MACL3L4C0R + filter )register */ - MODIFY_REG(*configreg, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol | - pL4FilterConfig->SrcPortFilterMatch | - pL4FilterConfig->DestPortFilterMatch)); + if (Filter == ETH_L4_FILTER_0) + { + /* Write configuration to MACL3L4C0R register */ + MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol | + pL4FilterConfig->SrcPortFilterMatch | + pL4FilterConfig->DestPortFilterMatch)); - configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)); + /* Write configuration to MACL4A0R register */ + WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16))); - /* Write configuration to (MACL4A0R + filter )register */ - MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP), (pL4FilterConfig->SourcePort | - (pL4FilterConfig->DestinationPort << 16))); + } + else /* Filter == ETH_L4_FILTER_1 */ + { + /* Write configuration to MACL3L4C1R register */ + MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol | + pL4FilterConfig->SrcPortFilterMatch | + pL4FilterConfig->DestPortFilterMatch)); + + /* Write configuration to MACL4A1R register */ + WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16))); + } /* Enable L4 filter */ SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); @@ -172,7 +184,7 @@ HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t * that contains L4 filter configuration. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, +HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig) { if (pL4FilterConfig == NULL) @@ -180,18 +192,32 @@ HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t return HAL_ERROR; } - /* Get configuration to (MACL3L4C0R + filter )register */ - pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), - ETH_MACL3L4CR_L4PEN); - pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), - (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)); - pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), - (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM)); - - /* Get configuration to (MACL3L4C0R + filter )register */ - pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), - ETH_MACL4AR_L4DP) >> 16); - pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP); + if (Filter == ETH_L4_FILTER_0) + { + /* Get configuration from MACL3L4C0R register */ + pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C0R, ETH_MACL3L4CR_L4PEN); + pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R, + (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)); + pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R, + (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM)); + + /* Get configuration from MACL4A0R register */ + pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_DSTP_MASK) >> 16); + pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_SRSP_MASK); + } + else /* Filter == ETH_L4_FILTER_1 */ + { + /* Get configuration from MACL3L4C1R register */ + pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C1R, ETH_MACL3L4CR_L4PEN); + pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R, + (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)); + pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R, + (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM)); + + /* Get configuration from MACL4A1R register */ + pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_DSTP_MASK) >> 16); + pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_SRSP_MASK); + } return HAL_OK; } @@ -210,43 +236,83 @@ HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t * @retval HAL status */ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, - ETH_L3FilterConfigTypeDef *pL3FilterConfig) + const ETH_L3FilterConfigTypeDef *pL3FilterConfig) { - __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)); - if (pL3FilterConfig == NULL) { return HAL_ERROR; } - /* Write configuration to (MACL3L4C0R + filter )register */ - MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol | - pL3FilterConfig->SrcAddrFilterMatch | - pL3FilterConfig->DestAddrFilterMatch | - (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) | - (pL3FilterConfig->DestAddrHigherBitsMatch << 11))); + if (Filter == ETH_L3_FILTER_0) + { + /* Write configuration to MACL3L4C0R register */ + MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol | + pL3FilterConfig->SrcAddrFilterMatch | + pL3FilterConfig->DestAddrFilterMatch | + (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) | + (pL3FilterConfig->DestAddrHigherBitsMatch << 11))); + } + else /* Filter == ETH_L3_FILTER_1 */ + { + /* Write configuration to MACL3L4C1R register */ + MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol | + pL3FilterConfig->SrcAddrFilterMatch | + pL3FilterConfig->DestAddrFilterMatch | + (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) | + (pL3FilterConfig->DestAddrHigherBitsMatch << 11))); + } - /* Check if IPv6 protocol is selected */ - if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + if (Filter == ETH_L3_FILTER_0) { - /* Set the IPv6 address match */ - /* Set Bits[31:0] of 128-bit IP addr */ - *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0]; - /* Set Bits[63:32] of 128-bit IP addr */ - *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1]; - /* update Bits[95:64] of 128-bit IP addr */ - *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2]; - /* update Bits[127:96] of 128-bit IP addr */ - *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3]; + /* Check if IPv6 protocol is selected */ + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + { + /* Set the IPv6 address match */ + /* Set Bits[31:0] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]); + /* Set Bits[63:32] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]); + /* update Bits[95:64] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]); + /* update Bits[127:96] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]); + } + else /* IPv4 protocol is selected */ + { + /* Set the IPv4 source address match */ + WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr); + /* Set the IPv4 destination address match */ + WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr); + } } - else /* IPv4 protocol is selected */ + else /* Filter == ETH_L3_FILTER_1 */ { - /* Set the IPv4 source address match */ - *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr; - /* Set the IPv4 destination address match */ - *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr; + /* Check if IPv6 protocol is selected */ + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + { + /* Set the IPv6 address match */ + /* Set Bits[31:0] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]); + /* Set Bits[63:32] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[1]); + /* update Bits[95:64] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[2]); + /* update Bits[127:96] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[3]); + } + else /* IPv4 protocol is selected */ + { + /* Set the IPv4 source address match */ + WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4SrcAddr); + /* Set the IPv4 destination address match */ + WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4DestAddr); + + } } + /* Enable L3 filter */ + SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); + return HAL_OK; } @@ -263,14 +329,13 @@ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t * that will contain the L3 filter configuration. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, +HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig) { if (pL3FilterConfig == NULL) { return HAL_ERROR; } - pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN); pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), @@ -282,17 +347,35 @@ HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11); - if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + if (Filter == ETH_L3_FILTER_0) { - pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)); - pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)); - pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)); - pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)); + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + { + WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R0R); + WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R0R); + WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R0R); + WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R0R); + } + else + { + WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R0R); + WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R0R); + } } - else + else /* ETH_L3_FILTER_1 */ { - pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)); - pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)); + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + { + WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R1R); + WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R1R); + WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R1R); + WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R1R); + } + else + { + WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R1R); + WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R1R); + } } return HAL_OK; @@ -330,7 +413,7 @@ void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth) * that will contain the VLAN filter configuration. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig) +HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig) { if (pVlanConfig == NULL) { @@ -340,12 +423,14 @@ HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE; pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS); - pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE; + pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE; pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE; pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE; - pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE; pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS); pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)); @@ -407,7 +492,7 @@ void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable) * that will contain the Tx VLAN filter configuration. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, +HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag, ETH_TxVLANConfigTypeDef *pVlanConfig) { if (pVlanConfig == NULL) @@ -443,7 +528,7 @@ HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL * @retval HAL Status */ HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, - ETH_TxVLANConfigTypeDef *pVlanConfig) + const ETH_TxVLANConfigTypeDef *pVlanConfig) { if (VLANTag == ETH_INNER_TX_VLANTAG) { @@ -544,7 +629,6 @@ void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth) __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE); } - /** * @brief Returns the ETH MAC LPI event * @param heth: pointer to a ETH_HandleTypeDef structure that contains diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fdcan.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fdcan.c index 7f07b83f0a..68c573d403 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fdcan.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fdcan.c @@ -253,7 +253,7 @@ static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, * @{ */ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan); -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, const uint8_t *pTxData, uint32_t BufferIndex); /** * @} @@ -3474,7 +3474,7 @@ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) * @param BufferIndex index of the buffer to be configured. * @retval none */ -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, const uint8_t *pTxData, uint32_t BufferIndex) { uint32_t TxElementW1; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c index f656b915fb..ae7425ca07 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c @@ -362,6 +362,7 @@ void HAL_FLASH_IRQHandler(void) __IO uint32_t *reg_cr; __IO uint32_t *reg_ccr; const __IO uint32_t *reg_sr; + const __IO uint32_t *reg_ecccorr; /* Access to CR, CCR and SR registers depends on operation type */ #if defined (FLASH_OPTSR2_TZEN) @@ -373,6 +374,7 @@ void HAL_FLASH_IRQHandler(void) reg_ccr = &(FLASH_NS->NSCCR); reg_sr = &(FLASH_NS->NSSR); #endif /* FLASH_OPTSR2_TZEN */ + reg_ecccorr = &(FLASH->ECCCORR); /* Save Flash errors */ errorflag = (*reg_sr) & FLASH_FLAG_SR_ERRORS; @@ -460,6 +462,16 @@ void HAL_FLASH_IRQHandler(void) HAL_FLASH_EndOfOperationCallback(param); } + /* Check FLASH ECC correction flag */ + if ((*reg_ecccorr & FLASH_ECCR_ECCC) != 0U) + { + /* Call User callback */ + HAL_FLASHEx_EccCorrectionCallback(); + + /* Clear ECC correction flag in order to allow new ECC error record */ + FLASH->ECCCORR |= FLASH_ECCR_ECCC; + } + if (pFlash.ProcedureOnGoing == 0U) { /* Disable Flash Operation and Error source interrupt */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c index d1cdf324f6..2d83c5411c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c @@ -1380,6 +1380,18 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig1, uint32_ } #endif /* FLASH_OPTSR2_SRAM1_ECC */ +#if defined (FLASH_OPTSR2_USBPD_DIS) + if ((UserType & OB_USER_USBPD_DIS) != 0U) + { + /* USBPD_DIS option byte should be modified */ + assert_param(IS_OB_USER_USBPD_DIS(UserConfig2 & FLASH_OPTSR2_USBPD_DIS)); + + /* Set value and mask for USBPD_DIS option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_USBPD_DIS); + optr_reg2_mask |= FLASH_OPTSR2_USBPD_DIS; + } +#endif /* FLASH_OPTSR2_USBPD_DIS */ + #if defined (FLASH_OPTSR2_TZEN) if ((UserType & OB_USER_TZEN) != 0U) { @@ -1714,6 +1726,15 @@ static void FLASH_OB_GetHDP(uint32_t Bank, uint32_t *HDPStartSector, uint32_t *H * * @param EDATASize specifies the size (in sectors) of the Flash high-cycle data area * This parameter can be sectors number between 0 and 8 + * 0: Disable all EDATA sectors. + * 1: The last sector is reserved for flash high-cycle data. + * 2: The two last sectors are reserved for flash high-cycle data. + * 3: The three last sectors are reserved for flash high-cycle data + * 4: The four last sectors is reserved for flash high-cycle data. + * 5: The five last sectors are reserved for flash high-cycle data. + * 6: The six last sectors are reserved for flash high-cycle data. + * 7: The seven last sectors are reserved for flash high-cycle data. + * 8: The eight last sectors are reserved for flash high-cycle data. * * @retval None */ @@ -1743,13 +1764,13 @@ static void FLASH_OB_EDATAConfig(uint32_t Banks, uint32_t EDATASize) /* Write EDATA registers */ if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) { - /* de-activate Flash high-cycle data for bank 1 */ + /* Disable Flash high-cycle data for bank 1 */ FLASH->EDATA1R_PRG = 0U; } if ((Banks & FLASH_BANK_2) == FLASH_BANK_2) { - /* de-activate Flash high-cycle data for bank 2 */ + /* Disable Flash high-cycle data for bank 2 */ FLASH->EDATA2R_PRG = 0U; } } @@ -1783,14 +1804,211 @@ static void FLASH_OB_GetEDATA(uint32_t Bank, uint32_t *EDATASize) } /* Get configuration of secure area */ - *EDATASize = (regvalue & FLASH_EDATAR_EDATA_STRT); + if ((regvalue & FLASH_EDATAR_EDATA_EN) != 0U) + { + /* Encoding of Edata Area size is register value + 1 */ + *EDATASize = (regvalue & FLASH_EDATAR_EDATA_STRT) + 1U; + } + else + { + /* No defined Edata area */ + *EDATASize = 0U; + } + +} +#endif /* FLASH_EDATAR_EDATA_EN */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group3 Extended ECC operation functions + * @brief Extended ECC operation functions + * +@verbatim + =============================================================================== + ##### Extended ECC operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + ECC Operations. + +@endverbatim + * @{ + */ +/** + * @brief Enable ECC correction interrupt + * @param None + * @retval None + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ECCC); } + +/** + * @brief Disable ECC correction interrupt + * @param None + * @retval None + */ +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ECCC); +} + +/** + * @brief Get the ECC error information. + * @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the + * ECC error information. + * @note This function should be called before ECC bit is cleared + * (in callback function) + * @retval None + */ +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData) +{ + uint32_t correction_reg = FLASH->ECCCORR; + uint32_t detection_reg = FLASH->ECCDETR; + uint32_t data_reg = FLASH->ECCDR; + uint32_t addr_reg = 0xFFFFFFFFU; + + /* Check if the operation is a correction or a detection*/ + if ((correction_reg & FLASH_ECCR_ECCC) != 0U) + { + /* Get area and offset address values from ECCCORR register*/ + pData->Area = correction_reg & (~(FLASH_ECCR_ECCIE | FLASH_ECCR_ADDR_ECC | FLASH_ECCR_ECCC)); + addr_reg = (correction_reg & FLASH_ECCR_ADDR_ECC); + } + else if ((detection_reg & FLASH_ECCR_ECCD) != 0U) + { + /* Get area and offset address values from ECCDETR register */ + pData->Area = detection_reg & (~(FLASH_ECCR_ADDR_ECC | FLASH_ECCR_ECCD)); + addr_reg = (detection_reg & FLASH_ECCR_ADDR_ECC); + } + else + { + /* Do nothing */ + } + + /* Check that an ECC single or double error has occurred to continue the calculation of area address */ + if (addr_reg != 0xFFFFFFFFU) + { + /* Get address value according to area value*/ + switch (pData->Area) + { + case FLASH_ECC_AREA_USER_BANK1: + /* + * One error detection/correction or two error detections per 128-bit flash word + * Therefore, the address returned by ECC registers in bank1 represents 128-bit flash word, + * to get the correct address value, we must do a shift by 4 bits + */ + addr_reg = addr_reg << 4U; + pData->Address = FLASH_BASE + addr_reg; + break; + case FLASH_ECC_AREA_USER_BANK2: + /* + * One error detection/correction or two error detections per 128-bit flash word + * Therefore, the address returned by ECC registers in bank2 represents 128-bit flash word, + * to get the correct address value, we must do a shift by 4 bits + */ + addr_reg = addr_reg << 4U; + pData->Address = FLASH_BASE + FLASH_BANK_SIZE + addr_reg; + break; + case FLASH_ECC_AREA_SYSTEM: + /* check system flash bank */ + if ((correction_reg & FLASH_ECCR_BK_ECC) == FLASH_ECCR_BK_ECC) + { + pData->Address = FLASH_SYSTEM_BASE + FLASH_SYSTEM_SIZE + addr_reg; + } + else + { + pData->Address = FLASH_SYSTEM_BASE + addr_reg; + } + break; +#if defined (FLASH_SR_OBKERR) + case FLASH_ECC_AREA_OBK: + pData->Address = FLASH_OBK_BASE + addr_reg; + break; +#endif /* FLASH_SR_OBKERR */ +#if defined (FLASH_EDATAR_EDATA_EN) + case FLASH_ECC_AREA_EDATA: + /* check flash high-cycle data bank */ + if ((correction_reg & FLASH_ECCR_BK_ECC) == FLASH_ECCR_BK_ECC) + { + /* + * addr_reg is the address returned by the ECC register along with an offset value depends on area + * To calculate the exact address set by user while an ECC occurred, we must subtract the offset value, + * In addition, the address returned by ECC registers represents 128-bit flash word (multiply by 4), + */ + pData->Address = FLASH_EDATA_BASE + FLASH_BANK_SIZE + ((addr_reg - FLASH_ADDRESS_OFFSET_EDATA) * 4U); + } + else + { + pData->Address = FLASH_EDATA_BASE + ((addr_reg - FLASH_ADDRESS_OFFSET_EDATA) * 4U); + } + break; #endif /* FLASH_EDATAR_EDATA_EN */ + case FLASH_ECC_AREA_OTP: + /* Address returned by the ECC is an halfword, multiply by 4 to get the exact address*/ + pData->Address = FLASH_OTP_BASE + ((addr_reg - FLASH_ADDRESS_OFFSET_OTP) * 4U); + break; + + default: + /* Do nothing */ + break; + } + } + + pData->Data = data_reg & FLASH_ECCR_ADDR_ECC; +} + +/** + * @brief Handle Flash ECC Detection interrupt request. + * @retval None + */ +void HAL_FLASHEx_ECCD_IRQHandler(void) +{ + /* Check if the ECC double error occurred*/ + if (READ_BIT(FLASH->ECCDETR, FLASH_ECCR_ECCD) != 0U) + { + /* FLASH ECC detection user callback */ + HAL_FLASHEx_EccDetectionCallback(); + + /* Clear ECCD flag + note : this step will clear all the information related to the flash ecc detection + */ + SET_BIT(FLASH->ECCDETR, FLASH_ECCR_ECCD); + } +} + +/** + * @brief FLASH ECC Correction interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccCorrectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH ECC Detection interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccDetectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file + */ +} /** * @} */ +/** + * @} + */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fmac.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fmac.c index 6f9a6900dd..8709c66720 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fmac.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_fmac.c @@ -166,7 +166,7 @@ [..] Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: @@ -182,10 +182,10 @@ [..] By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples GetDataCallback(), OutputDataReadyCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_FMAC_Init() + reset to the legacy weak functions in the HAL_FMAC_Init() and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -202,8 +202,7 @@ [..] When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. - + and weak callbacks are used. @endverbatim * @@ -229,7 +228,6 @@ /** @defgroup FMAC_Private_Constants FMAC Private Constants * @{ */ - #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU) #define MAX_PRELOAD_INDEX 0xFFU #define PRELOAD_ACCESS_DMA 0x00U @@ -322,7 +320,6 @@ /* Private variables ---------------------------------------------------------*/ /* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); @@ -348,7 +345,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma); static void FMAC_DMAError(DMA_HandleTypeDef *hdma); /* Functions Definition ------------------------------------------------------*/ - /** @defgroup FMAC_Exported_Functions FMAC Exported Functions * @{ */ @@ -2576,7 +2572,6 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) #else HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ - } /** @@ -2708,11 +2703,11 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma) HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ } + /** * @} */ - /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c index 12f9e46837..a59d2ca1fb 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c @@ -206,15 +206,15 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure Alternate function mapped with the current IO */ tmp = GPIOx->AFR[position >> 3U]; - tmp &= ~(0x0FUL << ((position & 0x07U) * 4U)); - tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * 4U)); + tmp &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); GPIOx->AFR[position >> 3U] = tmp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ tmp = GPIOx->MODER; - tmp &= ~(GPIO_MODER_MODE0 << (position * 2U)); - tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); GPIOx->MODER = tmp; /* In case of Output or Alternate function mode selection */ @@ -226,8 +226,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure the IO Speed */ tmp = GPIOx->OSPEEDR; - tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); - tmp |= (pGPIO_Init->Speed << (position * 2U)); + tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); GPIOx->OSPEEDR = tmp; /* Configure the IO Output Type */ @@ -244,8 +244,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Activate the Pull-up or Pull down resistor for the current IO */ tmp = GPIOx->PUPDR; - tmp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); - tmp |= ((pGPIO_Init->Pull) << (position * 2U)); + tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); GPIOx->PUPDR = tmp; } @@ -254,8 +254,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { tmp = EXTI->EXTICR[position >> 2U]; - tmp &= ~((0x0FUL) << (8U * (position & 0x03U))); - tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))); + tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); EXTI->EXTICR[position >> 2U] = tmp; /* Clear Rising Falling edge configuration */ @@ -327,8 +327,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = EXTI->EXTICR[position >> 2U]; - tmp &= ((0x0FUL) << (8U * (position & 0x03U))); - if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)))) + tmp &= ((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos))) { /* Clear EXTI line configuration */ EXTI->IMR1 &= ~(iocurrent); @@ -338,25 +338,25 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) EXTI->RTSR1 &= ~(iocurrent); EXTI->FTSR1 &= ~(iocurrent); - tmp = (0x0FUL) << (8U * (position & 0x03U)); + tmp = (0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos); EXTI->EXTICR[position >> 2U] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ - GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3U] &= ~(0x0FUL << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position); /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); } position++; @@ -704,7 +704,7 @@ HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uin /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin) && (GPIO_Pin != GPIO_PIN_ALL)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); /* Get secure attribute of the port pin */ while ((GPIO_Pin >> position) != 0U) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gtzc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gtzc.c index 9f3eb34757..26ccc25b54 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gtzc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gtzc.c @@ -134,33 +134,42 @@ #define GTZC_TZSC_MPCWM4_SDRAM_MEM_SIZE 0x10000000U /* 256MB max size */ #endif /* defined(FMC_SDRAM_BANK_2) */ +/* Definitions for GTZC TZSC & TZIC Crypto peripherals */ +#if defined(STM32H573xx) || defined(STM32H533xx) +#define GTZC_CRYP_CFG3_MSK 0x00190000U +#define GTZC_CRYP_CFG4_MSK 0x00000010U +#else +#define GTZC_CRYP_CFG3_MSK 0U +#define GTZC_CRYP_CFG4_MSK 0U +#endif /* defined(STM32H573xx) || defined(STM32H533xx) */ + /* Definitions for GTZC TZSC & TZIC ALL register values */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define TZSC1_SECCFGR1_ALL (0xFFFFFFFFUL) -#define TZSC1_SECCFGR2_ALL (0xFF0FFF07UL) -#define TZSC1_SECCFGR3_ALL (0x05FFFF03UL) -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined(STM32H573xx) || defined(STM32H563xx) +#define GTZC_CFGR1_MSK 0xFFFFFFFFU +#define GTZC_CFGR2_MSK 0xFF0FFF07U +#define GTZC_CFGR3_MSK (0x05E6FF03U | GTZC_CRYP_CFG3_MSK) +#define GTZC_CFGR4_MSK (0x3F1F0FDFU | GTZC_CRYP_CFG4_MSK) +#elif defined(STM32H533xx) || defined(STM32H523xx) +#define GTZC_CFGR1_MSK 0xC33FFE7FU +#define GTZC_CFGR2_MSK 0x16089F07U +#define GTZC_CFGR3_MSK (0x05A6F106U | GTZC_CRYP_CFG3_MSK) +#define GTZC_CFGR4_MSK (0x3F1F0FDFU | GTZC_CRYP_CFG4_MSK) +#elif defined(STM32H562xx) +#define GTZC_CFGR1_MSK 0xFFFFFFFFU +#define GTZC_CFGR2_MSK 0xFF0FFF05U +#define GTZC_CFGR3_MSK 0x05A6FF03U +#define GTZC_CFGR4_MSK 0x3F1F0FDFU +#elif defined(STM32H503xx) +#define GTZC_CFGR1_MSK 0xC21E7E33U +#define GTZC_CFGR2_MSK 0x12080B19U +#define GTZC_CFGR3_MSK 0x04065104U +#define GTZC_CFGR4_MSK 0x00000000U +#endif /* (STM32H533xx) || defined(STM32H523xx) */ #if defined (GTZC_TZIC1) -#define TZSC1_PRIVCFGR1_ALL (0xFFFFFFFFUL) -#define TZSC1_PRIVCFGR2_ALL (0xFF0FFF07UL) -#define TZSC1_PRIVCFGR3_ALL (0x05FFFF03UL) +#define GTZC_SEC_PRIV_MSK (GTZC_TZSC_PERIPH_PRIV | GTZC_TZSC_PERIPH_SEC) #else -#define TZSC1_PRIVCFGR1_ALL (0xC21E7E33UL) -#define TZSC1_PRIVCFGR2_ALL (0x12080B19UL) -#define TZSC1_PRIVCFGR3_ALL (0x04065106UL) -#endif /* defined (GTZC_TZIC1) */ - -#if defined (GTZC_TZIC1) -#define TZIC1_IER1_ALL (0xFFFFFFFFUL) -#define TZIC1_IER2_ALL (0xFF0FFF07UL) -#define TZIC1_IER3_ALL (0x05FFFF03UL) -#define TZIC1_IER4_ALL (0x3F3F0FFFUL) - -#define TZIC1_FCR1_ALL (0xFFFFFFFFUL) -#define TZIC1_FCR2_ALL (0xFF0FFF07UL) -#define TZIC1_FCR3_ALL (0x05FFFF03UL) -#define TZIC1_FCR4_ALL (0x3F3F0FFFUL) +#define GTZC_SEC_PRIV_MSK GTZC_TZSC_PERIPH_PRIV #endif /* defined (GTZC_TZIC1) */ /** * @} @@ -189,6 +198,15 @@ #define GTZC_BASE_ADDRESS(mem)\ ( mem ## _BASE ) +#if defined(GTZC_MPCBB_CR_INVSECSTATE_Pos) +#define MPCBB_PARAMETERS_CHECK() \ + ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE) \ + && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE)) \ + || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) \ + && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)) +#else +#define MPCBB_PARAMETERS_CHECK() (0U == 1U) +#endif /* defined(GTZC_MPCBB_CR_INVSECSTATE_Pos) */ /** * @} */ @@ -235,17 +253,10 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, uint32_t register_address; /* check entry parameters */ -#if defined (GTZC_TZIC1) - if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV)) - || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) - || (((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) -#else - if ((PeriphAttributes > GTZC_TZSC_PERIPH_PRIV) + if (((PeriphAttributes & ~(GTZC_SEC_PRIV_MSK)) != 0U) || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) -#endif /* defined (GTZC_TZIC1) */ { return HAL_ERROR; } @@ -258,15 +269,15 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, /* secure configuration */ if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC) { - SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL); - SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL); - SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL); + SET_BIT(GTZC_TZSC1->SECCFGR1, GTZC_CFGR1_MSK); + SET_BIT(GTZC_TZSC1->SECCFGR2, GTZC_CFGR2_MSK); + SET_BIT(GTZC_TZSC1->SECCFGR3, GTZC_CFGR3_MSK); } else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC) { - CLEAR_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL); - CLEAR_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL); - CLEAR_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL); + CLEAR_BIT(GTZC_TZSC1->SECCFGR1, GTZC_CFGR1_MSK); + CLEAR_BIT(GTZC_TZSC1->SECCFGR2, GTZC_CFGR2_MSK); + CLEAR_BIT(GTZC_TZSC1->SECCFGR3, GTZC_CFGR3_MSK); } else { @@ -277,15 +288,15 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, /* privilege configuration */ if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV) { - SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL); - SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL); - SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL); + SET_BIT(GTZC_TZSC1->PRIVCFGR1, GTZC_CFGR1_MSK); + SET_BIT(GTZC_TZSC1->PRIVCFGR2, GTZC_CFGR2_MSK); + SET_BIT(GTZC_TZSC1->PRIVCFGR3, GTZC_CFGR3_MSK); } else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV) { - CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL); - CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL); - CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL); + CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, GTZC_CFGR1_MSK); + CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, GTZC_CFGR2_MSK); + CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, GTZC_CFGR3_MSK); } else { @@ -363,126 +374,126 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, if ((PeriphId & GTZC_PERIPH_ALL) != 0U) { -#if defined (GTZC_TZIC1) - /* get secure configuration: read each register and deploy each bit value + /* get privilege configuration: read each register and deploy each bit value * of corresponding index in the destination array */ - reg_value = READ_REG(GTZC_TZSC1->SECCFGR1); + reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1); for (i = 0U; i < 32U; i++) { if (((reg_value & (1UL << i)) >> i) != 0U) { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; + PeriphAttributes[i] = GTZC_TZSC_PERIPH_PRIV; } else { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; + PeriphAttributes[i] = GTZC_TZSC_PERIPH_NPRIV; } } - reg_value = READ_REG(GTZC_TZSC1->SECCFGR2); + reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2); for (i = 32U; i < 64U; i++) { if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; + PeriphAttributes[i] = GTZC_TZSC_PERIPH_PRIV; } else { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; + PeriphAttributes[i] = GTZC_TZSC_PERIPH_NPRIV; } } - reg_value = READ_REG(GTZC_TZSC1->SECCFGR3); + reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3); for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++) { if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U) { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; + PeriphAttributes[i] = GTZC_TZSC_PERIPH_PRIV; } else { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; + PeriphAttributes[i] = GTZC_TZSC_PERIPH_NPRIV; } } -#endif /* defined (GTZC_TZIC1) */ - - /* get privilege configuration: read each register and deploy each bit value +#if defined (GTZC_TZIC1) + /* get secure configuration: read each register and deploy each bit value * of corresponding index in the destination array */ - reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1); + reg_value = READ_REG(GTZC_TZSC1->SECCFGR1); for (i = 0U; i < 32U; i++) { if (((reg_value & (1UL << i)) >> i) != 0U) { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_SEC; } else { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NSEC; } } - reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2); + reg_value = READ_REG(GTZC_TZSC1->SECCFGR2); for (i = 32U; i < 64U; i++) { if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_SEC; } else { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NSEC; } } - reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3); + reg_value = READ_REG(GTZC_TZSC1->SECCFGR3); for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++) { if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U) { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_SEC; } else { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NSEC; } } + +#endif /* defined (GTZC_TZIC1) */ } else { - /* common case where only one peripheral is configured */ -#if defined (GTZC_TZIC1) - /* secure configuration */ - register_address = (uint32_t) &(GTZC_TZSC1->SECCFGR1) - + (4U * GTZC_GET_REG_INDEX(PeriphId)); + /* privilege configuration */ + register_address = (uint32_t) &(GTZC_TZSC1->PRIVCFGR1) + + (4U * GTZC_GET_REG_INDEX(PeriphId)); if (((READ_BIT(*(__IO uint32_t *)register_address, - 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) + 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) != 0U) { - *PeriphAttributes = GTZC_TZSC_PERIPH_SEC; + *PeriphAttributes = GTZC_TZSC_PERIPH_PRIV; } else { - *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC; + *PeriphAttributes = GTZC_TZSC_PERIPH_NPRIV; } -#endif /* defined (GTZC_TZIC1) */ - /* privilege configuration */ - register_address = (uint32_t) &(GTZC_TZSC1->PRIVCFGR1) + /* common case where only one peripheral is configured */ +#if defined (GTZC_TZIC1) + /* secure configuration */ + register_address = (uint32_t) &(GTZC_TZSC1->SECCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); if (((READ_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) != 0U) { - *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV; + *PeriphAttributes |= GTZC_TZSC_PERIPH_SEC; } else { - *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV; + *PeriphAttributes |= GTZC_TZSC_PERIPH_NSEC; } +#endif /* defined (GTZC_TZIC1) */ } return HAL_OK; } @@ -834,17 +845,11 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))) - || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE) - && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE)) - || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) - && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED))) + || MPCBB_PARAMETERS_CHECK()) #else if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))) - || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE) - && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE)) - || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) - && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED))) + || MPCBB_PARAMETERS_CHECK()) #endif /* defined (GTZC_MPCBB3) */ { return HAL_ERROR; @@ -1569,10 +1574,10 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId) if ((PeriphId & GTZC_PERIPH_ALL) != 0U) { /* same configuration is applied to all peripherals */ - WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL); - WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL); - WRITE_REG(GTZC_TZIC1->IER3, TZIC1_IER3_ALL); - WRITE_REG(GTZC_TZIC1->IER4, TZIC1_IER4_ALL); + WRITE_REG(GTZC_TZIC1->IER1, GTZC_CFGR1_MSK); + WRITE_REG(GTZC_TZIC1->IER2, GTZC_CFGR2_MSK); + WRITE_REG(GTZC_TZIC1->IER3, GTZC_CFGR3_MSK); + WRITE_REG(GTZC_TZIC1->IER4, GTZC_CFGR4_MSK); } else { @@ -1634,7 +1639,7 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag) } reg_value = READ_REG(GTZC_TZIC1->SR4); - for (i = 96U; i < 128U; i++) + for (i = 96U; i < GTZC_TZIC_PERIPH_NUMBER; i++) { pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U); } @@ -1673,10 +1678,10 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId) if ((PeriphId & GTZC_PERIPH_ALL) != 0U) { /* same configuration is applied to all peripherals */ - WRITE_REG(GTZC_TZIC1->FCR1, TZIC1_FCR1_ALL); - WRITE_REG(GTZC_TZIC1->FCR2, TZIC1_FCR2_ALL); - WRITE_REG(GTZC_TZIC1->FCR3, TZIC1_FCR3_ALL); - WRITE_REG(GTZC_TZIC1->FCR4, TZIC1_FCR4_ALL); + WRITE_REG(GTZC_TZIC1->FCR1, GTZC_CFGR1_MSK); + WRITE_REG(GTZC_TZIC1->FCR2, GTZC_CFGR2_MSK); + WRITE_REG(GTZC_TZIC1->FCR3, GTZC_CFGR3_MSK); + WRITE_REG(GTZC_TZIC1->FCR4, GTZC_CFGR4_MSK); } else { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c index 9c09db3fcc..21aea51096 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c @@ -2530,15 +2530,58 @@ static void HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *pInBuffer, { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint8_t tmp1; + uint8_t tmp2; + uint8_t tmp3; - - for (buffercounter = 0U; buffercounter < Size ; buffercounter += 4U) + for (buffercounter = 0U; buffercounter < (Size / 4U) ; buffercounter++) { /* Write input data 4 bytes at a time */ hhash->Instance->DIN = *(uint32_t *)inputaddr; inputaddr += 4U; hhash->HashInCount += 4U; } + + if ((Size % 4U) != 0U) + { + if (hhash->Init.DataType == HASH_HALFWORD_SWAP) + { + /* Write remaining input data */ + if ((Size % 4U) <= 2U) + { + hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + hhash->Instance->DIN = *(uint32_t *)inputaddr; + } + } + else if ((hhash->Init.DataType == HASH_BYTE_SWAP) + || (hhash->Init.DataType == HASH_BIT_SWAP)) /* byte swap or bit swap or */ + { + /* Write remaining input data */ + if ((Size % 4U) == 1U) + { + hhash->Instance->DIN = (uint32_t) * (uint8_t *)inputaddr; + } + if ((Size % 4U) == 2U) + { + hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + tmp1 = *(uint8_t *)inputaddr; + tmp2 = *(((uint8_t *)inputaddr) + 1U); + tmp3 = *(((uint8_t *)inputaddr) + 2U); + hhash->Instance->DIN = ((uint32_t)tmp1) | ((uint32_t)tmp2 << 8U) | ((uint32_t)tmp3 << 16U); + } + } + else + { + hhash->Instance->DIN = *(uint32_t *)inputaddr; + } + hhash->HashInCount += 4U; + } } /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c index 36498d018f..8c5e0d6ba9 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c @@ -169,9 +169,6 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Init Host */ (void)USB_HostInit(hhcd->Instance, hhcd->Init); - /* Deactivate the power down */ - hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; - hhcd->State = HAL_HCD_STATE_READY; /* Host Port State */ @@ -219,6 +216,27 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, __HAL_LOCK(hhcd); + if (ch_num > 16U) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + + if (((epnum & 0xFU)== 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) + { + hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[0U].pmaadress; + hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[0U].pmaaddr0; + hhcd->hc[ch_num & 0xFU].pmaaddr1 = hhcd->hc[0U].pmaaddr1; + + hhcd->phy_chin_state[0U] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + + hhcd->phy_chout_state[0U] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + /* Check if the logical channel are already allocated */ used_channel = HAL_HCD_Check_usedChannel(hhcd, ch_num); @@ -231,6 +249,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, /* No free Channel available, return error */ if (hhcd->hc[ch_num & 0xFU].phy_ch_num == HCD_FREE_CH_NOT_FOUND) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -267,6 +286,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } @@ -285,6 +305,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -302,22 +323,28 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } else { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } else { + /* This is a dual EP0 PMA allocation */ + hhcd->ep0_PmaAllocState |= (0x1U << 12); + /* PMA Dynamic Allocation for EP0 OUT direction */ hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } @@ -327,6 +354,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -352,6 +380,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -730,8 +759,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { uint8_t phy_chnum; - uint8_t chnum; - uint32_t epch_reg; + uint8_t ch_dir; uint32_t wIstr = USB_ReadInterrupts(hhcd->Instance); /* Port Change Detected (Connection/Disconnection) */ @@ -749,50 +777,21 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /* Correct Transaction Detected -------*/ if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) { - /* Handle Host channel Interrupt */ - for (phy_chnum = 0U; phy_chnum < hhcd->Init.Host_channels; phy_chnum++) - { - if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTRX) != 0U) - { - /* Get Logical channel to check if the channel is already opened */ - chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U); - - if (chnum != HCD_LOGICAL_CH_NOT_OPENED) - { - /* Call Channel_IN_IRQ() */ - HCD_HC_IN_IRQHandler(hhcd, chnum); - } - else - { - /*Channel was not closed correctly still have interrupt */ - epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); - epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRRX) & (~USB_CH_VTRX))) | - (USB_CH_VTTX | USB_CH_ERRTX); - - HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg); - } - } - - if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTTX) != 0U) - { - /* Get Logical channel to check if the channel is already opened */ - chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U); + /* Get Physical channel */ + phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); - if (chnum != HCD_LOGICAL_CH_NOT_OPENED) - { - /*Call Channel_OUT_IRQ()*/ - HCD_HC_OUT_IRQHandler(hhcd, chnum); - } - else - { - /* Clear Error & unwanted VTTX or Channel was not closed correctly */ - epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); - epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRTX) & (~USB_CH_VTTX))) | - (USB_CH_VTRX | USB_CH_ERRRX); + /* Get channel direction */ + ch_dir = (uint8_t)__HAL_HCD_GET_CHDIR(hhcd); - HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg); - } - } + if (ch_dir == CH_OUT_DIR) + { + /* Call Channel_OUT_IRQ() */ + HCD_HC_OUT_IRQHandler(hhcd, phy_chnum); + } + else + { + /* Call Channel_IN_IRQ() */ + HCD_HC_IN_IRQHandler(hhcd, phy_chnum); } return; @@ -1292,16 +1291,21 @@ transfers. */ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) { + __IO uint32_t count = HCD_PDWN_EXIT_CNT; + __HAL_LOCK(hhcd); - /*Set the PullDown on the PHY */ - hhcd->Instance->BCDR |= USB_BCDR_DPPD; + /* Remove PowerDown */ + hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; - /* Clear Reset */ - hhcd->Instance->CNTR &= ~USB_CNTR_USBRST; + /* Few cycles to ensure exit from powerdown */ + while (count > 0U) + { + count--; + } - /*Remove PowerDown */ - hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; + /* Clear Reset */ + hhcd->Instance->CNTR &= ~USB_CNTR_USBRST; __HAL_UNLOCK(hhcd); @@ -1347,7 +1351,7 @@ HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd) /* wait for Suspend Ready */ while ((hhcd->Instance->CNTR & USB_CNTR_SUSPRDY) == 0U) { - if (++count > 0xFFFFFFU) + if (++count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -1581,7 +1585,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { /* manage multiple Xfer */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; /* check if we need to free user buffer */ if ((regvalue & USB_CH_DTOG_RX) != 0U) @@ -1620,7 +1624,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, else { /* Transfer complete state */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; hhcd->hc[ch_num & 0xFU].state = HC_XFRC; hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; @@ -1642,7 +1646,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { /* manage multiple Xfer */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; /* check if we need to free user buffer */ if ((regvalue & USB_CH_DTOG_RX) == 0U) @@ -1683,7 +1687,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, else { /* Transfer complete state */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; hhcd->hc[ch_num & 0xFU].state = HC_XFRC; hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; @@ -1857,16 +1861,17 @@ static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num, /** * @brief Handle Host Channel IN interrupt requests. * @param hhcd HCD handle - * @param ch_num Channel number - * This parameter can be a value from 1 to 15 + * @param chnum Channel number + * This parameter can be a value from 1 to 8 * @retval none */ -static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { uint16_t received_bytes; - uint8_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); + uint8_t phy_chnum = chnum; + uint8_t ch_num = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U); - /*Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */ + /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */ uint32_t ch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); /* Manage Correct Transaction */ @@ -1932,6 +1937,12 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; hhcd->hc[ch_num & 0xFU].state = HC_NAK; + + if (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR) + { + /* Close the channel */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); + } } /* manage STALL Response */ else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) @@ -2001,16 +2012,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) * @brief Handle Host Channel OUT interrupt requests. * @param hhcd HCD handle * @param chnum Channel number - * This parameter can be a value from 1 to 15 + * This parameter can be a value from 1 to 8 * @retval none */ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - uint16_t data_xfr; __IO uint32_t WregCh; + uint16_t data_xfr; + uint8_t phy_chnum = chnum; - /* Get Physical Channel number */ - uint32_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); + /* Get Virtual Channel number */ + uint8_t ch_num = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U); /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control &status */ uint32_t ch_reg = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); @@ -2048,8 +2060,8 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* Transfer complete state */ - hhcd->hc[chnum & 0xFU].state = HC_XFRC; - hhcd->hc[chnum & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; } /*Clear Correct Transfer */ @@ -2057,9 +2069,9 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /*TX COMPLETE*/ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } @@ -2070,36 +2082,36 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->TXBD & 0x03FF0000U) >> 16U); - if (hhcd->hc[chnum & 0xFU].xfer_len >= data_xfr) + if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr) { - hhcd->hc[chnum & 0xFU].xfer_len -= data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr; } else { - hhcd->hc[chnum & 0xFU].xfer_len = 0U; + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; } /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ - if (hhcd->hc[chnum & 0xFU].xfer_len != 0U) + if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { /* manage multiple Xfer */ - hhcd->hc[chnum & 0xFU].xfer_buff += data_xfr; - hhcd->hc[chnum & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; /* start a new transfer */ - (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[chnum & 0xFU]); + (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]); } else { /* Transfer complete */ - hhcd->hc[chnum & 0xFU].xfer_count += data_xfr; - hhcd->hc[chnum & 0xFU].state = HC_XFRC; - hhcd->hc[chnum & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - if ((hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_BULK) || - (hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_INTR)) + if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) { - hhcd->hc[chnum & 0xFU].toggle_out ^= 1U; + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; } } } @@ -2108,9 +2120,9 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_NAK)) { /* Update Channel status */ - hhcd->hc[chnum & 0xFU].state = HC_NAK; - hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY; - hhcd->hc[chnum & 0xFU].ErrCnt = 0U; + hhcd->hc[ch_num & 0xFU].state = HC_NAK; + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; /* Get Channel register value */ WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); @@ -2121,28 +2133,28 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Update channel register Value */ HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, WregCh); - if (hhcd->hc[chnum & 0xFU].doublebuffer == 0U) + if (hhcd->hc[ch_num & 0xFU].doublebuffer == 0U) { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } /* Check STALL Response */ else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_STALL) { - (void) HAL_HCD_HC_Halt(hhcd, (uint8_t)chnum); - hhcd->hc[chnum & 0xFU].state = HC_STALL; - hhcd->hc[chnum & 0xFU].urb_state = URB_STALL; + (void) HAL_HCD_HC_Halt(hhcd, (uint8_t)ch_num); + hhcd->hc[ch_num & 0xFU].state = HC_STALL; + hhcd->hc[ch_num & 0xFU].urb_state = URB_STALL; } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Check double buffer ACK in case of bulk transaction */ else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_DBUF) { /* Double buffer management Bulk Out */ - (void) HCD_HC_OUT_BulkDb(hhcd, chnum, (uint8_t)phy_chnum, ch_reg); + (void) HCD_HC_OUT_BulkDb(hhcd, ch_num, (uint8_t)phy_chnum, ch_reg); } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ else @@ -2153,38 +2165,38 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((ch_reg & USB_CH_TX_STTX) != USB_CH_TX_NAK) { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } HCD_CLEAR_TX_CH_CTR(hhcd->Instance, phy_chnum); - } /* end no isochronous */ + } /* End no isochronous */ } /*------ Manage Transaction Error------*/ else { - hhcd->hc[chnum & 0xFU].ErrCnt++; - if (hhcd->hc[chnum & 0xFU].ErrCnt > 3U) + hhcd->hc[ch_num & 0xFU].ErrCnt++; + if (hhcd->hc[ch_num & 0xFU].ErrCnt > 3U) { HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); - hhcd->hc[chnum & 0xFU].urb_state = URB_ERROR; + hhcd->hc[ch_num & 0xFU].urb_state = URB_ERROR; } else { - hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; } - hhcd->hc[chnum & 0xFU].state = HC_XACTERR; + hhcd->hc[ch_num & 0xFU].state = HC_XACTERR; - /*Clear ERR_TX*/ + /* Clear ERR_TX */ HCD_CLEAR_TX_CH_ERR(hhcd->Instance, phy_chnum); #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } @@ -2620,7 +2632,7 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, /* Get a FreePMA Address */ pma_addr0 = HAL_HCD_GetFreePMA(hhcd, mps); - /* if there is no free space to allocate */ + /* If there is no free space to allocate */ if (pma_addr0 == 0xFFFFU) { return HAL_ERROR; @@ -2635,7 +2647,8 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (hc->ep_num == 0U) { - hhcd->ep0_PmaAllocState = ch_num; + hhcd->ep0_PmaAllocState &= 0xFFF0U; + hhcd->ep0_PmaAllocState |= ch_num; hhcd->ep0_PmaAllocState |= (1U << 8); } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c index 27673574c2..f2314a6268 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c @@ -90,7 +90,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -156,7 +156,7 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -214,7 +214,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -1363,6 +1363,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1389,14 +1391,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - /* Preload TX data if no stretch enable */ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { @@ -1410,6 +1404,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1421,6 +1427,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1433,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1456,31 +1470,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until AF flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } - return HAL_ERROR; + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { @@ -4785,7 +4816,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4794,7 +4825,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -5460,9 +5493,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5891,9 +5923,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -6495,6 +6526,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ @@ -6584,6 +6616,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -7172,6 +7255,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { @@ -7283,16 +7372,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -7300,19 +7391,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -7326,12 +7412,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) { @@ -7341,11 +7431,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; } } } - return HAL_OK; + return status; } /** diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2s.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2s.c index 2c9e7b6fe4..c5c92b8a53 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2s.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2s.c @@ -170,7 +170,7 @@ When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -540,6 +540,8 @@ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) * the configuration information for the specified I2S. * @param CallbackID ID of the callback to be registered * @param pCallback pointer to the Callback function + * @note The HAL_I2S_RegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET + * to register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, @@ -554,8 +556,6 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2s); if (HAL_I2S_STATE_READY == hi2s->State) { @@ -637,8 +637,6 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2s); return status; } @@ -648,15 +646,14 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains * the configuration information for the specified I2S. * @param CallbackID ID of the callback to be unregistered + * @note The HAL_I2S_UnRegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET + * to un-register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2s); - if (HAL_I2S_STATE_READY == hi2s->State) { switch (CallbackID) @@ -736,8 +733,6 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2s); return status; } #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c index 1d43699e5c..63add3cb59 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i3c.c @@ -112,6 +112,8 @@ And then application must send a associated dynamic address through HAL_I3C_Ctrl_SetDynAddr(). This procedure in loop automatically in hardware side until a target respond to repeated ENTDAA sequence. The application is informed of the end of the procedure at reception of HAL_I3C_CtrlDAACpltCallback(). + Then application can easily retrieve ENTDAA payload information through HAL_I3C_Get_ENTDAA_Payload_Info() + function. At the end of procedure, the function HAL_I3C_Ctrl_ConfigBusDevices() must be called to store in hardware register part the target capabilities as Dynamic address, IBI support with or without additional data byte, Controller role request support, Controller stop transfer after IBI through I3C_DeviceConfTypeDef structure. @@ -353,11 +355,129 @@ #define I3C_BROADCAST_RSTDAA (0x00000006U) #define I3C_BROADCAST_ENTDAA (0x00000007U) +/* Private define to split ENTDAA payload */ +#define I3C_DCR_IN_PAYLOAD_SHIFT 56 +#define I3C_PID_IN_PAYLOAD_MASK 0xFFFFFFFFFFFFU + +/* Private define to split PID */ +/* Bits[47:33]: MIPI Manufacturer ID */ +#define I3C_MIPIMID_PID_SHIFT 33 +#define I3C_MIPIMID_PID_MASK 0x7FFFU + +/* Bit[32]: Provisioned ID Type Selector */ +#define I3C_IDTSEL_PID_SHIFT 32 +#define I3C_IDTSEL_PID_MASK 0x01U + +/* Bits[31:16]: Part ID */ +#define I3C_PART_ID_PID_SHIFT 16 +#define I3C_PART_ID_PID_MASK 0xFFFFU + +/* Bits[15:12]: MIPI Instance ID */ +#define I3C_MIPIID_PID_SHIFT 12 +#define I3C_MIPIID_PID_MASK 0xFU /** * @} */ /* Private macro -----------------------------------------------------------------------------------------------------*/ + +/** @brief Get Provisioned ID in payload (64bits) receive during ENTDAA procedure. + * @param __PAYLOAD__ specifies the Device Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFF. + * @retval The value of PID Return value between Min_Data=0x00 and Max_Data=0xFFFFFFFFFFFF. + */ +#define I3C_GET_PID(__PAYLOAD__) ((uint64_t)(__PAYLOAD__) & I3C_PID_IN_PAYLOAD_MASK) + +/** @brief Get MIPI Manufacturer ID in PID (48bits). + * @param __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF. + * @retval The value of MIPI ID Return value between Min_Data=0x00 and Max_Data=0x7FFF. + */ +#define I3C_GET_MIPIMID(__PID__) ((uint16_t)((uint64_t)(__PID__) >> I3C_MIPIMID_PID_SHIFT) & \ + I3C_MIPIMID_PID_MASK) + +/** @brief Get Type Selector in PID (48bits). + * @param __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF. + * @retval The value of Type Selector Return 0 or 1. + */ +#define I3C_GET_IDTSEL(__PID__) ((uint8_t)((uint64_t)(__PID__) >> I3C_IDTSEL_PID_SHIFT) & \ + I3C_IDTSEL_PID_MASK) + +/** @brief Get Part ID in PID (48bits). + * @param __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF. + * @retval The value of Part ID Return value between Min_Data=0x00 and Max_Data=0xFFFF. + */ +#define I3C_GET_PART_ID(__PID__) ((uint16_t)((uint64_t)(__PID__) >> I3C_PART_ID_PID_SHIFT) & \ + I3C_PART_ID_PID_MASK) + +/** @brief Get Instance ID in PID (48bits). + * @param __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF. + * @retval The value of Instance ID Return value between Min_Data=0x00 and Max_Data=0xF. + */ +#define I3C_GET_MIPIID(__PID__) ((uint8_t)((uint64_t)(__PID__) >> I3C_MIPIID_PID_SHIFT) & \ + I3C_MIPIID_PID_MASK) + +/** @brief Get Device Characterics in payload (64bits) receive during ENTDAA procedure. + * @param __PAYLOAD__ specifies the Device Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF. + * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF. + */ +#define I3C_GET_DCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> I3C_DCR_IN_PAYLOAD_SHIFT)) & \ + I3C_DCR_DCR) + +/** @brief Get Advanced Capabilities. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The value of advanced capabilities: + * ENABLE: supports optional advanced capabilities. + * DISABLE: not supports optional advanced capabilities. + */ +#define I3C_GET_ADVANCED_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR5_Msk) >> \ + I3C_BCR_BCR5_Pos) == 1U) ? ENABLE : DISABLE) + +/** @brief Get virtual target support. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The value of offline capable: + * ENABLE: is a Virtual Target + * DISABLE: is not a Virtual Target + */ +#define I3C_GET_VIRTUAL_TGT(__BCR__) (((((__BCR__) & I3C_BCR_BCR4_Msk) >> \ + I3C_BCR_BCR4_Pos) == 1U) ? ENABLE : DISABLE) + +/** @brief Get offline capable. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The value of offline capable + * ENABLE: Device will not always respond to I3C Bus commands + * DISABLE: Device will always respond to I3C Bus commands + */ +#define I3C_GET_OFFLINE_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR3_Msk) >> \ + I3C_BCR_BCR3_Pos) == 1U) ? ENABLE : DISABLE) + +/** @brief Get Max data speed limitation. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The value of offline capable: + * ENABLE: Limitation + * DISABLE: No Limitation + */ +#define I3C_GET_MAX_DATA_SPEED_LIMIT(__BCR__) (((((__BCR__) & I3C_BCR_BCR0_Msk) >> \ + I3C_BCR_BCR0_Pos) == 1U) ? ENABLE : DISABLE) + +/** @brief Change uint32_t variable form big endian to little endian. + * @param __DATA__ .uint32_t variable in big endian. + * This parameter must be a number between Min_Data=0x00(uint32_t) and Max_Data=0xFFFFFFFF. + * @retval uint32_t variable in little endian. + */ +#define I3C_BIG_TO_LITTLE_ENDIAN(__DATA__) ((uint32_t)((((__DATA__) & 0xff000000U) >> 24) | \ + (((__DATA__) & 0x00ff0000U) >> 8) | \ + (((__DATA__) & 0x0000ff00U) << 8) | \ + (((__DATA__) & 0x000000ffU) << 24))) + /* Private variables -------------------------------------------------------------------------------------------------*/ /** @addtogroup I3C_Private_Variables * @{ @@ -377,31 +497,31 @@ typedef struct /** @addtogroup I3C_Private_Functions * @{ */ -static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); +static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); #if defined(HAL_DMA_MODULE_ENABLED) -static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); +static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); #endif /* HAL_DMA_MODULE_ENABLED */ -static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef *hi3c, - uint32_t itFlags, - uint32_t itSources); +static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Tx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Rx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); #if defined(HAL_DMA_MODULE_ENABLED) -static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, - uint32_t itFlags, - uint32_t itSources); +static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); #endif /* HAL_DMA_MODULE_ENABLED */ -static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); -static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources); +static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); + static HAL_StatusTypeDef I3C_WaitOnDAAUntilTimeout(I3C_HandleTypeDef *hi3c, uint32_t timeout, uint32_t tickstart); static HAL_StatusTypeDef I3C_WaitOnFlagUntilTimeout(I3C_HandleTypeDef *hi3c, uint32_t flag, FlagStatus flagstatus, uint32_t timeout, uint32_t tickstart); @@ -1486,10 +1606,12 @@ void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c) /* Derogation MISRAC2012-Rul uint32_t it_flags = READ_REG(hi3c->Instance->EVR); uint32_t it_sources = READ_REG(hi3c->Instance->IER); + uint32_t it_masks = (uint32_t)(it_flags & it_sources); + /* I3C events treatment */ if (hi3c->XferISR != NULL) { - hi3c->XferISR(hi3c, it_flags, it_sources); + hi3c->XferISR(hi3c, it_masks); } } /** @@ -2519,7 +2641,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC(I3C_HandleTypeDef *hi3c, /* Check on user parameters */ if ((pXferData == NULL) || - ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -2679,7 +2801,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_IT(I3C_HandleTypeDef *hi3c, /* Check on user parameters */ if ((pXferData == NULL) || - ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -2699,9 +2821,19 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_IT(I3C_HandleTypeDef *hi3c, { /* Set handle transfer parameters */ hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_TX; + + if (handle_state == HAL_I3C_STATE_LISTEN) + { + hi3c->XferISR = I3C_Ctrl_Tx_Listen_Event_ISR; + } + else + { + hi3c->XferISR = I3C_Ctrl_Tx_ISR; + } + hi3c->pXferData = pXferData; - hi3c->XferISR = I3C_Ctrl_Tx_ISR; + hi3c->State = HAL_I3C_STATE_BUSY_TX; + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) @@ -2767,7 +2899,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_DMA(I3C_HandleTypeDef *hi3c, /* Check on user parameters */ if ((pXferData == NULL) || - ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -2792,10 +2924,10 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_DMA(I3C_HandleTypeDef *hi3c, else { /* Set handle transfer parameters */ - hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_TX; - hi3c->pXferData = pXferData; - hi3c->XferISR = I3C_Ctrl_Tx_DMA_ISR; + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->XferISR = I3C_Ctrl_Tx_DMA_ISR; + hi3c->pXferData = pXferData; + hi3c->State = HAL_I3C_STATE_BUSY_TX; /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/ /* Set the I3C DMA transfer complete callback */ @@ -3164,10 +3296,17 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_IT(I3C_HandleTypeDef *hi3c, { /* Set handle transfer parameters */ hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_RX; + if (handle_state == HAL_I3C_STATE_LISTEN) + { + hi3c->XferISR = I3C_Ctrl_Rx_Listen_Event_ISR; + } + else + { + hi3c->XferISR = I3C_Ctrl_Rx_ISR; + } hi3c->pXferData = pXferData; hi3c->RxXferCount = pXferData->RxBuf.Size; - hi3c->XferISR = I3C_Ctrl_Rx_ISR; + hi3c->State = HAL_I3C_STATE_BUSY_RX; /* Check on CCC defining byte */ if (hi3c->TxXferCount != 0U) @@ -3281,10 +3420,10 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_DMA(I3C_HandleTypeDef *hi3c, { /* Set handle transfer parameters */ hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_RX; + hi3c->XferISR = I3C_Ctrl_Rx_DMA_ISR; hi3c->pXferData = pXferData; hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; - hi3c->XferISR = I3C_Ctrl_Rx_DMA_ISR; + hi3c->State = HAL_I3C_STATE_BUSY_RX; /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/ /* Set the I3C DMA transfer complete callback */ @@ -3506,7 +3645,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit(I3C_HandleTypeDef *hi3c, /* Check on user parameters */ if ((pXferData == NULL) || - ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -3528,7 +3667,6 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit(I3C_HandleTypeDef *hi3c, hi3c->ErrorCode = HAL_I3C_ERROR_NONE; hi3c->State = HAL_I3C_STATE_BUSY_TX; hi3c->pXferData = pXferData; - hi3c->TxXferCount = hi3c->pXferData->TxBuf.Size; /* Check on the Tx threshold to know the Tx treatment process : byte or word */ if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) @@ -3667,7 +3805,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_IT(I3C_HandleTypeDef *hi3c, /* Check on user parameters */ if ((pXferData == NULL) || - ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -3687,10 +3825,16 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_IT(I3C_HandleTypeDef *hi3c, { /* Set handle transfer parameters */ hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_TX; + if (handle_state == HAL_I3C_STATE_LISTEN) + { + hi3c->XferISR = I3C_Ctrl_Tx_Listen_Event_ISR; + } + else + { + hi3c->XferISR = I3C_Ctrl_Tx_ISR; + } hi3c->pXferData = pXferData; - hi3c->TxXferCount = hi3c->pXferData->TxBuf.Size; - hi3c->XferISR = I3C_Ctrl_Tx_ISR; + hi3c->State = HAL_I3C_STATE_BUSY_TX; /* Check on the Tx threshold to know the Tx treatment process : byte or word */ if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) @@ -3757,7 +3901,7 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_DMA(I3C_HandleTypeDef *hi3c, /* Check on user parameters */ if ((pXferData == NULL) || - ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) { hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -3783,10 +3927,9 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_DMA(I3C_HandleTypeDef *hi3c, { /* Set handle transfer parameters */ hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->XferISR = I3C_Ctrl_Tx_DMA_ISR; hi3c->State = HAL_I3C_STATE_BUSY_TX; hi3c->pXferData = pXferData; - hi3c->TxXferCount = hi3c->pXferData->TxBuf.Size; - hi3c->XferISR = I3C_Ctrl_Tx_DMA_ISR; /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/ /* Set the I3C DMA transfer complete callback */ @@ -4127,10 +4270,17 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_IT(I3C_HandleTypeDef *hi3c, { /* Set handle transfer parameters */ hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_RX; + if (handle_state == HAL_I3C_STATE_LISTEN) + { + hi3c->XferISR = I3C_Ctrl_Rx_Listen_Event_ISR; + } + else + { + hi3c->XferISR = I3C_Ctrl_Rx_ISR; + } hi3c->pXferData = pXferData; hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; - hi3c->XferISR = I3C_Ctrl_Rx_ISR; + hi3c->State = HAL_I3C_STATE_BUSY_RX; /* Check on the Rx threshold to know the Rx treatment process : byte or word */ if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) @@ -4220,10 +4370,10 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_DMA(I3C_HandleTypeDef *hi3c, { /* Set handle transfer parameters */ hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_RX; + hi3c->XferISR = I3C_Ctrl_Rx_DMA_ISR; hi3c->pXferData = pXferData; hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; - hi3c->XferISR = I3C_Ctrl_Rx_DMA_ISR; + hi3c->State = HAL_I3C_STATE_BUSY_RX; /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/ /* Set the I3C DMA transfer complete callback */ @@ -4409,11 +4559,18 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_IT(I3C_HandleTypeDef *hi3c, { /* Set handle transfer parameters */ hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_TX_RX; + if (handle_state == HAL_I3C_STATE_LISTEN) + { + hi3c->XferISR = I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR; + } + else + { + hi3c->XferISR = I3C_Ctrl_Multiple_Xfer_ISR; + } hi3c->pXferData = pXferData; hi3c->TxXferCount = hi3c->pXferData->TxBuf.Size; hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; - hi3c->XferISR = I3C_Ctrl_Multiple_Xfer_ISR; + hi3c->State = HAL_I3C_STATE_BUSY_TX_RX; /* Check on the Tx threshold to know the Tx treatment process : byte or word */ if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) @@ -4520,11 +4677,11 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_DMA(I3C_HandleTypeDef *hi3c, I { /* Set handle transfer parameters */ hi3c->ErrorCode = HAL_I3C_ERROR_NONE; - hi3c->State = HAL_I3C_STATE_BUSY_TX_RX; + hi3c->XferISR = I3C_Ctrl_Multiple_Xfer_DMA_ISR; hi3c->pXferData = pXferData; hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; hi3c->TxXferCount = hi3c->pXferData->TxBuf.Size; - hi3c->XferISR = I3C_Ctrl_Multiple_Xfer_DMA_ISR; + hi3c->State = HAL_I3C_STATE_BUSY_TX_RX; /*------------------------------------ I3C DMA channel for Control Data -------------------------------------*/ /* Set the I3C DMA transfer complete callback */ @@ -6622,7 +6779,7 @@ uint32_t HAL_I3C_GetError(const I3C_HandleTypeDef *hi3c) * It can be a combination of value of @ref HAL_I3C_Notification_ID_definition. * @param pCCCInfo : [IN/OUT] Pointer to an I3C_CCCInfoTypeDef structure that contains the CCC information * updated after CCC event. - * @retval None + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c, uint32_t notifyId, @@ -6710,6 +6867,73 @@ HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c, return status; } + +/** + * @brief Get BCR, DCR and PID information after ENTDAA. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param ENTDAA_payload :[IN] Payload received after ENTDAA + * @param pENTDAA_payload :[OUT] Pointer to an I3C_ENTDAAPayloadTypeDef structure that contains the BCR, DCR and PID + * information. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c, + uint64_t ENTDAA_payload, + I3C_ENTDAAPayloadTypeDef *pENTDAA_payload) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t BCR; + uint64_t PID; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check on user parameters */ + if (pENTDAA_payload == NULL) + { + /* Update handle error code parameter */ + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + /* Get Bus Characterics */ + BCR = __HAL_I3C_GET_BCR(ENTDAA_payload); + + /* Retrieve BCR information */ + pENTDAA_payload->BCR.IBIPayload = __HAL_I3C_GET_IBI_PAYLOAD(BCR); + pENTDAA_payload->BCR.IBIRequestCapable = __HAL_I3C_GET_IBI_CAPABLE(BCR); + pENTDAA_payload->BCR.DeviceRole = __HAL_I3C_GET_CR_CAPABLE(BCR); + pENTDAA_payload->BCR.AdvancedCapabilities = I3C_GET_ADVANCED_CAPABLE(BCR); + pENTDAA_payload->BCR.OfflineCapable = I3C_GET_OFFLINE_CAPABLE(BCR); + pENTDAA_payload->BCR.VirtualTargetSupport = I3C_GET_VIRTUAL_TGT(BCR); + pENTDAA_payload->BCR.MaxDataSpeedLimitation = I3C_GET_MAX_DATA_SPEED_LIMIT(BCR); + + /* Get Device Characterics */ + pENTDAA_payload->DCR = I3C_GET_DCR(ENTDAA_payload); + + /* Get Provisioned ID */ + PID = I3C_GET_PID(ENTDAA_payload); + + /* Change PID from BigEndian to litlleEndian */ + PID = (uint64_t)((((uint64_t)I3C_BIG_TO_LITTLE_ENDIAN((uint32_t) PID) << 32) | + ((uint64_t)I3C_BIG_TO_LITTLE_ENDIAN((uint32_t)(PID >> 32)))) >> 16); + + /* Retrieve PID information*/ + pENTDAA_payload->PID.MIPIMID = I3C_GET_MIPIMID(PID); + pENTDAA_payload->PID.IDTSEL = I3C_GET_IDTSEL(PID); + pENTDAA_payload->PID.PartID = I3C_GET_PART_ID(PID); + pENTDAA_payload->PID.MIPIID = I3C_GET_MIPIID(PID); + } + } + + return status; +} + /** * @} */ @@ -6727,24 +6951,22 @@ HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c, * @brief Interrupt Sub-Routine which handles target received events. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { uint32_t tmpevent = 0U; /* I3C Rx FIFO not empty interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, HAL_I3C_FLAG_RXFNEF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, HAL_I3C_IT_RXFNEIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) { /* Call receive treatment function */ hi3c->ptrRxFunc(hi3c); } /* I3C target complete controller-role hand-off procedure (direct GETACCR CCC) event management --------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_CRUPDF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_CRUPDIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRUPDF) != RESET) { /* Clear controller-role update flag */ LL_I3C_ClearFlag_CRUPD(hi3c->Instance); @@ -6754,7 +6976,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive any direct GETxxx CCC event management -------------------------------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_GETF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_GETIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_GETF) != RESET) { /* Clear GETxxx CCC flag */ LL_I3C_ClearFlag_GET(hi3c->Instance); @@ -6764,7 +6986,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive get status command (direct GETSTATUS CCC) event management -----------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_STAF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_STAIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_STAF) != RESET) { /* Clear GETSTATUS CCC flag */ LL_I3C_ClearFlag_STA(hi3c->Instance); @@ -6774,7 +6996,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive a dynamic address update (ENTDAA/RSTDAA/SETNEWDA CCC) event management -----------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_DAUPDF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_DAUPDIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DAUPDF) != RESET) { /* Clear dynamic address update flag */ LL_I3C_ClearFlag_DAUPD(hi3c->Instance); @@ -6784,8 +7006,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive maximum write length update (direct SETMWL CCC) event management -----------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_MWLUPDF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_MWLUPDIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_MWLUPDF) != RESET) { /* Clear SETMWL CCC flag */ LL_I3C_ClearFlag_MWLUPD(hi3c->Instance); @@ -6795,8 +7016,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive maximum read length update(direct SETMRL CCC) event management -------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_MRLUPDF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_MRLUPDIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_MRLUPDF) != RESET) { /* Clear SETMRL CCC flag */ LL_I3C_ClearFlag_MRLUPD(hi3c->Instance); @@ -6806,7 +7026,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target detect reset pattern (broadcast or direct RSTACT CCC) event management -------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_RSTF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_RSTIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_RSTF) != RESET) { /* Clear reset pattern flag */ LL_I3C_ClearFlag_RST(hi3c->Instance); @@ -6816,7 +7036,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive activity state update (direct or broadcast ENTASx) CCC event management ----------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_ASUPDF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_ASUPDIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_ASUPDF) != RESET) { /* Clear ENTASx CCC flag */ LL_I3C_ClearFlag_ASUPD(hi3c->Instance); @@ -6826,8 +7046,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive a direct or broadcast ENEC/DISEC CCC event management ----------------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_INTUPDF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_INTUPDIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_INTUPDF) != RESET) { /* Clear ENEC/DISEC CCC flag */ LL_I3C_ClearFlag_INTUPD(hi3c->Instance); @@ -6837,7 +7056,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive a broadcast DEFTGTS CCC event management -----------------------------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_DEFF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_DEFIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DEFF) != RESET) { /* Clear DEFTGTS CCC flag */ LL_I3C_ClearFlag_DEF(hi3c->Instance); @@ -6847,7 +7066,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target receive a group addressing (broadcast DEFGRPA CCC) event management ----------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_GRPF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_GRPIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_GRPF) != RESET) { /* Clear DEFGRPA CCC flag */ LL_I3C_ClearFlag_GRP(hi3c->Instance); @@ -6857,7 +7076,7 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin } /* I3C target wakeup event management ----------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_WKPF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_WKPIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) { /* Clear WKP flag */ LL_I3C_ClearFlag_WKP(hi3c->Instance); @@ -6887,14 +7106,13 @@ static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uin * @brief Interrupt Sub-Routine which handles Controller received events. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_IBIF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_IBIIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) { /* Clear IBI request flag */ LL_I3C_ClearFlag_IBI(hi3c->Instance); @@ -6909,7 +7127,7 @@ static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, ui } /* I3C controller controller-role request event management ---------------------------------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_CRF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_CRIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) { /* Clear controller-role request flag */ LL_I3C_ClearFlag_CR(hi3c->Instance); @@ -6924,7 +7142,7 @@ static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, ui } /* I3C controller hot-join event management ------------------------------------------------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_HJF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_HJIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) { /* Clear hot-join flag */ LL_I3C_ClearFlag_HJ(hi3c->Instance); @@ -6948,14 +7166,13 @@ static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, ui * @brief Interrupt Sub-Routine which handles target hot join event. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C target receive a dynamic address update event management */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_DAUPDF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_DAUPDIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DAUPDF) != RESET) { /* Clear dynamic address update flag */ LL_I3C_ClearFlag_DAUPD(hi3c->Instance); @@ -6994,14 +7211,13 @@ static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, u * @brief Interrupt Sub-Routine which handles target control role event. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C target complete controller-role hand-off procedure (direct GETACCR CCC) event management -------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_CRUPDF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_CRUPDIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRUPDF) != RESET) { /* Clear controller-role update flag */ LL_I3C_ClearFlag_CRUPD(hi3c->Instance); @@ -7029,15 +7245,13 @@ static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, * @brief Interrupt Sub-Routine which handles target IBI event. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* I3C target IBI end process event management ---------------------------------------------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_IBIENDF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_IBIENDIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIENDF) != RESET) { /* Clear IBI end flag */ LL_I3C_ClearFlag_IBIEND(hi3c->Instance); @@ -7065,18 +7279,16 @@ static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 * @brief Interrupt Sub-Routine which handles target transmit data in Interrupt mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that a Tx process is ongoing */ if (hi3c->State == HAL_I3C_STATE_BUSY_TX) { /* I3C Tx FIFO not full interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_TXFNFF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_TXFNFIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) { if (hi3c->TxXferCount > 0U) { @@ -7086,7 +7298,7 @@ static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 } /* I3C target frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7119,7 +7331,7 @@ static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 } /* I3C target wakeup event management ----------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_WKPF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_WKPIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) { /* Clear WKP flag */ LL_I3C_ClearFlag_WKP(hi3c->Instance); @@ -7141,18 +7353,16 @@ static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 * @brief Interrupt Sub-Routine which handles target receive data in Interrupt mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that an Rx process is ongoing */ if (hi3c->State == HAL_I3C_STATE_BUSY_RX) { /* I3C Rx FIFO not empty interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, HAL_I3C_FLAG_RXFNEF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, HAL_I3C_IT_RXFNEIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) { if (hi3c->RxXferCount > 0U) { @@ -7162,7 +7372,7 @@ static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 } /* I3C target frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7195,7 +7405,7 @@ static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 } /* I3C target wakeup event management ----------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_WKPF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_WKPIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) { /* Clear WKP flag */ LL_I3C_ClearFlag_WKP(hi3c->Instance); @@ -7218,17 +7428,16 @@ static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32 * @brief Interrupt Sub-Routine which handles target transmit data in DMA mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that a Tx process is ongoing */ if (hi3c->State == HAL_I3C_STATE_BUSY_TX) { /* I3C target frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7264,7 +7473,7 @@ static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, ui } /* I3C target wakeup event management ----------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_WKPF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_WKPIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) { /* Clear WKP flag */ LL_I3C_ClearFlag_WKP(hi3c->Instance); @@ -7286,17 +7495,16 @@ static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, ui * @brief Interrupt Sub-Routine which handles target receive data in DMA mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that a Rx process is ongoing */ if (hi3c->State == HAL_I3C_STATE_BUSY_RX) { /* I3C target frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7332,7 +7540,7 @@ static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, ui } /* I3C target wakeup event management ----------------------------------*/ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_WKPF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_WKPIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) { /* Clear WKP flag */ LL_I3C_ClearFlag_WKP(hi3c->Instance); @@ -7355,18 +7563,16 @@ static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, ui * @brief Interrupt Sub-Routine which handles controller transmission in interrupt mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that a Tx process is ongoing */ if (hi3c->State == HAL_I3C_STATE_BUSY_TX) { /* Check if Control FIFO requests data */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_CFNFF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_CFNFIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) { if (hi3c->ControlXferCount > 0U) { @@ -7376,8 +7582,7 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 } /* I3C Tx FIFO not full interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_TXFNFF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_TXFNFIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) { if (hi3c->TxXferCount > 0U) { @@ -7387,7 +7592,7 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 } /* I3C target frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7433,18 +7638,16 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 * @brief Interrupt Sub-Routine which handles controller reception in interrupt mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that an Rx process is ongoing */ if (hi3c->State == HAL_I3C_STATE_BUSY_RX) { /* Check if Control FIFO requests data */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_CFNFF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_CFNFIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) { if (hi3c->ControlXferCount > 0U) { @@ -7454,8 +7657,7 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 } /* I3C Rx FIFO not empty interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, HAL_I3C_FLAG_RXFNEF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, HAL_I3C_IT_RXFNEIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) { if (hi3c->RxXferCount > 0U) { @@ -7465,8 +7667,7 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 } /* I3C Tx FIFO not full interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_TXFNFF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_TXFNFIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) { if (hi3c->TxXferCount > 0U) { @@ -7476,7 +7677,7 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 } /* I3C target frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7521,20 +7722,16 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint3 * @brief Interrupt Sub-Routine which handles controller multiple transmission/reception in interrupt mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef *hi3c, - uint32_t itFlags, - uint32_t itSources) +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that a Tx/Rx process is ongoing */ if (hi3c->State == HAL_I3C_STATE_BUSY_TX_RX) { /* Check if Control FIFO requests data */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_CFNFF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_CFNFIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) { if (hi3c->ControlXferCount > 0U) { @@ -7544,8 +7741,7 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef * } /* I3C Tx FIFO not full interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_TXFNFF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_TXFNFIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) { if (hi3c->TxXferCount > 0U) { @@ -7555,8 +7751,7 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef * } /* I3C Rx FIFO not empty interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, HAL_I3C_FLAG_RXFNEF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, HAL_I3C_IT_RXFNEIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) { if (hi3c->RxXferCount > 0U) { @@ -7566,7 +7761,7 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef * } /* I3C target frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7603,15 +7798,189 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef * return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handles controller transmission and Controller received events + * in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Tx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) + { + /* Clear IBI request flag */ + LL_I3C_ClearFlag_IBI(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_IBI); +#else + /* Asynchronous IBI event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller controller-role request event management ---------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) + { + /* Clear controller-role request flag */ + LL_I3C_ClearFlag_CR(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_CR); +#else + /* Asynchronous controller-role event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller hot-join event management ------------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) + { + /* Clear hot-join flag */ + LL_I3C_ClearFlag_HJ(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_HJ); +#else + /* Asynchronous hot-join event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* ISR controller transmission */ + return (I3C_Ctrl_Tx_ISR(hi3c, itMasks)); +} + +/** + * @brief Interrupt Sub-Routine which handles controller reception and Controller received events in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Rx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) + { + /* Clear IBI request flag */ + LL_I3C_ClearFlag_IBI(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_IBI); +#else + /* Asynchronous IBI event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller controller-role request event management ---------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) + { + /* Clear controller-role request flag */ + LL_I3C_ClearFlag_CR(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_CR); +#else + /* Asynchronous controller-role event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller hot-join event management ------------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) + { + /* Clear hot-join flag */ + LL_I3C_ClearFlag_HJ(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_HJ); +#else + /* Asynchronous hot-join event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* ISR controller reception */ + return (I3C_Ctrl_Rx_ISR(hi3c, itMasks)); +} + +/** + * @brief Interrupt Sub-Routine which handles controller multiple transmission/reception and + * Controller received eventsin interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) + { + /* Clear IBI request flag */ + LL_I3C_ClearFlag_IBI(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_IBI); +#else + /* Asynchronous IBI event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller controller-role request event management ---------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) + { + /* Clear controller-role request flag */ + LL_I3C_ClearFlag_CR(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_CR); +#else + /* Asynchronous controller-role event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller hot-join event management ------------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) + { + /* Clear hot-join flag */ + LL_I3C_ClearFlag_HJ(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_HJ); +#else + /* Asynchronous hot-join event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* ISR controller transmission/reception */ + return (I3C_Ctrl_Multiple_Xfer_ISR(hi3c, itMasks)); +} /** * @brief Interrupt Sub-Routine which handles controller CCC Dynamic Address Assignment command in interrupt mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { uint64_t target_payload = 0U; @@ -7619,16 +7988,14 @@ static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint if (hi3c->State == HAL_I3C_STATE_BUSY_DAA) { /* I3C Control FIFO not full interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_CFNFF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_CFNFIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) { /* Write ENTDAA CCC information in the control register */ LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_ENTDAA, 0U, LL_I3C_GENERATE_STOP); } /* I3C Tx FIFO not full interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_TXFNFF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_TXFNFIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) { /* Check on the Rx FIFO threshold to know the Dynamic Address Assignment treatment process : byte or word */ if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) @@ -7658,7 +8025,7 @@ static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint } /* I3C frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7687,17 +8054,16 @@ static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint * @brief Interrupt Sub-Routine which handles controller transmit data in DMA mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that a Tx process is ongoing */ if (hi3c->State == HAL_I3C_STATE_BUSY_TX) { /* I3C target frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7756,17 +8122,16 @@ static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, u * @brief Interrupt Sub-Routine which handles controller receive data in DMA mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that an Rx process is ongoing */ if (hi3c->State == HAL_I3C_STATE_BUSY_RX) { /* I3C target frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7825,19 +8190,16 @@ static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, u * @brief Interrupt Sub-Routine which handles controller multiple receive and transmit data in DMA mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, - uint32_t itFlags, - uint32_t itSources) +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that an Rx or Tx process is ongoing */ if (hi3c->State == HAL_I3C_STATE_BUSY_TX_RX) { /* I3C target frame complete event Check */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -7903,18 +8265,16 @@ static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeD * @brief Interrupt Sub-Routine which handles abort process in interrupt mode. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information * for the specified I3C. - * @param itFlags : [IN] Interrupt flags to handle. - * @param itSources : [IN] Interrupt sources enabled. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ -static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itFlags, uint32_t itSources) +static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) { /* Check that an Abort process is ongoing */ if (hi3c->State == HAL_I3C_STATE_ABORT) { /* I3C Rx FIFO not empty interrupt Check */ - if ((I3C_CHECK_FLAG(itFlags, HAL_I3C_FLAG_RXFNEF) != RESET) && - (I3C_CHECK_IT_SOURCE(itSources, HAL_I3C_IT_RXFNEIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) { if (LL_I3C_IsActiveFlag_DOVR(hi3c->Instance) == 1U) { @@ -7926,7 +8286,7 @@ static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_ /* I3C Abort frame complete event Check */ /* Evenif abort is called, the Frame completion can arrive if abort is requested at the end of the processus */ /* Evenif completion occurs, treat this end of processus as abort completion process */ - if ((I3C_CHECK_FLAG(itFlags, I3C_EVR_FCF) != RESET) && (I3C_CHECK_IT_SOURCE(itSources, I3C_IER_FCIE) != RESET)) + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) { /* Clear frame complete flag */ LL_I3C_ClearFlag_FC(hi3c->Instance); @@ -8548,12 +8908,12 @@ static HAL_StatusTypeDef I3C_Xfer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint /** * @brief I3C fill Tx Buffer with data from CCC Descriptor. - * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration - * information for the specified I3C. - * @param indexDesc : [IN] Index of descriptor. - * @param txSize : [IN] Size of Tx data. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param indexDesc : [IN] Index of descriptor. + * @param txSize : [IN] Size of Tx data. * @param txCurrentIndex : [IN] Current Index of TxBuffer. - * @retval index_tx : [OUT] New current Index of TxBuffer. + * @retval index_tx : [OUT] New current Index of TxBuffer. */ static uint32_t I3C_FillTxBuffer_CCC(I3C_HandleTypeDef *hi3c, uint32_t indexDesc, @@ -8574,12 +8934,12 @@ static uint32_t I3C_FillTxBuffer_CCC(I3C_HandleTypeDef *hi3c, /** * @brief I3C fill Tx Buffer with data from Private Descriptor. - * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration - * information for the specified I3C. - * @param indexDesc : [IN] Index of descriptor. - * @param txSize : [IN] Size of Tx data. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param indexDesc : [IN] Index of descriptor. + * @param txSize : [IN] Size of Tx data. * @param txCurrentIndex : [IN] Current Index of TxBuffer. - * @retval index_tx : [OUT] New current Index of TxBuffer. + * @retval index_tx : [OUT] New current Index of TxBuffer. */ static uint32_t I3C_FillTxBuffer_Private(I3C_HandleTypeDef *hi3c, uint32_t indexDesc, diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c index 00b580252f..4ce76ea02c 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c @@ -51,6 +51,11 @@ (#) Enable and disable the Instruction Cache with respectively HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. + To ensure a deterministic cache behavior after power on, system reset or after + a call to @ref HAL_ICACHE_Disable(), the application must call + @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset + or cache disable, an automatic cache invalidation procedure is launched and the + cache is bypassed until the operation completes. (#) Initiate the cache maintenance invalidation procedure with either HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() @@ -185,34 +190,34 @@ HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) /** * @brief DeInitialize the Instruction Cache. - * @retval HAL status (HAL_OK/HAL_TIMEOUT) + * @retval HAL status (HAL_OK) */ HAL_StatusTypeDef HAL_ICACHE_DeInit(void) { - HAL_StatusTypeDef status; + /* Reset interrupt enable value */ + WRITE_REG(ICACHE->IER, 0U); - /* Disable cache with reset value for 2-ways set associative mode */ + /* Clear any pending flags */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); + + /* Disable cache then set default associative mode value */ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); /* Stop monitor and reset monitor values */ - (void)HAL_ICACHE_Monitor_Stop(ICACHE_MONITOR_HIT_MISS); - (void)HAL_ICACHE_Monitor_Reset(ICACHE_MONITOR_HIT_MISS); + CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); + SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); #if defined(ICACHE_CRRx_REN) - /* No remapped regions */ - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_0); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_1); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_2); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_3); + /* Reset regions configuration values */ + WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); #endif /* ICACHE_CRRx_REN */ - /* Wait for end of invalidate cache procedure */ - status = HAL_ICACHE_WaitForInvalidateComplete(); - - /* Clear any pending flags */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); - - return status; + return HAL_OK; } /** @@ -285,22 +290,15 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) { HAL_StatusTypeDef status; - /* Check no ongoing operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) - { - status = HAL_ERROR; - } - else + /* Check if no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) { - /* Make sure BSYENDF is reset before to start cache invalidation */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - /* Launch cache invalidation */ SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); - - status = HAL_ICACHE_WaitForInvalidateComplete(); } + status = HAL_ICACHE_WaitForInvalidateComplete(); + return status; } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c index 2b6c22cb98..373df018e8 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_mmc.c @@ -56,7 +56,6 @@ (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization - *** MMC Card Initialization and configuration *** ================================================ [..] @@ -549,7 +548,6 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) return HAL_OK; } - /** * @brief Initializes the MMC MSP. * @param hmmc: Pointer to MMC handle @@ -3537,7 +3535,6 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc) * @{ */ - /** * @brief Initializes the mmc card. * @param hmmc: Pointer to MMC handle @@ -3621,7 +3618,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->ErrorCode |= errorstate; } - /* Get Extended CSD parameters */ if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) { @@ -3871,7 +3867,6 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) tmp = hmmc->pRxBuffPtr; - if (hmmc->RxXferSize >= SDMMC_FIFO_SIZE) { /* Read data from SDMMC Rx FIFO */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c index ff123ebce2..41fba182a4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c @@ -9,7 +9,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c index 517c6fa684..b3cbbb97ba 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c @@ -9,7 +9,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c index 8e18b71017..b040a96e1a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c @@ -1619,11 +1619,20 @@ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) * @param ep_addr endpoint address * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(ep_addr); + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); return HAL_OK; } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c index 4d77c6b31d..d130001620 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c @@ -309,6 +309,7 @@ HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode); void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in); void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in); void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in); +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in); void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in); void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in); @@ -727,6 +728,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca (++) HAL_PKA_ECCMulFastMode() (++) HAL_PKA_ECCMul_GetResult(); + (++) HAL_PKA_ECCMulEx() (++) HAL_PKA_ECCDoubleBaseLadder() (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); (++) HAL_PKA_ECCProjective2Affine() @@ -771,6 +773,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca (++) HAL_PKA_ECCMulFastMode_IT(); (++) HAL_PKA_ECCMul_GetResult(); + (++) HAL_PKA_ECCMulEx_IT(); (++) HAL_PKA_ECCDoubleBaseLadder_IT() (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); (++) HAL_PKA_ECCProjective2Affine_IT() @@ -808,9 +811,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - opsize = in->OpSize; - /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout); } @@ -825,9 +826,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - opsize = in->OpSize; - /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP); } @@ -843,9 +842,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - opsize = in->OpSize; - /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout); } @@ -860,9 +857,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - opsize = in->OpSize; - /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); } @@ -880,9 +875,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpP { /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); - opsize = in->OpSize; - return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout); } @@ -897,12 +890,11 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE { /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); - opsize = in->OpSize; - return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); } + /** * @brief Retrieve operation result. * @param hpka PKA handle @@ -931,9 +923,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - primeordersize = in->primeOrderSize; - /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout); } @@ -948,9 +938,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - primeordersize = in->primeOrderSize; - /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE); } @@ -1128,9 +1116,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - modulussize = in->modulusSize; - /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1145,9 +1131,37 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - modulussize = in->modulusSize; + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); +} +/** + * @brief ECC scalar multiplication extended in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + modulussize = in->modulusSize; + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); +} +/** + * @brief ECC scalar multiplication extended in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + modulussize = in->modulusSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1704,13 +1718,11 @@ void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka) void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) { uint32_t mode = PKA_GetMode(hpka); - FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR); - FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR); - FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND); - FlagStatus operErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR); + uint32_t itsource = READ_REG(hpka->Instance->CR); + uint32_t flag = READ_REG(hpka->Instance->SR); /* Address error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET)) + if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR; @@ -1719,7 +1731,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* RAM access error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET)) + if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR; @@ -1728,7 +1740,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* OPERATION access error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_FLAG_OPERR) == SET) && (operErrFlag == SET)) + if (((itsource & PKA_IT_OPERR) == PKA_IT_OPERR) && ((flag & PKA_FLAG_OPERR) == PKA_FLAG_OPERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; @@ -1792,7 +1804,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* End Of Operation interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET)) + if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND)) { /* Clear PROCEND flag */ __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND); @@ -2591,7 +2603,50 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); } +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder)); + + /* Get the modulus length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters coefficient b to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + /* Move the input parameters scalar multiplier k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters curve prime order N to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); +} /** * @brief Set input parameters. diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pssi.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pssi.c index 8f44a72181..9fd47dc085 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pssi.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pssi.c @@ -53,7 +53,6 @@ (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API. - (#) For PSSI IO operations, two operation modes are available within this driver : *** Polling mode IO operation *** @@ -166,7 +165,6 @@ */ - /** * @} */ @@ -651,8 +649,8 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u HAL_PSSI_DISABLE(hpssi); /* Configure transfer parameters */ - hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL); + MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL), + (PSSI_CR_OUTEN_OUTPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL))); #if defined(HAL_DMA_MODULE_ENABLED) /* DMA Disable */ @@ -804,8 +802,8 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui /* Disable the selected PSSI peripheral */ HAL_PSSI_DISABLE(hpssi); /* Configure transfer parameters */ - hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL); + MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL), + (PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL))); #if defined(HAL_DMA_MODULE_ENABLED) /* DMA Disable */ @@ -1122,7 +1120,7 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat if (hpssi->hdmarx != NULL) { /* Configure BusWidth */ - if (hpssi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE) + if (hpssi->hdmarx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE) { MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE | ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c index f59fbd1dbd..dee00c6180 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c @@ -672,13 +672,23 @@ void HAL_PWREx_DisableFlashPowerDown(void) * content. The user can select which memory is discarded during STOP * mode by means of xxSO bits. * @param MemoryBlock : Specifies the memory block to shut-off during Stop mode. - * This parameter can be one of the following values: - * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode - * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode - * @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode - * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode - * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode - * @note The PWR_ETHERNET_MEMORY_BLOCK is not available for STM32H503xx devices. + * This parameter can be one of the following values for STM32H573xx/STM32H563xx/STM32H562xx : + * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode + * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H533xx/STM32H523xx : + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H503xx : + * @arg PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO : RAM2 shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode * @retval None. */ void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock) @@ -694,13 +704,23 @@ void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock) * @brief Disable memory block shut-off in Stop mode * @param MemoryBlock : Specifies the memory block to keep content during * Stop mode. - * This parameter can be one of the following values: - * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode - * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode - * @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode - * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode - * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode - * @note The PWR_ETHERNET_MEMORY_BLOCK is not available for STM32H503xx devices. + * This parameter can be one of the following values for STM32H573xx/STM32H563xx/STM32H562xx : + * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode + * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H533xx/STM32H523xx : + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H503xx : + * @arg PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO : RAM2 shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode * @retval None. */ void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_ramcfg.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_ramcfg.c index 2399b43706..4e081081fd 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_ramcfg.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_ramcfg.c @@ -1,13 +1,12 @@ /** ****************************************************************************** * @file stm32h5xx_hal_ramcfg.c - * @author MCD Application Team + * @author GPM Application Team * @brief RAMCFG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the RAMs configuration controller peripheral: * + RAMCFG Initialization and De-initialization Functions. * + RAMCFG ECC Operation Functions. - * + RAMCFG Configure Wait State Functions. * + RAMCFG Write Protection Functions. * + RAMCFG Erase Operation Functions. * + RAMCFG Handle Interrupt and Callbacks Functions. @@ -76,8 +75,11 @@ call HAL_RAMCFG_GetDoubleErrorAddress() to get the address of the last fail RAM word detected (only for double error). - (+) Call HAL_RAMCFG_IsECCErrorDetected() to check if an ECC single/double - error was detected. This API is used in silent mode (No ECC interrupt + (+) Call HAL_RAMCFG_IsECCSingleErrorDetected() to check if an ECC single + error was detected. + Call HAL_RAMCFG_IsECCDoubleErrorDetected() to check if an ECC double + error was detected. + These APIs are used in silent mode (No ECC interrupt is enabled). *** Write protection feature *** @@ -217,7 +219,7 @@ HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg) /* Clear RAMCFG monitor flags */ __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAGS_ALL); - /* Initialise the RAMCFG error code */ + /* Initialize the RAMCFG error code */ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE; /* Initialize the RAMCFG state */ @@ -329,8 +331,10 @@ __weak void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg) The HAL_RAMCFG_DisableNotification() function allows disabling interrupts for single ECC error, double ECC error. When NMI interrupt is enabled it can only be disabled by a global peripheral reset or by a system reset. - The HAL_RAMCFG_IsECCErrorDetected() function allows to check if an ECC error - has occurred. + The HAL_RAMCFG_IsECCSingleErrorDetected() function allows to check if an + single ECC error has occurred. + The HAL_RAMCFG_IsECCDoubleErrorDetected() function allows to check if an + double ECC error has occurred. The HAL_RAMCFG_GetSingleErrorAddress() function allows to get the address of the last single ECC error detected. The HAL_RAMCFG_GetDoubleErrorAddress() function allows to get the address of @@ -364,10 +368,15 @@ HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg) { /* Start the SRAM ECC mechanism and latching the error address */ hramcfg->Instance->CR |= (RAMCFG_CR_ECCE | RAMCFG_CR_ALE); - - /* Update the RAMCFG state */ - hramcfg->State = HAL_RAMCFG_STATE_READY; } + else + { + /* Start latching the error address */ + hramcfg->Instance->CR |= RAMCFG_CR_ALE; + } + + /* Update the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_READY; } else { @@ -407,10 +416,9 @@ HAL_StatusTypeDef HAL_RAMCFG_StopECC(RAMCFG_HandleTypeDef *hramcfg) /* Stop the SRAM ECC mechanism and latching the error address */ hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE); - - /* Update the RAMCFG state */ - hramcfg->State = HAL_RAMCFG_STATE_READY; } + /* Update the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_READY; } else { @@ -530,7 +538,7 @@ uint32_t HAL_RAMCFG_IsECCDoubleErrorDetected(const RAMCFG_HandleTypeDef *hramcfg /* Check the parameters */ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance)); - /* Return the state of DEDC flag */ + /* Return the state of DED flag */ return ((READ_BIT(hramcfg->Instance->ISR, RAMCFG_FLAG_DOUBLEERR) == (RAMCFG_FLAG_DOUBLEERR)) ? 1UL : 0UL); } @@ -563,6 +571,7 @@ uint32_t HAL_RAMCFG_GetDoubleErrorAddress(const RAMCFG_HandleTypeDef *hramcfg) return hramcfg->Instance->DEAR; } + /** * @} */ @@ -602,6 +611,9 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg uint32_t page_mask_0 = 0U; uint32_t page_mask_1 = 0U; +#if defined (RAMCFG_WPR3_P64WP) + uint32_t page_mask_2 = 0U; +#endif /* RAMCFG_WPR3_P64WP */ /* Check the parameters */ assert_param(IS_RAMCFG_WP_INSTANCE(hramcfg->Instance)); assert_param(IS_RAMCFG_WRITEPROTECTION_PAGE(StartPage + NbPage)); @@ -612,6 +624,7 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg /* Update RAMCFG peripheral state */ hramcfg->State = HAL_RAMCFG_STATE_BUSY; +#if defined (RAMCFG_WPR3_P64WP) /* Repeat for page number to be protected */ for (uint32_t count = 0U; count < NbPage; count++) { @@ -619,16 +632,38 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg { page_mask_0 |= (1UL << (StartPage + count)); } - else + else if ((StartPage + count) < 64U) { page_mask_1 |= (1UL << ((StartPage + count) - 32U)); } + else + { + page_mask_2 |= (1UL << ((StartPage + count) - 64U)); + } } /* Apply mask to protect pages */ SET_BIT(hramcfg->Instance->WPR1, page_mask_0); SET_BIT(hramcfg->Instance->WPR2, page_mask_1); + SET_BIT(hramcfg->Instance->WPR3, page_mask_2); +#else + /* Repeat for page number to be protected */ + for (uint32_t count = 0U; count < NbPage; count++) + { + if ((StartPage + count) < 32U) + { + page_mask_0 |= (1UL << (StartPage + count)); + } + else + { + page_mask_1 |= (1UL << ((StartPage + count) - 32U)); + } + } + /* Apply mask to protect pages */ + SET_BIT(hramcfg->Instance->WPR1, page_mask_0); + SET_BIT(hramcfg->Instance->WPR2, page_mask_1); +#endif /* RAMCFG_WPR3_P64WP */ /* Update the RAMCFG state */ hramcfg->State = HAL_RAMCFG_STATE_READY; } @@ -641,6 +676,7 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg return status; } + /** * @} */ @@ -718,6 +754,7 @@ HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg) return HAL_OK; } + /** * @} */ @@ -1009,6 +1046,7 @@ HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, H return status; } + /** * @} */ @@ -1022,7 +1060,7 @@ HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, H =============================================================================== [..] This section provides functions to check and get the RAMCFG state - and the error code. + and the error code. [..] The HAL_RAMCFG_GetState() function allows the user to get the RAMCFG peripheral state. @@ -1064,6 +1102,7 @@ uint32_t HAL_RAMCFG_GetError(const RAMCFG_HandleTypeDef *hramcfg) /* Return the RAMCFG error code */ return hramcfg->ErrorCode; } + /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c index 3ed66c6e5f..b142aa486f 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c @@ -1697,11 +1697,11 @@ void HAL_RCC_NMI_IRQHandler(void) /* Check RCC CSSF interrupt flag */ if (__HAL_RCC_GET_IT(RCC_IT_HSECSS)) { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_HSECSS); + + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); } } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c index aee5e94430..ee5954a180 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c @@ -1152,9 +1152,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe /* I3C2 clock source config set later after clock selection check */ break; +#if defined(RCC_I3C2CLKSOURCE_PLL3R) + case RCC_I3C2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I3C2*/ + /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); +#else case RCC_I3C2CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I3C2*/ /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); +#endif /* RCC_I3C2CLKSOURCE_PLL3R */ /* I3C2 clock source config set later after clock selection check */ break; @@ -2436,7 +2442,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe } - /** * @brief Get the pPeriphClkInit according to the internal RCC configuration registers. * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that @@ -4185,11 +4190,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { frequency = HAL_RCC_GetPCLK3Freq(); } +#if defined(RCC_I3C1CLKSOURCE_PLL3R) + else if (srcclk == RCC_I3C2CLKSOURCE_PLL3R) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } +#else else if (srcclk == RCC_I3C2CLKSOURCE_PLL2R) { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_R_Frequency; } +#endif /* RCC_I3C1CLKSOURCE_PLL3R */ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I3C2CLKSOURCE_HSI)) { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c index 0fc1114968..d29d91044b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c @@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Get tick */ tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { @@ -674,8 +674,6 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Update the error code and status */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; status = HAL_ERROR; - /* Clear bit DRDY */ - CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); } else /* No seed error */ { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c index c0fe2f2816..96bd9d982b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -41,7 +41,7 @@ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -53,11 +53,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -269,7 +269,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc.c index dfc0394eb8..5b87abc51a 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc.c @@ -1349,14 +1349,8 @@ void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc) /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set RTC_CR_BKP Bit */ SET_BIT(RTC->CR, RTC_CR_BKP); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /** @@ -1369,14 +1363,8 @@ void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc) /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Clear RTC_CR_BKP Bit */ CLEAR_BIT(RTC->CR, RTC_CR_BKP); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /** @@ -1539,9 +1527,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } } - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Alarm register */ if (sAlarm->Alarm == RTC_ALARM_A) { @@ -1616,9 +1601,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA SET_BIT(RTC->CR, RTC_CR_ALRBE); } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1758,9 +1740,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } } - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Alarm registers */ if (sAlarm->Alarm == RTC_ALARM_A) { @@ -1833,9 +1812,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1865,9 +1841,6 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ if (Alarm == RTC_ALARM_A) { @@ -1884,9 +1857,6 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc_ex.c index c303104373..348ead9a4b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc_ex.c @@ -247,9 +247,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Get the RTC_CR register and clear the bits to be configured */ #if defined(RTC_CR_TSEDGE) CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE)); @@ -260,9 +257,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /* Configure the Time Stamp TSEDGE and Enable bits */ SET_BIT(RTC->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -306,9 +300,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Get the RTC_CR register and clear the bits to be configured */ #if defined(RTC_CR_TSEDGE) CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); @@ -322,9 +313,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /* Enable timestamp and IT */ SET_BIT(RTC->CR, RTC_CR_TSE | RTC_CR_TSIE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -347,9 +335,6 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ #if defined(RTC_CR_TSEDGE) CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); @@ -357,9 +342,6 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) CLEAR_BIT(RTC->CR, (RTC_CR_TSE | RTC_CR_TSIE)); #endif /* RTC_CR_TSEDGE */ - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -384,15 +366,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the internal Time Stamp Enable bits */ SET_BIT(RTC->CR, RTC_CR_ITSE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -415,15 +391,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the internal Time Stamp Enable bits */ CLEAR_BIT(RTC->CR, RTC_CR_ITSE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -619,9 +589,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Clear WUTE in RTC_CR to disable the wakeup timer */ CLEAR_BIT(RTC->CR, RTC_CR_WUTE); @@ -639,9 +606,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* New check to avoid false timeout detection in case of preemption */ if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_TIMEOUT; @@ -667,9 +631,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Enable the Wakeup Timer */ SET_BIT(RTC->CR, RTC_CR_WUTE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -708,9 +669,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Clear WUTE in RTC_CR to disable the wakeup timer */ CLEAR_BIT(RTC->CR, RTC_CR_WUTE); @@ -730,9 +688,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* New check to avoid false timeout detection in case of preemption */ if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_TIMEOUT; @@ -758,9 +713,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/ SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE)); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -777,52 +729,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t */ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart; - /* Process Locked */ __HAL_LOCK(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Disable the Wakeup Timer */ /* In case of interrupt mode is used, the interrupt source must disabled */ CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE)); - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - else - { - break; - } - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -993,9 +909,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - tickstart = HAL_GetTick(); /* check if a calibration is pending */ @@ -1006,8 +919,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo /* New check to avoid false timeout detection in case of preemption */ if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_TIMEOUT; @@ -1024,6 +935,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo } } + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Configure the Smooth calibration settings */ MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue)); @@ -1104,9 +1018,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - tickstart = HAL_GetTick(); /* Wait until the shift is completed */ @@ -1117,9 +1028,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh /* New check to avoid false timeout detection in case of preemption */ if (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_TIMEOUT; @@ -1135,6 +1043,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh } } + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + #if defined(RTC_CR_REFCKON) /* Check if the reference clock detection is disabled */ if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U) @@ -1210,18 +1121,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32 /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the RTC_CR register */ MODIFY_REG(RTC->CR, RTC_CR_COSEL, CalibOutput); /* Enable calibration output */ SET_BIT(RTC->CR, RTC_CR_COE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1244,15 +1149,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Disable calibration output */ CLEAR_BIT(RTC->CR, RTC_CR_COE); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1368,15 +1267,9 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set the BYPSHAD bit */ SET_BIT(RTC->CR, RTC_CR_BYPSHAD); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1401,15 +1294,9 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Reset the BYPSHAD bit */ CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1476,15 +1363,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Enable IT SSRU */ __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1507,15 +1388,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_SSRU); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1740,13 +1615,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(const RTC_HandleTypeDef *hrtc, const RTC_T /* Timestamp on tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /* Control register 1 */ @@ -1812,13 +1681,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(const RTC_HandleTypeDef *hrtc, const RT /* Timestamp on tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /* Interrupt enable register */ @@ -1913,13 +1776,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ tmp_cr = READ_REG(RTC->CR); if ((tmp_cr & RTC_CR_TAMPTS) != (sAllTamper->TimeStampOnTamperDetection)) { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sAllTamper->TimeStampOnTamperDetection); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } tmp_cr1 = READ_REG(TAMP->CR1); @@ -2179,13 +2036,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(const RTC_HandleTypeDef *hrtc, /* Timestamp enable on internal tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /* No Erase Backup register enable for Internal Tamper */ @@ -2226,13 +2077,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(const RTC_HandleTypeDef *hrtc, /* Timestamp enable on internal tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /* Interrupt enable register */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c index c0805263a4..cbfe233d1e 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c @@ -171,7 +171,7 @@ [..] Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. [..] @@ -186,10 +186,10 @@ [..] By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SAI_Init + reset to the legacy weak functions in the HAL_SAI_Init and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -206,7 +206,7 @@ [..] When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c index 1ba5e096d9..a2bfe629b0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c @@ -56,7 +56,6 @@ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization - *** SD Card Initialization and configuration *** ================================================ [..] @@ -613,7 +612,6 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) return HAL_OK; } - /** * @brief Initializes the SD MSP. * @param hsd: Pointer to SD handle @@ -1316,7 +1314,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Enable transfer interrupts */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - return HAL_OK; } else @@ -1383,7 +1380,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *p config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMABASER = (uint32_t) pData ; @@ -2330,7 +2326,6 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT status = HAL_ERROR; } - return status; } @@ -2371,6 +2366,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t SDMMC_InitTypeDef Init; uint32_t errorstate; uint32_t sdmmc_clk; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ @@ -2422,11 +2418,15 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1); } #if defined(SDMMC2) - else + else if (hsd->Instance == SDMMC2) { sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC2); } #endif /* SDMMC2 */ + else + { + sdmmc_clk = 0U; + } if (sdmmc_clk != 0U) { /* Configure the SDMMC peripheral */ @@ -2950,7 +2950,6 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) return HAL_OK; } - /** * @brief Abort the current transfer and disable the SD (IT mode). * @param hsd: pointer to a SD_HandleTypeDef structure that contains @@ -3008,7 +3007,6 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) * @{ */ - /** * @brief Initializes the sd card. * @param hsd: Pointer to SD handle @@ -3515,7 +3513,6 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) } } - /** * @brief Finds the SD card SCR register value. * @param hsd: Pointer to SD handle @@ -3570,7 +3567,6 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) index++; } - if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; @@ -3727,7 +3723,6 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); - errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode); if (errorstate != HAL_SD_ERROR_NONE) { @@ -3745,7 +3740,6 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) } loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c index 16e05f8df7..9cb1ef54a6 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sdram.c @@ -9,7 +9,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c index da61bcf8d6..13efd25711 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c @@ -2494,7 +2494,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus.c index 22254296b3..02e9de2206 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus.c @@ -2585,8 +2585,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); + if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) + { + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + } /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus_ex.c index 8d80b1fdae..217ca3f301 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smbus_ex.c @@ -6,6 +6,8 @@ * This file provides firmware functions to manage the following * functionalities of SMBUS Extended peripheral: * + Extended features functions + * + WakeUp Mode Functions + * + FastModePlus Functions * ****************************************************************************** * @attention diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c index 4f55e257cb..02a4f07768 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c @@ -111,9 +111,8 @@ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() or HAL_SPI_Init() function. - When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined, + the callback registering feature is not available and weak callbacks are used. SuspendCallback restriction: SuspendCallback is called only when MasterReceiverAutoSusp is enabled and @@ -152,7 +151,6 @@ * @{ */ #define SPI_DEFAULT_TIMEOUT 100UL -#define MAX_FIFO_LENGTH 16UL /** * @} */ @@ -570,6 +568,8 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) * the configuration information for the specified SPI. * @param CallbackID ID of the callback to be registered * @param pCallback pointer to the Callback function + * @note The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, @@ -584,8 +584,6 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call return HAL_ERROR; } - /* Lock the process */ - __HAL_LOCK(hspi); if (HAL_SPI_STATE_READY == hspi->State) { @@ -674,8 +672,6 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hspi); return status; } @@ -685,15 +681,14 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call * @param hspi Pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI. * @param CallbackID ID of the callback to be unregistered + * @note The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - /* Lock the process */ - __HAL_LOCK(hspi); - if (HAL_SPI_STATE_READY == hspi->State) { switch (CallbackID) @@ -781,8 +776,6 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hspi); return status; } #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -839,31 +832,26 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData #endif /* __GNUC__ */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -921,11 +909,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -965,11 +954,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1014,11 +1004,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1034,16 +1025,19 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { return HAL_ERROR; } - return errorcode; + else + { + return HAL_OK; + } } /** @@ -1058,7 +1052,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; #if defined (__GNUC__) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ @@ -1066,26 +1059,22 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1143,11 +1132,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1178,11 +1168,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1209,11 +1200,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1234,16 +1226,20 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { return HAL_ERROR; } - return errorcode; + else + { + return HAL_OK; + } } /** @@ -1259,22 +1255,19 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - HAL_StatusTypeDef errorcode = HAL_OK; #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ uint32_t tickstart; + uint32_t fifo_length; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1283,18 +1276,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1312,6 +1304,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Set Full-Duplex mode */ SPI_2LINES(hspi); + /* Initialize FIFO length */ + if (IS_SPI_FULL_INSTANCE(hspi->Instance)) + { + fifo_length = SPI_HIGHEND_FIFO_SIZE; + } + else + { + fifo_length = SPI_LOWEND_FIFO_SIZE; + } + /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1326,10 +1328,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Transmit and Receive data in 32 Bit mode */ if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) { + /* Adapt fifo length to 32bits data width */ + fifo_length = (fifo_length / 4UL); + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { /* Check TXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) { *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); @@ -1352,11 +1358,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1364,10 +1371,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Transmit and Receive data in 16 Bit mode */ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { + /* Adapt fifo length to 16bits data width */ + fifo_length = (fifo_length / 2UL); + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { /* Check the TXP flag */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL)) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) { #if defined (__GNUC__) *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); @@ -1398,11 +1409,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1413,7 +1425,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { /* Check the TXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) { *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); @@ -1436,11 +1449,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1455,16 +1469,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { return HAL_ERROR; } - return errorcode; + else + { + return HAL_OK; + } } /** @@ -1477,28 +1494,22 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1542,6 +1553,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); + /* Enable EOT, TXP, FRE, MODF and UDR interrupts */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); @@ -1551,8 +1565,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1565,28 +1578,22 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1634,6 +1641,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); + /* Enable EOT, RXP, OVR, FRE and MODF interrupts */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); @@ -1643,9 +1653,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Unlock the process */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1660,9 +1668,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; uint32_t tmp_TxXferCount; - #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); #endif /* __GNUC__ */ @@ -1670,23 +1676,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1757,6 +1759,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint } } + /* Unlock the process */ + __HAL_UNLOCK(hspi); + /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); @@ -1766,9 +1771,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Unlock the process */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } @@ -1785,28 +1788,24 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode; + HAL_StatusTypeDef status; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1837,9 +1836,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE))) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } /* Adjust XferCount according to DMA alignment / Data size */ @@ -1908,39 +1906,30 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Set DMA destination address */ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, - hspi->TxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } /* Set the number of data at current transfer */ @@ -1970,7 +1959,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + + return HAL_OK; } /** @@ -1984,28 +1974,27 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode; + HAL_StatusTypeDef status; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2035,9 +2024,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } /* Clear RXDMAEN bit */ @@ -2106,39 +2094,30 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set DMA destination address */ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, - hspi->RxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } /* Set the number of data at current transfer */ @@ -2168,7 +2147,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + + return HAL_OK; } /** @@ -2184,28 +2164,24 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - HAL_StatusTypeDef errorcode; + HAL_StatusTypeDef status; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2232,10 +2208,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } /* Adjust XferCount according to DMA alignment / Data size */ @@ -2310,39 +2285,30 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Set DMA destination address */ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, - hspi->RxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2384,39 +2350,33 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Set DMA destination address */ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, - hspi->TxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { + /* Abort Rx DMA Channel already started */ + (void)HAL_DMA_Abort(hspi->hdmarx); + /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) @@ -2445,7 +2405,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + + return HAL_OK; } #endif /* HAL_DMA_MODULE_ENABLED */ @@ -2573,12 +2534,12 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_NONE; } - /* Unlock the process */ - __HAL_UNLOCK(hspi); - /* Restore hspi->state to ready */ hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return errorcode; } @@ -2848,7 +2809,6 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) handled = 1UL; } - if (handled != 0UL) { return; @@ -3334,7 +3294,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->TxHalfCpltCallback(hspi); @@ -3351,7 +3312,8 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRA */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->RxHalfCpltCallback(hspi); @@ -3368,7 +3330,8 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->TxRxHalfCpltCallback(hspi); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c index 0769a12e44..ea761f2d5b 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c @@ -9,7 +9,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c index cdae141f78..664122b9e4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c @@ -3854,7 +3854,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3886,7 +3886,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) @@ -3916,7 +3916,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) @@ -3946,7 +3946,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) @@ -3976,7 +3976,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -3985,11 +3985,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break input event */ - if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else @@ -4015,7 +4016,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -4028,7 +4029,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else @@ -4041,7 +4042,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->EncoderIndexCallback(htim); #else @@ -4054,7 +4055,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->DirectionChangeCallback(htim); #else @@ -4067,7 +4068,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IndexErrorCallback(htim); #else @@ -4080,7 +4081,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TransitionErrorCallback(htim); #else @@ -4617,6 +4618,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_OR1 * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -4633,7 +4635,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) { HAL_StatusTypeDef status = HAL_OK; uint32_t BlockDataLength = 0; @@ -4761,6 +4764,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_OR1 * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -5070,6 +5074,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_OR1 * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -5214,6 +5219,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_OR1 * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -7033,38 +7039,18 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } } else { @@ -7131,42 +7117,18 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } } else { @@ -7230,11 +7192,6 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) - { - htim->State = HAL_TIM_STATE_READY; - } - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -7267,11 +7224,6 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) - { - htim->State = HAL_TIM_STATE_READY; - } - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -7341,6 +7293,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } } /** @@ -7465,7 +7424,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c index 8693b9ef21..0a8426cba4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c @@ -872,7 +872,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1149,17 +1149,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1403,7 +1392,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -2196,6 +2185,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); @@ -2212,15 +2202,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); - - /* Set BREAK AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { @@ -2228,20 +2210,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); - - /* Set BREAK2 AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } /* Set TIMx_BDTR */ @@ -2265,7 +2240,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; @@ -2381,6 +2355,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin (*) * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin (*) + * @arg TIM_TIM2_ETR_USB_SOF TIM2_ETR is connected to USB SOF (*) * @arg TIM_TIM2_ETR_ETH_PPS TIM2 ETR is connected to ETH PPS (*) * * For TIM3, the parameter can take one of the following values: @@ -2399,11 +2374,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * * For TIM5, the parameter can take one of the following values: (**) * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO - * @arg TIM_TIM2_ETR_SAI2_FSA TIM2 ETR is connected to SAI2 FSA - * @arg TIM_TIM2_ETR_SAI2_FSB TIM2 ETR is connected to SAI2 FSB + * @arg TIM_TIM5_ETR_SAI2_FSA TIM5 ETR is connected to SAI2 FSA + * @arg TIM_TIM5_ETR_SAI2_FSB TIM5 ETR is connected to SAI2 FSB * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin * @arg TIM_TIM5_ETR_TIM4_ETR TIM5 ETR is connected to TIM4 ETR pin + * @arg TIM_TIM5_ETR_USB_SOF TIM5_ETR is connected to USB SOF (*) * * For TIM8, the parameter can take one of the following values: (**) * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO @@ -2548,6 +2524,18 @@ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISel { case TIM_CHANNEL_1: MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); + +#if defined(TIM17) + /* If required, set OR1 bit to request HSE 1MHz clock */ + if ((IS_TIM_RTCPREEN_INSTANCE(htim->Instance)) && (IS_TIM_RTCPREEN_SELECTION(TISelection))) + { + SET_BIT(htim->Instance->OR1, TIM_OR1_RTCPREEN); + } + else + { + CLEAR_BIT(htim->Instance->OR1, TIM_OR1_RTCPREEN); + } +#endif /* TIM17 */ break; case TIM_CHANNEL_2: MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); @@ -2620,7 +2608,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B uint32_t tmpbdtr; /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) @@ -2637,7 +2625,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B } break; } - case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ @@ -2675,7 +2662,7 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint3 uint32_t tickstart; /* Check the parameters */ - assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) @@ -3089,7 +3076,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3103,7 +3090,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3118,7 +3105,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3133,7 +3120,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break2 detection callback in non blocking mode + * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ @@ -3322,38 +3309,18 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } } else { @@ -3393,6 +3360,11 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } else { /* nothing to do */ @@ -3424,13 +3396,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha { uint32_t tmp; - tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ } /** * @} diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_timebase_tim_template.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_timebase_tim_template.c index a5ca9c5047..26b4f87854 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_timebase_tim_template.c @@ -112,6 +112,14 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) TimHandle.Init.ClockDivision = 0; TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; status = HAL_TIM_Base_Init(&TimHandle); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + if (status == HAL_OK) + { + status = HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); + } +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + if (status == HAL_OK) { /* Start the TIM time Base generation in interrupt mode */ @@ -130,9 +138,6 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) } } } -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) - HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ HAL_NVIC_EnableIRQ(TIM6_IRQn); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c index d367dbf284..ae35d5a845 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c @@ -973,10 +973,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = pCallback; } @@ -987,9 +984,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -1003,10 +997,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ } @@ -1017,8 +1008,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); return status; } @@ -3433,7 +3422,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_TIMEOUT; } - if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c index 69412887c4..0be95e79f0 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_xspi.c @@ -2387,7 +2387,7 @@ HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSP */ /** - * @brief Abort the current transmission. + * @brief Abort the current operation, return to the indirect mode. * @param hxspi : XSPI handle * @retval HAL status */ @@ -2440,12 +2440,18 @@ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) if (status == HAL_OK) { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + hxspi->State = HAL_XSPI_STATE_READY; } } } else { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + hxspi->State = HAL_XSPI_STATE_READY; } } @@ -2459,7 +2465,7 @@ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) } /** - * @brief Abort the current transmission (non-blocking function) + * @brief Abort the current operation, return to the indirect mode. (non-blocking function) * @param hxspi : XSPI handle * @retval HAL status */ @@ -2523,9 +2529,15 @@ HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) /* Perform an abort of the XSPI */ SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); } else { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + hxspi->State = HAL_XSPI_STATE_READY; /* Abort callback */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_adc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_adc.c index 7c79b7e950..5a5f6c53eb 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_adc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_adc.c @@ -517,11 +517,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Disable ADC instance if not already disabled. */ if (LL_ADC_IsEnabled(ADCx) == 1UL) { - /* Set ADC group regular trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - /* Stop potential ADC conversion on going on ADC group regular. */ if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) { @@ -531,11 +526,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) } } - /* Set ADC group injected trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); - /* Stop potential ADC conversion on going on ADC group injected. */ if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) { diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_crs.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_crs.c index 520e10a742..e1d52d4918 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_crs.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_crs.c @@ -61,7 +61,6 @@ ErrorStatus LL_CRS_DeInit(void) } - /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c index 53a64c35fb..054beb89d7 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma.c @@ -115,6 +115,13 @@ #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_NORMAL) || \ ((__VALUE__) == LL_DMA_PFCTRL)) +#define IS_LL_DMA_PFREQ_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == GPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_0) || \ + ((Channel) == LL_DMA_CHANNEL_7))) || \ + (((INSTANCE) == GPDMA2) && \ + (((Channel) == LL_DMA_CHANNEL_0) || \ + ((Channel) == LL_DMA_CHANNEL_7)))) + #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \ ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)) @@ -229,7 +236,8 @@ #define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \ ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC)) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} */ @@ -346,7 +354,7 @@ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LL_DMA_DisableChannelSecure(DMAx, Channel); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ } return (uint32_t)status; @@ -405,6 +413,10 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr)); assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset)); assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + if (DMA_InitStruct->Mode == LL_DMA_PFCTRL) + { + assert_param(IS_LL_DMA_PFREQ_INSTANCE(DMAx, Channel)); + } /* Check DMA instance */ if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) @@ -742,7 +754,7 @@ void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) /* Set DMA_InitNodeStruct fields to default values */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC; -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0; DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE; DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE; @@ -751,7 +763,7 @@ void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC; -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0; DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE; DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; @@ -765,6 +777,7 @@ void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST; DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY; DMA_InitNodeStruct->Request = 0x00000000U; + DMA_InitNodeStruct->Mode = LL_DMA_NORMAL; DMA_InitNodeStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT; DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT; DMA_InitNodeStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT; @@ -825,7 +838,7 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure)); assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure)); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Check trigger polarity */ if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) @@ -888,7 +901,7 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \ DMA_InitNodeStruct->SrcSecure); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Update CTR1 register fields */ pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \ @@ -1120,10 +1133,10 @@ void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t L * @} */ -#endif /* defined (GPDMA1) */ +#endif /* GPDMA1 */ /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c index b099732d44..5029fdbcf2 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_exti.c @@ -83,6 +83,8 @@ ErrorStatus LL_EXTI_DeInit(void) LL_EXTI_WriteReg(IMR1, 0xFFFE0000U); #if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx)) LL_EXTI_WriteReg(IMR2, 0x03DBBFFFU); +#elif defined(STM32H533xx) + LL_EXTI_WriteReg(IMR2, 0x07DBFFFFU); #else LL_EXTI_WriteReg(IMR2, 0x001BFFFFU); #endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmac.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmac.c index 4451b98497..dfd436e9b4 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmac.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmac.c @@ -113,8 +113,6 @@ ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx) return (status); } - - /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c index 0105b3cce9..cf03303498 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -400,14 +400,15 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | + (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | + (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | + (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) | + (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | + Timing->AccessMode; /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) @@ -629,10 +630,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); + Device->PMEM = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); return HAL_OK; } @@ -660,10 +661,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); + Device->PATT = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); return HAL_OK; } diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c index 27c8de1991..2fdf9fd7ba 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rcc.c @@ -41,35 +41,47 @@ /** @addtogroup RCC_LL_Private_Macros * @{ */ -#if defined(USART6) +#if defined(USART10) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART10_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART11_CLKSOURCE)) +#elif defined(USART6) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE)) #else #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) #endif /* USART6 */ -#if defined(UART4) +#if defined(UART7) #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_UART9_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_UART12_CLKSOURCE)) -#endif /* UART4 */ +#elif defined(UART5) +#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)) +#endif /* UART7 */ #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) -#if defined(I2C3) +#if defined(I2C4) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) +#elif defined(I2C3) +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) #else #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE)) @@ -82,18 +94,23 @@ #define IS_LL_RCC_I3C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I3C1_CLKSOURCE)) #endif /* I3C2 */ -#if defined(SPI4) +#if defined(SPI5) #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SPI4_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SPI5_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE)) +#elif defined(SPI4) +#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SPI4_CLKSOURCE)) #else #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE)) -#endif /* SPI4 */ +#endif /* SPI5 */ #if defined(LPTIM3) #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ @@ -364,63 +381,69 @@ void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks) /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) SYSCLK = PLL_VCO / PLLP */ - pllsource = LL_RCC_PLL1_GetSource(); - switch (pllsource) + pPLL_Clocks->PLL_P_Frequency = LL_RCC_PERIPH_FREQUENCY_NO; + pPLL_Clocks->PLL_Q_Frequency = LL_RCC_PERIPH_FREQUENCY_NO; + pPLL_Clocks->PLL_R_Frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + if (LL_RCC_PLL1_IsReady() != 0U) { - case LL_RCC_PLL1SOURCE_HSI: - if (LL_RCC_HSI_IsReady() != 0U) - { - pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); - } - break; - case LL_RCC_PLL1SOURCE_CSI: - if (LL_RCC_CSI_IsReady() != 0U) - { - pllinputfreq = CSI_VALUE; - } - break; + pllsource = LL_RCC_PLL1_GetSource(); - case LL_RCC_PLL1SOURCE_HSE: - if (LL_RCC_HSE_IsReady() != 0U) - { - pllinputfreq = HSE_VALUE; - } - break; - - case LL_RCC_PLL1SOURCE_NONE: - default: - /* PLL clock disabled */ - break; - } + switch (pllsource) + { + case LL_RCC_PLL1SOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + pllinputfreq = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); + } + break; - pPLL_Clocks->PLL_P_Frequency = 0U; - pPLL_Clocks->PLL_Q_Frequency = 0U; - pPLL_Clocks->PLL_R_Frequency = 0U; + case LL_RCC_PLL1SOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + pllinputfreq = CSI_VALUE; + } + break; - pllm = LL_RCC_PLL1_GetM(); - plln = LL_RCC_PLL1_GetN(); - if (LL_RCC_PLL1FRACN_IsEnabled() != 0U) - { - fracn = LL_RCC_PLL1_GetFRACN(); - } + case LL_RCC_PLL1SOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + pllinputfreq = HSE_VALUE; + } + break; - if (pllm != 0U) - { - if (LL_RCC_PLL1P_IsEnabled() != 0U) - { - pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetP()); + case LL_RCC_PLL1SOURCE_NONE: + default: + /* PLL clock disabled */ + break; } - if (LL_RCC_PLL1Q_IsEnabled() != 0U) + pllm = LL_RCC_PLL1_GetM(); + plln = LL_RCC_PLL1_GetN(); + + if (LL_RCC_PLL1FRACN_IsEnabled() != 0U) { - pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetQ()); + fracn = LL_RCC_PLL1_GetFRACN(); } - if (LL_RCC_PLL1R_IsEnabled() != 0U) + if ((pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO) && (pllm != 0U)) { - pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetR()); + if (LL_RCC_PLL1P_IsEnabled() != 0U) + { + pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetP()); + } + + if (LL_RCC_PLL1Q_IsEnabled() != 0U) + { + pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetQ()); + } + + if (LL_RCC_PLL1R_IsEnabled() != 0U) + { + pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetR()); + } } } } @@ -441,63 +464,69 @@ void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks) /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) SYSCLK = PLL_VCO / PLLP */ - pllsource = LL_RCC_PLL2_GetSource(); - switch (pllsource) - { - case LL_RCC_PLL2SOURCE_HSI: - if (LL_RCC_HSI_IsReady() != 0U) - { - pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); - } - break; + pPLL_Clocks->PLL_P_Frequency = LL_RCC_PERIPH_FREQUENCY_NO; + pPLL_Clocks->PLL_Q_Frequency = LL_RCC_PERIPH_FREQUENCY_NO; + pPLL_Clocks->PLL_R_Frequency = LL_RCC_PERIPH_FREQUENCY_NO; - case LL_RCC_PLL2SOURCE_CSI: - if (LL_RCC_CSI_IsReady() != 0U) - { - pllinputfreq = CSI_VALUE; - } - break; + if (LL_RCC_PLL2_IsReady() != 0U) + { - case LL_RCC_PLL2SOURCE_HSE: - if (LL_RCC_HSE_IsReady() != 0U) - { - pllinputfreq = HSE_VALUE; - } - break; + pllsource = LL_RCC_PLL2_GetSource(); - case LL_RCC_PLL2SOURCE_NONE: - default: - /* PLL clock disabled */ - break; - } + switch (pllsource) + { + case LL_RCC_PLL2SOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + pllinputfreq = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); + } + break; - pPLL_Clocks->PLL_P_Frequency = 0U; - pPLL_Clocks->PLL_Q_Frequency = 0U; - pPLL_Clocks->PLL_R_Frequency = 0U; + case LL_RCC_PLL2SOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + pllinputfreq = CSI_VALUE; + } + break; - pllm = LL_RCC_PLL2_GetM(); - plln = LL_RCC_PLL2_GetN(); - if (LL_RCC_PLL2FRACN_IsEnabled() != 0U) - { - fracn = LL_RCC_PLL2_GetFRACN(); - } + case LL_RCC_PLL2SOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + pllinputfreq = HSE_VALUE; + } + break; - if (pllm != 0U) - { - if (LL_RCC_PLL2P_IsEnabled() != 0U) - { - pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetP()); + case LL_RCC_PLL2SOURCE_NONE: + default: + /* PLL clock disabled */ + break; } - if (LL_RCC_PLL2Q_IsEnabled() != 0U) + pllm = LL_RCC_PLL2_GetM(); + plln = LL_RCC_PLL2_GetN(); + + if (LL_RCC_PLL2FRACN_IsEnabled() != 0U) { - pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetQ()); + fracn = LL_RCC_PLL2_GetFRACN(); } - if (LL_RCC_PLL2R_IsEnabled() != 0U) + if ((pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO) && (pllm != 0U)) { - pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetR()); + if (LL_RCC_PLL2P_IsEnabled() != 0U) + { + pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetP()); + } + + if (LL_RCC_PLL2Q_IsEnabled() != 0U) + { + pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetQ()); + } + + if (LL_RCC_PLL2R_IsEnabled() != 0U) + { + pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetR()); + } } } } @@ -519,63 +548,68 @@ void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks) /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) SYSCLK = PLL_VCO / PLLP */ - pllsource = LL_RCC_PLL3_GetSource(); - switch (pllsource) - { - case LL_RCC_PLL3SOURCE_HSI: - if (LL_RCC_HSI_IsReady() != 0U) - { - pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); - } - break; + pPLL_Clocks->PLL_P_Frequency = LL_RCC_PERIPH_FREQUENCY_NO; + pPLL_Clocks->PLL_Q_Frequency = LL_RCC_PERIPH_FREQUENCY_NO; + pPLL_Clocks->PLL_R_Frequency = LL_RCC_PERIPH_FREQUENCY_NO; - case LL_RCC_PLL3SOURCE_CSI: - if (LL_RCC_CSI_IsReady() != 0U) - { - pllinputfreq = CSI_VALUE; - } - break; + if (LL_RCC_PLL3_IsReady() != 0U) + { - case LL_RCC_PLL3SOURCE_HSE: - if (LL_RCC_HSE_IsReady() != 0U) - { - pllinputfreq = HSE_VALUE; - } - break; + pllsource = LL_RCC_PLL3_GetSource(); - case LL_RCC_PLL3SOURCE_NONE: - default: - /* PLL clock disabled */ - break; - } + switch (pllsource) + { + case LL_RCC_PLL3SOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + pllinputfreq = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); + } + break; - pPLL_Clocks->PLL_P_Frequency = 0U; - pPLL_Clocks->PLL_Q_Frequency = 0U; - pPLL_Clocks->PLL_R_Frequency = 0U; + case LL_RCC_PLL3SOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + pllinputfreq = CSI_VALUE; + } + break; - pllm = LL_RCC_PLL3_GetM(); - plln = LL_RCC_PLL3_GetN(); - if (LL_RCC_PLL3FRACN_IsEnabled() != 0U) - { - fracn = LL_RCC_PLL3_GetFRACN(); - } + case LL_RCC_PLL3SOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + pllinputfreq = HSE_VALUE; + } + break; - if ((pllm != 0U) && (pllinputfreq != 0U)) - { - if (LL_RCC_PLL3P_IsEnabled() != 0U) - { - pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetP()); + case LL_RCC_PLL3SOURCE_NONE: + default: + /* PLL clock disabled */ + break; } - if (LL_RCC_PLL3Q_IsEnabled() != 0U) + pllm = LL_RCC_PLL3_GetM(); + plln = LL_RCC_PLL3_GetN(); + if (LL_RCC_PLL3FRACN_IsEnabled() != 0U) { - pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetQ()); + fracn = LL_RCC_PLL3_GetFRACN(); } - if (LL_RCC_PLL3R_IsEnabled() != 0U) + if ((pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO) && (pllm != 0U)) { - pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetR()); + if (LL_RCC_PLL3P_IsEnabled() != 0U) + { + pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetP()); + } + + if (LL_RCC_PLL3Q_IsEnabled() != 0U) + { + pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetQ()); + } + + if (LL_RCC_PLL3R_IsEnabled() != 0U) + { + pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetR()); + } } } } @@ -663,7 +697,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - usart_frequency = HSI_VALUE; + usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -722,7 +756,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - usart_frequency = HSI_VALUE; + usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -781,7 +815,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - usart_frequency = HSI_VALUE; + usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -840,7 +874,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - usart_frequency = HSI_VALUE; + usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -900,7 +934,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) case LL_RCC_USART10_CLKSOURCE_HSI: /* USART10 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - usart_frequency = HSI_VALUE; + usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -960,7 +994,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) case LL_RCC_USART11_CLKSOURCE_HSI: /* USART11 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - usart_frequency = HSI_VALUE; + usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1047,7 +1081,7 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - uart_frequency = HSI_VALUE; + uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1104,7 +1138,7 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - uart_frequency = HSI_VALUE; + uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1127,6 +1161,7 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) break; } } +#if defined(UART7) else if (UARTxSource == LL_RCC_UART7_CLKSOURCE) { /* UART7CLK clock frequency */ @@ -1161,7 +1196,7 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - uart_frequency = HSI_VALUE; + uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1184,6 +1219,8 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) break; } } +#endif /* UART7 */ +#if defined(UART8) else if (UARTxSource == LL_RCC_UART8_CLKSOURCE) { /* UART8CLK clock frequency */ @@ -1218,7 +1255,7 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - uart_frequency = HSI_VALUE; + uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1241,6 +1278,8 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) break; } } +#endif /* UART8 */ +#if defined(UART9) else if (UARTxSource == LL_RCC_UART9_CLKSOURCE) { /* UART9CLK clock frequency */ @@ -1275,7 +1314,7 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) case LL_RCC_UART9_CLKSOURCE_HSI: /* UART9 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - uart_frequency = HSI_VALUE; + uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1298,6 +1337,8 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) break; } } +#endif /* UART9 */ +#if defined(UART12) else if (UARTxSource == LL_RCC_UART12_CLKSOURCE) { /* UART12CLK clock frequency */ @@ -1332,7 +1373,7 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) case LL_RCC_UART12_CLKSOURCE_HSI: /* UART12 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - uart_frequency = HSI_VALUE; + uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1355,6 +1396,7 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) break; } } +#endif /* UART12 */ else { /* nothing to do */ @@ -1579,7 +1621,7 @@ uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource) case LL_RCC_SPI4_CLKSOURCE_HSI: /* SPI4 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - spi_frequency = HSI_VALUE; + spi_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1638,7 +1680,7 @@ uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource) case LL_RCC_SPI5_CLKSOURCE_HSI: /* SPI5 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - spi_frequency = HSI_VALUE; + spi_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1697,7 +1739,7 @@ uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource) case LL_RCC_SPI6_CLKSOURCE_HSI: /* SPI6 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - spi_frequency = HSI_VALUE; + spi_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1786,7 +1828,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - i2c_frequency = HSI_VALUE; + i2c_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1838,7 +1880,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - i2c_frequency = HSI_VALUE; + i2c_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1879,7 +1921,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - i2c_frequency = HSI_VALUE; + i2c_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -1920,7 +1962,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - i2c_frequency = HSI_VALUE; + i2c_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -2000,7 +2042,7 @@ uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource) case LL_RCC_I3C1_CLKSOURCE_HSI: /* I3C1 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - I3C_frequency = HSI_VALUE; + I3C_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -2024,6 +2066,17 @@ uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource) I3C_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; +#if defined(RCC_CR_PLL3ON) + case LL_RCC_I3C2_CLKSOURCE_PLL3R: /* I3C2 Clock is PLL3 R */ + if (LL_RCC_PLL3_IsReady() != 0U) + { + if (LL_RCC_PLL3R_IsEnabled() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + I3C_frequency = PLL_Clocks.PLL_R_Frequency; + } + } +#else case LL_RCC_I3C2_CLKSOURCE_PLL2R: /* I3C2 Clock is PLL2 R */ if (LL_RCC_PLL2_IsReady() != 0U) { @@ -2033,12 +2086,13 @@ uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource) I3C_frequency = PLL_Clocks.PLL_R_Frequency; } } +#endif /* PLL3 */ break; case LL_RCC_I3C2_CLKSOURCE_HSI: /* I3C2 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - I3C_frequency = HSI_VALUE; + I3C_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -2108,7 +2162,7 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - lpuart_frequency = HSI_VALUE; + lpuart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -2891,7 +2945,7 @@ uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCDACxSource) case LL_RCC_ADCDAC_CLKSOURCE_HSI: /* ADCDAC Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady() == 1U) { - adcdac_frequency = HSI_VALUE; + adcdac_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -3129,7 +3183,7 @@ uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource) case LL_RCC_CLKP_CLKSOURCE_HSI: /* HSI used as CLKP clock source */ if (LL_RCC_HSI_IsReady() != 0U) { - clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + clkp_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); } break; @@ -3182,7 +3236,7 @@ uint32_t RCC_GetSystemClockFreq(void) switch (LL_RCC_GetSysClkSource()) { case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - frequency = HSI_VALUE; + frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); break; case LL_RCC_SYS_CLKSOURCE_STATUS_CSI: /* CSI used as system clock source */ @@ -3198,7 +3252,7 @@ uint32_t RCC_GetSystemClockFreq(void) break; default: - frequency = HSI_VALUE; + frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); break; } @@ -3267,7 +3321,7 @@ uint32_t RCC_PLL1_GetFreqSystem(void) switch (pllsource) { case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */ - pllinputfreq = HSI_VALUE; + pllinputfreq = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider()); break; case LL_RCC_PLL1SOURCE_CSI: /* CSI used as PLL1 clock source */ @@ -3287,18 +3341,11 @@ uint32_t RCC_PLL1_GetFreqSystem(void) } - - - - - - /** * @} */ - /** * @} */ diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rng.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rng.c index 3d18d5541a..b355d88fbd 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rng.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rng.c @@ -110,7 +110,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_spi.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_spi.c index c70a438adf..d0b0e04d14 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_spi.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_spi.c @@ -573,10 +573,13 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) uint32_t packetlength = 1UL; uint32_t ispcm = 0UL; uint32_t tmp; - uint32_t sourceclock; + uint32_t sourceclock = 0UL; ErrorStatus status = ERROR; + /* Prevent unused argument(s) compilation warning */ + UNUSED(sourceclock); + /* Check the I2S parameters */ assert_param(IS_I2S_ALL_INSTANCE(SPIx)); assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_tim.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_tim.c index 7059879738..e0f172302f 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_tim.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_tim.c @@ -79,8 +79,8 @@ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \ || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \ || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT)) @@ -783,6 +783,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ @@ -795,8 +797,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); @@ -850,8 +850,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -879,8 +877,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -929,8 +929,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -958,8 +956,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -1008,8 +1008,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -1037,8 +1035,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -1087,8 +1087,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1116,8 +1114,10 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); @@ -1392,7 +1392,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usart.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usart.c index 506c8f895d..859b911fc3 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usart.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usart.c @@ -375,7 +375,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USA #if defined(UART9) else if (USARTx == UART9) { - periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_UART9_CLKSOURCE); + periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART9_CLKSOURCE); } #endif /* UART9 */ #if defined(USART10) diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c index d17ce7e360..ddc27c6240 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c @@ -211,6 +211,47 @@ HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) return ret; } +/** + * @brief USB_FlushTxFifo : Flush a Tx FIFO + * @param USBx : Selected device + * @param num : FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(num); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + + #if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint @@ -962,14 +1003,14 @@ HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) /* Clear All Pending Interrupt */ USBx->ISTR = 0U; + /* Set the PullDown on the PHY */ + USBx->BCDR |= USB_BCDR_DPPD; + /* Enable Global interrupt */ USBx->CNTR |= (USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); - /* Remove Reset */ - USBx->CNTR &= ~USB_CNTR_USBRST; - return HAL_OK; } @@ -1085,7 +1126,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, wChRegVal = USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_T_MASK; - /* initialize host Channel */ + /* Initialize host Channel */ switch (ep_type) { case EP_TYPE_CTRL: @@ -1109,7 +1150,10 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, break; } - wChRegVal &= ~USB_CHEP_DEVADDR; + /* Clear device address, Endpoint number and Low Speed Endpoint fields */ + wChRegVal &= ~(USB_CHEP_DEVADDR | USB_CHEP_ADDR | USB_CHEP_LSEP); + + /* Set device address and Endpoint number associated to the channel */ wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | ((uint32_t)epnum & 0x0FU)); @@ -1122,7 +1166,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, wChRegVal |= USB_CHEP_LSEP; } - /* Set the dev_address & ep type */ + /* Update the channel register value */ USB_DRD_SET_CHEP(USBx, phy_ch_num, (wChRegVal | USB_CH_VTRX | USB_CH_VTTX)); return ret; @@ -1167,11 +1211,11 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) { (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE); - /*Set the Double buffer counter*/ + /* Set the Double buffer counter */ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len); } - else /* switch to single buffer mode */ + else /* Switch to single buffer mode */ { (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE); @@ -1179,7 +1223,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); } } - else /* isochronous */ + else /* Isochronous */ { /* Set the Double buffer counter */ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); @@ -1187,12 +1231,12 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) } #endif /* USE_USB_DOUBLE_BUFFER */ - /*Enable host channel */ - USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CHEP_RX_STRX); + /* Enable host channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_VALID); } else /* Out Channel */ { - /* Multi packet transfer*/ + /* Multi packet transfer */ if (hc->xfer_len > hc->max_packet) { len = hc->max_packet; @@ -1202,13 +1246,13 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) len = hc->xfer_len; } - /* configure and validate Tx endpoint */ + /* Configure and validate Tx endpoint */ if (hc->doublebuffer == 0U) { USB_WritePMA(USBx, hc->xfer_buff, hc->pmaadress, (uint16_t)len); USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)len); - /*SET PID SETUP */ + /* SET PID SETUP */ if ((hc->data_pid) == HC_PID_SETUP) { USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num); diff --git a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c index c9a9385c3b..0b47a3d0df 100644 --- a/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c +++ b/system/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_utils.c @@ -201,7 +201,8 @@ static ErrorStatus UTILS_PLL_IsBusy(void); */ /** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with HCLK + * as SysTick clock source. * @note When a RTOS is used, it is recommended to avoid changing the Systick * configuration by calling this function, for a delay use rather osDelay RTOS service. * @param HCLKFrequency HCLK frequency in Hz @@ -215,16 +216,59 @@ void LL_Init1msTick(uint32_t HCLKFrequency) } /** - * @brief This function provides accurate delay (in milliseconds) based + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with HCLK/8 + * as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @retval None + */ +void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency) +{ + /* Configure the SysTick to have 1ms time base with HCLK/8 as SysTick clock source */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / 8000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with LSE as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @retval None + */ +void LL_Init1msTick_LSE(void) +{ + /* Configure the SysTick to have 1ms time base with LSE as SysTick clock source */ + SysTick->LOAD = (uint32_t)((LSE_VALUE / 1000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with LSI as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @retval None + */ +void LL_Init1msTick_LSI(void) +{ + /* Configure the SysTick to have 1ms time base with LSI as SysTick clock source */ + SysTick->LOAD = (uint32_t)((LSI_VALUE / 1000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based * on SysTick counter flag * @note When a RTOS is used, it is recommended to avoid using blocking delay * and use rather osDelay service. * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which * will configure Systick to 1ms - * @param Delay specifies the delay time length, in milliseconds. + * @param Delay specifies the minimum delay time length, in milliseconds. * @retval None */ - void LL_mDelay(uint32_t Delay) { __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 7b5f1fe2d1..e4a709a78f 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -9,7 +9,7 @@ * STM32F7: 1.3.0 * STM32G0: 1.4.6 * STM32G4: 1.2.3 - * STM32H5: 1.1.0 + * STM32H5: 1.2.0 * STM32H7: 1.11.1 * STM32L0: 1.10.6 * STM32L1: 1.4.5 From 6dc7119488fa29fae0a67a28317f1e727057f7ae Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 8 Apr 2024 09:23:36 +0200 Subject: [PATCH 2/6] system(H5): update STM32H5xx CMSIS Drivers to v1.2.0 Included in STM32CubeH5 FW v1.2.0 Signed-off-by: Frederic Pillon --- .../Include/Templates/partition_stm32h523xx.h | 660 + .../Include/Templates/partition_stm32h533xx.h | 664 + .../Include/Templates/partition_stm32h562xx.h | 219 +- .../Include/Templates/partition_stm32h563xx.h | 229 +- .../Include/Templates/partition_stm32h573xx.h | 23 +- .../STM32H5xx/Include/partition_stm32h5xx.h | 23 +- .../Device/ST/STM32H5xx/Include/stm32h503xx.h | 552 +- .../Device/ST/STM32H5xx/Include/stm32h523xx.h | 20193 +++++++++++++++ .../Device/ST/STM32H5xx/Include/stm32h533xx.h | 20776 ++++++++++++++++ .../Device/ST/STM32H5xx/Include/stm32h562xx.h | 484 +- .../Device/ST/STM32H5xx/Include/stm32h563xx.h | 484 +- .../Device/ST/STM32H5xx/Include/stm32h573xx.h | 118 +- .../Device/ST/STM32H5xx/Include/stm32h5xx.h | 13 +- .../CMSIS/Device/ST/STM32H5xx/README.md | 12 +- .../Device/ST/STM32H5xx/Release_Notes.html | 23 +- .../Templates/gcc/linker/STM32H503xx_FLASH.ld | 12 +- .../Templates/gcc/linker/STM32H503xx_RAM.ld | 12 +- .../Templates/gcc/linker/STM32H523xx_FLASH.ld | 187 + .../gcc/linker/STM32H523xx_FLASH_ns.ld | 187 + .../gcc/linker/STM32H523xx_FLASH_s.ld | 195 + .../Templates/gcc/linker/STM32H523xx_RAM.ld | 187 + .../gcc/linker/STM32H523xx_RAM_ns.ld | 187 + .../Templates/gcc/linker/STM32H523xx_RAM_s.ld | 195 + .../Templates/gcc/linker/STM32H533xx_FLASH.ld | 187 + .../gcc/linker/STM32H533xx_FLASH_ns.ld | 187 + .../gcc/linker/STM32H533xx_FLASH_s.ld | 195 + .../Templates/gcc/linker/STM32H533xx_RAM.ld | 187 + .../gcc/linker/STM32H533xx_RAM_ns.ld | 187 + .../Templates/gcc/linker/STM32H533xx_RAM_s.ld | 195 + .../Templates/gcc/linker/STM32H562xx_FLASH.ld | 12 +- .../gcc/linker/STM32H562xx_FLASH_ns.ld | 12 +- .../gcc/linker/STM32H562xx_FLASH_s.ld | 12 +- .../Templates/gcc/linker/STM32H562xx_RAM.ld | 12 +- .../gcc/linker/STM32H562xx_RAM_ns.ld | 12 +- .../Templates/gcc/linker/STM32H562xx_RAM_s.ld | 12 +- .../Templates/gcc/linker/STM32H563xx_FLASH.ld | 12 +- .../gcc/linker/STM32H563xx_FLASH_ns.ld | 12 +- .../gcc/linker/STM32H563xx_FLASH_s.ld | 12 +- .../Templates/gcc/linker/STM32H563xx_RAM.ld | 12 +- .../gcc/linker/STM32H563xx_RAM_ns.ld | 12 +- .../Templates/gcc/linker/STM32H563xx_RAM_s.ld | 12 +- .../Templates/gcc/linker/STM32H573xx_FLASH.ld | 12 +- .../gcc/linker/STM32H573xx_FLASH_ns.ld | 12 +- .../gcc/linker/STM32H573xx_FLASH_s.ld | 12 +- .../Templates/gcc/linker/STM32H573xx_RAM.ld | 12 +- .../gcc/linker/STM32H573xx_RAM_ns.ld | 12 +- .../Templates/gcc/linker/STM32H573xx_RAM_s.ld | 12 +- .../Templates/gcc/startup_stm32h503xx.s | 3 +- .../Templates/gcc/startup_stm32h523xx.s | 634 + .../Templates/gcc/startup_stm32h533xx.s | 646 + .../Templates/gcc/startup_stm32h562xx.s | 3 +- .../Templates/gcc/startup_stm32h563xx.s | 3 +- .../Templates/gcc/startup_stm32h573xx.s | 3 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 54 files changed, 47345 insertions(+), 938 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h523xx.s create mode 100644 system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h533xx.s diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h new file mode 100644 index 0000000000..039a4293e8 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h @@ -0,0 +1,660 @@ +/** + ****************************************************************************** + * @file partition_stm32h523xx.h + * @author MCD Application Team + * @brief CMSIS STM32H523xx Device Header File for Initial Setup for Secure / + * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h + * Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32H523XX_H +#define PARTITION_STM32H523XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20034000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x20043FFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 131..132) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 131..132 +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32H523XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h new file mode 100644 index 0000000000..aa4972cc3a --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h @@ -0,0 +1,664 @@ +/** + ****************************************************************************** + * @file partition_stm32h533xx.h + * @author MCD Application Team + * @brief CMSIS STM32H533xx Device Header File for Initial Setup for Secure / + * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h + * Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32H533XX_H +#define PARTITION_STM32H533XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20034000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x20043FFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 131..132) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 131..132 +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32H533XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h562xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h562xx.h index e71349364e..40465c2166 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h562xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h562xx.h @@ -13,17 +13,24 @@ * - Setup Interrupt Target * ****************************************************************************** - * @attention + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. ****************************************************************************** - */ + */ #ifndef PARTITION_STM32H562XX_H #define PARTITION_STM32H562XX_H @@ -420,34 +427,33 @@ // GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state // GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state // IWDG_IRQn <0=> Secure state <1=> Non-Secure state -// ADC1_IRQn <0=> Secure state <1=> Non-Secure state -// DAC1_IRQn <0=> Secure state <1=> Non-Secure state -// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state -// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state -// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state -// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state -// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state -// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state -// TIM2_IRQn <0=> Secure state <1=> Non-Secure state -// TIM3_IRQn <0=> Secure state <1=> Non-Secure state -// TIM4_IRQn <0=> Secure state <1=> Non-Secure state -// TIM5_IRQn <0=> Secure state <1=> Non-Secure state -// TIM6_IRQn <0=> Secure state <1=> Non-Secure state -// TIM7_IRQn <0=> Secure state <1=> Non-Secure state -// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state -// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state -// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state -// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state -// SPI1_IRQn <0=> Secure state <1=> Non-Secure state -// SPI2_IRQn <0=> Secure state <1=> Non-Secure state -// SPI3_IRQn <0=> Secure state <1=> Non-Secure state -// USART1_IRQn <0=> Secure state <1=> Non-Secure state -// USART2_IRQn <0=> Secure state <1=> Non-Secure state -// USART3_IRQn <0=> Secure state <1=> Non-Secure state -// UART4_IRQn <0=> Secure state <1=> Non-Secure state -// UART5_IRQn <0=> Secure state <1=> Non-Secure state -// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 @@ -462,38 +468,38 @@ /* // Interrupts 64..95 -// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state -// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state -// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state -// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state -// ADC2_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state -// TIM15_IRQn <0=> Secure state <1=> Non-Secure state -// TIM16_IRQn <0=> Secure state <1=> Non-Secure state -// TIM17_IRQn <0=> Secure state <1=> Non-Secure state -// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state -// CRS_IRQn <0=> Secure state <1=> Non-Secure state -// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state -// FMC_IRQn <0=> Secure state <1=> Non-Secure state -// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state -// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state -// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state -// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state -// SPI4_IRQn <0=> Secure state <1=> Non-Secure state -// SPI5_IRQn <0=> Secure state <1=> Non-Secure state -// SPI6_IRQn <0=> Secure state <1=> Non-Secure state -// USART6_IRQn <0=> Secure state <1=> Non-Secure state -// USART10_IRQn <0=> Secure state <1=> Non-Secure state -// USART11_IRQn <0=> Secure state <1=> Non-Secure state -// SAI1_IRQn <0=> Secure state <1=> Non-Secure state -// SAI2_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// USART11_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 @@ -502,41 +508,60 @@ */ /* -// Initialize ITNS 3 (Interrupts 96..121) +// Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 1 /* -// Interrupts 96..121 -// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state -// UART7_IRQn <0=> Secure state <1=> Non-Secure state -// UART8_IRQn <0=> Secure state <1=> Non-Secure state -// UART9_IRQn <0=> Secure state <1=> Non-Secure state -// UART12_IRQn <0=> Secure state <1=> Non-Secure state -// FPU_IRQn <0=> Secure state <1=> Non-Secure state -// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state -// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state -// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state -// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state -// FMAC_IRQn <0=> Secure state <1=> Non-Secure state -// DTS_IRQn <0=> Secure state <1=> Non-Secure state -// RNG_IRQn <0=> Secure state <1=> Non-Secure state -// HASH_IRQn <0=> Secure state <1=> Non-Secure state -// CEC_IRQn <0=> Secure state <1=> Non-Secure state -// TIM12_IRQn <0=> Secure state <1=> Non-Secure state -// TIM13_IRQn <0=> Secure state <1=> Non-Secure state -// TIM14_IRQn <0=> Secure state <1=> Non-Secure state -// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state -// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state -// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state -// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state +// Interrupts 96..127 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// UART12_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..130) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..130 +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + /* // */ @@ -644,6 +669,10 @@ __STATIC_INLINE void TZ_SAU_Setup (void) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + } #endif /* PARTITION_STM32H562XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h563xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h563xx.h index b31a2a0b95..a550c90622 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h563xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h563xx.h @@ -13,17 +13,24 @@ * - Setup Interrupt Target * ****************************************************************************** - * @attention + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. ****************************************************************************** - */ + */ #ifndef PARTITION_STM32H563XX_H #define PARTITION_STM32H563XX_H @@ -420,34 +427,33 @@ // GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state // GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state // IWDG_IRQn <0=> Secure state <1=> Non-Secure state -// ADC1_IRQn <0=> Secure state <1=> Non-Secure state -// DAC1_IRQn <0=> Secure state <1=> Non-Secure state -// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state -// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state -// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state -// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state -// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state -// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state -// TIM2_IRQn <0=> Secure state <1=> Non-Secure state -// TIM3_IRQn <0=> Secure state <1=> Non-Secure state -// TIM4_IRQn <0=> Secure state <1=> Non-Secure state -// TIM5_IRQn <0=> Secure state <1=> Non-Secure state -// TIM6_IRQn <0=> Secure state <1=> Non-Secure state -// TIM7_IRQn <0=> Secure state <1=> Non-Secure state -// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state -// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state -// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state -// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state -// SPI1_IRQn <0=> Secure state <1=> Non-Secure state -// SPI2_IRQn <0=> Secure state <1=> Non-Secure state -// SPI3_IRQn <0=> Secure state <1=> Non-Secure state -// USART1_IRQn <0=> Secure state <1=> Non-Secure state -// USART2_IRQn <0=> Secure state <1=> Non-Secure state -// USART3_IRQn <0=> Secure state <1=> Non-Secure state -// UART4_IRQn <0=> Secure state <1=> Non-Secure state -// UART5_IRQn <0=> Secure state <1=> Non-Secure state -// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 @@ -462,38 +468,38 @@ /* // Interrupts 64..95 -// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state -// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state -// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state -// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state -// ADC2_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state -// TIM15_IRQn <0=> Secure state <1=> Non-Secure state -// TIM16_IRQn <0=> Secure state <1=> Non-Secure state -// TIM17_IRQn <0=> Secure state <1=> Non-Secure state -// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state -// CRS_IRQn <0=> Secure state <1=> Non-Secure state -// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state -// FMC_IRQn <0=> Secure state <1=> Non-Secure state -// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state -// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state -// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state -// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state -// SPI4_IRQn <0=> Secure state <1=> Non-Secure state -// SPI5_IRQn <0=> Secure state <1=> Non-Secure state -// SPI6_IRQn <0=> Secure state <1=> Non-Secure state -// USART6_IRQn <0=> Secure state <1=> Non-Secure state -// USART10_IRQn <0=> Secure state <1=> Non-Secure state -// USART11_IRQn <0=> Secure state <1=> Non-Secure state -// SAI1_IRQn <0=> Secure state <1=> Non-Secure state -// SAI2_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state -// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// USART11_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 @@ -502,46 +508,65 @@ */ /* -// Initialize ITNS 3 (Interrupts 96..126) +// Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 1 /* -// Interrupts 96..126 -// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state -// UART7_IRQn <0=> Secure state <1=> Non-Secure state -// UART8_IRQn <0=> Secure state <1=> Non-Secure state -// UART9_IRQn <0=> Secure state <1=> Non-Secure state -// UART12_IRQn <0=> Secure state <1=> Non-Secure state -// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state -// FPU_IRQn <0=> Secure state <1=> Non-Secure state -// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state -// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state -// ETH_IRQn <0=> Secure state <1=> Non-Secure state -// ETH_WKUP_IRQn <0=> Secure state <1=> Non-Secure state -// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state -// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state -// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state -// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state -// FMAC_IRQn <0=> Secure state <1=> Non-Secure state -// DTS_IRQn <0=> Secure state <1=> Non-Secure state -// RNG_IRQn <0=> Secure state <1=> Non-Secure state -// HASH_IRQn <0=> Secure state <1=> Non-Secure state -// CEC_IRQn <0=> Secure state <1=> Non-Secure state -// TIM12_IRQn <0=> Secure state <1=> Non-Secure state -// TIM13_IRQn <0=> Secure state <1=> Non-Secure state -// TIM14_IRQn <0=> Secure state <1=> Non-Secure state -// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state -// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state -// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state -// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state -// LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state +// Interrupts 96..127 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// UART12_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// ETH_IRQn <0=> Secure state <1=> Non-Secure state +// ETH_WKUP_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..130) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..130 +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + /* // */ @@ -649,6 +674,10 @@ __STATIC_INLINE void TZ_SAU_Setup (void) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + } #endif /* PARTITION_STM32H563XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h573xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h573xx.h index adadcc42a9..3aaac442d8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h573xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h573xx.h @@ -13,17 +13,24 @@ * - Setup Interrupt Target * ****************************************************************************** - * @attention + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. ****************************************************************************** - */ + */ #ifndef PARTITION_STM32H573XX_H #define PARTITION_STM32H573XX_H @@ -472,7 +479,7 @@ // TIM15_IRQn <0=> Secure state <1=> Non-Secure state // TIM16_IRQn <0=> Secure state <1=> Non-Secure state // TIM17_IRQn <0=> Secure state <1=> Non-Secure state -// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state // CRS_IRQn <0=> Secure state <1=> Non-Secure state // UCPD1_IRQn <0=> Secure state <1=> Non-Secure state // FMC_IRQn <0=> Secure state <1=> Non-Secure state diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h index 859bd89355..7a4d10a750 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h @@ -12,15 +12,22 @@ * and interrupt secure and non-secure assignment. * ****************************************************************************** - * @attention + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. ****************************************************************************** */ @@ -49,6 +56,10 @@ #include "partition_stm32h563xx.h" #elif defined(STM32H562xx) #include "partition_stm32h562xx.h" +#elif defined(STM32H533xx) + #include "partition_stm32h533xx.h" +#elif defined(STM32H523xx) + #include "partition_stm32h523xx.h" #else #error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)" #endif diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h index a8e7560bea..5ec4cd1093 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h @@ -1,4 +1,4 @@ -/** +/** ****************************************************************************** * @file stm32h503xx.h * @author MCD Application Team @@ -429,22 +429,22 @@ typedef struct __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ - __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x14 */ __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x1C */ __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ - __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x34 */ __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ - uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ + uint32_t RESERVED4[9]; /*!< Reserved 4, 0x3C-- 0x5C */ __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ - uint32_t RESERVED3[4]; /*!< Reserved 3, 0x70 -- 0x7C */ + uint32_t RESERVED5[4]; /*!< Reserved 5, 0x70 -- 0x7C */ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ - uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ + uint32_t RESERVED6[2]; /*!< Reserved 6, 0x88 -- 0x8C */ __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ } EXTI_TypeDef; @@ -537,8 +537,6 @@ typedef struct uint32_t RESERVED3[17]; /*!< Reserved3, Address offset: 0x2C-0x6C */ __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ - __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ - __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ } GTZC_TZSC_TypeDef; typedef struct @@ -591,7 +589,8 @@ typedef struct __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ - uint32_t RESERVED0[221];/*!< Reserved, Address offset: 0x68 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ } TIM_TypeDef; @@ -769,6 +768,7 @@ typedef struct __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ } RCC_TypeDef; + /* * @brief RTC Specific device feature definitions */ @@ -1299,9 +1299,6 @@ typedef struct #define FLASH_SYSTEM_SIZE (0x8000U) /*!< 32 Kbytes system Flash */ -/*!< USB PMA SIZE */ -#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ - /*!< Non Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF8FE6CUL) @@ -4286,104 +4283,6 @@ typedef struct #define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ #define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */ -/******************* Bit definition for EXTI_SECENR1 register ******************/ -#define EXTI_SECENR1_SEC0_Pos (0U) -#define EXTI_SECENR1_SEC0_Msk (0x1UL << EXTI_SECENR1_SEC0_Pos) /*!< 0x00000001 */ -#define EXTI_SECENR1_SEC0 EXTI_SECENR1_SEC0_Msk /*!< Security enable on line 0 */ -#define EXTI_SECENR1_SEC1_Pos (1U) -#define EXTI_SECENR1_SEC1_Msk (0x1UL << EXTI_SECENR1_SEC1_Pos) /*!< 0x00000002 */ -#define EXTI_SECENR1_SEC1 EXTI_SECENR1_SEC1_Msk /*!< Security enable on line 1 */ -#define EXTI_SECENR1_SEC2_Pos (2U) -#define EXTI_SECENR1_SEC2_Msk (0x1UL << EXTI_SECENR1_SEC2_Pos) /*!< 0x00000004 */ -#define EXTI_SECENR1_SEC2 EXTI_SECENR1_SEC2_Msk /*!< Security enable on line 2 */ -#define EXTI_SECENR1_SEC3_Pos (3U) -#define EXTI_SECENR1_SEC3_Msk (0x1UL << EXTI_SECENR1_SEC3_Pos) /*!< 0x00000008 */ -#define EXTI_SECENR1_SEC3 EXTI_SECENR1_SEC3_Msk /*!< Security enable on line 3 */ -#define EXTI_SECENR1_SEC4_Pos (4U) -#define EXTI_SECENR1_SEC4_Msk (0x1UL << EXTI_SECENR1_SEC4_Pos) /*!< 0x00000010 */ -#define EXTI_SECENR1_SEC4 EXTI_SECENR1_SEC4_Msk /*!< Security enable on line 4 */ -#define EXTI_SECENR1_SEC5_Pos (5U) -#define EXTI_SECENR1_SEC5_Msk (0x1UL << EXTI_SECENR1_SEC5_Pos) /*!< 0x00000020 */ -#define EXTI_SECENR1_SEC5 EXTI_SECENR1_SEC5_Msk /*!< Security enable on line 5 */ -#define EXTI_SECENR1_SEC6_Pos (6U) -#define EXTI_SECENR1_SEC6_Msk (0x1UL << EXTI_SECENR1_SEC6_Pos) /*!< 0x00000040 */ -#define EXTI_SECENR1_SEC6 EXTI_SECENR1_SEC6_Msk /*!< Security enable on line 6 */ -#define EXTI_SECENR1_SEC7_Pos (7U) -#define EXTI_SECENR1_SEC7_Msk (0x1UL << EXTI_SECENR1_SEC7_Pos) /*!< 0x00000080 */ -#define EXTI_SECENR1_SEC7 EXTI_SECENR1_SEC7_Msk /*!< Security enable on line 7 */ -#define EXTI_SECENR1_SEC8_Pos (8U) -#define EXTI_SECENR1_SEC8_Msk (0x1UL << EXTI_SECENR1_SEC8_Pos) /*!< 0x00000100 */ -#define EXTI_SECENR1_SEC8 EXTI_SECENR1_SEC8_Msk /*!< Security enable on line 8 */ -#define EXTI_SECENR1_SEC9_Pos (9U) -#define EXTI_SECENR1_SEC9_Msk (0x1UL << EXTI_SECENR1_SEC9_Pos) /*!< 0x00000200 */ -#define EXTI_SECENR1_SEC9 EXTI_SECENR1_SEC9_Msk /*!< Security enable on line 9 */ -#define EXTI_SECENR1_SEC10_Pos (10U) -#define EXTI_SECENR1_SEC10_Msk (0x1UL << EXTI_SECENR1_SEC10_Pos) /*!< 0x00000400 */ -#define EXTI_SECENR1_SEC10 EXTI_SECENR1_SEC10_Msk /*!< Security enable on line 10 */ -#define EXTI_SECENR1_SEC11_Pos (11U) -#define EXTI_SECENR1_SEC11_Msk (0x1UL << EXTI_SECENR1_SEC11_Pos) /*!< 0x00000800 */ -#define EXTI_SECENR1_SEC11 EXTI_SECENR1_SEC11_Msk /*!< Security enable on line 11 */ -#define EXTI_SECENR1_SEC12_Pos (12U) -#define EXTI_SECENR1_SEC12_Msk (0x1UL << EXTI_SECENR1_SEC12_Pos) /*!< 0x00001000 */ -#define EXTI_SECENR1_SEC12 EXTI_SECENR1_SEC12_Msk /*!< Security enable on line 12 */ -#define EXTI_SECENR1_SEC13_Pos (13U) -#define EXTI_SECENR1_SEC13_Msk (0x1UL << EXTI_SECENR1_SEC13_Pos) /*!< 0x00002000 */ -#define EXTI_SECENR1_SEC13 EXTI_SECENR1_SEC13_Msk /*!< Security enable on line 13 */ -#define EXTI_SECENR1_SEC14_Pos (14U) -#define EXTI_SECENR1_SEC14_Msk (0x1UL << EXTI_SECENR1_SEC14_Pos) /*!< 0x00004000 */ -#define EXTI_SECENR1_SEC14 EXTI_SECENR1_SEC14_Msk /*!< Security enable on line 14 */ -#define EXTI_SECENR1_SEC15_Pos (15U) -#define EXTI_SECENR1_SEC15_Msk (0x1UL << EXTI_SECENR1_SEC15_Pos) /*!< 0x00008000 */ -#define EXTI_SECENR1_SEC15 EXTI_SECENR1_SEC15_Msk /*!< Security enable on line 15 */ -#define EXTI_SECENR1_SEC16_Pos (16U) -#define EXTI_SECENR1_SEC16_Msk (0x1UL << EXTI_SECENR1_SEC16_Pos) /*!< 0x00010000 */ -#define EXTI_SECENR1_SEC16 EXTI_SECENR1_SEC16_Msk /*!< Security enable on line 16 */ -#define EXTI_SECENR1_SEC17_Pos (17U) -#define EXTI_SECENR1_SEC17_Msk (0x1UL << EXTI_SECENR1_SEC17_Pos) /*!< 0x00020000 */ -#define EXTI_SECENR1_SEC17 EXTI_SECENR1_SEC17_Msk /*!< Security enable on line 17 */ -#define EXTI_SECENR1_SEC18_Pos (18U) -#define EXTI_SECENR1_SEC18_Msk (0x1UL << EXTI_SECENR1_SEC18_Pos) /*!< 0x00040000 */ -#define EXTI_SECENR1_SEC18 EXTI_SECENR1_SEC18_Msk /*!< Security enable on line 18 */ -#define EXTI_SECENR1_SEC19_Pos (19U) -#define EXTI_SECENR1_SEC19_Msk (0x1UL << EXTI_SECENR1_SEC19_Pos) /*!< 0x00080000 */ -#define EXTI_SECENR1_SEC19 EXTI_SECENR1_SEC19_Msk /*!< Security enable on line 19 */ -#define EXTI_SECENR1_SEC20_Pos (20U) -#define EXTI_SECENR1_SEC20_Msk (0x1UL << EXTI_SECENR1_SEC20_Pos) /*!< 0x00100000 */ -#define EXTI_SECENR1_SEC20 EXTI_SECENR1_SEC20_Msk /*!< Security enable on line 20 */ -#define EXTI_SECENR1_SEC21_Pos (21U) -#define EXTI_SECENR1_SEC21_Msk (0x1UL << EXTI_SECENR1_SEC21_Pos) /*!< 0x00200000 */ -#define EXTI_SECENR1_SEC21 EXTI_SECENR1_SEC21_Msk /*!< Security enable on line 21 */ -#define EXTI_SECENR1_SEC22_Pos (22U) -#define EXTI_SECENR1_SEC22_Msk (0x1UL << EXTI_SECENR1_SEC22_Pos) /*!< 0x00400000 */ -#define EXTI_SECENR1_SEC22 EXTI_SECENR1_SEC22_Msk /*!< Security enable on line 22 */ -#define EXTI_SECENR1_SEC23_Pos (23U) -#define EXTI_SECENR1_SEC23_Msk (0x1UL << EXTI_SECENR1_SEC23_Pos) /*!< 0x00800000 */ -#define EXTI_SECENR1_SEC23 EXTI_SECENR1_SEC23_Msk /*!< Security enable on line 23 */ -#define EXTI_SECENR1_SEC24_Pos (24U) -#define EXTI_SECENR1_SEC24_Msk (0x1UL << EXTI_SECENR1_SEC24_Pos) /*!< 0x01000000 */ -#define EXTI_SECENR1_SEC24 EXTI_SECENR1_SEC24_Msk /*!< Security enable on line 24 */ -#define EXTI_SECENR1_SEC25_Pos (25U) -#define EXTI_SECENR1_SEC25_Msk (0x1UL << EXTI_SECENR1_SEC25_Pos) /*!< 0x02000000 */ -#define EXTI_SECENR1_SEC25 EXTI_SECENR1_SEC25_Msk /*!< Security enable on line 25 */ -#define EXTI_SECENR1_SEC26_Pos (26U) -#define EXTI_SECENR1_SEC26_Msk (0x1UL << EXTI_SECENR1_SEC26_Pos) /*!< 0x04000000 */ -#define EXTI_SECENR1_SEC26 EXTI_SECENR1_SEC26_Msk /*!< Security enable on line 26 */ -#define EXTI_SECENR1_SEC27_Pos (27U) -#define EXTI_SECENR1_SEC27_Msk (0x1UL << EXTI_SECENR1_SEC27_Pos) /*!< 0x08000000 */ -#define EXTI_SECENR1_SEC27 EXTI_SECENR1_SEC27_Msk /*!< Security enable on line 27 */ -#define EXTI_SECENR1_SEC28_Pos (28U) -#define EXTI_SECENR1_SEC28_Msk (0x1UL << EXTI_SECENR1_SEC28_Pos) /*!< 0x10000000 */ -#define EXTI_SECENR1_SEC28 EXTI_SECENR1_SEC28_Msk /*!< Security enable on line 28 */ -#define EXTI_SECENR1_SEC29_Pos (29U) -#define EXTI_SECENR1_SEC29_Msk (0x1UL << EXTI_SECENR1_SEC29_Pos) /*!< 0x20000000 */ -#define EXTI_SECENR1_SEC29 EXTI_SECENR1_SEC29_Msk /*!< Security enable on line 29 */ -#define EXTI_SECENR1_SEC30_Pos (30U) -#define EXTI_SECENR1_SEC30_Msk (0x1UL << EXTI_SECENR1_SEC30_Pos) /*!< 0x40000000 */ -#define EXTI_SECENR1_SEC30 EXTI_SECENR1_SEC30_Msk /*!< Security enable on line 30 */ -#define EXTI_SECENR1_SEC31_Pos (31U) -#define EXTI_SECENR1_SEC31_Msk (0x1UL << EXTI_SECENR1_SEC31_Pos) /*!< 0x80000000 */ -#define EXTI_SECENR1_SEC31 EXTI_SECENR1_SEC31_Msk /*!< Security enable on line 31 */ - /******************* Bit definition for EXTI_PRIVENR1 register ******************/ #define EXTI_PRIVENR1_PRIV0_Pos (0U) @@ -4440,24 +4339,15 @@ typedef struct #define EXTI_PRIVENR1_PRIV17_Pos (17U) #define EXTI_PRIVENR1_PRIV17_Msk (0x1UL << EXTI_PRIVENR1_PRIV17_Pos) /*!< 0x00020000 */ #define EXTI_PRIVENR1_PRIV17 EXTI_PRIVENR1_PRIV17_Msk /*!< Privilege enable on line 17 */ -#define EXTI_PRIVENR1_PRIV18_Pos (18U) -#define EXTI_PRIVENR1_PRIV18_Msk (0x1UL << EXTI_PRIVENR1_PRIV18_Pos) /*!< 0x00040000 */ -#define EXTI_PRIVENR1_PRIV18 EXTI_PRIVENR1_PRIV18_Msk /*!< Privilege enable on line 18 */ #define EXTI_PRIVENR1_PRIV19_Pos (19U) #define EXTI_PRIVENR1_PRIV19_Msk (0x1UL << EXTI_PRIVENR1_PRIV19_Pos) /*!< 0x00080000 */ #define EXTI_PRIVENR1_PRIV19 EXTI_PRIVENR1_PRIV19_Msk /*!< Privilege enable on line 19 */ -#define EXTI_PRIVENR1_PRIV20_Pos (20U) -#define EXTI_PRIVENR1_PRIV20_Msk (0x1UL << EXTI_PRIVENR1_PRIV20_Pos) /*!< 0x00100000 */ -#define EXTI_PRIVENR1_PRIV20 EXTI_PRIVENR1_PRIV20_Msk /*!< Privilege enable on line 20 */ #define EXTI_PRIVENR1_PRIV21_Pos (21U) #define EXTI_PRIVENR1_PRIV21_Msk (0x1UL << EXTI_PRIVENR1_PRIV21_Pos) /*!< 0x00200000 */ #define EXTI_PRIVENR1_PRIV21 EXTI_PRIVENR1_PRIV21_Msk /*!< Privilege enable on line 21 */ #define EXTI_PRIVENR1_PRIV22_Pos (22U) #define EXTI_PRIVENR1_PRIV22_Msk (0x1UL << EXTI_PRIVENR1_PRIV22_Pos) /*!< 0x00400000 */ #define EXTI_PRIVENR1_PRIV22 EXTI_PRIVENR1_PRIV22_Msk /*!< Privilege enable on line 22 */ -#define EXTI_PRIVENR1_PRIV23_Pos (23U) -#define EXTI_PRIVENR1_PRIV23_Msk (0x1UL << EXTI_PRIVENR1_PRIV23_Pos) /*!< 0x00800000 */ -#define EXTI_PRIVENR1_PRIV23 EXTI_PRIVENR1_PRIV23_Msk /*!< Privilege enable on line 23 */ #define EXTI_PRIVENR1_PRIV24_Pos (24U) #define EXTI_PRIVENR1_PRIV24_Msk (0x1UL << EXTI_PRIVENR1_PRIV24_Pos) /*!< 0x01000000 */ #define EXTI_PRIVENR1_PRIV24 EXTI_PRIVENR1_PRIV24_Msk /*!< Privilege enable on line 24 */ @@ -4476,20 +4366,11 @@ typedef struct #define EXTI_PRIVENR1_PRIV29_Pos (29U) #define EXTI_PRIVENR1_PRIV29_Msk (0x1UL << EXTI_PRIVENR1_PRIV29_Pos) /*!< 0x20000000 */ #define EXTI_PRIVENR1_PRIV29 EXTI_PRIVENR1_PRIV29_Msk /*!< Privilege enable on line 29 */ -#define EXTI_PRIVENR1_PRIV30_Pos (30U) -#define EXTI_PRIVENR1_PRIV30_Msk (0x1UL << EXTI_PRIVENR1_PRIV30_Pos) /*!< 0x40000000 */ -#define EXTI_PRIVENR1_PRIV30 EXTI_PRIVENR1_PRIV30_Msk /*!< Privilege enable on line 30 */ -#define EXTI_PRIVENR1_PRIV31_Pos (31U) -#define EXTI_PRIVENR1_PRIV31_Msk (0x1UL << EXTI_PRIVENR1_PRIV31_Pos) /*!< 0x80000000 */ -#define EXTI_PRIVENR1_PRIV31 EXTI_PRIVENR1_PRIV31_Msk /*!< Privilege enable on line 31 */ /****************** Bit definition for EXTI_RTSR2 register *******************/ -#define EXTI_RTSR2_TR_Pos (14U) -#define EXTI_RTSR2_TR_Msk (0x244UL << EXTI_RTSR2_TR_Pos) /*!< 0x00244000 */ +#define EXTI_RTSR2_TR_Pos (16U) +#define EXTI_RTSR2_TR_Msk (0x24UL << EXTI_RTSR2_TR_Pos) /*!< 0x00240000 */ #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */ -#define EXTI_RTSR2_TR46_Pos (14U) -#define EXTI_RTSR2_TR46_Msk (0x1UL << EXTI_RTSR2_TR46_Pos) /*!< 0x00004000 */ -#define EXTI_RTSR2_TR46 EXTI_RTSR2_TR46_Msk /*!< Rising trigger event configuration bit of line 46 */ #define EXTI_RTSR2_TR50_Pos (18U) #define EXTI_RTSR2_TR50_Msk (0x1UL << EXTI_RTSR2_TR50_Pos) /*!< 0x00040000 */ #define EXTI_RTSR2_TR50 EXTI_RTSR2_TR50_Msk /*!< Rising trigger event configuration bit of line 50 */ @@ -4498,12 +4379,9 @@ typedef struct #define EXTI_RTSR2_TR53 EXTI_RTSR2_TR53_Msk /*!< Rising trigger event configuration bit of line 53 */ /****************** Bit definition for EXTI_FTSR2 register *******************/ -#define EXTI_FTSR2_TR_Pos (14U) -#define EXTI_FTSR2_TR_Msk (0x244 << EXTI_FTSR2_TR_Pos) /*!< 0x00244000 */ +#define EXTI_FTSR2_TR_Pos (16U) +#define EXTI_FTSR2_TR_Msk (0x24 << EXTI_FTSR2_TR_Pos) /*!< 0x00240000 */ #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */ -#define EXTI_FTSR2_TR46_Pos (14U) -#define EXTI_FTSR2_TR46_Msk (0x1UL << EXTI_FTSR2_TR46_Pos) /*!< 0x00004000 */ -#define EXTI_FTSR2_TR46 EXTI_FTSR2_TR46_Msk /*!< Falling trigger event configuration bit of line 46 */ #define EXTI_FTSR2_TR50_Pos (18U) #define EXTI_FTSR2_TR50_Msk (0x1UL << EXTI_FTSR2_TR50_Pos) /*!< 0x00040000 */ #define EXTI_FTSR2_TR50 EXTI_FTSR2_TR50_Msk /*!< Falling trigger event configuration bit of line 50 */ @@ -4512,9 +4390,6 @@ typedef struct #define EXTI_FTSR2_TR53 EXTI_FTSR2_TR53_Msk /*!< Falling trigger event configuration bit of line 53 */ /****************** Bit definition for EXTI_SWIER2 register ******************/ -#define EXTI_SWIER2_SWIER46_Pos (14U) -#define EXTI_SWIER2_SWIER46_Msk (0x1UL << EXTI_SWIER2_SWIER46_Pos) /*!< 0x00004000 */ -#define EXTI_SWIER2_SWIER46 EXTI_SWIER2_SWIER46_Msk /*!< Software Interrupt on line 46 */ #define EXTI_SWIER2_SWIER50_Pos (18U) #define EXTI_SWIER2_SWIER50_Msk (0x1UL << EXTI_SWIER2_SWIER50_Pos) /*!< 0x00040000 */ #define EXTI_SWIER2_SWIER50 EXTI_SWIER2_SWIER50_Msk /*!< Software Interrupt on line 50 */ @@ -4523,12 +4398,9 @@ typedef struct #define EXTI_SWIER2_SWIER53 EXTI_SWIER2_SWIER53_Msk /*!< Software Interrupt on line 53 */ /****************** Bit definition for EXTI_RPR2 register *******************/ -#define EXTI_RPR2_RPIF_Pos (14U) -#define EXTI_RPR2_RPIF_Msk (0x244UL << EXTI_RPR2_RPIF_Pos) /*!< 0x00244000 */ +#define EXTI_RPR2_RPIF_Pos (16U) +#define EXTI_RPR2_RPIF_Msk (0x24UL << EXTI_RPR2_RPIF_Pos) /*!< 0x00240000 */ #define EXTI_RPR2_RPIF EXTI_RPR2_RPIF_Msk /*!< Rising pending edge configuration bits */ -#define EXTI_RPR2_RPIF46_Pos (14U) -#define EXTI_RPR2_RPIF46_Msk (0x1UL << EXTI_RPR2_RPIF46_Pos) /*!< 0x00004000 */ -#define EXTI_RPR2_RPIF46 EXTI_RPR2_RPIF46_Msk /*!< Rising pending edge configuration bit of line 46 */ #define EXTI_RPR2_RPIF50_Pos (18U) #define EXTI_RPR2_RPIF50_Msk (0x1UL << EXTI_RPR2_RPIF50_Pos) /*!< 0x00040000 */ #define EXTI_RPR2_RPIF50 EXTI_RPR2_RPIF50_Msk /*!< Rising pending edge configuration bit of line 50 */ @@ -4537,12 +4409,9 @@ typedef struct #define EXTI_RPR2_RPIF53 EXTI_RPR2_RPIF53_Msk /*!< Rising pending edge configuration bit of line 53 */ /****************** Bit definition for EXTI_FPR2 register *******************/ -#define EXTI_FPR2_FPIF_Pos (14U) -#define EXTI_FPR2_FPIF_Msk (0x244UL << EXTI_FPR2_FPIF_Pos) /*!< 0x00244000 */ +#define EXTI_FPR2_FPIF_Pos (16U) +#define EXTI_FPR2_FPIF_Msk (0x24UL << EXTI_FPR2_FPIF_Pos) /*!< 0x00240000 */ #define EXTI_FPR2_FPIF EXTI_FPR2_FPIF_Msk /*!< Rising falling edge configuration bits */ -#define EXTI_FPR2_FPIF46_Pos (14U) -#define EXTI_FPR2_FPIF46_Msk (0x1UL << EXTI_FPR2_FPIF46_Pos) /*!< 0x00004000 */ -#define EXTI_FPR2_FPIF46 EXTI_FPR2_FPIF46_Msk /*!< Rising falling edge configuration bit of line 46 */ #define EXTI_FPR2_FPIF50_Pos (18U) #define EXTI_FPR2_FPIF50_Msk (0x1UL << EXTI_FPR2_FPIF50_Pos) /*!< 0x00040000 */ #define EXTI_FPR2_FPIF50 EXTI_FPR2_FPIF50_Msk /*!< Rising falling edge configuration bit of line 50 */ @@ -4550,102 +4419,7 @@ typedef struct #define EXTI_FPR2_FPIF53_Msk (0x1UL << EXTI_FPR2_FPIF53_Pos) /*!< 0x00200000 */ #define EXTI_FPR2_FPIF53 EXTI_FPR2_FPIF53_Msk /*!< Rising falling edge configuration bit of line 53 */ -/******************* Bit definition for EXTI_SECENR2 register ******************/ -#define EXTI_SECENR2_SEC32_Pos (0U) -#define EXTI_SECENR2_SEC32_Msk (0x1UL << EXTI_SECENR2_SEC32_Pos) /*!< 0x00000001 */ -#define EXTI_SECENR2_SEC32 EXTI_SECENR2_SEC32_Msk /*!< Security enable on line 32 */ -#define EXTI_SECENR2_SEC33_Pos (1U) -#define EXTI_SECENR2_SEC33_Msk (0x1UL << EXTI_SECENR2_SEC33_Pos) /*!< 0x00000002 */ -#define EXTI_SECENR2_SEC33 EXTI_SECENR2_SEC33_Msk /*!< Security enable on line 33 */ -#define EXTI_SECENR2_SEC34_Pos (2U) -#define EXTI_SECENR2_SEC34_Msk (0x1UL << EXTI_SECENR2_SEC34_Pos) /*!< 0x00000004 */ -#define EXTI_SECENR2_SEC34 EXTI_SECENR2_SEC34_Msk /*!< Security enable on line 2 */ -#define EXTI_SECENR2_SEC35_Pos (3U) -#define EXTI_SECENR2_SEC35_Msk (0x1UL << EXTI_SECENR2_SEC35_Pos) /*!< 0x00000008 */ -#define EXTI_SECENR2_SEC35 EXTI_SECENR2_SEC35_Msk /*!< Security enable on line 3 */ -#define EXTI_SECENR2_SEC36_Pos (4U) -#define EXTI_SECENR2_SEC36_Msk (0x1UL << EXTI_SECENR2_SEC36_Pos) /*!< 0x00000010 */ -#define EXTI_SECENR2_SEC36 EXTI_SECENR2_SEC36_Msk /*!< Security enable on line 4 */ -#define EXTI_SECENR2_SEC37_Pos (5U) -#define EXTI_SECENR2_SEC37_Msk (0x1UL << EXTI_SECENR2_SEC37_Pos) /*!< 0x00000020 */ -#define EXTI_SECENR2_SEC37 EXTI_SECENR2_SEC37_Msk /*!< Security enable on line 5 */ -#define EXTI_SECENR2_SEC38_Pos (6U) -#define EXTI_SECENR2_SEC38_Msk (0x1UL << EXTI_SECENR2_SEC38_Pos) /*!< 0x00000040 */ -#define EXTI_SECENR2_SEC38 EXTI_SECENR2_SEC38_Msk /*!< Security enable on line 6 */ -#define EXTI_SECENR2_SEC39_Pos (7U) -#define EXTI_SECENR2_SEC39_Msk (0x1UL << EXTI_SECENR2_SEC39_Pos) /*!< 0x00000080 */ -#define EXTI_SECENR2_SEC39 EXTI_SECENR2_SEC39_Msk /*!< Security enable on line 7 */ -#define EXTI_SECENR2_SEC40_Pos (8U) -#define EXTI_SECENR2_SEC40_Msk (0x1UL << EXTI_SECENR2_SEC40_Pos) /*!< 0x00000100 */ -#define EXTI_SECENR2_SEC40 EXTI_SECENR2_SEC40_Msk /*!< Security enable on line 8 */ -#define EXTI_SECENR2_SEC41_Pos (9U) -#define EXTI_SECENR2_SEC41_Msk (0x1UL << EXTI_SECENR2_SEC41_Pos) /*!< 0x00000200 */ -#define EXTI_SECENR2_SEC41 EXTI_SECENR2_SEC41_Msk /*!< Security enable on line 9 */ -#define EXTI_SECENR2_SEC42_Pos (10U) -#define EXTI_SECENR2_SEC42_Msk (0x1UL << EXTI_SECENR2_SEC42_Pos) /*!< 0x00000400 */ -#define EXTI_SECENR2_SEC42 EXTI_SECENR2_SEC42_Msk /*!< Security enable on line 10 */ -#define EXTI_SECENR2_SEC43_Pos (11U) -#define EXTI_SECENR2_SEC43_Msk (0x1UL << EXTI_SECENR2_SEC43_Pos) /*!< 0x00000800 */ -#define EXTI_SECENR2_SEC43 EXTI_SECENR2_SEC43_Msk /*!< Security enable on line 11 */ -#define EXTI_SECENR2_SEC44_Pos (12U) -#define EXTI_SECENR2_SEC44_Msk (0x1UL << EXTI_SECENR2_SEC44_Pos) /*!< 0x00001000 */ -#define EXTI_SECENR2_SEC44 EXTI_SECENR2_SEC44_Msk /*!< Security enable on line 12 */ -#define EXTI_SECENR2_SEC45_Pos (13U) -#define EXTI_SECENR2_SEC45_Msk (0x1UL << EXTI_SECENR2_SEC45_Pos) /*!< 0x00002000 */ -#define EXTI_SECENR2_SEC45 EXTI_SECENR2_SEC45_Msk /*!< Security enable on line 13 */ -#define EXTI_SECENR2_SEC46_Pos (14U) -#define EXTI_SECENR2_SEC46_Msk (0x1UL << EXTI_SECENR2_SEC46_Pos) /*!< 0x00004000 */ -#define EXTI_SECENR2_SEC46 EXTI_SECENR2_SEC46_Msk /*!< Security enable on line 14 */ -#define EXTI_SECENR2_SEC47_Pos (15U) -#define EXTI_SECENR2_SEC47_Msk (0x1UL << EXTI_SECENR2_SEC47_Pos) /*!< 0x00008000 */ -#define EXTI_SECENR2_SEC47 EXTI_SECENR2_SEC47_Msk /*!< Security enable on line 15 */ -#define EXTI_SECENR2_SEC48_Pos (16U) -#define EXTI_SECENR2_SEC48_Msk (0x1UL << EXTI_SECENR2_SEC48_Pos) /*!< 0x00010000 */ -#define EXTI_SECENR2_SEC48 EXTI_SECENR2_SEC48_Msk /*!< Security enable on line 16 */ -#define EXTI_SECENR2_SEC49_Pos (17U) -#define EXTI_SECENR2_SEC49_Msk (0x1UL << EXTI_SECENR2_SEC49_Pos) /*!< 0x00020000 */ -#define EXTI_SECENR2_SEC49 EXTI_SECENR2_SEC49_Msk /*!< Security enable on line 17 */ -#define EXTI_SECENR2_SEC50_Pos (18U) -#define EXTI_SECENR2_SEC50_Msk (0x1UL << EXTI_SECENR2_SEC50_Pos) /*!< 0x00040000 */ -#define EXTI_SECENR2_SEC50 EXTI_SECENR2_SEC50_Msk /*!< Security enable on line 18 */ -#define EXTI_SECENR2_SEC51_Pos (19U) -#define EXTI_SECENR2_SEC51_Msk (0x1UL << EXTI_SECENR2_SEC51_Pos) /*!< 0x00080000 */ -#define EXTI_SECENR2_SEC51 EXTI_SECENR2_SEC51_Msk /*!< Security enable on line 19 */ -#define EXTI_SECENR2_SEC52_Pos (20U) -#define EXTI_SECENR2_SEC52_Msk (0x1UL << EXTI_SECENR2_SEC52_Pos) /*!< 0x00100000 */ -#define EXTI_SECENR2_SEC52 EXTI_SECENR2_SEC52_Msk /*!< Security enable on line 20 */ -#define EXTI_SECENR2_SEC53_Pos (21U) -#define EXTI_SECENR2_SEC53_Msk (0x1UL << EXTI_SECENR2_SEC53_Pos) /*!< 0x00200000 */ -#define EXTI_SECENR2_SEC53 EXTI_SECENR2_SEC53_Msk /*!< Security enable on line 21 */ -#define EXTI_SECENR2_SEC54_Pos (22U) -#define EXTI_SECENR2_SEC54_Msk (0x1UL << EXTI_SECENR2_SEC54_Pos) /*!< 0x00400000 */ -#define EXTI_SECENR2_SEC54 EXTI_SECENR2_SEC54_Msk /*!< Security enable on line 22 */ -#define EXTI_SECENR2_SEC55_Pos (23U) -#define EXTI_SECENR2_SEC55_Msk (0x1UL << EXTI_SECENR2_SEC55_Pos) /*!< 0x00800000 */ -#define EXTI_SECENR2_SEC55 EXTI_SECENR2_SEC55_Msk /*!< Security enable on line 23 */ -#define EXTI_SECENR2_SEC56_Pos (24U) -#define EXTI_SECENR2_SEC56_Msk (0x1UL << EXTI_SECENR2_SEC56_Pos) /*!< 0x01000000 */ -#define EXTI_SECENR2_SEC56 EXTI_SECENR2_SEC56_Msk /*!< Security enable on line 24 */ -#define EXTI_SECENR2_SEC57_Pos (25U) -#define EXTI_SECENR2_SEC57_Msk (0x1UL << EXTI_SECENR2_SEC57_Pos) /*!< 0x02000000 */ -#define EXTI_SECENR2_SEC57 EXTI_SECENR2_SEC57_Msk /*!< Security enable on line 25 */ - /******************* Bit definition for EXTI_PRIVENR2 register ******************/ -#define EXTI_PRIVENR2_PRIV32_Pos (0U) -#define EXTI_PRIVENR2_PRIV32_Msk (0x1UL << EXTI_PRIVENR2_PRIV32_Pos) /*!< 0x00000001 */ -#define EXTI_PRIVENR2_PRIV32 EXTI_PRIVENR2_PRIV32_Msk /*!< Security enable on line 32 */ -#define EXTI_PRIVENR2_PRIV33_Pos (1U) -#define EXTI_PRIVENR2_PRIV33_Msk (0x1UL << EXTI_PRIVENR2_PRIV33_Pos) /*!< 0x00000002 */ -#define EXTI_PRIVENR2_PRIV33 EXTI_PRIVENR2_PRIV33_Msk /*!< Security enable on line 33 */ -#define EXTI_PRIVENR2_PRIV34_Pos (2U) -#define EXTI_PRIVENR2_PRIV34_Msk (0x1UL << EXTI_PRIVENR2_PRIV34_Pos) /*!< 0x00000004 */ -#define EXTI_PRIVENR2_PRIV34 EXTI_PRIVENR2_PRIV34_Msk /*!< Security enable on line 2 */ -#define EXTI_PRIVENR2_PRIV35_Pos (3U) -#define EXTI_PRIVENR2_PRIV35_Msk (0x1UL << EXTI_PRIVENR2_PRIV35_Pos) /*!< 0x00000008 */ -#define EXTI_PRIVENR2_PRIV35 EXTI_PRIVENR2_PRIV35_Msk /*!< Security enable on line 3 */ -#define EXTI_PRIVENR2_PRIV36_Pos (4U) -#define EXTI_PRIVENR2_PRIV36_Msk (0x1UL << EXTI_PRIVENR2_PRIV36_Pos) /*!< 0x00000010 */ -#define EXTI_PRIVENR2_PRIV36 EXTI_PRIVENR2_PRIV36_Msk /*!< Security enable on line 4 */ #define EXTI_PRIVENR2_PRIV37_Pos (5U) #define EXTI_PRIVENR2_PRIV37_Msk (0x1UL << EXTI_PRIVENR2_PRIV37_Pos) /*!< 0x00000020 */ #define EXTI_PRIVENR2_PRIV37 EXTI_PRIVENR2_PRIV37_Msk /*!< Security enable on line 5 */ @@ -4664,51 +4438,18 @@ typedef struct #define EXTI_PRIVENR2_PRIV42_Pos (10U) #define EXTI_PRIVENR2_PRIV42_Msk (0x1UL << EXTI_PRIVENR2_PRIV42_Pos) /*!< 0x00000400 */ #define EXTI_PRIVENR2_PRIV42 EXTI_PRIVENR2_PRIV42_Msk /*!< Security enable on line 10 */ -#define EXTI_PRIVENR2_PRIV43_Pos (11U) -#define EXTI_PRIVENR2_PRIV43_Msk (0x1UL << EXTI_PRIVENR2_PRIV43_Pos) /*!< 0x00000800 */ -#define EXTI_PRIVENR2_PRIV43 EXTI_PRIVENR2_PRIV43_Msk /*!< Security enable on line 11 */ -#define EXTI_PRIVENR2_PRIV44_Pos (12U) -#define EXTI_PRIVENR2_PRIV44_Msk (0x1UL << EXTI_PRIVENR2_PRIV44_Pos) /*!< 0x00001000 */ -#define EXTI_PRIVENR2_PRIV44 EXTI_PRIVENR2_PRIV44_Msk /*!< Security enable on line 12 */ -#define EXTI_PRIVENR2_PRIV45_Pos (13U) -#define EXTI_PRIVENR2_PRIV45_Msk (0x1UL << EXTI_PRIVENR2_PRIV45_Pos) /*!< 0x00002000 */ -#define EXTI_PRIVENR2_PRIV45 EXTI_PRIVENR2_PRIV45_Msk /*!< Security enable on line 13 */ -#define EXTI_PRIVENR2_PRIV46_Pos (14U) -#define EXTI_PRIVENR2_PRIV46_Msk (0x1UL << EXTI_PRIVENR2_PRIV46_Pos) /*!< 0x00004000 */ -#define EXTI_PRIVENR2_PRIV46 EXTI_PRIVENR2_PRIV46_Msk /*!< Security enable on line 14 */ #define EXTI_PRIVENR2_PRIV47_Pos (15U) #define EXTI_PRIVENR2_PRIV47_Msk (0x1UL << EXTI_PRIVENR2_PRIV47_Pos) /*!< 0x00008000 */ #define EXTI_PRIVENR2_PRIV47 EXTI_PRIVENR2_PRIV47_Msk /*!< Security enable on line 15 */ -#define EXTI_PRIVENR2_PRIV48_Pos (16U) -#define EXTI_PRIVENR2_PRIV48_Msk (0x1UL << EXTI_PRIVENR2_PRIV48_Pos) /*!< 0x00010000 */ -#define EXTI_PRIVENR2_PRIV48 EXTI_PRIVENR2_PRIV48_Msk /*!< Security enable on line 16 */ #define EXTI_PRIVENR2_PRIV49_Pos (17U) #define EXTI_PRIVENR2_PRIV49_Msk (0x1UL << EXTI_PRIVENR2_PRIV49_Pos) /*!< 0x00020000 */ #define EXTI_PRIVENR2_PRIV49 EXTI_PRIVENR2_PRIV49_Msk /*!< Security enable on line 17 */ #define EXTI_PRIVENR2_PRIV50_Pos (18U) #define EXTI_PRIVENR2_PRIV50_Msk (0x1UL << EXTI_PRIVENR2_PRIV50_Pos) /*!< 0x00040000 */ #define EXTI_PRIVENR2_PRIV50 EXTI_PRIVENR2_PRIV50_Msk /*!< Security enable on line 18 */ -#define EXTI_PRIVENR2_PRIV51_Pos (19U) -#define EXTI_PRIVENR2_PRIV51_Msk (0x1UL << EXTI_PRIVENR2_PRIV51_Pos) /*!< 0x00080000 */ -#define EXTI_PRIVENR2_PRIV51 EXTI_PRIVENR2_PRIV51_Msk /*!< Security enable on line 19 */ -#define EXTI_PRIVENR2_PRIV52_Pos (20U) -#define EXTI_PRIVENR2_PRIV52_Msk (0x1UL << EXTI_PRIVENR2_PRIV52_Pos) /*!< 0x00100000 */ -#define EXTI_PRIVENR2_PRIV52 EXTI_PRIVENR2_PRIV52_Msk /*!< Security enable on line 20 */ #define EXTI_PRIVENR2_PRIV53_Pos (21U) #define EXTI_PRIVENR2_PRIV53_Msk (0x1UL << EXTI_PRIVENR2_PRIV53_Pos) /*!< 0x00200000 */ #define EXTI_PRIVENR2_PRIV53 EXTI_PRIVENR2_PRIV53_Msk /*!< Security enable on line 21 */ -#define EXTI_PRIVENR2_PRIV54_Pos (22U) -#define EXTI_PRIVENR2_PRIV54_Msk (0x1UL << EXTI_PRIVENR2_PRIV54_Pos) /*!< 0x00400000 */ -#define EXTI_PRIVENR2_PRIV54 EXTI_PRIVENR2_PRIV54_Msk /*!< Security enable on line 22 */ -#define EXTI_PRIVENR2_PRIV55_Pos (23U) -#define EXTI_PRIVENR2_PRIV55_Msk (0x1UL << EXTI_PRIVENR2_PRIV55_Pos) /*!< 0x00800000 */ -#define EXTI_PRIVENR2_PRIV55 EXTI_PRIVENR2_PRIV55_Msk /*!< Security enable on line 23 */ -#define EXTI_PRIVENR2_PRIV56_Pos (24U) -#define EXTI_PRIVENR2_PRIV56_Msk (0x1UL << EXTI_PRIVENR2_PRIV56_Pos) /*!< 0x01000000 */ -#define EXTI_PRIVENR2_PRIV56 EXTI_PRIVENR2_PRIV56_Msk /*!< Security enable on line 24 */ -#define EXTI_PRIVENR2_PRIV57_Pos (25U) -#define EXTI_PRIVENR2_PRIV57_Msk (0x1UL << EXTI_PRIVENR2_PRIV57_Pos) /*!< 0x02000000 */ -#define EXTI_PRIVENR2_PRIV57 EXTI_PRIVENR2_PRIV57_Msk /*!< Security enable on line 25 */ /***************** Bit definition for EXTI_EXTICR1 register **************/ #define EXTI_EXTICR1_EXTI0_Pos (0U) @@ -4832,7 +4573,7 @@ typedef struct /******************* Bit definition for EXTI_IMR1 register ******************/ #define EXTI_IMR1_IM_Pos (0U) -#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */ +#define EXTI_IMR1_IM_Msk (0x3F6BFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x3F6BFFFF */ #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask */ #define EXTI_IMR1_IM0_Pos (0U) #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ @@ -4888,24 +4629,15 @@ typedef struct #define EXTI_IMR1_IM17_Pos (17U) #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR1_IM18_Pos (18U) -#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ -#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ #define EXTI_IMR1_IM19_Pos (19U) #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR1_IM20_Pos (20U) -#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ -#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ #define EXTI_IMR1_IM21_Pos (21U) #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ #define EXTI_IMR1_IM22_Pos (22U) #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */ -#define EXTI_IMR1_IM23_Pos (23U) -#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ -#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ #define EXTI_IMR1_IM24_Pos (24U) #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ @@ -4924,12 +4656,6 @@ typedef struct #define EXTI_IMR1_IM29_Pos (29U) #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */ -#define EXTI_IMR1_IM30_Pos (30U) -#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ -#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */ -#define EXTI_IMR1_IM31_Pos (31U) -#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ -#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ /******************* Bit definition for EXTI_EMR1 register ******************/ #define EXTI_EMR1_EM_Pos (0U) @@ -4989,24 +4715,15 @@ typedef struct #define EXTI_EMR1_EM17_Pos (17U) #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ -#define EXTI_EMR1_EM18_Pos (18U) -#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ -#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ #define EXTI_EMR1_EM19_Pos (19U) #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ -#define EXTI_EMR1_EM20_Pos (20U) -#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ -#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */ #define EXTI_EMR1_EM21_Pos (21U) #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ #define EXTI_EMR1_EM22_Pos (22U) #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */ -#define EXTI_EMR1_EM23_Pos (23U) -#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ -#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ #define EXTI_EMR1_EM24_Pos (24U) #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */ @@ -5025,32 +4742,11 @@ typedef struct #define EXTI_EMR1_EM29_Pos (29U) #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */ -#define EXTI_EMR1_EM30_Pos (30U) -#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ -#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */ -#define EXTI_EMR1_EM31_Pos (31U) -#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ -#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ /******************* Bit definition for EXTI_IMR2 register *******************/ #define EXTI_IMR2_IM_Pos (0U) -#define EXTI_IMR2_IM_Msk (0x003FFFFFUL << EXTI_IMR2_IM_Pos) /*!< 0x003FFFFF */ +#define EXTI_IMR2_IM_Msk (0x002687E0UL << EXTI_IMR2_IM_Pos) /*!< 0x002687E0 */ #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask */ -#define EXTI_IMR2_IM32_Pos (0U) -#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ -#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */ -#define EXTI_IMR2_IM33_Pos (1U) -#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ -#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */ -#define EXTI_IMR2_IM34_Pos (2U) -#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ -#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */ -#define EXTI_IMR2_IM35_Pos (3U) -#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ -#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */ -#define EXTI_IMR2_IM36_Pos (4U) -#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ -#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */ #define EXTI_IMR2_IM37_Pos (5U) #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */ @@ -5069,69 +4765,24 @@ typedef struct #define EXTI_IMR2_IM42_Pos (10U) #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */ #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */ -#define EXTI_IMR2_IM43_Pos (11U) -#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */ -#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */ -#define EXTI_IMR2_IM44_Pos (12U) -#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ -#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */ -#define EXTI_IMR2_IM46_Pos (14U) -#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ -#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */ #define EXTI_IMR2_IM47_Pos (15U) #define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */ #define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */ -#define EXTI_IMR2_IM48_Pos (16U) -#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */ -#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */ #define EXTI_IMR2_IM49_Pos (17U) #define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */ #define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */ #define EXTI_IMR2_IM50_Pos (18U) #define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */ #define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */ -#define EXTI_IMR2_IM51_Pos (19U) -#define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */ -#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */ -#define EXTI_IMR2_IM52_Pos (20U) -#define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */ -#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */ #define EXTI_IMR2_IM53_Pos (21U) #define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */ #define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */ -#define EXTI_IMR2_IM54_Pos (22U) -#define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */ -#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */ -#define EXTI_IMR2_IM55_Pos (23U) -#define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */ -#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */ -#define EXTI_IMR2_IM56_Pos (24U) -#define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */ -#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */ -#define EXTI_IMR2_IM57_Pos (25U) -#define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */ -#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */ /******************* Bit definition for EXTI_EMR2 register *******************/ #define EXTI_EMR2_EM_Pos (0U) -#define EXTI_EMR2_EM_Msk (0x03FFFFFFUL << EXTI_EMR2_EM_Pos) /*!< 0x03FFFFFF */ +#define EXTI_EMR2_EM_Msk (0x002687E0UL << EXTI_EMR2_EM_Pos) /*!< 0x002687E0 */ #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask */ -#define EXTI_EMR2_EM32_Pos (0U) -#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ -#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/ -#define EXTI_EMR2_EM33_Pos (1U) -#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ -#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/ -#define EXTI_EMR2_EM34_Pos (2U) -#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ -#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/ -#define EXTI_EMR2_EM35_Pos (3U) -#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ -#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/ -#define EXTI_EMR2_EM36_Pos (4U) -#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */ -#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/ #define EXTI_EMR2_EM37_Pos (5U) #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */ #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/ @@ -5150,48 +4801,18 @@ typedef struct #define EXTI_EMR2_EM42_Pos (10U) #define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */ #define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */ -#define EXTI_EMR2_EM43_Pos (11U) -#define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */ -#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */ -#define EXTI_EMR2_EM44_Pos (12U) -#define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */ -#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */ -#define EXTI_EMR2_EM46_Pos (14U) -#define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */ -#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */ #define EXTI_EMR2_EM47_Pos (15U) #define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */ #define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */ -#define EXTI_EMR2_EM48_Pos (16U) -#define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */ -#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */ #define EXTI_EMR2_EM49_Pos (17U) #define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */ #define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */ #define EXTI_EMR2_EM50_Pos (18U) #define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */ #define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */ -#define EXTI_EMR2_EM51_Pos (19U) -#define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */ -#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */ -#define EXTI_EMR2_EM52_Pos (20U) -#define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */ -#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */ #define EXTI_EMR2_EM53_Pos (21U) #define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */ #define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */ -#define EXTI_EMR2_EM54_Pos (22U) -#define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */ -#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */ -#define EXTI_EMR2_EM55_Pos (23U) -#define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */ -#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */ -#define EXTI_EMR2_EM56_Pos (24U) -#define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */ -#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */ -#define EXTI_EMR2_EM57_Pos (25U) -#define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */ -#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */ /******************************************************************************/ /* */ @@ -5775,7 +5396,7 @@ typedef struct /* FLASH */ /* */ /******************************************************************************/ -#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycle */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycle */ #define FLASH_BLOCKBASED_NB_REG (1U) /*!< 1 Block-based registers for each Flash bank */ #define FLASH_SIZE_DEFAULT (0x20000U) /*!< FLASH Size */ #define FLASH_SECTOR_NB (8U) /*!< Flash Sector number */ @@ -7831,6 +7452,11 @@ typedef struct #define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ + __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ + __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ + __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ + __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ + __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ + __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ + uint32_t RESERVED6[7]; /*!< Reserved6, Address offset: 0xA4-0xBF */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xC4-0xDC */ + __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ + __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ + __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ + uint32_t RESERVED9[7]; /*!< Reserved9, Address offset: 0x1A4-0x1BF */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + uint32_t RESERVED10[7]; /*!< Reserved10, Address offset: 0x1C4-0x1DC */ + __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ + __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ + __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ + __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ + __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ + __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + __IO uint32_t WPR3; /*!< SRAM Write Protection Register 3, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< RCC PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ + __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ + uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ + __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ + __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + uint32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */ + __IO uint32_t IPVER; /*!< UCPD IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPID; /*!< UCPD IP Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< UCPD Magic Identification register, Address offset: 0x3FC */ +} UCPD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ + +#define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ +#define SRAM2_SIZE (0x14000UL) /*!< SRAM2=80k */ +#define SRAM3_SIZE (0x10000UL) /*!< SRAM3=64k */ +#define BKPSRAM_SIZE (0x00800UL) /*!< BKPSRAM=2k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 512 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (128 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20020000UL) /*!< SRAM2 (80 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20034000UL) /*!< SRAM3 (64 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ +#define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ +#define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ + + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) + +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define I3C2_BASE_NS (APB3PERIPH_BASE_NS + 0x3000UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +/*!< AHB4 Non secure peripherals */ +#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) + +#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 512 KB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (128 KB) secure base address */ +#define SRAM2_BASE_S (0x30020000UL) /*!< SRAM2 (80 KB) secure base address */ +#define SRAM3_BASE_S (0x30034000UL) /*!< SRAM3 (64 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) +#define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) +#define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) +#define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) +#define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) +#define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) +#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) +#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) +#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB3 secure peripherals */ +#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define I3C2_BASE_S (APB3PERIPH_BASE_S + 0x3000UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB3 secure peripherals */ +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) + +/*!< AHB4 secure peripherals */ +#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) +#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) + +#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) + +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ + +/* Internal Flash EDATA Area */ +#define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ +#define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ +#define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ + +/* Internal Flash OBK Area */ +#define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ +#define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ +#define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ +#define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ +#define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ +#define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ +#define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ +#define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ + +#define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ + +#define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ +#endif /* CMSE */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB84UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0xBF9FB68UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it jumps to the non-secure reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; +} S_pFuncTypeDef; + +/** + * @brief RSSLib Non-secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; +} NSC_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + uint32_t RESERVED1[3]; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB6CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB74UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0xBF9FB6CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *)TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *)TIM14_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) +#define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + +/*!< AHB4 Non secure peripherals */ +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) + +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) +#define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) +#define USART2_S ((USART_TypeDef *)USART2_BASE_S) +#define USART3_S ((USART_TypeDef *)USART3_BASE_S) +#define UART4_S ((USART_TypeDef *)UART4_BASE_S) +#define UART5_S ((USART_TypeDef *)UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) +#define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) +#define CRS_S ((CRS_TypeDef *)CRS_BASE_S) +#define USART6_S ((USART_TypeDef *)USART6_BASE_S) +#define CEC_S ((CEC_TypeDef *)CEC_BASE_S) +#define DTS_S ((DTS_TypeDef *)DTS_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) + +/*!< APB2 secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) +#define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) +#define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) +#define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) +#define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) +#define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) +#define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) +#define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) + + +/*!< AHB2 secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) + +/*!< APB3 secure peripherals */ +#define SBS_S ((SBS_TypeDef *) SBS_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) + +/*!< AHB4 secure peripherals */ +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) + +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) + +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define FLASH_OBK_BASE FLASH_OBK_BASE_S +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_S +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define APB3PERIPH_BASE APB3PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA2 GPDMA2_S +#define GPDMA2_BASE GPDMA2_BASE_S + +#define GPDMA2_Channel0 GPDMA2_Channel0_S +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S + +#define GPDMA2_Channel1 GPDMA2_Channel1_S +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S + +#define GPDMA2_Channel2 GPDMA2_Channel2_S +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S + +#define GPDMA2_Channel3 GPDMA2_Channel3_S +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S + +#define GPDMA2_Channel4 GPDMA2_Channel4_S +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S + +#define GPDMA2_Channel5 GPDMA2_Channel5_S +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S + +#define GPDMA2_Channel6 GPDMA2_Channel6_S +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S + +#define GPDMA2_Channel7 GPDMA2_Channel7_S +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define CEC CEC_S +#define CEC_BASE CEC_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SBS SBS_S +#define SBS_BASE SBS_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + + + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#else + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_OBK_BASE FLASH_OBK_BASE_NS +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS + +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +#define SRAM3_BASE SRAM3_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define CEC CEC_NS +#define CEC_BASE CEC_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + + + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#endif + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ +#define ADC_OR_OP1_Pos (1U) +#define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OBKERR_Pos (21U) +#define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ +#define FLASH_SR_OBKWERR_Pos (22U) +#define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OBKERRIE_Pos (21U) +#define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ +#define FLASH_CR_OBKWERRIE_Pos (22U) +#define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OBKERR_Pos (21U) +#define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ +#define FLASH_CCR_CLR_OBKWERR_Pos (22U) +#define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/****************** Bits definition for FLASH_OBKCFGR register *****************/ +#define FLASH_OBKCFGR_LOCK_Pos (0U) +#define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ +#define FLASH_OBKCFGR_ALT_SECT_Pos (2U) +#define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ +#define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ +#define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) +#define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ +#define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_BOOT_UBE_Pos (22U) +#define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ +#define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) +#define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ +#define FLASH_OPTSR2_TZEN_Pos (24U) +#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ +#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + +/***************** Bits definition for FLASH_SECWMR register ********************/ +#define FLASH_SECWMR_SECWM_STRT_Pos (0U) +#define FLASH_SECWMR_SECWM_STRT_Msk (0x1FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ +#define FLASH_SECWMR_SECWM_END_Pos (16U) +#define FLASH_SECWMR_SECWM_END_Msk (0x1FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0x000000FFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x000000FF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + +/***************** Bits definition for FLASH_EDATA register ********************/ +#define FLASH_EDATAR_EDATA_STRT_Pos (0U) +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ +#define FLASH_EDATAR_EDATA_EN_Pos (15U) +#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ +#define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x1FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x1FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x001F0000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_OBK_ECC_Pos (20U) +#define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ +#define FLASH_ECCR_DATA_ECC_Pos (21U) +#define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_OR register ******************/ +#define RTC_OR_OUT2_RMP_Pos (0U) +#define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP4MF_Pos (19U) +#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk +#define TAMP_SMISR_ITAMP15MF_Pos (30U) +#define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + +/******************** Bits definition for TAMP_OR register ***************/ +#define TAMP_OR_OUT3_RMP_Pos (1U) +#define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ +#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk +#define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ +#define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ +#define TAMP_OR_OUT5_RMP_Pos (3U) +#define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk +#define TAMP_OR_IN2_RMP_Pos (8U) +#define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk +#define TAMP_OR_IN3_RMP_Pos (9U) +#define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk +#define TAMP_OR_IN4_RMP_Pos (10U) +#define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* SBS */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SBS_HDPLCR register *****************/ +#define SBS_HDPLCR_INCR_HDPL_Pos (0U) +#define SBS_HDPLCR_INCR_HDPL_Msk (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLCR_INCR_HDPL SBS_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL value. */ + +/******************** Bit definition for SBS_HDPLSR register *****************/ +#define SBS_HDPLSR_HDPL_Pos (0U) +#define SBS_HDPLSR_HDPL_Msk (0xFFUL << SBS_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLSR_HDPL SBS_HDPLSR_HDPL_Msk /*!< HDPL value. */ + +/******************** Bit definition for SBS_NEXTHDPLCR register *****************/ +#define SBS_NEXTHDPLCR_NEXTHDPL_Pos (0U) +#define SBS_NEXTHDPLCR_NEXTHDPL_Msk (0x3UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000003 */ +#define SBS_NEXTHDPLCR_NEXTHDPL SBS_NEXTHDPLCR_NEXTHDPL_Msk /*!< NEXTHDPL value. */ +#define SBS_NEXTHDPLCR_NEXTHDPL_0 (0x1UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000001 */ +#define SBS_NEXTHDPLCR_NEXTHDPL_1 (0x2UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000002 */ + +/******************** Bit definition for SBS_DBGCR register *****************/ +#define SBS_DBGCR_AP_UNLOCK_Pos (0U) +#define SBS_DBGCR_AP_UNLOCK_Msk (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGCR_AP_UNLOCK SBS_DBGCR_AP_UNLOCK_Msk /*!< Open the Access Port. */ + +#define SBS_DBGCR_DBG_UNLOCK_Pos (8U) +#define SBS_DBGCR_DBG_UNLOCK_Msk (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define SBS_DBGCR_DBG_UNLOCK SBS_DBGCR_DBG_UNLOCK_Msk /*!< Open the debug when DBG_AUTH_HDPL is reached. */ + +#define SBS_DBGCR_DBG_AUTH_HDPL_Pos (16U) +#define SBS_DBGCR_DBG_AUTH_HDPL_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define SBS_DBGCR_DBG_AUTH_HDPL SBS_DBGCR_DBG_AUTH_HDPL_Msk /*!< HDPL value when the debug should be effectively opened. */ + +#define SBS_DBGCR_DBG_AUTH_SEC_Pos (24U) +#define SBS_DBGCR_DBG_AUTH_SEC_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-secured and secured debugs. */ + +/******************** Bit definition for SBS_DBGLCKR register *****************/ +#define SBS_DBGLOCKR_DBGCFG_LOCK_Pos (0U) +#define SBS_DBGLOCKR_DBGCFG_LOCK_Msk (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGLOCKR_DBGCFG_LOCK SBS_DBGLOCKR_DBGCFG_LOCK_Msk /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */ + +/******************** Bit definition for SBS_RSSCMDR register ***************/ +#define SBS_RSSCMDR_RSSCMD_Pos (0U) +#define SBS_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SBS_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ +#define SBS_RSSCMDR_RSSCMD SBS_RSSCMDR_RSSCMD_Msk /*!< command to be executed by the RSS. */ + +/******************** Bit definition for SBS_EPOCHSELCR register ************/ +#define SBS_EPOCHSELCR_EPOCH_SEL_Pos (0U) +#define SBS_EPOCHSELCR_EPOCH_SEL_Msk (0x3UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000003 */ +#define SBS_EPOCHSELCR_EPOCH_SEL SBS_EPOCHSELCR_EPOCH_SEL_Msk /*!< Select EPOCH sent to SAES IP to encrypt/decrypt keys */ +#define SBS_EPOCHSELCR_EPOCH_SEL_0 (0x1UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000001 */ +#define SBS_EPOCHSELCR_EPOCH_SEL_1 (0x2UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000002 */ + +/****************** Bit definition for SBS_PMCR register ****************/ +#define SBS_PMCR_PB6_FMP_Pos (16U) +#define SBS_PMCR_PB6_FMP_Msk (0x1UL << SBS_PMCR_PB6_FMP_Pos) /*!< 0x00010000 */ +#define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode Plus command on PB(6) */ +#define SBS_PMCR_PB7_FMP_Pos (17U) +#define SBS_PMCR_PB7_FMP_Msk (0x1UL << SBS_PMCR_PB7_FMP_Pos) /*!< 0x00020000 */ +#define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode Plus command on PB(7) */ +#define SBS_PMCR_PB8_FMP_Pos (18U) +#define SBS_PMCR_PB8_FMP_Msk (0x1UL << SBS_PMCR_PB8_FMP_Pos) /*!< 0x00040000 */ +#define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode Plus command on PB(8) */ +#define SBS_PMCR_PB9_FMP_Pos (19U) +#define SBS_PMCR_PB9_FMP_Msk (0x1UL << SBS_PMCR_PB9_FMP_Pos) /*!< 0x00080000 */ +#define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode Plus command on PB(9) */ + +/****************** Bit definition for SBS_FPUIMR register ***************/ +#define SBS_FPUIMR_FPU_IE_Pos (0U) +#define SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */ +#define SBS_FPUIMR_FPU_IE SBS_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */ +#define SBS_FPUIMR_FPU_IE_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_1 (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */ + +/****************** Bit definition for SBS_MESR register ****************/ +#define SBS_MESR_MCLR_Pos (0U) +#define SBS_MESR_MCLR_Msk (0x1UL << SBS_MESR_MCLR_Pos) /*!< 0x00000001 */ +#define SBS_MESR_MCLR SBS_MESR_MCLR_Msk /*!< Status of Erase after Reset */ +#define SBS_MESR_IPMEE_Pos (16U) +#define SBS_MESR_IPMEE_Msk (0x1UL << SBS_MESR_IPMEE_Pos) /*!< 0x00010000 */ +#define SBS_MESR_IPMEE SBS_MESR_IPMEE_Msk /*!< Status of End of Erase for ICache and PKA RAMs */ + +/****************** Bit definition for SBS_CCCSR register ****************/ +#define SBS_CCCSR_EN1_Pos (0U) +#define SBS_CCCSR_EN1_Msk (0x1UL << SBS_CCCSR_EN1_Pos) /*!< 0x00000001 */ +#define SBS_CCCSR_EN1 SBS_CCCSR_EN1_Msk /*!< Enable compensation cell for VDD power rail */ +#define SBS_CCCSR_CS1_Pos (1U) +#define SBS_CCCSR_CS1_Msk (0x1UL << SBS_CCCSR_CS1_Pos) /*!< 0x00000002 */ +#define SBS_CCCSR_CS1 SBS_CCCSR_CS1_Msk /*!< Code selection for VDD power rail */ +#define SBS_CCCSR_EN2_Pos (2U) +#define SBS_CCCSR_EN2_Msk (0x1UL << SBS_CCCSR_EN2_Pos) /*!< 0x00000004 */ +#define SBS_CCCSR_EN2 SBS_CCCSR_EN2_Msk /*!< Enable compensation cell for VDDIO power rail */ +#define SBS_CCCSR_CS2_Pos (3U) +#define SBS_CCCSR_CS2_Msk (0x1UL << SBS_CCCSR_CS2_Pos) /*!< 0x00000008 */ +#define SBS_CCCSR_CS2 SBS_CCCSR_CS2_Msk /*!< Code selection for VDDIO power rail */ +#define SBS_CCCSR_RDY1_Pos (8U) +#define SBS_CCCSR_RDY1_Msk (0x1UL << SBS_CCCSR_RDY1_Pos) /*!< 0x00000100 */ +#define SBS_CCCSR_RDY1 SBS_CCCSR_RDY1_Msk /*!< VDD compensation cell ready flag */ +#define SBS_CCCSR_RDY2_Pos (9U) +#define SBS_CCCSR_RDY2_Msk (0x1UL << SBS_CCCSR_RDY2_Pos) /*!< 0x00000200 */ +#define SBS_CCCSR_RDY2 SBS_CCCSR_RDY2_Msk /*!< VDDIO compensation cell ready flag */ + +/****************** Bit definition for SBS_CCVALR register ****************/ +#define SBS_CCVALR_ANSRC1_Pos (0U) +#define SBS_CCVALR_ANSRC1_Msk (0xFUL << SBS_CCVALR_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCVALR_ANSRC1 SBS_CCVALR_ANSRC1_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC1_Pos (4U) +#define SBS_CCVALR_APSRC1_Msk (0xFUL << SBS_CCVALR_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCVALR_APSRC1 SBS_CCVALR_APSRC1_Msk /*!< PMOS compensation value */ +#define SBS_CCVALR_ANSRC2_Pos (8U) +#define SBS_CCVALR_ANSRC2_Msk (0xFUL << SBS_CCVALR_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCVALR_ANSRC2 SBS_CCVALR_ANSRC2_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC2_Pos (12U) +#define SBS_CCVALR_APSRC2_Msk (0xFUL << SBS_CCVALR_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCVALR_APSRC2 SBS_CCVALR_APSRC2_Msk /*!< PMOS compensation value */ + +/****************** Bit definition for SBS_CCSWCR register ****************/ +#define SBS_CCSWCR_SW_ANSRC1_Pos (0U) +#define SBS_CCSWCR_SW_ANSRC1_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCSWCR_SW_ANSRC1 SBS_CCSWCR_SW_ANSRC1_Msk /*!< NMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_APSRC1_Pos (4U) +#define SBS_CCSWCR_SW_APSRC1_Msk (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCSWCR_SW_APSRC1 SBS_CCSWCR_SW_APSRC1_Msk /*!< PMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_ANSRC2_Pos (8U) +#define SBS_CCSWCR_SW_ANSRC2_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCSWCR_SW_ANSRC2 SBS_CCSWCR_SW_ANSRC2_Msk /*!< NMOS compensation code for VDDIO Power Rail */ +#define SBS_CCSWCR_SW_APSRC2_Pos (12U) +#define SBS_CCSWCR_SW_APSRC2_Msk (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCSWCR_SW_APSRC2 SBS_CCSWCR_SW_APSRC2_Msk /*!< PMOS compensation code for VDDIO Power Rail */ + +/****************** Bit definition for SBS_CFGR2 register ****************/ +#define SBS_CFGR2_CLL_Pos (0U) +#define SBS_CFGR2_CLL_Msk (0x1UL << SBS_CFGR2_CLL_Pos) /*!< 0x00000001 */ +#define SBS_CFGR2_CLL SBS_CFGR2_CLL_Msk /*!< Core Lockup Lock */ +#define SBS_CFGR2_SEL_Pos (1U) +#define SBS_CFGR2_SEL_Msk (0x1UL << SBS_CFGR2_SEL_Pos) /*!< 0x00000002 */ +#define SBS_CFGR2_SEL SBS_CFGR2_SEL_Msk /*!< SRAM ECC Lock */ +#define SBS_CFGR2_PVDL_Pos (2U) +#define SBS_CFGR2_PVDL_Msk (0x1UL << SBS_CFGR2_PVDL_Pos) /*!< 0x00000004 */ +#define SBS_CFGR2_PVDL SBS_CFGR2_PVDL_Msk /*!< PVD Lock */ +#define SBS_CFGR2_ECCL_Pos (3U) +#define SBS_CFGR2_ECCL_Msk (0x1UL << SBS_CFGR2_ECCL_Pos) /*!< 0x00000008 */ +#define SBS_CFGR2_ECCL SBS_CFGR2_ECCL_Msk /*!< Flash ECC Lock*/ + +/******************** Bit definition for SBS_SECCFGR register ***************/ +#define SBS_SECCFGR_SBSSEC_Pos (0U) +#define SBS_SECCFGR_SBSSEC_Msk (0x1UL << SBS_SECCFGR_SBSSEC_Pos) /*!< 0x00000001 */ +#define SBS_SECCFGR_SBSSEC SBS_SECCFGR_SBSSEC_Msk /*!< SBS clock control security enable */ +#define SBS_SECCFGR_CLASSBSEC_Pos (1U) +#define SBS_SECCFGR_CLASSBSEC_Msk (0x1UL << SBS_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */ +#define SBS_SECCFGR_CLASSBSEC SBS_SECCFGR_CLASSBSEC_Msk /*!< ClassB SBS security enable */ +#define SBS_SECCFGR_FPUSEC_Pos (3U) +#define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */ +#define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */ + +/****************** Bit definition for SBS_CNSLCKR register **************/ +#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U) +#define SBS_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */ +#define SBS_CNSLCKR_LOCKNSVTOR SBS_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */ +#define SBS_CNSLCKR_LOCKNSMPU_Pos (1U) +#define SBS_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */ + +/****************** Bit definition for SBS_CSLCKR register ***************/ +#define SBS_CSLCKR_LOCKSVTAIRCR_Pos (0U) +#define SBS_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SBS_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */ +#define SBS_CSLCKR_LOCKSVTAIRCR SBS_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */ +#define SBS_CSLCKR_LOCKSMPU_Pos (1U) +#define SBS_CSLCKR_LOCKSMPU_Msk (0x1UL << SBS_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CSLCKR_LOCKSMPU SBS_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */ +#define SBS_CSLCKR_LOCKSAU_Pos (2U) +#define SBS_CSLCKR_LOCKSAU_Msk (0x1UL << SBS_CSLCKR_LOCKSAU_Pos) /*!< 0x00000004 */ +#define SBS_CSLCKR_LOCKSAU SBS_CSLCKR_LOCKSAU_Msk /*!< Disable changes to SAU registers */ + +/****************** Bit definition for SBS_ECCNMIR register ***************/ +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos (0U) +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos) /*!< 0x00000001 */ +#define SBS_ECCNMIR_ECCNMI_MASK_EN SBS_ECCNMIR_ECCNMI_MASK_EN_Msk /*!< Disable NMI in case of double ECC error in flash interface */ + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ + +/******************* Bits definition for GTZC_TZSC_MPCWM_CFGR register **********/ +#define GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) +#define GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk +#define GTZC_TZSC_MPCWM_CFGR_SEC_Pos (8U) +#define GTZC_TZSC_MPCWM_CFGR_SEC_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SEC GTZC_TZSC_MPCWM_CFGR_SEC_Msk +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) +#define GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk + +/******************* Bits definition for GTZC_TZSC_MPCWMR register **************/ +#define GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) +#define GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk + +/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/ + +/*************** Bits definition for register x=1 (TZSC1) *************/ +#define GTZC_CFGR1_TIM2_Pos (0U) +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos (1U) +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_TIM4_Pos (2U) +#define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) +#define GTZC_CFGR1_TIM5_Pos (3U) +#define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos) +#define GTZC_CFGR1_TIM6_Pos (4U) +#define GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) +#define GTZC_CFGR1_TIM7_Pos (5U) +#define GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) +#define GTZC_CFGR1_TIM12_Pos (6U) +#define GTZC_CFGR1_TIM12_Msk (0x01UL << GTZC_CFGR1_TIM12_Pos) +#define GTZC_CFGR1_WWDG_Pos (9U) +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos (10U) +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_SPI2_Pos (11U) +#define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) +#define GTZC_CFGR1_SPI3_Pos (12U) +#define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) +#define GTZC_CFGR1_USART2_Pos (13U) +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_USART3_Pos (14U) +#define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) +#define GTZC_CFGR1_UART4_Pos (15U) +#define GTZC_CFGR1_UART4_Msk (0x01UL << GTZC_CFGR1_UART4_Pos) +#define GTZC_CFGR1_UART5_Pos (16U) +#define GTZC_CFGR1_UART5_Msk (0x01UL << GTZC_CFGR1_UART5_Pos) +#define GTZC_CFGR1_I2C1_Pos (17U) +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_I2C2_Pos (18U) +#define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) +#define GTZC_CFGR1_I3C1_Pos (19U) +#define GTZC_CFGR1_I3C1_Msk (0x01UL << GTZC_CFGR1_I3C1_Pos) +#define GTZC_CFGR1_CRS_Pos (20U) +#define GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) +#define GTZC_CFGR1_USART6_Pos (21U) +#define GTZC_CFGR1_USART6_Msk (0x01UL << GTZC_CFGR1_USART6_Pos) +#define GTZC_CFGR1_HDMICEC_Pos (24U) +#define GTZC_CFGR1_HDMICEC_Msk (0x01UL << GTZC_CFGR1_HDMICEC_Pos) +#define GTZC_CFGR1_DAC1_Pos (25U) +#define GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) +#define GTZC_CFGR1_DTS_Pos (30U) +#define GTZC_CFGR1_DTS_Msk (0x01UL << GTZC_CFGR1_DTS_Pos) +#define GTZC_CFGR1_LPTIM2_Pos (31U) +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/*************** Bits definition for register x=2 (TZSC1) *************/ +#define GTZC_CFGR2_FDCAN1_Pos (0U) +#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos) +#define GTZC_CFGR2_FDCAN2_Pos (1U) +#define GTZC_CFGR2_FDCAN2_Msk (0x01UL << GTZC_CFGR2_FDCAN2_Pos) +#define GTZC_CFGR2_UCPD1_Pos (2U) +#define GTZC_CFGR2_UCPD1_Msk (0x01UL << GTZC_CFGR2_UCPD1_Pos) +#define GTZC_CFGR2_TIM1_Pos (8U) +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos (9U) +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_TIM8_Pos (10U) +#define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos) +#define GTZC_CFGR2_USART1_Pos (11U) +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM15_Pos (12U) +#define GTZC_CFGR2_TIM15_Msk (0x01UL << GTZC_CFGR2_TIM15_Pos) +#define GTZC_CFGR2_SPI4_Pos (15U) +#define GTZC_CFGR2_SPI4_Msk (0x01UL << GTZC_CFGR2_SPI4_Pos) +#define GTZC_CFGR2_USB_Pos (19U) +#define GTZC_CFGR2_USB_Msk (0x01UL << GTZC_CFGR2_USB_Pos) +#define GTZC_CFGR2_LPUART1_Pos (25U) +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos (26U) +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos (28U) +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) + +/*************** Bits definition for register x=3 (TZSC1) *************/ +#define GTZC_CFGR3_VREFBUF_Pos (1U) +#define GTZC_CFGR3_VREFBUF_Msk (0x01UL << GTZC_CFGR3_VREFBUF_Pos) +#define GTZC_CFGR3_I3C2_Pos (2U) +#define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) +#define GTZC_CFGR3_CRC_Pos (8U) +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos (12U) +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_DCACHE1_REG_Pos (13U) +#define GTZC_CFGR3_DCACHE1_REG_Msk (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos) +#define GTZC_CFGR3_ADC_Pos (14U) +#define GTZC_CFGR3_ADC_Msk (0x01UL << GTZC_CFGR3_ADC_Pos) +#define GTZC_CFGR3_DCMI_PSSI_Pos (15U) +#define GTZC_CFGR3_DCMI_PSSI_Msk (0x01UL << GTZC_CFGR3_DCMI_PSSI_Pos) +#define GTZC_CFGR3_HASH_Pos (17U) +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos (18U) +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_PKA_Pos (20U) +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_SDMMC1_Pos (21U) +#define GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos) +#define GTZC_CFGR3_FMC_REG_Pos (23U) +#define GTZC_CFGR3_FMC_REG_Msk (0x01UL << GTZC_CFGR3_FMC_REG_Pos) +#define GTZC_CFGR3_OCTOSPI1_Pos (24U) +#define GTZC_CFGR3_OCTOSPI1_Msk (0x01UL << GTZC_CFGR3_OCTOSPI1_Pos) +#define GTZC_CFGR3_RAMCFG_Pos (26U) +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) + +/*************** Bits definition for register x=4 (TZSC1) *************/ +#define GTZC_CFGR4_GPDMA1_Pos (0U) +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_GPDMA2_Pos (1U) +#define GTZC_CFGR4_GPDMA2_Msk (0x01UL << GTZC_CFGR4_GPDMA2_Pos) +#define GTZC_CFGR4_FLASH_Pos (2U) +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos (3U) +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) + +#define GTZC_CFGR4_SBS_Pos (6U) +#define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos) +#define GTZC_CFGR4_RTC_Pos (7U) +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos (8U) +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos (9U) +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos (10U) +#define GTZC_CFGR4_RCC_Msk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos (11U) +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_TZSC_Pos (16U) +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos (17U) +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_OCTOSPI1_MEM_Pos (18U) +#define GTZC_CFGR4_OCTOSPI1_MEM_Msk (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos) +#define GTZC_CFGR4_FMC_MEM_Pos (19U) +#define GTZC_CFGR4_FMC_MEM_Msk (0x01UL << GTZC_CFGR4_FMC_MEM_Pos) +#define GTZC_CFGR4_BKPSRAM_Pos (20U) +#define GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) +#define GTZC_CFGR4_SRAM1_Pos (24U) +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos (25U) +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos (26U) +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos (27U) +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM3_Pos (28U) +#define GTZC_CFGR4_SRAM3_Msk (0x01UL << GTZC_CFGR4_SRAM3_Pos) +#define GTZC_CFGR4_MPCBB3_REG_Pos (29U) +#define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) + +/******************* Bits definition for GTZC_TZSC1_SECCFGR1 register ***************/ +#define GTZC_TZSC1_SECCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_SECCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_SECCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_SECCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_SECCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_SECCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_SECCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_SECCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_SECCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_SECCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_SECCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_SECCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_SECCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_SECCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_SECCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_SECCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_SECCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_SECCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_SECCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_SECCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_SECCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_SECCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_SECCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_SECCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_SECCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_SECCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_SECCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_SECCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_SECCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_SECCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_SECCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_SECCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_SECCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_SECCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_SECCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_SECCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_SECCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_SECCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_SECCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_SECCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_SECCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_SECCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_SECCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_SECCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_SECCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_SECCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_SECCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_SECCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_SECCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_SECCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_SECCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_SECCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_SECCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_SECCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_SECCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_SECCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_SECCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_SECCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_SECCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_PRIVCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_PRIVCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_PRIVCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_PRIVCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC1_IER1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_IER1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_IER1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_IER1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_IER1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_IER1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_IER1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_IER1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_IER1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_IER1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_IER1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_IER1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_IER1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_IER1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_IER1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_IER1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_IER1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_IER1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_IER1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_IER1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_IER1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_IER1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_IER1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_IER1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_IER1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_IER1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_IER1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_IER1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_IER1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_IER1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_IER1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_IER1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_IER1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_IER1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_IER1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_IER1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_IER1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_IER1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_IER1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_IER1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_IER1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_IER1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC1_IER2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_IER2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_IER2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_IER2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_IER2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_IER2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_IER2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_IER2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_IER2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_IER2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_IER2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_IER2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_IER2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_IER2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_IER2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_IER2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_IER2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_IER2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC1_IER3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_IER3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_IER3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_IER3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_IER3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_IER3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_IER3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_IER3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_IER3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_IER3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_IER3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_IER3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_IER3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_IER3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_IER3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_IER3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_IER3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_IER3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC1_IER4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_IER4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_IER4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_IER4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_IER4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_IER4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_IER4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_IER4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_IER4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_IER4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_IER4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_IER4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_IER4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_IER4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_IER4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_IER4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_IER4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_IER4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_IER4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_IER4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_IER4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_IER4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_IER4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_IER4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_IER4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_IER4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_IER4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_IER4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_IER4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_IER4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_IER4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_IER4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_IER4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_IER4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_IER4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_IER4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC1_SR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_SR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_SR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_SR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_SR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_SR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_SR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_SR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_SR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_SR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_SR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_SR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_SR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_SR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_SR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_SR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_SR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_SR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_SR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_SR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_SR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_SR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_SR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_SR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_SR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_SR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_SR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_SR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_SR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_SR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_SR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_SR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_SR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_SR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_SR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_SR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_SR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_SR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_SR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_SR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_SR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_SR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC1_SR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_SR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_SR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_SR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_SR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_SR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_SR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_SR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_SR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_SR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_SR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_SR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_SR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_SR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_SR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_SR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_SR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_SR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC1_SR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_SR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_SR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_SR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_SR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_SR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_SR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_SR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_SR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_SR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_SR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_SR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_SR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_SR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_SR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_SR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_SR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_SR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_SR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_SR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC1_SR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_SR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_SR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_SR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_SR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_SR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_SR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_SR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_SR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_SR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_SR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_SR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_SR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_SR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_SR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_SR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_SR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_SR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_SR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_SR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_SR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_SR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_SR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_SR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_SR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_SR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_SR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_SR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_SR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_SR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_SR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_SR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_SR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_SR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_SR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_SR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC1_FCR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_FCR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_FCR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_FCR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_FCR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_FCR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_FCR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_FCR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_FCR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_FCR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_FCR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_FCR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_FCR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_FCR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_FCR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_FCR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_FCR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_FCR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_FCR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_FCR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_FCR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_FCR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_FCR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_FCR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_FCR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_FCR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_FCR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_FCR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_FCR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_FCR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_FCR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_FCR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_FCR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_FCR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_FCR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_FCR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_FCR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_FCR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_FCR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_FCR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_FCR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_FCR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_FCR2 register **************/ +#define GTZC_TZIC1_FCR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_FCR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_FCR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_FCR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_FCR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_FCR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_FCR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_FCR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_FCR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_FCR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_FCR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_FCR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_FCR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_FCR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_FCR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_FCR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_FCR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_FCR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC1_FCR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_FCR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_FCR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_FCR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_FCR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_FCR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_FCR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_FCR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_FCR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_FCR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_FCR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_FCR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_FCR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_FCR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_FCR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_FCR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_FCR4 register ***************/ +#define GTZC_TZIC1_FCR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_FCR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_FCR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_FCR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_FCR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_FCR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_FCR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_FCR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_FCR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_FCR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_FCR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_FCR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_FCR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_FCR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_FCR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_FCR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_FCR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_FCR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_FCR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_FCR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_FCR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_FCR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_FCR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_FCR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_FCR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_FCR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_FCR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_FCR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_FCR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_FCR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_FCR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_FCR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCKR1 register ************/ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos (4U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos (5U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos (6U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos (7U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos (8U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos (9U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos (10U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos (11U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos (12U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos (13U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos (14U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos (15U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos (16U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos (17U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos (18U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos (19U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos (20U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos (21U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos (22U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos (23U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos (24U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos (25U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos (26U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos (27U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos (28U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos (29U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos (30U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos (31U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */ + + +/******************************************************************************/ +/* */ +/* UCPD */ +/* */ +/******************************************************************************/ +/******************** Bits definition for UCPD_CFG1 register *******************/ +#define UCPD_CFG1_HBITCLKDIV_Pos (0U) +#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */ +#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */ +#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */ +#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */ +#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */ +#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */ +#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */ +#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */ +#define UCPD_CFG1_IFRGAP_Pos (6U) +#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */ +#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */ +#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */ +#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */ +#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */ +#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */ +#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */ +#define UCPD_CFG1_TRANSWIN_Pos (11U) +#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */ +#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */ +#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */ +#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */ +#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */ +#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */ +#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */ +#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U) +#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */ +#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */ +#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */ +#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */ +#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */ +#define UCPD_CFG1_RXORDSETEN_Pos (20U) +#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x1FF00000 */ +#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */ +#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00100000 */ +#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00200000 */ +#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00400000 */ +#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00800000 */ +#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x01000000 */ +#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x02000000 */ +#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x04000000 */ +#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x08000000 */ +#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x10000000 */ +#define UCPD_CFG1_TXDMAEN_Pos (29U) +#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */ +#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define UCPD_CFG1_RXDMAEN_Pos (30U) +#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */ +#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define UCPD_CFG1_UCPDEN_Pos (31U) +#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */ +#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */ + +/******************** Bits definition for UCPD_CFG2 register *******************/ +#define UCPD_CFG2_RXFILTDIS_Pos (0U) +#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */ +#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */ +#define UCPD_CFG2_RXFILT2N3_Pos (1U) +#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */ +#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */ +#define UCPD_CFG2_FORCECLK_Pos (2U) +#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */ +#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */ +#define UCPD_CFG2_WUPEN_Pos (3U) +#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */ +#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define UCPD_CFG2_RXAFILTEN_Pos (8U) +#define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */ +#define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< Rx analog filter enable */ + +/******************** Bits definition for UCPD_CFG3 register *******************/ +#define UCPD_CFG3_TRIM_CC1_RD_Pos (0U) +#define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */ +#define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */ +#define UCPD_CFG3_TRIM_CC1_RP_Pos (9U) +#define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */ +#define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */ +#define UCPD_CFG3_TRIM_CC2_RD_Pos (16U) +#define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */ +#define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */ +#define UCPD_CFG3_TRIM_CC2_RP_Pos (25U) +#define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */ +#define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */ + +/******************** Bits definition for UCPD_CR register ********************/ +#define UCPD_CR_TXMODE_Pos (0U) +#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ +#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */ +#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */ +#define UCPD_CR_TXSEND_Pos (2U) +#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */ +#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXHRST_Pos (3U) +#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */ +#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */ +#define UCPD_CR_RXMODE_Pos (4U) +#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */ +#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */ +#define UCPD_CR_PHYRXEN_Pos (5U) +#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */ +#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */ +#define UCPD_CR_PHYCCSEL_Pos (6U) +#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */ +#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */ +#define UCPD_CR_ANASUBMODE_Pos (7U) +#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */ +#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */ +#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */ +#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */ +#define UCPD_CR_ANAMODE_Pos (9U) +#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */ +#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */ +#define UCPD_CR_CCENABLE_Pos (10U) +#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */ +#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */ +#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */ +#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */ +#define UCPD_CR_USEEXTPHY_Pos (12U) +#define UCPD_CR_USEEXTPHY_Msk (0x1UL << UCPD_CR_USEEXTPHY_Pos) /*!< 0x00001000 */ +#define UCPD_CR_USEEXTPHY UCPD_CR_USEEXTPHY_Msk /*!< Controls enable of USB Power Delivery transmitter */ +#define UCPD_CR_CC2VCONNEN_Pos (13U) +#define UCPD_CR_CC2VCONNEN_Msk (0x1UL << UCPD_CR_CC2VCONNEN_Pos) /*!< 0x00002000 */ +#define UCPD_CR_CC2VCONNEN UCPD_CR_CC2VCONNEN_Msk /*!< VCONN enable for CC2 */ +#define UCPD_CR_CC1VCONNEN_Pos (14U) +#define UCPD_CR_CC1VCONNEN_Msk (0x1UL << UCPD_CR_CC1VCONNEN_Pos) /*!< 0x00004000 */ +#define UCPD_CR_CC1VCONNEN UCPD_CR_CC1VCONNEN_Msk /*!< VCONN enable for CC1 */ +#define UCPD_CR_DBATEN_Pos (15U) +#define UCPD_CR_DBATEN_Msk (0x1UL << UCPD_CR_DBATEN_Pos) /*!< 0x00008000 */ +#define UCPD_CR_DBATEN UCPD_CR_DBATEN_Msk /*!< Enable dead battery behavior (Active High) */ +#define UCPD_CR_FRSRXEN_Pos (16U) +#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */ +#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */ +#define UCPD_CR_FRSTX_Pos (17U) +#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */ +#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */ +#define UCPD_CR_RDCH_Pos (18U) +#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */ +#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */ +#define UCPD_CR_RPUSBABSENT_Pos (19U) +#define UCPD_CR_RPUSBABSENT_Msk (0x1UL << UCPD_CR_RPUSBABSENT_Pos) /*!< 0x00080000 */ +#define UCPD_CR_RPUSBABSENT UCPD_CR_RPUSBABSENT_Msk /*!< */ +#define UCPD_CR_CC1TCDIS_Pos (20U) +#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */ +#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */ +#define UCPD_CR_CC2TCDIS_Pos (21U) +#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */ +#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */ + +/******************** Bits definition for UCPD_IMR register *******************/ +#define UCPD_IMR_TXISIE_Pos (0U) +#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */ +#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */ +#define UCPD_IMR_TXMSGDISCIE_Pos (1U) +#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */ +#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */ +#define UCPD_IMR_TXMSGSENTIE_Pos (2U) +#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */ +#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */ +#define UCPD_IMR_TXMSGABTIE_Pos (3U) +#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */ +#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */ +#define UCPD_IMR_HRSTDISCIE_Pos (4U) +#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */ +#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */ +#define UCPD_IMR_HRSTSENTIE_Pos (5U) +#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */ +#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */ +#define UCPD_IMR_TXUNDIE_Pos (6U) +#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */ +#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */ +#define UCPD_IMR_RXNEIE_Pos (8U) +#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */ +#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */ +#define UCPD_IMR_RXORDDETIE_Pos (9U) +#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */ +#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */ +#define UCPD_IMR_RXHRSTDETIE_Pos (10U) +#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */ +#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */ +#define UCPD_IMR_RXOVRIE_Pos (11U) +#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */ +#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */ +#define UCPD_IMR_RXMSGENDIE_Pos (12U) +#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */ +#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */ +#define UCPD_IMR_TYPECEVT1IE_Pos (14U) +#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */ +#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */ +#define UCPD_IMR_TYPECEVT2IE_Pos (15U) +#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */ +#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */ +#define UCPD_IMR_FRSEVTIE_Pos (20U) +#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */ +#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */ + +/******************** Bits definition for UCPD_SR register ********************/ +#define UCPD_SR_TXIS_Pos (0U) +#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */ +#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */ +#define UCPD_SR_TXMSGDISC_Pos (1U) +#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */ +#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */ +#define UCPD_SR_TXMSGSENT_Pos (2U) +#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */ +#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */ +#define UCPD_SR_TXMSGABT_Pos (3U) +#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */ +#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */ +#define UCPD_SR_HRSTDISC_Pos (4U) +#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */ +#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */ +#define UCPD_SR_HRSTSENT_Pos (5U) +#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */ +#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */ +#define UCPD_SR_TXUND_Pos (6U) +#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */ +#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */ +#define UCPD_SR_RXNE_Pos (8U) +#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */ +#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */ +#define UCPD_SR_RXORDDET_Pos (9U) +#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */ +#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */ +#define UCPD_SR_RXHRSTDET_Pos (10U) +#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */ +#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */ +#define UCPD_SR_RXOVR_Pos (11U) +#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */ +#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */ +#define UCPD_SR_RXMSGEND_Pos (12U) +#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */ +#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */ +#define UCPD_SR_RXERR_Pos (13U) +#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */ +#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */ +#define UCPD_SR_TYPECEVT1_Pos (14U) +#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */ +#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */ +#define UCPD_SR_TYPECEVT2_Pos (15U) +#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */ +#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U) +#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */ +#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U) +#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/** @addtogroup STM32H5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)|| \ + ((INSTANCE) == ADC2_NS)|| \ + ((INSTANCE) == ADC2_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S)) +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ + ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ + ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ + ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ + ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* DTS Instances *******************************/ +#define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On H5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On H5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************** I3C Instances *******************************/ +#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S) || \ + ((INSTANCE) == I3C2_NS) || ((INSTANCE) == I3C2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) + +/****************************** FDCAN Instances *******************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \ + ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ + ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM12_NS) || ((__INSTANCE__) == TIM12_S)|| \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** CEC Instance *****************************************/ +#define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32H523xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H523xx_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h new file mode 100644 index 0000000000..0ca641531c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h @@ -0,0 +1,20776 @@ +/** + ****************************************************************************** + * @file stm32h533xx.h + * @author MCD Application Team + * @brief CMSIS STM32H533xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H533xx_H +#define STM32H533xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H533xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H533xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ + IWDG_IRQn = 35, /*!< IWDG global interrupt */ + SAES_IRQn = 36, /*!< Secure AES global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 55, /*!< SPI1 global interrupt */ + SPI2_IRQn = 56, /*!< SPI2 global interrupt */ + SPI3_IRQn = 57, /*!< SPI3 global interrupt */ + USART1_IRQn = 58, /*!< USART1 global interrupt */ + USART2_IRQn = 59, /*!< USART2 global interrupt */ + USART3_IRQn = 60, /*!< USART3 global interrupt */ + UART4_IRQn = 61, /*!< UART4 global interrupt */ + UART5_IRQn = 62, /*!< UART5 global interrupt */ + LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ + TIM8_BRK_IRQn = 65, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 66, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 67, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 68, /*!< TIM8 Capture Compare interrupt */ + ADC2_IRQn = 69, /*!< ADC2 global interrupt */ + LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 71, /*!< TIM15 global interrupt */ + USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + UCPD1_IRQn = 76, /*!< UCPD1 global interrupt */ + FMC_IRQn = 77, /*!< FMC global interrupt */ + OCTOSPI1_IRQn = 78, /*!< OctoSPI1 global interrupt */ + SDMMC1_IRQn = 79, /*!< SDMMC1 global interrupt */ + I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ + SPI4_IRQn = 82, /*!< SPI4 global interrupt */ + USART6_IRQn = 85, /*!< USART6 global interrupt */ + GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ + GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ + GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ + GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ + GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ + GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ + GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ + GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ + FPU_IRQn = 103, /*!< FPU global interrupt */ + ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ + DCACHE1_IRQn = 105, /*!< Data cache global interrupt */ + DCMI_PSSI_IRQn = 108, /*!< DCMI/PSSI global interrupt */ + FDCAN2_IT0_IRQn = 109, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 110, /*!< FDCAN2 interrupt 1 */ + DTS_IRQn = 113, /*!< DTS global interrupt */ + RNG_IRQn = 114, /*!< RNG global interrupt */ + OTFDEC1_IRQn = 115, /*!< OTFDEC1 global interrupt */ + AES_IRQn = 116, /*!< AES global interrupt */ + HASH_IRQn = 117, /*!< HASH global interrupt */ + PKA_IRQn = 118, /*!< PKA global interrupt */ + CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ + TIM12_IRQn = 120, /*!< TIM12 global interrupt */ + I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ + I3C2_EV_IRQn = 131, /*!< I3C2 Event interrupt */ + I3C2_ER_IRQn = 132, /*!< I3C2 Error interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ + __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ + __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ + __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ + __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ + __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ + __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ + uint32_t RESERVED6[7]; /*!< Reserved6, Address offset: 0xA4-0xBF */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xC4-0xDC */ + __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ + __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ + __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ + uint32_t RESERVED9[7]; /*!< Reserved9, Address offset: 0x1A4-0x1BF */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + uint32_t RESERVED10[7]; /*!< Reserved10, Address offset: 0x1C4-0x1DC */ + __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ + __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ + __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ + __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ + __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ + __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + __IO uint32_t WPR3; /*!< SRAM Write Protection Register 3, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< RCC PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ + __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ + uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ + __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ + __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + uint32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */ + __IO uint32_t IPVER; /*!< UCPD IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPID; /*!< UCPD IP Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< UCPD Magic Identification register, Address offset: 0x3FC */ +} UCPD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ + +#define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ +#define SRAM2_SIZE (0x14000UL) /*!< SRAM2=80k */ +#define SRAM3_SIZE (0x10000UL) /*!< SRAM3=64k */ +#define BKPSRAM_SIZE (0x00800UL) /*!< BKPSRAM=2k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 512 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (128 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20020000UL) /*!< SRAM2 (80 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20034000UL) /*!< SRAM3 (64 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ +#define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ +#define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ + + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) + +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define I3C2_BASE_NS (APB3PERIPH_BASE_NS + 0x3000UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +/*!< AHB4 Non secure peripherals */ +#define OTFDEC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) + +#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 512 KB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (128 KB) secure base address */ +#define SRAM2_BASE_S (0x30020000UL) /*!< SRAM2 (80 KB) secure base address */ +#define SRAM3_BASE_S (0x30034000UL) /*!< SRAM3 (64 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) +#define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) +#define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) +#define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) +#define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) +#define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) +#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) +#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) +#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB3 secure peripherals */ +#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define I3C2_BASE_S (APB3PERIPH_BASE_S + 0x3000UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB3 secure peripherals */ +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) + +/*!< AHB4 secure peripherals */ +#define OTFDEC1_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) +#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) + +#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) + +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ + +/* Internal Flash EDATA Area */ +#define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ +#define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ +#define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ + +/* Internal Flash OBK Area */ +#define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ +#define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ +#define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ +#define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ +#define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ +#define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ +#define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ +#define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ + +#define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ + +#define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ +#endif /* CMSE */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB84UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0xBF9FB68UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it jumps to the non-secure reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; +} S_pFuncTypeDef; + +/** + * @brief RSSLib Non-secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; +} NSC_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + uint32_t RESERVED1[3]; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB6CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB74UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0xBF9FB6CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + +/* + * Certificate address description + */ +#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U) +#define CERT_CHIP_PACK1_SIZE (0x200U) +#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U) +#define CERT_CHIP_PACK2_SIZE (0x200U) + +#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) +#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) + +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET (152U) +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET (216U) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET (484U) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET) + +#define CERT_ST_DUA_USER_PUB_KEY_OFFSET (12U) +#define CERT_ST_DUA_USER_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_SIGN_OFFSET (76U) +#define CERT_ST_DUA_USER_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SIGN_OFFSET) +#define CERT_ST_DUA_USER_SERIAL_OFFSET (140U) +#define CERT_ST_DUA_USER_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SERIAL_OFFSET) + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *)TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *)TIM14_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) +#define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + +/*!< AHB4 Non secure peripherals */ +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) + +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) +#define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) +#define USART2_S ((USART_TypeDef *)USART2_BASE_S) +#define USART3_S ((USART_TypeDef *)USART3_BASE_S) +#define UART4_S ((USART_TypeDef *)UART4_BASE_S) +#define UART5_S ((USART_TypeDef *)UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) +#define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) +#define CRS_S ((CRS_TypeDef *)CRS_BASE_S) +#define USART6_S ((USART_TypeDef *)USART6_BASE_S) +#define CEC_S ((CEC_TypeDef *)CEC_BASE_S) +#define DTS_S ((DTS_TypeDef *)DTS_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) + +/*!< APB2 secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) +#define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) +#define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) +#define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) +#define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) +#define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) +#define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) +#define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) + + +/*!< AHB2 secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) + +/*!< APB3 secure peripherals */ +#define SBS_S ((SBS_TypeDef *) SBS_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) + +/*!< AHB4 secure peripherals */ +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) + +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) + +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define FLASH_OBK_BASE FLASH_OBK_BASE_S +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_S +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define APB3PERIPH_BASE APB3PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA2 GPDMA2_S +#define GPDMA2_BASE GPDMA2_BASE_S + +#define GPDMA2_Channel0 GPDMA2_Channel0_S +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S + +#define GPDMA2_Channel1 GPDMA2_Channel1_S +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S + +#define GPDMA2_Channel2 GPDMA2_Channel2_S +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S + +#define GPDMA2_Channel3 GPDMA2_Channel3_S +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S + +#define GPDMA2_Channel4 GPDMA2_Channel4_S +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S + +#define GPDMA2_Channel5 GPDMA2_Channel5_S +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S + +#define GPDMA2_Channel6 GPDMA2_Channel6_S +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S + +#define GPDMA2_Channel7 GPDMA2_Channel7_S +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define CEC CEC_S +#define CEC_BASE CEC_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SBS SBS_S +#define SBS_BASE SBS_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + + + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#else + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_OBK_BASE FLASH_OBK_BASE_NS +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS + +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +#define SRAM3_BASE SRAM3_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define CEC CEC_NS +#define CEC_BASE CEC_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + + + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#endif + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ +#define ADC_OR_OP1_Pos (1U) +#define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OBKERR_Pos (21U) +#define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ +#define FLASH_SR_OBKWERR_Pos (22U) +#define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OBKERRIE_Pos (21U) +#define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ +#define FLASH_CR_OBKWERRIE_Pos (22U) +#define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OBKERR_Pos (21U) +#define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ +#define FLASH_CCR_CLR_OBKWERR_Pos (22U) +#define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/****************** Bits definition for FLASH_OBKCFGR register *****************/ +#define FLASH_OBKCFGR_LOCK_Pos (0U) +#define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ +#define FLASH_OBKCFGR_ALT_SECT_Pos (2U) +#define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ +#define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ +#define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) +#define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ +#define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_BOOT_UBE_Pos (22U) +#define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ +#define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) +#define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ +#define FLASH_OPTSR2_TZEN_Pos (24U) +#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ +#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + +/***************** Bits definition for FLASH_SECWMR register ********************/ +#define FLASH_SECWMR_SECWM_STRT_Pos (0U) +#define FLASH_SECWMR_SECWM_STRT_Msk (0x1FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ +#define FLASH_SECWMR_SECWM_END_Pos (16U) +#define FLASH_SECWMR_SECWM_END_Msk (0x1FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0x000000FFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x000000FF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + +/***************** Bits definition for FLASH_EDATA register ********************/ +#define FLASH_EDATAR_EDATA_STRT_Pos (0U) +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ +#define FLASH_EDATAR_EDATA_EN_Pos (15U) +#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ +#define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x1FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x1FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x001F0000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_OBK_ECC_Pos (20U) +#define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ +#define FLASH_ECCR_DATA_ECC_Pos (21U) +#define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_OR register ******************/ +#define RTC_OR_OUT2_RMP_Pos (0U) +#define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP4MF_Pos (19U) +#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk +#define TAMP_SMISR_ITAMP15MF_Pos (30U) +#define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + +/******************** Bits definition for TAMP_OR register ***************/ +#define TAMP_OR_OUT3_RMP_Pos (1U) +#define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ +#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk +#define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ +#define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ +#define TAMP_OR_OUT5_RMP_Pos (3U) +#define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk +#define TAMP_OR_IN2_RMP_Pos (8U) +#define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk +#define TAMP_OR_IN3_RMP_Pos (9U) +#define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk +#define TAMP_OR_IN4_RMP_Pos (10U) +#define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* SBS */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SBS_HDPLCR register *****************/ +#define SBS_HDPLCR_INCR_HDPL_Pos (0U) +#define SBS_HDPLCR_INCR_HDPL_Msk (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLCR_INCR_HDPL SBS_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL value. */ + +/******************** Bit definition for SBS_HDPLSR register *****************/ +#define SBS_HDPLSR_HDPL_Pos (0U) +#define SBS_HDPLSR_HDPL_Msk (0xFFUL << SBS_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLSR_HDPL SBS_HDPLSR_HDPL_Msk /*!< HDPL value. */ + +/******************** Bit definition for SBS_NEXTHDPLCR register *****************/ +#define SBS_NEXTHDPLCR_NEXTHDPL_Pos (0U) +#define SBS_NEXTHDPLCR_NEXTHDPL_Msk (0x3UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000003 */ +#define SBS_NEXTHDPLCR_NEXTHDPL SBS_NEXTHDPLCR_NEXTHDPL_Msk /*!< NEXTHDPL value. */ +#define SBS_NEXTHDPLCR_NEXTHDPL_0 (0x1UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000001 */ +#define SBS_NEXTHDPLCR_NEXTHDPL_1 (0x2UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000002 */ + +/******************** Bit definition for SBS_DBGCR register *****************/ +#define SBS_DBGCR_AP_UNLOCK_Pos (0U) +#define SBS_DBGCR_AP_UNLOCK_Msk (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGCR_AP_UNLOCK SBS_DBGCR_AP_UNLOCK_Msk /*!< Open the Access Port. */ + +#define SBS_DBGCR_DBG_UNLOCK_Pos (8U) +#define SBS_DBGCR_DBG_UNLOCK_Msk (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define SBS_DBGCR_DBG_UNLOCK SBS_DBGCR_DBG_UNLOCK_Msk /*!< Open the debug when DBG_AUTH_HDPL is reached. */ + +#define SBS_DBGCR_DBG_AUTH_HDPL_Pos (16U) +#define SBS_DBGCR_DBG_AUTH_HDPL_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define SBS_DBGCR_DBG_AUTH_HDPL SBS_DBGCR_DBG_AUTH_HDPL_Msk /*!< HDPL value when the debug should be effectively opened. */ + +#define SBS_DBGCR_DBG_AUTH_SEC_Pos (24U) +#define SBS_DBGCR_DBG_AUTH_SEC_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-secured and secured debugs. */ + +/******************** Bit definition for SBS_DBGLCKR register *****************/ +#define SBS_DBGLOCKR_DBGCFG_LOCK_Pos (0U) +#define SBS_DBGLOCKR_DBGCFG_LOCK_Msk (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGLOCKR_DBGCFG_LOCK SBS_DBGLOCKR_DBGCFG_LOCK_Msk /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */ + +/******************** Bit definition for SBS_RSSCMDR register ***************/ +#define SBS_RSSCMDR_RSSCMD_Pos (0U) +#define SBS_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SBS_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ +#define SBS_RSSCMDR_RSSCMD SBS_RSSCMDR_RSSCMD_Msk /*!< command to be executed by the RSS. */ + +/******************** Bit definition for SBS_EPOCHSELCR register ************/ +#define SBS_EPOCHSELCR_EPOCH_SEL_Pos (0U) +#define SBS_EPOCHSELCR_EPOCH_SEL_Msk (0x3UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000003 */ +#define SBS_EPOCHSELCR_EPOCH_SEL SBS_EPOCHSELCR_EPOCH_SEL_Msk /*!< Select EPOCH sent to SAES IP to encrypt/decrypt keys */ +#define SBS_EPOCHSELCR_EPOCH_SEL_0 (0x1UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000001 */ +#define SBS_EPOCHSELCR_EPOCH_SEL_1 (0x2UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000002 */ + +/****************** Bit definition for SBS_PMCR register ****************/ +#define SBS_PMCR_PB6_FMP_Pos (16U) +#define SBS_PMCR_PB6_FMP_Msk (0x1UL << SBS_PMCR_PB6_FMP_Pos) /*!< 0x00010000 */ +#define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode Plus command on PB(6) */ +#define SBS_PMCR_PB7_FMP_Pos (17U) +#define SBS_PMCR_PB7_FMP_Msk (0x1UL << SBS_PMCR_PB7_FMP_Pos) /*!< 0x00020000 */ +#define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode Plus command on PB(7) */ +#define SBS_PMCR_PB8_FMP_Pos (18U) +#define SBS_PMCR_PB8_FMP_Msk (0x1UL << SBS_PMCR_PB8_FMP_Pos) /*!< 0x00040000 */ +#define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode Plus command on PB(8) */ +#define SBS_PMCR_PB9_FMP_Pos (19U) +#define SBS_PMCR_PB9_FMP_Msk (0x1UL << SBS_PMCR_PB9_FMP_Pos) /*!< 0x00080000 */ +#define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode Plus command on PB(9) */ + +/****************** Bit definition for SBS_FPUIMR register ***************/ +#define SBS_FPUIMR_FPU_IE_Pos (0U) +#define SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */ +#define SBS_FPUIMR_FPU_IE SBS_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */ +#define SBS_FPUIMR_FPU_IE_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_1 (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */ + +/****************** Bit definition for SBS_MESR register ****************/ +#define SBS_MESR_MCLR_Pos (0U) +#define SBS_MESR_MCLR_Msk (0x1UL << SBS_MESR_MCLR_Pos) /*!< 0x00000001 */ +#define SBS_MESR_MCLR SBS_MESR_MCLR_Msk /*!< Status of Erase after Reset */ +#define SBS_MESR_IPMEE_Pos (16U) +#define SBS_MESR_IPMEE_Msk (0x1UL << SBS_MESR_IPMEE_Pos) /*!< 0x00010000 */ +#define SBS_MESR_IPMEE SBS_MESR_IPMEE_Msk /*!< Status of End of Erase for ICache and PKA RAMs */ + +/****************** Bit definition for SBS_CCCSR register ****************/ +#define SBS_CCCSR_EN1_Pos (0U) +#define SBS_CCCSR_EN1_Msk (0x1UL << SBS_CCCSR_EN1_Pos) /*!< 0x00000001 */ +#define SBS_CCCSR_EN1 SBS_CCCSR_EN1_Msk /*!< Enable compensation cell for VDD power rail */ +#define SBS_CCCSR_CS1_Pos (1U) +#define SBS_CCCSR_CS1_Msk (0x1UL << SBS_CCCSR_CS1_Pos) /*!< 0x00000002 */ +#define SBS_CCCSR_CS1 SBS_CCCSR_CS1_Msk /*!< Code selection for VDD power rail */ +#define SBS_CCCSR_EN2_Pos (2U) +#define SBS_CCCSR_EN2_Msk (0x1UL << SBS_CCCSR_EN2_Pos) /*!< 0x00000004 */ +#define SBS_CCCSR_EN2 SBS_CCCSR_EN2_Msk /*!< Enable compensation cell for VDDIO power rail */ +#define SBS_CCCSR_CS2_Pos (3U) +#define SBS_CCCSR_CS2_Msk (0x1UL << SBS_CCCSR_CS2_Pos) /*!< 0x00000008 */ +#define SBS_CCCSR_CS2 SBS_CCCSR_CS2_Msk /*!< Code selection for VDDIO power rail */ +#define SBS_CCCSR_RDY1_Pos (8U) +#define SBS_CCCSR_RDY1_Msk (0x1UL << SBS_CCCSR_RDY1_Pos) /*!< 0x00000100 */ +#define SBS_CCCSR_RDY1 SBS_CCCSR_RDY1_Msk /*!< VDD compensation cell ready flag */ +#define SBS_CCCSR_RDY2_Pos (9U) +#define SBS_CCCSR_RDY2_Msk (0x1UL << SBS_CCCSR_RDY2_Pos) /*!< 0x00000200 */ +#define SBS_CCCSR_RDY2 SBS_CCCSR_RDY2_Msk /*!< VDDIO compensation cell ready flag */ + +/****************** Bit definition for SBS_CCVALR register ****************/ +#define SBS_CCVALR_ANSRC1_Pos (0U) +#define SBS_CCVALR_ANSRC1_Msk (0xFUL << SBS_CCVALR_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCVALR_ANSRC1 SBS_CCVALR_ANSRC1_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC1_Pos (4U) +#define SBS_CCVALR_APSRC1_Msk (0xFUL << SBS_CCVALR_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCVALR_APSRC1 SBS_CCVALR_APSRC1_Msk /*!< PMOS compensation value */ +#define SBS_CCVALR_ANSRC2_Pos (8U) +#define SBS_CCVALR_ANSRC2_Msk (0xFUL << SBS_CCVALR_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCVALR_ANSRC2 SBS_CCVALR_ANSRC2_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC2_Pos (12U) +#define SBS_CCVALR_APSRC2_Msk (0xFUL << SBS_CCVALR_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCVALR_APSRC2 SBS_CCVALR_APSRC2_Msk /*!< PMOS compensation value */ + +/****************** Bit definition for SBS_CCSWCR register ****************/ +#define SBS_CCSWCR_SW_ANSRC1_Pos (0U) +#define SBS_CCSWCR_SW_ANSRC1_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCSWCR_SW_ANSRC1 SBS_CCSWCR_SW_ANSRC1_Msk /*!< NMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_APSRC1_Pos (4U) +#define SBS_CCSWCR_SW_APSRC1_Msk (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCSWCR_SW_APSRC1 SBS_CCSWCR_SW_APSRC1_Msk /*!< PMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_ANSRC2_Pos (8U) +#define SBS_CCSWCR_SW_ANSRC2_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCSWCR_SW_ANSRC2 SBS_CCSWCR_SW_ANSRC2_Msk /*!< NMOS compensation code for VDDIO Power Rail */ +#define SBS_CCSWCR_SW_APSRC2_Pos (12U) +#define SBS_CCSWCR_SW_APSRC2_Msk (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCSWCR_SW_APSRC2 SBS_CCSWCR_SW_APSRC2_Msk /*!< PMOS compensation code for VDDIO Power Rail */ + +/****************** Bit definition for SBS_CFGR2 register ****************/ +#define SBS_CFGR2_CLL_Pos (0U) +#define SBS_CFGR2_CLL_Msk (0x1UL << SBS_CFGR2_CLL_Pos) /*!< 0x00000001 */ +#define SBS_CFGR2_CLL SBS_CFGR2_CLL_Msk /*!< Core Lockup Lock */ +#define SBS_CFGR2_SEL_Pos (1U) +#define SBS_CFGR2_SEL_Msk (0x1UL << SBS_CFGR2_SEL_Pos) /*!< 0x00000002 */ +#define SBS_CFGR2_SEL SBS_CFGR2_SEL_Msk /*!< SRAM ECC Lock */ +#define SBS_CFGR2_PVDL_Pos (2U) +#define SBS_CFGR2_PVDL_Msk (0x1UL << SBS_CFGR2_PVDL_Pos) /*!< 0x00000004 */ +#define SBS_CFGR2_PVDL SBS_CFGR2_PVDL_Msk /*!< PVD Lock */ +#define SBS_CFGR2_ECCL_Pos (3U) +#define SBS_CFGR2_ECCL_Msk (0x1UL << SBS_CFGR2_ECCL_Pos) /*!< 0x00000008 */ +#define SBS_CFGR2_ECCL SBS_CFGR2_ECCL_Msk /*!< Flash ECC Lock*/ + +/******************** Bit definition for SBS_SECCFGR register ***************/ +#define SBS_SECCFGR_SBSSEC_Pos (0U) +#define SBS_SECCFGR_SBSSEC_Msk (0x1UL << SBS_SECCFGR_SBSSEC_Pos) /*!< 0x00000001 */ +#define SBS_SECCFGR_SBSSEC SBS_SECCFGR_SBSSEC_Msk /*!< SBS clock control security enable */ +#define SBS_SECCFGR_CLASSBSEC_Pos (1U) +#define SBS_SECCFGR_CLASSBSEC_Msk (0x1UL << SBS_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */ +#define SBS_SECCFGR_CLASSBSEC SBS_SECCFGR_CLASSBSEC_Msk /*!< ClassB SBS security enable */ +#define SBS_SECCFGR_FPUSEC_Pos (3U) +#define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */ +#define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */ + +/****************** Bit definition for SBS_CNSLCKR register **************/ +#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U) +#define SBS_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */ +#define SBS_CNSLCKR_LOCKNSVTOR SBS_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */ +#define SBS_CNSLCKR_LOCKNSMPU_Pos (1U) +#define SBS_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */ + +/****************** Bit definition for SBS_CSLCKR register ***************/ +#define SBS_CSLCKR_LOCKSVTAIRCR_Pos (0U) +#define SBS_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SBS_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */ +#define SBS_CSLCKR_LOCKSVTAIRCR SBS_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */ +#define SBS_CSLCKR_LOCKSMPU_Pos (1U) +#define SBS_CSLCKR_LOCKSMPU_Msk (0x1UL << SBS_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CSLCKR_LOCKSMPU SBS_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */ +#define SBS_CSLCKR_LOCKSAU_Pos (2U) +#define SBS_CSLCKR_LOCKSAU_Msk (0x1UL << SBS_CSLCKR_LOCKSAU_Pos) /*!< 0x00000004 */ +#define SBS_CSLCKR_LOCKSAU SBS_CSLCKR_LOCKSAU_Msk /*!< Disable changes to SAU registers */ + +/****************** Bit definition for SBS_ECCNMIR register ***************/ +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos (0U) +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos) /*!< 0x00000001 */ +#define SBS_ECCNMIR_ECCNMI_MASK_EN SBS_ECCNMIR_ECCNMI_MASK_EN_Msk /*!< Disable NMI in case of double ECC error in flash interface */ + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ + +/******************* Bits definition for GTZC_TZSC_MPCWM_CFGR register **********/ +#define GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) +#define GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk +#define GTZC_TZSC_MPCWM_CFGR_SEC_Pos (8U) +#define GTZC_TZSC_MPCWM_CFGR_SEC_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SEC GTZC_TZSC_MPCWM_CFGR_SEC_Msk +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) +#define GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk + +/******************* Bits definition for GTZC_TZSC_MPCWMR register **************/ +#define GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) +#define GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk + +/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/ + +/*************** Bits definition for register x=1 (TZSC1) *************/ +#define GTZC_CFGR1_TIM2_Pos (0U) +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos (1U) +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_TIM4_Pos (2U) +#define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) +#define GTZC_CFGR1_TIM5_Pos (3U) +#define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos) +#define GTZC_CFGR1_TIM6_Pos (4U) +#define GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) +#define GTZC_CFGR1_TIM7_Pos (5U) +#define GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) +#define GTZC_CFGR1_TIM12_Pos (6U) +#define GTZC_CFGR1_TIM12_Msk (0x01UL << GTZC_CFGR1_TIM12_Pos) +#define GTZC_CFGR1_WWDG_Pos (9U) +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos (10U) +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_SPI2_Pos (11U) +#define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) +#define GTZC_CFGR1_SPI3_Pos (12U) +#define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) +#define GTZC_CFGR1_USART2_Pos (13U) +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_USART3_Pos (14U) +#define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) +#define GTZC_CFGR1_UART4_Pos (15U) +#define GTZC_CFGR1_UART4_Msk (0x01UL << GTZC_CFGR1_UART4_Pos) +#define GTZC_CFGR1_UART5_Pos (16U) +#define GTZC_CFGR1_UART5_Msk (0x01UL << GTZC_CFGR1_UART5_Pos) +#define GTZC_CFGR1_I2C1_Pos (17U) +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_I2C2_Pos (18U) +#define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) +#define GTZC_CFGR1_I3C1_Pos (19U) +#define GTZC_CFGR1_I3C1_Msk (0x01UL << GTZC_CFGR1_I3C1_Pos) +#define GTZC_CFGR1_CRS_Pos (20U) +#define GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) +#define GTZC_CFGR1_USART6_Pos (21U) +#define GTZC_CFGR1_USART6_Msk (0x01UL << GTZC_CFGR1_USART6_Pos) +#define GTZC_CFGR1_HDMICEC_Pos (24U) +#define GTZC_CFGR1_HDMICEC_Msk (0x01UL << GTZC_CFGR1_HDMICEC_Pos) +#define GTZC_CFGR1_DAC1_Pos (25U) +#define GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) +#define GTZC_CFGR1_DTS_Pos (30U) +#define GTZC_CFGR1_DTS_Msk (0x01UL << GTZC_CFGR1_DTS_Pos) +#define GTZC_CFGR1_LPTIM2_Pos (31U) +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/*************** Bits definition for register x=2 (TZSC1) *************/ +#define GTZC_CFGR2_FDCAN1_Pos (0U) +#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos) +#define GTZC_CFGR2_FDCAN2_Pos (1U) +#define GTZC_CFGR2_FDCAN2_Msk (0x01UL << GTZC_CFGR2_FDCAN2_Pos) +#define GTZC_CFGR2_UCPD1_Pos (2U) +#define GTZC_CFGR2_UCPD1_Msk (0x01UL << GTZC_CFGR2_UCPD1_Pos) +#define GTZC_CFGR2_TIM1_Pos (8U) +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos (9U) +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_TIM8_Pos (10U) +#define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos) +#define GTZC_CFGR2_USART1_Pos (11U) +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM15_Pos (12U) +#define GTZC_CFGR2_TIM15_Msk (0x01UL << GTZC_CFGR2_TIM15_Pos) +#define GTZC_CFGR2_SPI4_Pos (15U) +#define GTZC_CFGR2_SPI4_Msk (0x01UL << GTZC_CFGR2_SPI4_Pos) +#define GTZC_CFGR2_USB_Pos (19U) +#define GTZC_CFGR2_USB_Msk (0x01UL << GTZC_CFGR2_USB_Pos) +#define GTZC_CFGR2_LPUART1_Pos (25U) +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos (26U) +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos (28U) +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) + +/*************** Bits definition for register x=3 (TZSC1) *************/ +#define GTZC_CFGR3_VREFBUF_Pos (1U) +#define GTZC_CFGR3_VREFBUF_Msk (0x01UL << GTZC_CFGR3_VREFBUF_Pos) +#define GTZC_CFGR3_I3C2_Pos (2U) +#define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) +#define GTZC_CFGR3_CRC_Pos (8U) +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos (12U) +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_DCACHE1_REG_Pos (13U) +#define GTZC_CFGR3_DCACHE1_REG_Msk (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos) +#define GTZC_CFGR3_ADC_Pos (14U) +#define GTZC_CFGR3_ADC_Msk (0x01UL << GTZC_CFGR3_ADC_Pos) +#define GTZC_CFGR3_DCMI_PSSI_Pos (15U) +#define GTZC_CFGR3_DCMI_PSSI_Msk (0x01UL << GTZC_CFGR3_DCMI_PSSI_Pos) +#define GTZC_CFGR3_AES_Pos (16U) +#define GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) +#define GTZC_CFGR3_HASH_Pos (17U) +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos (18U) +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_SAES_Pos (19U) +#define GTZC_CFGR3_SAES_Msk (0x01UL << GTZC_CFGR3_SAES_Pos) +#define GTZC_CFGR3_PKA_Pos (20U) +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_SDMMC1_Pos (21U) +#define GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos) +#define GTZC_CFGR3_FMC_REG_Pos (23U) +#define GTZC_CFGR3_FMC_REG_Msk (0x01UL << GTZC_CFGR3_FMC_REG_Pos) +#define GTZC_CFGR3_OCTOSPI1_Pos (24U) +#define GTZC_CFGR3_OCTOSPI1_Msk (0x01UL << GTZC_CFGR3_OCTOSPI1_Pos) +#define GTZC_CFGR3_RAMCFG_Pos (26U) +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) + +/*************** Bits definition for register x=4 (TZSC1) *************/ +#define GTZC_CFGR4_GPDMA1_Pos (0U) +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_GPDMA2_Pos (1U) +#define GTZC_CFGR4_GPDMA2_Msk (0x01UL << GTZC_CFGR4_GPDMA2_Pos) +#define GTZC_CFGR4_FLASH_Pos (2U) +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos (3U) +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) + +#define GTZC_CFGR4_OTFDEC1_Pos (4U) +#define GTZC_CFGR4_OTFDEC1_Msk (0x01UL << GTZC_CFGR4_OTFDEC1_Pos) +#define GTZC_CFGR4_SBS_Pos (6U) +#define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos) +#define GTZC_CFGR4_RTC_Pos (7U) +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos (8U) +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos (9U) +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos (10U) +#define GTZC_CFGR4_RCC_Msk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos (11U) +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_TZSC_Pos (16U) +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos (17U) +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_OCTOSPI1_MEM_Pos (18U) +#define GTZC_CFGR4_OCTOSPI1_MEM_Msk (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos) +#define GTZC_CFGR4_FMC_MEM_Pos (19U) +#define GTZC_CFGR4_FMC_MEM_Msk (0x01UL << GTZC_CFGR4_FMC_MEM_Pos) +#define GTZC_CFGR4_BKPSRAM_Pos (20U) +#define GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) +#define GTZC_CFGR4_SRAM1_Pos (24U) +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos (25U) +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos (26U) +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos (27U) +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM3_Pos (28U) +#define GTZC_CFGR4_SRAM3_Msk (0x01UL << GTZC_CFGR4_SRAM3_Pos) +#define GTZC_CFGR4_MPCBB3_REG_Pos (29U) +#define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) + +/******************* Bits definition for GTZC_TZSC1_SECCFGR1 register ***************/ +#define GTZC_TZSC1_SECCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_SECCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_SECCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_SECCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_SECCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_SECCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_SECCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_SECCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_SECCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_SECCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_SECCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_SECCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_SECCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_SECCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_SECCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_SECCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_SECCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_SECCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_SECCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_SECCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_SECCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_SECCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_SECCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_SECCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_SECCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_SECCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_SECCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_SECCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_SECCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_SECCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_SECCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_SECCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_SECCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_SECCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_SECCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_SECCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_SECCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_SECCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_SECCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_SECCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_SECCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_SECCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_SECCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_SECCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_SECCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_SECCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_SECCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_SECCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_SECCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_SECCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_SECCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_SECCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_SECCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_SECCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_SECCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_SECCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_SECCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_SECCFGR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZSC1_SECCFGR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_SECCFGR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZSC1_SECCFGR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZSC1_SECCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_SECCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_PRIVCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_PRIVCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_PRIVCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_PRIVCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_PRIVCFGR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZSC1_PRIVCFGR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_PRIVCFGR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZSC1_PRIVCFGR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC1_IER1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_IER1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_IER1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_IER1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_IER1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_IER1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_IER1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_IER1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_IER1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_IER1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_IER1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_IER1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_IER1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_IER1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_IER1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_IER1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_IER1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_IER1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_IER1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_IER1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_IER1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_IER1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_IER1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_IER1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_IER1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_IER1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_IER1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_IER1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_IER1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_IER1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_IER1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_IER1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_IER1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_IER1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_IER1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_IER1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_IER1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_IER1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_IER1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_IER1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_IER1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_IER1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC1_IER2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_IER2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_IER2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_IER2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_IER2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_IER2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_IER2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_IER2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_IER2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_IER2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_IER2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_IER2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_IER2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_IER2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_IER2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_IER2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_IER2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_IER2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC1_IER3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_IER3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_IER3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_IER3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_IER3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_IER3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_IER3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_IER3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_IER3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_IER3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_IER3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_IER3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_IER3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_IER3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_IER3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_IER3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_IER3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_IER3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_IER3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_IER3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_IER3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_IER3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC1_IER4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_IER4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_IER4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_IER4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_IER4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_IER4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_IER4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_IER4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_IER4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_IER4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_IER4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_IER4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_IER4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_IER4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_IER4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_IER4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_IER4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_IER4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_IER4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_IER4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_IER4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_IER4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_IER4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_IER4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_IER4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_IER4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_IER4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_IER4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_IER4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_IER4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_IER4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_IER4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_IER4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_IER4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_IER4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_IER4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_IER4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_IER4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC1_SR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_SR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_SR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_SR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_SR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_SR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_SR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_SR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_SR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_SR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_SR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_SR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_SR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_SR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_SR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_SR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_SR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_SR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_SR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_SR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_SR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_SR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_SR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_SR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_SR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_SR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_SR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_SR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_SR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_SR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_SR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_SR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_SR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_SR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_SR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_SR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_SR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_SR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_SR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_SR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_SR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_SR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC1_SR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_SR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_SR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_SR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_SR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_SR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_SR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_SR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_SR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_SR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_SR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_SR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_SR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_SR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_SR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_SR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_SR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_SR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC1_SR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_SR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_SR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_SR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_SR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_SR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_SR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_SR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_SR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_SR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_SR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_SR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_SR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_SR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_SR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_SR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_SR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_SR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_SR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_SR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_SR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_SR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_SR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_SR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC1_SR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_SR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_SR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_SR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_SR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_SR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_SR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_SR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_SR4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_SR4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_SR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_SR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_SR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_SR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_SR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_SR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_SR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_SR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_SR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_SR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_SR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_SR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_SR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_SR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_SR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_SR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_SR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_SR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_SR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_SR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_SR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_SR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_SR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_SR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_SR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_SR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_SR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_SR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC1_FCR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_FCR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_FCR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_FCR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_FCR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_FCR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_FCR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_FCR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_FCR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_FCR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_FCR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_FCR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_FCR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_FCR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_FCR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_FCR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_FCR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_FCR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_FCR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_FCR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_FCR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_FCR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_FCR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_FCR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_FCR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_FCR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_FCR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_FCR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_FCR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_FCR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_FCR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_FCR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_FCR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_FCR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_FCR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_FCR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_FCR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_FCR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_FCR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_FCR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_FCR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_FCR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_FCR2 register **************/ +#define GTZC_TZIC1_FCR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_FCR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_FCR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_FCR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_FCR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_FCR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_FCR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_FCR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_FCR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_FCR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_FCR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_FCR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_FCR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_FCR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_FCR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_FCR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_FCR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_FCR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC1_FCR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_FCR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_FCR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_FCR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_FCR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_FCR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_FCR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_FCR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_FCR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_FCR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_FCR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_FCR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_FCR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_FCR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_FCR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_FCR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_FCR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_FCR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_FCR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_FCR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_FCR4 register ***************/ +#define GTZC_TZIC1_FCR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_FCR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_FCR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_FCR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_FCR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_FCR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_FCR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_FCR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_FCR4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_FCR4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_FCR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_FCR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_FCR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_FCR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_FCR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_FCR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_FCR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_FCR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_FCR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_FCR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_FCR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_FCR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_FCR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_FCR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_FCR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_FCR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_FCR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_FCR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_FCR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_FCR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_FCR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_FCR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_FCR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_FCR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCKR1 register ************/ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos (4U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos (5U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos (6U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos (7U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos (8U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos (9U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos (10U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos (11U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos (12U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos (13U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos (14U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos (15U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos (16U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos (17U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos (18U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos (19U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos (20U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos (21U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos (22U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos (23U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos (24U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos (25U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos (26U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos (27U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos (28U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos (29U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos (30U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos (31U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */ + + +/******************************************************************************/ +/* */ +/* UCPD */ +/* */ +/******************************************************************************/ +/******************** Bits definition for UCPD_CFG1 register *******************/ +#define UCPD_CFG1_HBITCLKDIV_Pos (0U) +#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */ +#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */ +#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */ +#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */ +#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */ +#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */ +#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */ +#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */ +#define UCPD_CFG1_IFRGAP_Pos (6U) +#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */ +#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */ +#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */ +#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */ +#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */ +#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */ +#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */ +#define UCPD_CFG1_TRANSWIN_Pos (11U) +#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */ +#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */ +#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */ +#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */ +#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */ +#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */ +#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */ +#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U) +#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */ +#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */ +#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */ +#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */ +#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */ +#define UCPD_CFG1_RXORDSETEN_Pos (20U) +#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x1FF00000 */ +#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */ +#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00100000 */ +#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00200000 */ +#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00400000 */ +#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00800000 */ +#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x01000000 */ +#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x02000000 */ +#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x04000000 */ +#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x08000000 */ +#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x10000000 */ +#define UCPD_CFG1_TXDMAEN_Pos (29U) +#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */ +#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define UCPD_CFG1_RXDMAEN_Pos (30U) +#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */ +#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define UCPD_CFG1_UCPDEN_Pos (31U) +#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */ +#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */ + +/******************** Bits definition for UCPD_CFG2 register *******************/ +#define UCPD_CFG2_RXFILTDIS_Pos (0U) +#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */ +#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */ +#define UCPD_CFG2_RXFILT2N3_Pos (1U) +#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */ +#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */ +#define UCPD_CFG2_FORCECLK_Pos (2U) +#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */ +#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */ +#define UCPD_CFG2_WUPEN_Pos (3U) +#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */ +#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define UCPD_CFG2_RXAFILTEN_Pos (8U) +#define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */ +#define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< Rx analog filter enable */ + +/******************** Bits definition for UCPD_CFG3 register *******************/ +#define UCPD_CFG3_TRIM_CC1_RD_Pos (0U) +#define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */ +#define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */ +#define UCPD_CFG3_TRIM_CC1_RP_Pos (9U) +#define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */ +#define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */ +#define UCPD_CFG3_TRIM_CC2_RD_Pos (16U) +#define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */ +#define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */ +#define UCPD_CFG3_TRIM_CC2_RP_Pos (25U) +#define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */ +#define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */ + +/******************** Bits definition for UCPD_CR register ********************/ +#define UCPD_CR_TXMODE_Pos (0U) +#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ +#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */ +#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */ +#define UCPD_CR_TXSEND_Pos (2U) +#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */ +#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXHRST_Pos (3U) +#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */ +#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */ +#define UCPD_CR_RXMODE_Pos (4U) +#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */ +#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */ +#define UCPD_CR_PHYRXEN_Pos (5U) +#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */ +#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */ +#define UCPD_CR_PHYCCSEL_Pos (6U) +#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */ +#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */ +#define UCPD_CR_ANASUBMODE_Pos (7U) +#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */ +#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */ +#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */ +#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */ +#define UCPD_CR_ANAMODE_Pos (9U) +#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */ +#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */ +#define UCPD_CR_CCENABLE_Pos (10U) +#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */ +#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */ +#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */ +#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */ +#define UCPD_CR_USEEXTPHY_Pos (12U) +#define UCPD_CR_USEEXTPHY_Msk (0x1UL << UCPD_CR_USEEXTPHY_Pos) /*!< 0x00001000 */ +#define UCPD_CR_USEEXTPHY UCPD_CR_USEEXTPHY_Msk /*!< Controls enable of USB Power Delivery transmitter */ +#define UCPD_CR_CC2VCONNEN_Pos (13U) +#define UCPD_CR_CC2VCONNEN_Msk (0x1UL << UCPD_CR_CC2VCONNEN_Pos) /*!< 0x00002000 */ +#define UCPD_CR_CC2VCONNEN UCPD_CR_CC2VCONNEN_Msk /*!< VCONN enable for CC2 */ +#define UCPD_CR_CC1VCONNEN_Pos (14U) +#define UCPD_CR_CC1VCONNEN_Msk (0x1UL << UCPD_CR_CC1VCONNEN_Pos) /*!< 0x00004000 */ +#define UCPD_CR_CC1VCONNEN UCPD_CR_CC1VCONNEN_Msk /*!< VCONN enable for CC1 */ +#define UCPD_CR_DBATEN_Pos (15U) +#define UCPD_CR_DBATEN_Msk (0x1UL << UCPD_CR_DBATEN_Pos) /*!< 0x00008000 */ +#define UCPD_CR_DBATEN UCPD_CR_DBATEN_Msk /*!< Enable dead battery behavior (Active High) */ +#define UCPD_CR_FRSRXEN_Pos (16U) +#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */ +#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */ +#define UCPD_CR_FRSTX_Pos (17U) +#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */ +#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */ +#define UCPD_CR_RDCH_Pos (18U) +#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */ +#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */ +#define UCPD_CR_RPUSBABSENT_Pos (19U) +#define UCPD_CR_RPUSBABSENT_Msk (0x1UL << UCPD_CR_RPUSBABSENT_Pos) /*!< 0x00080000 */ +#define UCPD_CR_RPUSBABSENT UCPD_CR_RPUSBABSENT_Msk /*!< */ +#define UCPD_CR_CC1TCDIS_Pos (20U) +#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */ +#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */ +#define UCPD_CR_CC2TCDIS_Pos (21U) +#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */ +#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */ + +/******************** Bits definition for UCPD_IMR register *******************/ +#define UCPD_IMR_TXISIE_Pos (0U) +#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */ +#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */ +#define UCPD_IMR_TXMSGDISCIE_Pos (1U) +#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */ +#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */ +#define UCPD_IMR_TXMSGSENTIE_Pos (2U) +#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */ +#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */ +#define UCPD_IMR_TXMSGABTIE_Pos (3U) +#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */ +#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */ +#define UCPD_IMR_HRSTDISCIE_Pos (4U) +#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */ +#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */ +#define UCPD_IMR_HRSTSENTIE_Pos (5U) +#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */ +#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */ +#define UCPD_IMR_TXUNDIE_Pos (6U) +#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */ +#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */ +#define UCPD_IMR_RXNEIE_Pos (8U) +#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */ +#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */ +#define UCPD_IMR_RXORDDETIE_Pos (9U) +#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */ +#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */ +#define UCPD_IMR_RXHRSTDETIE_Pos (10U) +#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */ +#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */ +#define UCPD_IMR_RXOVRIE_Pos (11U) +#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */ +#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */ +#define UCPD_IMR_RXMSGENDIE_Pos (12U) +#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */ +#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */ +#define UCPD_IMR_TYPECEVT1IE_Pos (14U) +#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */ +#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */ +#define UCPD_IMR_TYPECEVT2IE_Pos (15U) +#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */ +#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */ +#define UCPD_IMR_FRSEVTIE_Pos (20U) +#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */ +#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */ + +/******************** Bits definition for UCPD_SR register ********************/ +#define UCPD_SR_TXIS_Pos (0U) +#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */ +#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */ +#define UCPD_SR_TXMSGDISC_Pos (1U) +#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */ +#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */ +#define UCPD_SR_TXMSGSENT_Pos (2U) +#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */ +#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */ +#define UCPD_SR_TXMSGABT_Pos (3U) +#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */ +#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */ +#define UCPD_SR_HRSTDISC_Pos (4U) +#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */ +#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */ +#define UCPD_SR_HRSTSENT_Pos (5U) +#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */ +#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */ +#define UCPD_SR_TXUND_Pos (6U) +#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */ +#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */ +#define UCPD_SR_RXNE_Pos (8U) +#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */ +#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */ +#define UCPD_SR_RXORDDET_Pos (9U) +#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */ +#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */ +#define UCPD_SR_RXHRSTDET_Pos (10U) +#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */ +#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */ +#define UCPD_SR_RXOVR_Pos (11U) +#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */ +#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */ +#define UCPD_SR_RXMSGEND_Pos (12U) +#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */ +#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */ +#define UCPD_SR_RXERR_Pos (13U) +#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */ +#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */ +#define UCPD_SR_TYPECEVT1_Pos (14U) +#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */ +#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */ +#define UCPD_SR_TYPECEVT2_Pos (15U) +#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */ +#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U) +#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */ +#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U) +#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/** @addtogroup STM32H5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)|| \ + ((INSTANCE) == ADC2_NS)|| \ + ((INSTANCE) == ADC2_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S)) +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ + ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ + ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ + ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ + ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* DTS Instances *******************************/ +#define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On H5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On H5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************** I3C Instances *******************************/ +#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S) || \ + ((INSTANCE) == I3C2_NS) || ((INSTANCE) == I3C2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) + +/****************************** FDCAN Instances *******************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \ + ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ + ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM12_NS) || ((__INSTANCE__) == TIM12_S)|| \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** CEC Instance *****************************************/ +#define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32H533xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H533xx_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h index ea69087317..c8062b41c7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h @@ -1,4 +1,4 @@ -/** +/** ****************************************************************************** * @file stm32h562xx.h * @author MCD Application Team @@ -176,6 +176,7 @@ typedef enum DTS_IRQn = 113, /*!< DTS global interrupt */ RNG_IRQn = 114, /*!< RNG global interrupt */ HASH_IRQn = 117, /*!< HASH global interrupt */ + PKA_IRQn = 118, /*!< PKA global interrupt */ CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ TIM12_IRQn = 120, /*!< TIM12 global interrupt */ TIM13_IRQn = 121, /*!< TIM13 global interrupt */ @@ -773,7 +774,8 @@ typedef struct __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ - uint32_t RESERVED0[221];/*!< Reserved, Address offset: 0x68 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ } TIM_TypeDef; @@ -975,6 +977,18 @@ typedef struct __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ } RCC_TypeDef; +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + /* * @brief RTC Specific device feature definitions */ @@ -1696,6 +1710,8 @@ typedef struct #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) #define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) #define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) /*!< APB3 Non secure peripherals */ @@ -1734,9 +1750,9 @@ typedef struct /* Flash, Peripheral and internal SRAMs base addresses - Secure */ #define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ -#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (256 KB) secure base address */ #define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */ -#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (512 KB) secure base address */ +#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (320 KB) secure base address */ #define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ /* Peripheral memory map - Secure */ @@ -1862,6 +1878,8 @@ typedef struct #define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) #define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) #define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) /*!< APB3 secure peripherals */ #define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) @@ -1948,9 +1966,6 @@ typedef struct #define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ #endif /* CMSE */ -/*!< USB PMA SIZE */ -#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ - /*!< Root Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) @@ -2233,6 +2248,7 @@ typedef struct #define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) #define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) #define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) /*!< APB3 Non secure peripherals */ @@ -2378,6 +2394,7 @@ typedef struct #define HASH_S ((HASH_TypeDef *) HASH_BASE_S) #define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) #define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) /*!< APB3 secure peripherals */ #define SBS_S ((SBS_TypeDef *) SBS_BASE_S) @@ -2791,6 +2808,10 @@ typedef struct #define RNG RNG_S #define RNG_BASE RNG_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + #define SDMMC1 SDMMC1_S @@ -3197,6 +3218,10 @@ typedef struct #define RNG RNG_NS #define RNG_BASE RNG_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + #define SDMMC1 SDMMC1_NS @@ -6241,7 +6266,7 @@ typedef struct #define EXTI_PRIVENR1_PRIV31 EXTI_PRIVENR1_PRIV31_Msk /*!< Privilege enable on line 31 */ /****************** Bit definition for EXTI_RTSR2 register *******************/ -#define EXTI_RTSR2_TR_Pos (14U) +#define EXTI_RTSR2_TR_Pos (12U) #define EXTI_RTSR2_TR_Msk (0x244UL << EXTI_RTSR2_TR_Pos) /*!< 0x00244000 */ #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */ #define EXTI_RTSR2_TR46_Pos (14U) @@ -6255,7 +6280,7 @@ typedef struct #define EXTI_RTSR2_TR53 EXTI_RTSR2_TR53_Msk /*!< Rising trigger event configuration bit of line 53 */ /****************** Bit definition for EXTI_FTSR2 register *******************/ -#define EXTI_FTSR2_TR_Pos (14U) +#define EXTI_FTSR2_TR_Pos (12U) #define EXTI_FTSR2_TR_Msk (0x244 << EXTI_FTSR2_TR_Pos) /*!< 0x00244000 */ #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */ #define EXTI_FTSR2_TR46_Pos (14U) @@ -6280,7 +6305,7 @@ typedef struct #define EXTI_SWIER2_SWIER53 EXTI_SWIER2_SWIER53_Msk /*!< Software Interrupt on line 53 */ /****************** Bit definition for EXTI_RPR2 register *******************/ -#define EXTI_RPR2_RPIF_Pos (14U) +#define EXTI_RPR2_RPIF_Pos (12U) #define EXTI_RPR2_RPIF_Msk (0x244UL << EXTI_RPR2_RPIF_Pos) /*!< 0x00244000 */ #define EXTI_RPR2_RPIF EXTI_RPR2_RPIF_Msk /*!< Rising pending edge configuration bits */ #define EXTI_RPR2_RPIF46_Pos (14U) @@ -6294,7 +6319,7 @@ typedef struct #define EXTI_RPR2_RPIF53 EXTI_RPR2_RPIF53_Msk /*!< Rising pending edge configuration bit of line 53 */ /****************** Bit definition for EXTI_FPR2 register *******************/ -#define EXTI_FPR2_FPIF_Pos (14U) +#define EXTI_FPR2_FPIF_Pos (12U) #define EXTI_FPR2_FPIF_Msk (0x244UL << EXTI_FPR2_FPIF_Pos) /*!< 0x00244000 */ #define EXTI_FPR2_FPIF EXTI_FPR2_FPIF_Msk /*!< Rising falling edge configuration bits */ #define EXTI_FPR2_FPIF46_Pos (14U) @@ -6837,6 +6862,9 @@ typedef struct #define EXTI_IMR2_IM44_Pos (12U) #define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ #define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */ +#define EXTI_IMR2_IM45_Pos (13U) +#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< Interrupt Mask on line 45 */ #define EXTI_IMR2_IM46_Pos (14U) #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */ @@ -6918,6 +6946,9 @@ typedef struct #define EXTI_EMR2_EM44_Pos (12U) #define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */ #define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */ +#define EXTI_EMR2_EM45_Pos (13U) +#define EXTI_EMR2_EM45_Msk (0x1UL << EXTI_EMR2_EM45_Pos) /*!< 0x00002000 */ +#define EXTI_EMR2_EM45 EXTI_EMR2_EM45_Msk /*!< Event Mask on line 45 */ #define EXTI_EMR2_EM46_Pos (14U) #define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */ #define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */ @@ -7676,7 +7707,7 @@ typedef struct /* FLASH */ /* */ /******************************************************************************/ -#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycle */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycle */ #define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-based registers for each Flash bank */ #define FLASH_SIZE_DEFAULT (0x200000U) /*!< FLASH Size */ #define FLASH_SECTOR_NB (128U) /*!< Flash Sector number */ @@ -7970,6 +8001,9 @@ typedef struct #define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) #define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ #define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ #define FLASH_OPTSR2_TZEN_Pos (24U) #define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ #define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ @@ -8002,7 +8036,7 @@ typedef struct /***************** Bits definition for FLASH_EDATA register ********************/ #define FLASH_EDATAR_EDATA_STRT_Pos (0U) -#define FLASH_EDATAR_EDATA_STRT_Msk (0x3UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000003 */ +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ #define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ #define FLASH_EDATAR_EDATA_EN_Pos (15U) #define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ @@ -8625,7 +8659,7 @@ typedef struct #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + /** @addtogroup STM32H5xx_Peripheral_Exported_macros * @{ @@ -20695,6 +21081,9 @@ typedef struct #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ ((INSTANCE) == ADC12_COMMON_S)) +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + /******************************* CORDIC Instances *****************************/ #define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) @@ -20738,6 +21127,11 @@ typedef struct ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + /****************************** RAMCFG Instances ********************************/ #define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ @@ -21261,6 +21655,9 @@ typedef struct ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) +/******************* TIM Instances : supporting bitfield RTCPREEN in OR1 register ********************/ +#define IS_TIM_RTCPREEN_INSTANCE(INSTANCE) (((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + /****************** TIM Instances : Advanced timer instances *******************/ #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) @@ -21458,7 +21855,6 @@ typedef struct /******************************* USB DRD FS PCD Instances *************************/ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) - /** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ /** @} */ /* End of group STM32H562xx */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h index 1411530df1..6657fe60b1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h @@ -1,4 +1,4 @@ -/** +/** ****************************************************************************** * @file stm32h563xx.h * @author MCD Application Team @@ -181,6 +181,7 @@ typedef enum DTS_IRQn = 113, /*!< DTS global interrupt */ RNG_IRQn = 114, /*!< RNG global interrupt */ HASH_IRQn = 117, /*!< HASH global interrupt */ + PKA_IRQn = 118, /*!< PKA global interrupt */ CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ TIM12_IRQn = 120, /*!< TIM12 global interrupt */ TIM13_IRQn = 121, /*!< TIM13 global interrupt */ @@ -951,7 +952,8 @@ typedef struct __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ - uint32_t RESERVED0[221];/*!< Reserved, Address offset: 0x68 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ } TIM_TypeDef; @@ -1153,6 +1155,18 @@ typedef struct __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ } RCC_TypeDef; +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + /* * @brief RTC Specific device feature definitions */ @@ -1877,6 +1891,8 @@ typedef struct #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) #define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) #define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) /*!< APB3 Non secure peripherals */ @@ -1917,9 +1933,9 @@ typedef struct /* Flash, Peripheral and internal SRAMs base addresses - Secure */ #define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ -#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (256 KB) secure base address */ #define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */ -#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (512 KB) secure base address */ +#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (320 KB) secure base address */ #define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ /* Peripheral memory map - Secure */ @@ -2048,6 +2064,8 @@ typedef struct #define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) #define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) #define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) /*!< APB3 secure peripherals */ #define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) @@ -2136,9 +2154,6 @@ typedef struct #define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ #endif /* CMSE */ -/*!< USB PMA SIZE */ -#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ - /*!< Root Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) @@ -2424,6 +2439,7 @@ typedef struct #define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) #define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) #define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) /*!< APB3 Non secure peripherals */ @@ -2574,6 +2590,7 @@ typedef struct #define HASH_S ((HASH_TypeDef *) HASH_BASE_S) #define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) #define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) /*!< APB3 secure peripherals */ #define SBS_S ((SBS_TypeDef *) SBS_BASE_S) @@ -2991,6 +3008,10 @@ typedef struct #define RNG RNG_S #define RNG_BASE RNG_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + #define ETH ETH_S #define ETH_BASE ETH_BASE_S @@ -3408,6 +3429,10 @@ typedef struct #define RNG RNG_NS #define RNG_BASE RNG_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + #define ETH ETH_NS #define ETH_BASE ETH_BASE_NS @@ -8325,7 +8350,7 @@ typedef struct #define EXTI_PRIVENR1_PRIV31 EXTI_PRIVENR1_PRIV31_Msk /*!< Privilege enable on line 31 */ /****************** Bit definition for EXTI_RTSR2 register *******************/ -#define EXTI_RTSR2_TR_Pos (14U) +#define EXTI_RTSR2_TR_Pos (12U) #define EXTI_RTSR2_TR_Msk (0x244UL << EXTI_RTSR2_TR_Pos) /*!< 0x00244000 */ #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */ #define EXTI_RTSR2_TR46_Pos (14U) @@ -8339,7 +8364,7 @@ typedef struct #define EXTI_RTSR2_TR53 EXTI_RTSR2_TR53_Msk /*!< Rising trigger event configuration bit of line 53 */ /****************** Bit definition for EXTI_FTSR2 register *******************/ -#define EXTI_FTSR2_TR_Pos (14U) +#define EXTI_FTSR2_TR_Pos (12U) #define EXTI_FTSR2_TR_Msk (0x244 << EXTI_FTSR2_TR_Pos) /*!< 0x00244000 */ #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */ #define EXTI_FTSR2_TR46_Pos (14U) @@ -8364,7 +8389,7 @@ typedef struct #define EXTI_SWIER2_SWIER53 EXTI_SWIER2_SWIER53_Msk /*!< Software Interrupt on line 53 */ /****************** Bit definition for EXTI_RPR2 register *******************/ -#define EXTI_RPR2_RPIF_Pos (14U) +#define EXTI_RPR2_RPIF_Pos (12U) #define EXTI_RPR2_RPIF_Msk (0x244UL << EXTI_RPR2_RPIF_Pos) /*!< 0x00244000 */ #define EXTI_RPR2_RPIF EXTI_RPR2_RPIF_Msk /*!< Rising pending edge configuration bits */ #define EXTI_RPR2_RPIF46_Pos (14U) @@ -8378,7 +8403,7 @@ typedef struct #define EXTI_RPR2_RPIF53 EXTI_RPR2_RPIF53_Msk /*!< Rising pending edge configuration bit of line 53 */ /****************** Bit definition for EXTI_FPR2 register *******************/ -#define EXTI_FPR2_FPIF_Pos (14U) +#define EXTI_FPR2_FPIF_Pos (12U) #define EXTI_FPR2_FPIF_Msk (0x244UL << EXTI_FPR2_FPIF_Pos) /*!< 0x00244000 */ #define EXTI_FPR2_FPIF EXTI_FPR2_FPIF_Msk /*!< Rising falling edge configuration bits */ #define EXTI_FPR2_FPIF46_Pos (14U) @@ -8921,6 +8946,9 @@ typedef struct #define EXTI_IMR2_IM44_Pos (12U) #define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ #define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */ +#define EXTI_IMR2_IM45_Pos (13U) +#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< Interrupt Mask on line 45 */ #define EXTI_IMR2_IM46_Pos (14U) #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */ @@ -9002,6 +9030,9 @@ typedef struct #define EXTI_EMR2_EM44_Pos (12U) #define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */ #define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */ +#define EXTI_EMR2_EM45_Pos (13U) +#define EXTI_EMR2_EM45_Msk (0x1UL << EXTI_EMR2_EM45_Pos) /*!< 0x00002000 */ +#define EXTI_EMR2_EM45 EXTI_EMR2_EM45_Msk /*!< Event Mask on line 45 */ #define EXTI_EMR2_EM46_Pos (14U) #define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */ #define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */ @@ -9760,7 +9791,7 @@ typedef struct /* FLASH */ /* */ /******************************************************************************/ -#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycle */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycle */ #define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-based registers for each Flash bank */ #define FLASH_SIZE_DEFAULT (0x200000U) /*!< FLASH Size */ #define FLASH_SECTOR_NB (128U) /*!< Flash Sector number */ @@ -10054,6 +10085,9 @@ typedef struct #define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) #define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ #define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ #define FLASH_OPTSR2_TZEN_Pos (24U) #define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ #define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ @@ -10086,7 +10120,7 @@ typedef struct /***************** Bits definition for FLASH_EDATA register ********************/ #define FLASH_EDATAR_EDATA_STRT_Pos (0U) -#define FLASH_EDATAR_EDATA_STRT_Msk (0x3UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000003 */ +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ #define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ #define FLASH_EDATAR_EDATA_EN_Pos (15U) #define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ @@ -10709,7 +10743,7 @@ typedef struct #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + /** @addtogroup STM32H5xx_Peripheral_Exported_macros * @{ @@ -22827,6 +23213,9 @@ typedef struct #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ ((INSTANCE) == ADC12_COMMON_S)) +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + /******************************* CORDIC Instances *****************************/ #define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) @@ -22872,6 +23261,11 @@ typedef struct ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + /****************************** RAMCFG Instances ********************************/ #define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ @@ -23397,6 +23791,9 @@ typedef struct ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \ ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) +/******************* TIM Instances : supporting bitfield RTCPREEN in OR1 register ********************/ +#define IS_TIM_RTCPREEN_INSTANCE(INSTANCE) (((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + /****************** TIM Instances : Advanced timer instances *******************/ #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) @@ -23594,7 +23991,6 @@ typedef struct /******************************* USB DRD FS PCD Instances *************************/ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) - /** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ /** @} */ /* End of group STM32H563xx */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h index f681a555af..49c99c8f4e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h @@ -1,4 +1,4 @@ -/** +/** ****************************************************************************** * @file stm32h573xx.h * @author MCD Application Team @@ -989,7 +989,8 @@ typedef struct __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ - uint32_t RESERVED0[221];/*!< Reserved, Address offset: 0x68 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ } TIM_TypeDef; @@ -2003,9 +2004,9 @@ typedef struct /* Flash, Peripheral and internal SRAMs base addresses - Secure */ #define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ -#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (256 KB) secure base address */ #define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */ -#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (512 KB) secure base address */ +#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (320 KB) secure base address */ #define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ /* Peripheral memory map - Secure */ @@ -2231,9 +2232,6 @@ typedef struct #define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ #endif /* CMSE */ -/*!< USB PMA SIZE */ -#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */ - /*!< Root Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) @@ -8760,7 +8758,7 @@ typedef struct #define EXTI_PRIVENR1_PRIV31 EXTI_PRIVENR1_PRIV31_Msk /*!< Privilege enable on line 31 */ /****************** Bit definition for EXTI_RTSR2 register *******************/ -#define EXTI_RTSR2_TR_Pos (14U) +#define EXTI_RTSR2_TR_Pos (12U) #define EXTI_RTSR2_TR_Msk (0x244UL << EXTI_RTSR2_TR_Pos) /*!< 0x00244000 */ #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */ #define EXTI_RTSR2_TR46_Pos (14U) @@ -8774,7 +8772,7 @@ typedef struct #define EXTI_RTSR2_TR53 EXTI_RTSR2_TR53_Msk /*!< Rising trigger event configuration bit of line 53 */ /****************** Bit definition for EXTI_FTSR2 register *******************/ -#define EXTI_FTSR2_TR_Pos (14U) +#define EXTI_FTSR2_TR_Pos (12U) #define EXTI_FTSR2_TR_Msk (0x244 << EXTI_FTSR2_TR_Pos) /*!< 0x00244000 */ #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */ #define EXTI_FTSR2_TR46_Pos (14U) @@ -8799,7 +8797,7 @@ typedef struct #define EXTI_SWIER2_SWIER53 EXTI_SWIER2_SWIER53_Msk /*!< Software Interrupt on line 53 */ /****************** Bit definition for EXTI_RPR2 register *******************/ -#define EXTI_RPR2_RPIF_Pos (14U) +#define EXTI_RPR2_RPIF_Pos (12U) #define EXTI_RPR2_RPIF_Msk (0x244UL << EXTI_RPR2_RPIF_Pos) /*!< 0x00244000 */ #define EXTI_RPR2_RPIF EXTI_RPR2_RPIF_Msk /*!< Rising pending edge configuration bits */ #define EXTI_RPR2_RPIF46_Pos (14U) @@ -8813,7 +8811,7 @@ typedef struct #define EXTI_RPR2_RPIF53 EXTI_RPR2_RPIF53_Msk /*!< Rising pending edge configuration bit of line 53 */ /****************** Bit definition for EXTI_FPR2 register *******************/ -#define EXTI_FPR2_FPIF_Pos (14U) +#define EXTI_FPR2_FPIF_Pos (12U) #define EXTI_FPR2_FPIF_Msk (0x244UL << EXTI_FPR2_FPIF_Pos) /*!< 0x00244000 */ #define EXTI_FPR2_FPIF EXTI_FPR2_FPIF_Msk /*!< Rising falling edge configuration bits */ #define EXTI_FPR2_FPIF46_Pos (14U) @@ -9356,6 +9354,9 @@ typedef struct #define EXTI_IMR2_IM44_Pos (12U) #define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ #define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */ +#define EXTI_IMR2_IM45_Pos (13U) +#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */ +#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< Interrupt Mask on line 45 */ #define EXTI_IMR2_IM46_Pos (14U) #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */ @@ -9437,6 +9438,9 @@ typedef struct #define EXTI_EMR2_EM44_Pos (12U) #define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */ #define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */ +#define EXTI_EMR2_EM45_Pos (13U) +#define EXTI_EMR2_EM45_Msk (0x1UL << EXTI_EMR2_EM45_Pos) /*!< 0x00002000 */ +#define EXTI_EMR2_EM45 EXTI_EMR2_EM45_Msk /*!< Event Mask on line 45 */ #define EXTI_EMR2_EM46_Pos (14U) #define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */ #define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */ @@ -10195,7 +10199,7 @@ typedef struct /* FLASH */ /* */ /******************************************************************************/ -#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycle */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycle */ #define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-based registers for each Flash bank */ #define FLASH_SIZE_DEFAULT (0x200000U) /*!< FLASH Size */ #define FLASH_SECTOR_NB (128U) /*!< Flash Sector number */ @@ -10489,6 +10493,9 @@ typedef struct #define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) #define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ #define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ #define FLASH_OPTSR2_TZEN_Pos (24U) #define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ #define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ @@ -10521,7 +10528,7 @@ typedef struct /***************** Bits definition for FLASH_EDATA register ********************/ #define FLASH_EDATAR_EDATA_STRT_Pos (0U) -#define FLASH_EDATAR_EDATA_STRT_Msk (0x3UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000003 */ +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ #define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ #define FLASH_EDATAR_EDATA_EN_Pos (15U) #define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ @@ -11144,7 +11151,7 @@ typedef struct #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!Release Notes for  STM32H5xx C

Update History

- +

Main Changes

    +
  • First official release of STM32H5xx CMSIS drivers to support STM32H533xx and STM32H523xx devices
    • +
  • Add bit definition for I3C_BCR register
    • +
  • Add IS_DMA_PFREQ_INSTANCE macro
    • +
  • Fix Ticket 163445: [FLASH][CMSIS] Wrong EDATA_STRT start sectors mask size
    • +
  • Fix Ticket 163090: [FOSS-Audit] Licensing issues: Missing copyright from Arm Limited and original header not retained
    • +
  • Update CubeIDE projects to be compliant with GCC12 diagnostics
    • +
  • Fix Ticket 165407: [H5][GTZC][CMSIS]: wrong Flash illegal access bit definition
    • +
  • Fix Ticket 147880: [STM32H5]|FLASH_HAL] Some option bytes are missing in stm32h5xx_hal_flash_ex.h
    • +
  • Set FMC_SDCMR_MODE_2 bit field definition to 0x4
    • +
  • Fix Ticket 162902: [GitHub] Wrong declaration of g_pfnVectors size in gcc/startup files
    • +
  • Fix: Ticket 167776: [CMSIS] Missing TIM option register related definitions
    • +
+
+
+
+ +
+

Main Changes

+
  • Add DUA addresses constants definitions for STM32H573xx devices only
  • Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE & IS_TIM_TISEL_INSTANCE macros
  • Update possible values of the ATCKSEL field of TAMP active tamper control register and update the mask accordingly.
    • @@ -43,7 +62,7 @@

    Main Changes

    -

    Main Changes

    +

    Main Changes

    • First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)
    diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H503xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H503xx_FLASH.ld index 1ab7bafc73..36463666c6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H503xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H503xx_FLASH.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H503xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H503xx_RAM.ld index c46980f148..aa062e31ff 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H503xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H503xx_RAM.ld @@ -83,13 +83,15 @@ SECTIONS . = ALIGN(4); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -97,7 +99,7 @@ SECTIONS . = ALIGN(4); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -106,7 +108,7 @@ SECTIONS . = ALIGN(4); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -116,7 +118,7 @@ SECTIONS . = ALIGN(4); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH.ld new file mode 100644 index 0000000000..64cf153e73 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH.ld @@ -0,0 +1,187 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H523xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 272K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH_ns.ld new file mode 100644 index 0000000000..cf7bdfb863 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH_ns.ld @@ -0,0 +1,187 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H523xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20034000, LENGTH = 64K /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */ + FLASH (rx) : ORIGIN = 0x8040000, LENGTH = 256K /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH_s.ld new file mode 100644 index 0000000000..ba316e919e --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_FLASH_s.ld @@ -0,0 +1,195 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H523xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 208K /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */ + FLASH (rx) : ORIGIN = 0xc000000, LENGTH = 248K /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */ + FLASH_NSC (rx) : ORIGIN = 0xc03e000, LENGTH = 8K /* Non-Secure Call-able region */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM.ld new file mode 100644 index 0000000000..22952e69f1 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM.ld @@ -0,0 +1,187 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld (debug in RAM dedicated) + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H523xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 272K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >RAM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >RAM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >RAM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >RAM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM_ns.ld new file mode 100644 index 0000000000..df5708ea4f --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM_ns.ld @@ -0,0 +1,187 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld (debug in RAM dedicated) + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H523xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20020000, LENGTH = 144K /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */ + FLASH (rx) : ORIGIN = 0x8040000, LENGTH = 256K /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >RAM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >RAM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >RAM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >RAM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM_s.ld new file mode 100644 index 0000000000..42dd807fdc --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H523xx_RAM_s.ld @@ -0,0 +1,195 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld (debug in RAM dedicated) + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H523xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 120K /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */ + RAM_NSC (xrw) : ORIGIN = 0x3001e000, LENGTH = 8K /* Non-Secure Call-able region */ + FLASH (rx) : ORIGIN = 0xc000000, LENGTH = 256K /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >RAM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >RAM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >RAM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >RAM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >RAM_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH.ld new file mode 100644 index 0000000000..0999e1ca0f --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH.ld @@ -0,0 +1,187 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H533xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 272K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH_ns.ld new file mode 100644 index 0000000000..03af851957 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH_ns.ld @@ -0,0 +1,187 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H533xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20034000, LENGTH = 64K /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */ + FLASH (rx) : ORIGIN = 0x8040000, LENGTH = 256K /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH_s.ld new file mode 100644 index 0000000000..cfc89d3c77 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_FLASH_s.ld @@ -0,0 +1,195 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H533xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 208K /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */ + FLASH (rx) : ORIGIN = 0xc000000, LENGTH = 248K /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */ + FLASH_NSC (rx) : ORIGIN = 0xc03e000, LENGTH = 8K /* Non-Secure Call-able region */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM.ld new file mode 100644 index 0000000000..1f63351748 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM.ld @@ -0,0 +1,187 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld (debug in RAM dedicated) + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H533xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 272K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >RAM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >RAM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >RAM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >RAM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM_ns.ld new file mode 100644 index 0000000000..d2f7b4cb1b --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM_ns.ld @@ -0,0 +1,187 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld (debug in RAM dedicated) + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H533xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20020000, LENGTH = 144K /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */ + FLASH (rx) : ORIGIN = 0x8040000, LENGTH = 256K /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >RAM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >RAM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >RAM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >RAM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM_s.ld new file mode 100644 index 0000000000..75d1bdc13a --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H533xx_RAM_s.ld @@ -0,0 +1,195 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld (debug in RAM dedicated) + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H533xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 120K /* Memory is divided. Actual start is 0x20000000 and actual length is 272K */ + RAM_NSC (xrw) : ORIGIN = 0x3001e000, LENGTH = 8K /* Non-Secure Call-able region */ + FLASH (rx) : ORIGIN = 0xc000000, LENGTH = 256K /* Memory is divided. Actual start is 0x8000000 and actual length is 512K */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >RAM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >RAM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >RAM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >RAM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >RAM_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH.ld index 672c1ee39c..f42c58b9b4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH_ns.ld index 4f404ef688..fbf3951720 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH_ns.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH_s.ld index 764e13613d..fe0299e21f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_FLASH_s.ld @@ -86,13 +86,15 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -100,7 +102,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -109,7 +111,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -119,7 +121,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM.ld index 28a0aafdd3..0e5bf4e98c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(4); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(4); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(4); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(4); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM_ns.ld index 61ab7ea085..d5060fd5e5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM_ns.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(4); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(4); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(4); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(4); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM_s.ld index 286ccc8b2a..cef8f197da 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H562xx_RAM_s.ld @@ -88,13 +88,15 @@ SECTIONS . = ALIGN(4); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -102,7 +104,7 @@ SECTIONS . = ALIGN(4); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -111,7 +113,7 @@ SECTIONS . = ALIGN(4); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -121,7 +123,7 @@ SECTIONS . = ALIGN(4); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH.ld index 8975f24483..fd13ed12bb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH_ns.ld index 9fd0481bff..a7605b06d1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH_ns.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH_s.ld index 34a39b42bd..c99b285d83 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_FLASH_s.ld @@ -86,13 +86,15 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -100,7 +102,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -109,7 +111,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -119,7 +121,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM.ld index a23c8a45e0..79c1c2b444 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(4); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(4); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(4); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(4); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM_ns.ld index 7d93174088..51d6d44cfb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM_ns.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(4); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(4); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(4); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(4); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM_s.ld index 4fe745b33f..082258b084 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H563xx_RAM_s.ld @@ -88,13 +88,15 @@ SECTIONS . = ALIGN(4); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -102,7 +104,7 @@ SECTIONS . = ALIGN(4); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -111,7 +113,7 @@ SECTIONS . = ALIGN(4); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -121,7 +123,7 @@ SECTIONS . = ALIGN(4); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH.ld index 97c63fe6ac..c784d99568 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH_ns.ld index 1dab69df13..b4794c2820 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH_ns.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH_s.ld index de53e502fd..b9a0a6f207 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_FLASH_s.ld @@ -86,13 +86,15 @@ SECTIONS . = ALIGN(4); } >FLASH - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -100,7 +102,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -109,7 +111,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -119,7 +121,7 @@ SECTIONS . = ALIGN(4); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM.ld index dc45f30953..8452b4472a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(4); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(4); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(4); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(4); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM_ns.ld index ee7d1304a4..ad08495e06 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM_ns.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(4); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(4); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(4); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(4); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM_s.ld index e2aab7a792..b4a053a14d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/linker/STM32H573xx_RAM_s.ld @@ -88,13 +88,15 @@ SECTIONS . = ALIGN(4); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -102,7 +104,7 @@ SECTIONS . = ALIGN(4); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -111,7 +113,7 @@ SECTIONS . = ALIGN(4); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -121,7 +123,7 @@ SECTIONS . = ALIGN(4); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h503xx.s b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h503xx.s index 14c3242b70..5e2ad745d7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h503xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h503xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -278,6 +277,8 @@ g_pfnVectors: .word I3C2_ER_IRQHandler .word COMP1_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h523xx.s b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h523xx.s new file mode 100644 index 0000000000..d870f9eacc --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h523xx.s @@ -0,0 +1,634 @@ +/** + ****************************************************************************** + * @file startup_stm32h523xx.s + * @author MCD Application Team + * @brief STM32h523xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None + */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32h523xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_AVD_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word IWDG_IRQHandler + .word 0 + .word ADC1_IRQHandler + .word DAC1_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word TIM5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word SPI3_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC2_IRQHandler + .word LPTIM2_IRQHandler + .word TIM15_IRQHandler + .word 0 + .word 0 + .word USB_DRD_FS_IRQHandler + .word CRS_IRQHandler + .word UCPD1_IRQHandler + .word FMC_IRQHandler + .word OCTOSPI1_IRQHandler + .word SDMMC1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word 0 + .word USART6_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word GPDMA2_Channel0_IRQHandler + .word GPDMA2_Channel1_IRQHandler + .word GPDMA2_Channel2_IRQHandler + .word GPDMA2_Channel3_IRQHandler + .word GPDMA2_Channel4_IRQHandler + .word GPDMA2_Channel5_IRQHandler + .word GPDMA2_Channel6_IRQHandler + .word GPDMA2_Channel7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + .word ICACHE_IRQHandler + .word DCACHE1_IRQHandler + .word 0 + .word 0 + .word DCMI_PSSI_IRQHandler + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word 0 + .word 0 + .word DTS_IRQHandler + .word RNG_IRQHandler + .word 0 + .word 0 + .word HASH_IRQHandler + .word 0 + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word 0 + .word 0 + .word I3C1_EV_IRQHandler + .word I3C1_ER_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word I3C2_EV_IRQHandler + .word I3C2_ER_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak USB_DRD_FS_IRQHandler + .thumb_set USB_DRD_FS_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel0_IRQHandler + .thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler + + .weak GPDMA2_Channel1_IRQHandler + .thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler + + .weak GPDMA2_Channel2_IRQHandler + .thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler + + .weak GPDMA2_Channel3_IRQHandler + .thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler + + .weak GPDMA2_Channel4_IRQHandler + .thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler + + .weak GPDMA2_Channel5_IRQHandler + .thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler + + .weak GPDMA2_Channel6_IRQHandler + .thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel7_IRQHandler + .thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak DCACHE1_IRQHandler + .thumb_set DCACHE1_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak I3C2_EV_IRQHandler + .thumb_set I3C2_EV_IRQHandler,Default_Handler + + .weak I3C2_ER_IRQHandler + .thumb_set I3C2_ER_IRQHandler,Default_Handler \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h533xx.s b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h533xx.s new file mode 100644 index 0000000000..8dbd003123 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h533xx.s @@ -0,0 +1,646 @@ +/** + ****************************************************************************** + * @file startup_stm32h533xx.s + * @author MCD Application Team + * @brief STM32h533xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None + */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32h533xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_AVD_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word IWDG_IRQHandler + .word SAES_IRQHandler + .word ADC1_IRQHandler + .word DAC1_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word TIM5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word SPI3_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC2_IRQHandler + .word LPTIM2_IRQHandler + .word TIM15_IRQHandler + .word 0 + .word 0 + .word USB_DRD_FS_IRQHandler + .word CRS_IRQHandler + .word UCPD1_IRQHandler + .word FMC_IRQHandler + .word OCTOSPI1_IRQHandler + .word SDMMC1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word 0 + .word USART6_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word GPDMA2_Channel0_IRQHandler + .word GPDMA2_Channel1_IRQHandler + .word GPDMA2_Channel2_IRQHandler + .word GPDMA2_Channel3_IRQHandler + .word GPDMA2_Channel4_IRQHandler + .word GPDMA2_Channel5_IRQHandler + .word GPDMA2_Channel6_IRQHandler + .word GPDMA2_Channel7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + .word ICACHE_IRQHandler + .word DCACHE1_IRQHandler + .word 0 + .word 0 + .word DCMI_PSSI_IRQHandler + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word 0 + .word 0 + .word DTS_IRQHandler + .word RNG_IRQHandler + .word OTFDEC1_IRQHandler + .word AES_IRQHandler + .word HASH_IRQHandler + .word PKA_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word 0 + .word 0 + .word I3C1_EV_IRQHandler + .word I3C1_ER_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word I3C2_EV_IRQHandler + .word I3C2_ER_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak USB_DRD_FS_IRQHandler + .thumb_set USB_DRD_FS_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel0_IRQHandler + .thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler + + .weak GPDMA2_Channel1_IRQHandler + .thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler + + .weak GPDMA2_Channel2_IRQHandler + .thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler + + .weak GPDMA2_Channel3_IRQHandler + .thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler + + .weak GPDMA2_Channel4_IRQHandler + .thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler + + .weak GPDMA2_Channel5_IRQHandler + .thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler + + .weak GPDMA2_Channel6_IRQHandler + .thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel7_IRQHandler + .thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak DCACHE1_IRQHandler + .thumb_set DCACHE1_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak OTFDEC1_IRQHandler + .thumb_set OTFDEC1_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak I3C2_EV_IRQHandler + .thumb_set I3C2_EV_IRQHandler,Default_Handler + + .weak I3C2_ER_IRQHandler + .thumb_set I3C2_ER_IRQHandler,Default_Handler \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h562xx.s b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h562xx.s index ee36dc21a5..c9b678a71a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h562xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h562xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -275,6 +274,8 @@ g_pfnVectors: .word LPTIM5_IRQHandler .word LPTIM6_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h563xx.s b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h563xx.s index 50bb4b4c38..d7d0d51f69 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h563xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h563xx.s @@ -125,7 +125,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -276,6 +275,8 @@ g_pfnVectors: .word LPTIM5_IRQHandler .word LPTIM6_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h573xx.s b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h573xx.s index b950053471..e6b9141d23 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h573xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/startup_stm32h573xx.s @@ -128,7 +128,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -280,6 +279,8 @@ g_pfnVectors: .word LPTIM5_IRQHandler .word LPTIM6_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 13fff7038b..da802b0a2f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -9,7 +9,7 @@ * STM32F7: 1.2.8 * STM32G0: 1.4.4 * STM32G4: 1.2.3 - * STM32H5: 1.1.0 + * STM32H5: 1.2.0 * STM32H7: 1.10.3 * STM32L0: 1.9.3 * STM32L1: 2.3.3 From 064bbe4d83b895facdb4eb3ca0b81b7fcb13ccdc Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 8 Apr 2024 09:23:36 +0200 Subject: [PATCH 3/6] core(H5): update wrapped files Signed-off-by: Frederic Pillon --- cores/arduino/stm32/stm32_def_build.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index 12d45ea5b4..5ac348f9dd 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -222,6 +222,10 @@ #define CMSIS_STARTUP_FILE "startup_stm32gbk1cb.s" #elif defined(STM32H503xx) #define CMSIS_STARTUP_FILE "startup_stm32h503xx.s" + #elif defined(STM32H523xx) + #define CMSIS_STARTUP_FILE "startup_stm32h523xx.s" + #elif defined(STM32H533xx) + #define CMSIS_STARTUP_FILE "startup_stm32h533xx.s" #elif defined(STM32H562xx) #define CMSIS_STARTUP_FILE "startup_stm32h562xx.s" #elif defined(STM32H563xx) From b839de3b00d38fb5ac401f5d698a3a5a99517b04 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 8 Apr 2024 09:28:36 +0200 Subject: [PATCH 4/6] chore(h5): update hal conf default Signed-off-by: Frederic Pillon --- system/STM32H5xx/stm32h5xx_hal_conf_default.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/system/STM32H5xx/stm32h5xx_hal_conf_default.h b/system/STM32H5xx/stm32h5xx_hal_conf_default.h index e27135ecd1..4eef816c84 100644 --- a/system/STM32H5xx/stm32h5xx_hal_conf_default.h +++ b/system/STM32H5xx/stm32h5xx_hal_conf_default.h @@ -148,7 +148,7 @@ The real value may vary depending on the variations in voltage and temperature.*/ #if !defined (LSI_STARTUP_TIME) -#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */ +#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in us */ #endif /* LSI_STARTUP_TIME */ /** From f0ea33471c139c4afb55f16139355af14d026950 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 8 Apr 2024 09:46:33 +0200 Subject: [PATCH 5/6] chore(h5): update variants to add new h523/h533 Signed-off-by: Frederic Pillon --- .../STM32H5xx/H503CB(T-U)/PeripheralPins.c | 2 +- variants/STM32H5xx/H503EBY/PeripheralPins.c | 2 +- variants/STM32H5xx/H503KBU/PeripheralPins.c | 2 +- variants/STM32H5xx/H503RBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 391 ++++++++++ .../H523C(C-E)(T-U)_H533CE(T-U)/PinNamesVar.h | 67 ++ .../boards_entry.txt | 53 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 71 ++ .../variant_generic.h | 190 +++++ .../H523HEY_H533HEY/PeripheralPins.c | 336 +++++++++ .../STM32H5xx/H523HEY_H533HEY/PinNamesVar.h | 58 ++ .../H523HEY_H533HEY/boards_entry.txt | 21 + .../STM32H5xx/H523HEY_H533HEY/generic_clock.c | 27 + .../H523HEY_H533HEY/variant_generic.cpp | 60 ++ .../H523HEY_H533HEY/variant_generic.h | 172 +++++ .../H523R(C-E)T_H533RET/PeripheralPins.c | 562 ++++++++++++++ .../H523R(C-E)T_H533RET/PinNamesVar.h | 79 ++ .../H523R(C-E)T_H533RET/boards_entry.txt | 29 + .../H523R(C-E)T_H533RET/generic_clock.c | 28 + .../H523R(C-E)T_H533RET/variant_generic.cpp | 90 +++ .../H523R(C-E)T_H533RET/variant_generic.h | 222 ++++++ .../PeripheralPins.c | 651 +++++++++++++++++ .../H523V(C-E)(I-T)_H533VE(I-T)/PinNamesVar.h | 79 ++ .../boards_entry.txt | 53 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 122 ++++ .../variant_generic.h | 250 +++++++ .../PeripheralPins.c | 686 ++++++++++++++++++ .../H523Z(C-E)(J-T)_H533ZE(J-T)/PinNamesVar.h | 79 ++ .../boards_entry.txt | 53 ++ .../generic_clock.c | 29 + .../variant_generic.cpp | 158 ++++ .../variant_generic.h | 282 +++++++ .../STM32H5xx/H562A(G-I)I/PeripheralPins.c | 2 +- .../H562I(G-I)(K-T)/PeripheralPins.c | 2 +- .../STM32H5xx/H562R(G-I)T/PeripheralPins.c | 2 +- .../STM32H5xx/H562R(G-I)V/PeripheralPins.c | 2 +- .../STM32H5xx/H562V(G-I)T/PeripheralPins.c | 2 +- .../STM32H5xx/H562Z(G-I)T/PeripheralPins.c | 2 +- .../H563A(G-I)I_H573AII/PeripheralPins.c | 2 +- .../H563AIIxQ_H573AIIxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H563IIKxQ_H573IIKxQ/PeripheralPins.c | 2 +- .../H563IITxQ_H573IITxQ/PeripheralPins.c | 2 +- .../H563MIYxQ_H573MIYxQ/PeripheralPins.c | 2 +- .../H563R(G-I)T_H573RIT/PeripheralPins.c | 2 +- .../H563R(G-I)V_H573RIV/PeripheralPins.c | 2 +- .../H563V(G-I)T_H573VIT/PeripheralPins.c | 2 +- .../H563VITxQ_H573VITxQ/PeripheralPins.c | 31 +- .../H563VITxQ_H573VITxQ/variant_generic.h | 3 + .../H563Z(G-I)T_H573ZIT/PeripheralPins.c | 2 +- .../H563ZITxQ_H573ZITxQ/PeripheralPins.c | 35 +- .../H563ZITxQ_H573ZITxQ/variant_generic.h | 3 + 54 files changed, 5044 insertions(+), 24 deletions(-) create mode 100644 variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c create mode 100644 variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PinNamesVar.h create mode 100644 variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/boards_entry.txt create mode 100644 variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/generic_clock.c create mode 100644 variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/variant_generic.cpp create mode 100644 variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/variant_generic.h create mode 100644 variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c create mode 100644 variants/STM32H5xx/H523HEY_H533HEY/PinNamesVar.h create mode 100644 variants/STM32H5xx/H523HEY_H533HEY/boards_entry.txt create mode 100644 variants/STM32H5xx/H523HEY_H533HEY/generic_clock.c create mode 100644 variants/STM32H5xx/H523HEY_H533HEY/variant_generic.cpp create mode 100644 variants/STM32H5xx/H523HEY_H533HEY/variant_generic.h create mode 100644 variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c create mode 100644 variants/STM32H5xx/H523R(C-E)T_H533RET/PinNamesVar.h create mode 100644 variants/STM32H5xx/H523R(C-E)T_H533RET/boards_entry.txt create mode 100644 variants/STM32H5xx/H523R(C-E)T_H533RET/generic_clock.c create mode 100644 variants/STM32H5xx/H523R(C-E)T_H533RET/variant_generic.cpp create mode 100644 variants/STM32H5xx/H523R(C-E)T_H533RET/variant_generic.h create mode 100644 variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c create mode 100644 variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PinNamesVar.h create mode 100644 variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/boards_entry.txt create mode 100644 variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/generic_clock.c create mode 100644 variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/variant_generic.cpp create mode 100644 variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/variant_generic.h create mode 100644 variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c create mode 100644 variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PinNamesVar.h create mode 100644 variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/boards_entry.txt create mode 100644 variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/generic_clock.c create mode 100644 variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/variant_generic.cpp create mode 100644 variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/variant_generic.h diff --git a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c index 23bf51b0e2..860a173898 100644 --- a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c +++ b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503CBTx.xml, STM32H503CBUx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503EBY/PeripheralPins.c b/variants/STM32H5xx/H503EBY/PeripheralPins.c index 8237f2f1c1..da42357e03 100644 --- a/variants/STM32H5xx/H503EBY/PeripheralPins.c +++ b/variants/STM32H5xx/H503EBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503EBYx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503KBU/PeripheralPins.c b/variants/STM32H5xx/H503KBU/PeripheralPins.c index 4f17b58eda..62abfc7175 100644 --- a/variants/STM32H5xx/H503KBU/PeripheralPins.c +++ b/variants/STM32H5xx/H503KBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503KBUx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503RBT/PeripheralPins.c b/variants/STM32H5xx/H503RBT/PeripheralPins.c index 5cd984d790..cd32fbcc22 100644 --- a/variants/STM32H5xx/H503RBT/PeripheralPins.c +++ b/variants/STM32H5xx/H503RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503RBTx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c new file mode 100644 index 0000000000..7bca48fd4e --- /dev/null +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c @@ -0,0 +1,391 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H523CCTx.xml, STM32H523CCUx.xml + * STM32H523CETx.xml, STM32H523CEUx.xml + * STM32H533CETx.xml, STM32H533CEUx.xml + * CubeMX DB release 6.0.110 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_4, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_8, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I3C2)}, + {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PB_5, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_5, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI3)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_8, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI1)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_7, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI3)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_0, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PinNamesVar.h b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PinNamesVar.h new file mode 100644 index 0000000000..d521e25ca7 --- /dev/null +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PinNamesVar.h @@ -0,0 +1,67 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/boards_entry.txt b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/boards_entry.txt new file mode 100644 index 0000000000..4ddfd05182 --- /dev/null +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/boards_entry.txt @@ -0,0 +1,53 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H523CCTx +GenH5.menu.pnum.GENERIC_H523CCTX=Generic H523CCTx +GenH5.menu.pnum.GENERIC_H523CCTX.upload.maximum_size=262144 +GenH5.menu.pnum.GENERIC_H523CCTX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523CCTX.build.board=GENERIC_H523CCTX +GenH5.menu.pnum.GENERIC_H523CCTX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523CCTX.build.variant=STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U) + +# Generic H523CCUx +GenH5.menu.pnum.GENERIC_H523CCUX=Generic H523CCUx +GenH5.menu.pnum.GENERIC_H523CCUX.upload.maximum_size=262144 +GenH5.menu.pnum.GENERIC_H523CCUX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523CCUX.build.board=GENERIC_H523CCUX +GenH5.menu.pnum.GENERIC_H523CCUX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523CCUX.build.variant=STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U) + +# Generic H523CETx +GenH5.menu.pnum.GENERIC_H523CETX=Generic H523CETx +GenH5.menu.pnum.GENERIC_H523CETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H523CETX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523CETX.build.board=GENERIC_H523CETX +GenH5.menu.pnum.GENERIC_H523CETX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523CETX.build.variant=STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U) + +# Generic H523CEUx +GenH5.menu.pnum.GENERIC_H523CEUX=Generic H523CEUx +GenH5.menu.pnum.GENERIC_H523CEUX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H523CEUX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523CEUX.build.board=GENERIC_H523CEUX +GenH5.menu.pnum.GENERIC_H523CEUX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523CEUX.build.variant=STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U) + +# Generic H533CETx +GenH5.menu.pnum.GENERIC_H533CETX=Generic H533CETx +GenH5.menu.pnum.GENERIC_H533CETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H533CETX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H533CETX.build.board=GENERIC_H533CETX +GenH5.menu.pnum.GENERIC_H533CETX.build.product_line=STM32H533xx +GenH5.menu.pnum.GENERIC_H533CETX.build.variant=STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U) + +# Generic H533CEUx +GenH5.menu.pnum.GENERIC_H533CEUX=Generic H533CEUx +GenH5.menu.pnum.GENERIC_H533CEUX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H533CEUX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H533CEUX.build.board=GENERIC_H533CEUX +GenH5.menu.pnum.GENERIC_H533CEUX.build.product_line=STM32H533xx +GenH5.menu.pnum.GENERIC_H533CEUX.build.variant=STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U) + diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/generic_clock.c b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/generic_clock.c new file mode 100644 index 0000000000..d330186241 --- /dev/null +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H523CCTX) || defined(ARDUINO_GENERIC_H523CCUX) ||\ + defined(ARDUINO_GENERIC_H523CETX) || defined(ARDUINO_GENERIC_H523CEUX) ||\ + defined(ARDUINO_GENERIC_H533CETX) || defined(ARDUINO_GENERIC_H533CEUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/variant_generic.cpp b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/variant_generic.cpp new file mode 100644 index 0000000000..6945a7b330 --- /dev/null +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/variant_generic.cpp @@ -0,0 +1,71 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H523CCTX) || defined(ARDUINO_GENERIC_H523CCUX) ||\ + defined(ARDUINO_GENERIC_H523CETX) || defined(ARDUINO_GENERIC_H523CEUX) ||\ + defined(ARDUINO_GENERIC_H533CETX) || defined(ARDUINO_GENERIC_H533CEUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_12, // D26 + PB_13, // D27 + PB_14, // D28 + PB_15, // D29 + PC_13, // D30 + PC_14, // D31 + PC_15, // D32 + PH_0, // D33 + PH_1 // D34 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/variant_generic.h b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/variant_generic.h new file mode 100644 index 0000000000..4c9a20e2a5 --- /dev/null +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/variant_generic.h @@ -0,0 +1,190 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB12 26 +#define PB13 27 +#define PB14 28 +#define PB15 29 +#define PC13 30 +#define PC14 31 +#define PC15 32 +#define PH0 33 +#define PH1 34 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 35 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c b/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c new file mode 100644 index 0000000000..d0d4d7bdcb --- /dev/null +++ b/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c @@ -0,0 +1,336 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H523HEYx.xml, STM32H533HEYx.xml + * CubeMX DB release 6.0.110 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_4, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_8, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I3C2)}, + {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI3)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_8, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI1)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_7, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI3)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_0, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H523HEY_H533HEY/PinNamesVar.h b/variants/STM32H5xx/H523HEY_H533HEY/PinNamesVar.h new file mode 100644 index 0000000000..1acdb5135f --- /dev/null +++ b/variants/STM32H5xx/H523HEY_H533HEY/PinNamesVar.h @@ -0,0 +1,58 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_7_ALT1 = PB_7 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H523HEY_H533HEY/boards_entry.txt b/variants/STM32H5xx/H523HEY_H533HEY/boards_entry.txt new file mode 100644 index 0000000000..6db91cdab4 --- /dev/null +++ b/variants/STM32H5xx/H523HEY_H533HEY/boards_entry.txt @@ -0,0 +1,21 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H523HEYx +GenH5.menu.pnum.GENERIC_H523HEYX=Generic H523HEYx +GenH5.menu.pnum.GENERIC_H523HEYX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H523HEYX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523HEYX.build.board=GENERIC_H523HEYX +GenH5.menu.pnum.GENERIC_H523HEYX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523HEYX.build.variant=STM32H5xx/H523HEY_H533HEY + +# Generic H533HEYx +GenH5.menu.pnum.GENERIC_H533HEYX=Generic H533HEYx +GenH5.menu.pnum.GENERIC_H533HEYX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H533HEYX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H533HEYX.build.board=GENERIC_H533HEYX +GenH5.menu.pnum.GENERIC_H533HEYX.build.product_line=STM32H533xx +GenH5.menu.pnum.GENERIC_H533HEYX.build.variant=STM32H5xx/H523HEY_H533HEY + diff --git a/variants/STM32H5xx/H523HEY_H533HEY/generic_clock.c b/variants/STM32H5xx/H523HEY_H533HEY/generic_clock.c new file mode 100644 index 0000000000..4041622d45 --- /dev/null +++ b/variants/STM32H5xx/H523HEY_H533HEY/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H523HEYX) || defined(ARDUINO_GENERIC_H533HEYX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H523HEY_H533HEY/variant_generic.cpp b/variants/STM32H5xx/H523HEY_H533HEY/variant_generic.cpp new file mode 100644 index 0000000000..91112af5ab --- /dev/null +++ b/variants/STM32H5xx/H523HEY_H533HEY/variant_generic.cpp @@ -0,0 +1,60 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H523HEYX) || defined(ARDUINO_GENERIC_H533HEYX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_11, // D9 + PA_12, // D10 + PA_13, // D11 + PA_14, // D12 + PA_15, // D13 + PB_0, // D14/A8 + PB_1, // D15/A9 + PB_3, // D16 + PB_4, // D17 + PB_7, // D18 + PB_8, // D19 + PB_15, // D20 + PC_13, // D21 + PC_14, // D22 + PC_15, // D23 + PH_0, // D24 + PH_1 // D25 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 14, // A8, PB0 + 15 // A9, PB1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H523HEY_H533HEY/variant_generic.h b/variants/STM32H5xx/H523HEY_H533HEY/variant_generic.h new file mode 100644 index 0000000000..71fbc95e3b --- /dev/null +++ b/variants/STM32H5xx/H523HEY_H533HEY/variant_generic.h @@ -0,0 +1,172 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA11 9 +#define PA12 10 +#define PA13 11 +#define PA14 12 +#define PA15 13 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB3 16 +#define PB4 17 +#define PB7 18 +#define PB8 19 +#define PB15 20 +#define PC13 21 +#define PC14 22 +#define PC15 23 +#define PH0 24 +#define PH1 25 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB4 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA8 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c b/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c new file mode 100644 index 0000000000..8c8a4b8f88 --- /dev/null +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c @@ -0,0 +1,562 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H523RCTx.xml, STM32H523RETx.xml + * STM32H533RETx.xml + * CubeMX DB release 6.0.110 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_4, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PC_7, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PC_11, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_8, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I3C2)}, + {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PB_5, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PC_6, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PC_10, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_5, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI3)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_8, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI1)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1_ALT1, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_7, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI3)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_0, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/PinNamesVar.h b/variants/STM32H5xx/H523R(C-E)T_H533RET/PinNamesVar.h new file mode 100644 index 0000000000..248f1e4e24 --- /dev/null +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/PinNamesVar.h @@ -0,0 +1,79 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/boards_entry.txt b/variants/STM32H5xx/H523R(C-E)T_H533RET/boards_entry.txt new file mode 100644 index 0000000000..0c7f456d5b --- /dev/null +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/boards_entry.txt @@ -0,0 +1,29 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H523RCTx +GenH5.menu.pnum.GENERIC_H523RCTX=Generic H523RCTx +GenH5.menu.pnum.GENERIC_H523RCTX.upload.maximum_size=262144 +GenH5.menu.pnum.GENERIC_H523RCTX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523RCTX.build.board=GENERIC_H523RCTX +GenH5.menu.pnum.GENERIC_H523RCTX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523RCTX.build.variant=STM32H5xx/H523R(C-E)T_H533RET + +# Generic H523RETx +GenH5.menu.pnum.GENERIC_H523RETX=Generic H523RETx +GenH5.menu.pnum.GENERIC_H523RETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H523RETX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523RETX.build.board=GENERIC_H523RETX +GenH5.menu.pnum.GENERIC_H523RETX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523RETX.build.variant=STM32H5xx/H523R(C-E)T_H533RET + +# Generic H533RETx +GenH5.menu.pnum.GENERIC_H533RETX=Generic H533RETx +GenH5.menu.pnum.GENERIC_H533RETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H533RETX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H533RETX.build.board=GENERIC_H533RETX +GenH5.menu.pnum.GENERIC_H533RETX.build.product_line=STM32H533xx +GenH5.menu.pnum.GENERIC_H533RETX.build.variant=STM32H5xx/H523R(C-E)T_H533RET + diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/generic_clock.c b/variants/STM32H5xx/H523R(C-E)T_H533RET/generic_clock.c new file mode 100644 index 0000000000..03d7d6e862 --- /dev/null +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H523RCTX) || defined(ARDUINO_GENERIC_H523RETX) ||\ + defined(ARDUINO_GENERIC_H533RETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_generic.cpp b/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_generic.cpp new file mode 100644 index 0000000000..0015ac9e78 --- /dev/null +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_generic.cpp @@ -0,0 +1,90 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H523RCTX) || defined(ARDUINO_GENERIC_H523RETX) ||\ + defined(ARDUINO_GENERIC_H533RETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_12, // D26 + PB_13, // D27 + PB_14, // D28 + PB_15, // D29 + PC_0, // D30/A10 + PC_1, // D31/A11 + PC_2, // D32/A12 + PC_3, // D33/A13 + PC_4, // D34/A14 + PC_5, // D35/A15 + PC_6, // D36 + PC_7, // D37 + PC_8, // D38 + PC_9, // D39 + PC_10, // D40 + PC_11, // D41 + PC_12, // D42 + PC_13, // D43 + PC_14, // D44 + PC_15, // D45 + PD_2, // D46 + PH_0, // D47 + PH_1 // D48 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 30, // A10, PC0 + 31, // A11, PC1 + 32, // A12, PC2 + 33, // A13, PC3 + 34, // A14, PC4 + 35 // A15, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_generic.h b/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_generic.h new file mode 100644 index 0000000000..62e4dc8bf7 --- /dev/null +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_generic.h @@ -0,0 +1,222 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB12 26 +#define PB13 27 +#define PB14 28 +#define PB15 29 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 36 +#define PC7 37 +#define PC8 38 +#define PC9 39 +#define PC10 40 +#define PC11 41 +#define PC12 42 +#define PC13 43 +#define PC14 44 +#define PC15 45 +#define PD2 46 +#define PH0 47 +#define PH1 48 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 49 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// SDMMC signals not available +#define SDMMC_CDIR_NA + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c new file mode 100644 index 0000000000..c4a69bf48a --- /dev/null +++ b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c @@ -0,0 +1,651 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H523VCIx.xml, STM32H523VCTx.xml + * STM32H523VEIx.xml, STM32H523VETx.xml + * STM32H533VEIx.xml, STM32H533VETx.xml + * CubeMX DB release 6.0.110 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_4, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PC_7, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PC_11, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PD_7, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_8, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I3C2)}, + {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PB_5, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PC_6, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PC_10, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PD_6, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_5, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI3)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_8, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI1)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1_ALT1, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_7, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI3)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_0, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PinNamesVar.h b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PinNamesVar.h new file mode 100644 index 0000000000..f8229cff78 --- /dev/null +++ b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PinNamesVar.h @@ -0,0 +1,79 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/boards_entry.txt b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/boards_entry.txt new file mode 100644 index 0000000000..6d4a627f8d --- /dev/null +++ b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/boards_entry.txt @@ -0,0 +1,53 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H523VCIx +GenH5.menu.pnum.GENERIC_H523VCIX=Generic H523VCIx +GenH5.menu.pnum.GENERIC_H523VCIX.upload.maximum_size=262144 +GenH5.menu.pnum.GENERIC_H523VCIX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523VCIX.build.board=GENERIC_H523VCIX +GenH5.menu.pnum.GENERIC_H523VCIX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523VCIX.build.variant=STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T) + +# Generic H523VCTx +GenH5.menu.pnum.GENERIC_H523VCTX=Generic H523VCTx +GenH5.menu.pnum.GENERIC_H523VCTX.upload.maximum_size=262144 +GenH5.menu.pnum.GENERIC_H523VCTX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523VCTX.build.board=GENERIC_H523VCTX +GenH5.menu.pnum.GENERIC_H523VCTX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523VCTX.build.variant=STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T) + +# Generic H523VEIx +GenH5.menu.pnum.GENERIC_H523VEIX=Generic H523VEIx +GenH5.menu.pnum.GENERIC_H523VEIX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H523VEIX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523VEIX.build.board=GENERIC_H523VEIX +GenH5.menu.pnum.GENERIC_H523VEIX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523VEIX.build.variant=STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T) + +# Generic H523VETx +GenH5.menu.pnum.GENERIC_H523VETX=Generic H523VETx +GenH5.menu.pnum.GENERIC_H523VETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H523VETX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523VETX.build.board=GENERIC_H523VETX +GenH5.menu.pnum.GENERIC_H523VETX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523VETX.build.variant=STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T) + +# Generic H533VEIx +GenH5.menu.pnum.GENERIC_H533VEIX=Generic H533VEIx +GenH5.menu.pnum.GENERIC_H533VEIX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H533VEIX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H533VEIX.build.board=GENERIC_H533VEIX +GenH5.menu.pnum.GENERIC_H533VEIX.build.product_line=STM32H533xx +GenH5.menu.pnum.GENERIC_H533VEIX.build.variant=STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T) + +# Generic H533VETx +GenH5.menu.pnum.GENERIC_H533VETX=Generic H533VETx +GenH5.menu.pnum.GENERIC_H533VETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H533VETX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H533VETX.build.board=GENERIC_H533VETX +GenH5.menu.pnum.GENERIC_H533VETX.build.product_line=STM32H533xx +GenH5.menu.pnum.GENERIC_H533VETX.build.variant=STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T) + diff --git a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/generic_clock.c b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/generic_clock.c new file mode 100644 index 0000000000..10e41b336a --- /dev/null +++ b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H523VCIX) || defined(ARDUINO_GENERIC_H523VCTX) ||\ + defined(ARDUINO_GENERIC_H523VEIX) || defined(ARDUINO_GENERIC_H523VETX) ||\ + defined(ARDUINO_GENERIC_H533VEIX) || defined(ARDUINO_GENERIC_H533VETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/variant_generic.cpp b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/variant_generic.cpp new file mode 100644 index 0000000000..3343493919 --- /dev/null +++ b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/variant_generic.cpp @@ -0,0 +1,122 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H523VCIX) || defined(ARDUINO_GENERIC_H523VCTX) ||\ + defined(ARDUINO_GENERIC_H523VEIX) || defined(ARDUINO_GENERIC_H523VETX) ||\ + defined(ARDUINO_GENERIC_H533VEIX) || defined(ARDUINO_GENERIC_H533VETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A10 + PC_1, // D32/A11 + PC_2, // D33/A12 + PC_3, // D34/A13 + PC_4, // D35/A14 + PC_5, // D36/A15 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_2, // D64 + PE_3, // D65 + PE_4, // D66 + PE_5, // D67 + PE_6, // D68 + PE_7, // D69 + PE_8, // D70 + PE_9, // D71 + PE_10, // D72 + PE_11, // D73 + PE_12, // D74 + PE_13, // D75 + PE_14, // D76 + PE_15, // D77 + PH_0, // D78 + PH_1 // D79 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 31, // A10, PC0 + 32, // A11, PC1 + 33, // A12, PC2 + 34, // A13, PC3 + 35, // A14, PC4 + 36 // A15, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/variant_generic.h b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/variant_generic.h new file mode 100644 index 0000000000..1f35154d1e --- /dev/null +++ b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/variant_generic.h @@ -0,0 +1,250 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE2 64 +#define PE3 65 +#define PE4 66 +#define PE5 67 +#define PE6 68 +#define PE7 69 +#define PE8 70 +#define PE9 71 +#define PE10 72 +#define PE11 73 +#define PE12 74 +#define PE13 75 +#define PE14 76 +#define PE15 77 +#define PH0 78 +#define PH1 79 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 80 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c new file mode 100644 index 0000000000..5b518519ba --- /dev/null +++ b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c @@ -0,0 +1,686 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32H523ZCJx.xml, STM32H523ZCTx.xml + * STM32H523ZEJx.xml, STM32H523ZETx.xml + * STM32H533ZEJx.xml, STM32H533ZETx.xml + * CubeMX DB release 6.0.110 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** I3C *** + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SDA[] = { + {PB_4, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PB_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_9, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PC_7, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PC_11, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PD_7, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PD_13, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_0, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PF_15, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I3C_MODULE_ENABLED +WEAK const PinMap PinMap_I3C_SCL[] = { + {PA_8, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I3C2)}, + {PB_3, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PB_5, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PB_6, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PB_8, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {PC_6, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF10_I3C2)}, + {PC_10, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PD_6, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PD_12, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PF_1, I3C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C2)}, + {PF_5, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I3C1)}, + {PG_7, I3C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I3C1)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_10_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_12, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 3, 0)}, // TIM8_CH3 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 2, 0)}, // TIM8_CH2 + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT2, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_4, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_9_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_3_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_5, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_6_ALT1, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_10_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_15, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11_ALT1, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART6)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI3)}, + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_8, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI1)}, + {PB_15_ALT1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1_ALT1, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PG_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PG_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_7, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_7, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_SPI3)}, + {PB_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_0, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_9, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_3, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_5, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PG_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PG_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {PG_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_8, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PB_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {PD_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {PD_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PA_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PB_13, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {PG_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {PG_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {PG_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {PG_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CKIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SDMMC1)}, // SDMMC1_CDIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR + {NC, NP, 0} +}; +#endif + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PinNamesVar.h b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PinNamesVar.h new file mode 100644 index 0000000000..f8229cff78 --- /dev/null +++ b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PinNamesVar.h @@ -0,0 +1,79 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PA_2_ALT2 = PA_2 | ALT2, +PA_3_ALT1 = PA_3 | ALT1, +PA_3_ALT2 = PA_3 | ALT2, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_12_ALT1 = PA_12 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_5_ALT1 = PB_5 | ALT1, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_14_ALT2 = PB_14 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_0_ALT1 = PC_0 | ALT1, +PC_1_ALT1 = PC_1 | ALT1, +PC_2_ALT1 = PC_2 | ALT1, +PC_3_ALT1 = PC_3 | ALT1, +PC_4_ALT1 = PC_4 | ALT1, +PC_5_ALT1 = PC_5 | ALT1, +PC_6_ALT1 = PC_6 | ALT1, +PC_7_ALT1 = PC_7 | ALT1, +PC_8_ALT1 = PC_8 | ALT1, +PC_9_ALT1 = PC_9 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PD_2, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PD_3, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, +#endif diff --git a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/boards_entry.txt b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/boards_entry.txt new file mode 100644 index 0000000000..5c617ceba5 --- /dev/null +++ b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/boards_entry.txt @@ -0,0 +1,53 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic H523ZCJx +GenH5.menu.pnum.GENERIC_H523ZCJX=Generic H523ZCJx +GenH5.menu.pnum.GENERIC_H523ZCJX.upload.maximum_size=262144 +GenH5.menu.pnum.GENERIC_H523ZCJX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523ZCJX.build.board=GENERIC_H523ZCJX +GenH5.menu.pnum.GENERIC_H523ZCJX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523ZCJX.build.variant=STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T) + +# Generic H523ZCTx +GenH5.menu.pnum.GENERIC_H523ZCTX=Generic H523ZCTx +GenH5.menu.pnum.GENERIC_H523ZCTX.upload.maximum_size=262144 +GenH5.menu.pnum.GENERIC_H523ZCTX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523ZCTX.build.board=GENERIC_H523ZCTX +GenH5.menu.pnum.GENERIC_H523ZCTX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523ZCTX.build.variant=STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T) + +# Generic H523ZEJx +GenH5.menu.pnum.GENERIC_H523ZEJX=Generic H523ZEJx +GenH5.menu.pnum.GENERIC_H523ZEJX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H523ZEJX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523ZEJX.build.board=GENERIC_H523ZEJX +GenH5.menu.pnum.GENERIC_H523ZEJX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523ZEJX.build.variant=STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T) + +# Generic H523ZETx +GenH5.menu.pnum.GENERIC_H523ZETX=Generic H523ZETx +GenH5.menu.pnum.GENERIC_H523ZETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H523ZETX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H523ZETX.build.board=GENERIC_H523ZETX +GenH5.menu.pnum.GENERIC_H523ZETX.build.product_line=STM32H523xx +GenH5.menu.pnum.GENERIC_H523ZETX.build.variant=STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T) + +# Generic H533ZEJx +GenH5.menu.pnum.GENERIC_H533ZEJX=Generic H533ZEJx +GenH5.menu.pnum.GENERIC_H533ZEJX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H533ZEJX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H533ZEJX.build.board=GENERIC_H533ZEJX +GenH5.menu.pnum.GENERIC_H533ZEJX.build.product_line=STM32H533xx +GenH5.menu.pnum.GENERIC_H533ZEJX.build.variant=STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T) + +# Generic H533ZETx +GenH5.menu.pnum.GENERIC_H533ZETX=Generic H533ZETx +GenH5.menu.pnum.GENERIC_H533ZETX.upload.maximum_size=524288 +GenH5.menu.pnum.GENERIC_H533ZETX.upload.maximum_data_size=278528 +GenH5.menu.pnum.GENERIC_H533ZETX.build.board=GENERIC_H533ZETX +GenH5.menu.pnum.GENERIC_H533ZETX.build.product_line=STM32H533xx +GenH5.menu.pnum.GENERIC_H533ZETX.build.variant=STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T) + diff --git a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/generic_clock.c b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/generic_clock.c new file mode 100644 index 0000000000..7e9e22fa16 --- /dev/null +++ b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H523ZCJX) || defined(ARDUINO_GENERIC_H523ZCTX) ||\ + defined(ARDUINO_GENERIC_H523ZEJX) || defined(ARDUINO_GENERIC_H523ZETX) ||\ + defined(ARDUINO_GENERIC_H533ZEJX) || defined(ARDUINO_GENERIC_H533ZETX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/variant_generic.cpp b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/variant_generic.cpp new file mode 100644 index 0000000000..a1589099a7 --- /dev/null +++ b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/variant_generic.cpp @@ -0,0 +1,158 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H523ZCJX) || defined(ARDUINO_GENERIC_H523ZCTX) ||\ + defined(ARDUINO_GENERIC_H523ZEJX) || defined(ARDUINO_GENERIC_H523ZETX) ||\ + defined(ARDUINO_GENERIC_H533ZEJX) || defined(ARDUINO_GENERIC_H533ZETX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_0, // D31/A10 + PC_1, // D32/A11 + PC_2, // D33/A12 + PC_3, // D34/A13 + PC_4, // D35/A14 + PC_5, // D36/A15 + PC_6, // D37 + PC_7, // D38 + PC_8, // D39 + PC_9, // D40 + PC_10, // D41 + PC_11, // D42 + PC_12, // D43 + PC_13, // D44 + PC_14, // D45 + PC_15, // D46 + PD_0, // D47 + PD_1, // D48 + PD_2, // D49 + PD_3, // D50 + PD_4, // D51 + PD_5, // D52 + PD_6, // D53 + PD_7, // D54 + PD_8, // D55 + PD_9, // D56 + PD_10, // D57 + PD_11, // D58 + PD_12, // D59 + PD_13, // D60 + PD_14, // D61 + PD_15, // D62 + PE_0, // D63 + PE_2, // D64 + PE_3, // D65 + PE_4, // D66 + PE_5, // D67 + PE_6, // D68 + PE_7, // D69 + PE_8, // D70 + PE_9, // D71 + PE_10, // D72 + PE_11, // D73 + PE_12, // D74 + PE_13, // D75 + PE_14, // D76 + PE_15, // D77 + PF_0, // D78 + PF_1, // D79 + PF_2, // D80 + PF_3, // D81 + PF_4, // D82 + PF_5, // D83 + PF_6, // D84 + PF_7, // D85 + PF_8, // D86 + PF_9, // D87 + PF_10, // D88 + PF_11, // D89/A16 + PF_12, // D90/A17 + PF_13, // D91/A18 + PF_14, // D92/A19 + PF_15, // D93 + PG_0, // D94 + PG_1, // D95 + PG_2, // D96 + PG_3, // D97 + PG_4, // D98 + PG_5, // D99 + PG_6, // D100 + PG_7, // D101 + PG_8, // D102 + PG_9, // D103 + PG_10, // D104 + PG_11, // D105 + PG_12, // D106 + PG_13, // D107 + PG_14, // D108 + PG_15, // D109 + PH_0, // D110 + PH_1 // D111 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 31, // A10, PC0 + 32, // A11, PC1 + 33, // A12, PC2 + 34, // A13, PC3 + 35, // A14, PC4 + 36, // A15, PC5 + 89, // A16, PF11 + 90, // A17, PF12 + 91, // A18, PF13 + 92 // A19, PF14 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/variant_generic.h b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/variant_generic.h new file mode 100644 index 0000000000..0a17ddd2b1 --- /dev/null +++ b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/variant_generic.h @@ -0,0 +1,282 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 37 +#define PC7 38 +#define PC8 39 +#define PC9 40 +#define PC10 41 +#define PC11 42 +#define PC12 43 +#define PC13 44 +#define PC14 45 +#define PC15 46 +#define PD0 47 +#define PD1 48 +#define PD2 49 +#define PD3 50 +#define PD4 51 +#define PD5 52 +#define PD6 53 +#define PD7 54 +#define PD8 55 +#define PD9 56 +#define PD10 57 +#define PD11 58 +#define PD12 59 +#define PD13 60 +#define PD14 61 +#define PD15 62 +#define PE0 63 +#define PE2 64 +#define PE3 65 +#define PE4 66 +#define PE5 67 +#define PE6 68 +#define PE7 69 +#define PE8 70 +#define PE9 71 +#define PE10 72 +#define PE11 73 +#define PE12 74 +#define PE13 75 +#define PE14 76 +#define PE15 77 +#define PF0 78 +#define PF1 79 +#define PF2 80 +#define PF3 81 +#define PF4 82 +#define PF5 83 +#define PF6 84 +#define PF7 85 +#define PF8 86 +#define PF9 87 +#define PF10 88 +#define PF11 PIN_A16 +#define PF12 PIN_A17 +#define PF13 PIN_A18 +#define PF14 PIN_A19 +#define PF15 93 +#define PG0 94 +#define PG1 95 +#define PG2 96 +#define PG3 97 +#define PG4 98 +#define PG5 99 +#define PG6 100 +#define PG7 101 +#define PG8 102 +#define PG9 103 +#define PG10 104 +#define PG11 105 +#define PG12 106 +#define PG13 107 +#define PG14 108 +#define PG15 109 +#define PH0 110 +#define PH1 111 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 112 +#define NUM_ANALOG_INPUTS 20 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4_ALT1 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PB8 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB0 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB10 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 4 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA0 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c index 84de66853c..cc60de5b5b 100644 --- a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c +++ b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562AGIx.xml, STM32H562AIIx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c index f3dd1f2df9..7aa2efc1ab 100644 --- a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H562IGKx.xml, STM32H562IGTx.xml * STM32H562IIKx.xml, STM32H562IITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c index 4b2c91c25b..50218207e8 100644 --- a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGTx.xml, STM32H562RITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c index bdb471f39d..58d74a76e9 100644 --- a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGVx.xml, STM32H562RIVx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c index 21459abe93..a31b92c9e4 100644 --- a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562VGTx.xml, STM32H562VITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c index bc2c2a3718..f6da0d6c92 100644 --- a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562ZGTx.xml, STM32H562ZITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c b/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c index cd0b480efc..9959896446 100644 --- a/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563AGIx.xml, STM32H563AIIx.xml * STM32H573AIIx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c index d0f602895e..70617d4f51 100644 --- a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563AIIxQ.xml, STM32H573AIIxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c index 921f4b3d82..1a82016e0c 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H563IGKx.xml, STM32H563IGTx.xml * STM32H563IIKx.xml, STM32H563IITx.xml * STM32H573IIKx.xml, STM32H573IITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c index e721763c88..f28d919005 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563IIKxQ.xml, STM32H573IIKxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c index 22ca02f65b..8d7c9f2572 100644 --- a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563IITxQ.xml, STM32H573IITxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c index eb57d1a9d0..76469ccabf 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563MIYxQ.xml, STM32H573MIYxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c index 9d232a66f6..2929fd97bc 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563RGTx.xml, STM32H563RITx.xml * STM32H573RITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c index e2cde3d7fa..291da0b18c 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563RGVx.xml, STM32H563RIVx.xml * STM32H573RIVx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c index 9f862af7db..df7012ba01 100644 --- a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563VGTx.xml, STM32H563VITx.xml * STM32H573VITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c index ecc7e86ec6..7041057d42 100644 --- a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563VITxQ.xml, STM32H573VITxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -427,7 +427,34 @@ WEAK const PinMap PinMap_CAN_TD[] = { }; #endif -//*** No ETHERNET *** +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {NC, NP, 0} +}; +#endif //*** OCTOSPI *** diff --git a/variants/STM32H5xx/H563VITxQ_H573VITxQ/variant_generic.h b/variants/STM32H5xx/H563VITxQ_H573VITxQ/variant_generic.h index 43598b1e2d..f48587c4f8 100644 --- a/variants/STM32H5xx/H563VITxQ_H573VITxQ/variant_generic.h +++ b/variants/STM32H5xx/H563VITxQ_H573VITxQ/variant_generic.h @@ -216,6 +216,9 @@ #if !defined(HAL_DAC_MODULE_DISABLED) #define HAL_DAC_MODULE_ENABLED #endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif #if !defined(HAL_OSPI_MODULE_DISABLED) #define HAL_OSPI_MODULE_ENABLED #endif diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c index 02090103b2..3644280010 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563ZGTx.xml, STM32H563ZITx.xml * STM32H573ZITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c index 2e6f120f32..5e44f93004 100644 --- a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563ZITxQ.xml, STM32H573ZITxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -483,7 +483,38 @@ WEAK const PinMap PinMap_CAN_TD[] = { }; #endif -//*** No ETHERNET *** +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +WEAK const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK + {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV + {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV + {PA_9, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_ER + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PB_15, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {NC, NP, 0} +}; +#endif //*** OCTOSPI *** diff --git a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/variant_generic.h b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/variant_generic.h index 802ba6287b..d9e873676d 100644 --- a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/variant_generic.h +++ b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/variant_generic.h @@ -251,6 +251,9 @@ #if !defined(HAL_DAC_MODULE_DISABLED) #define HAL_DAC_MODULE_ENABLED #endif +#if !defined(HAL_ETH_MODULE_DISABLED) + #define HAL_ETH_MODULE_ENABLED +#endif #if !defined(HAL_OSPI_MODULE_DISABLED) #define HAL_OSPI_MODULE_ENABLED #endif From ce31fedea47a76c1af8b691d1f0e30e91a2f8e0c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 8 Apr 2024 09:48:31 +0200 Subject: [PATCH 6/6] chore(h5): add cmake support to new variants Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 6 ++-- .../CMakeLists.txt | 31 +++++++++++++++++++ .../STM32H5xx/H523HEY_H533HEY/CMakeLists.txt | 31 +++++++++++++++++++ .../H523R(C-E)T_H533RET/CMakeLists.txt | 31 +++++++++++++++++++ .../CMakeLists.txt | 31 +++++++++++++++++++ .../CMakeLists.txt | 31 +++++++++++++++++++ 6 files changed, 158 insertions(+), 3 deletions(-) create mode 100644 variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/CMakeLists.txt create mode 100644 variants/STM32H5xx/H523HEY_H533HEY/CMakeLists.txt create mode 100644 variants/STM32H5xx/H523R(C-E)T_H533RET/CMakeLists.txt create mode 100644 variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/CMakeLists.txt create mode 100644 variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/CMakeLists.txt diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index af691d12f5..e09e54a069 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -102957,13 +102957,13 @@ set(NUCLEO_L496ZG-P_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4x set(NUCLEO_L496ZG-P_MAXSIZE 1048576) set(NUCLEO_L496ZG-P_MAXDATASIZE 327680) set(NUCLEO_L496ZG-P_MCU cortex-m4) -set(NUCLEO_L496ZG-P_FPCONF "fpv4-sp-d16-") +set(NUCLEO_L496ZG-P_FPCONF "fpv4-sp-d16-hard") add_library(NUCLEO_L496ZG-P INTERFACE) target_compile_options(NUCLEO_L496ZG-P INTERFACE "SHELL:-DSTM32L496xx " "SHELL:" "SHELL:" - "SHELL:-mfpu=fpv4-sp-d16 " + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L496ZG-P_MCU} ) target_compile_definitions(NUCLEO_L496ZG-P INTERFACE @@ -102987,7 +102987,7 @@ target_link_options(NUCLEO_L496ZG-P INTERFACE "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=1048576" "LINKER:--defsym=LD_MAX_DATA_SIZE=327680" - "SHELL:-mfpu=fpv4-sp-d16 " + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${NUCLEO_L496ZG-P_MCU} ) diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/CMakeLists.txt b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H523HEY_H533HEY/CMakeLists.txt b/variants/STM32H5xx/H523HEY_H533HEY/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H523HEY_H533HEY/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/CMakeLists.txt b/variants/STM32H5xx/H523R(C-E)T_H533RET/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/CMakeLists.txt b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/CMakeLists.txt b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) +