From e268a5a632668c941c97efb81e844d25739fc1fc Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 29 Nov 2023 09:41:01 +0100 Subject: [PATCH 1/2] system(F4) update STM32F4xx HAL Drivers to v1.8.2 Included in STM32CubeF4 FW v1.28.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 436 +- .../Inc/stm32f4xx_hal_adc.h | 58 +- .../Inc/stm32f4xx_hal_adc_ex.h | 30 +- .../Inc/stm32f4xx_hal_can.h | 53 +- .../Inc/stm32f4xx_hal_cec.h | 136 +- .../Inc/stm32f4xx_hal_cortex.h | 1 + .../Inc/stm32f4xx_hal_crc.h | 2 +- .../Inc/stm32f4xx_hal_dac.h | 32 +- .../Inc/stm32f4xx_hal_dac_ex.h | 9 +- .../Inc/stm32f4xx_hal_def.h | 2 + .../Inc/stm32f4xx_hal_dfsdm.h | 24 +- .../Inc/stm32f4xx_hal_dsi.h | 12 +- .../Inc/stm32f4xx_hal_eth.h | 42 +- .../Inc/stm32f4xx_hal_fmpi2c.h | 143 +- .../Inc/stm32f4xx_hal_fmpi2c_ex.h | 4 +- .../Inc/stm32f4xx_hal_fmpsmbus.h | 139 +- .../Inc/stm32f4xx_hal_fmpsmbus_ex.h | 6 +- .../Inc/stm32f4xx_hal_hcd.h | 26 +- .../Inc/stm32f4xx_hal_irda.h | 4 +- .../Inc/stm32f4xx_hal_lptim.h | 8 +- .../Inc/stm32f4xx_hal_ltdc.h | 16 +- .../Inc/stm32f4xx_hal_nand.h | 45 +- .../Inc/stm32f4xx_hal_nor.h | 2 +- .../Inc/stm32f4xx_hal_pcd.h | 12 +- .../Inc/stm32f4xx_hal_pcd_ex.h | 14 +- .../Inc/stm32f4xx_hal_pwr.h | 13 +- .../Inc/stm32f4xx_hal_rcc.h | 5 +- .../Inc/stm32f4xx_hal_rcc_ex.h | 108 +- .../Inc/stm32f4xx_hal_rng.h | 6 +- .../Inc/stm32f4xx_hal_rtc.h | 9 +- .../Inc/stm32f4xx_hal_rtc_ex.h | 16 +- .../Inc/stm32f4xx_hal_sai.h | 4 +- .../Inc/stm32f4xx_hal_sai_ex.h | 4 +- .../Inc/stm32f4xx_hal_smartcard.h | 4 +- .../Inc/stm32f4xx_hal_smbus.h | 36 +- .../Inc/stm32f4xx_hal_spdifrx.h | 56 +- .../Inc/stm32f4xx_hal_sram.h | 2 +- .../Inc/stm32f4xx_hal_tim.h | 93 +- .../Inc/stm32f4xx_hal_tim_ex.h | 19 +- .../Inc/stm32f4xx_hal_uart.h | 33 +- .../Inc/stm32f4xx_hal_usart.h | 6 +- .../Inc/stm32f4xx_ll_adc.h | 51 +- .../Inc/stm32f4xx_ll_cortex.h | 10 + .../Inc/stm32f4xx_ll_crc.h | 4 +- .../Inc/stm32f4xx_ll_dac.h | 138 +- .../Inc/stm32f4xx_ll_fmc.h | 4 +- .../Inc/stm32f4xx_ll_fmpi2c.h | 135 +- .../Inc/stm32f4xx_ll_fsmc.h | 2 +- .../Inc/stm32f4xx_ll_i2c.h | 44 +- .../Inc/stm32f4xx_ll_lptim.h | 90 +- .../Inc/stm32f4xx_ll_rng.h | 19 +- .../Inc/stm32f4xx_ll_rtc.h | 22 +- .../Inc/stm32f4xx_ll_sdmmc.h | 8 +- .../Inc/stm32f4xx_ll_tim.h | 177 +- .../Inc/stm32f4xx_ll_usart.h | 220 +- .../Inc/stm32f4xx_ll_usb.h | 250 +- .../STM32F4xx_HAL_Driver/Release_Notes.html | 15646 +++++----------- .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c | 7 +- .../Src/stm32f4xx_hal_adc.c | 260 +- .../Src/stm32f4xx_hal_adc_ex.c | 134 +- .../Src/stm32f4xx_hal_can.c | 92 +- .../Src/stm32f4xx_hal_cec.c | 57 +- .../Src/stm32f4xx_hal_cortex.c | 10 + .../Src/stm32f4xx_hal_crc.c | 4 +- .../Src/stm32f4xx_hal_cryp.c | 126 +- .../Src/stm32f4xx_hal_dac.c | 127 +- .../Src/stm32f4xx_hal_dac_ex.c | 43 +- .../Src/stm32f4xx_hal_dfsdm.c | 28 +- .../Src/stm32f4xx_hal_dma2d.c | 22 +- .../Src/stm32f4xx_hal_dsi.c | 379 +- .../Src/stm32f4xx_hal_eth.c | 85 +- .../Src/stm32f4xx_hal_exti.c | 8 +- .../Src/stm32f4xx_hal_fmpi2c.c | 1509 +- .../Src/stm32f4xx_hal_fmpsmbus.c | 209 +- .../Src/stm32f4xx_hal_hash.c | 2 +- .../Src/stm32f4xx_hal_hcd.c | 757 +- .../Src/stm32f4xx_hal_i2c.c | 251 +- .../Src/stm32f4xx_hal_irda.c | 19 +- .../Src/stm32f4xx_hal_lptim.c | 24 +- .../Src/stm32f4xx_hal_ltdc.c | 8 +- .../Src/stm32f4xx_hal_ltdc_ex.c | 21 +- .../Src/stm32f4xx_hal_nand.c | 104 +- .../Src/stm32f4xx_hal_nor.c | 208 +- .../Src/stm32f4xx_hal_pcd.c | 98 +- .../Src/stm32f4xx_hal_pcd_ex.c | 22 +- .../Src/stm32f4xx_hal_pwr.c | 51 +- .../Src/stm32f4xx_hal_qspi.c | 12 +- .../Src/stm32f4xx_hal_rcc.c | 4 +- .../Src/stm32f4xx_hal_rcc_ex.c | 24 + .../Src/stm32f4xx_hal_rng.c | 29 +- .../Src/stm32f4xx_hal_rtc.c | 94 +- .../Src/stm32f4xx_hal_rtc_ex.c | 41 +- .../Src/stm32f4xx_hal_sai.c | 28 +- .../Src/stm32f4xx_hal_sai_ex.c | 4 +- .../Src/stm32f4xx_hal_sd.c | 22 +- .../Src/stm32f4xx_hal_sdram.c | 36 +- .../Src/stm32f4xx_hal_smartcard.c | 21 +- .../Src/stm32f4xx_hal_smbus.c | 22 +- .../Src/stm32f4xx_hal_spdifrx.c | 56 +- .../Src/stm32f4xx_hal_spi.c | 132 +- .../Src/stm32f4xx_hal_sram.c | 40 +- .../Src/stm32f4xx_hal_tim.c | 189 +- .../Src/stm32f4xx_hal_tim_ex.c | 58 +- ...tm32f4xx_hal_timebase_rtc_alarm_template.c | 8 +- ...m32f4xx_hal_timebase_rtc_wakeup_template.c | 8 +- .../Src/stm32f4xx_hal_timebase_tim_template.c | 2 +- .../Src/stm32f4xx_hal_uart.c | 174 +- .../Src/stm32f4xx_hal_usart.c | 26 +- .../Src/stm32f4xx_ll_adc.c | 116 +- .../Src/stm32f4xx_ll_crc.c | 2 +- .../Src/stm32f4xx_ll_dac.c | 74 +- .../Src/stm32f4xx_ll_fmc.c | 5 +- .../Src/stm32f4xx_ll_fmpi2c.c | 16 +- .../Src/stm32f4xx_ll_fsmc.c | 3 +- .../Src/stm32f4xx_ll_lptim.c | 7 +- .../Src/stm32f4xx_ll_rng.c | 4 +- .../Src/stm32f4xx_ll_rtc.c | 2 +- .../Src/stm32f4xx_ll_tim.c | 71 +- .../Src/stm32f4xx_ll_usart.c | 6 +- .../Src/stm32f4xx_ll_usb.c | 522 +- .../STM32F4xx_HAL_Driver/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../{mini-st.css => mini-st_2020.css} | 365 +- .../STM32F4xx_HAL_Driver/_htmresc/st_logo.png | Bin 18616 -> 0 bytes .../_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 125 files changed, 10293 insertions(+), 15087 deletions(-) create mode 100644 system/Drivers/STM32F4xx_HAL_Driver/_htmresc/favicon.png rename system/Drivers/STM32F4xx_HAL_Driver/_htmresc/{mini-st.css => mini-st_2020.css} (77%) delete mode 100644 system/Drivers/STM32F4xx_HAL_Driver/_htmresc/st_logo.png create mode 100644 system/Drivers/STM32F4xx_HAL_Driver/_htmresc/st_logo_2020.png diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 934f1f971b..aa00ff4d2c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -37,16 +37,12 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#if defined(STM32U5) -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ -#endif /* STM32U5 || STM32H7 || STM32MP1 */ +#endif /* STM32H7 || STM32MP1 */ /** * @} */ @@ -113,6 +109,9 @@ extern "C" { #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 #endif /* STM32U5 */ +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ /** * @} */ @@ -140,7 +139,8 @@ extern "C" { #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) @@ -214,6 +214,11 @@ extern "C" { #endif #endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + /** * @} */ @@ -234,10 +239,12 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ -#if defined(STM32C0) +#if defined(STM32H5) || defined(STM32C0) #else -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ #endif /** * @} @@ -280,7 +287,13 @@ extern "C" { #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -345,7 +358,8 @@ extern "C" { #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #endif @@ -530,6 +544,9 @@ extern "C" { #define OB_USER_nBOOT0 OB_USER_NBOOT0 #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ /** @@ -574,6 +591,106 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + /** * @} */ @@ -641,14 +758,16 @@ extern "C" { #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH @@ -670,9 +789,9 @@ extern "C" { #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32H5) #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ -#endif /* STM32U5 */ +#endif /* STM32U5 || STM32H5 */ #if defined(STM32U5) #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 @@ -686,7 +805,25 @@ extern "C" { */ #if defined(STM32U5) #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB #endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ /** * @} */ @@ -867,7 +1004,8 @@ extern "C" { #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -1005,7 +1143,7 @@ extern "C" { #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1101,6 +1239,26 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32H5) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA */ + #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK @@ -1111,12 +1269,12 @@ extern "C" { #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 */ +#endif /* STM32F7 || STM32H7 || STM32L0 */ /** * @} @@ -1283,7 +1441,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) || defined(STM32MP2) +#if defined(STM32U5) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -1396,30 +1554,40 @@ extern "C" { #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ @@ -1427,6 +1595,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1590,7 +1760,8 @@ extern "C" { #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ - )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1599,8 +1770,10 @@ extern "C" { #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode @@ -1634,16 +1807,21 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ - )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA @@ -1768,6 +1946,17 @@ extern "C" { #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP @@ -1776,6 +1965,8 @@ extern "C" { #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY @@ -1786,6 +1977,7 @@ extern "C" { #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #endif @@ -1794,6 +1986,20 @@ extern "C" { * @} */ +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA */ + +/** + * @} + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ @@ -1819,7 +2025,8 @@ extern "C" { #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback @@ -2076,7 +2283,8 @@ extern "C" { #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) @@ -2248,8 +2456,10 @@ extern "C" { /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ /** * @} */ @@ -2408,7 +2618,9 @@ extern "C" { #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE @@ -2417,8 +2629,12 @@ extern "C" { #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 @@ -2454,8 +2670,8 @@ extern "C" { #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -2959,6 +3175,11 @@ extern "C" { #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE @@ -3423,7 +3644,8 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3568,6 +3790,92 @@ extern "C" { #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE #endif /* STM32U5 */ +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + /** * @} */ @@ -3584,9 +3892,9 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ - defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32C0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3621,6 +3929,13 @@ extern "C" { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER @@ -3639,6 +3954,11 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h index 072ea91f05..c3a94a6e2f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h @@ -21,7 +21,7 @@ #define __STM32F4xx_ADC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -101,11 +101,11 @@ typedef struct If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) - or in Continuous mode (DMA transfer unlimited, whatever number of conversions). - Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). - This parameter can be set to ENABLE or DISABLE. */ -}ADC_InitTypeDef; + or in Continuous mode (DMA transfer unlimited, whatever number of conversions). + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). + This parameter can be set to ENABLE or DISABLE. */ +} ADC_InitTypeDef; @@ -130,7 +130,7 @@ typedef struct sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ -}ADC_ChannelConfTypeDef; +} ADC_ChannelConfTypeDef; /** * @brief ADC Configuration multi-mode structure definition @@ -150,7 +150,7 @@ typedef struct is interrupt mode or in polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ -}ADC_AnalogWDGConfTypeDef; +} ADC_AnalogWDGConfTypeDef; /** * @brief HAL ADC state machine: ADC states definition (bitfields) @@ -217,7 +217,7 @@ typedef struct void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -}ADC_HandleTypeDef; +} ADC_HandleTypeDef; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** @@ -401,7 +401,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ - /** @defgroup ADC_EOCSelection ADC EOC Selection +/** @defgroup ADC_EOCSelection ADC EOC Selection * @{ */ #define ADC_EOC_SEQ_CONV 0x00000000U @@ -562,10 +562,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ /* Initialization/de-initialization functions ***********************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ @@ -580,25 +580,25 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca * @{ */ /* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} @@ -608,8 +608,8 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions *************************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); /** * @} */ @@ -618,7 +618,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * @{ */ /* Peripheral State functions ***************************************************/ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h index b0a4eb724d..8ce8484dda 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h @@ -21,7 +21,7 @@ #define __STM32F4xx_ADC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -106,7 +106,7 @@ typedef struct If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ -}ADC_InjectionConfTypeDef; +} ADC_InjectionConfTypeDef; /** * @brief ADC Configuration multi-mode structure definition @@ -119,7 +119,7 @@ typedef struct This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ -}ADC_MultiModeTypeDef; +} ADC_MultiModeTypeDef; /** * @} @@ -264,20 +264,20 @@ typedef struct */ /* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); /* Peripheral Control functions *************************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode); +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h index aa4a40d0bc..b4c229b209 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h @@ -102,21 +102,25 @@ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ @@ -205,7 +209,11 @@ typedef struct /** * @brief CAN handle Structure definition */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 typedef struct __CAN_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ { CAN_TypeDef *Instance; /*!< Register base address */ @@ -294,11 +302,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to #define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ #define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ #define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ #define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ #define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ @@ -329,7 +337,8 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to #define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ -#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with + silent mode */ /** * @} */ @@ -644,7 +653,8 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)); +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)); HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ @@ -658,7 +668,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca */ /* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig); /** * @} @@ -674,14 +684,16 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox); HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); -uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); -uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo); /** * @} @@ -729,8 +741,8 @@ void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); /** @@ -806,7 +818,8 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); #define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) -#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \ + CAN_TX_MAILBOX2)) #define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) #define IS_CAN_DLC(DLC) ((DLC) <= 8U) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h index 9d6c226a74..2abdc3b5b0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h @@ -48,61 +48,70 @@ extern "C" { typedef struct { uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. - It can be one of @ref CEC_Signal_Free_Time + It can be one of CEC_Signal_Free_Time and belongs to the set {0,...,7} where 0x0 is the default configuration else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, - it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE - or CEC_EXTENDED_TOLERANCE */ + it can be a value of CEC_Tolerance : + it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */ - uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. + uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising + Error stops the reception. CEC_NO_RX_STOP_ON_BRE: reception is not stopped. CEC_RX_STOP_ON_BRE: reception is stopped. */ - uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the + uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an + Error-Bit is generated on the CEC line upon Bit Rising Error detection. CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ - uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the + uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an + Error-Bit is generated on the CEC line upon Long Bit Period Error detection. CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ - uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line + uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an + Error-Bit generation on the CEC line upon an error detected on a broadcast message. - It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values: + It supersedes BREGEN and LBPEGEN bits for a broadcast message error + handling. It can take two values: 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. - a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE - and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. + a) BRE detection: error-bit generation on the CEC line if + BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. b) LBPE detection: error-bit generation on the CEC line if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. - no error-bit generation in case neither a) nor b) are satisfied. Additionally, - there is no error-bit generation in case of Short Bit Period Error detection in - a broadcast message while LSTN bit is set. */ + no error-bit generation in case neither a) nor b) are satisfied. + Additionally, there is no error-bit generation in case of Short Bit + Period Error detection in a broadcast message while LSTN bit is set. */ - uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts. + uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts. CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. - CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ + CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end + of message transmission/reception. */ - uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values: + uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode. + It can take two values: - CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its - own address (OAR). Messages addressed to different destination are ignored. + CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed + to its own address (OAR). Messages addressed to different destination + are ignored. Broadcast messages are always received. - CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own - address (OAR) with positive acknowledge. Messages addressed to different destination - are received, but without interfering with the CEC bus: no acknowledge sent. */ + CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its + own address (OAR) with positive acknowledge. Messages addressed to + different destination are received, but without interfering with the + CEC bus: no acknowledge sent. */ - uint16_t OwnAddress; /*!< Own addresses configuration - This parameter can be a value of @ref CEC_OWN_ADDRESS */ + uint16_t OwnAddress; /*!< Own addresses configuration + This parameter can be a value of CEC_OWN_ADDRESS */ uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ @@ -111,7 +120,8 @@ typedef struct /** * @brief HAL CEC State definition - * @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition). + * @note HAL CEC State value is a combination of 2 different substates: gState and RxState + (see CEC_State_Definition). * - gState contains CEC state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -159,37 +169,37 @@ typedef struct __CEC_HandleTypeDef typedef struct #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ { - CEC_TypeDef *Instance; /*!< CEC registers base address */ + CEC_TypeDef *Instance; /*!< CEC registers base address */ - CEC_InitTypeDef Init; /*!< CEC communication parameters */ + CEC_InitTypeDef Init; /*!< CEC communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ - uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ + uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ - uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ + uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ - HAL_LockTypeDef Lock; /*!< Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management and also related to Tx operations. - This parameter can be a value of @ref HAL_CEC_StateTypeDef */ + This parameter can be a value of HAL_CEC_StateTypeDef */ HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. - This parameter can be a value of @ref HAL_CEC_StateTypeDef */ + This parameter can be a value of HAL_CEC_StateTypeDef */ uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register - in case error is reported */ + in case error is reported */ #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) void (* TxCpltCallback)(struct __CEC_HandleTypeDef - *hcec); /*!< CEC Tx Transfer completed callback */ + *hcec); /*!< CEC Tx Transfer completed callback */ void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, - uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ - void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ + uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ + void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ - void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ - void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ + void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ + void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ #endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */ } CEC_HandleTypeDef; @@ -202,7 +212,7 @@ typedef enum { HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */ HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */ - HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ + HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */ HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */ } HAL_CEC_CallbackIDTypeDef; @@ -212,7 +222,8 @@ typedef enum */ typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, - uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */ + uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed + callback function */ #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ /** * @} @@ -358,16 +369,16 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_OWN_ADDRESS CEC Own Address * @{ */ -#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ -#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ -#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ -#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ -#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ -#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ -#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ -#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ -#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ -#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ +#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ +#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ +#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ +#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ +#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ +#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ +#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ +#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ +#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ +#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ @@ -421,8 +432,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags * @{ */ -#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ - CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) +#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ + CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) /** * @} */ @@ -430,7 +441,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag * @{ */ -#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) +#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) /** * @} */ @@ -438,7 +449,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag * @{ */ -#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) +#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) /** * @} */ @@ -622,7 +633,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) * @retval none */ -#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) +#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \ + (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) /** * @} @@ -660,8 +672,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); */ /* I/O operation functions ***************************************************/ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, - uint8_t *pData, uint32_t Size); -uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); + const uint8_t *pData, uint32_t Size); +uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec); void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); @@ -675,8 +687,8 @@ void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); * @{ */ /* Peripheral State functions ************************************************/ -HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); -uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); +HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec); +uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec); /** * @} */ @@ -731,8 +743,9 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) -#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ - ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) +#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \ + (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ + ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) @@ -789,4 +802,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #endif #endif /* STM32F4xxHAL_CEC_H */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h index 8643779a20..51ab367800 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h @@ -286,6 +286,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ +void HAL_CORTEX_ClearEvent(void); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h index 41edbe381c..ac36ed8c43 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h @@ -157,7 +157,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h index a79ca73a17..3ee217afa0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h @@ -78,19 +78,19 @@ typedef struct __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); #if defined(DAC_CHANNEL2_SUPPORT) - void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); #endif /* DAC_CHANNEL2_SUPPORT */ - void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; @@ -404,7 +404,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); @@ -430,8 +430,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA * @{ */ /* Peripheral Control functions ***********************************************/ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} */ @@ -440,8 +441,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac); +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac); /** * @} @@ -477,4 +478,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); #endif /* STM32F4xx_HAL_DAC_H */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h index db10990297..1bb5ce4563 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h @@ -81,6 +81,7 @@ extern "C" { * @} */ + /** * @} */ @@ -147,19 +148,18 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); #if defined(DAC_CHANNEL2_SUPPORT) -#endif HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); +uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac); +#endif /* DAC_CHANNEL2_SUPPORT */ #if defined(DAC_CHANNEL2_SUPPORT) -#endif void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); - +#endif /* DAC_CHANNEL2_SUPPORT */ /** * @} @@ -202,4 +202,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); #endif #endif /* STM32F4xx_HAL_DAC_EX_H */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h index 59720256c6..7c2f96fbaa 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h @@ -54,7 +54,9 @@ typedef enum /* Exported macro ------------------------------------------------------------*/ +#if !defined(UNUSED) #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ #define HAL_MAX_DELAY 0xFFFFFFFFU diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h index ad39ff6cb2..2b0f1937d0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h @@ -811,11 +811,11 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); @@ -827,7 +827,7 @@ void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); * @{ */ /* Channel state function *****************************************************/ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /** * @} */ @@ -887,16 +887,16 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef* awdParam); + const DFSDM_Filter_AwdParamTypeDef* awdParam); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); @@ -917,8 +917,8 @@ void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); * @{ */ /* Filter state functions *****************************************************/ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h index 6da96681c3..6b51ecb2db 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h @@ -976,7 +976,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI warpper enabling */ \ + /* Delay after an DSI wrapper enabling */ \ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ UNUSED(tmpreg); \ } while(0U) @@ -989,7 +989,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ __IO uint32_t tmpreg = 0x00U; \ CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI warpper disabling*/ \ + /* Delay after an DSI wrapper disabling*/ \ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ UNUSED(tmpreg); \ } while(0U) @@ -1271,10 +1271,10 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\ || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) -#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\ - || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) -#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\ - || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\ + || ((Vsync) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\ + || ((Hsync) == DSI_HSYNC_ACTIVE_LOW)) #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ ((VideoModeType) == DSI_VID_MODE_BURST)) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h index ba5a09bbc8..91fdb62be5 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h @@ -171,6 +171,7 @@ typedef struct * */ +#ifdef HAL_ETH_USE_PTP /** * @brief ETH Timeupdate structure definition */ @@ -182,6 +183,7 @@ typedef struct /** * */ +#endif /* HAL_ETH_USE_PTP */ /** * @brief DMA Receive Descriptors Wrapper structure definition @@ -347,7 +349,6 @@ typedef struct uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers. This parameter can be a value of @ref ETH_Burst_Mode */ - FunctionalState DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */ FunctionalState ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode */ @@ -407,6 +408,7 @@ typedef enum * */ +#ifdef HAL_ETH_USE_PTP /** * @brief HAL ETH PTP Update type enum definition */ @@ -418,13 +420,13 @@ typedef enum /** * */ +#endif /* HAL_ETH_USE_PTP */ /** * @brief ETH Init Structure definition */ typedef struct { - uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ @@ -443,6 +445,7 @@ typedef struct * */ +#ifdef HAL_ETH_USE_PTP /** * @brief ETH PTP Init Structure definition */ @@ -470,6 +473,7 @@ typedef struct /** * */ +#endif /* HAL_ETH_USE_PTP */ /** * @brief HAL State structures definition @@ -538,7 +542,7 @@ typedef struct __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management and also related to Tx operations. This parameter can - be a value of @ref HAL_ETH_StateTypeDef */ + be a value of @ref ETH_State_Codes */ __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine This parameter can be a value of @ref ETH_Error_Code.*/ @@ -595,14 +599,12 @@ typedef enum { HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ - HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ HAL_ETH_ERROR_CB_ID = 0x04U, /*!< ETH Error Callback ID */ HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */ HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */ - } HAL_ETH_CallbackIDTypeDef; /** @@ -1298,7 +1300,7 @@ TDES7 | Transmit Time Stamp High [31:0] * @} */ -/** @defgroup HAL_ETH_StateTypeDef ETH States +/** @defgroup ETH_State_Codes ETH States * @{ */ #define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */ @@ -1902,6 +1904,7 @@ TDES7 | Transmit Time Stamp High [31:0] * enabled @ref ETH_MAC_Interrupts * @retval None */ + #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \ |= (__INTERRUPT__)) @@ -1921,8 +1924,8 @@ TDES7 | Transmit Time Stamp High [31:0] * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts * @retval The state of ETH MAC IT (SET or RESET). */ -#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\ - ( __INTERRUPT__)) == ( __INTERRUPT__)) +#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\ + ( __INTERRUPT__)) == ( __INTERRUPT__)) /*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */ #define ETH_WAKEUP_EXTI_LINE 0x00080000U @@ -1991,6 +1994,7 @@ TDES7 | Transmit Time Stamp High [31:0] (__FLAG__)) == (__FLAG__)) ? SET : RESET) #define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__)) + /** * @} */ @@ -2059,7 +2063,7 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue); HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue); @@ -2095,12 +2099,14 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t /* MAC L2 Packet Filtering APIs **********************************************/ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); -HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig); HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); -HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr); +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, + const uint8_t *pMACAddr); /* MAC Power Down APIs *****************************************************/ -void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig); +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, + const ETH_PowerDownConfigTypeDef *pPowerDownConfig); void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); @@ -2112,11 +2118,11 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi * @{ */ /* Peripheral State functions **************************************************/ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); +HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth); /** * @} */ @@ -2140,5 +2146,3 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); #endif #endif /* STM32F4xx_HAL_ETH_H */ - - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h index 400b923ebb..60ed94b812 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h @@ -119,8 +119,6 @@ typedef enum HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_FMPI2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_FMPI2C_StateTypeDef; @@ -208,6 +206,7 @@ typedef struct __FMPI2C_HandleTypeDef DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */ + HAL_LockTypeDef Lock; /*!< FMPI2C locking object */ __IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */ @@ -218,6 +217,10 @@ typedef struct __FMPI2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */ + __IO uint32_t Devaddress; /*!< FMPI2C Target device address */ + + __IO uint32_t Memaddress; /*!< FMPI2C Target memory address */ + #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) void (* MasterTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Master Tx Transfer completed callback */ @@ -276,7 +279,7 @@ typedef enum typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c); /*!< pointer to an FMPI2C callback function */ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, - uint16_t AddrMatchCode); + uint16_t AddrMatchCode); /*!< pointer to an FMPI2C Address Match callback function */ #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ @@ -458,10 +461,10 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint */ #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) #define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET) #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ @@ -513,7 +516,7 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ - (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified FMPI2C flag is set or not. * @param __HANDLE__ specifies the FMPI2C Handle. @@ -540,7 +543,7 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint */ #define FMPI2C_FLAG_MASK (0x0001FFFFU) #define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ - (__FLAG__)) == (__FLAG__)) ? SET : RESET) + (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the FMPI2C Handle. @@ -560,8 +563,8 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint * @retval None */ #define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? \ - ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ - ((__HANDLE__)->Instance->ICR = (__FLAG__))) + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified FMPI2C peripheral. * @param __HANDLE__ specifies the FMPI2C Handle. @@ -604,7 +607,7 @@ void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, - pFMPI2C_CallbackTypeDef pCallback); + pFMPI2C_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, pFMPI2C_AddrCallbackTypeDef pCallback); @@ -620,64 +623,64 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout); + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout); + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout); + uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout); + uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout); + uint32_t Timeout); /******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); + uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); + uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c); HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c); HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress); /******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); + uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); + uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); /** * @} */ @@ -706,9 +709,9 @@ void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); * @{ */ /* Peripheral State, Mode and Error functions *********************************/ -HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c); -HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c); -uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); +HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(const FMPI2C_HandleTypeDef *hfmpi2c); +HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(const FMPI2C_HandleTypeDef *hfmpi2c); +uint32_t HAL_FMPI2C_GetError(const FMPI2C_HandleTypeDef *hfmpi2c); /** * @} @@ -733,28 +736,28 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); */ #define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT)) + ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT)) #define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE)) + ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE)) #define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \ - ((MASK) == FMPI2C_OA2_MASK01) || \ - ((MASK) == FMPI2C_OA2_MASK02) || \ - ((MASK) == FMPI2C_OA2_MASK03) || \ - ((MASK) == FMPI2C_OA2_MASK04) || \ - ((MASK) == FMPI2C_OA2_MASK05) || \ - ((MASK) == FMPI2C_OA2_MASK06) || \ - ((MASK) == FMPI2C_OA2_MASK07)) + ((MASK) == FMPI2C_OA2_MASK01) || \ + ((MASK) == FMPI2C_OA2_MASK02) || \ + ((MASK) == FMPI2C_OA2_MASK03) || \ + ((MASK) == FMPI2C_OA2_MASK04) || \ + ((MASK) == FMPI2C_OA2_MASK05) || \ + ((MASK) == FMPI2C_OA2_MASK06) || \ + ((MASK) == FMPI2C_OA2_MASK07)) #define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \ - ((CALL) == FMPI2C_GENERALCALL_ENABLE)) + ((CALL) == FMPI2C_GENERALCALL_ENABLE)) #define IS_FMPI2C_NO_STRETCH(STRETCH) (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE)) + ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE)) #define IS_FMPI2C_MEMADD_SIZE(SIZE) (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT)) + ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT)) #define IS_TRANSFER_MODE(MODE) (((MODE) == FMPI2C_RELOAD_MODE) || \ ((MODE) == FMPI2C_AUTOEND_MODE) || \ @@ -766,25 +769,25 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); ((REQUEST) == FMPI2C_NO_STARTSTOP)) #define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_FIRST_FRAME) || \ - ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \ - ((REQUEST) == FMPI2C_NEXT_FRAME) || \ - ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == FMPI2C_LAST_FRAME) || \ - ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP) || \ - IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == FMPI2C_NEXT_FRAME) || \ + ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == FMPI2C_LAST_FRAME) || \ + ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP) || \ + IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) #define IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_OTHER_FRAME) || \ - ((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME)) + ((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME)) #define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ - FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ - FMPI2C_CR2_RD_WRN))) + (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ + FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ + FMPI2C_CR2_RD_WRN))) #define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) \ - >> 16U)) + >> 16U)) #define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) \ - >> 16U)) + >> 16U)) #define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) #define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)) #define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)) @@ -793,19 +796,19 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); #define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) #define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ - (uint16_t)(0xFF00U))) >> 8U))) + (uint16_t)(0xFF00U))) >> 8U))) #define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) #define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ - (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ - (~FMPI2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ - (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & \ - (~FMPI2C_CR2_RD_WRN))) + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ + (~FMPI2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START) | \ + (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN))) #define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \ - ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET) #define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h index 8b90f40752..995b5d3f4c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h @@ -115,12 +115,12 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE)) + ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE)) #define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \ - (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA)) + (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA)) /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h index 6d1ff4b19c..84c5400240 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h @@ -101,8 +101,6 @@ typedef struct #define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} @@ -208,7 +206,7 @@ typedef enum typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< pointer to an FMPSMBUS callback function */ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, - uint16_t AddrMatchCode); + uint16_t AddrMatchCode); /*!< pointer to an FMPSMBUS Address Match callback function */ #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ @@ -372,9 +370,9 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE #define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \ - FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) #define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \ - FMPSMBUS_IT_RXI) + FMPSMBUS_IT_RXI) #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) /** @@ -423,10 +421,10 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus */ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ @@ -512,6 +510,7 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus * @param __HANDLE__ specifies the FMPSMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: + * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) * @arg @ref FMPSMBUS_FLAG_AF NACK received flag * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag @@ -524,7 +523,9 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus * * @retval None */ -#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPSMBUS_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified FMPSMBUS peripheral. * @param __HANDLE__ specifies the FMPSMBUS Handle. @@ -557,84 +558,84 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus */ #define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \ - ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) + ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) #define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \ - ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) + ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) #define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) + ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) #define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \ - ((MASK) == FMPSMBUS_OA2_MASK01) || \ - ((MASK) == FMPSMBUS_OA2_MASK02) || \ - ((MASK) == FMPSMBUS_OA2_MASK03) || \ - ((MASK) == FMPSMBUS_OA2_MASK04) || \ - ((MASK) == FMPSMBUS_OA2_MASK05) || \ - ((MASK) == FMPSMBUS_OA2_MASK06) || \ - ((MASK) == FMPSMBUS_OA2_MASK07)) + ((MASK) == FMPSMBUS_OA2_MASK01) || \ + ((MASK) == FMPSMBUS_OA2_MASK02) || \ + ((MASK) == FMPSMBUS_OA2_MASK03) || \ + ((MASK) == FMPSMBUS_OA2_MASK04) || \ + ((MASK) == FMPSMBUS_OA2_MASK05) || \ + ((MASK) == FMPSMBUS_OA2_MASK06) || \ + ((MASK) == FMPSMBUS_OA2_MASK07)) #define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \ - ((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) + ((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) #define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \ - ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) + ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) #define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \ - ((PEC) == FMPSMBUS_PEC_ENABLE)) + ((PEC) == FMPSMBUS_PEC_ENABLE)) #define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \ - ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ - ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) + ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ + ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) #define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ - ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ - ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ - ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ - ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ - FMPSMBUS_RELOAD_MODE ))) + ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ + ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ + ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ + ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ + FMPSMBUS_RELOAD_MODE ))) #define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ - ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ - ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ - ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) + ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ + ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) #define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ - ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ - ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ - ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) + ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ + ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ + ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) #define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ - ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) + ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) #define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ - FMPI2C_CR1_PECEN))) + (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ + FMPI2C_CR1_PECEN))) #define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ - FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ - FMPI2C_CR2_RD_WRN))) + (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ + FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ + FMPI2C_CR2_RD_WRN))) #define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ - (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ - (~FMPI2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & \ - (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ - (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ + (~FMPI2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & \ + (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ + (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) #define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) #define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) @@ -643,7 +644,7 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus #define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN) #define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ - ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) #define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) #define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) @@ -676,13 +677,13 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, - pFMPSMBUS_CallbackTypeDef pCallback); + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, + pFMPSMBUS_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - pFMPSMBUS_AddrCallbackTypeDef pCallback); + pFMPSMBUS_AddrCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ /** @@ -699,7 +700,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf */ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout); + uint32_t Timeout); /** * @} */ @@ -709,14 +710,14 @@ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, */ /******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions); + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions); + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); + uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); @@ -749,8 +750,8 @@ void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); */ /* Peripheral State and Errors functions **************************************************/ -uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus); -uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus); +uint32_t HAL_FMPSMBUS_GetState(const FMPSMBUS_HandleTypeDef *hfmpsmbus); +uint32_t HAL_FMPSMBUS_GetError(const FMPSMBUS_HandleTypeDef *hfmpsmbus); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h index 001dc54733..e83a598dd8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h @@ -104,9 +104,9 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == \ - FMPSMBUS_FASTMODEPLUS_SCL) || \ - (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \ - FMPSMBUS_FASTMODEPLUS_SDA)) + FMPSMBUS_FASTMODEPLUS_SCL) || \ + (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \ + FMPSMBUS_FASTMODEPLUS_SDA)) /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h index 9cd148626c..a6fee35e45 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h @@ -159,6 +159,10 @@ typedef struct #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ + ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) + #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) @@ -167,6 +171,9 @@ typedef struct #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) #define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN) /** * @} */ @@ -248,6 +255,11 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping); +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr); + +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num); + /* Non-Blocking mode: Interrupt */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd); @@ -277,16 +289,13 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions * @{ */ -HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd); -HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum); -HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum); -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd); +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum); uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); -/** - * @} - */ /** * @} @@ -307,6 +316,9 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** * @} */ +/** + * @} + */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #ifdef __cplusplus diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h index 0d1c5f15a3..5735215dc1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h @@ -593,8 +593,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); * @{ */ /* Peripheral State functions **************************************************/ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h index 7a41ee9da0..fba2d52c0d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h @@ -689,9 +689,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); * @{ */ /* Reading operation functions ************************************************/ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim); /** * @} */ @@ -727,7 +727,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ * @{ */ /* Peripheral State functions ************************************************/ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h index ab951d3ea7..78349ebbf4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h @@ -338,14 +338,14 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer /** @defgroup LTDC_Pixelformat LTDC Pixel format * @{ */ -#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h index 26f650256f..9fc12a0189 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h @@ -109,9 +109,8 @@ typedef struct FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This parameter is mandatory for some NAND parts after the read command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. - Example: Toshiba THTH58BYG3S0HBAI6. This parameter could be ENABLE or DISABLE - Please check the Read Mode sequnece in the NAND device datasheet */ + Please check the Read Mode sequence in the NAND device datasheet */ } NAND_DeviceConfigTypeDef; /** @@ -131,7 +130,7 @@ typedef struct __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ - NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ + NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ @@ -219,27 +218,27 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); - -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress); -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); +uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /* NAND callback registering/unregistering */ @@ -269,8 +268,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, * @{ */ /* NAND State functions *******************************************************/ -HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); +HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand); +uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand); /** * @} */ @@ -290,7 +289,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); #define NAND_DEVICE2 0x80000000UL #else #define NAND_DEVICE 0x80000000UL -#endif +#endif /* NAND_SECOND_BANK */ #define NAND_WRITE_TIMEOUT 0x01000000UL #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h index cc7f1b5e50..427c2ccd1a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h @@ -238,7 +238,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); */ /* NOR State functions ********************************************************/ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); +HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor); HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h index 92488b2fe7..de1ec24186 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h @@ -190,14 +190,14 @@ typedef struct * @brief macros to handle interrupts and specific clock configurations * @{ */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ @@ -368,9 +368,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); /** * @} */ @@ -379,7 +381,7 @@ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions * @{ */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h index 72ded2b6ca..0c6f2e01dd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h @@ -51,15 +51,21 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \ + || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); -#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h index 3b9ad5a390..c391153ba1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h @@ -114,6 +114,8 @@ typedef struct */ #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03) + /** * @} */ @@ -123,6 +125,7 @@ typedef struct */ #define PWR_STOPENTRY_WFI ((uint8_t)0x01) #define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03) /** * @} */ @@ -401,8 +404,14 @@ void HAL_PWR_DisableSEVOnPend(void); ((MODE) == PWR_PVD_MODE_NORMAL)) #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \ + ((ENTRY) == PWR_STOPENTRY_WFE) || \ + ((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h index dcf5814451..c348e5effa 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @@ -660,7 +660,6 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) @@ -683,7 +682,6 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) @@ -708,7 +706,6 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) @@ -1407,7 +1404,7 @@ void HAL_RCC_CSSCallback(void); ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) +#define IS_RCC_PLLM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h index dbcc98cd29..735c8f7c62 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h @@ -526,7 +526,7 @@ typedef struct * @{ */ #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U -#define RCC_I2SCLKSOURCE_EXT 0x00000001U +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC /** * @} */ @@ -1665,6 +1665,7 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x22E017FFU) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) @@ -1696,7 +1697,12 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F469xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C1U) +#endif /* STM32F427xx || STM32F429xx || STM32F469xx */ +#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000F1U) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) @@ -1721,7 +1727,12 @@ typedef struct * @brief Force or release AHB3 peripheral reset. * @{ */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000001U) +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) +#endif /* STM32F469xx || STM32F479xx */ #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) @@ -1738,6 +1749,7 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xF6FEC9FFU) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) @@ -1783,6 +1795,15 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x0C777933U) +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F429xx) || defined(STM32F439xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x04777933U) +#endif /* STM32F429xx || STM32F439xx */ +#if defined(STM32F427xx) || defined(STM32F437xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00777933U) +#endif /* STM32F427xx || STM32F437xx */ #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) @@ -2590,6 +2611,12 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#if defined (STM32F405xx) || defined (STM32F415xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x206011FFU) +#endif /* STM32F405xx || STM32F415xx */ +#if defined (STM32F407xx) || defined (STM32F417xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x226011FFU) +#endif /* STM32F407xx || STM32F417xx */ #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) @@ -2615,7 +2642,12 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#if defined (STM32F415xx) || defined (STM32F417xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000F1U) +#endif /* STM32F415xx || STM32F417xx */ +#if defined (STM32F405xx) || defined (STM32F407xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C1U) +#endif /* STM32F405xx || STM32F407xx */ #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) #if defined(STM32F407xx)|| defined(STM32F417xx) @@ -2644,7 +2676,7 @@ typedef struct * @brief Force or release AHB3 peripheral reset. * @{ */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000001U) #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) @@ -2657,6 +2689,7 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xF6FEC9FFU) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) @@ -2698,6 +2731,7 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x04777933U) #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) @@ -3097,7 +3131,7 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) @@ -3114,7 +3148,7 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000080U) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) @@ -3127,7 +3161,7 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x10E2C80FU) #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) @@ -3148,7 +3182,7 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00077931U) #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) @@ -3413,6 +3447,7 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x80601087U) #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) @@ -3445,6 +3480,12 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#if defined (STM32F410Rx) || defined (STM32F410Cx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x31624A18U) +#endif /* STM32F410Rx || STM32F410Cx */ +#if defined (STM32F410Tx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x31620A18U) +#endif /* STM32F410Tx */ #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) @@ -3462,6 +3503,12 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#if defined (STM32F410Rx) || defined (STM32F410Cx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00155131U) +#endif /* STM32F410Rx || STM32F410Cx */ +#if defined (STM32F410Tx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00055111U) +#endif /* STM32F410Tx */ #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) /** @@ -3754,6 +3801,7 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) @@ -3769,7 +3817,7 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000080U) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) @@ -3792,6 +3840,7 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x10E2C80FU) #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) @@ -3811,6 +3860,7 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00177931U) #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) @@ -4430,6 +4480,7 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x206010FFU) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) @@ -4451,7 +4502,7 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000081U) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) @@ -4468,7 +4519,7 @@ typedef struct * @brief Force or release AHB3 peripheral reset. * @{ */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) @@ -4484,6 +4535,7 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x3FFFC9FFU) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) @@ -4531,6 +4583,7 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00C77933U) #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) @@ -5343,6 +5396,18 @@ typedef struct * @brief Force or release AHB1 peripheral reset. * @{ */ +#if defined (STM32F412Zx) || defined(STM32F413xx) || defined (STM32F423xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x006010FFU) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined (STM32F412Cx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x00601087U) +#endif /* STM32F412Cx */ +#if defined (STM32F412Vx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) +#endif /* STM32F412Vx */ +#if defined (STM32F412Rx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060108FU) +#endif /* STM32F412Rx */ #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ @@ -5374,10 +5439,11 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C0U) #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) #if defined(STM32F423xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000D0U) #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) #endif /* STM32F423xx */ @@ -5396,7 +5462,7 @@ typedef struct * @{ */ #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) @@ -5423,6 +5489,12 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFECBFFU) +#endif /* STM32F413xx || STM32F423xx */ +#if defined (STM32F412Zx) || defined (STM32F412Vx) || defined (STM32F412Rx) || defined (STM32F412Cx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x17E6C9FFU) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) @@ -5486,6 +5558,12 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ +#if defined(STM32F413xx)|| defined(STM32F423xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x035779F3U) +#endif /* STM32F413xx || STM32F423xx */ +#if defined (STM32F412Zx) || defined (STM32F412Vx) || defined (STM32F412Rx) || defined (STM32F412Cx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x01177933U) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #if defined(STM32F413xx) || defined(STM32F423xx) #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) @@ -6101,7 +6179,7 @@ typedef struct * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin * used as I2S clock source. */ -#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (__SOURCE__))) /** @brief Macro to get the I2S clock source (I2SCLK). diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h index 7d4dca1ebd..87279ef79c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h @@ -304,7 +304,7 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); @@ -317,8 +317,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h index 24affc5428..9d58161fe0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -489,6 +489,12 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to (__HANDLE__)->Instance->WPR = 0xFFU; \ } while(0U) +/** + * @brief Check whether the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U) /** * @brief Enable the RTC ALARMA peripheral. @@ -772,6 +778,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); RTC_DR_MT | RTC_DR_MU | \ RTC_DR_DT | RTC_DR_DU | \ RTC_DR_WDU)) +#define RTC_ISR_RESERVED_MASK ((uint32_t)(RTC_FLAGS_MASK | RTC_ISR_INIT)) #define RTC_INIT_MASK 0xFFFFFFFFU #define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) #define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h index ff5f14d498..bee4e320bc 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -162,7 +162,7 @@ typedef struct * @{ */ #define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U -#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG +#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE /** @@ -635,18 +635,6 @@ typedef struct */ #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__)) -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper 1 interrupt - * @arg RTC_IT_TAMP2: Tamper 2 interrupt - * @note RTC_IT_TAMP2 is not applicable to all devices. - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) - /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h index 6c23f93c15..368316d20a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h @@ -748,8 +748,8 @@ void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); * @{ */ /* Peripheral State functions ************************************************/ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai); -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h index c6fdd56612..75ba6d20f5 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h @@ -71,8 +71,8 @@ extern "C" { */ /* Extended features functions ************************************************/ -void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai); -uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai); +void SAI_BlockSynchroConfig(const SAI_HandleTypeDef *hsai); +uint32_t SAI_GetInputClock(const SAI_HandleTypeDef *hsai); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h index 135f40261e..7aa4ce34b8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h @@ -671,8 +671,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc); * @{ */ /* Peripheral State functions **************************************************/ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc); +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h index ea92afa30c..d0ffed83cb 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h @@ -150,35 +150,35 @@ typedef enum */ typedef struct __SMBUS_HandleTypeDef { - I2C_TypeDef *Instance; /*!< SMBUS registers base address */ + I2C_TypeDef *Instance; /*!< SMBUS registers base address */ - SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ + SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ - uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ + uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ - uint16_t XferSize; /*!< SMBUS transfer size */ + uint16_t XferSize; /*!< SMBUS transfer size */ - __IO uint16_t XferCount; /*!< SMBUS transfer counter */ + __IO uint16_t XferCount; /*!< SMBUS transfer counter */ __IO uint32_t XferOptions; /*!< SMBUS transfer options this parameter can - be a value of @ref SMBUS_OPTIONS */ + be a value of @ref SMBUS_XferOptions_definition */ __IO uint32_t PreviousState; /*!< SMBUS communication Previous state and mode - context for internal usage */ + context for internal usage */ - HAL_LockTypeDef Lock; /*!< SMBUS locking object */ + HAL_LockTypeDef Lock; /*!< SMBUS locking object */ - __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */ + __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */ - __IO HAL_SMBUS_ModeTypeDef Mode; /*!< SMBUS communication mode */ + __IO HAL_SMBUS_ModeTypeDef Mode; /*!< SMBUS communication mode */ - __IO uint32_t ErrorCode; /*!< SMBUS Error code */ + __IO uint32_t ErrorCode; /*!< SMBUS Error code */ - __IO uint32_t Devaddress; /*!< SMBUS Target device address */ + __IO uint32_t Devaddress; /*!< SMBUS Target device address */ - __IO uint32_t EventCount; /*!< SMBUS Event counter */ + __IO uint32_t EventCount; /*!< SMBUS Event counter */ - uint8_t XferPEC; /*!< SMBUS PEC data in reception mode */ + uint8_t XferPEC; /*!< SMBUS PEC data in reception mode */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ @@ -604,6 +604,10 @@ void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_AbortCpltCallback(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + /** * @} */ @@ -718,10 +722,6 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); * @} */ -/** -* @} -*/ - #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h index 7ea04aa900..386903bcf0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h @@ -56,7 +56,8 @@ typedef struct uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input. This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */ - uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B. + uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status + from channel A or B. This parameter can be a value of @ref SPDIFRX_Channel_Selection */ uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...). @@ -65,16 +66,19 @@ typedef struct uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ - uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_PT_Mask */ + uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_PT_Mask */ - uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame. + uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not + into the received frame. This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. This parameter can be a value of @ref SPDIFRX_V_Mask */ - uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame. + uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not + into the received frame. This parameter can be a value of @ref SPDIFRX_PE_Mask */ } SPDIFRX_InitTypeDef; @@ -89,17 +93,20 @@ typedef struct uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ - uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_PT_Mask */ + uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_PT_Mask */ - uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ + uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_V_Mask */ + This parameter can be a value of @ref SPDIFRX_V_Mask */ - uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_PE_Mask */ + uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_PE_Mask */ } SPDIFRX_SetDataFormatTypeDef; @@ -151,7 +158,8 @@ typedef struct decremented when a sample is received. NbSamplesReceived = RxBufferSize-RxBufferCount) */ - DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */ + DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information + DMA handle parameters */ DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */ @@ -162,9 +170,11 @@ typedef struct __IO uint32_t ErrorCode; /* SPDIFRX Error code */ #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed callback */ + void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed + callback */ void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */ - void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */ + void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed + callback */ void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */ void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */ void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */ @@ -172,9 +182,6 @@ typedef struct #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } SPDIFRX_HandleTypeDef; -/** - * @} - */ #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) /** @@ -194,9 +201,12 @@ typedef enum /** * @brief HAL SPDIFRX Callback pointer definition */ -typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback function */ +typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback + function */ #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ - +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants * @{ @@ -260,8 +270,10 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< /** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask * @{ */ -#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */ -#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/ +#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied + into the SPDIF_DR */ +#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied + into the SPDIF_DR, zeros are written instead*/ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h index e135aa1378..a6e61110ee 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h @@ -209,7 +209,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); */ /* SRAM State functions ******************************************************/ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h index 8c81414fad..1a8357cddb 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h @@ -385,29 +385,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1654,6 +1653,10 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) + #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3)) @@ -1705,7 +1708,6 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) @@ -1896,7 +1898,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} @@ -1918,7 +1920,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -1940,7 +1943,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -1992,7 +1996,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @{ */ /* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); @@ -2025,21 +2029,26 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); * @{ */ /* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, @@ -2049,7 +2058,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ @@ -2086,17 +2095,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @{ */ /* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); /** * @} */ @@ -2110,9 +2119,9 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h index 39fb500f67..561e9bbe87 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h @@ -74,9 +74,8 @@ typedef struct #if defined (TIM2) #if defined(TIM8) #define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */ -#else -#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ #endif /* TIM8 */ +#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ #define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */ #define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */ #endif /* TIM2 */ @@ -205,7 +204,7 @@ typedef struct * @{ */ /* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); @@ -238,7 +237,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -257,7 +257,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -291,9 +292,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig); + const TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); /** * @} @@ -316,8 +317,8 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); * @{ */ /* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h index c5f5d3e348..e6ce82fca7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h @@ -137,12 +137,23 @@ typedef enum /** * @brief HAL UART Reception type definition * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * It is expected to admit following values : + * This parameter can be a value of @ref UART_Reception_Type_Values : * HAL_UART_RECEPTION_STANDARD = 0x00U, * HAL_UART_RECEPTION_TOIDLE = 0x01U, */ typedef uint32_t HAL_UART_RxTypeTypeDef; +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -166,6 +177,8 @@ typedef struct __UART_HandleTypeDef __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ @@ -381,7 +394,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @} */ -/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values +/** @defgroup UART_Reception_Type_Values UART Reception type values * @{ */ #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ @@ -390,6 +403,16 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @} */ +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) +/** + * @} + */ + /** * @} */ @@ -734,6 +757,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); + /* Transfer Abort functions */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); @@ -775,8 +800,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); * @{ */ /* Peripheral State functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h index b64e95dc0c..655f8482ee 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h @@ -544,8 +544,8 @@ void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); * @{ */ /* Peripheral State functions ************************************************/ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); /** * @} */ @@ -624,7 +624,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup USART_Private_Functions USART Private Functions +/** @addtogroup USART_Private_Functions * @{ */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h index 44e8af28d3..43b4a1ed54 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h @@ -684,8 +684,8 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode -* @{ -*/ + * @{ + */ #define LL_ADC_REG_CONV_SINGLE 0x00000000UL /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** @@ -808,8 +808,8 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode -* @{ -*/ + * @{ + */ #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** @@ -1866,12 +1866,12 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { /* Retrieve address of register DR */ - data_reg_addr = (uint32_t)&(ADCx->DR); + data_reg_addr = (uint32_t) & (ADCx->DR); } else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ { /* Retrieve address of register CDR */ - data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); + data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); } return data_reg_addr; @@ -1879,8 +1879,11 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis #else __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { + /* Prevent unused argument compilation warning */ + (void)Register; + /* Retrieve address of register DR */ - return (uint32_t)&(ADCx->DR); + return (uint32_t) & (ADCx->DR); } #endif @@ -2145,11 +2148,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { -/* Note: On this STM32 series, ADC group regular external trigger edge */ -/* is used to perform a ADC conversion start. */ -/* This function does not set external trigger edge. */ -/* This feature is set using function */ -/* @ref LL_ADC_REG_StartConversionExtTrig(). */ + /* Note: On this STM32 series, ADC group regular external trigger edge */ + /* is used to perform a ADC conversion start. */ + /* This function does not set external trigger edge. */ + /* This feature is set using function */ + /* @ref LL_ADC_REG_StartConversionExtTrig(). */ MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); } @@ -2588,10 +2591,10 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); - return (uint32_t) (READ_BIT(*preg, - ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) - >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) - ); + return (uint32_t)(READ_BIT(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ); } /** @@ -2780,11 +2783,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { -/* Note: On this STM32 series, ADC group injected external trigger edge */ -/* is used to perform a ADC conversion start. */ -/* This function does not set external trigger edge. */ -/* This feature is set using function */ -/* @ref LL_ADC_INJ_StartConversionExtTrig(). */ + /* Note: On this STM32 series, ADC group injected external trigger edge */ + /* is used to perform a ADC conversion start. */ + /* This function does not set external trigger edge. */ + /* This feature is set using function */ + /* @ref LL_ADC_INJ_StartConversionExtTrig(). */ MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); } @@ -4015,7 +4018,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) { - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } /** @@ -4030,7 +4033,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) { - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } #if defined(ADC_MULTIMODE_SUPPORT) @@ -4546,7 +4549,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); } #endif /* ADC_MULTIMODE_SUPPORT */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h index d478e13019..3861f55ffd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h @@ -371,6 +371,16 @@ __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } +/** + * @brief Clear pending events. + * @retval None + */ +__STATIC_INLINE void LL_LPM_ClearEvent(void) +{ + __SEV(); + __WFE(); +} + /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h index 0a280062b8..8ada06d580 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h @@ -135,7 +135,7 @@ __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). */ -__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->DR)); } @@ -173,7 +173,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) * @{ */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h index ea1500ba58..4bff015f18 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h @@ -118,10 +118,10 @@ extern "C" { /* DAC registers bits positions */ #if defined(DAC_CHANNEL2_SUPPORT) -#endif #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos +#endif /* DAC_CHANNEL2_SUPPORT */ /* Miscellaneous data */ #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 @@ -429,7 +429,7 @@ typedef struct * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval 1...2 (value "2" depending on DAC channel 2 availability) */ @@ -449,36 +449,26 @@ typedef struct * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. */ #if defined(DAC_CHANNEL2_SUPPORT) -#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) == 1UL) \ - ? ( \ - LL_DAC_CHANNEL_1 \ - ) \ - : \ - (((__DECIMAL_NB__) == 2UL) \ - ? ( \ - LL_DAC_CHANNEL_2 \ - ) \ - : \ - ( \ - 0UL \ - ) \ - ) \ +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1UL) \ + ? (LL_DAC_CHANNEL_1) \ + : \ + (((__DECIMAL_NB__) == 2UL) \ + ? (LL_DAC_CHANNEL_2) \ + : \ + (0UL) \ + ) \ ) #else -#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) == 1UL) \ - ? ( \ - LL_DAC_CHANNEL_1 \ - ) \ - : \ - ( \ - 0UL \ - ) \ +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1UL) \ + ? (LL_DAC_CHANNEL_1) \ + : \ + (0UL) \ ) #endif /* DAC_CHANNEL2_SUPPORT */ @@ -514,12 +504,10 @@ typedef struct * @arg @ref LL_DAC_RESOLUTION_8B * @retval DAC conversion data (unit: digital value) */ -#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ - __DAC_VOLTAGE__,\ - __DAC_RESOLUTION__) \ -((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ -) +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ + ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ + ) /** * @} @@ -534,6 +522,7 @@ typedef struct /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions * @{ */ + /** * @brief Set the conversion trigger source for the selected DAC channel. * @note For conversion trigger source to be effective, DAC trigger @@ -549,7 +538,7 @@ typedef struct * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE @@ -582,7 +571,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE @@ -594,7 +583,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 */ -__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -611,7 +600,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param WaveAutoGeneration This parameter can be one of the following values: * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE @@ -636,14 +625,14 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -665,7 +654,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param NoiseLFSRMask This parameter can be one of the following values: * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 @@ -699,7 +688,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 @@ -715,7 +704,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -737,7 +726,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param TriangleAmplitude This parameter can be one of the following values: * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 @@ -772,7 +761,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 @@ -788,7 +777,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -804,7 +793,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputBuffer This parameter can be one of the following values: * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE @@ -827,13 +816,13 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -859,7 +848,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -880,7 +869,7 @@ __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -900,11 +889,11 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -938,7 +927,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Register This parameter can be one of the following values: * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED @@ -946,7 +935,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED * @retval DAC register address */ -__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ @@ -973,7 +962,7 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -992,7 +981,7 @@ __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -1012,11 +1001,11 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1040,7 +1029,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -1059,7 +1048,7 @@ __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -1079,11 +1068,11 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1110,7 +1099,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ @@ -1131,7 +1120,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None @@ -1155,7 +1144,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None @@ -1179,7 +1168,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x00 and Max_Data=0xFF * @retval None @@ -1267,11 +1256,11 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); @@ -1293,7 +1282,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); } @@ -1305,7 +1294,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); } @@ -1397,7 +1386,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); } @@ -1409,7 +1398,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); } @@ -1424,8 +1413,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) * @{ */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); +ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx); +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct); void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); /** @@ -1452,4 +1441,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); #endif #endif /* STM32F4xx_LL_DAC_H */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h index 3dc863d46c..dda9d895a4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h @@ -369,7 +369,7 @@ typedef struct delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ } FMC_NAND_InitTypeDef; -#endif +#endif /* FMC_Bank3 || FMC_Bank2_3 */ #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) /** @@ -1388,7 +1388,7 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); -uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h index dcc001605e..a3c14b6ef2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h @@ -295,7 +295,7 @@ typedef struct #define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ #define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | \ - FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) + FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ #define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ @@ -343,7 +343,7 @@ typedef struct #define LL_FMPI2C_FMPSMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ #define LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | \ - FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB + FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ /** * @} @@ -452,7 +452,7 @@ __STATIC_INLINE void LL_FMPI2C_Disable(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE) == (FMPI2C_CR1_PE)) ? 1UL : 0UL); } @@ -501,7 +501,7 @@ __STATIC_INLINE void LL_FMPI2C_SetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx, uint32_ * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetDigitalFilter(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_DNF) >> FMPI2C_CR1_DNF_Pos); } @@ -536,7 +536,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAnalogFilter(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAnalogFilter(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF) != (FMPI2C_CR1_ANFOFF)) ? 1UL : 0UL); } @@ -569,7 +569,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_TX(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN) == (FMPI2C_CR1_TXDMAEN)) ? 1UL : 0UL); } @@ -602,7 +602,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN) == (FMPI2C_CR1_RXDMAEN)) ? 1UL : 0UL); } @@ -617,7 +617,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx) * @arg @ref LL_FMPI2C_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(const FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction) { uint32_t data_reg_addr; @@ -665,7 +665,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableClockStretching(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledClockStretching(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledClockStretching(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH) != (FMPI2C_CR1_NOSTRETCH)) ? 1UL : 0UL); } @@ -698,7 +698,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC) == (FMPI2C_CR1_SBC)) ? 1UL : 0UL); } @@ -733,7 +733,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableGeneralCall(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledGeneralCall(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledGeneralCall(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN) == (FMPI2C_CR1_GCEN)) ? 1UL : 0UL); } @@ -761,7 +761,7 @@ __STATIC_INLINE void LL_FMPI2C_SetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx, * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetMasterAddressingMode(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_ADD10)); } @@ -810,7 +810,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress1(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress1(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN) == (FMPI2C_OAR1_OA1EN)) ? 1UL : 0UL); } @@ -866,7 +866,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress2(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress2(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN) == (FMPI2C_OAR2_OA2EN)) ? 1UL : 0UL); } @@ -891,7 +891,7 @@ __STATIC_INLINE void LL_FMPI2C_SetTiming(FMPI2C_TypeDef *FMPI2Cx, uint32_t Timin * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_PRESC) >> FMPI2C_TIMINGR_PRESC_Pos); } @@ -902,7 +902,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLL) >> FMPI2C_TIMINGR_SCLL_Pos); } @@ -913,7 +913,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLH) >> FMPI2C_TIMINGR_SCLH_Pos); } @@ -924,7 +924,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SDADEL) >> FMPI2C_TIMINGR_SDADEL_Pos); } @@ -935,7 +935,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLDEL) >> FMPI2C_TIMINGR_SCLDEL_Pos); } @@ -972,7 +972,7 @@ __STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t Periphe * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetMode(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN)); } @@ -1021,7 +1021,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN) == (FMPI2C_CR1_ALERTEN)) ? 1UL : 0UL); } @@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN) == (FMPI2C_CR1_PECEN)) ? 1UL : 0UL); } @@ -1082,7 +1082,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) * @retval None */ __STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, - uint32_t TimeoutB) + uint32_t TimeoutB) { MODIFY_REG(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA | FMPI2C_TIMEOUTR_TIDLE | FMPI2C_TIMEOUTR_TIMEOUTB, TimeoutA | TimeoutAMode | (TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos)); @@ -1111,7 +1111,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_ * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA)); } @@ -1143,7 +1143,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uin * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIDLE)); } @@ -1171,7 +1171,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_ * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTB) >> FMPI2C_TIMEOUTR_TIMEOUTB_Pos); } @@ -1225,7 +1225,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint * @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(const FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) { return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == \ (ClockTimeout)) ? 1UL : 0UL); @@ -1267,7 +1267,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_TX(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TX(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TX(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE) == (FMPI2C_CR1_TXIE)) ? 1UL : 0UL); } @@ -1300,7 +1300,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_RX(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_RX(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_RX(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE) == (FMPI2C_CR1_RXIE)) ? 1UL : 0UL); } @@ -1333,7 +1333,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ADDR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ADDR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE) == (FMPI2C_CR1_ADDRIE)) ? 1UL : 0UL); } @@ -1366,7 +1366,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_NACK(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_NACK(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_NACK(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE) == (FMPI2C_CR1_NACKIE)) ? 1UL : 0UL); } @@ -1399,7 +1399,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_STOP(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_STOP(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_STOP(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE) == (FMPI2C_CR1_STOPIE)) ? 1UL : 0UL); } @@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_TC(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE) == (FMPI2C_CR1_TCIE)) ? 1UL : 0UL); } @@ -1489,7 +1489,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableIT_ERR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE) == (FMPI2C_CR1_ERRIE)) ? 1UL : 0UL); } @@ -1510,7 +1510,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXE) == (FMPI2C_ISR_TXE)) ? 1UL : 0UL); } @@ -1523,7 +1523,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXIS) == (FMPI2C_ISR_TXIS)) ? 1UL : 0UL); } @@ -1536,7 +1536,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_RXNE) == (FMPI2C_ISR_RXNE)) ? 1UL : 0UL); } @@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDR) == (FMPI2C_ISR_ADDR)) ? 1UL : 0UL); } @@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_NACKF) == (FMPI2C_ISR_NACKF)) ? 1UL : 0UL); } @@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_STOPF) == (FMPI2C_ISR_STOPF)) ? 1UL : 0UL); } @@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TC) == (FMPI2C_ISR_TC)) ? 1UL : 0UL); } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TCR) == (FMPI2C_ISR_TCR)) ? 1UL : 0UL); } @@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BERR) == (FMPI2C_ISR_BERR)) ? 1UL : 0UL); } @@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ARLO) == (FMPI2C_ISR_ARLO)) ? 1UL : 0UL); } @@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_OVR) == (FMPI2C_ISR_OVR)) ? 1UL : 0UL); } @@ -1655,7 +1655,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_PECERR) == (FMPI2C_ISR_PECERR)) ? 1UL : 0UL); } @@ -1670,7 +1670,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TIMEOUT) == (FMPI2C_ISR_TIMEOUT)) ? 1UL : 0UL); } @@ -1686,7 +1686,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMP * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ALERT) == (FMPI2C_ISR_ALERT)) ? 1UL : 0UL); } @@ -1699,7 +1699,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2 * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BUSY(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BUSY(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BUSY) == (FMPI2C_ISR_BUSY)) ? 1UL : 0UL); } @@ -1860,7 +1860,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAutoEndMode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAutoEndMode(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND) == (FMPI2C_CR2_AUTOEND)) ? 1UL : 0UL); } @@ -1895,7 +1895,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableReloadMode(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledReloadMode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledReloadMode(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD) == (FMPI2C_CR2_RELOAD)) ? 1UL : 0UL); } @@ -1919,7 +1919,7 @@ __STATIC_INLINE void LL_FMPI2C_SetTransferSize(FMPI2C_TypeDef *FMPI2Cx, uint32_t * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES) >> FMPI2C_CR2_NBYTES_Pos); } @@ -1996,7 +1996,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAuto10BitRead(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R) != (FMPI2C_CR2_HEAD10R)) ? 1UL : 0UL); } @@ -2024,7 +2024,7 @@ __STATIC_INLINE void LL_FMPI2C_SetTransferRequest(FMPI2C_TypeDef *FMPI2Cx, uint3 * @arg @ref LL_FMPI2C_REQUEST_WRITE * @arg @ref LL_FMPI2C_REQUEST_READ */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferRequest(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferRequest(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN)); } @@ -2048,7 +2048,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Sl * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_SADD)); } @@ -2092,13 +2092,20 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx) * @retval None */ __STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, - uint32_t TransferSize, uint32_t EndMode, uint32_t Request) + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & FMPI2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & FMPI2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD | FMPI2C_CR2_ADD10 | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RELOAD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << FMPI2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** @@ -2111,7 +2118,7 @@ __STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t * @arg @ref LL_FMPI2C_DIRECTION_WRITE * @arg @ref LL_FMPI2C_DIRECTION_READ */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_DIR)); } @@ -2122,7 +2129,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDCODE) >> FMPI2C_ISR_ADDCODE_Pos << 1); } @@ -2152,7 +2159,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(const FMPI2C_TypeDef *FMPI2Cx) { return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE) == (FMPI2C_CR2_PECBYTE)) ? 1UL : 0UL); } @@ -2165,7 +2172,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(const FMPI2C_TypeDef *FMPI2Cx) { return (uint32_t)(READ_BIT(FMPI2Cx->PECR, FMPI2C_PECR_PEC)); } @@ -2176,7 +2183,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_FMPI2C_ReceiveData8(FMPI2C_TypeDef *FMPI2Cx) +__STATIC_INLINE uint8_t LL_FMPI2C_ReceiveData8(const FMPI2C_TypeDef *FMPI2Cx) { return (uint8_t)(READ_BIT(FMPI2Cx->RXDR, FMPI2C_RXDR_RXDATA)); } @@ -2202,8 +2209,8 @@ __STATIC_INLINE void LL_FMPI2C_TransmitData8(FMPI2C_TypeDef *FMPI2Cx, uint8_t Da * @{ */ -ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct); -ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx); +ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, const LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct); +ErrorStatus LL_FMPI2C_DeInit(const FMPI2C_TypeDef *FMPI2Cx); void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h index 8b0ceb75f9..5fb1c4f256 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h @@ -304,7 +304,7 @@ typedef struct delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ } FSMC_NAND_InitTypeDef; -#endif +#endif /* FSMC_Bank2_3 */ #if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h index babba6bf9d..92d4a74a1a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h @@ -263,7 +263,7 @@ typedef struct * @} */ -/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper +/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported Macros Helper * @{ */ @@ -869,7 +869,7 @@ __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, /** * @brief Configure peripheral mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBUS LL_I2C_SetMode\n * CR1 SMBTYPE LL_I2C_SetMode\n @@ -889,7 +889,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) /** * @brief Get peripheral mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBUS LL_I2C_GetMode\n * CR1 SMBTYPE LL_I2C_GetMode\n @@ -908,7 +908,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -926,7 +926,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -944,7 +944,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert * @param I2Cx I2C Instance. @@ -957,7 +957,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC * @param I2Cx I2C Instance. @@ -970,7 +970,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC * @param I2Cx I2C Instance. @@ -983,7 +983,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC * @param I2Cx I2C Instance. @@ -1166,7 +1166,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx) /** * @brief Enable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Bus Error detection (BERR) @@ -1187,7 +1187,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) /** * @brief Disable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Bus Error detection (BERR) @@ -1370,7 +1370,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR * @param I2Cx I2C Instance. @@ -1383,7 +1383,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT * @param I2Cx I2C Instance. @@ -1396,7 +1396,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus alert flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT * @param I2Cx I2C Instance. @@ -1435,7 +1435,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Host address reception (Slave mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: No SMBus Host address * SET: SMBus Host address received. @@ -1451,7 +1451,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Device default address reception (Slave mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: No SMBus Device default address * SET: SMBus Device default address received. @@ -1583,7 +1583,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT * @param I2Cx I2C Instance. @@ -1596,7 +1596,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT * @param I2Cx I2C Instance. @@ -1774,7 +1774,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx) /** * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This feature is cleared by hardware when the PEC byte is transferred or compared, * or by a START or STOP condition, it is also cleared by software. @@ -1789,7 +1789,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare * @param I2Cx I2C Instance. @@ -1802,7 +1802,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare * @param I2Cx I2C Instance. @@ -1815,7 +1815,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC * @param I2Cx I2C Instance. diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h index 9495e019f2..273d89dc7b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h @@ -315,14 +315,27 @@ typedef struct * @{ */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM +/** +@endcond + */ + #if defined(USE_FULL_LL_DRIVER) /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions * @{ */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); /** * @} @@ -352,7 +365,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } @@ -398,7 +411,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD */ -__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); } @@ -427,7 +440,7 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto * @param LPTIMx Low-Power Timer instance * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } @@ -454,7 +467,7 @@ __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t Compare * @param LPTIMx Low-Power Timer instance * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP)); } @@ -469,7 +482,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval Counter value */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); } @@ -497,7 +510,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); } @@ -546,7 +559,7 @@ __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Wavefo * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); } @@ -573,7 +586,7 @@ __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polari * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); } @@ -617,7 +630,7 @@ __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Presc * @arg @ref LL_LPTIM_PRESCALER_DIV64 * @arg @ref LL_LPTIM_PRESCALER_DIV128 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); } @@ -683,7 +696,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } @@ -744,7 +757,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Sour * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM1_TRGO * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM5_TRGO */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); } @@ -759,7 +772,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_FILTER_4 * @arg @ref LL_LPTIM_TRIG_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); } @@ -773,7 +786,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); } @@ -809,7 +822,7 @@ __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t Clo * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); } @@ -851,7 +864,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockF * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -866,7 +879,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_CLK_FILTER_4 * @arg @ref LL_LPTIM_CLK_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); } @@ -904,7 +917,7 @@ __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t Enc * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -943,7 +956,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } @@ -956,13 +969,14 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) * @{ */ + /** * @brief Clear the compare match flag (CMPMCF) - * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM + * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF); } @@ -973,18 +987,18 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } /** * @brief Clear the autoreload match flag (ARRMCF) - * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM + * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); } @@ -995,7 +1009,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } @@ -1017,7 +1031,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } @@ -1040,7 +1054,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } @@ -1063,7 +1077,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } @@ -1086,7 +1100,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } @@ -1109,7 +1123,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } @@ -1150,7 +1164,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } @@ -1183,7 +1197,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } @@ -1216,7 +1230,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } @@ -1249,7 +1263,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } @@ -1282,7 +1296,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } @@ -1315,7 +1329,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } @@ -1348,7 +1362,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h index 151cb4a728..21c7330ce6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h @@ -38,6 +38,7 @@ extern "C" { */ /* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -145,7 +146,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); } @@ -164,7 +165,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); } @@ -175,7 +176,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); } @@ -186,7 +187,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); } @@ -197,7 +198,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); } @@ -208,7 +209,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); } @@ -274,7 +275,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); } @@ -293,7 +294,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval Generated 32-bit random value */ -__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_REG(RNGx->DR)); } @@ -306,7 +307,7 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h index 180cc15f14..74a0aee089 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -1030,7 +1030,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1064,7 +1064,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1134,7 +1134,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1184,7 +1184,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1326,7 +1326,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll DR YT LL_RTC_DATE_GetYear\n @@ -1360,7 +1360,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1407,7 +1407,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll DR MT LL_RTC_DATE_GetMonth\n @@ -1449,7 +1449,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll DR DT LL_RTC_DATE_GetDay\n @@ -1511,7 +1511,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h index 35c47e3c04..8bd32f4163 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h @@ -300,10 +300,14 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U #define SDMMC_CARD_LOCKED 0x02000000U -#ifndef SDMMC_DATATIMEOUT -#define SDMMC_DATATIMEOUT 0xFFFFFFFFU +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#endif /* SDMMC_SWDATATIMEOUT */ + #define SDMMC_0TO7BITS 0x000000FFU #define SDMMC_8TO15BITS 0x0000FF00U #define SDMMC_16TO23BITS 0x00FF0000U diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h index 61148e4e44..a11f561933 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h @@ -562,10 +562,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!> 16U) >> TIM_CCMR1_IC1PSC_Pos))) -/** - * @} - */ - - /** * @} */ @@ -1143,7 +1135,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); } @@ -1176,7 +1168,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval Inverted state of bit (0 or 1). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); } @@ -1210,7 +1202,7 @@ __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSo * @arg @ref LL_TIM_UPDATESOURCE_REGULAR * @arg @ref LL_TIM_UPDATESOURCE_COUNTER */ -__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); } @@ -1237,7 +1229,7 @@ __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulse * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE */ -__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); } @@ -1281,7 +1273,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) { uint32_t counter_mode; @@ -1323,7 +1315,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); } @@ -1360,7 +1352,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 */ -__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); } @@ -1387,7 +1379,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) * @param TIMx Timer instance * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) */ -__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CNT)); } @@ -1400,7 +1392,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_COUNTERDIRECTION_UP * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); } @@ -1427,7 +1419,7 @@ __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) * @param TIMx Timer instance * @retval Prescaler value between Min_Data=0 and Max_Data=65535 */ -__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->PSC)); } @@ -1456,7 +1448,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload * @param TIMx Timer instance * @retval Auto-reload value */ -__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->ARR)); } @@ -1483,7 +1475,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep * @param TIMx Timer instance * @retval Repetition counter value */ -__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->RCR)); } @@ -1524,6 +1516,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); } +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check @@ -1562,7 +1565,7 @@ __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAR * @arg @ref LL_TIM_CCDMAREQUEST_CC * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE */ -__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); } @@ -1656,7 +1659,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH4 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) { return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); } @@ -1757,7 +1760,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_PWM1 * @arg @ref LL_TIM_OCMODE_PWM2 */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -1815,7 +1818,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCPOLARITY_HIGH * @arg @ref LL_TIM_OCPOLARITY_LOW */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); @@ -1876,7 +1879,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCIDLESTATE_LOW * @arg @ref LL_TIM_OCIDLESTATE_HIGH */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); @@ -1941,7 +1944,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH4 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2005,7 +2008,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH4 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2078,7 +2081,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH4 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2181,7 +2184,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -2197,7 +2200,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -2213,7 +2216,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -2229,7 +2232,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -2329,7 +2332,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_TRC */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2380,7 +2383,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_ICPSC_DIV4 * @arg @ref LL_TIM_ICPSC_DIV8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2455,7 +2458,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2512,7 +2515,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_IC_POLARITY_FALLING * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> @@ -2553,7 +2556,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); } @@ -2569,7 +2572,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -2585,7 +2588,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -2601,7 +2604,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -2617,7 +2620,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -2664,7 +2667,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); } @@ -2813,7 +2816,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); } @@ -2974,7 +2977,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); } @@ -3017,7 +3020,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); } @@ -3190,7 +3193,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); } @@ -3212,7 +3215,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); } @@ -3234,7 +3237,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); } @@ -3256,7 +3259,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); } @@ -3278,7 +3281,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } @@ -3300,7 +3303,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); } @@ -3322,7 +3325,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); } @@ -3344,7 +3347,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } @@ -3367,7 +3370,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); } @@ -3390,7 +3393,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); } @@ -3413,7 +3416,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); } @@ -3436,7 +3439,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); } @@ -3476,7 +3479,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); } @@ -3509,7 +3512,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); } @@ -3542,7 +3545,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); } @@ -3575,7 +3578,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); } @@ -3608,7 +3611,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); } @@ -3641,7 +3644,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); } @@ -3674,7 +3677,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); } @@ -3707,7 +3710,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); } @@ -3747,7 +3750,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); } @@ -3780,7 +3783,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); } @@ -3813,7 +3816,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); } @@ -3846,7 +3849,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); } @@ -3879,7 +3882,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); } @@ -3912,7 +3915,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); } @@ -3945,7 +3948,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); } @@ -4054,19 +4057,19 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) * @{ */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h index e07c232680..ed83b6c6ec 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h @@ -345,7 +345,7 @@ typedef struct * @} */ -/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported Macros Helper * @{ */ @@ -432,7 +432,7 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); } @@ -510,7 +510,7 @@ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32 * @arg @ref LL_USART_DIRECTION_TX * @arg @ref LL_USART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -544,7 +544,7 @@ __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) * @arg @ref LL_USART_PARITY_EVEN * @arg @ref LL_USART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -571,7 +571,7 @@ __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Me * @arg @ref LL_USART_WAKEUP_IDLELINE * @arg @ref LL_USART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); } @@ -598,7 +598,7 @@ __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataW * @arg @ref LL_USART_DATAWIDTH_8B * @arg @ref LL_USART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); } @@ -625,14 +625,14 @@ __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t Ov * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); } /** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput * @param USARTx USART Instance @@ -649,7 +649,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 /** * @brief Retrieve Clock pulse of the last data bit output configuration * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput * @param USARTx USART Instance @@ -657,14 +657,14 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); } /** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_SetClockPhase * @param USARTx USART Instance @@ -680,7 +680,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc /** * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_GetClockPhase * @param USARTx USART Instance @@ -688,14 +688,14 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc * @arg @ref LL_USART_PHASE_1EDGE * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); } /** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_SetClockPolarity * @param USARTx USART Instance @@ -711,7 +711,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C /** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_GetClockPolarity * @param USARTx USART Instance @@ -719,14 +719,14 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C * @arg @ref LL_USART_POLARITY_LOW * @arg @ref LL_USART_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); } /** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function @@ -754,7 +754,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, /** * @brief Enable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput * @param USARTx USART Instance @@ -767,7 +767,7 @@ __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Disable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput * @param USARTx USART Instance @@ -780,13 +780,13 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); } @@ -817,7 +817,7 @@ __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_STOPBITS_1_5 * @arg @ref LL_USART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); } @@ -875,14 +875,14 @@ __STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t Nod * @param USARTx USART Instance * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD)); } /** * @brief Enable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl * @param USARTx USART Instance @@ -895,7 +895,7 @@ __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl * @param USARTx USART Instance @@ -908,7 +908,7 @@ __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Enable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl * @param USARTx USART Instance @@ -921,7 +921,7 @@ __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl * @param USARTx USART Instance @@ -934,7 +934,7 @@ __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n * CR3 CTSE LL_USART_SetHWFlowCtrl @@ -953,7 +953,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard /** * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n * CR3 CTSE LL_USART_GetHWFlowCtrl @@ -964,7 +964,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard * @arg @ref LL_USART_HWCONTROL_CTS * @arg @ref LL_USART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -997,7 +997,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); } @@ -1042,7 +1042,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) { uint32_t usartdiv = 0x0U; uint32_t brrresult = 0x0U; @@ -1077,7 +1077,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t Pe /** * @brief Enable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_EnableIrda * @param USARTx USART Instance @@ -1090,7 +1090,7 @@ __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) /** * @brief Disable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_DisableIrda * @param USARTx USART Instance @@ -1103,20 +1103,20 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) /** * @brief Indicate if IrDA mode is enabled - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_IsEnabledIrda * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); } /** * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode * @param USARTx USART Instance @@ -1132,7 +1132,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P /** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode * @param USARTx USART Instance @@ -1140,7 +1140,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P * @arg @ref LL_USART_IRDA_POWER_NORMAL * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); } @@ -1148,7 +1148,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) /** * @brief Set Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler * @param USARTx USART Instance @@ -1163,13 +1163,13 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P /** * @brief Return Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler * @param USARTx USART Instance * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -1184,7 +1184,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) /** * @brief Enable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK * @param USARTx USART Instance @@ -1197,7 +1197,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Disable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK * @param USARTx USART Instance @@ -1210,20 +1210,20 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); } /** * @brief Enable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_EnableSmartcard * @param USARTx USART Instance @@ -1236,7 +1236,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) /** * @brief Disable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_DisableSmartcard * @param USARTx USART Instance @@ -1249,13 +1249,13 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard mode is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); } @@ -1263,7 +1263,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) /** * @brief Set Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler * @param USARTx USART Instance @@ -1278,13 +1278,13 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler * @param USARTx USART Instance * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -1292,7 +1292,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) /** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime * @param USARTx USART Instance @@ -1307,13 +1307,13 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime * @param USARTx USART Instance * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); } @@ -1328,7 +1328,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) /** * @brief Enable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex * @param USARTx USART Instance @@ -1341,7 +1341,7 @@ __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Disable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex * @param USARTx USART Instance @@ -1354,13 +1354,13 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); } @@ -1375,7 +1375,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) /** * @brief Set LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen * @param USARTx USART Instance @@ -1391,7 +1391,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 /** * @brief Return LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen * @param USARTx USART Instance @@ -1399,14 +1399,14 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LINBREAK_DETECT_10B * @arg @ref LL_USART_LINBREAK_DETECT_11B */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); } /** * @brief Enable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_EnableLIN * @param USARTx USART Instance @@ -1419,7 +1419,7 @@ __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) /** * @brief Disable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_DisableLIN * @param USARTx USART Instance @@ -1432,13 +1432,13 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) /** * @brief Indicate if LIN mode is enabled - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); } @@ -1493,7 +1493,7 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the USART in Synchronous mode. - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1531,7 +1531,7 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also set the UART/USART in LIN mode. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function @@ -1571,7 +1571,7 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - IREN bit in the USART_CR3 register, * This function also sets the UART/USART in Half Duplex mode. - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1610,7 +1610,7 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) * This function also configures Stop bits to 1.5 bits and * sets the USART in Smartcard mode (SCEN bit). * Clock Output is also enabled (CLKEN). - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1652,7 +1652,7 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1734,7 +1734,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE)); } @@ -1745,7 +1745,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE)); } @@ -1756,7 +1756,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE)); } @@ -1767,7 +1767,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE)); } @@ -1778,7 +1778,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE)); } @@ -1789,7 +1789,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE)); } @@ -1800,7 +1800,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC)); } @@ -1811,33 +1811,33 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE)); } /** * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD)); } /** * @brief Check if the USART CTS Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS)); } @@ -1848,7 +1848,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK)); } @@ -1859,7 +1859,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU)); } @@ -1983,7 +1983,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx) /** * @brief Clear LIN Break Detection Flag - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll SR LBD LL_USART_ClearFlag_LBD * @param USARTx USART Instance @@ -1996,7 +1996,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) /** * @brief Clear CTS Interrupt Flag - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll SR CTS LL_USART_ClearFlag_nCTS * @param USARTx USART Instance @@ -2072,7 +2072,7 @@ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) /** * @brief Enable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD * @param USARTx USART Instance @@ -2100,7 +2100,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Enable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS * @param USARTx USART Instance @@ -2168,7 +2168,7 @@ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) /** * @brief Disable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD * @param USARTx USART Instance @@ -2196,7 +2196,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Disable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS * @param USARTx USART Instance @@ -2213,7 +2213,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); } @@ -2224,7 +2224,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); } @@ -2235,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); } @@ -2246,7 +2246,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); } @@ -2257,20 +2257,20 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); } /** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); } @@ -2281,20 +2281,20 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); } /** * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); } @@ -2335,7 +2335,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); } @@ -2368,7 +2368,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); } @@ -2380,7 +2380,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx) { /* return address of DR register */ return ((uint32_t) &(USARTx->DR)); @@ -2400,7 +2400,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) { return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR)); } @@ -2411,7 +2411,7 @@ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) { return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR)); } @@ -2489,10 +2489,10 @@ __STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx) /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h index a7114cd02a..caabcf332e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h @@ -37,18 +37,24 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ +#ifndef HAL_USB_TIMEOUT +#define HAL_USB_TIMEOUT 0xF000000U +#endif /* define HAL_USB_TIMEOUT */ + +#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS +#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U +#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ /** * @brief USB Mode definition */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) typedef enum { - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1, - USB_DRD_MODE = 2 -} USB_OTG_ModeTypeDef; + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; /** * @brief URB States definition @@ -61,7 +67,7 @@ typedef enum URB_NYET, URB_ERROR, URB_STALL -} USB_OTG_URBStateTypeDef; +} USB_URBStateTypeDef; /** * @brief Host channel States definition @@ -71,13 +77,14 @@ typedef enum HC_IDLE = 0, HC_XFRC, HC_HALTED, + HC_ACK, HC_NAK, HC_NYET, HC_STALL, HC_XACTERR, HC_BBLERR, HC_DATATGLERR -} USB_OTG_HCStateTypeDef; +} USB_HCStateTypeDef; /** @@ -85,40 +92,41 @@ typedef enum */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t Host_channels; /*!< Host Channels number. + uint8_t Host_channels; /*!< Host Channels number. This parameter Depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t dma_enable; /*!< USB DMA state. + If DMA is not supported this parameter shall be set by default to zero */ - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ -} USB_OTG_CfgTypeDef; +} USB_CfgTypeDef; typedef struct { @@ -140,25 +148,25 @@ typedef struct uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + uint8_t even_odd_frame; /*!< IFrame parity This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ uint16_t tx_fifo_num; /*!< Transmission FIFO number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - uint32_t xfer_len; /*!< Current transfer length */ - uint32_t xfer_size; /*!< requested transfer size */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ -} USB_OTG_EPTypeDef; +} USB_EPTypeDef; typedef struct { @@ -179,8 +187,13 @@ typedef struct (HCD_DEVICE_SPEED_xxx) */ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ + uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ - uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ + uint8_t hub_port_nbr; /*!< USB HUB port number */ + uint8_t hub_addr; /*!< USB HUB address */ uint8_t ep_type; /*!< Endpoint Type. This parameter can be any value of @ref USB_LL_EP_Type */ @@ -193,7 +206,7 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - uint32_t XferSize; /*!< OTG Channel transfer size. */ + uint32_t XferSize; /*!< OTG Channel transfer size. */ uint32_t xfer_len; /*!< Current transfer length. */ @@ -208,15 +221,21 @@ typedef struct uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ uint32_t ErrCnt; /*!< Host channel error count. */ + uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + USB_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_URBStateTypeDef */ - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ -} USB_OTG_HCTypeDef; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + USB_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_HCStateTypeDef */ +} USB_HCTypeDef; +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -244,18 +263,6 @@ typedef struct * @} */ -/** @defgroup USB_LL Device Speed - * @{ - */ -#define USBD_HS_SPEED 0U -#define USBD_HSINFS_SPEED 1U -#define USBH_HS_SPEED 0U -#define USBD_FS_SPEED 2U -#define USBH_FSLS_SPEED 1U -/** - * @} - */ - /** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed * @{ */ @@ -319,7 +326,7 @@ typedef struct /** * @} */ - +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ @@ -331,6 +338,18 @@ typedef struct * @} */ +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + /** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed * @{ */ @@ -341,18 +360,30 @@ typedef struct * @} */ -/** @defgroup USB_LL_EP_Type USB Low Layer EP Type +/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type * @{ */ -#define EP_TYPE_CTRL 0U -#define EP_TYPE_ISOC 1U -#define EP_TYPE_BULK 2U -#define EP_TYPE_INTR 3U -#define EP_TYPE_MSK 3U +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U /** * @} */ +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines * @{ */ @@ -375,6 +406,16 @@ typedef struct * @} */ +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + /** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines * @{ */ @@ -390,16 +431,21 @@ typedef struct #define HCCHAR_BULK 2U #define HCCHAR_INTR 3U -#define HC_PID_DATA0 0U -#define HC_PID_DATA2 1U -#define HC_PID_DATA1 2U -#define HC_PID_SETUP 3U - #define GRXSTS_PKTSTS_IN 2U #define GRXSTS_PKTSTS_IN_XFER_COMP 3U #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U #define GRXSTS_PKTSTS_CH_HALTED 7U +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U +#define ISO_SPLT_MPS 188U + +#define HCSPLT_BEGIN 1U +#define HCSPLT_MIDDLE 2U +#define HCSPLT_END 3U +#define HCSPLT_FULL 4U + #define TEST_J 1U #define TEST_K 2U #define TEST_SE0_NAK 3U @@ -423,13 +469,9 @@ typedef struct + USB_OTG_HOST_CHANNEL_BASE\ + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #define EP_ADDR_MSK 0xFU - -#ifndef USE_USB_DOUBLE_BUFFER -#define USE_USB_DOUBLE_BUFFER 1U -#endif /* USE_USB_DOUBLE_BUFFER */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ @@ -460,55 +502,55 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); -uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); -uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html index 1fa103755e..997f338633 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html @@ -1,11459 +1,4189 @@ - - - - - - - - Release Notes for STM32F4xx HAL Drivers - -
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Back to - Release page

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Release - - - - Notes for STM32F4xx HAL Drivers

-

Copyright 2017 - STMicroelectronics

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-

Update - - - - History

V1.8.1 - / 24-June-2022

-
-

Main - - - - - Changes
-

-
-
  • General updates to fix HAL ETH defects and implementation enhancements.

  • HAL - updates

    - - -
      -
    • HAL ETH update
      • Remove useless assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)) from static function ETH_MACAddressConfig().
      • Replace hard coded Rx buffer size (1000U) by macro ETH_RX_BUF_SIZE.
      • Correct -bit positions when getting MAC and DMA configurations and replace -‘UnicastSlowProtocolPacketDetect’ by ‘UnicastPausePacketDetect’ in the -MAC default configuration structure.
      • Ensure a delay of 4 TX_CLK/RX_CLK cycles between two successive write operations to the same register.
      • Disable DMA transmission in both HAL_ETH_Stop_IT() and HAL_ETH_Stop() APIs.

V1.8.0 - / 11-February-2022

-
-

Main - - - - - Changes
-

-
-
    -
  • General updates to fix known defects and implementation enhancements.
    • -
  • All source files: update disclaimer to add reference to the new license agreement.
    -
    • -
  • The following changes done on the HAL drivers require an update of the application code based on older HAL versions
    • Rework of HAL Ethernet driver to resolve problems and improve performance (compatibility break). 
    • A new HAL Ethernet driver has been redesigned with new APIs, to bypass limitations with previous HAL Ethernet driver version.
    • The new HAL Ethernet driver is the -recommended version. It is located as usual in -Drivers/STM32F4xx_HAL_Driver/Src and Drivers/STM32F4xx_HAL_Driver/Inc -folders. 
      • It can be enabled through switch HAL_ETH_MODULE_ENABLED in stm32f4xx_hal_conf.h
    • The legacy HAL Ethernet driver is also -present in the release in Drivers/STM32F4xx_HAL_Driver/Src/Legacy and -Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software -compatibility reasons.
      • Its usage is not recommended as -deprecated. It can however be enabled through switch -HAL_ETH_LEGACY_MODULE_ENABLED in stm32f4xx_hal_conf.h
    -

  • HAL - updates

    - - -
      - - - - -
    • HAL ETH update -
        -
      • Entire receive process reworked.
      • Resolve the problem of received data corruption.
      • Implement transmission in interrupt mode.
      • Handle one interrupt for multiple transmitted packets.
      • Implement APIs to handle PTP feature.
      • Implement APIs to handle Timestamp feature.
      • Add support of receive buffer unavailable.
        • -
      • Update HAL_ETH_IRQHandler() to handle receive buffer unavailable.
        • - -
      • -
    • HAL SMBUS update
      • -
        -
      • Update to fix issue of mismatched data -received by master in case of data size to be transmitted by the slave -is greater than the data size to be received by the master.
        • -
          -
        • Add flush on TX register.
          • -
        -
      -
    • HAL TIM update
      • -
        -
      • __LL_TIM_CALC_PSC() macro update to round up the evaluate value when the fractional part of the division is greater than 0.5.
        • -
      - -
    • HAL LPTIM update
      • -
        -
      • Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()
        • -
      -
    • HAL UART update
      • -
        -
      • Add const qualifier for read only pointers.
        • -
      • Improve header description of UART_WaitOnFlagUntilTimeout() function.
        • -
      • Add a check on the UART parity before enabling the parity error interruption.
        • -
      • Fix typo in UART_IT_TXE bit description.
        -
        • - -
      -
    • HAL IRDA update
      • -
        -
      • Improve header description of IRDA_WaitOnFlagUntilTimeout() function.
        • -
      • Add a check on the IRDA parity before enabling the parity error interrupt.
        • -
      • Add const qualifier for read only pointers.
        • -
      -
    • HAL SMARTCARD update
      • -
        -
      • Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function
        • -
      • Add const qualifier for read only pointers.
        • -
      -
    • HAL NOR update
      • -
        -
      • Apply adequate commands according to the command set field value
        • -
      • command set 1 for Micron JS28F512P33
        • -
      • command set 2 for Micron M29W128G and Cypress S29GL128P
        • -
      • Add new command operations:
        • -
          -
        • NOR_CMD_READ_ARRAY
          • -
        • NOR_CMD_WORD_PROGRAM
          • -
        • NOR_CMD_BUFFERED_PROGRAM
          • -
        • NOR_CMD_CONFIRM
          • -
        • NOR_CMD_BLOCK_ERASE
          • -
        • NOR_CMD_BLOCK_UNLOCK
          • -
        • NOR_CMD_READ_STATUS_REG
          • -
        • NOR_CMD_CLEAR_STATUS_REG
          • -
        -
      • Update some APIs in order to be compliant for memories with different command set, the updated APIs are:
        • -
          -
        • HAL_NOR_Init()
          • -
        • HAL_NOR_Read_ID()
          • -
        • HAL_NOR_ReturnToReadMode()
          • -
        • HAL_NOR_Read()
          • -
        • HAL_NOR_Program()
          • -
        • HAL_NOR_ReadBuffer()
          • -
        • HAL_NOR_ProgramBuffer()
          • -
        • HAL_NOR_Erase_Block()
          • -
        • HAL_NOR_Erase_Chip()
          • -
        • HAL_NOR_GetStatus()
          • -
        -
      • Align HAL_NOR_Init() API with core of the function when write operation is disabled to avoid HardFault.
        • -
      -
    • HAL SDMMC update
      • -
        -
      • Take into account the voltage range in the CMD1 command.
        • -
      • Add new LL function to have correct response for MMC driver.
        • -
      • Update the driver to have all fields correctly initialized.
        • -
      • Add an internal variable to manage the power class and call it before to update speed of bus width.
        • -
      • Add new API to get the value of the Extended CSD register and populate the ExtCSD field of the MMC handle.
        • -
      • In HAL_MMC_InitCard(), call to SDIO_PowerState_ON() moved after -__HAL_MMC_ENABLE() to ensure MMC clock is enabled before the call to -HAL_Delay() from within SDIO_PowerState_ON().
        • -
      -
    • HAL DMA update
      • -
        -
      • Manage the case of an invalid value of CallbackID passed to the HAL_DMA_RegisterCallback() API.
        • -
      -
    • HAL LTDC update
      • -
        -
      • Update HAL_LTDC_DeInit() to fix MCU Hang up during LCD turn OFF.
        • -
      - -
    • HAL I2C update
      • -
        -
      • Update to fix issue detected due to low system frequency execution (HSI).
        • -
      • Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA
        • -
      • Update HAL I2C Master Receive IT process to safe manage data N= 2 and N= 3.
        • -
          -
        • Disable RxNE interrupt if nothing to do.
          • -
        -
      -
    • HAL USART update
      • -
        -
      • Improve header description of USART_WaitOnFlagUntilTimeout() function.
        • -
      • Add a check on the USART parity before enabling the parity error interrupt.
        • -
      • Add const qualifier for read only pointers.
        • -
      -
    • HAL/LL ADC update
      • -
        -
      • Update LL_ADC_IsActiveFlag_MST_EOCS() API to get the appropriate flag.
        • -
      • Better performance by removing multiple volatile reads or writes in interrupt handler.
        • -
      -
    • HAL FMPI2C update
      -
      • -
        -
      • Update to handle errors in polling mode.
        • -
          -
        • Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs.
          • -
        -
      -
    • HAL EXTI update
      • -
        -
      • Update HAL_EXTI_GetConfigLine() API to fix wrong calculation of GPIOSel value.
        • -
      -
    • HAL QSPI update
      • -
        -
      • Update HAL_QSPI_Abort() and  -HAL_QSPI_Abort_IT() APIs to check on QSPI BUSY flag status before -executing the abort procedure.
        • -
      - -
    • HAL/LL RTC cleanup
      • -
        -
      • Use bits definitions from CMSIS Device header file instead of hard-coded values.
        • -
      • Wrap comments to be 80-character long and correct typos.
        • -
      • Move constants RTC_IT_TAMP. from hal_rtc.h to hal_rtc_ex.h.
        • -
      • Gather all instructions related to exiting the "init" mode into new function RTC_ExitInitMode().
        • -
      • Add -new macro -assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, -sTamper->Trigger)) to check tamper filtering is disabled in case -tamper events are triggered on signal edges.
        • -
      • Rework functions HAL_RTCEx_SetTamper() and HAL_RTCEx_SetTamper_IT() to:
        • -
          -
        • Write in TAFCR register in one single access instead of two.
          • -
        • Avoid modifying user structure sTamper.
          • -
        -
      • Remove functions LL_RTC_EnablePushPullMode() and LL_RTC_DisablePushPullMode() as related to non-supported features.
        • -
      • Remove any reference to non-supported features (e.g., LL_RTC_ISR_TAMP3F).
        • -
      • Remove -useless conditional defines as corresponding features are supported by -all part-numbers (e.g., #if defined(RTC_TAFCR_TAMPPRCH)).
        • -
      -
    • HAL USB OTG update
      • -
        - - -
      • Fix USB_FlushRxFifo() and USB_FlushTxFifo() APIs by adding check on AHB master IDLE state before flushing the USB FIFO
        • -
      • Fix to avoid resetting host channel direction during channel halt
        • -
      • Fix to report correct received amount of data with USB DMA enabled
        • -
      • Fix to avoid compiler optimization on count variable used for USB HAL timeout loop check
        • -
      • Add missing registered callbacks check for HAL_HCD_HC_NotifyURBChange_Callback()
        • -
      • Add new API HAL_PCD_SetTestMode() APIs to handle USB device high speed Test modes
        • -
      • Setting SNAK for EPs not required during device reset
        • -
      • Update USB IRQ handler to enable EP OUT disable
        • -
      • Add support of USB IN/OUT Iso incomplete
        • -
      • Fix USB BCD data contact timeout
        -
        -
        • - -
      -
    -
    • + + + + + + + Release Notes for STM32F4xx HAL Drivers + + + + + + +
    +
    +
    +

    Release Notes for STM32F4xx HAL Drivers

    +

    Copyright © 2017 STMicroelectronics
    +

    + +
    +

    Purpose

    +

    The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

    +

    The Portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

    +

    The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provide basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not Fully Portable across the STM32 families; the availability of some functions depend on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

    +
      +
    • New set of inline function for direct and atomic register access
      • +
    • One-shot operations that can be used by the HAL drivers or from application level.
      • +
    • Fully Independent from HAL and can be used in standalone usage (without HAL drivers)
      • +
    • Full features coverage of the all the supported peripherals.
    -

    V1.7.13 - / 16-July-2021

    -
    -

    Main - - - - - Changes
    -

    -
    -
    • -

      HAL - updates

      - -
        -
      • HAL EXTI - update -
        • Update - HAL_EXTI_GetConfigLine() - API to set default - configuration value of - Trigger and GPIOSel - before checking each - corresponding registers.
        -
        • -
      • HAL GPIO - update -
        • Update - HAL_GPIO_Init() API to - avoid the configuration - of PUPDR register when - Analog mode is selected.
        -
        • -
      • HAL DMA - update -
        • Update - HAL_DMA_IRQHandler() API - to set the DMA state - before unlocking access - to the DMA handle.
        -
        • -
      • HAL/LL ADC - update -
        • Update - LL_ADC_DeInit() API to - clear missing SQR3 - register.
        • Update - LL_ADC_DMA_GetRegAddr() - API to prevent unused - argument compilation - warning.
        • Update HAL - timeout mechanism to - avoid false timeout - detection in case of - preemption.
        -
        • -
      • HAL CAN - update -
        • Update - HAL_CAN_Init() API to be - aligned with referance - manual and to avoid - timeout error:
        -
        • -
      • HAL/LL - RTC_BKP update -
        • Update - __HAL_RTC_…(__HANDLE__, - …) macros to access - registers through - (__HANDLE__)->Instance - pointer and avoid - “unused variable” - warnings.
        • Correct month - management in - IS_LL_RTC_MONTH() macro.
        -
        • -
      • HAL RNG - update -
        • Update timeout - mechanism to avoid false - timeout detection in - case of preemption.
        -
        • -
      • HAL QSPI - update -
        • ES0305 - workaround disabled for - STM32412xx devices.
        -
        • -
      • HAL I2C - update -
        • Update - HAL_I2C_Mem_Write_DMA() - and - HAL_I2C_Mem_Read_DMA() - APIs to initialize - Devaddress, Memaddress - and EventCount - parameters.
        • Update to - prevent several calls of - Start bit: -
          • Update - I2C_MemoryTransmit_TXE_BTF() - API to increment - EventCount.
          -
        • Update to - avoid I2C interrupt in - endless loop: -
          • Update - HAL_I2C_Master_Transmit_IT(), - HAL_I2C_Master_Receive_IT(), - - HAL_I2C_Master_Transmit_DMA() - - and - HAL_I2C_Master_Receive_DMA() - APIs to unlock the - I2C peripheral - before generating - the start.
          -
        • Update to use - the right macro to clear - I2C ADDR flag inside - I2C_Slave_ADDR() API as - it’s indicated in the - reference manual.
        • Update - I2C_IsAcknowledgeFailed() - API to avoid I2C in busy - state if NACK received - after transmitting - register address.
        • Update - HAL_I2C_EV_IRQHandler() - and - I2C_MasterTransmit_BTF() - APIs to correctly manage - memory transfers: -
          • Add check - on memory mode - before calling - callbacks - procedures.
          -
        -
        • -
      • LL USART - update -
        • Handling of - UART concurrent register - access in case of race - condition between Tx and - Rx transfers (HAL UART - and LL LPUART)
        -
        • -
      • HAL SMBUS - update -
        • Updated - HAL_SMBUS_ER_IRQHandler() - API to return the - correct error code - “SMBUS_FLAG_PECERR” in - case of packet error - occurs.
        -
        • -
      • HAL/LL SPI - update -
        • Updated to fix - MISRA-C 2012 Rule-13.2.
        • Update - LL_SPI_TransmitData8() - API to avoid casting the - result to 8 bits.
        -
        • -
      • HAL UART - update -
        • Fix wrong - comment related to RX - pin configuration within - the description section
        • Correction on - UART ReceptionType - management in case of - ReceptionToIdle API are - called from RxEvent - callback
        • Handling of - UART concurrent register - access in case of race - condition between Tx and - Rx transfers (HAL UART - and LL LPUART) -
          • Update CAN - Initialization - sequence to set - "request - initialization" bit - before exit from - sleep mode.
          -
        -
        • -
      • HAL USB - update -
        • HAL PCD: add - fix transfer complete - for IN Interrupt - transaction in single - buffer mode
        • Race condition - in USB PCD control - endpoint receive ISR.
        -
      -

    V1.7.12 - / 26-March-2021

    -

    Main - - - - - Changes

    -
      -
    • HAL
      • -
        -
      • HAL/LL - USART update
        • -
          -
        • Fix typo in - USART_Receive_IT() and - USART_TransmitReceive_IT() - APIs to avoid possible - compilation issues if the - UART driver files are not - included.
          • -
        -
      -
    -

    V1.7.11 - / 12-February-2021

    -

    Main - - - - - Changes

    -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • Added - - - - new HAL - - - - FMPSMBUS extended driver - - - - - to support FMPSMBUS fast Mode - Plus.
      • -
    • Removed - - - - “register” keyword to be - compliant with new C++ rules:
      • -
        -
      • The register - storage class specifier was - deprecated in C++11 and - removed in C++17.
        • -
      -
    • HAL
      • -
        -
      • HAL update
        • -
      • General - updates to fix known defects - and enhancements - implementation.
        • -
      • Added new - defines for ARM compiler V6:
        • -
          -
        • __weak
          • -
        • __packed
          • -
        • __NOINLINE
          • -
        -
      • Updated HAL TimeBase - TIM, RTC alarm and RTC WakeUp - templates for more robustness
        • -
          -
        • Updated Hal_Init_Tick() - API to propoerty - store the priority when - using the non-default time - base.
          • -
        -
      • Updated - PPP_MODULE_ENABLED for - FMPSMBUS.
        • -
      • HAL/LL ADC update
        • -
          -
        • Updated to - add include of the LL ADC - driver.
          • -
        • Updated the - following APIs to set status - HAL_ADC_STATE_ERROR_INTERNAL - and error code - HAL_ADC_ERROR_INTERNAL when - error occurs:
          • -
            -
          • HAL_ADC_Start()
            • -
          • HAL_ADC_Start_IT()
            • -
          • HAL_ADC_Start_DMA()
            • -
          • HAL_ADCEx_InjectedStart()
            • -
          • HAL_ADCEx_InjectedStart_IT()
            • -
          • HAL_ADCEx_MultiModeStart_DMA()
            • -
          -
        • Updated HAL_ADC_Stop_DMA() - API to check if DMA state is - Busy before calling HAL_DMA_Abort() - - - - - API to avoid DMA internal - error.
          • -
        • Updated - IS_ADC_CHANNEL to support - temperature sensor for:
          • -
            -
          • STM32F411xE
            • -
          • STM32F413xx
            • -
          • STM32F423xx
            • -
          -
        • Fixed wrong - defined values for:
          • -
            -
          • LL_ADC_MULTI_REG_DMA_LIMIT_3
            • -
          • LL_ADC_MULTI_REG_DMA_UNLMT_3
            • -
          -
        • Added - __LL_ADC_CALC_VREFANALOG_VOLTAGE() - macro to evaluate analog - reference voltage.
          • -
        • Removed - __LL_ADC_CALC_TEMPERATURE() - macro for STM32F4x9 devices - as the TS_CAL2 is not - available.
          • -
        -
      • HAL/LL DAC update
        • -
          -
        • Added restruction - on DAC Channel 2 defines and - parametres.
          • -
        • HAL_DAC_MSPINIT_CB_ID - - - - - and HAL_DAC_MSPDEINIT_CB_ID - used instead of - HAL_DAC_MSP_INIT_CB_ID and - HAL_DAC_MSP_DEINIT_CB_ID.
          • -
        • Updated to - support dual mode:
          • -
            -
          • Added two - new APIs:
            • -
              -
            • HAL_DACEx_DualStart()
              • -
            • HAL_DACEx_DualStop()
              • -
            -
          -
        • Added - position bit definition to - be used instead of - __DAC_MASK_SHIFT macro
          • -
            -
          • __DAC_MASK_SHIFT - - - - macro has been removed.
            • -
          -
        • Updated HAL_DAC_Start_DMA() - API to return HAL_ERROR when - error occurs.
          • -
        • Updated HAL_DAC_Stop_DMA() - API to not return HAL_ERROR - when DAC is already - disabled.
          • -
        -
      • HAL CEC update
        • -
          -
        • Updated HAL_CEC_IRQHandler() - API to avoid appending an - extra byte to the end of a - message.
          • -
        -
      • HAL/LL GPIO update
        • -
          -
        • Updated - IS_GPIO_AF() to - add missing values for - STM32F401xC and STM32F401xE - devices:
          • -
            -
          • GPIO_AF3_TIM9
            • -
          • GPIO_AF3_TIM10
            • -
          • GPIO_AF3_TIM11
            • -
          -
        • Updated - LL/HAL GPIO_TogglePin() - APIs to allow multi Pin’s - toggling.
          • -
        • Updated HAL_GPIO_Init() - API to avoid the - configuration of PUPDR - register when Analog mode is - selected.
          • -
        -
      • HAL/LL RCC update
        • -
          -
        • Updated HAL_RCC_OscConfig() - API to add missing checks - and to don’t return - HAL_ERROR if request repeats - the current PLL - configuration.
          • -
        • Updated - IS_RCC_PLLN_VALUE(VALUE) - macro in case of STM32F411xE - device in order to - be aligned with reference - manual.
          • -
        -
      • HAL SD update
        • -
          -
        • Update - function SD_FindSCR() - to resolve issue of FIFO - blocking when reading.
          • -
        • Update - read/write functions in DMA - mode in - - - - order to - force the DMA direction, - updated functions:
          • -
            -
          • HAL_SD_ReadBlocks_DMA()
            • -
          • HAL_SD_WriteBlocks_DMA()
            • -
          -
        • Add the - block size settings in the - initialization functions and - remove it from read/write - transactions to avoid - repeated and inefficient - reconfiguration, updated - functions:
          • -
            -
          • HAL_SD_InitCard()
            • -
          • HAL_SD_GetCardStatus()
            • -
          • HAL_SD_ConfigWideBusOperation() 
            • -
          • HAL_SD_ReadBlocks()
            • -
          • HAL_SD_WriteBlocks()
            • -
          • HAL_SD_ReadBlocks_IT()
            • -
          • HAL_SD_WriteBlocks_IT()
            • -
          • HAL_SD_ReadBlocks_DMA()
            • -
          • HAL_SD_WriteBlocks_DMA()
            • -
          -
        -
      • HAL MMC update
        • -
          -
        • Add the - block size settings in the - initialization function and - remove it from read/write - transactions to avoid - repeated and inefficient - reconfiguration, updated - functions:
          • -
            -
          • HAL_MMC_InitCard()
            • -
          • HAL_MMC_ReadBlocks()
            • -
          • HAL_MMC_WriteBlocks()
            • -
          • HAL_MMC_ReadBlocks_IT()
            • -
          • HAL_MMC_WriteBlocks_IT()
            • -
          • HAL_MMC_ReadBlocks_DMA()
            • -
          • HAL_MMC_WriteBlocks_DMA()
            • -
          -
        • Update - read/write functions in DMA - mode in - - - - order to - force the DMA direction, - updated functions:
          • -
            -
          • HAL_MMC_ReadBlocks_DMA()
            • -
          • HAL_MMC_WriteBlocks_DMA()
            • -
          -
        • Deploy new - functions MMC_ReadExtCSD() - and SDMMC_CmdSendEXTCSD - () that read and check the - sectors number of the - device in order to resolve - the issue of wrongly reading - big memory size.
          • -
        -
      • HAL NAND - update
        • -
          -
        • Update - functions - HAL_NAND_Read_SpareArea_16b() - and - HAL_NAND_Write_SpareArea_16b() - to fix column address - calculation issue.
          • -
        -
      • LL SDMMC - update
        • -
          -
        • Update the - definition of - SDMMC_DATATIMEOUT constant in - - - - order to - allow the user to redefine - it in his proper - application.
          • -
        • Remove - 'register' storage class - specifier from LL SDMMC - driver.
          • -
        • Deploy new - functions MMC_ReadExtCSD() - and SDMMC_CmdSendEXTCSD - () that read and check the - sectors number of the device - in order to resolve the - issue of wrongly reading big - memory size.
          • -
        -
      • HAL SMBUS update
        • -
          -
        • Support for - Fast Mode Plus to be SMBUS - rev 3 compliant.
          • -
        • Added HAL_FMPSMBUSEx_EnableFastModePlus() - and HAL_FMPSMBUSEx_DisableFastModePlus() - - - - - APIs to manage Fm+.
          • -
        • Updated SMBUS_MasterTransmit_BTF() - , SMBUS_MasterTransmit_TXE() - - - - - and SMBUS_MasterReceive_BTF() - - - - - APIs to allow stop - generation when CurrentXferOptions - is different from - SMBUS_FIRST_FRAME and - SMBUS_NEXT_FRAME.
          • -
        • Updated SMBUS_ITError() - API to correct the twice - call of HAL_SMBUS_ErrorCallback.
          • -
        -
      • HAL SPI update
        • -
          -
        • Updated HAL_SPI_Init() - API
          • -
            -
          • To avoid - setting the BaudRatePrescaler - in case of Slave Motorola - Mode.
            • -
          • Use the bit-mask - for SPI configuration.
            • -
          -
        • Updated - Transmit/Receive processes - in half-duplex mode
          • -
            -
          • Disable - the SPI instance before - setting BDIOE bit.
            • -
          -
        • Fixed wrong - timeout management
          • -
        • Calculate - Timeout based on a software - loop to avoid blocking issue - if Systick - is disabled.
          • -
        -
      • HAL - SPDIFRX update
        • -
          -
        • Remove - 'register' storage class - specifier from HAL SPDIFRX - driver.
          • -
        -
      • HAL I2S update
        • -
          -
        • Updated - I2SEx APIs to correctly - support circular transfers
          • -
            -
          • Updated - I2SEx_TxRxDMACplt() - API to manage DMA circular - mode.
            • -
          -
        • Updated - HAL_I2SEx_TransmitReceive_DMA() - API to set hdmatx - (transfert - callback and half) to NULL.
          • -
        -
      • HAL SAI update
        • -
          -
        • Updated to - avoid the incorrect - left/right synchronization.
          • -
            -
          • Updated HAL_SAI_Transmit_DMA() - API to follow the sequence - described in the reference - manual for slave - transmitter mode.
            • -
          -
        • Updated HAL_SAI_Init() - API to correct the formula - in case of SPDIF is wrong.
          • -
        -
      • HAL CRYP update
        • -
          -
        • Updated HAL_CRYP_SetConfig() - and HAL_CRYP_GetConfig() - - - - - APIs to set/get the - continent of KeyIVConfigSkip - correctly.
          • -
        -
      • HAL EXTI update
        • -
          -
        • __EXTI_LINE__ - - - - is now used instead of - __LINE__ which is a standard - C macro.
          • -
        -
      • HAL DCMI
        • -
          -
        • Support of - HAL callback registration - feature for DCMI extended - driver.
          • -
        -
      • HAL/LL TIM update
        • -
          -
        • Updated HAL_TIMEx_OnePulseN_Start() - and HAL_TIMEx_OnePulseN_Stop() - - - - - APIs (pooling and IT mode) - to take into consideration - all OutputChannel - parameters.
          • -
        • Corrected - reversed description of - TIM_LL_EC_ONEPULSEMODE One - Pulse Mode.
          • -
        • Updated LL_TIM_GetCounterMode() - API to return the correct - counter mode.
          • -
        -
      • HAL/LL - SMARTCARD update
        • -
          -
        • Fixed - invalid initialization of - SMARTCARD configuration by - removing FIFO mode - configuration as it is not - member of SMARTCARD_InitTypeDef - Structure.
          • -
        • Fixed typos - in SMARTCARD State - definition description
          • -
        -
      • HAL/LL IRDA update
        • -
          -
        • Fixed typos - in IRDA State definition - description
          • -
        -
      • LL USART update
        • -
          -
        • Remove - useless check on maximum BRR - value by removing - IS_LL_USART_BRR_MAX() - macro.
          • -
        • Update - USART polling and - interruption processes to - fix issues related to - accesses out of user - specified buffer.
          • -
        -
      • HAL USB update
        • -
          -
        • Enhanced - USB OTG host HAL with USB - DMA is enabled:
          • -
            -
          • fixed - ping and data toggle - issue,
            • -
          • reworked - Channel error report - management
            • -
          -
        -
      -
    -

    V1.7.10 - - - - / 22-October-2020

    -

    Main Changes

    -
      -
    • General - - - - updates to fix known defects.
      • -
    • HAL/LL - - - - I2C update
      • -
    -
      -
        -
      •   Update - to fix hardfault - issue with HAL_I2C_Mem_Write_DMA() - API:
        • -
          -
        •   - Abort the right ongoing DMA - transfer when memory write - access request operation - failed: fix typo “hdmarx” - replaced by “hdmatx”
          • -
        -
      -
    -

    V1.7.9 - - - - / 14-August-2020

    -

    Main Changes

    -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • HAL/LL - - - - I2C update
      • -
    -
      -
        -
      •   Update - HAL_I2C_ER_IRQHandler() - API to fix acknowledge failure - issue with I2C memory IT - processes
        • -
          -
        •   Add - stop condition generation - when NACK occurs.
          • -
        -
      •   Update - I2C_DMAXferCplt(), - - - - - I2C_DMAError() and - I2C_DMAAbort() APIs to fix hardfault - issue when hdmatx - and hdmarx - parameters in i2c handle - aren't initialized (NULL - pointer).
        • -
          -
        •   Add - additional check on - hi2c->hdmtx - and hi2c->hdmarx - before resetting DMA Tx/Rx - complete callbacks
          • -
        -
      •   Update - Sequential transfer APIs to - adjust xfermode - condition.
        • -
          -
        •   - - - - - Replace hi2c->XferCount - < MAX_NBYTE_SIZE by - hi2c->XferCount - <= MAX_NBYTE_SIZE which - corresponds to a case - without reload
          • -
        -
      -
    -
      -
    •  HAL/LL - - - - USB update
      • -
        -
      •   Bug - - - - fix: USB_ReadPMA() - and USB_WritePMA() - - - - - by ensuring 16-bits access to - USB PMA memory
        • -
      •   Bug - - - - fix: correct USB RX count - calculation
        • -
      •   Fix - USB Bulk transfer double - buffer mode
        • -
      •   Remove - register keyword from USB - defined macros as no more - supported by C++ compiler
        • -
      •   Minor - rework on USBD_Start() - and USBD_Stop() - - - - - APIs: stopping device will be - handled by HAL_PCD_DeInit() - - - - - API.
        • -
      •   Remove - non used API for USB device - mode.
        • -
      -
    -

    V1.7.8 - - - - / 12-February-2020

    -

    Main Changes

    -
      -
    • Add - new HAL FMPSMBUS and LL - - - - FMPI2C drivers
      • -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    -
      -
    • Update - - - - HAL CRYP driver to support block - by block decryption without - reinitializes the IV and KEY for - each call.
      • -
    • Improve - - - - code quality by fixing - MisraC-2012 violations
      • -
    • HAL/LL - - - - USB update
      • -
        -
      •  Add - handling USB host babble error - interrupt
        • -
      •  Fix - Enabling ULPI interface for - platforms that integrates USB - HS PHY
        • -
      •  Fix - Host data toggling for IN Iso - transfers
        • -
      •  Ensure - to disable USB EP during - endpoint deactivation
        • -
      -
    • HAL - - - - CRYP update
      • -
        -
      •  Update - HAL CRYP driver to support - block by block decryption - without initializing the IV - and KEY at each call.
        • -
          -
        • Add new - CRYP Handler parameters: "KeyIVConfig" - and "SizesSum"
          • -
        • Add new - CRYP init - parameter: "KeyIVConfigSkip"
          • -
        -
      -
    • HAL - - - - I2S update
      • -
        -
      • Update - HAL_I2S_DMAStop() - API to be more safe
        • -
          -
        • Add a check - on BSY, TXE and RXNE flags - before disabling the I2S
          • -
        -
      • Update - HAL_I2S_DMAStop() - API to fix multi-call transfer - issue(to avoid re-initializing - the I2S for the next - transfer).
        • -
          -
        • Add - __HAL_I2SEXT_FLUSH_RX_DR() - and __HAL_I2S_FLUSH_RX_DR() - macros to flush the - remaining data inside DR - registers.
          • -
        • Add new ErrorCode - define: - HAL_I2S_ERROR_BUSY_LINE_RX
          • -
        -
      -
    -

    V1.7.7 - - - - / 06-December-2019

    -

    Main Changes

    -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • HAL - - - - Generic update
      • -
        -
      • HAL_SetTickFreq(): update to - restore the previous tick - frequency when HAL_InitTick() - - - - - configuration failed.
        • -
      -
    • HAL/LL - - - - GPIO update
      • -
        -
      • Update GPIO - initialization sequence to - - - - avoid unwanted pulse on GPIO Pin's
        • -
      -
    • HAL - - - - EXTI update
      • -
    -
      -
        -
      • General - update to enhance HAL EXTI - driver robustness 
        • -
          -
        • Add - additional assert check on - EXTI config lines
          • -
        • Update to - compute EXTI line mask - before read/write access - to EXTI registers
          -
          -
          • -
        -
      • Update EXTI - callbacks management to be - compliant with reference - manual: only one PR - register for rising and - falling interrupts.
        • -
          -
        • Update - parameters in EXTI_HandleTypeDef - structure: merge HAL - EXTI RisingCallback - and FallingCallback - in only one PendingCallback
          • -
        • Remove - HAL_EXTI_RISING_CB_ID and - HAL_EXTI_FALLING_CB_ID - values from EXTI_CallbackIDTypeDef - enumeration.
          -
          -
          • -
        -
      • Update - HAL_EXTI_IRQHandler() - API to serve interrupts - correctly.
        • -
          -
        • Update to - compute EXTI line mask - before handle - EXTI interrupt.
          • -
        -
      • Update to - support GPIO port - interrupts:
        • -
          -
        • Add new "GPIOSel" - parameter in EXTI_ConfigTypeDef - structure
          • -
        -
      -
    • HAL/LL - - - - RCC update
      • -
        -
      • Update HAL_RCCEx_PeriphCLKConfig() - API to support PLLI2S - configuration for STM32F42xxx - and STM32F43xxx devices
        • -
      • Update the HAL_RCC_ClockConfig() - and HAL_RCC_DeInit() - - - - - API to don't overwrite the - custom tick priority
        • -
      • Fix LL_RCC_DeInit() - failure detected with gcc - compiler and high optimization - level is selected(-03)
        • -
      • Update HAL_RCC_OscConfig() - API to don't return - HAL_ERROR if request repeats - the current PLL configuration
        • -
      -
    • HAL - - - - ADC update
      • -
        -
      • Update LL_ADC_REG_Init() - to fix wrong ADC CR1 register - configuration
        • -
          -
        • The ADC - sequencer length is part - of ADC SQR1 - register not of ADC CR1 - register
          • -
        -
      -
    • HAL - - - - CRYP update
      • -
        -
      • Update HAL_CRYP_Encrypt() - and HAL_CRYP_Decrypt() - - - - - APIs to take into - consideration the datatype fed - to the DIN register (1-, 8-, - 16-, or 32-bit data) when - padding the last block of the - payload, in case the size of - this last block is less than - 128 bits.
        • -
      -
    • HAL - - - - RNG update
      • -
        -
      • Update HAL_RNG_IRQHandler() - API to fix error code - management issue: error code - is assigned - "HAL_RNG_ERROR_CLOCK" in case - of clock error and - "HAL_RNG_ERROR_SEED" in case - of seed error, not the - opposite.
        • -
      -
    • HAL - - - - DFSDM update
      • -
        -
      • Update DFSDM_GetChannelFromInstance() - API to remove unreachable - check condition
        • -
      -
    • HAL - - - - DMA update
      • -
        -
      • Update HAL_DMA_Start_IT() - API to omit the FIFO error
        • -
      -
    • HAL - - - - FLASH update
      • -
        -
      • Update FLASH_Program_DoubleWord() - API to fix with EWARM high - level optimization issue
        • -
      -
    • HAL - - - - QSPI update
      • -
        -
      • Remove Lock - mechanism from HAL_QSPI_Init() - and HAL_QSPI_DeInit() - - - - - APIs
        • -
      -
    • HAL - - - - HASH update
      • -
        -
      • Null pointer - on handler "hhash" - is now checked before - accessing structure member "hhash->Init.DataType" - in the following API:
        • -
          -
        • HAL_HASH_Init()
          • -
        -
      • Following interrupt-based - APIs have been added. - Interrupt mode could allow the - MCU to enter "Sleep" mode - while a data block is being - processed. Please refer to the - "##### How to use this driver - #####" section for details - about their use.
        • -
          -
        • HAL_HASH_SHA1_Accmlt_IT()
          • -
        • HAL_HASH_MD5_Accmlt_IT()
          • -
        • HAL_HASHEx_SHA224_Accmlt_IT()
          • -
        • HAL_HASHEx_SHA256_Accmlt_IT()
          • -
        -
      • Following aliases - have been added (just for - clarity sake) as they - shall be used at the end - of the computation of a - multi-buffers message and not - at the start:
        • -
          -
        • HAL_HASH_SHA1_Accmlt_End() - to be used instead of - HAL_HASH_SHA1_Start()
          • -
        • HAL_HASH_MD5_Accmlt_End() - to be used instead of - HAL_HASH_MD5_Start()
          • -
        • HAL_HASH_SHA1_Accmlt_End_IT() - to be used instead of - HAL_HASH_SHA1_Start_IT()
          • -
        • HAL_HASH_MD5_Accmlt_End_IT() - to be used instead of - HAL_HASH_MD5_Start_IT()
          • -
        • HAL_HASHEx_SHA224_Accmlt_End() - to be used instead of - HAL_HASHEx_SHA224_Start()
          • -
        • HAL_HASHEx_SHA256_Accmlt_End() - to be used instead of - HAL_HASHEx_SHA256_Start()
          • -
        -
      -
    -
      -
        -
          -
        • HAL_HASHEx_SHA224_Accmlt_End_IT() - to be used instead of - HAL_HASHEx_SHA224_Start_IT()
          • -
        • HAL_HASHEx_SHA256_Accmlt_End_IT() - to be used instead of - HAL_HASHEx_SHA256_Start_IT()
          • -
        -
      -
    -
      -
        -
      • MISRAC-2012 - rule R.5.1 (identifiers - shall be distinct in the first - 31 characters) constrained the - naming of the above listed - aliases (e.g. - HAL_HASHEx_SHA256_Accmlt_End() - could not be named - HAL_HASHEx_SHA256_Accumulate_End(). - - - - - Otherwise the name would have - conflicted with - HAL_HASHEx_SHA256_Accumulate_End_IT()). - In - - - - - order to - have aligned names following - APIs have been renamed:
        • -
      -
    -
      -
        -
          -
            -
          • HAL_HASH_MD5_Accumulate() - renamed - HAL_HASH_MD5_Accmlt()
            • -
          • HAL_HASH_SHA1_Accumulate() - renamed - HAL_HASH_SHA1_Accmlt()
            • -
          • HAL_HASHEx_SHA224_Accumulate() - renamed - HAL_HASHEx_SHA224_Accmlt()
            • -
          -
        -
      -
    -
      -
        -
          -
            -
          • HAL_HASHEx_SHA256_Accumulate() - renamed - HAL_HASHEx_SHA256_Accmlt()
            • -
          -
        -
      -
    -
      -
        -
      • HASH handler - state is no more - reset to HAL_HASH_STATE_READY - once DMA has been started - in the following APIs:
        • -
          -
        • HAL_HASH_MD5_Start_DMA()
          • -
        • HAL_HMAC_MD5_Start_DMA()
          • -
        • HAL_HASH_SHA1_Start_DMA()
          • -
        • HAL_HMAC_SHA1_Start_DMA()
          • -
        -
      • HASH phase - state is now set to - HAL_HASH_PHASE_READY once - the digest has been read - in the following APIs:
        • -
          -
        • HASH_IT()
          • -
        • HMAC_Processing()
          • -
        • HASH_Start()
          • -
        • HASH_Finish()
          • -
        -
      • Case of a - large buffer scattered around - in memory each piece of which - is not necessarily a multiple - - - - of 4 bytes in length.
        • -
          -
        • In section - "##### How to use this - driver #####", sub-section - "*** Remarks on message - length ***" added to provide - recommendations to follow in - such case.
          • -
        • No - modification of the driver - as the root-cause is at - design-level.
          • -
        -
      -
    -
      -
    • HAL CAN - - - - update
      • -
        -
      • HAL_CAN_GetRxMessage() update to - get the correct value for the - RTR (type of frame for - the message that will be - transmitted) field in the CAN_RxHeaderTypeDef - structure.
        • -
      -
    • HAL - - - - DCMI update
      • -
        -
      • Add new HAL_DCMI_ConfigSyncUnmask() - API to set embedded - synchronization delimiters - unmasks.
        • -
      -
    • HAL - - - - RTC update
      • -
        -
      • Following IRQ - handlers' implementation has - been aligned with the - STM32Cube firmware - specification (in case of - interrupt lines shared by - multiple events, first check - the IT enable bit is set then - check the IT flag is set too):
        • -
          -
        • HAL_RTC_AlarmIRQHandler()
          • -
        • HAL_RTCEx_WakeUpTimerIRQHandler()
          • -
        • HAL_RTCEx_TamperTimeStampIRQHandler()
          • -
        -
      -
    -
      -
    • HAL - - - - WWDG update
      • -
        -
      • In "##### - WWDG Specific features #####" - descriptive comment section:
        • -
          -
        • Maximal prescaler - value has been corrected (8 - instead of 128).
          • -
        • Maximal APB - frequency has been corrected - (42MHz instead of 56MHz) and - possible timeout values - updated.
          • -
        -
      -
    • HAL - - - - DMA2D update
      • -
    -
      -
        -
      • Add the - following API's to Start DMA2D - CLUT Loading.
        • -
          -
        • HAL_DMA2D_CLUTStartLoad() - Start DMA2D CLUT Loading.
          • -
        • HAL_DMA2D_CLUTStartLoad_IT() - Start DMA2D CLUT Loading - with interrupt enabled.
          • -
        -
      • The following - old wrong services will be - kept in the HAL DCMI driver - for legacy purpose and a - specific Note is added:
        • -
          -
        • HAL_DMA2D_CLUTLoad() - can be replaced with - HAL_DMA2D_CLUTStartLoad()
          • -
        • HAL_DMA2D_CLUTLoad_IT() can - - - - - be replaced with - HAL_DMA2D_CLUTStartLoad_IT()
          • -
        • HAL_DMA2D_ConfigCLUT() - can be omitted as the config - can be performed using - the HAL_DMA2D_CLUTStartLoad() - API.
          • -
        -
      -
    -
      -
    • HAL - - - - SDMMC update
      • -
        -
      • Fix  - typo in "FileFormatGroup" - parameter in the HAL_MMC_CardCSDTypeDef - and HAL_SD_CardCSDTypeDef - structures 
        • -
      • Fix an - improve handle state and - error management
        • -
      • Rename the - defined MMC card capacity type - to be more meaningful:
        • -
          -
        • Update MMC_HIGH_VOLTAGE_CARD to - - - - - MMC LOW_CAPACITY_CARD
          • -
        • Update MMC_DUAL_VOLTAGE_CRAD - to MMC_HIGH_CAPACITY_CARD
          • -
        -
      • Fix - management of peripheral - flags depending on commands - or data transfers
        • -
          -
        • Add new - defines - "SDIO_STATIC_CMD_FLAGS" - and "SDIO_STATIC_DATA_FLAGS" 
          • -
        • Updates HAL - - - - SD and HAL MMC drivers to - manage the new SDIO static - flags.
          -
          -
          • -
        -
      • Due to - limitation SDIO hardware flow - control indicated in Errata - Sheet:
        • -
          -
        • In 4-bits - bus wide mode, do not use - the HAL_SD_WriteBlocks_IT() - or HAL_SD_WriteBlocks() - - - - - APIs otherwise underrun will - occur and it isn't possible - to activate the flow - control.
          • -
        • Use DMA - mode when using 4-bits bus - wide mode or decrease the - SDIO_CK frequency.
          • -
        -
      -
    • HAL - - - - UART update
      • -
        -
      • Update UART - polling processes to handle - efficiently the Lock mechanism
        • -
          -
        •  Move - the process unlock at the - top of the HAL_UART_Receive() - and HAL_UART_Transmit() - - - - - API.
          • -
        -
      • Fix baudrate - calculation error for clock - higher than 172Mhz
        • -
          -
        • Add a - forced cast on - UART_DIV_SAMPLING8() and - UART_DIV_SAMPLING16() - macros.
          • -
        • Remove - useless parenthesis from - UART_DIVFRAQ_SAMPLING8(), - UART_DIVFRAQ_SAMPLING16(), - UART_BRR_SAMPLING8() and - UART_BRR_SAMPLING16() macros - to solve some MISRA - warnings.
          • -
        -
      • Update UART - interruption handler to manage - correctly the overrun interrupt
        • -
          -
        • Add in - the HAL_UART_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
          • -
        -
      • Fix baudrate - calculation error UART9 - and UART10
        • -
          -
        • In UART_SetConfig() - API fix UART9 and UART10 - clock source when computing - baudrate - values by adding a check on - these instances and setting - clock sourcePCLK2 instead of - PCLK1.
          • -
        -
      • Update UART_SetConfig() - API
        • -
          -
        • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the - UART_BRR_SAMPLING8() and - UART_BRR_SAMPLING8() - macros 
          • -
        -
      -
    • HAL - - - - USART update
      • -
        -
      • Fix baudrate - calculation error for clock - higher than 172Mhz
        • -
          -
        • Add a - forced cast on USART_DIV() - macro.
          • -
        • Remove - useless parenthesis - from USART_DIVFRAQ() - macro to solve some MISRA - warnings.
          • -
        -
      • Update USART - interruption handler to manage - correctly the overrun interrupt
        • -
          -
        • Add in - the HAL_USART_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
          • -
        -
      • Fix baudrate - calculation error UART9 - and UART10
        • -
          -
        • In USART_SetConfig() - API fix UART9 and UART10 - clock source when computing - baudrate - values by adding a check on - these instances and setting - clock sourcePCLK2 instead of - PCLK1.
          • -
        -
      • Update USART_SetConfig() - API
        • -
          -
        • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the USART_BRR() - macro
          • -
        -
      -
    • HAL - - - - IRDA update
      • -
        -
      • Fix baudrate - calculation error for clock - higher than 172Mhz
        • -
          -
        • Add a - forced cast on IRDA_DIV() - macro.
          • -
        • Remove - useless parenthesis - from IRDA_DIVFRAQ() - macro to solve some - MISRA warnings.
          • -
        -
      • Update IRDA - interruption handler to manage - correctly the overrun interrupt
        • -
          -
        • Add in - the HAL_IRDA_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
          • -
        -
      • Fix baudrate - calculation error UART9 - and UART10
        • -
          -
        • In IRDA_SetConfig() - API fix UART9 and UART10 - clock source when computing - baudrate - values by adding a check on - these instances and setting - clock sourcePCLK2 instead of - PCLK1.
          • -
        -
      • Update IRDA_SetConfig() - API
        • -
          -
        • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the IRDA_BRR() - macro
          • -
        -
      -
    • HAL - - - - SMARTCARD update
      • -
        -
      • Fix baudrate - calculation error for clock - higher than 172Mhz
        • -
          -
        • Add a - forced cast on SMARTCARD_DIV() - macro.
          • -
        • Remove useless parenthesis - - - - - from SMARTCARD_DIVFRAQ() - macro to solve some - MISRA warnings.
          • -
        -
      • Update - SMARTCARD interruption handler - to manage correctly the - overrun interrupti
        • -
          -
        • Add in - the HAL_SMARTCARD_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
          • -
        -
      • Update SMARTCARD_SetConfig() - API
        • -
          -
        • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the - SMARTCARD_BRR() macro
          • -
        -
      -
    • HAL - - - - TIM update
      • -
        -
      • Add new - macros to enable and disable - the fast mode when using the - one pulse mode to output a - waveform with a minimum delay
        • -
          -
        • __HAL_TIM_ENABLE_OCxFAST() - and __HAL_TIM_DISABLE_OCxFAST().
          • -
        -
      • Update - Encoder interface mode to - keep TIM_CCER_CCxNP - bits low
        • -
          -
        • Add TIM_ENCODERINPUTPOLARITY_RISING - - - - - and - TIM_ENCODERINPUTPOLARITY_FALLING - definitions to determine - encoder input polarity.
          • -
        • Add - IS_TIM_ENCODERINPUT_POLARITY() - macro to check the - encoder input polarity.
          • -
        • Update HAL_TIM_Encoder_Init() - API 
          • -
            -
          • Replace - IS_TIM_IC_POLARITY() - macro by - IS_TIM_ENCODERINPUT_POLARITY() - macro.
            • -
          -
        -
      • Update TIM - remapping input configuration - in HAL_TIMEx_RemapConfig() - API
        • -
          -
        • Remove - redundant check on - LPTIM_OR_TIM5_ITR1_RMP bit - and replace it by check on - LPTIM_OR_TIM9_ITR1_RMP bit.
          • -
        -
      • Update HAL_TIMEx_MasterConfigSynchronization() - API to avoid functional errors - and assert fails when using - some TIM instances as input - trigger.
        • -
          -
        • Replace IS_TIM_SYNCHRO_INSTANCE() - macro by - IS_TIM_MASTER_INSTANCE() - macro. 
          • -
        • Add IS_TIM_SLAVE_INSTANCE() - macro to check on - TIM_SMCR_MSM bit.
          • -
        -
      • Add lacking - TIM input remapping definition 
        • -
          -
        • Add - LL_TIM_TIM11_TI1_RMP_SPDIFRX - and - LL_TIM_TIM2_ITR1_RMP_ETH_PTP.
          • -
        • Add lacking - definition for linked - LPTIM_TIM input trigger remapping  
          • -
            -
          • Add - following definitions - - - - - : - LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO, - LL_TIM_TIM9_ITR1_RMP_LPTIM, - - - - LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO, - - - - - LL_TIM_TIM5_ITR1_RMP_LPTIM, - - - - LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO - - - - and - LL_TIM_TIM1_ITR2_RMP_LPTIM.
            • -
          • Add a new - mechanism in LL_TIM_SetRemap() - API to remap TIM1, TIM9, - and TIM5 input - triggers mapped on LPTIM - register. 
            • -
          -
        -
      -
    • HAL - - - - LPTIM update
      • -
        -
      • Add a polling - mechanism to check - on LPTIM_FLAG_XXOK flags - in different API 
        • -
          -
        • Add  - LPTIM_WaitForFlag() API to - wait for flag set.
          • -
        • Perform new - checks on - HAL_LPTIM_STATE_TIMEOUT.
          • -
        -
      • Add lacking - definitions of LPTIM input - trigger remapping and its - related API
        • -
          -
            -
          • LL_LPTIM_INPUT1_SRC_PAD_AF, - - - - - LL_LPTIM_INPUT1_SRC_PAD_PA4, - - - - LL_LPTIM_INPUT1_SRC_PAD_PB9 - - - - and - LL_LPTIM_INPUT1_SRC_TIM_DAC.
            • -
          • Add a new - API LL_LPTIM_SetInput1Src() - to access to the LPTIM_OR - register and remap the - LPTIM input trigger.
            • -
          -
        -
      • Perform a new - check on indirect EXTI23 line - associated to the LPTIM wake - up timer
        • -
          -
        • Condition - the use of the LPTIM Wake-up - Timer associated EXTI - line configuration's - macros by EXTI_IMR_MR23 - bit in different API - - - - :
          • -
            -
          • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE/DDISABLE_FALLING_EDGE()
            • -
          • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()
            • -
          • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() 
            • -
          • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()
            • -
          • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
            • -
          • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
            • -
          • __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()
            • -
          • __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()
            • -
          • __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() 
            • -
          -
        • Update HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop_IT(), - - - - - HAL_LPTIM_Counter_Start_IT() - - - - - and HAL_LPTIM_Counter_Stop_IT() - - - - - API by adding Enable/Disable - rising edge trigger on - the LPTIM Wake-up Timer - Exti - line.
          • -
        • Add - __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() - in the end of the HAL_LPTIM_IRQHandler() - - - - - API conditioned by - EXTI_IMR_MR23 bit.
          • -
        -
      -
    • HAL - - - - I2C update
      • -
        -
      • Update - HAL_I2C_EV_IRQHandler() - API to fix I2C send break - issue 
        • -
          -
        • Add - additional check on - hi2c->hdmatx, - hdmatx->XferCpltCallback, - hi2c->hdmarx, - hdmarx->XferCpltCallback - in I2C_Master_SB() - API to avoid enabling - DMA request when IT - mode is used.
          • -
        -
      • Update - HAL_I2C_ER_IRQHandler() - API to fix acknowledge failure - issue with I2C memory IT - processes
        • -
          -
        •  Add stop - - - - - condition generation when - NACK occurs.
          • -
        -
      • Update - HAL_I2C_Init() - API to force software reset - before setting new I2C - configuration
        • -
      • Update HAL - I2C processes to report ErrorCode - when wrong I2C start condition - occurs
        • -
          -
        •  Add - new ErrorCode - define: HAL_I2C_WRONG_START
          • -
        •  Set ErrorCode - parameter in I2C handle - to HAL_I2C_WRONG_START
          • -
        -
      • Update I2C_DMAXferCplt(), - - - - - I2C_DMAError() and - I2C_DMAAbort() APIs to fix hardfault - issue when hdmatx - and hdmarx parameters - - - - - in i2c handle aren't - initialized (NULL pointer).
        • -
          -
        • Add - additional check on - hi2c->hdmtx - and hi2c->hdmarx - before resetting DMA - Tx/Rx complete callbacks
          • -
        -
      -
    • HAL - - - - FMPI2C update
      • -
        -
      • Fix HAL - FMPI2C slave interrupt - handling issue with I2C - sequential transfers.
        • -
          -
        • Update - FMPI2C_Slave_ISR_IT() - and FMPI2C_Slave_ISR_DMA() - APIs to check on STOP - condition and handle it - before clearing the ADDR - flag
          • -
        -
      -
    • HAL - - - - NAND update
      • -
        -
      • Update - HAL_NAND_Write_Page_8b(), - - - - HAL_NAND_Write_Page_16b() - and  - HAL_NAND_Write_SpareArea_16b() - to manage correctly the time - out condition.
        • -
      -
    • HAL - - - - SAI update
      • -
        -
      • Optimize SAI_DMATxCplt() - and SAI_DMARxCplt() - - - - - APIs to check on "Mode" - parameter instead of CIRC - bit in the CR register.
        • -
      • Remove unused - SAI_FIFO_SIZE define
        • -
      • Update HAL_SAI_Receive_DMA() - programming sequence to be inline - with reference manual
        • -
      -
    -

    V1.7.6 - - - - / 12-April-2019

    -

    Main Changes

    -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • HAL - - - - I2C update
      • -
        -
      • Fix I2C send - break issue in IT processes
        • -
          -
        • Add - additional check on - hi2c->hdmatx - and hi2c->hdmarx to - - - - - avoid the DMA request - enable when IT mode is used.
          • -
        -
      -
    • HAL - - - - SPI update
      • -
        -
      • Update to - implement Erratasheet: - BSY bit may stay high at the - end of a data transfer in - Slave mode
        • -
      -
    • LL - - - - LPTIM update
      • -
        -
      • Fix - compilation errors with LL_LPTIM_WriteReg() - and LL_LPTIM_ReadReg() - - - - - macros
        • -
      -
    • HAL - - - - SDMMC update
      • -
        -
      • Fix - preprocessing compilation - issue with SDIO - STA STBITERR interrupt
        • -
      -
    • HAL/LL - - - - USB update
      • -
        -
      • Updated USB_WritePacket(), - - - - - USB_ReadPacket() - - - - - APIs to prevent compilation - warning with GCC GNU v8.2.0
        • -
      • Rework USB_EPStartXfer() - API to enable the USB endpoint - before unmasking the TX FiFo - empty interrupt in case DMA is - not used
        • -
      • USB HAL_HCD_Init() - and HAL_PCD_Init() - - - - - APIs updated to avoid enabling - USB DMA feature for OTG FS - instance, USB DMA feature is - available only on OTG HS - Instance
        • -
      • Remove - duplicated line in hal_hcd.c - header file comment section -
        • -
      • Rework USB - HAL driver to use instance PCD_SPEED_xxx, - HCD_SPEED_xx - speeds instead of OTG register - Core speed definition during - the instance initialization
        • -
      • Software - Quality improvement with a fix - of CodeSonar - warning on PCD_Port_IRQHandler() - and  HCD_Port_IRQHandler() - - - - - interrupt handlers
        • -
      -
    -

    V1.7.5 - - - - / 08-February-2019

    -

    Main Changes

    -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • General - - - - updates to fix CodeSonar - compilation warnings
      • -
    • General - - - - updates to fix SW4STM32 - compilation errors under Linux
      • -
    • General - - - - updates to fix the user manual - .chm files
      • -
    • Add - support of HAL callback - registration feature
      • -
    -
      -
    • Add - new HAL - - - - EXTI driver
      • -
    • Add - new HAL - - - - SMBUS driver
      • -
    • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on older HAL versions
      • -
        -
      • Rework of HAL - CRYP driver (compatibility - break)
        • -
          -
        • HAL CRYP - driver has been redesigned - with new API's, to bypass - limitations on data - Encryption/Decryption - management present with - previous HAL CRYP driver - version.
          • -
        • The new HAL - CRYP driver is the - recommended version. It is - located as usual in - Drivers/STM32F4xx_HAL_Driver/Src - and - Drivers/STM32f4xx_HAL_Driver/Inc - folders. It can be enabled - through switch - HAL_CRYP_MODULE_ENABLED in - stm32f4xx_hal_conf.h
          • -
        • The legacy - HAL CRYP driver is no longer - supported.
          • -
        -
      • Add new AutoReloadPreload - field in TIM_Base_InitTypeDef - structure to allow the - possibilities to enable or - disable the TIM Auto Reload - Preload.
        • -
      -
    -
      -
    • HAL/LL - - - - Generic update
      • -
        -
      • Add support - of HAL callback - registration feature
        • -
          -
        • The feature - disabled by default is - available for the following - HAL drivers:
          • -
            -
          • ADC, - CAN, CEC, CRYP, DAC, - DCMI, DFSDM, DMA2D, DSI, - ETH, HASH, HCD, I2C, - FMPI2C, SMBUS,
            - UART, USART, IRDA, - SMARTCARD, LPTIM, LTDC, - MMC, NAND, NOR, - PCCARD, PCD, QSPI, RNG,
            -             RTC, - SAI, SD, SDRAM, SRAM, - SPDIFRX, SPI, I2S, TIM, - and WWDG
            • -
          -
        • The feature - may be enabled individually - per HAL PPP driver - by setting the corresponding - definition USE_HAL_PPP_REGISTER_CALLBACKS - - - - - to 1U in - stm32f4xx_hal_conf.h project - configuration file (template - file - stm32f4xx_hal_conf_template.h - available from  - - - - Drivers/STM32F4xx_HAL_Driver/Inc)
          • -
        • Once enabled - - - - , the user - application may resort to HAL_PPP_RegisterCallback() - - - - - to register specific - callback function(s) and - unregister it(them) with HAL_PPP_UnRegisterCallback().
          • -
        -
      • General - updates to fix MISRA 2012 - compilation errors
        • -
          -
        • Replace HAL_GetUID() - API by HAL_GetUIDw0(), - HAL_GetUIDw1() and - HAL_GetUIDw2()
          • -
        • HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() - macros implementation update
          • -
        • "stdio.h" - include updated with "stddef.h"
          • -
        -
      -
    • HAL - - - - GPIO  - - - - update
      • -
        -
      • Add missing - define for SPI3 alternate - function "GPIO_AF5_SPI3" for - STM32F401VE devices
        • -
      • Remove - "GPIO_AF9_TIM14" from defined - alternate function list for - STM32F401xx devices
        • -
      • HAL_GPIO_TogglePin() reentrancy - robustness improvement
        • -
      • HAL_GPIO_DeInit() API update - to avoid potential pending - interrupt after call
        • -
      • Update - GPIO_GET_INDEX() - API for more compliance with - STM32F412Vx/STM32F412Rx/STM32F412Cx - devices
        • -
      • Update - GPIO_BRR registers with - Reference Manual regarding - registers and bit definition - values
        • -
      -
    • HAL - - - - CRYP update
      • -
        -
      • The CRYP_InitTypeDef - is no more - supported, changed by CRYP_ConfigTypedef - to allow changing parameters - using HAL_CRYP_setConfig() - API without reinitialize the - CRYP IP using the HAL_CRYP_Init() - - - - - API
        • -
      • New - parameters added in the CRYP_ConfigTypeDef - structure: B0 and DataWidthUnit
        • -
      • Input data - size parameter is added in the - CRYP_HandleTypeDef - structure
        • -
      • Add new APIs - to manage the CRYP - configuration:
        • -
          -
        •  HAL_CRYP_SetConfig()
          • -
        • HAL_CRYP_GetConfig()
          • -
        -
      • Add new APIs - to manage the Key derivation:
        • -
          -
        • HAL_CRYPEx_EnableAutoKeyDerivation()
          • -
        • HAL_CRYPEx_DisableAutoKeyDerivation()
          • -
        -
      • Add new APIs - to encrypt and decrypt data:
        • -
          -
        • HAL_CRYP_Encypt()
          • -
        • HAL_CRYP_Decypt()
          • -
        • HAL_CRYP_Encypt_IT()
          • -
        • HAL_CRYP_Decypt_IT()
          • -
        • HAL_CRYP_Encypt_DMA()
          • -
        • HAL_CRYP_Decypt_DMA()
          • -
        -
      • Add new APIs - to generate TAG:
        • -
          -
        • HAL_CRYPEx_AESGCM_GenerateAuthTAG()
          • -
        • HAL_CRYPEx_AESCCM_Generago teAuthTAG()
          • -
        -
      -
    • HAL - - - - LPTIM update
      • -
        -
      • Remove - useless LPTIM Wakeup EXTI - related macros from HAL_LPTIM_TimeOut_Start_IT() - API
        • -
      -
    • HAL - - - - I2C update
      • -
        -
      • I2C API - changes for MISRA-C 2012 - compliancy:
        • -
          -
        • Rename - HAL_I2C_Master_Sequential_Transmit_IT() - to - HAL_I2C_Master_Seq_Transmit_IT()
          • -
        • Rename - HAL_I2C_Master_Sequentiel_Receive_IT() - to - HAL_I2C_Master_Seq_Receive_IT()
          • -
        • Rename - HAL_I2C_Slave_Sequentiel_Transmit_IT() - to - HAL_I2C_Slave_Seq_Transmit_IT() -
          • -
        • Rename - HAL_I2C_Slave_Sequentiel_Receive_DMA() - to - HAL_I2C_Slave_Seq_Receive_DMA()
          • -
        -
      • SMBUS defined - flags are removed as not used - by the HAL I2C driver
        • -
          -
        • I2C_FLAG_SMBALERT
          • -
        • I2C_FLAG_TIMEOUT
          • -
        • I2C_FLAG_PECERR
          • -
        • I2C_FLAG_SMBHOST
          • -
        • I2C_FLAG_SMBDEFAULT
          • -
        -
      • Add support - of I2C repeated start feature - in DMA Mode:
        • -
          -
        • With the - following new API's
          • -
            -
          • HAL_I2C_Master_Seq_Transmit_DMA()
            • -
          • HAL_I2C_Master_Seq_Receive_DMA()
            • -
          • HAL_I2C_Slave_Seq_Transmit_DMA()
            • -
          • HAL_I2C_Slave_Seq_Receive_DMA()
            • -
          -
        -
      • Add new I2C - transfer options to easy - manage the sequential transfers
        • -
          -
        • I2C_FIRST_AND_NEXT_FRAME
          • -
        • I2C_LAST_FRAME_NO_STOP
          • -
        • I2C_OTHER_FRAME
          • -
        • I2C_OTHER_AND_LAST_FRAME
          • -
        -
      -
    • HAL - - - - FMPI2C update
      • -
        -
      • I2C API - changes for MISRA-C 2012 - compliancy:
        • -
          -
        • Rename - HAL_FMPI2C_Master_Sequential_Transmit_IT() - to - HAL_FMPI2C_Master_Seq_Transmit_IT()
          • -
        • Rename - HAL_FMPI2C_Master_Sequentiel_Receive_IT() - to - HAL_FMPI2C_Master_Seq_Receive_IT()
          • -
        • Rename - HAL_FMPI2C_Master_Sequentiel_Transmit_DMA() - to - HAL_FMPI2C_Master_Seq_Transmit_DMA() -
          • -
        • Rename - HAL_FMPI2C_Master_Sequentiel_Receive_DMA() - to - HAL_FMPI2C_Master_Seq_Receive_DMA()
          • -
        -
      • Rename - FMPI2C_CR1_DFN to - FMPI2C_CR1_DNF for more - compliance with Reference - Manual regarding registers and - bit definition naming
        • -
      • Add support - of I2C repeated start feature - in DMA Mode:
        • -
          -
        • With the - following new API's
          • -
            -
          • HAL_FMPI2C_Master_Seq_Transmit_DMA()
            • -
          • HAL_FMPI2C_Master_Seq_Receive_DMA()
            • -
          • HAL_FMPI2C_Slave_Seq_Transmit_DMA()
            • -
          • HAL_FMPI2C_Slave_Seq_Receive_DMA()
            • -
          -
        -
      -
    • HAL - - - - FLASH update
      • -
        -
      • Update the FLASH_OB_GetRDP() - API to return the correct RDP - level
        • -
      -
    • HAL  - RCC - update
      • -
        -
      • Remove GPIOD - CLK macros for STM32F412Cx - devices (X = D)
        • -
      • Remove GPIOE - CLK macros for - STM32F412Rx\412Cx devices: (X - = E)
        • -
      • Remove - GPIOF/G CLK macros for - STM32F412Vx\412Rx\412Cx - devices (X= F or G)
        • -
          -
        • __HAL_RCC_GPIOX_CLK_ENABLE()
          • -
        • __HAL_RCC_GPIOX_CLK_DISABLE()
          • -
        • __HAL_RCC_GPIOX_IS_CLK_ENABLED()
          • -
        • __HAL_RCC_GPIOX_IS_CLK_DISABLED()
          • -
        • __HAL_RCC_GPIOX_FORCE_RESET()
          • -
        -
      -
    • HAL - - - - RNG update
      • -
        -
      • Update to - manage RNG error code:
        • -
          -
        • Add ErrorCode - parameter in HAL RNG Handler - structure
          • -
        -
      -
    • LL - - - - ADC update
      • -
        -
      • Add - __LL_ADC_CALC_TEMPERATURE() - helper macro to calculate the - temperature (unit: degree - Celsius) from ADC conversion - data of internal temperature - sensor.
        • -
      • Fix ADC - channels configuration issues - on STM32F413xx/423xx devices
        • -
          -
        • To allow - possibility to switch - between VBAT and TEMPERATURE - channels configurations
          • -
        -
      • HAL_ADC_Start(), HAL_ADC_Start_IT() - - - - - and HAL_ADC_Start_DMA() - - - - - update to prevention from - starting ADC2 or ADC3 once - multimode is enabled
        • -
      -
    • HAL - - - - DFSDM  - - - - update
      • -
        -
      • General - updates to be compliant with - DFSDM bits naming used in - CMSIS files.
        • -
      -
    • HAL - - - - CAN  - - - - update
      • -
        -
      • Update - possible values list for FilterActivation - parameter in CAN_FilterTypeDef - structure
        • -
          -
        • CAN_FILTER_ENABLE - - - - - instead of ENABLE
          • -
        • CAN_FILTER_DISABLE - - - - - instead of DISABLE
          • -
        -
      -
    • HAL - - - - CEC  - - - - update
      • -
        -
      • Update HAL - CEC State management method:
        • -
          -
        • Remove HAL_CEC_StateTypeDef - structure parameters
          • -
        • Add new - defines for CEC states
          • -
        -
      -
    • HAL - - - - DMA  - - - - update
      • -
        -
      • Add clean of - callbacks in HAL_DMA_DeInit() - API
        • -
      -
    • HAL - - - - DMA2D  - - - - update
      • -
        -
      • Remove unused - DMA2D_ColorTypeDef structure - to be compliant with MISRAC - 2012 Rule 2.3
        • -
      • General - update to use dedicated - defines for - DMA2D_BACKGROUND_LAYER and - DMA2D_FOREGROUND_LAYER instead - of numerical values: 0/1.
        • -
      -
    • HAL - - - - DSI  - - - - update
      • -
        -
      • Fix read - multibyte issue: remove extra - call to __HAL_UNLOCK__ from DSI_ShortWrite() - API.
        • -
      -
    -
      -
    • HAL/LL - - - - RTC update
      • -
    -
      -
        -
      • HAL/ LL drivers - optimization
        • -
          -
        • HAL driver: - remove unused variables
          • -
        • LL driver: - getter APIs optimization
          • -
        -
      -
    • HAL - - - - PWR update
      • -
        -
      • Remove the - followings API's as feature - not supported by - STM32F469xx/479xx devices
        • -
          -
        • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
          • -
        • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
          • -
        -
      -
    • HAL - - - - SPI update
      • -
        -
      • Update HAL_SPI_StateTypeDef - structure to add new state: - HAL_SPI_STATE_ABORT
        • -
      -
    • HAL/LL - - - - TIM update
      • -
        -
      • Add new AutoReloadPreload - field in TIM_Base_InitTypeDef - structure
        • -
          -
        • Refer to - the TIM examples to identify - the changes -
          • -
        -
      • Move the - following TIM structures from - stm32f4xx_hal_tim_ex.h into - stm32f4xx_hal_tim.h
        • -
          -
        • TIM_MasterConfigTypeDef
          • -
        • TIM_BreakDeadTimeConfigTypeDef
          • -
        -
      • Add new TIM - Callbacks API's:
        • -
          -
        • HAL_TIM_PeriodElapsedHalfCpltCallback()
          • -
        • HAL_TIM_IC_CaptureHalfCpltCallback()
          • -
        • HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
          • -
        • HAL_TIM_TriggerHalfCpltCallback()
          • -
        -
      • TIM API - changes for MISRA-C 2012 - compliancy:
        • -
          -
        • Rename HAL_TIM_SlaveConfigSynchronization - to HAL_TIM_SlaveConfigSynchro
          • -
        • Rename HAL_TIM_SlaveConfigSynchronization_IT - to HAL_TIM_SlaveConfigSynchro_IT
          • -
        • Rename HAL_TIMEx_ConfigCommutationEvent - to HAL_TIMEx_ConfigCommutEvent
          • -
        • Rename HAL_TIMEx_ConfigCommutationEvent_IT - to HAL_TIMEx_ConfigCommutEvent_IT
          • -
        • Rename HAL_TIMEx_ConfigCommutationEvent_DMA - to HAL_TIMEx_ConfigCommutEvent_DMA
          • -
        • Rename HAL_TIMEx_CommutationCallback - to HAL_TIMEx_CommutCallback
          • -
        • Rename HAL_TIMEx_DMACommutationCplt - to TIMEx_DMACommutationCplt
          • -
        -
      -
    -
      -
    • HAL/LL - - - - USB update
      • -
        -
      • Rework USB - interrupt handler and improve - HS DMA support in Device mode
        • -
      • Fix BCD - handling fr OTG - instance in device mode
        • -
      • cleanup - reference to low speed in - device mode
        • -
      • allow writing - TX FIFO in case of transfer - length is equal to available - space in the TX FIFO
        • -
      • Fix Toggle - OUT interrupt channel in host - mode
        • -
      • Update USB - OTG max number of endpoints (6 - FS and 9 HS instead of 5 and - 8)
        • -
      • Update USB - OTG IP to enable internal - transceiver when starting USB - device after committee BCD negotiation
        • -
      -
    • LL - - - - IWDG update
      • -
        -
      • Update LL - inline macros to use IWDGx - parameter instead of IWDG - instance defined in CMSIS device
        • -
      -
    -

    V1.7.4 - - - - / 02-February-2018

    -

    Main Changes

    -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • HAL update
      • -
        -
      • Update UNUSED() - macro implementation to avoid - GCC warning
        • -
          -
        • The warning - is detected when the UNUSED() - macro is called from C++ - file
          • -
        -
      • Update to - make RAMFUNC define as generic - type instead of HAL_StatusTypdef - type.
        • -
      -
    • HAL - - - - FLASH update
      • -
        -
      • Update - the prototypes of the - following APIs after change on - RAMFUNC defines 
        • -
          -
        • HAL_FLASHEx_StopFlashInterfaceClk()
          • -
        • HAL_FLASHEx_StartFlashInterfaceClk()
          • -
        • HAL_FLASHEx_EnableFlashSleepMode()
          • -
        • HAL_FLASHEx_DisableFlashSleepMode()
          • -
        -
      -
    • HAL - - - - SAI update
      • -
        -
      • Update HAL_SAI_DMAStop() - and HAL_SAI_Abort() - - - - - process to fix the lock/unlock - audio issue
        • -
      -
    -

    V1.7.3 - - - - / 22-December-2017

    -

    Main Changes

    -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on older HAL versions
      • -
        -
      • Rework of - HAL CAN driver - (compatibility break) 
        • -
          -
        • A new HAL - CAN driver has been - redesigned with new APIs, to - bypass limitations on CAN - Tx/Rx FIFO management - present with previous HAL - CAN driver version.
          • -
        • The new HAL - CAN driver is the - recommended version. It is - located as usual in - Drivers/STM32F4xx_HAL_Driver/Src - and - Drivers/STM32f4xx_HAL_Driver/Inc - folders. It can be enabled - through switch - HAL_CAN_MODULE_ENABLED in - stm32f4xx_hal_conf.h
          • -
        • The legacy - HAL CAN driver is also - present in the release in - Drivers/STM32F4xx_HAL_Driver/Src/Legacy - - - - and - Drivers/STM32F4xx_HAL_Driver/Inc/Legacy - folders for software - compatibility reasons. Its - usage is not recommended as - deprecated. It can - however be enabled through - switch - HAL_CAN_LEGACY_MODULE_ENABLED - in stm32f4xx_hal_conf.h
          • -
        -
      -
    • HAL update
      • -
        -
      • Update HAL - driver to allow user to change - systick - period to 1ms, 10 ms - or 100 ms :
        • -
          -
        • Add the - following API's - - - - :  
          • -
            -
          • HAL_GetTickPrio(): - Returns a tick priority.
            • -
          • HAL_SetTickFreq(): Sets - new tick frequency.
            • -
          • HAL_GetTickFreq(): - Returns tick frequency.
            • -
          -
        • Add HAL_TickFreqTypeDef - enumeration for the - different Tick Frequencies: - 10 Hz, 100 Hz and 1KHz - (default).
          • -
        -
      -
    • HAL - - - - CAN update
      • -
        -
      • Fields of CAN_InitTypeDef - structure are reworked:
        • -
          -
        • SJW to SyncJumpWidth, - BS1 to TimeSeg1, BS2 to - TimeSeg2, TTCM to TimeTriggeredMode, - ABOM to AutoBusOff, - AWUM to AutoWakeUp, - NART to AutoRetransmission - (inversed), RFLM to ReceiveFifoLocked - and TXFP to TransmitFifoPriority
          • -
        -
      • HAL_CAN_Init() is split - into both HAL_CAN_Init() - - - - - and HAL_CAN_Start() - - - - - API's
        • -
      • HAL_CAN_Transmit() is replaced - by HAL_CAN_AddTxMessage() - - - - - to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() - - - - - for polling until completion.
        • -
      • HAL_CAN_Transmit_IT() is replaced - by HAL_CAN_ActivateNotification() - - - - - to enable transmit IT, then HAL_CAN_AddTxMessage() - - - - - for place Tx request.
        • -
      • HAL_CAN_Receive() is replaced - by HAL_CAN_GetRxFifoFillLevel() - - - - - for polling until reception, - then HAL_CAN_GetRxMessage() - - - - -
        - to get Rx message.
        • -
      • HAL_CAN_Receive_IT() is replaced - by HAL_CAN_ActivateNotification() to - - - - - enable receive IT, then HAL_CAN_GetRxMessage()
        - in the receivecallback - to get Rx message
        • -
      • HAL_CAN_Slepp() is renamed - as HAL_CAN_RequestSleep()
        • -
      • HAL_CAN_TxCpltCallback() is split - into - HAL_CAN_TxMailbox0CompleteCallback(), -HAL_CAN_TxMailbox1CompleteCallback() -and HAL_CAN_TxMailbox2CompleteCallback().
        • -
      • HAL_CAN_RxCpltCallback is split - into HAL_CAN_RxFifo0MsgPendingCallback() - and - HAL_CAN_RxFifo1MsgPendingCallback().
        • -
      • More complete - "How to use the new driver" is - detailed in the driver header - section itself.
        • -
      -
    • HAL - - - - FMPI2C update
      • -
        -
      • Add new - option - FMPI2C_LAST_FRAME_NO_STOP for - the sequential transfer management
        • -
          -
        • This option - allows to manage a restart - condition after several call - of the same master - sequential interface. 
          • -
        -
      -
    • HAL - - - - RCC update
      • -
        -
      • Add new HAL macros
        • -
          -
        • __HAL_RCC_GET_RTC_SOURCE() - allowing to get the RTC - clock source
          • -
        • __HAL_RCC_GET_RTC_HSE_PRESCALER() - allowing to get the HSE - clock divider for RTC - peripheral
          • -
        -
      • Ensure reset - of CIR and CSR registers when - issuing HAL_RCC_DeInit()/LL_RCC_DeInit - functions
        • -
      • Update HAL_RCC_OscConfig() to - - - - - keep backup domain enabled - when configuring - respectively LSE and RTC - clock source
        • -
      • Add new HAL - interfaces allowing to control - the activation or deactivation - of PLLI2S and PLLSAI:
        • -
          -
        • HAL_RCCEx_EnablePLLI2S()
          • -
        • HAL_RCCEx_DisablePLLI2S()
          • -
        • HAL_RCCEx_EnablePLLSAI()
          • -
        • HAL_RCCEx_DisablePLLSAI()
          • -
        -
      -
    -
      -
    • LL - - - - RCC update 
      • -
        -
      • Add new LL - RCC macro
        • -
          -
        • LL_RCC_PLL_SetMainSource() allowing - to configure PLL main clock - source
          • -
        -
      -
    • LL - - - - FMC / LL FSMC update
      • -
        -
      • Add clear of - the PTYP bit to select the - PCARD mode in FMC_PCCARD_Init() - / FSMC_PCCARD_Init()
        • -
      -
    -

    V1.7.2 - - - - / 06-October-2017

    -

    Main Changes

    -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • Fix - compilation warning with - GCC compiler
      • -
    • Remove - - - - Date and version - from header files
      • -
    • Update - - - - HAL drivers to refer to the - new CMSIS bit position - defines instead of usage the - POSITION_VAL() - macro
      • -
    • HAL - - - - Generic update
      • -
        -
      • stm32f4xx_hal_def.h - - - - file changes: 
        • -
          -
        • Update - __weak and __packed defined - values for ARM compiler
          • -
        • Update - __ALIGN_BEGIN and - __ALIGN_END defined values - for ARM compiler
          • -
        -
      • stm32f4xx_ll_system.h - - - - - file: - add LL_SYSCFG_REMAP_SDRAM - define
        • -
      -
    • HAL - - - - ADC update
      • -
        -
      • Fix wrong - definition of ADC channel - temperature sensor for - STM32F413xx and STM32F423xx - devices.
        • -
      -
    • HAL - - - - DMA update
      • -
        -
      • Update values - - - - for the following defines: - DMA_FLAG_FEIF0_4 and - DMA_FLAG_DMEIF0_4 
        • -
      -
    • HAL - - - - DSI update
      • -
        -
      • Fix Extra - warning with SW4STM32 compiler
        • -
      • Fix DSI - display issue when using EWARM - w/ high level optimization 
        • -
      • Fix - MISRAC errors
        • -
      -
    • HAL - - - - FLASH update
      • -
        -
      • HAL_FLASH_Unlock() update to - return state error when the - FLASH is already unlocked
        • -
      -
    • HAL - - - - FMPI2C update
      • -
        -
      • Update - Interface APIs headers to - remove confusing message about - device address
        • -
      • Update - FMPI2C_WaitOnRXNEFlagUntilTimeout() - to resolve a race condition - between STOPF and RXNE Flags
        • -
      • Update - FMPI2C_TransferConfig() - to fix wrong bit management.
        • -
      • Update code - comments to use DMA stream - instead of DMA channel
        • -
      -
    -
      -
    • HAL - - - - PWR update
      • -
        -
      • HAL_PWR_EnableWakeUpPin() update - description to add support of - PWR_WAKEUP_PIN2 and - PWR_WAKEUP_PIN3
        • -
      -
    • HAL - - - - NOR update
      • -
        -
      • Add the - support of STM32F412Rx devices
        • -
      -
    • HAL - - - - I2C update
      • -
        -
      • Update - Interface APIs headers to - remove confusing mesage - about device address
        • -
      • Update - I2C_MasterReceive_RXNE() - and I2C_MasterReceive_BTF() - static APIs to fix bad - Handling of NACK in I2C master - receive process.
        • -
      -
    -
      -
    • HAL - - - - RCC update
      • -
        -
      • Update HAL_RCC_GetOscConfig() - API to:
        • -
          -
        • set PLLR in - the RCC_OscInitStruct
          • -
        • check on - null pointer
          • -
        -
      • Update HAL_RCC_ClockConfig() - API to:
        • -
          -
        • check on - null pointer
          • -
        • optimize code - - - - size by updating the - handling method of the SWS bits
          • -
        • update to use  - - - - - __HAL_FLASH_GET_LATENCY() - - - - flash macro instead of using - direct register access - to LATENCY bits in - FLASH ACR register.
          • -
        -
      • Update HAL_RCC_DeInit() -  and LL_RCC_DeInit() - - - - - APIs to
        • -
          -
        • Be able to - return HAL/LL status
          • -
        • Add checks - for HSI, PLL and PLLI2S -  ready - before modifying RCC CFGR - registers
          • -
        • Clear all - interrupt falgs
          • -
        • Initialize - systick - interrupt period
          • -
        -
      • Update HAL_RCC_GetSysClockFreq() - to avoid risk of rounding - error which may leads to a - wrong returned value. 
        • -
      -
    -

     

    -

     

    -
      -
    • HAL - - - - RNG update
      • -
        -
      • HAL_RNG_Init() remove - Lock()/Unlock()
        • -
      -
    • HAL - - - - MMC update
      • -
        -
      • HAL_MMC_Erase() - API: add missing () to - fix compilation warning - detected with SW4STM32 when - extra feature is enabled.
        • -
      -
    • HAL - - - - RTC update
      • -
        -
      • HAL_RTC_Init() API: update - to force the wait for synchro - before setting TAFCR register - when BYPSHAD bit in CR - register is 0.
        • -
      -
    • HAL - - - - SAI update
      • -
        -
      • Update HAL_SAI_DMAStop() - API to flush fifo - after disabling SAI
        • -
      -
    • HAL - - - - I2S update
      • -
        -
      • Update I2S - DMA fullduplex process to - handle I2S Rx and Tx DMA Half - transfer complete callback
        • -
      -
    • HAL - - - - TIM update
      • -
        -
      • Update HAL_TIMEx_OCN_xxxx() - and HAL_TIMEx_PWMN_xxx() - - - - - API description to remove - support of TIM_CHANNEL_4
        • -
      -
    • LL - - - - DMA update
      • -
        -
      • Update to - clear DMA flags using WRITE_REG() - instead SET_REG() API to avoid - read access to the IFCR - register that is write only.
        • -
      -
    • LL - - - - RTC update
      • -
        -
      • Fix warning - with static analyzer
        • -
      -
    • LL - - - - USART update
      • -
        -
      • Add assert - macros to check USART BaudRate - register
        • -
      -
    • LL - - - - I2C update
      • -
        -
      • Rename - IS_I2C_CLOCK_SPEED() - and IS_I2C_DUTY_CYCLE() - respectively to - IS_LL_I2C_CLOCK_SPEED() and - IS_LL_I2C_DUTY_CYCLE() to - avoid incompatible macros - redefinition.
        • -
      -
    • LL - - - - TIM update
      • -
        -
      • Update LL_TIM_EnableUpdateEvent() - API to clear UDIS bit in TIM - CR1 register instead of - setting it.
        • -
      • Update LL_TIM_DisableUpdateEvent() - API to set UDIS bit in TIM CR1 - register instead of clearing - it.
        • -
      -
    • LL - - - - USART update
      • -
        -
      • Fix MISRA - error w/ IS_LL_USART_BRR() - macro
        • -
      • Fix wrong - check when UART10 instance is - used
        • -
      -
    -

    V1.7.1 - - - - / 14-April-2017

    -

    Main Changes

    -
      -
    • Update - - - - CHM UserManuals - to support LL drivers
      • -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • HAL - - - - CAN update
      • -
        -
      • Add - management of overrun - error. 
        • -
      • Allow - possibility to receive - messages from the 2 RX FIFOs - in parallel via interrupt.
        • -
      • Fix message - - - - lost issue with specific - sequence of transmit requests.
        • -
      • Handle - transmission failure with - error callback, when NART is - enabled.
        • -
      • Add - __HAL_CAN_CANCEL_TRANSMIT() - call to abort transmission - when timeout is reached
        • -
      -
    -
      -
    • HAL - - - - PWR update
      • -
        -
      • HAL_PWREx_EnterUnderDriveSTOPMode() API: remove - check on UDRDY flag
        • -
      -
    -
      -
    • LL - - - - ADC update
      • -
        -
      • Fix wrong ADC - group injected sequence configuration
        • -
          -
        • LL_ADC_INJ_SetSequencerRanks() and LL_ADC_INJ_GetSequencerRanks() - - - - - API's update to take in - consideration the ADC number - of conversions
          • -
        • Update - the defined values for - ADC group injected seqencer - ranks 
          • -
        -
      -
    -

    V1.7.0 - - - - / 17-February-2017

    -

    Main Changes

    -
      -
    • Add - - - - Low Layer drivers allowing - performance and footprint optimization
      • -
        -
      • Low Layer drivers - APIs provide register level - programming: require deep - knowledge of peripherals - described in STM32F4xx - Reference Manuals
        • -
      • Low Layer - drivers are available for: - ADC, Cortex, CRC, DAC, - DMA, DMA2D, EXTI, GPIO, I2C, - IWDG, LPTIM, PWR, RCC, RNG, - RTC, SPI, TIM, USART, WWDG - peripherals and additionnal - Low Level Bus, System and - Utilities APIs.
        • -
      • Low Layer drivers - APIs are implemented as static - inline function in new Inc/stm32f4xx_ll_ppp.h files - - - - - for PPP peripherals, there is - no configuration file and each stm32f4xx_ll_ppp.h file - - - - - must be included in user code.
        • -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • Fix extra - - - - warnings with GCC compiler
      • -
    • HAL - drivers clean up: remove - double casting 'uint32_t' and 'U'
      • -
    • Add - new HAL - - - - MMC driver
      • -
    • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on older HAL versions
      • -
        -
      • HAL SD update
        • -
          -
        • Overall - rework of the driver for a - more - efficient implementation
          • -
            -
          • Modify - initialization API and structures
            • -
          • Modify - Read / Write sequences: - separate transfer process - and SD Cards state management 
            • -
          • Adding - interrupt mode for Read / - Write operations
            • -
          • Update - the HAL_SD_IRQHandler - function by optimizing the - management of interrupt errors
            • -
          -
        • Refer to - the following example to - identify the changes: BSP - example and USB_Device/MSC_Standalone - application
          • -
        -
      • HAL NAND update
        • -
          -
        • Modify NAND_AddressTypeDef, - NAND_DeviceConfigTypeDef - and NAND_HandleTypeDef - structures fields
          • -
        • Add new HAL_NAND_ConfigDevice - API
          • -
        -
      • HAL DFSDM update
        • -
          -
        • Add - support of Multichannel - Delay feature
          • -
            -
          • Add HAL_DFSDM_ConfigMultiChannelDelay - API
            • -
          • The - following APIs are moved - to internal static - functions: HAL_DFSDM_ClockIn_SourceSelection, - HAL_DFSDM_ClockOut_SourceSelection, - HAL_DFSDM_DataInX_SourceSelection - (X=0,2,4,6), HAL_DFSDM_BitStreamClkDistribution_Config
            • -
          -
        -
      • HAL I2S update
        • -
          -
        • Add specific - - - - - callback API to manage I2S - full duplex end of transfer - process:
          • -
            -
          • HAL_I2S_TxCpltCallback() - and - HAL_I2S_RxCpltCallback() - API's will be replaced - with only - HAL_I2SEx_TxRxCpltCallback() - API. 
            • -
          -
        -
      -
    • HAL - - - - update
      • -
        -
      • Modifiy default HAL_Delay - implementation to guarantee - minimum delay 
        • -
      -
    • HAL - - - - Cortex update
      • -
        -
      • Move HAL_MPU_Disable() - and HAL_MPU_Enable() - - - - - from stm32f4xx_hal_cortex.h to - stm32f4xx_hal_cortex.c
        • -
      • Clear the - whole MPU control register - in HAL_MPU_Disable() - API
        • -
      -
    • HAL - - - - FLASH update
      • -
        -
      • IS_FLASH_ADDRESS() - macro update to support OTP - range
        • -
      • FLASH_Program_DoubleWord(): Replace - 64-bit accesses with 2 - double-words operations
        • -
      -
    • LL - - - - GPIO update
      • -
        -
      • Update - IS_GPIO_PIN() - macro implementation to be - more safe
        • -
      -
    • LL - - - - RCC update
      • -
        -
      • Update - IS_RCC_PLLQ_VALUE() - macro implementation: the - minimum accepted value is - 2 instead of 4
        • -
      • Rename - RCC_LPTIM1CLKSOURCE_PCLK - define to - RCC_LPTIM1CLKSOURCE_PCLK1
        • -
      • Fix - compilation issue w/ - __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() - and - __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() - macros for STM32F401xx devices
        • -
      • Add the - following is clock - enabled macros for STM32F401xx - devices
        • -
          -
        •  __HAL_RCC_SDIO_IS_CLK_ENABLED()
          • -
        • __HAL_RCC_SPI4_IS_CLK_ENABLED()
          • -
        • __HAL_RCC_TIM10_IS_CLK_ENABLED()
          • -
        -
      • Add the - following is clock - enabled macros for STM32F410xx - devices
        • -
          -
        •  __HAL_RCC_CRC_IS_CLK_ENABLED()
          • -
        • __HAL_RCC_RNG_IS_CLK_ENABLED()
          • -
        -
      • Update HAL_RCC_DeInit() - to reset the RCC clock - configuration to the default - reset state.
        • -
      • Remove macros - to configure BKPSRAM from - STM32F401xx devices 
        • -
      • Update to - refer to AHBPrescTable[] - and APBPrescTable[] - - - - - tables defined in - system_stm32f4xx.c file - instead of APBAHBPrescTable[] - - - - - table.
        • -
      -
    • HAL - - - - FMPI2C update
      • -
        -
      • Add - FMPI2C_FIRST_AND_NEXT_FRAME - define in Sequential - Transfer Options
        • -
      -
    • HAL - - - - ADC update
      • -
        -
      • HAL_ADCEx_InjectedConfigChannel(): update the - external trigger injected - condition
        • -
      -
    • HAL - - - - DMA update
      • -
        -
      • HAL_DMA_Init(): update to - check compatibility between - FIFO threshold level and size - of the memory burst 
        • -
      -
    • HAL - - - - QSPI update
      • -
        -
      • QSPI_HandleTypeDef structure: - Update transfer parameters on - uint32_t instead of uint16_t
        • -
      -
    • HAL - - - - UART/USART/IrDA/SMARTCARD update
      • -
        -
      • DMA Receive - process; the code has been - updated to clear the USART - OVR flag before - enabling DMA receive - request.
        • -
      • UART_SetConfig() update to - manage correctly USART6 - instance that is not available - on STM32F410Tx devices
        • -
      -
    • HAL - - - - CAN update
      • -
        -
      • Remove Lock - mechanism from HAL_CAN_Transmit_IT() - and HAL_CAN_Receive_IT() - - - - - processes
        • -
      -
    • HAL - - - - TIM update
      • -
        -
      • Add - __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() - macro to disable Master output - without check on TIM channel - state. 
        • -
      • Update HAL_TIMEx_ConfigBreakDeadTime() - to fix TIM BDTR register - corruption.
        • -
      -
    • HAL - - - - I2C update
      • -
        -
      • Update - HAL_I2C_Master_Transmit() - and HAL_I2C_Slave_Transmit() - to avoid sending extra - bytes at the end of the - transmit processes
        • -
      • Update - HAL_I2C_Mem_Read() - API to fix wrong check on - misused parameter “Size”
        • -
      • Update - I2C_MasterReceive_RXNE() - and I2C_MasterReceive_BTF() - static APIs to enhance Master - sequential reception process.
        • -
      -
    • HAL - - - - SPI update
      • -
        -
      • Add transfer - abort APIs and associated - callbacks in interrupt mode
        • -
          -
        • HAL_SPI_Abort()
          • -
        • HAL_SPI_Abort_IT()
          • -
        • HAL_SPI_AbortCpltCallback()
          • -
        -
      -
    • HAL - - - - I2S update
      • -
        -
      • Add specific - - - - - callback API to manage I2S - full duplex end of transfer - process:
        • -
          -
        • HAL_I2S_TxCpltCallback() - and HAL_I2S_RxCpltCallback() - API's will be replaced with - only - HAL_I2SEx_TxRxCpltCallback() - API. 
          • -
        -
      • Update I2S - Transmit/Receive polling - process to manage Overrun - and Underrun errors
        • -
      • Move - the I2S clock input - frequency calculation to - HAL RCC driver.
        • -
      • Update the - HAL I2SEx driver to keep only - full duplex feature.
        • -
      • HAL_I2S_Init() - API updated to
        • -
          -
        • Fix wrong - I2S clock calculation when - PCM mode is used.
          • -
        • Return - state HAL_I2S_ERROR_PRESCALER when - the I2S clock is wrongly configured
          • -
        -
      -
    -
      -
    • HAL - - - - LTDC update
      • -
        -
      • Optimize HAL_LTDC_IRQHandler() - function by using direct - register read
        • -
      • Rename the - following API's
        • -
          -
        • HAL_LTDC_Relaod() by HAL_LTDC_Reload() 
          • -
        • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
          • -
        • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
          • -
        -
      • Add new - defines for LTDC layers - (LTDC_LAYER_1 / LTDC_LAYER_2)
        • -
      • Remove unused - asserts
        • -
      -
    • HAL - - - - USB PCD - update
      • -
        -
      • Flush all TX - FIFOs on USB Reset
        • -
      • Remove Lock - mechanism from HAL_PCD_EP_Transmit() - and HAL_PCD_EP_Receive() - - - - - API's
        • -
      -
    -
      -
    • LL - - - - USB update
      • -
        -
      • Enable DMA - Burst mode for USB OTG HS
        • -
      • Fix SD card - detection issue
        • -
      -
    • LL - - - - SDMMC update
      • -
        -
      • Add new SDMMC_CmdSDEraseStartAdd, - SDMMC_CmdSDEraseEndAdd, - SDMMC_CmdOpCondition - and SDMMC_CmdSwitch - functions
        • -
      -
    -

    V1.6.0 - - - - / 04-November-2016

    -

    Main Changes

    -
      -
    • Add support of STM32F413xx - and STM32F423xx - devices
      • -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • HAL - - - - CAN update
      • -
        -
      • Update to add - the support of 3 CAN management
        • -
      -
    • HAL - - - - CRYP update
      • -
        -
      • Update to add - the support of AES features
        • -
      -
    • HAL - - - - DFSDM update
      • -
        -
      • Add - definitions for new external - trigger filters
        • -
      • Add - definition for new Channels - 4, 5, 6 and 7
        • -
      • Add - functions and API for Filter - state configuration and management
        • -
      • Add new - functions: 
        • -
          -
        • HAL_DFSDM_BitstreamClock_Start()
          • -
        • HAL_DFSDM_BitstreamClock_Stop()
          • -
        • HAL_DFSDM_BitStreamClkDistribution_Config() 
          • -
        -
      -
    • HAL - - - - DMA
      • -
        -
      • Add the - support of DMA Channels from - 8 to 15
        • -
      • Update HAL_DMA_DeInit() - function with the check on - DMA stream instance
        • -
      -
    • HAL - - - - DSI update
      • -
    -
      -
        -
      • Update HAL_DSI_ConfigHostTimeouts() - and HAL_DSI_Init() - - - - - functions to avoid scratch in - DSI_CCR register
        • -
      -
    • HAL - - - - FLASH update
      • -
        -
      • Enhance FLASH_WaitForLastOperation() - function implementation
        • -
      • Update - __HAL_FLASH_GET_FLAG() - macro implementation
        • -
      -
    • HAL - - - - GPIO update
      • -
        -
      • Add - specific alternate functions - definitions
        • -
      -
    • HAL - - - - I2C update
      • -
        -
      • Update I2C_DMAError() - function implementation to - ignore DMA FIFO error
        • -
      -
    • HAL - - - - I2S update
      • -
        -
      • Enhance - HAL_I2S_Init() - implementation to test on - PCM_SHORT and PCM_LONG - standards
        • -
      -
    • HAL - - - - IRDA update
      • -
        -
      • Add new - functions and call backs for - Transfer Abort
        • -
          -
        • HAL_IRDA_Abort()
          • -
        • HAL_IRDA_AbortTransmit()
          • -
        • HAL_IRDA_AbortReceive()
          • -
        • HAL_IRDA_Abort_IT()
          • -
        • HAL_IRDA_AbortTransmit_IT()
          • -
        • HAL_IRDA_AbortReceive_IT()
          • -
        • HAL_IRDA_AbortCpltCallback()
          • -
        • HAL_IRDA_AbortTransmitCpltCallback()
          • -
        -
      -
    -
      -
        -
          -
        • HAL_IRDA_AbortReceiveCpltCallback()
          • -
        -
      -
    • HAL - - - - PCD update
      • -
    -
      -
        -
      • Update HAL_PCD_GetRxCount() -  function implementation
        • -
      -
    • HAL - - - - RCC update
      • -
        -
      • Update - __HAL_RCC_HSE_CONFIG() - macro implementation
        • -
      • Update __HAL_RCC_LSE_CONFIG() - macro implementation
        • -
      -
    • HAL - - - - SMARTCARD update
      • -
    -
      -
        -
      • Add new - functions and call backs for - Transfer Abort
        • -
          -
        • HAL_ SMARTCARD_Abort()
          • -
        • HAL_ SMARTCARD_AbortTransmit()
          • -
        • HAL_ SMARTCARD_AbortReceive()
          • -
        • HAL_ SMARTCARD_Abort_IT()
          • -
        • HAL_ SMARTCARD_AbortTransmit_IT()
          • -
        • HAL_ SMARTCARD_AbortReceive_IT()
          • -
        • HAL_ SMARTCARD_AbortCpltCallback()
          • -
        • HAL_ SMARTCARD_AbortTransmitCpltCallback()
          • -
        • HAL_ SMARTCARD_AbortReceiveCpltCallback()
          • -
        -
      -
    • HAL - - - - TIM update
      • -
        -
      • Update HAL_TIMEx_RemapConfig() - function to manage TIM - internal trigger remap: - LPTIM or TIM3_TRGO
        • -
      -
    • HAL - - - - UART update
      • -
        -
      • Add - Transfer abort functions and - callbacks
        • -
      -
    • HAL - - - - USART update
      • -
        -
      • Add - Transfer abort functions and - callbacks
        • -
      -
    -

    V1.5.2 - - - - / 22-September-2016

    -

    Main Changes

    -
      -
    • HAL - - - - I2C update
      • -
        -
      • Fix wrong - behavior in consecutive - transfers in case of single - byte transmission - (Master/Memory Receive
        - interfaces)
        • -
      • Update - HAL_I2C_Master_Transmit_DMA() - / - HAL_I2C_Master_Receive_DMA()/ - HAL_I2C_Slave_Transmit_DMA()
        - and - HAL_I2C_Slave_Receive_DMA() to - manage addressing phase - through interruption instead - of polling
        • -
      • Add - a check on I2C handle - state at start of all I2C - API's to ensure that I2C is ready
        • -
      • Update I2C - API's (Polling, IT and DMA - interfaces) to manage I2C XferSize - and XferCount - handle parameters instead of - API size parameter to help - user to get information of - counter in case of - error. 
        • -
      • Update Abort - functionality to manage DMA - use case
        • -
      -
    • HAL - - - - FMPI2C update
      • -
        -
      • Update to - disable Own Address - before setting the new Own - Address - configuration:
        • -
          -
        • Update - HAL_FMPI2C_Init() - to disable FMPI2C_OARx_EN - bit before any - configuration in OARx - registers
          • -
        -
      -
    • HAL - - - - CAN update
      • -
        -
      • Update CAN - receive processes to set CAN - RxMsg - FIFONumber - parameter
        • -
      -
    • HAL - - - - UART update
      • -
        -
      • Update UART - - - - handle TxXferCount - and RxXferCount parameters - - - - - as volatile to avoid - eventual issue with High Speed - optimization  
        • -
      -
    -

    V1.5.1 - - - - / 01-July-2016

    -

    Main Changes

    -
      -
    • HAL - - - - GPIO update
      • -
        -
      • HAL_GPIO_Init()/HAL_GPIO_DeInit() - API's: - update GPIO_GET_INDEX() - macro implementation to - support all GPIO's
        • -
      -
    • HAL - - - - SPI update
      • -
        -
      • Fix - regression issue: - retore HAL_SPI_DMAPause() - and HAL_SPI_DMAResume() API's -
        • -
      -
    • HAL - - - - RCC update
      • -
        -
      • Fix FSMC - macros compilation warnings - with STM32F412Rx devices
        • -
      -
    • HAL - - - - DMA update
      • -
        -
      • HAL_DMA_PollFortransfer() API clean - up
        -
        -
        • -
      -
    • HAL - - - - PPP update(PPP refers to - IRDA, UART, USART and SMARTCARD)
      • -
        -
      • Update - - - - HAL_PPP_IRQHandler() - to add a check on interrupt - source before managing the - error 
        • -
      -
    -
      -
    • HAL - - - - QSPI update
      • -
        -
      • Implement - workaround to fix the - limitation pronounced - - - - in - the Errata - sheet 2.1.8 section: - In some specific cases, - DMA2 data corruption - occurs when managing AHB - and APB2 peripherals in a - concurrent way
        • -
      -
    -

    V1.5.0 - - - - / 06-May-2016

    -

    Main Changes

    -
      -
    • Add support of STM32F412cx, - - - - - STM32F412rx, STM32F412vx and - STM32F412zx devices
      • -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • Add - new HAL driver for DFSDM peripheral
      • -
    • Enhance - - - - HAL delay and time base - implementation:
      • -
        -
      • Add new - drivers - stm32f4xx_hal_timebase_rtc_alarm_template.c - and - stm32f4xx_hal_timebase_rtc_wakeup_template.c - which override the native HAL - time base functions (defined - as weak) to either use the RTC - as time base tick source. For - more details about the usage - of these drivers, please refer - to HAL\HAL_TimeBase_RTC - examples and - - - - - FreeRTOS-based - - - - - applications
        • -
      -
    • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on HAL V1.4.4
      • -
        -
      • HAL UART, - USART, IRDA, SMARTCARD, SPI, - I2C,FMPI2C, - - - - - QSPI (referenced - as PPP here - - - - - below) drivers
        • -
          -
        • Add PPP - error management during DMA - process. This requires the - following updates - on user application:
          • -
            -
          • Configure - and enable the PPP IRQ in - HAL_PPP_MspInit() - function
            • -
          • In stm32f4xx_it.c - - - - - file, PPP_IRQHandler() - function: add - - - - - a call to HAL_PPP_IRQHandler() - - - - - function
            • -
          • Add and - customize the Error - Callback API: HAL_PPP_ErrorCallback()
            • -
          -
        -
      • HAL I2C, FMPI2C (referenced - as PPP here - - - - - below) drivers:
        • -
          -
        • Update to - avoid waiting on STOPF/BTF/AF - - - - - flag under DMA ISR by using - the PPP - - - - end of transfer interrupt in - the DMA transfer process. This - - - - - requires the following - updates on user - application:
          • -
            -
          • Configure - and enable the PPP IRQ in - HAL_PPP_MspInit() - function
            • -
          • In stm32f4xx_it.c - - - - - file, PPP_IRQHandler() - function: add - - - - - a call to HAL_PPP_IRQHandler() - - - - - function
            • -
          -
        -
      • HAL I2C driver:
        • -
          -
        • I2C - transfer processes IT - update: NACK during - addressing phase is managed - through I2C Error - interrupt instead of - HAL state
          • -
        -
      -
    -
      -
        -
      • HAL IWDG driver: - rework overall driver for - better implementation
        • -
          -
        • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() - - - - - and HAL_IWDG_GetState() APIs
          • -
        -
      • HAL WWDG driver: - rework overall driver for - better implementation
        • -
          -
        • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() - - - - - and HAL_WWDG_GetState() - - - - - APIs 
          • -
        • Update - the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, - uint32_t counter) -  function and API -  by removing the -  "counter" parameter
          • -
        -
      • HAL QSPI - driver:  Enhance - the DMA transmit process - by using PPP TC - interrupt instead of waiting - on TC flag under DMA - ISR. This requires the - following updates on user - application:
        • -
          -
        • Configure - and enable the QSPI IRQ - in HAL_QSPI_MspInit() - function
          • -
        • In stm32f4xx_it.c - - - - - file, QSPI_IRQHandler() - function: add - - - - a call to HAL_QSPI_IRQHandler() - - - - - function
          • -
        -
      • HAL CEC - driver:  Overall - driver rework with - compatibility break versus - previous HAL version
        • -
          -
        • Remove HAL - CEC polling Process - functions: HAL_CEC_Transmit() - and HAL_CEC_Receive()
          • -
        • Remove HAL - CEC receive interrupt - process function HAL_CEC_Receive_IT() - and enable the "receive" -  mode during the Init - phase
          • -
        • Rename HAL_CEC_GetReceivedFrameSize() - funtion - to HAL_CEC_GetLastReceivedFrameSize()
          • -
        • Add new HAL - APIs: HAL_CEC_SetDeviceAddress() - and HAL_CEC_ChangeRxBuffer()
          • -
        • Remove - the 'InitiatorAddress' - field from the CEC_InitTypeDef - structure and manage - it as a parameter in - the HAL_CEC_Transmit_IT() - function
          • -
        • Add new - parameter 'RxFrameSize' - in HAL_CEC_RxCpltCallback() - function
          • -
        • Move CEC Rx - buffer pointer from CEC_HandleTypeDef - structure to CEC_InitTypeDef - structure
          • -
        -
      -
    -
      -
    • HAL - - - - RCC update
      • -
        -
      • Update HAL_RCC_ClockConfig() - function to adjust the SystemCoreClock
        • -
      • Rename macros - and Literals:
        • -
          -
        • RCC_PERIPHCLK_CK48 by RCC_PERIPHCLK_CLK48
          • -
        • IS_RCC_CK48CLKSOURCE by - - - - - IS_RCC_CLK48CLKSOURCE
          • -
        • RCC_CK48CLKSOURCE_PLLSAIP - - - - - by RCC_CLK48CLKSOURCE_PLLSAIP
          • -
        • RCC_SDIOCLKSOURCE_CK48 - - - - by RCC_SDIOCLKSOURCE_CLK48
          • -
        • RCC_CK48CLKSOURCE_PLLQ - - - - - by RCC_CLK48CLKSOURCE_PLLQ
          • -
        -
      • Update HAL_RCCEx_GetPeriphCLKConfig() - and HAL_RCCEx_PeriphCLKConfig() - - - - - functions to support TIM Prescaler - for STM32F411xx devices
        • -
      • HAL_RCCEx_PeriphCLKConfig() API: update - to fix the RTC clock - configuration issue
        • -
      -
    • HAL - - - - CEC update
      • -
        -
      • Overall - driver rework with break - of compatibility with HAL - V1.4.4
        • -
          -
        • Remove the - HAL CEC polling Process: HAL_CEC_Transmit() - and HAL_CEC_Receive()
          • -
        -
      -
    -
      -
        -
          -
        • Remove the - HAL CEC receive interrupt - process (HAL_CEC_Receive_IT()) - - - - - and manage the "Receive" - mode enable within the Init - phase
          • -
        • Rename HAL_CEC_GetReceivedFrameSize() - function to HAL_CEC_GetLastReceivedFrameSize() - - - - - function
          • -
        • Add new HAL - APIs: HAL_CEC_SetDeviceAddress() - and HAL_CEC_ChangeRxBuffer()
          • -
        • Remove - the 'InitiatorAddress' - field from the CEC_InitTypeDef - structure and manage - it as a parameter in - the HAL_CEC_Transmit_IT() - function
          • -
        • Add new - parameter 'RxFrameSize' - in HAL_CEC_RxCpltCallback() - function
          • -
        • Move CEC Rx - buffer pointer from CEC_HandleTypeDef - structure to CEC_InitTypeDef - structure
          • -
        -
      • Update driver - to implement the new CEC state - machine:
        • -
          -
        • Add - new "rxState" field - - - - - in CEC_HandleTypeDef - structure to provide the CEC state - - - - - information related to Rx Operations
          • -
        • Rename - "state" field in CEC_HandleTypeDef - structure to "gstate": - - - - CEC state - - - - - information related to - global Handle management and - Tx Operations
          • -
        • Update CEC - process to manage the new - CEC states.
          • -
        • Update - __HAL_CEC_RESET_HANDLE_STATE() - macro to handle the new CEC - state parameters (gState, - rxState)
          • -
        -
      -
    -
      -
    • HAL - - - - UART, USART, SMARTCARD and - IRDA (referenced - - - - as PPP here below) update
      • -
        -
      • Update - Polling management:
        • -
          -
        • The user - Timeout value must be - estimated for the overall - process duration: the - Timeout measurement is - cumulative
          • -
        -
      • Update DMA - process:
        • -
          -
        • Update the - management of PPP peripheral - errors during DMA process. - This requires the following - updates in user application:
          • -
            -
          • Configure - and enable the PPP IRQ in - HAL_PPP_MspInit() - function
            • -
          • In - stm32f4xx_it.c file, PPP_IRQHandler() - function: add a call to HAL_PPP_IRQHandler() - - - - - function
            • -
          • Add and - customize the Error - Callback API: HAL_PPP_ErrorCallback()
            • -
          -
        -
      -
    • HAL - - - - FMC update
      • -
        -
      • Update FMC_NORSRAM_Init() - to remove the Burst access - mode configuration
        • -
      • Update FMC_SDRAM_Timing_Init() - to fix initialization issue - when configuring 2 SDRAM banks
        • -
      -
    • HAL - - - - HCD update
      • -
        -
      • Update HCD_Port_IRQHandler() - to unmask disconnect IT only - when the port is disabled
        • -
      -
    • HAL - - - - I2C/FMPI2C - update
      • -
        -
      • Update Polling - - - - - management:
        • -
          -
        • The Timeout - value must be estimated for - the overall process - duration: the - Timeout measurement is - cumulative
          • -
        -
      • Add the - management of Abort - service: Abort DMA - transfer through interrupt
        • -
          -
        • In the case - of Master Abort IT transfer - usage:
          • -
            -
          • Add new - - - - user HAL_I2C_AbortCpltCallback() - to inform user of the end - of abort process
            • -
          • A new - abort state is defined in - the HAL_I2C_StateTypeDef structure
            • -
          -
        -
      • Add the - management of I2C peripheral - errors, ACK failure and STOP - condition detection during DMA - process. This requires the - following updates on user - application:
        • -
          -
        • Configure - and enable the I2C IRQ in - HAL_I2C_MspInit() - function
          • -
        • In - stm32f4xx_it.c file, I2C_IRQHandler() - function: add a call to - HAL_I2C_IRQHandler() - function
          • -
        • Add and - customize the Error Callback - API: HAL_I2C_ErrorCallback()
          • -
        • Refer to - the I2C_EEPROM or - I2C_TwoBoards_ComDMA project - examples usage of the API
          • -
        -
      • NACK error - during addressing phase is - returned through interrupt - instead of previously through - I2C transfer API's
        • -
      • I2C - addressing phase is updated to - be managed using interrupt - instead of polling (Only - for HAL I2C driver)
        • -
          -
        • Add new - static functions to manage - I2C SB, ADDR and ADD10 flags
          • -
        -
      -
    • HAL - - - - SPI update
      • -
    -
      -
        -
      • Overall - driver optimization to improve - performance in - polling/interrupt mode to - reach maximum peripheral frequency
        • -
          -
        • Polling - mode:
          • -
            -
          • Replace - the use of SPI_WaitOnFlagUnitTimeout() - function by "if" statement - to check on RXNE/TXE flage - while transferring data
            • -
          -
        -
      -
    -
      -
        -
          -
        •  Interrupt - - - - mode:
          • -
            -
          • Minimize - access on SPI registers
            • -
          -
        • All modes:
          • -
            -
          • Add the - USE_SPI_CRC switch to - minimize the number of - statements when CRC - calculation is disabled
            • -
          • Update timeout - - - - - management to check on - global processes
            • -
          • Update - error code management in - all processes
            • -
          -
        -
      • Update DMA - process:
        • -
          -
        • Add the - management of SPI peripheral - errors during DMA process. - This requires the following - updates in the user - application:
          • -
            -
          • Configure - and enable the SPI IRQ in - HAL_SPI_MspInit() - function
            • -
          • In - stm32f4xx_it.c file, SPI_IRQHandler() - function: add a call to HAL_SPI_IRQHandler() - - - - - function
            • -
          • Add and - customize the Error - Callback API: HAL_SPI_ErrorCallback()
            • -
          • Refer to - the following example - which describe the - changes: SPI_FullDuplex_ComDMA
            • -
          -
        -
      • Fix - regression in polling mode:
        • -
          -
        • Add - preparing data to transmit - in case of slave mode in HAL_SPI_TransmitReceive() - and HAL_SPI_Transmit()
          • -
        • Add to - manage properly the overrun - flag at the end of a HAL_SPI_TransmitReceive()
          • -
        -
      • Fix - regression in interrupt mode:
        • -
          -
        • Add a wait - on TXE flag in SPI_CloseTx_ISR() - and in SPI_CloseTxRx_ISR()
          • -
        • Add to - manage properly - the overrun flag in SPI_CloseRxTx_ISR() - and SPI_CloseRx_ISR()
          • -
        -
      -
    -
      -
    • HAL - - - - DMA2D update
      • -
        -
      • Update the - HAL_DMA2D_DeInit() - function to:
        • -
          -
        • Abort - transfer in case of ongoing - DMA2D transfer
          • -
        • Reset DMA2D - control registers
          • -
        -
      • Update - HAL_DMA2D_Abort() - to disable DMA2D interrupts - after stopping transfer
        • -
      • Optimize - HAL_DMA2D_IRQHandler() - by reading status registers - only once
        • -
      • Update - HAL_DMA2D_ProgramLineEvent() - function to:
        • -
          -
        • Return HAL - error state in case of wrong - line value
          • -
        • Enable line - interrupt after setting the - line watermark configuration
          • -
        -
      • Add new - HAL_DMA2D_CLUTLoad() - and HAL_DMA2D_CLUTLoad_IT() functions - - - - - to start DMA2D CLUT loading
        • -
          -
        • HAL_DMA2D_CLUTLoading_Abort() - function to abort the DMA2D - CLUT loading
          • -
        • HAL_DMA2D_CLUTLoading_Suspend() - function to suspend the - DMA2D CLUT loading
          • -
        • HAL_DMA2D_CLUTLoading_Resume() - function to resume the DMA2D - CLUT loading
          • -
        -
      • Add new DMA2D - dead time management:
        • -
          -
        • HAL_DMA2D_EnableDeadTime() - function to enable DMA2D - dead time feature
          • -
        • HAL_DMA2D_DisableDeadTime() - function to disable DMA2D - dead time feature
          • -
        • HAL_DMA2D_ConfigDeadTime() - function to configure dead - time
          • -
        -
      • Update the - name of DMA2D Input/Output - color mode defines to be more - - - - clear for - user (DMA2D_INPUT_XXX for - input layers Colors, - DMA2D_OUTPUT_XXX for output - framebuffer Colors)
        • -
      -
    -
      -
    • HAL - - - - LTDC update
      • -
    -
      -
        -
      • Update HAL_LTDC_IRQHandler() - to manage the case of reload - interrupt
        • -
      • Add new - callback API HAL_LTDC_ReloadEventCallback()
        • -
      • Add HAL_LTDC_Reload() - to configure LTDC reload - feature
        • -
      • Add new No - Reload LTDC variant APIs
        • -
          -
        • HAL_LTDC_ConfigLayer_NoReload() to - configure the LTDC Layer - according to the specified - without reloading
          • -
        • HAL_LTDC_SetWindowSize_NoReload() to set - the LTDC window size without - reloading
          • -
        • HAL_LTDC_SetWindowPosition_NoReload() to set - the LTDC window position - without reloading
          • -
        • HAL_LTDC_SetPixelFormat_NoReload() to - reconfigure the pixel format - without reloading
          • -
        • HAL_LTDC_SetAlpha_NoReload() to - reconfigure the layer alpha - value without reloading
          • -
        • HAL_LTDC_SetAddress_NoReload() to - reconfigure the frame buffer - Address without reloading
          • -
        • HAL_LTDC_SetPitch_NoReload() to - reconfigure the pitch for - specific cases
          • -
        • HAL_LTDC_ConfigColorKeying_NoReload() to - configure the color keying - without reloading
          • -
        • HAL_LTDC_EnableColorKeying_NoReload() to enable - the color keying without - reloading
          • -
        • HAL_LTDC_DisableColorKeying_NoReload() to - disable the color keying - without reloading
          • -
        • HAL_LTDC_EnableCLUT_NoReload() to enable - the color lookup table - without reloading
          • -
        • HAL_LTDC_DisableCLUT_NoReload() to - disable the color lookup - table without reloading
          • -
        • Note: Variant - functions with “_NoReload” - post fix allows to set the - LTDC configuration/settings - without immediate reload. - This is useful in case when - the program requires to - modify several LTDC settings - (on one or both layers) then - applying (reload) these - settings in one shot by - calling the function “HAL_LTDC_Reload”
          • -
        -
      -
    • HAL - - - - RTC update 
      • -
        -
      • Add new - timeout implementation based - on cpu - cycles - for ALRAWF, ALRBWF - and WUTWF flags
        • -
      -
    -
      -
    • HAL - - - - SAI update
      • -
        -
      • Update SAI - state in case of TIMEOUT error - within the HAL_SAI_Transmit() - / HAL_SAI_Receive()
        • -
      • Update HAL_SAI_IRQHandler:
        • -
          -
        • Add error - management in case DMA - errors through XferAbortCallback() - and HAL_DMA_Abort_IT()
          • -
        • Add error - management in case of IT
          • -
        -
      • Move SAI_BlockSynchroConfig() - and SAI_GetInputClock() - - - - - functions to - stm32f4xx_hal_sai.c/.h files - (extension files are kept - empty for projects - compatibility reason)
        • -
      -
    -
      -
    • HAL - - - - DCMI update
      • -
        -
      • Rename DCMI_DMAConvCplt - to DCMI_DMAXferCplt
        • -
      • Update HAL_DCMI_Start_DMA() - function to Enable the - DCMI peripheral
        • -
      • Add new - timeout implementation based - on cpu - cycles for DCMI stop
        • -
      • Add HAL_DCMI_Suspend() - function to suspend DCMI - capture
        • -
      • Add HAL_DCMI_Resume() - function to resume capture - after DCMI suspend
        • -
      • Update lock - mechanism for DCMI process
        • -
      • Update HAL_DCMI_IRQHandler() - function to:
        • -
          -
        • Add error - management in case DMA - errors through XferAbortCallback() - and HAL_DMA_Abort_IT()
          • -
        • Optimize - code by using direct - register read
          • -
        -
      -
    -
      -
    • HAL - - - - DMA - update
      • -
        -
      • Add new APIs - HAL_DMA_RegisterCallback() - and HAL_DMA_UnRegisterCallback - to register/unregister the - different callbacks identified - by the enum - typedef HAL_DMA_CallbackIDTypeDef
        • -
      • Add new API HAL_DMA_Abort_IT() - to abort DMA transfer under - interrupt context
        • -
          -
        • The new - registered Abort callback is - called when DMA transfer - abortion is completed
          • -
        -
      • Add the check - of compatibility between FIFO - threshold level and size of - the memory burst in the HAL_DMA_Init() - API
        • -
      • Add new Error - Codes: HAL_DMA_ERROR_PARAM, - HAL_DMA_ERROR_NO_XFER and - HAL_DMA_ERROR_NOT_SUPPORTED
        • -
      • Remove all - DMA states related to - MEM0/MEM1 in HAL_DMA_StateTypeDef
        • -
      -
    • HAL - - - - IWDG - update
      • -
        -
      • Overall - rework of the driver for a - more - efficient implementation
        • -
          -
        • Remove the - following APIs:
          • -
            -
          • HAL_IWDG_Start()
            • -
          • HAL_IWDG_MspInit()
            • -
          • HAL_IWDG_GetState()
            • -
          -
        • Update - implementation:
          • -
            -
          • HAL_IWDG_Init(): this - function insures the - configuration and the - start of the IWDG counter
            • -
          • HAL_IWDG_Refresh(): this - function insures the - reload of the IWDG counter
            • -
          -
        • Refer to - the following example to - identify the changes: IWDG_Example
          • -
        -
      -
    • HAL - - - - LPTIM - update
      • -
        -
      • Update HAL_LPTIM_TimeOut_Start_IT() - and HAL_LPTIM_Counter_Start_IT( - ) APIs to configure WakeUp - Timer EXTI interrupt to be - able to wakeup - MCU from low power mode by - pressing the EXTI line.
        • -
      • Update HAL_LPTIM_TimeOut_Stop_IT() - and HAL_LPTIM_Counter_Stop_IT( - ) APIs to disable WakeUp - Timer EXTI interrupt. 
        • -
      -
    • HAL - - - - NOR update
      • -
        -
      • Update - NOR_ADDR_SHIFT macro implementation
        • -
      -
    • HAL - - - - PCD update
      • -
        -
      • Update HAL_PCD_IRQHandler() - to get HCLK frequency before - setting TRDT value
        • -
      -
    • HAL - - - - QSPI - update
      • -
    -
      -
        -
      • Update to - manage QSPI error management - during DMA process
        • -
      • Improve the - DMA transmit process by using - QSPI TC interrupt instead of - waiting loop on TC flag under - DMA ISR
        • -
      • These two - improvements require the - following updates on user - application:
        • -
          -
        • Configure - and enable the QSPI IRQ in HAL_QSPI_MspInit() - function
          • -
        • In - stm32f4xx_it.c file, QSPI_IRQHandler() - function: add a call to HAL_QSPI_IRQHandler() - - - - function
          • -
        • Add and - customize the Error Callback - API: HAL_QSPI_ErrorCallback()
          • -
        -
      • Add the - management of non-blocking - transfer abort service: HAL_QSPI_Abort_IT(). - - - - - In this case the user must:
        • -
          -
        • Add new - callback HAL_QSPI_AbortCpltCallback() - to inform user at the end of - abort process
          • -
        • A new value - of State in the HAL_QSPI_StateTypeDef - provides the current state - during the abort phase
          • -
        -
      • Polling - management update:
        • -
          -
        • The Timeout - value user must be estimated - for the overall process - duration: the - Timeout measurement is - cumulative. 
          • -
        -
      • Refer to the - following examples, which - describe the changes:
        • -
          -
        • QSPI_ReadWrite_DMA
          • -
        • QSPI_MemoryMapped
          • -
        • QSPI_ExecuteInPlace
          • -
        -
      -
    -
      -
        -
      • Add two new - APIs for the QSPI fifo - threshold:
        • -
          -
        • HAL_QSPI_SetFifoThreshold(): - configure the FIFO threshold - of the QSPI
          • -
        • HAL_QSPI_GetFifoThreshold(): give the - current FIFO threshold
          • -
        -
      • Fix wrong - data size management in HAL_QSPI_Receive_DMA()
        • -
      -
    -
      -
    • HAL - - - - ADC update
      • -
        -
      • Add new - __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() - macro for STM32F42x and - STM32F43x devices to - provide the possibility - to convert VrefInt - channel when both VrefInt - and Vbat - channels are selected.
        • -
      -
    • HAL - - - - SPDIFRX update
      • -
        -
      • Overall driver - update for wait on flag - management optimization 
        • -
      -
    • HAL - - - - WWDG update 
      • -
        -
      • Overall - rework of the driver for more - efficient implementation
        • -
          -
        • Remove the - following APIs:
          • -
            -
          • HAL_WWDG_Start()
            • -
          • HAL_WWDG_Start_IT()
            • -
          • HAL_WWDG_MspDeInit()
            • -
          • HAL_WWDG_GetState()
            • -
          -
        • Update - implementation:
          • -
            -
          • HAL_WWDG_Init()
            • -
              -
            • A new - - - - parameter in the Init - Structure: EWIMode
              • -
            -
          • HAL_WWDG_MspInit()
            • -
          • HAL_WWDG_Refresh() 
            • -
              -
            • This - function insures the - reload of the counter
              • -
            • The - "counter" parameter has - been removed
              • -
            -
          • HAL_WWDG_IRQHandler()
            • -
          • HAL_WWDG_EarlyWakeupCallback() is the - new prototype of HAL_WWDG_WakeUpCallback()
            • -
          -
        -
      • Refer to the - following example to identify - the changes: WWDG_Example
        • -
      -
    -

    V1.4.4 - - - - / 22-January-2016

    -

    Main Changes

    -
      -
    • HAL - - - - Generic update
      • -
        -
      • stm32f4xx_hal_conf_template.h
        • -
          -
        • Optimize - HSE Startup Timeout value - from 5000ms to 100 ms
          • -
        • Add new - define LSE_STARTUP_TIMEOUT
          • -
        • Add new - define USE_SPI_CRC for code - cleanup when the CRC - calculation is disabled.
          • -
        -
      • Update HAL - drivers to support MISRA C - 2004 rule 10.6
        • -
      • Add new - template driver to - configure timebase - using TIMER :
        • -
          -
        • stm32f4xx_hal_timebase_tim_template.c
          • -
        -
      -
    -
      -
    • HAL - - - - CAN update
      • -
        -
      • Update HAL_CAN_Transmit() - and HAL_CAN_Transmit_IT() - - - - - functions to unlock - process when all Mailboxes are - busy
        • -
      -
    -
      -
    • HAL - - - - DSI update
      • -
        -
      • Update HAL_DSI_SetPHYTimings() - functions to use the correct - mask
        • -
      -
    • HAL - - - - UART update
      • -
        -
      • Several - update on HAL UART driver to - implement the new UART state - machine: 
        • -
          -
        • Add new - field in UART_HandleTypeDef - structure: "rxState", - - - - - UART state information - related to Rx Operations
          • -
        • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": - - - - UART state information - related to global Handle - management and Tx Operations
          • -
        • Update UART - process to manage the new - UART states.
          • -
        • Update - __HAL_UART_RESET_HANDLE_STATE() - macro to handle the new UART - state parameters (gState, - rxState)
          • -
        -
      • Update - UART_BRR_SAMPLING16() and - UART_BRR_SAMPLING8() Macros to - fix wrong baudrate - calculation.
        • -
      -
    -
      -
    • HAL - - - - IRDA update
      • -
        -
      • Several - update on HAL IRDA driver to - implement the new UART state - machine: 
        • -
          -
        • Add new - field in IRDA_HandleTypeDef - structure: "rxState", - - - - - IRDA state information - related to Rx Operations
          • -
        • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": - - - - IRDA state information - related to global Handle - management and Tx Operations
          • -
        • Update IRDA - process to manage the new - UART states.
          • -
        • Update - __HAL_IRDA_RESET_HANDLE_STATE() - macro to handle the new IRDA - state parameters (gState, - rxState)
          • -
        -
      • Removal of - IRDA_TIMEOUT_VALUE define
        • -
      • Update IRDA_BRR() - Macro to fix wrong baudrate - calculation
        • -
      -
    • HAL - - - - SMARTCARD update
      • -
        -
      • Several - update on HAL SMARTCARD driver - to implement the new UART - state machine: 
        • -
          -
        • Add new - field in SMARTCARD_HandleTypeDef - structure: "rxState", - - - - - SMARTCARDstate - information related to Rx Operations
          • -
        • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": - - - - SMARTCARDstate - information related to - global Handle management and - Tx Operations
          • -
        • Update SMARTCARD - - - - - process to manage the new - UART states.
          • -
        • Update - __HAL_SMARTCARD_RESET_HANDLE_STATE() - macro to handle the - new SMARTCARD state - parameters (gState, - rxState)
          • -
        -
      • Update - SMARTCARD_BRR() - macro to fix wrong baudrate - calculation
        • -
      -
    -
      -
    • HAL  - RCC - update
      • -
        -
      • Add new - default define value for HSI - calibration - "RCC_HSICALIBRATION_DEFAULT"
        • -
      • Optimize - Internal oscillators and PLL - startup timeout 
        • -
      • Update to - avoid the disable for HSE/LSE - oscillators before setting the - new RCC HSE/LSE configuration - and add the following notes in - HAL_RCC_OscConfig() - API description:
        • -
      -
    -

         - - - -       -     -     -     -       * - @note   Transitions LSE - Bypass to LSE On and LSE On to LSE - Bypass are not
    -         - - - - -     -     -     -     -     -      - *         -     supported by this - API. User should request a - transition to LSE Off
    -         - - - - -     -     -     -     -     -      - *         -     first and then LSE - On or LSE Bypass.
    -         - - - - -     -     -     -     -     -      * - @note   Transition HSE - Bypass to HSE On and HSE On to HSE - Bypass are not
    -         - - - - -     -     -     -     -     -      - *         -     supported by this - API. User should request a - transition to HSE Off
    -         - - - - -     -     -     -         -      - *         -     first and then HSE - On or HSE Bypass.

    -
      -
        -
      • Optimize - the HAL_RCC_ClockConfig() - API implementation.
        • -
      -
    -
      -
    • HAL - - - - DMA2D update
      • -
        -
      • Update - HAL_DMA2D_Abort() - Function to end current DMA2D - transfer properly
        • -
      • Update - HAL_DMA2D_PollForTransfer() - function to add poll for - background CLUT loading (layer - 0 and layer 1).
        • -
      • Update - HAL_DMA2D_PollForTransfer() - to set the corresponding ErrorCode - in case of error occurrence
        • -
      • Update - HAL_DMA2D_ConfigCLUT() - function to fix wrong CLUT - size and color mode settings
        • -
      • Removal of - useless macro __HAL_DMA2D_DISABLE()
        • -
      • Update - HAL_DMA2D_Suspend() - to manage correctly the case - where no transfer is on going
        • -
      • Update - HAL_DMA2D_Resume() to - - - - - manage correctly the case - where no transfer is on going
        • -
      • Update - HAL_DMA2D_Start_IT() - to enable all required - interrupts before enabling the - transfer.
        • -
      • Add - HAL_DMA2D_CLUTLoad_IT() - Function to allow loading a - CLUT with interruption model.
        • -
      •  Update - HAL_DMA2D_IRQHandler() - to manage the following - cases :
        -
        -
        • -
          -
        • CLUT - transfer complete
          • -
        • CLUT access - error
          • -
        • Transfer - watermark reached
          • -
        -
      • Add new - Callback APIs:
        • -
          -
        •  HAL_DMA2D_LineEventCallback() - to signal a transfer - watermark reached event
          • -
        •  HAL_DMA2D_CLUTLoadingCpltCallback() - to signal a CLUT loading - complete event
          • -
        -
      -
    -
      -
        -
      • Miscellaneous - Improvement:
        • -
          -
        • Add - "HAL_DMA2D_ERROR_CAE" new - define for CLUT Access error - management.
          • -
        • Add     “assert_param” - used for parameters check is - now done on the top of the - exported functions : before - locking the process using - __HAL_LOCK
          • -
        -
      -
    -

     

    -
      -
    • HAL - - - - I2C update
      • -
        -
      • Add support - of I2C repeated start feature:
        • -
          -
        • With the - following new API's
          • -
            -
          • HAL_I2C_Master_Sequential_Transmit_IT()
            • -
          • HAL_I2C_Master_Sequential_Receive_IT()
            • -
          • HAL_I2C_Master_Abort_IT()
            • -
          • HAL_I2C_Slave_Sequential_Transmit_IT()
            • -
          • HAL_I2C_Slave_Sequential_Receive_IT()
            • -
          • HAL_I2C_EnableListen_IT()
            • -
          • HAL_I2C_DisableListen_IT()
            • -
          -
        • Add new - user callbacks:
          • -
            -
          • HAL_I2C_ListenCpltCallback()
            • -
          • HAL_I2C_AddrCallback()
            • -
          -
        -
      • Update to - generate STOP condition when a - acknowledge failure error is detected
        • -
      • Several - update on HAL I2C driver to - implement the new I2C state - machine: 
        • -
          -
        • Add new API - to get the I2C mode: - HAL_I2C_GetMode()
          • -
        • Update I2C - process to manage the new - I2C states.
          • -
        -
      • Fix wrong behaviour - in single byte transmission 
        • -
      • Update I2C_WaitOnFlagUntilTimeout() to - - - - - manage the NACK feature.
        • -
      • Update  I2C - transmission process to - support the case data size - equal 0
        • -
      -
    -
      -
    • HAL - - - - FMPI2C update
      • -
        -
      • Add support - of FMPI2C repeated start - feature:
        • -
          -
        • With the - following new API's
          • -
            -
          • HAL_FMPI2C_Master_Sequential_Transmit_IT()
            • -
          • HAL_FMPI2C_Master_Sequential_Receive_IT()
            • -
          • HAL_FMPI2C_Master_Abort_IT()
            • -
          • HAL_FMPI2C_Slave_Sequential_Transmit_IT()
            • -
          • HAL_FMPI2C_Slave_Sequential_Receive_IT()
            • -
          • HAL_FMPI2C_EnableListen_IT()
            • -
          • HAL_FMPI2C_DisableListen_IT()
            • -
          -
        • Add new - user callbacks:
          • -
            -
          • HAL_FMPI2C_ListenCpltCallback()
            • -
          • HAL_FMPI2C_AddrCallback()
            • -
          -
        -
      • Several - update on HAL I2C driver to - implement the new I2C state - machine: 
        • -
          -
        • Add new API - to get the FMPI2C mode: - HAL_FMPI2C_GetMode()
          • -
        • Update - FMPI2C process to manage the - new FMPI2C states.
          • -
        -
      -
    -
      -
    • HAL - - - - SPI update
      • -
        -
      • Major Update - to improve performance in - polling/interrupt mode to - reach max frequency:
        • -
          -
        • Polling mode - - - - :
          • -
            -
          • Replace - use of SPI_WaitOnFlagUnitTimeout() - funnction - by "if" statement to check - on RXNE/TXE flage - while transferring data.
            • -
          • Use API - data pointer instead of - SPI handle data pointer.
            • -
          • Use a Goto - implementation instead of - "if..else" - statements.
            • -
          -
        -
      -
    -
      -
        -
          -
        • Interrupt - mode
          • -
            -
          • Minimize - access on SPI registers.
            • -
          • Split the - SPI modes into dedicated - static functions to - minimize checking - statements under HAL_IRQHandler():
            • -
              -
            • 1lines/2lines - - - - modes
              • -
            • 8 bit/ - 16 bits data formats
              • -
            • CRC - calculation - enabled/disabled.
              • -
            -
          • Remove - waiting loop under ISR - when closing - - - -  the - communication.
            • -
          -
        • All - modes:  
          • -
            -
          • Adding - switch USE_SPI_CRC to - minimize number of - statements when CRC - calculation is disabled.
            • -
          • Update - Timeout management to - check on global process.
            • -
          • Update - Error code management in - all processes.
            • -
          -
        -
      • Add note to - the max frequencies reached in - all modes.
        • -
      • Add note - about Master Receive mode restrictions :
        • -
          -
        • Master - - - - Receive mode restriction:
          -       - (#) In Master - unidirectional receive-only - mode (MSTR =1, BIDIMODE=0, - RXONLY=0) or
          -           - - - - - bidirectional receive mode - (MSTR=1, BIDIMODE=1, - BIDIOE=0), to ensure that - the SPI
          -           - - - - does not initiate a new - transfer the following - procedure has to be - respected:
          -           - - - - (##) HAL_SPI_DeInit()
          -           - - - - (##) HAL_SPI_Init() - - - -
          • -
        -
      -
    -
      -
    • HAL - - - - SAI update
      • -
        -
      • Update for - proper management of the - external synchronization input - selection
        • -
          -
        • update - of HAL_SAI_Init - () funciton
          • -
        • update - definition of SAI_Block_SyncExt - and SAI_Block_Synchronization - groups
          • -
        -
      • Update - SAI_SLOTACTIVE_X -  defines - values
        • -
      • Update HAL_SAI_Init() - function for proper companding - mode management
        • -
      • Update SAI_Transmit_ITxxBit() - functions to add the check on - transfer counter before - writing new data to SAIx_DR - registers
        • -
      • Update SAI_FillFifo() - function to avoid issue when - the number of data to transmit - is smaller than the FIFO size
        • -
      • Update HAL_SAI_EnableRxMuteMode() - function for proper mute - management
        • -
      • Update SAI_InitPCM() - function to support 24bits - configuration
        • -
      -
    • HAL - - - - ETH update
      • -
        -
      • Removal of - ETH MAC debug register defines
        • -
      -
    • HAL - - - - FLASH update
      • -
        -
      • Update FLASH_MassErase() - function to apply correctly - voltage range parameter
        • -
      -
    • HAL - - - - I2S update
      • -
        -
      • Update I2S_DMATxCplt() - and I2S_DMARxCplt() to manage - properly FullDuplex - mode without any risk of - missing data.
        • -
      -
    • LL - - - - FMC update
      • -
        -
      • Update the FMC_NORSRAM_Init() - function to use BurstAccessMode - field properly
        • -
      -
    • LL - - - - FSMC  - - - - update
      • -
        -
      • Update the FSMC_NORSRAM_Init() - function to use BurstAccessMode - field properly
        • -
      -
    -


    -
    -

    -

    V1.4.4 - / 11-December-2015

    -

    Main Changes

    -
      -
    • HAL - - - - Generic update
      • -
        -
      • Update HAL - weak empty callbacks to - prevent unused argument - compilation warnings with some - compilers by calling the - following line:
        • -
          -
        • UNUSED(hppp);
          • -
        -
      • STM32Fxxx_User_Manual.chm - - - - - files regenerated for HAL - V1.4.3
        • -
      -
    • HAL - - - - ETH update 
      • -
        -
      • Update HAL_ETH_Init() - function to add timeout on the - Software reset management
        • -
      -
    -

    V1.4.2 - - - - / 10-November-2015

    -

    Main Changes

    -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • One - - - - change done on the HAL CRYP - requires an update on the - application code based on HAL - V1.4.1
      • -
        -
      • Update HAL_CRYP_DESECB_Decrypt() - API to invert pPlainData - and pCypherData - parameters
        • -
      -
    • HAL - - - - generic - update
      • -
        -
      • Update HAL - weak empty callbacks to - prevent unused argument - compilation warnings with some - compilers by calling the - following line:
        • -
          -
        • UNUSED(hppp);
          • -
        -
      -
    -
      -
    • HAL - - - - CORTEX update
      • -
        -
      • Remove - duplication for - __HAL_CORTEX_SYSTICKCLK_CONFIG() - macro
        • -
      -
    -
      -
    • HAL - - - - HASH update
      • -
        -
      • Rename HAL_HASH_STATETypeDef - to HAL_HASH_StateTypeDef
        • -
      • Rename HAL_HASH_PhaseTypeDef - to HAL_HASH_PhaseTypeDef
        • -
      -
    • HAL - - - - RCC update
      • -
        -
      • Add new - macros __HAL_RCC_PPP_IS_CLK_ENABLED() - to check on Clock - enable/disable status
        • -
      • Update - __HAL_RCC_USB_OTG_FS_CLK_DISABLE() - macro to remove the disable - for the SYSCFG
        • -
      • Update HAL_RCC_MCOConfig() - API to use new defines for the - GPIO Speed
        • -
      • Generic - update to improve the - PLL VCO min - value(100MHz): PLLN, PLLI2S - and PLLSAI min value is 50 - instead of 192
        • -
      -
    • HAL - - - - FLASH update
      • -
        -
      • __HAL_FLASH_INSTRUCTION_CACHE_RESET() - macro: update to reset -  ICRST bit in - the ACR register after - setting it.
        • -
      • Update to - support until 15 FLASH wait - state (FLASH_LATENCY_15) for - STM32F446xx devices -
        • -
      -
    -

    §  - - - - - HAL CRYP update

    -
      -
        -
      • Update HAL_CRYP_DESECB_Decrypt() - API to fix the inverted pPlainData - and pCypherData - parameters issue
        • -
      -
    • HAL - - - - I2S update
      • -
        -
      • Update - HAL_I2S_Init() - API to call - __HAL_RCC_I2S_CONFIG() macro - when external I2S clock is - selected
        • -
      -
    • HAL - - - - LTDC update
      • -
        -
      • Update HAL_LTDC_SetWindowPosition() - API to configure - Immediate reload register - instead of vertical blanking - reload register.
        • -
      -
    • HAL - - - - TIM update
      • -
        -
      • Update HAL_TIM_ConfigClockSource() - API to check only the - required parameters
        • -
      -
    • HAL - - - - NAND update
      • -
        -
      • Update - HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() - APIs to manage correctly the - NAND Page access
        • -
      -
    • HAL - - - - CAN update
      • -
        -
      • Update to use - "=" instead of "|=" to clear - flags in the MSR, TSR, RF0R - and RF1R registers
        • -
      -
    • HAL - - - - HCD update
      • -
        -
      • Fix typo in - __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() - macro implementation
        • -
      -
    • HAL - - - - PCD update
      • -
        -
      • Update HAL_PCD_IRQHandler() - API to avoid issue - when DMA mode enabled for - Status Phase IN stage
        • -
      -
    • LL - - - - FMC update
      • -
        -
      • Update the FMC_NORSRAM_Extended_Timing_Init() - API to remove the check - on CLKDIvison - and DataLatency - parameters
        • -
      • Update the FMC_NORSRAM_Init() - API to add a check on the PageSize - parameter for STM32F42/43xx - devices
        • -
      -
    • LL - - - - FSMC update
      • -
        -
      • Update the FSMC_NORSRAM_Extended_Timing_Init() - API to remove the check - on CLKDIvison - and DataLatency - parameters
        • -
      -
    -

    V1.4.1 - - - - / 09-October-2015

    -

    Main Changes

    -
      -
    • HAL - - - - DSI update
      • -
        -
      • Update TCCR - register assigned value - in HAL_DSI_ConfigHostTimeouts() - function
        • -
      • Update WPCR - register assigned value - in HAL_DSI_Init(), - - - - - HAL_DSI_SetSlewRateAndDelayTuning(), - - - - - HAL_DSI_SetSlewRateAndDelayTuning(), - - - - - HAL_DSI_SetLowPowerRXFilter() - - - - - / HAL_DSI_SetSDD(), - - - - - HAL_DSI_SetLanePinsConfiguration(), - - - - - HAL_DSI_SetPHYTimings(), - - - - - HAL_DSI_ForceTXStopMode(), - - - - - HAL_DSI_ForceRXLowPower(), - - - - - HAL_DSI_ForceDataLanesInRX(), - - - - - HAL_DSI_SetPullDown() - - - - - and HAL_DSI_SetContentionDetectionOff() - - - - - functions
        • -
      • Update - DSI_HS_PM_ENABLE define value
        • -
      • Implement - workaround for the hardware - limitation: “The time to - activate the clock between HS - transmissions is not - calculated correctly”
        • -
      -
    -

    V1.4.0 - - - - / 14-August-2015

    -

    Main Changes

    -
      -
    • Add - support of STM32F469xx, STM32F479xx, - STM32F410Cx, STM32F410Rx - and STM32F410Tx  - devices
      • -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • Add - new HAL drivers for DSI and LPTIM - - - - - peripherals
      • -
    -
      -
    • HAL - - - - ADC update
      • -
        -
      • Rename - ADC_CLOCKPRESCALER_PCLK_DIV2 - define to - ADC_CLOCK_SYNC_PCLK_DIV2
        • -
      • Rename - ADC_CLOCKPRESCALER_PCLK_DIV4 - define to - ADC_CLOCK_SYNC_PCLK_DIV4
        • -
      • Rename - ADC_CLOCKPRESCALER_PCLK_DIV6 - define to - ADC_CLOCK_SYNC_PCLK_DIV6
        • -
      • Rename - ADC_CLOCKPRESCALER_PCLK_DIV8 - define to - ADC_CLOCK_SYNC_PCLK_DIV8
        • -
      -
    • HAL - - - - CORTEX update
      • -
        -
      • Add specific - API for MPU management
        • -
          -
        • add MPU_Region_InitTypeDef - structure
          • -
        • add new - function HAL_MPU_ConfigRegion()
          • -
        -
      -
    • HAL - - - - DMA update
      • -
        -
      • Overall driver - update for code optimization
        • -
          -
        • add StreamBaseAddress - and StreamIndex - new fields in the DMA_HandleTypeDef - structure
          • -
        • add DMA_Base_Registers - private structure
          • -
        • add static - function DMA_CalcBaseAndBitshift()
          • -
        • update HAL_DMA_Init() - function to use the new - added static function
          • -
        • update HAL_DMA_DeInit() - function to optimize clear - flag operations
          • -
        • update HAL_DMA_Start_IT() - function to optimize - interrupts enable
          • -
        • update HAL_DMA_PollForTransfer() - function to optimize check - on flags
          • -
        • update HAL_DMA_IRQHandler() - function to optimize - interrupt flag management
          • -
        -
      -
    • HAL - - - - FLASH update
      • -
        -
      • update HAL_FLASH_Program_IT() - function by removing the - pending flag clear
        • -
      • update HAL_FLASH_IRQHandler() - function to improve erase - operation procedure
        • -
      • update FLASH_WaitForLastOperation() - function by checking on end of - operation flag
        • -
      -
    • HAL - - - - GPIO update
      • -
        -
      • Rename - GPIO_SPEED_LOW define to - GPIO_SPEED_FREQ_LOW
        • -
      • Rename - GPIO_SPEED_MEDIUM define to - GPIO_SPEED_FREQ_MEDIUM
        • -
      • Rename - GPIO_SPEED_FAST define to - GPIO_SPEED_FREQ_HIGH
        • -
      • Rename - GPIO_SPEED_HIGH define to - GPIO_SPEED_FREQ_VERY_HIGH
        • -
      -
    • HAL - - - - I2S update
      • -
        -
      • Move - I2S_Clock_Source defines to - extension file to properly add - the support of STM32F410xx devices
        • -
      -
    • HAL - - - - LTDC update
      • -
        -
      • rename HAL_LTDC_LineEvenCallback() - function to HAL_LTDC_LineEventCallback()
        • -
      • add new - function HAL_LTDC_SetPitch()
        • -
      • add new - functions HAL_LTDC_StructInitFromVideoConfig() - and HAL_LTDC_StructInitFromAdaptedCommandConfig() - - - - - applicable only to STM32F469xx - and STM32F479xx devices
        • -
      -
    • HAL - - - - PWR update
      • -
        -
      • move - __HAL_PWR_VOLTAGESCALING_CONFIG() - macro to extension file
        • -
      • move - PWR_WAKEUP_PIN2 define to - extension file
        • -
      • add - PWR_WAKEUP_PIN3 define, - applicable only to STM32F10xx - devices
        • -
      • add new - functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() - and HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), - - - - - applicable only to STM32F469xx - and STM32F479xx devices
        • -
      -
    -
      -
    • HAL - - - - RTC update
      • -
        -
      • Update HAL_RTCEx_SetWakeUpTimer() - and HAL_RTCEx_SetWakeUpTimer_IT() - - - - - functions to properly check on - the WUTWF flag
        • -
      -
    • HAL - - - - TIM update
      • -
        -
      • add new - defines TIM_SYSTEMBREAKINPUT_HARDFAULT,  - - - - TIM_SYSTEMBREAKINPUT_PVD - - - - - and - TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD, - applicable only to STM32F410xx - devices
        • -
      -
    -

    V1.3.2 - - - - / 26-June-2015

    -

    Main Changes

    -
      -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • One - - - - changes - done on the HAL may require an - update on the application code - based on HAL V1.3.1
      • -
        -
      • HASH IT - process: update to call the HAL_HASH_InCpltCallback() - at the end of the complete - buffer instead of every each - 512 bits
        • -
      -
    -
      -
    • HAL - - - - RCC update
      • -
        -
      • HAL_RCCEx_PeriphCLKConfig() updates:
        • -
          -
        • Update the - LSE check condition after - backup domain reset: - update to check LSE - ready flag when LSE - oscillator is already - enabled instead of check on - LSE oscillator only when LSE - is used as RTC clock source
          • -
        • Use the - right macro to check the - PLLI2SQ parameters -
          • -
        -
      -
    -
      -
    • HAL - - - - RTC update
      • -
        -
      • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() - macro: fix implementation - issue
        • -
      • __HAL_RTC_ALARM_GET_IT(), - - - - - __HAL_RTC_ALARM_CLEAR_FLAG(), - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(), - - - - - __HAL_RTC_TIMESTAMP_CLEAR_FLAG() - - - - and - __HAL_RTC_TAMPER_CLEAR_FLAG() - macros implementation changed: - remove unused cast
        • -
      • IS_RTC_TAMPER() - macro: update to use literal - instead of hardcoded - value 
        • -
      • Add new - parameter SecondFraction - in RTC_TimeTypeDef - structure
        • -
      • HAL_RTC_GetTime() API update - to support the new - parameter SecondFraction -
        • -
      -
    • HAL - - - - ADC update
      • -
        -
      • Add new - literal: - ADC_INJECTED_SOFTWARE_START to - be used as possible value for - the ExternalTrigInjecConvEdge - parameter in the ADC_InitTypeDef - structure to select the ADC - software trigger mode.
        • -
      -
    • HAL - - - - FLASH update
      • -
        -
      • FLASH_OB_GetRDP() API update - to return uint8_t instead of FlagStatus
        • -
      •  __HAL_FLASH_GET_LATENCY() - new macro add to get the flash - latency
        • -
      -
    • HAL - - - - SPI update
      • -
        -
      • Fix the wrong - definition of - HAL_SPI_ERROR_FLAG literal
        • -
      -
    • HAL - - - - I2S update
      • -
        -
      • HAL_I2S_Transmit() - API update to check on busy - flag only for I2S slave mode
        • -
      -
    • HAL - - - - CRC update
      • -
        -
      • __HAL_CRC_SET_IDR() - macro implementation change to - use WRITE_REG() instead of - MODIFY_REG()
        • -
      -
    • HAL - - - - DMA2D update
      • -
        -
      • HAL_DMA2D_ConfigLayer() - API update to use "=" instead - of "|=" to erase BGCOLR and - FGCOLR registers before - setting the new configuration
        • -
      -
    • HAL - - - - HASH update
      • -
        -
      • HAL_HASH_MODE_Start_IT() (MODE - - - - stands for MD5, SHA1, - SHA224 and SHA36) updates:
        • -
          -
        • Fix processing - - - - - fail for small input buffers
          • -
        • Update to - unlock the process and - call return - HAL_OK at the end of - HASH processing to avoid - incorrectly repeating software
          • -
        • Update to - properly manage the HashITCounter
          • -
        • Update to - call the HAL_HASH_InCpltCallback() - at the end of the complete - buffer instead of every each - 512 bits
          • -
        -
      • __HAL_HASH_GET_FLAG() - update to  check the - right register when the DINNE - flag  is selected
        • -
      • HAL_HASH_SHA1_Accumulate() - updates:
        • -
          -
        • Add - a call to the new - IS_HASH_SHA1_BUFFER_SIZE() - macro to check the size - parameter. 
          • -
        • Add the - following note in API description
          • -
        -
      -
    -
    -

     * - - - - - @note  - - - - - Input buffer - size in bytes must be a multiple - of 4 otherwise the digest - computation is corrupted.

    -
    -
      -
    • HAL - - - - RTC update
      • -
        -
      • Update to - define hardware - independent literals names:
        • -
          -
        • Rename - RTC_TAMPERPIN_PC13 by - - - -  RTC_TAMPERPIN_DEFAULT
          • -
        • Rename - RTC_TAMPERPIN_PA0 by - RTC_TAMPERPIN_POS1
          • -
        • Rename - RTC_TAMPERPIN_PI8 by - RTC_TAMPERPIN_POS1
          • -
        • Rename - RTC_TIMESTAMPPIN_PC13 by - RTC_TIMESTAMPPIN_DEFAULT
          • -
        • Rename - RTC_TIMESTAMPPIN_PA0 by - RTC_TIMESTAMPPIN_POS1
          • -
        • Rename - RTC_TIMESTAMPPIN_PI8 by - RTC_TIMESTAMPPIN_POS1
          • -
        -
      -
    • HAL - - - - ETH update
      • -
        -
      • Remove - duplicated IS_ETH_DUPLEX_MODE() - and IS_ETH_RX_MODE() macros
        • -
      • Remove - illegal space - ETH_MAC_READCONTROLLER_FLUSHING - macro
        • -
      • Update - ETH_MAC_READCONTROLLER_XXX - defined values (XXX can be - IDLE, READING_DATA and - READING_STATUS)
        • -
      -
    • HAL - - - - PCD update
      • -
        -
      • HAL_PCD_IRQHandler API: fix the - bad Configuration of - Turnaround Time
        • -
      -
    • HAL - - - - HCD update
      • -
        -
      • Update to use - local variable in USB - Host channel re-activation
        • -
      -
    • LL - - - - FMC update
      • -
        -
      • FMC_SDRAM_SendCommand() API: remove - the following line: return - HAL_ERROR;
        • -
      -
    • LL - - - - USB update
      • -
        -
      • USB_FlushTxFifo API: - update to flush all Tx FIFO
        • -
      • Update to use - local variable in USB - Host channel re-activation
        • -
      -
    -

    V1.3.1 - - - - / 25-Mars-2015

    -

    Main Changes

    -
      -
    • HAL - - - - PWR update
      • -
        -
      • Fix - compilation issue with - STM32F417xx product: - update STM32F17xx - by STM32F417xx
        • -
      -
    • HAL - - - - SPI update
      • -
        -
      • Remove unused - variable to avoid warning with - TrueSTUDIO 
        • -
      -
    • HAL - - - - I2C update
      • -
        -
      • I2C - Polling/IT/DMA processes: move - the wait loop on busy - flag at the top of the - processes, to ensure that - software not perform any write - access to I2C_CR1 register - before hardware - clearing STOP bit and to - avoid - - - - - also the - waiting loop on BUSY flag - under I2C/DMA ISR.
        • -
      • Update busy - flag Timeout value
        • -
      • I2C Master - Receive Processes update to - disable ACK before generate - the STOP 
        • -
      -
    • HAL - - - - DAC update
      • -
        -
      • Fix V1.3.0 - regression issue with DAC - software trigger configuration
        • -
      -
    -

    V1.3.0 - - - - / 09-Mars-2015

    -

    Main Changes

    -
      -
    • Add - support of STM32F446xx devices
      • -
    • General - - - - updates to fix known defects and - enhancements implementation
      • -
    • Add - new HAL drivers for CEC, - QSPI, FMPI2C and SPDIFRX - - - - peripherals
      • -
    • Two - - - - changes done on the HAL - requires an update on the - application code based on HAL - V1.2.0
      • -
        -
      • Overall SAI - driver rework to have - exhaustive support of the - peripheral features: details - are provided in HAL SAI update - - - - section below --> Compatibility - - - - - with previous version is impacted
        • -
      • CRYP driver - updated to support multi instance,so - user must ensure that the - new parameter Instance is - initalized - in his application(CRYPHandle.Instance - = CRYP) 
        • -
      -
    -
      -
    • HAL - - - - Generic update
      • -
        -
      • stm32f4xx_hal_def.h
        • -
          -
        • Remove NULL - definition and add - include for stdio.h
          • -
        -
      • stm32_hal_legacy.h
        • -
          -
        • Update method - - - - to manage deference in - alias implementation between - all STM32 families
          • -
        -
      • stm32f4xx_hal_ppp.c
        • -
          -
        • HAL_PPP_Init(): update - to force the - HAL_PPP_STATE_RESET before - calling the HAL_PPP_MspInit()
          • -
        -
      -
    -
      -
    • HAL - - - - RCC update
      • -
        -
      • Add new - function HAL_RCCEx_GetPeriphCLKFreq()
        • -
      • Move RCC_PLLInitTypeDef - structure to extension file - and add the new PLLR field - specific to STM32F446xx devices
        • -
      • Move the - following functions to - extension file and add a - __weak attribute in generic driver - - - - : this - update is related to new - system clock source (PLL/PLLR) - added and only available for - STM32F44xx devices
        • -
          -
        • HAL_RCC_OscConfig()
          • -
        • HAL_RCC_GetSysClockFreq()
          • -
        • HAL_RCC_GetOscConfig()
          • -
        -
      • Move the - following macro to extension - file as they have device - dependent implementation
        • -
          -
        • __HAL_RCC_PLL_CONFIG()
          • -
        • __HAL_RCC_PLLI2S_CONFIG()
          • -
        • __HAL_RCC_I2S_CONFIG()
          • -
        -
      • Add new - structure RCC_PLLI2SInitTypeDef - containing new PLLI2S - division factors used only w/ - STM32F446xx devices
        • -
      • Add new - structure RCC_PLLSAIInitTypeDef - containing new PLLSAI - division factors used only w/ - STM32F446xx devices
        • -
      • Add new RCC_PeriphCLKInitTypeDef - to support the peripheral - source clock selection for (I2S, - - - - SAI, SDIO, FMPI2C, CEC, - SPDIFRX and CLK48)
        • -
      • Update the HAL_RCCEx_PeriphCLKConfig() - and HAL_RCCEx_GetPeriphCLKConfig() - - - - - functions to support the - new peripherals Clock source - selection
        • -
      • Add __HAL_RCC_PLL_CONFIG() - macro (the number of parameter - and the implementation depend - on the device part number)
        • -
      • Add __HAL_RCC_PLLI2S_CONFIG() - macro(the number of parameter - and the implementation depend - on device part number)
        • -
      • Update __HAL_RCC_PLLSAI_CONFIG() - macro to support new PLLSAI - factors (PLLSAIM and - PLLSAIP)
        • -
      • Add new - macros for clock - enable/Disable for the - following peripherals (CEC, - - - - SPDIFRX, SAI2, QUADSPI)
        • -
      • Add the - following new macros for clock - source selection - - - - :
        • -
          -
        • __HAL_RCC_SAI1_CONFIG() - / - __HAL_RCC_GET_SAI1_SOURCE()
          • -
        • __HAL_RCC_SAI2_CONFIG() - / - __HAL_RCC_GET_SAI2_SOURCE()
          • -
        • __HAL_RCC_I2S1_CONFIG() - / - __HAL_RCC_GET_I2S1_SOURCE()
          • -
        • __HAL_RCC_I2S2_CONFIG() - / - __HAL_RCC_GET_I2S2_SOURCE()
          • -
        • __HAL_RCC_CEC_CONFIG() - / - __HAL_RCC__GET_CEC_SOURCE() -
          • -
        • __HAL_RCC_FMPI2C1_CONFIG() - / - __HAL_RCC_GET_FMPI2C1_SOURCE() -
          • -
        • __HAL_RCC_SDIO_CONFIG() - / - __HAL_RCC_GET_SDIO_SOURCE() -
          • -
        • __HAL_RCC_CLK48_CONFIG() - / - __HAL_RCC_GET_CLK48_SOURCE() -
          • -
        • __HAL_RCC_SPDIFRXCLK_CONFIG() - / - __HAL_RCC_GET_SPDIFRX_SOURCE()
          • -
        -
      • __HAL_RCC_PPP_CLK_ENABLE(): - - - - - Implement workaround to cover - RCC limitation regarding - peripheral enable delay
        • -
      • HAL_RCC_OscConfig() fix - issues: 
        • -
          -
        • Add a check - on LSERDY flag when - LSE_BYPASS is selected as - new state for LSE - oscillator.
          • -
        -
      • Add - new possible value RCC_PERIPHCLK_PLLI2S - - - - to be selected as PeriphClockSelection - parameter in the - - - - -  RCC_PeriphCLKInitTypeDef - structure to allow the - possibility to output the - PLLI2S on MCO without - activating the I2S or the SAI.
        • -
      • __HAL_RCC_HSE_CONFIG() -  macro: add - the comment below:
        • -
      -
    -
    -

     * - - - - - @note   Transition - HSE Bypass to HSE On and HSE - On to HSE Bypass are not - supported by this macro.
    -  *         - - - - User should request a - transition to HSE Off first - and then HSE On or HSE Bypass.

    -
    -
      -
        -
      • __HAL_RCC_LSE_CONFIG()  macro: add - the comment below:
        • -
      -
    -
    -

      * - - - - - @note   Transition - LSE Bypass to LSE On and LSE - On to LSE Bypass are not - supported by this macro.
    -   - *         - User should request a - transition to LSE Off first - and then LSE On or LSE Bypass.

    -
    -
      -
        -
      • Add the - following new macros for - PLL source and PLLM selection - - - - :
        • -
          -
        • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
          • -
        • __HAL_RCC_PLL_PLLM_CONFIG()
          • -
        -
      • Macros - rename:
        • -
          -
        • HAL_RCC_OTGHS_FORCE_RESET() -by HAL_RCC_USB_OTG_HS_FORCE_RESET()
          • -
        • HAL_RCC_OTGHS_RELEASE_RESET() -by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
          • -
        • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() -by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
          • -
        • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() -by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
          • -
        • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() -by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
          • -
        • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() -by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
          • -
        -
      • Add __HAL_RCC_SYSCLK_CONFIG() - new macro to configure the - system clock source (SYSCLK)
        • -
      • __HAL_RCC_GET_SYSCLK_SOURCE() - updates:
        • -
          -
        • Add new RCC - Literals:
          • -
            -
          • RCC_SYSCLKSOURCE_STATUS_HSI
            • -
          • RCC_SYSCLKSOURCE_STATUS_HSE
            • -
          • RCC_SYSCLKSOURCE_STATUS_PLLCLK
            • -
          • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
            • -
          -
        •  Update - - - - macro description to refer - to the literals above -
          • -
        -
      -
    • HAL - - - - PWR update
      • -
        -
      • Add new - define PWR_WAKEUP_PIN2
        • -
      • Add new API - to Control/Get VOS bits - of CR register
        • -
          -
        • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
          • -
        • HAL_PWREx_GetVoltageRange()
          • -
        -
      • __HAL_PWR_ - VOLTAGESCALING_CONFIG(): Implement - workaround to cover VOS - limitation delay when PLL is - enabled after setting the VOS - configuration
        • -
      -
    • HAL - - - - GPIO update
      • -
        -
      • Add the new - Alternate functions literals - related to remap for SPI, - - - - USART, I2C, SPDIFRX, CEC - and QSPI
        • -
      • HAL_GPIO_DeInit(): - - - - Update to check if GPIO - Pin x is already used in EXTI - mode on another GPIO Port - before De-Initialize the EXTI - registers
        • -
      -
    • HAL - - - - FLASH update
      • -
        -
      • __HAL_FLASH_INSTRUCTION_CACHE_RESET() - macro: update to reset -  ICRST bit in - the ACR register after - setting it.
        • -
      • __HAL_FLASH_DATA_CACHE_RESET() macro: - - - - - update to reset -  DCRST bit in the ACR - register after setting it.
        • -
      -
    • HAL - - - - ADC update
      • -
        -
      • Add new - literal: ADC_SOFTWARE_START to - be used as possible value for - the ExternalTrigConv - parameter in the ADC_InitTypeDef - structure to select the ADC - software trigger mode.
        • -
      • IS_ADC_CHANNEL() - macro update to don't assert - stop the ADC_CHANNEL_TEMPSENSOR - value
        • -
      • HAL_ADC_PollForConversion(): update to - manage particular case when - ADC configured in DMA mode and - ADC sequencer with several - ranks and polling for end of - each conversion
        • -
      • HAL_ADC_Start()/HAL_ADC_Start_IT() - /HAL_ADC_Start_DMA() - - - - - update:
        • -
          -
        • unlock the - process before starting the - ADC software conversion.
          • -
        • Optimize - the ADC stabilization delays
          • -
        -
      • __HAL_ADC_GET_IT_SOURCE() - update macro implementation
        • -
      • Add more - details in 'How to use this - driver' section
        • -
      -
    • HAL - - - - DAC update
      • -
        -
      • Add new macro - to check if the specified DAC - interrupt source is enabled or - disabled
        • -
          -
        • __HAL_DAC_GET_IT_SOURCE()
          • -
        -
      • HAL_DACEx_TriangleWaveGeneration() update to - use DAC CR bit mask definition
        • -
      • HAL_DACEx_NoiseWaveGeneration() update to - use DAC CR bit mask definition
        • -
      -
    • HAL - - - - CAN update
      • -
        -
      • CanTxMsgTypeDef structure: - update to use uint8_t Data[8] - - - - - instead of - uint32_t Data[8]
        • -
      • CanRxMsgTypeDef structure: - update to use uint8_t Data[8] - instead of - uint32_t Data[8]
        • -
      -
    -
      -
    • HAL - - - - RTC update
      • -
        -
      • Update to - use CMSIS mask definition - instead of hardcoded values (EXTI_IMR_IM17, - EXTI_IMR_IM19..)
        • -
      -
    • HAL - - - - LTDC update
      • -
        -
      • LTDC_SetConfig() update to - allow the drawing - of partial bitmap in - active layer.
        • -
      -
    • HAL - - - - USART update
      • -
        -
      • HAL_USART_Init() fix USART - baud rate configuration - issue: USART baud rate is - twice Higher than expected
        • -
      -
    • HAL - - - - SMARTCARD update
      • -
        -
      • HAL_SMARTCARD_Transmit_IT() update to - force the disable for the ERR - interrupt to avoid the OVR - interrupt
        • -
      • HAL_SMARTCARD_IRQHandler() - update check condition - for transmission end
        • -
      • Clean up: - remove the following - literals that aren't used in - smartcard mode
        • -
          -
        • SMARTCARD_PARITY_NONE
          • -
        • SMARTCARD_WORDLENGTH_8B
          • -
        • SMARTCARD_STOPBITS_1
          • -
        • SMARTCADR_STOPBITS_2
          • -
        -
      -
    • HAL - - - - SPI update
      • -
        -
      • HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TarnsmitReceive_DMA() - update to unlock - the process before - enabling the SPI peripheral
        • -
      • HAL_SPI_Transmit_DMA() update to - manage correctly the DMA RX - stream in SPI Full duplex mode
        • -
      • Section - SPI_Exported_Functions_Group2 update - to remove duplication in *.chm - UM
        • -
      -
    • HAL - - - - CRYP update
      • -
        -
      • Update to - manage multi instance:
        • -
          -
        • Add new - parameter Instance in the CRYP_HandleTypeDef - Handle structure.
          • -
        • Add new - parameter in all HAL CRYP - macros
          • -
            -
          • example: __HAL_CRYP_ENABLE() -  updated by - __HAL_CRYP_ENABLE(__HANDLE__)
            • -
          -
        -
      -
    • HAL - - - - DCMI update
      • -
        -
      • Add an - extension - driver stm32f4xx_hal_dcmi_ex.c/h - to manage the support of new - Black and White feature -
        • -
      • Add  __weak attribute - for HAL_DCMI_Init() - function and add a new - implementation in the - extension driver to manage the - black and white configuration - only available in the  - STM32F446xx devices. -
        • -
      • Move DCMI_InitTypeDef - structure to extension driver - and add the - following new fields - related to black and white - feature: ByteSelectMode, ByteSelectStart, LineSelectMode - and LineSelectStart
        • -
      -
    • HAL - - - - PCD update
      • -
        -
      • Add the - support of LPM feature
        • -
          -
        • add PCD_LPM_StateTypeDef - enum
          • -
        • update PCD_HandleTypeDef - structure to support the LPM - feature
          • -
        • add new - functions HAL_PCDEx_ActivateLPM(), - - - - - HAL_PCDEx_DeActivateLPM() - - - - - and HAL_PCDEx_LPM_Callback() - - - - - in the - stm32f4xx_hal_pcd_ex.h/.c - files
          • -
        -
      -
    • HAL - - - - TIM update
      • -
        -
      • Add  - TIM_TIM11_SPDIFRX - - - - define
        • -
      -
    • HAL - - - - SAI update
      • -
        -
      • Add - stm32f4xx_hal_sai_ex.h/.c - files for the SAI_BlockSynchroConfig() - and the SAI_GetInputClock() - - - - - management
        • -
      • Add new - defines HAL_SAI_ERROR_AFSDET, - HAL_SAI_ERROR_LFSDET, - HAL_SAI_ERROR_CNREADY, - HAL_SAI_ERROR_WCKCFG, - HAL_SAI_ERROR_TIMEOUT in the SAI_Error_Code - group
        • -
      • Add new - defines SAI_SYNCEXT_DISABLE, - SAI_SYNCEXT_IN_ENABLE, - SAI_SYNCEXT_OUTBLOCKA_ENABLE, - SAI_SYNCEXT_OUTBLOCKB_ENABLE - for the SAI External - synchronization
        • -
      • Add new - defines SAI_I2S_STANDARD, - SAI_I2S_MSBJUSTIFIED, - SAI_I2S_LSBJUSTIFIED, - SAI_PCM_LONG and SAI_PCM_SHORT - for the SAI Supported protocol
        • -
      • Add new - defines - SAI_PROTOCOL_DATASIZE_16BIT, - SAI_PROTOCOL_DATASIZE_16BITEXTENDED, - SAI_PROTOCOL_DATASIZE_24BIT - and - SAI_PROTOCOL_DATASIZE_32BIT - for SAI protocol data size
        • -
      • Add SAI - Callback prototype definition
        • -
      • Update SAI_InitTypeDef - structure by adding new - fields: SynchroExt, - Mckdiv, - MonoStereoMode, - CompandingMode, - TriState
        • -
      • Update SAI_HandleTypeDef - structure:
        • -
          -
        • remove - uint16_t *pTxBuffPtr, - *pRxBuffPtr, - TxXferSize, - RxXferSize, - TxXferCount - and RxXferCount - and replace them - respectively by uint8_t *pBuffPtr, - uint16_t XferSize and - - - - - uint16_t XferCount
          • -
        • add mutecallback - field
          • -
        • add struct - __SAI_HandleTypeDef - *hsai field
          • -
        -
      • Remove - SAI_CLKSOURCE_PLLR and - SAI_CLOCK_PLLSRC defines
        • -
      • Add - SAI_CLKSOURCE_NA define
        • -
      • Add - SAI_AUDIO_FREQUENCY_MCKDIV - define
        • -
      • Add - SAI_SPDIF_PROTOCOL define
        • -
      • Add - SAI_SYNCHRONOUS_EXT define
        • -
      • Add new - functions HAL_SAI_InitProtocol(), - - - - - HAL_SAI_Abort(), - - - - - HAL_SAI_EnableTxMuteMode(), - - - - - HAL_SAI_DisableTxMuteMode(), - - - - - HAL_SAI_EnableRxMuteMode(), - - - - - HAL_SAI_DisableRxMuteMode()
        • -
      • Update HAL_SAI_Transmit(), - - - - - HAL_SAI_Receive(), - - - - - HAL_SAI_Transmit_IT(), - - - - - HAL_SAI_Receive_IT(), - - - - - HAL_SAI_Transmit_DMA(), - - - - - HAL_SAI_Receive_DMA() - - - - - functions to use uint8_t *pData - instead of uint16_t *pData - --> This update is mainly - impacting the compatibility - with previous driver - version.
        • -
      -
    • HAL - - - - I2S update
      • -
        -
      • Split the - following - functions between Generic - and Extended API based on full - duplex management and add the - attribute __weak in the - Generic API
        • -
          -
        • HAL_I2S_Init(), -HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), HAL_I2S_DMAResume(), HAL_I2S_IRQHandle() -
          • -
        -
      • Move the - following static functions - from generic to extension driver
        • -
          -
        •  I2S_DMARxCplt() - and I2S_DMATxCplt()
          • -
        -
      • Remove static - attribute from I2S_Transmit_IT() - and I2S_Receive_IT() functions
        • -
      • Move I2SxEXT() - macro to extension file
        • -
      • Add - I2S_CLOCK_PLLR and - I2S_CLOCK_PLLSRC defines for - I2S clock source
        • -
      • Add new - function I2S_GetInputClock()
        • -
      -
    • HAL - - - - LL FMC update
      • -
        -
      • Add WriteFifo - and PageSize - fields in the FMC_NORSRAM_InitTypeDef - structure
        • -
      • Add - FMC_PAGE_SIZE_NONE, - FMC_PAGE_SIZE_128, - FMC_PAGE_SIZE_256, - FMC_PAGE_SIZE_1024, - FMC_WRITE_FIFO_DISABLE, - FMC_WRITE_FIFO_ENABLE defines
        • -
      • Update FMC_NORSRAM_Init(), - - - - - FMC_NORSRAM_DeInit() - - - - - and FMC_NORSRAM_Extended_Timing_Init() functions
        • -
      -
    • HAL - - - - LL USB update
      • -
        -
      • Update USB_OTG_CfgTypeDef - structure to support LPM, lpm_enable - field added
        • -
      • Update USB_HostInit() - and USB_DevInit() - - - - - functions to support the VBUS - Sensing B activation
        • -
      -
    -

    V1.2.0 - - - - / 26-December-2014

    -

    Main Changes

    -
      -
    • Maintenance - - - - release to fix known defects - and enhancements implementation
      • -
    -
      -
    • Macros - - - - and literals renaming to - ensure compatibles across - STM32 series, - backward compatibility - maintained thanks to new added - file stm32_hal_legacy.h under - - - - /Inc/Legacy
      • -
    • Add - *.chm UM for all drivers, a UM - is provided for each superset RPN
      • -
    • Update - - - - drivers to be C++ compliant
      • -
    • Several - - - - update on source code - formatting, for better UM - generation (i.e. - Doxygen - tags updated)
      • -
    • Two - - - - changes done on the HAL - requires an update on the - application code based on HAL - V1.1.0
      • -
        -
      • LSI_VALUE constant has - been corrected in - stm32f4xx_hal_conf.h file, its - value changed from 40 KHz - to 32 KHz
        • -
      • UART, USART, - IRDA and SMARTCARD - (referenced as PPP - here below) drivers: - in DMA transmit process, the - code has been updated to avoid - waiting on TC flag under DMA - ISR, PPP TC interrupt - is used instead. Below the - update to be done on user - application:
        • -
          -
        • Configure - and enable the USART IRQ in - HAL_PPP_MspInit() - function
          • -
        • In - stm32f4xx_it.c file, PPP_IRQHandler() - function: add a call to HAL_PPP_IRQHandler() - - - - function
          • -
        -
      -
    -
      -
    • HAL - - - - generic - update
      • -
    -
      -
        -
      • stm32f4xx_hal_def.h
        • -
          -
        • Update NULL - definition to fix C++ - compilation issue
          • -
        • Add UNUSED() - macro
          • -
        • Add a new - define __NOINLINE to be used - for the no inline code - independent from tool chain
          • -
        -
      • stm32f4xx_hal_conf_template.h
        • -
          -
        • LSI_VALUE constant - has been corrected, - its value changed from 40 KHz - to 32 KHz
          • -
        -
      -
    -
      -
        -
      • Update all - macros and literals naming to - be uper - case
        • -
      • ErrorCode parameter in - PPP_HandleTypeDef - structure updated - to uint32_t instead - of enum HAL_PPP_ErrorTypeDef
        • -
      • Remove the - - - - unused FLAG and IT assert macros
        • -
      -
    • HAL - - - - ADC update
      • -
        -
      • Fix temperature - - - - - sensor channel configuration - issue for STM32F427/437xx - - - - -  and STM32F429/439xx - - - - devices
        • -
      -
    • HAL - - - - DAC update
      • -
        -
      • HAL_DAC_ConfigChannel(): update the - access to the DAC peripheral - registers via the hdac - handle instance
        • -
      • HAL_DAC_IRQHandler(): update to - check on both DAC_FLAG_DMAUDR1 - and DAC_FLAG_DMAUDR2
        • -
      • HAL_DACEx_NoiseWaveGenerate(): update to - reset DAC CR register before - setting the new DAC - configuration
        • -
      • HAL_DACEx_TriangleWaveGenerate(): update to - reset DAC CR register before - setting the new DAC - configuration
        • -
      -
    • HAL - - - - CAN update
      • -
        -
      • Unlock the - CAN process when communication - error occurred
        • -
      -
    • HAL - - - - CORTEX update
      • -
        -
      • Add new macro - IS_NVIC_DEVICE_IRQ() - to check on negative values of - IRQn - parameter
        • -
      -
    -

    §  - - - - - HAL CRYP update

    -
      -
        -
      • HAL_CRYP_DESECB_Decrypt_DMA(): fix the - inverted pPlainData - and pCypherData - parameters issue
        • -
      • CRYPEx_GCMCCM_SetInitVector(): remove - the IVSize - parameter as the key length - 192bits and 256bits are not - supported by this version
        • -
      • Add restriction for - - - - - the CCM Encrypt/Decrypt API's - that only DataType - equal to 8bits is supported
        • -
      • HAL_CRYPEx_AESGCM_Finish():
        • -
          -
        • Add restriction - - - - - that the implementation is - limited to 32bits inputs - data length  (Plain/Cyphertext, - - - - Header) compared with GCM stadards - specifications (800-38D)
          • -
        • Update Size - parameter on 32bits instead - of 16bits
          • -
        • Fix issue - with 16-bit Data Type: - update to use intrinsic __ROR() - instead of __REV16()
          • -
        -
      -
    -

    §  - - - - - HAL DCMI update

    -
      -
        -
      • HAL_DCMI_ConfigCROP(): Invert - assert macros to check Y0 and - Ysize - parameters
        • -
      -
    -

    §  - - - - - HAL DMA update

    -
      -
        -
      • HAL_DMA_Init(): Update to - - - - - clear the DBM bit in the - SxCR - register before setting the - new configuration
        • -
      • DMA_SetConfig(): - add to clear the DBM - bit in the SxCR - register
        • -
      -
    -

    §  - - - - - HAL FLASH update

    -
      -
        -
      • Add "HAL_" - prefix in the defined values - for the FLASH error code
        • -
          -
        • Example: FLASH_ERROR_PGP - renamed by HAL_FLASH_ERROR_PGP
          • -
        -
      • Clear the - - - - Flash ErrorCode - in the FLASH_WaitForLastOperation() - function
        • -
      • Update FLASH_SetErrorCode() - function to use "|=" - operant to update the Flash ErrorCode - parameter in the FLASH handle
        • -
      • IS_FLASH_ADDRESS(): Update the - macro check using '<=' - condition instead of '<'
        • -
      • IS_OPTIONBYTE(): Update the - macro check using '<=' - condition instead of '<'
        • -
      • Add "FLASH_" - - - - - prefix in the defined values - of FLASH Type Program - parameter
        • -
          -
        • Example: TYPEPROGRAM_BYTE - renamed by FLASH_TYPEPROGRAM_BYTE
          • -
        -
      • Add "FLASH_" - - - - - prefix in the defined values - of FLASH Type Erase parameter
        • -
          -
        • Example: TYPEERASE_SECTORS - renamed by FLASH_TYPEERASE_SECTORS
          • -
        -
      • Add "FLASH_" - - - - - prefix in the defined values - of FLASH Voltage Range - parameter
        • -
          -
        • Example: VOLTAGE_RANGE_1 - renamed by FLASH_VOLTAGE_RANGE_1
          • -
        -
      • Add "OB_" - - - - - prefix in the defined values - of FLASH WRP State parameter
        • -
          -
        • Example: WRPSTATE_ENABLE - renamed by OB_WRPSTATE_ENABLE
          • -
        -
      • Add "OB_" - - - - - prefix in the defined values - of the FLASH PCROP State - parameter
        • -
          -
        • PCROPSTATE_DISABLE  - updated by OB_PCROP_STATE_DISABLE
          • -
        • PCROPSTATE_ENABLE -  updated by OB_PCROP_STATE_ENABLE
          • -
        -
      • Change - "OBEX" prefix by - "OPTIONBYTE" prefix in these - defines:
        • -
          -
        • OBEX_PCROP - - - - by OPTIONBYTE_PCROP 
          • -
        • OBEX_BOOTCONFIG - - - - by OPTIONBYTE_BOOTCONFIG
          • -
        -
      -
    -

    §  - - - - - HAL ETH update

    -
      -
        -
      • Fix macros - naming typo
        • -
      -
    -
      -
        -
          -
        • Update - __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() - by - __HAL_ETH_EXTI_SET_RISING_EDGE_TRIGGER()
          • -
        • Update - __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() -by __HAL_ETH_EXTI_SET_FALLING_EDGE_TRIGGER()
          • -
        -
      -
    -

    §  - - - - - HAL PWR update

    -
      -
        -
      • Add new API - to manage SLEEPONEXIT and - SEVONPEND bits of SCR register
        • -
          -
        • HAL_PWR_DisableSleepOnExit()
          • -
        • HAL_PWR_EnableSleepOnExit()
          • -
        • HAL_PWR_EnableSEVOnPend()
          • -
        • HAL_PWR_DisableSEVOnPend()
          • -
        -
      • HAL_PWR_EnterSTOPMode()
        • -
          -
        • Update to - - - - clear the CORTEX SLEEPDEEP - bit of SCR register - before entering in sleep mode
          • -
        • Update - usage of __WFE() - in low power entry function: - if there is a pending event, - calling __WFE() will not - enter the CortexM4 core to - sleep mode. The solution is - to made the call below; the - first __WFE() - is always ignored and clears - the event if one was already - pending, the second is - always applied
          • -
        -
      -
    -
    -

    __SEV()
    -     __WFE()
    -     __WFE()

    -
    -
      -
        -
      • Add - new PVD configuration modes
        • -
          -
        • PWR_PVD_MODE_NORMAL
          • -
        • PWR_PVD_MODE_EVENT_RISING 
          • -
        • PWR_PVD_MODE_EVENT_FALLING
          • -
        • PWR_PVD_MODE_EVENT_RISING_FALLING
          • -
        -
      • Add new - macros to manage PVD Trigger
        • -
          -
        • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()
          • -
        • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(
          • -
        • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()
          • -
        • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
          • -
        • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
          • -
        • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
          • -
        -
      • PVD macros:
        • -
          -
        • Remove the - __EXTILINE__ parameter
          • -
        • Update to - use prefix "__HAL_PWR_PVD_" - instead of  prefix - "__HAL_PVD"
          • -
        -
      -
    -
      -
        -
      • Rename HAL_PWR_PVDConfig() - by HAL_PWR_ConfigPVD()
        • -
      • Rename HAL_PWREx_ActivateOverDrive() - by HAL_PWREx_EnableOverDrive() - - - - -
        • -
      • Rename HAL_PWREx_DeactivateOverDrive() - by HAL_PWREx_DisableOverDrive() - - - - -
        • -
      -
    • HAL - - - - GPIO update
      • -
        -
      • HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call - to the CMSIS assert macro - to check GPIO instance: - IS_GPIO_ALL_INSTANCE() 
        • -
      • HAL_GPIO_WritePin(): update to - write in BSRR register
        • -
      • Rename GPIO_GET_SOURCE() - by GET_GPIO_INDEX() and - - - - move this later to file  - stm32f4xx_hal_gpio_ex.h
        • -
      • Add new - define for alternate function - GPIO_AF5_SPI3 for - STM32F429xx/439xx and - STM32F427xx/437xx devices
        • -
      -
    • HAL - - - - HASH update
      • -
        -
      • HAL_HASH_MD5_Start_IT(): - - - - - fix input - address management issue
        • -
      -
    • HAL - - - - RCC update
      • -
        -
      • Rename the - following Macros
        • -
          -
        • __PPP_CLK_ENABLE()  - - - - - by - __HAL_RCC_PPP_CLK_ENABLE()
          • -
        • __PPP_CLK_DISABLE()  - - - - - by - __HAL_RCC_PPP_CLK_DISABLE()
          • -
        • __PPP_FORCE_RESET()  - - - - - by - __HAL_RCC_PPP_FORCE_RESET()
          • -
        • __PPP_RELEASE_RESET()  - - - - - by - __HAL_RCC_PPP_RELEASE_RESET()
          • -
        • __PPP_CLK_SLEEP_ENABLE() - by - __HAL_RCC_PPP_CLK_SLEEP_ENABLE()
          • -
        • __PPP_CLK_SLEEP_DISABLE() - by - __HAL_RCC_PPP_CLK_SLEEP_DISABLE()
          • -
        -
      • IS_RCC_PLLSAIN_VALUE() - macro: update the check - condition
        • -
      • Add - description of RCC known Limitations
        • -
      • Rename HAL_RCC_CCSCallback() - by HAL_RCC_CSSCallback()
        • -
      • HAL_RCC_OscConfig() fix - issues: 
        • -
          -
        • Remove the - disable of HSE - oscillator when - HSE_BYPASS is used as - system clock source or as - PPL clock source
          • -
        • Add a check - on HSERDY flag - when HSE_BYPASS is - selected as new state - for HSE oscillator.
          • -
        -
      • Rename - __HAL_RCC_I2SCLK() - by __HAL_RCC_I2S_Config()
        • -
      -
    -

    §  - - - - - HAL I2S update

    -
      -
        -
      • HAL_I2S_Init(): add check - on I2S instance - using CMSIS macro IS_I2S_ALL_INSTANCE() 
        • -
      • HAL_I2S_IRQHandler() - update for compliancy w/ C++
        • -
      • Add use - of tmpreg - variable in __HAL_I2S_CLEAR_OVRFLAG() - and __HAL_I2S_CLEAR_UDRFLAG() - macro for compliancy with C++
        • -
      • HAL_I2S_GetError(): update to - return uint32_t instead of - HAL_I2S_ErrorTypeDef - enumeration
        • -
      -
    -

    §  - - - - - HAL I2C update

    -
      -
        -
      • Update to - - - - - clear the POS bit in the - CR1 register at the end - of HAL_I2C_Master_Read_IT() - and HAL_I2C_Mem_Read_IT() - process
        • -
      • Rename - HAL_I2CEx_DigitalFilter_Config()  - - - - by - HAL_I2CEx_ConfigDigitalFilter() -
        • -
      • Rename - HAL_I2CEx_AnalogFilter_Config()  - - - - by - HAL_I2CEx_ConfigAnalogFilter() -
        • -
      • Add use - of tmpreg - variable in __HAL_I2C_CLEAR_ADDRFLAG() - and __HAL_I2C_CLEAR_STOPFLAG() - macro for compliancy with - C++
        • -
      -
    • HAL - - - - IrDA update
      • -
        -
      • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, IrDA TC - interrupt is used instead. - Below the update to be done on - user application:
        • -
          -
        • Configure - and enable the USART IRQ in - HAL_IRDA_MspInit() - function
          • -
        • In - stm32f4xx_it.c file, UASRTx_IRQHandler() - function: add a call to HAL_IRDA_IRQHandler() - - - - function
          • -
        -
      • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under IRDA ISR, IrDA TC - interrupt is used instead. No - impact on user application
        • -
      • Rename - Macros: add prefix "__HAL"
        • -
          -
        • __IRDA_ENABLE() - by __HAL_IRDA_ENABLE()
          • -
        • __IRDA_DISABLE() - by __HAL_IRDA_DISABLE()
          • -
        -
      • Add new user - macros to manage the sample - method feature
        • -
          -
        • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE()
          • -
        • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE()
          • -
        -
      • HAL_IRDA_Transmit_IT(): update to - remove the enable of the - parity error interrupt
        • -
      • Add use - of tmpreg - variable in __HAL_IRDA_CLEAR_PEFLAG() - macro for compliancy with - C++
        • -
      • HAL_IRDA_Transmit_DMA() update to - follow the - right procedure - "Transmission using DMA"  - in the reference manual
        • -
          -
        • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
          • -
        -
      -
    • HAL - - - - IWDG update
      • -
        -
      • Rename the - defined IWDG keys: 
        • -
          -
        • KR_KEY_RELOAD - - - - by IWDG_KEY_RELOAD
          • -
        • KR_KEY_ENABLE - - - - by IWDG_KEY_ENABLE
          • -
        • KR_KEY_EWA - by - IWDG_KEY_WRITE_ACCESS_ENABLE
          • -
        • KR_KEY_DWA - by - IWDG_KEY_WRITE_ACCESS_DISABLE
          • -
        -
      •  Add new - macros - __HAL_IWDG_RESET_HANDLE_STATE() - and - __HAL_IWDG_CLEAR_FLAG() 
        • -
      • Update - __HAL_IWDG_ENABLE_WRITE_ACCESS() - and - __HAL_IWDG_DISABLE_WRITE_ACCESS() - as private macro
        • -
      -
    -

    §  - - - - - HAL SPI update

    -
      -
        -
      • HAL_SPI_TransmitReceive_DMA() update to - remove the  DMA Tx Error - Callback initialization when - SPI RxOnly - mode is selected
        • -
      • Add use of UNUSED(tmpreg) - in __HAL_SPI_CLEAR_MODFFLAG(), - __HAL_SPI_CLEAR_OVRFLAG(), - __HAL_SPI_CLEAR_FREFLAG() to - fix "Unused variable" warning - with TrueSTUDIO.
        • -
      • Rename - Literals: remove "D" from - "DISABLED" and "ENABLED"
        • -
          -
        • SPI_TIMODE_DISABLED by - - - - - SPI_TIMODE_DISABLE
          • -
        • SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE
          • -
        • SPI_CRCCALCULATION_DISABLED - by - - - - -  SPI_CRCCALCULATION_DISABLE
          • -
        • SPI_CRCCALCULATION_ENABLED - by - - - - -  SPI_CRCCALCULATION_ENABLE
          • -
        -
      • Add use - of tmpreg - variable in __HAL_SPI_CLEAR_MODFFLAG(), - - - - - __HAL_SPI_CLEAR_FREFLAG() and - __HAL_SPI_CLEAR_OVRFLAG() - macros for compliancy - with C++
        • -
      -
    -

    §  - - - - - HAL SDMMC update

    -
      -
        -
      • IS_SDIO_ALL_INSTANCE() -  macro moved to CMSIS - files
        • -
      -
    • HAL - - - - LTDC update
      • -
        -
      • HAL_LTDC_ConfigCLUT: optimize - the function when pixel format -is LTDC_PIXEL_FORMAT_AL44 
        • -
          -
        • Update the - size of color look up table - to 16 instead of 256 when - the pixel format - is LTDC_PIXEL_FORMAT_AL44 -
          • -
        -
      -
    • HAL - - - - NAND update
      • -
        -
      • Rename NAND - Address structure to NAND_AddressTypeDef - instead of NAND_AddressTypedef
        • -
      • Update the - used algorithm of these functions
        • -
          -
        • HAL_NAND_Read_Page()
          • -
        • HAL_NAND_Write_Page()
          • -
        • HAL_NAND_Read_SpareArea()
          • -
        • HAL_NAND_Write_SpareArea()
          • -
        -
      • HAL_NAND_Write_Page(): move - initialization of tickstart - before while loop
        • -
      • HAL_NAND_Erase_Block(): add whait - until NAND status is ready - before exiting this function
        • -
      -
    • HAL - - - - NOR update
      • -
        -
      • Rename NOR - Address structure to NOR_AddressTypeDef - instead of NOR_AddressTypedef
        • -
      • NOR Status - literals renamed
        • -
          -
        • NOR_SUCCESS - by HAL_NOR_STATUS_SUCCESS
          • -
        • NOR_ONGOING - by HAL_NOR_STATUS_ONGOING
          • -
        • NOR_ERROR - by HAL_NOR_STATUS_ERROR
          • -
        • NOR_TIMEOUT - by HAL_NOR_STATUS_TIMEOUT
          • -
        -
      • HAL_NOR_GetStatus() update to - fix Timeout issue - and exit from waiting - loop when timeout occurred
        • -
      -
    • HAL - - - - PCCARD update
      • -
        -
      • Rename PCCARD - Address structure to HAL_PCCARD_StatusTypeDef - instead of CF_StatusTypedef
        • -
      • PCCARD Status - literals renamed
        • -
          -
        • CF_SUCCESS - by HAL_PCCARD_STATUS_SUCCESS
          • -
        • CF_ONGOING - by HAL_PCCARD_STATUS_ONGOING
          • -
        • CF_ERROR - by HAL_PCCARD_STATUS_ERROR
          • -
        • CF_TIMEOUT - by HAL_PCCARD_STATUS_TIMEOUT
          • -
        -
      • Update "CF" - by "PCCARD" in functions, - literals - and macros
        • -
      -
    • HAL - - - - PCD update
      • -
        -
      • Rename functions
        • -
          -
        • HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup()
          • -
        • HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup()
          • -
        -
      • Rename literals
        • -
          -
        • USB_FS_EXTI_TRIGGER_RISING_EDGE - - - - - by - USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
          • -
        • USB_FS_EXTI_TRIGGER_FALLING_EDGE - - - - - by - USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
          • -
        • USB_FS_EXTI_TRIGGER_BOTH_EDGE() - by - USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
          • -
        • USB_HS_EXTI_TRIGGER_RISING_EDGE - - - - - by - USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 
          • -
        • USB_HS_EXTI_TRIGGER_FALLING_EDGE - - - - - by - USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
          • -
        • USB_HS_EXTI_TRIGGER_BOTH_EDGE - - - - - by - USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
          • -
        • USB_HS_EXTI_LINE_WAKEUP - - - - - by - USB_OTG_HS_EXTI_LINE_WAKEUP
          • -
        • USB_FS_EXTI_LINE_WAKEUP - - - - - by - USB_OTG_FS_EXTI_LINE_WAKEUP
          • -
        -
      • Rename USB - EXTI macros (FS, HS - - - - referenced as SUBBLOCK - here below)
        • -
          -
        • __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() -  by  - __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()  
          • -
        • __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT()
          • -
        • __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG() 
          • -
        • __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG()
          • -
        • __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE()
          • -
        • __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
          • -
        • __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
          • -
        • __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT()  - - - - - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GENERATE_SWIT()                                       -
          • -
        -
      -
    -
      -
    • HAL - - - - RNG update
      • -
        -
      • Add new functions
        • -
          -
        • HAL_RNG_GenerateRandomNumber(): to - generate a 32-bits random - number, - return - random value in argument and - return HAL status.
          • -
        • HAL_RNG_GenerateRandomNumber_IT(): to -  start generation of - the 32-bits random - number, user should call - the HAL_RNG_ReadLastRandomNumber() - - - - - function under the HAL_RNG_ReadyCallback() - - - - to get the generated random - value.
          • -
        • HAL_RNG_ReadLastRandomNumber(): to - return the last random value - stored in the RNG handle
          • -
        -
      • HAL_RNG_GetRandomNumber(): return - value update (obsolete), - replaced by HAL_RNG_GenerateRandomNumber()
        • -
      • HAL_RNG_GetRandomNumber_IT(): wrong - implementation (obsolete), - replaced by HAL_RNG_GenerateRandomNumber_IT()
        • -
      • __HAL_RNG_CLEAR_FLAG() - macro (obsolete), replaced by - new __HAL_RNG_CLEAR_IT() macro
        • -
      • Add new - define for RNG ready - interrupt:  RNG_IT_DRDY
        • -
      -
    • HAL - - - - RTC update
      • -
        -
      • HAL_RTC_GetTime() and HAL_RTC_GetDate(): - - - - - add the comment below
        • -
      -
    -
    -
    -

      - - - - - * @note You must call HAL_RTC_GetDate() - after HAL_RTC_GetTime() - - - - - to unlock the values
    -       - - - - - * in the higher-order - calendar shadow registers to - ensure consistency between - the time and date values.
    -       - - - - - * Reading RTC current time - locks the values in calendar - shadow registers until - Current date is read. 

    -
    -
    -
      -
        -
      • Rename - literals: add prefix "__HAL"
        • -
          -
        • FORMAT_BIN by HAL_FORMAT_BIN
          • -
        • FORMAT_BCD - by HAL_FORMAT_BCD
          • -
        -
      • Rename macros - (ALARM, WAKEUPTIMER and - TIMESTAMP referenced - as SUBBLOCK here - below)
        • -
          -
        • __HAL_RTC_EXTI_ENABLE_IT() - by  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT()
          • -
        • __HAL_RTC_EXTI_DISABLE_IT() - by  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_IT()
          • -
        • __HAL_RTC_EXTI_CLEAR_FLAG() - by  __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG()
          • -
        • __HAL_RTC_EXTI_GENERATE_SWIT() - by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT()
          • -
        -
      • Add new - macros (ALARM, - WAKEUPTIMER and TAMPER_TIMESTAMP - - - - referenced as SUBBLOCK - here below)
        • -
          -
        • __HAL_RTC_SUBBLOCK_GET_IT_SOURCE() 
          • -
        • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT()
          • -
        • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT()
          • -
        • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE()
          • -
        • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE()
          • -
        • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE()
          • -
        • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE()
          • -
        •  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE()
          • -
        •  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE()
          • -
        •  __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG()
          • -
        -
      -
    • HAL - - - - SAI update
      • -
        -
      • Update - SAI_STREOMODE by SAI_STEREOMODE
        • -
      • Update FIFO - status Level defines in upper - case
        • -
      • Rename - literals: remove "D" from - "DISABLED" and "ENABLED"
        • -
          -
        • SAI_OUTPUTDRIVE_DISABLED - - - - -  by - SAI_OUTPUTDRIVE_DISABLE
          • -
        • SAI_OUTPUTDRIVE_ENABLED - - - - -  by - SAI_OUTPUTDRIVE_ENABLE
          • -
        • SAI_MASTERDIVIDER_ENABLED  by - SAI_MASTERDIVIDER_ENABLE
          • -
        • SAI_MASTERDIVIDER_DISABLED  by - SAI_MASTERDIVIDER_DISABLE
          • -
        -
      -
    -
      -
    • HAL - - - - SD update
      • -
        -
      • Rename - SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS
        • -
      • SD_PowerON() updated to - add 1ms required power up - waiting time before starting - the SD initialization sequence
        • -
      • SD_DMA_RxCplt()/SD_DMA_TxCplt(): - - - - - add a call to - HAL_DMA_Abort()
        • -
      • HAL_SD_ReadBlocks() update to - set the defined - DATA_BLOCK_SIZE as SDIO DataBlockSize - parameter
        • -
      • HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() - update to call the HAL_DMA_Start_IT() - - - - function with DMA Datalength - set to BlockSize/4  - - - - - as the DMA is - configured in word 
        • -
      -
    • HAL - - - - SMARTCARD update 
      • -
        -
      • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, SMARTCARD - TC interrupt is used instead. - Below the update to be done on - user application:
        • -
          -
        • Configure - and enable the USART IRQ in - HAL_SAMRTCARD_MspInit() - function
          • -
        • In - stm32f4xx_it.c file, UASRTx_IRQHandler() - function: add a call to HAL_SMARTCARD_IRQHandler() - - - - - function
          • -
        -
      • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under SMARTCARD - ISR, SMARTCARD TC - interrupt is used instead. No - impact on user application
        • -
      • Rename - macros: add prefix "__HAL"
        • -
          -
        • __SMARTCARD_ENABLE() - by __HAL_SMARTCARD_ENABLE()
          • -
        • __SMARTCARD_DISABLE() - by __HAL_SMARTCARD_DISABLE()
          • -
        • __SMARTCARD_ENABLE_IT() - by - __HAL_SMARTCARD_ENABLE_IT()
          • -
        • __SMARTCARD_DISABLE_IT() - by - __HAL_SMARTCARD_DISABLE_IT()
          • -
        • __SMARTCARD_DMA_REQUEST_ENABLE() - by - __HAL_SMARTCARD_DMA_REQUEST_ENABLE()
          • -
        • __SMARTCARD_DMA_REQUEST_DISABLE() - by - __HAL_SMARTCARD_DMA_REQUEST_DISABLE()
          • -
        -
      • Rename - literals: remove "D" from - "DISABLED" and "ENABLED"
        • -
          -
        • SMARTCARD_NACK_ENABLED by - - - - - SMARTCARD_NACK_ENABLE
          • -
        • SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE
          • -
        -
      • Add new user - macros to manage the sample - method feature
        • -
          -
        • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE()
          • -
        • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE()
          • -
        -
      • Add use - of tmpreg - variable in - __HAL_SMARTCARD_CLEAR_PEFLAG() - macro for compliancy with - C++
        • -
      • HAL_SMARTCARD_Transmit_DMA() update to - follow the - right procedure - "Transmission using DMA"  - in the reference manual
        • -
          -
        • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
          • -
        -
      -
    • HAL - - - - TIM update
      • -
        -
      • Add - TIM_CHANNEL_ALL as possible - value for all Encoder - Start/Stop APIs Description
        • -
      • HAL_TIM_OC_ConfigChannel() remove call - to IS_TIM_FAST_STATE() assert - macro
        • -
      • HAL_TIM_PWM_ConfigChannel() add a call - to IS_TIM_FAST_STATE() assert - macro to check the OCFastMode - parameter
        • -
      • HAL_TIM_DMADelayPulseCplt() Update to - set the TIM Channel before to - call  HAL_TIM_PWM_PulseFinishedCallback()
        • -
      • HAL_TIM_DMACaptureCplt() update to - set the TIM Channel before to - call  HAL_TIM_IC_CaptureCallback()
        • -
      • TIM_ICx_ConfigChannel() update - to fix Timer CCMR1 register - corruption when setting ICFilter - parameter
        • -
      • HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() - update to abort the DMA - transfer for the specifc - TIM channel
        • -
      • Add new - function for TIM Slave - configuration in IT mode: - HAL_TIM_SlaveConfigSynchronization_IT() 
        • -
      • HAL_TIMEx_ConfigBreakDeadTime() add an - assert check on Break & DeadTime - parameters values
        • -
      • HAL_TIMEx_OCN_Start_IT() add the - enable of Break Interrupt for - all output modes
        • -
      • Add new - macros to ENABLE/DISABLE URS - bit in TIM CR1 register:
        • -
          -
        • __HAL_TIM_URS_ENABLE()
          • -
        • __HAL_TIM_URS_DISABLE()
          • -
        -
      • Add new macro - for TIM Edge modification: - __HAL_TIM_SET_CAPTUREPOLARITY()
        • -
      -
    • HAL - - - - UART update
      • -
        -
      • Add IS_LIN_WORD_LENGTH() - and - IS_LIN_OVERSAMPLING()  - macros: to check respectively - WordLength - and OverSampling - parameters in LIN mode
        • -
      • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, UART TC - interrupt is used instead. - Below the update to be done on - user application:
        • -
          -
        • Configure - and enable the USART IRQ in - HAL_UART_MspInit() - function
          • -
        • In - stm32f4xx_it.c file, USARTx_IRQHandler() - function: add a call to HAL_UART_IRQHandler() - - - - function
          • -
        -
      • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under UART ISR, UART - TC interrupt is used instead. - No impact on user application
        • -
      • Rename - macros:
        • -
          -
        • __HAL_UART_ONEBIT_ENABLE() - by - __HAL_UART_ONE_BIT_SAMPLE_ENABLE()
          • -
        • __HAL_UART_ONEBIT_DISABLE() - by - __HAL_UART_ONE_BIT_SAMPLE_DISABLE()
          • -
        -
      • Rename - literals:
        • -
          -
        • UART_WAKEUPMETHODE_IDLELINE by - - - - - UART_WAKEUPMETHOD_IDLELINE
          • -
        • UART_WAKEUPMETHODE_ADDRESSMARK by -UART_WAKEUPMETHOD_ADDRESSMARK
          • -
        -
      • Add use - of tmpreg - variable in __HAL_UART_CLEAR_PEFLAG() - macro for compliancy with - C++
        • -
      • HAL_UART_Transmit_DMA() update to - follow the right procedure - "Transmission using DMA" in - the reference manual
        • -
          -
        • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
          • -
        -
      -
    • HAL - - - - USART update
      • -
        -
      • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, USART TC - interrupt is used instead. - Below the update to be done on - user application:
        • -
          -
        • Configure - and enable the USART IRQ in - HAL_USART_MspInit() - function
          • -
        • In - stm32f4xx_it.c file, USARTx_IRQHandler() - function: add a call to HAL_USART_IRQHandler() - - - - - function
          • -
        -
      • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under USART ISR, - USART TC interrupt is used - instead. No impact on user - application
        • -
      • HAL_USART_Init() update - to enable the USART - oversampling by 8 by default - in order to reach max USART - frequencies
        • -
      • USART_DMAReceiveCplt() update - to set the new USART state - after checking on the - old state
        • -
      • HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() - update to - follow the - right procedure - "Transmission using DMA"  - in the reference manual
        • -
          -
        • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
          • -
        -
      • Rename - macros:
        • -
          -
        • __USART_ENABLE() - by __HAL_USART_ENABLE()
          • -
        • __USART_DISABLE() - by __HAL_USART_DISABLE()
          • -
        • __USART_ENABLE_IT() - by __HAL_USART_ENABLE_IT()
          • -
        • __USART_DISABLE_IT() - by __HAL_USART_DISABLE_IT()
          • -
        -
      • Rename - literals: remove "D" from - "DISABLED" and "ENABLED"
        • -
          -
        • USART_CLOCK_DISABLED by - - - - - USART_CLOCK_DISABLE
          • -
        • USART_CLOCK_ENABLED by - - - - - USART_CLOCK_ENABLE
          • -
        • USARTNACK_ENABLED - - - - by USART_NACK_ENABLE
          • -
        • USARTNACK_DISABLED - - - - by USART_NACK_DISABLE
          • -
        -
      • Add new user - macros to manage the sample - method feature
        • -
          -
        • __HAL_USART_ONE_BIT_SAMPLE_ENABLE()
          • -
        • __HAL_USART_ONE_BIT_SAMPLE_DISABLE()
          • -
        -
      • Add use - of tmpreg - variable in __HAL_USART_CLEAR_PEFLAG() - macro for compliancy with - C++
        • -
      -
    • HAL - - - - WWDG update
      • -
        -
      • Add new - parameter in - __HAL_WWDG_ENABLE_IT() - macro
        • -
      • Add new - macros to manage WWDG IT & - correction:
        • -
          -
        • __HAL_WWDG_DISABLE()
          • -
        • __HAL_WWDG_DISABLE_IT()
          • -
        • __HAL_WWDG_GET_IT()
          • -
        • __HAL_WWDG_GET_IT_SOURCE()
          • -
        -
      -
    -

    V1.1.0 - - - - / 19-June-2014

    -

    Main Changes

    -
      -
    • Add - support of STM32F411xE devices
      • -
    -
      -
    • HAL - - - - generic - update
      • -
        -
      • Enhance HAL - delay and time base implementation
        • -
          -
        • Systick timer is - used by default as source of - time base, but user can - eventually implement his - proper time base source (a general - - - - purpose - timer for example or other - time source)
          • -
        • Functions - affecting time base - configurations are declared - as __Weak to make override - possible in case of other - implementations in user - file, for more details - please refer to HAL_TimeBase - example
          • -
        -
      • Fix flag - clear procedure: use atomic - write operation "=" instead of - ready-modify-write operation - "|=" or "&="
        • -
      • Fix on - Timeout management, Timeout - value set to 0 passed to API - automatically exits the - function after checking the - flag without any wait
        • -
      • Common update - for the following - communication peripherals: - SPI, UART, USART and IRDA
        • -
          -
        • Add DMA - circular mode support
          • -
        • Remove lock - from recursive process
          • -
        -
      • Add new macro - __HAL_RESET_HANDLE_STATE to - reset a given handle state
        • -
      • Add a new - attribute for functions - executed from internal SRAM - and depending from - Compiler implementation
        • -
      • When USE_RTOS - == 1 (in - stm32l0xx_hal_conf.h), the - __HAL_LOCK() - is not defined instead of - being defined empty
        • -
      • Miscellaneous - comments and formatting update
        • -
      • stm32f4xx_hal_conf_template.h
        • -
          -
        • Add a new - define for LSI default value - LSI_VALUE
          • -
        • Add a new - define for LSE default value - LSE_VALUE
          • -
        • Add a new - define for Tick interrupt - priority TICK_INT_PRIORITY - (needed for the enhanced - time base implementation)
          • -
        -
      • Important - - - - - Note: - aliases has been added for any - API naming change, to keep - compatibility with previous version
        • -
      -
    • HAL - - - - GPIO update
      • -
    -
      -
        -
      • Add a new - macro __HAL_GPIO_EXTI_GENERATE_SWIT() - to manage the generation of - software interrupt on selected - EXTI line
        • -
      • HAL_GPIO_Init(): use - temporary variable when - modifying the registers, to - avoid unexpected transition in - the GPIO pin configuration
        • -
      • Remove - IS_GET_GPIO_PIN macro
        • -
      • Add a new - function HAL_GPIO_LockPin()
        • -
      • Private Macro - __HAL_GET_GPIO_SOURCE renamed - into GET_GPIO_SOURCE
        • -
      • Add the - support of STM32F411xx devices - - - - - : add the - new Alternate functions values - related to new remap added for - SPI, USART, I2C
        • -
      • Update the - following HAL GPIO macros - description: rename EXTI_Linex - by GPIO_PIN_x
        • -
          -
        • __HAL_GPIO_EXTI_CLEAR_IT()
          • -
        • __HAL_GPIO_EXTI_GET_IT()
          • -
        • __HAL_GPIO_EXTI_CLEAR_FLAG()
          • -
        • __HAL_GPIO_EXTI_GET_FLAG()
          • -
        -
      -
    -

    §  - - - - - HAL DMA update

    -
      -
        -
      • Fix in HAL_DMA_PollForTransfer() - to:
        • -
          -
        • set DMA - error code in case of - HAL_ERROR status
          • -
        • set HAL - Unlock before DMA state update
          • -
        -
      -
    -

    §  - - - - - HAL DMA2D - update

    -
      -
        -
      • Add - configuration of source - address in case of A8 or A4 - M2M_PFC DMA2D mode
        • -
      -
    • HAL - - - - FLASH update
      • -
    -
      -
        -
      • Functions - reorganization update, - depending on the features - supported by each STM32F4 device
        • -
      • Add new - driver - (stm32f4xx_hal_flash_ramfunc.h/.c) - to manage function executed - from RAM, these functions are - available only for STM32F411xx - Devices
        • -
          -
        • FLASH_StopFlashInterfaceClk()  : - Stop the flash interface - while System Run
          • -
        • FLASH_StartFlashInterfaceClk() : Stop the - flash interface while System - Run
          • -
        • FLASH_EnableFlashSleepMode() : Enable - the flash sleep while System - Run
          • -
        • FLASH_DisableFlashSleepMode() :  - Disable the flash sleep - while System Run
          • -
        -
      -
    -
      -
    • HAL - - - - PWR update
      • -
    -
      -
        -
      • HAL_PWR_PVDConfig(): add clear - of the EXTI trigger before new - configuration
        • -
      • Fix in HAL_PWR_EnterSTANDBYMode() - to not clear Wakeup flag - (WUF), which need to be - cleared at application level - before to call this function
        • -
      • HAL_PWR_EnterSLEEPMode()
        • -
          -
        • Remove - disable and enable of SysTick - Timer
          • -
        • Update - usage of __WFE() - in low power entry function: - if there is a pending event, - calling __WFE() will not - enter the CortexM4 core to - sleep mode. The solution is - to made the call below; the - first __WFE() - is always ignored and clears - the event if one was already - pending, the second is - always applied
          • -
        -
      -
    -
    -

    __SEV()
    -     __WFE()
    -     __WFE()

    -
    -
      -
        -
      • Add new macro - for software event generation - __HAL_PVD_EXTI_GENERATE_SWIT()
        • -
      • Remove the - following defines form Generic - driver and add them under - extension driver because they - are only used within extension - functions.
        • -
          -
        • CR_FPDS_BB: - used within HAL_PWREx_EnableFlashPowerDown() - function
          • -
        • CSR_BRE_BB: - used within HAL_PWREx_EnableBkUpReg() - function
          • -
        -
      • Add the - support of STM32F411xx devices - add the define STM32F411xE
        • -
          -
        • For - STM32F401xC, STM32F401xE and - STM32F411xE devices add the - following functions used to - enable or disable the low - voltage mode for regulators
          • -
        -
      -
    -
      -
        -
          -
            -
          • HAL_PWREx_EnableMainRegulatorLowVoltage()
            • -
          • HAL_PWREx_DisableMainRegulatorLowVoltage()
            • -
          • HAL_PWREx_EnableLowRegulatorLowVoltage()
            • -
          • HAL_PWREx_DisableLowRegulatorLowVoltage()
            • -
          -
        -
      • For - STM32F42xxx/43xxx devices, add - a new function for Under - Driver management as the macro - already added for this mode is - not sufficient: HAL_PWREx_EnterUnderDriveSTOPMode()
        • -
      -
    -
      -
    • HAL - - - - RCC update
      • -
        -
      • In HAL_RCC_ClockConfig() - function: update the AHB clock - divider before clock switch to - new source
        • -
      • Allow to - calibrate the HSI when it is - used as system clock source
        • -
      • Rename the - following macros
        • -
          -
        • __OTGFS_FORCE_RESET - - - - ()  by - __USB_OTG_FS_FORCE_RESET()
          • -
        • __OTGFS_RELEASE_RESET - - - - ()  by  -__USB_OTG_FS_RELEASE_RESET()
          • -
        • __OTGFS_CLK_SLEEP_ENABLE - - - - - ()  by  -__USB_OTG_FS_CLK_SLEEP_ENABLE()
          • -
        • __OTGFS_CLK_SLEEP_DISABLE - - - - - () by  __USB_OTG_FS_CLK_SLEEP_DISABLE()
          • -
        -
      -
    -

     

    -
      -
        -
      • Add new field - PLLI2SM in - RCC_PLLI2SInitTypeDef - structure, this division - factor is added for PLLI2S VCO - input clock only STM32F411xE - devices => the FW - compatibility is broken vs. - STM32F401xx devices
        • -
      • Update HAL_RCCEx_PeriphCLKConfig() - and  HAL_RCCEx_GetPeriphCLKConfig()  - - - - - functions to support the new - PLLI2SM
        • -
      • Add new - function to manage the new LSE - mode - - - - - : HAL_RCCEx_SelectLSEMode()
        • -
      • Reorganize - the macros depending from - Part number used and make them - more clear
        • -
      -
    -

    §  HAL - - - - UART update

    -
      -
        -
      • Add new - macros to control CTS and RTS
        • -
      • Add specific - macros to manage the flags - cleared only by a software sequence
        • -
          -
        • __HAL_UART_CLEAR_PEFLAG()
          • -
        • __HAL_UART_CLEAR_FEFLAG()
          • -
        • __HAL_UART_CLEAR_NEFLAG()
          • -
        • __HAL_UART_CLEAR_OREFLAG()
          • -
        • __HAL_UART_CLEAR_IDLEFLAG()
          • -
        -
      • Add several - enhancements without affecting - the driver functionalities -
        • -
          -
        • Remove the - check on RXNE set after - reading the Data in the DR - register
          • -
        • Update the - transmit processes to use - TXE instead of TC
          • -
        • Update HAL_UART_Transmit_IT() - to enable UART_IT_TXE - instead of UART_IT_TC
          • -
        -
      -
    -

    §  - - - - - HAL USART - update

    -
      -
        -
      • Add specific - macros to manage the flags - cleared only by a software sequence
        • -
          -
        • __HAL_USART_CLEAR_PEFLAG()
          • -
        • __HAL_USART_CLEAR_FEFLAG()
          • -
        • __HAL_USART_CLEAR_NEFLAG()
          • -
        • __HAL_USART_CLEAR_OREFLAG()
          • -
        • __HAL_USART_CLEAR_IDLEFLAG()
          • -
        -
      • Update HAL_USART_Transmit_IT() - to enable USART_IT_TXE - instead of USART_IT_TC
        • -
      -
    -

    §  - - - - - HAL IRDA update

    -
      -
        -
      • Add specific - macros to manage the flags - cleared only by a software sequence
        • -
          -
        • __HAL_IRDA_CLEAR_PEFLAG()
          • -
        • __HAL_ - IRDA _CLEAR_FEFLAG()
          • -
        • __HAL_ - IRDA _CLEAR_NEFLAG()
          • -
        • __HAL_ - IRDA _CLEAR_OREFLAG()
          • -
        • __HAL_ - IRDA _CLEAR_IDLEFLAG()
          • -
        -
      • Add several - enhancements without affecting - the driver functionalities
        • -
      -
    -
      -
        -
          -
        • Remove the - check on RXNE set after - reading the Data in the DR - register
          • -
        • Update HAL_IRDA_Transmit_IT() - to enable IRDA_IT_TXE - instead of IRDA_IT_TC
          • -
        -
      • Add the - following APIs used within DMA - process -
        • -
          -
        • HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef - *hirda);
          • -
        • HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef - *hirda);
          • -
        • HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef - *hirda); -
          • -
        • void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef - *hirda);
          • -
        • void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef - *hirda);
          • -
        -
      -
    -

    §  - - - - - HAL SMARTCARD - update

    -
      -
        -
      • Add specific - macros to manage the flags - cleared only by a software sequence
        • -
          -
        • __HAL_SMARTCARD_CLEAR_PEFLAG()
          • -
        • __HAL_SMARTCARD_CLEAR_FEFLAG()
          • -
        • __HAL_SMARTCARD_CLEAR_NEFLAG()
          • -
        • __HAL_SMARTCARD_CLEAR_OREFLAG()
          • -
        • __HAL_SMARTCARD_CLEAR_IDLEFLAG()
          • -
        -
      • Add several - enhancements without affecting - the driver functionalities
        • -
          -
        • Add a new - state HAL_SMARTCARD_STATE_BUSY_TX_RX - and all processes has been - updated accordingly
          • -
        • Update HAL_SMARTCARD_Transmit_IT() - to enable SMARTCARD_IT_TXE - instead of SMARTCARD_IT_TC
          • -
        -
      -
    -
      -
    • HAL - - - - SPI update
      • -
        -
      • Bugs fix
        • -
          -
        • SPI - interface is used in - synchronous polling mode: at - high clock rates like SPI prescaler - 2 and 4, calling
          - HAL_SPI_TransmitReceive() - returns with error - HAL_TIMEOUT           -
          • -
        • HAL_SPI_TransmitReceive_DMA() does not - clean up the TX DMA, so any - subsequent SPI calls return - the DMA error
          • -
        • HAL_SPI_Transmit_DMA() is failing - when data size is equal to 1 - byte -
          • -
        -
      • Add the - following APIs used within the - DMA process
        • -
      -
    -
      -
        -
          -
        • HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef - *hspi);
          • -
        • HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef - *hspi);
          • -
        • HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef - *hspi);
          • -
        • void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef - *hspi);
          • -
        • void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef - *hspi);
          • -
        • void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef - *hspi);
          • -
        -
      -
    -
      -
    • HAL - - - - RNG update
      • -
        -
          -
        • Add a - conditional define to make - this driver visible for all - STM32F4xx devices except - STM32F401xx and STM32F411xx - Devices.
          • -
        -
      -
    • HAL - - - - CRC update
      • -
        -
          -
        • These - macros are added to - read/write the CRC IDR - register: __HAL_CRC_SET_IDR() - and __HAL_CRC_GET_IDR()
          • -
        -
      -
    -
      -
    • HAL - - - - DAC update
      • -
        -
      • Enhance the - DMA channel configuration when - used with DAC
        • -
      -
    • HAL - - - - TIM update
      • -
        -
      • HAL_TIM_IRQHandler(): update to - check the input capture - channel 3 and 4 in CCMR2 - instead of CCMR1
        • -
      • __HAL_TIM_PRESCALER() - updated to use '=' instead of - '|='
        • -
      • Add the - following macro in TIM HAL - driver
        • -
          -
        • __HAL_TIM_GetCompare() -
          • -
        • __HAL_TIM_GetCounter() -
          • -
        • __HAL_TIM_GetAutoreload() -
          • -
        • __HAL_TIM_GetClockDivision() -
          • -
        • __HAL_TIM_GetICPrescaler()
          • -
        -
      -
    • HAL - - - - SDMMC update
      • -
    -
      -
        -
      • Use of CMSIS - constants instead of magic values
        • -
      • Miscellaneous - update in functions internal - coding
        • -
      -
    • HAL - - - - NAND update
      • -
        -
      • Fix - - - - issue of macros returning - wrong address for NAND blocks
        • -
      • Fix - - - - issue for read/write NAND - page/spare area
        • -
      -
    • HAL - - - - NOR update
      • -
        -
      • Add - - - - the NOR address bank macro - used within the API
        • -
      • Update - - - - NOR API implementation to - avoid the use of NOR address - bank hard coded
        • -
      -
    • HAL - - - - HCD update
      • -
        -
      • HCD_StateTypeDef structure - members renamed
        • -
      • These macro are renamed
        • -
          -
        • __HAL_GET_FLAG(__HANDLE__, - - - - - __INTERRUPT__)    - - - - by - __HAL_HCD_GET_FLAG(__HANDLE__, - __INTERRUPT__)
          • -
        • __HAL_CLEAR_FLAG(__HANDLE__, - - - - - __INTERRUPT__) by - __HAL_HCD_CLEAR_FLAG(__HANDLE__, - __INTERRUPT__) 
          • -
        • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  - - - - - by - __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)  -
          • -
        -
      -
    • HAL - - - - PCD update
      • -
        -
      • HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() - - - - - renamed into HAL_PCDEx_SetTxFiFo() - - - - - and HAL_PCDEx_SetRxFiFo() - - - - - and moved to the extension - files - stm32f4xx_hal_pcd_ex.h/.c
        • -
      • PCD_StateTypeDef structure - members renamed
        • -
      • Fix incorrect - masking of TxFIFOEmpty
        • -
      • stm32f4xx_ll_usb.c: - - - - fix issue in HS mode
        • -
      • New macros added
        • -
          -
        • __HAL_PCD_IS_PHY_SUSPENDED()
          • -
        • __HAL_USB_HS_EXTI_GENERATE_SWIT()
          • -
        • __HAL_USB_FS_EXTI_GENERATE_SWIT()
          • -
        -
      • These macro are renamed
        • -
          -
        • __HAL_GET_FLAG(__HANDLE__, - - - - - __INTERRUPT__)    - - - - by - __HAL_PCD_GET_FLAG(__HANDLE__, - __INTERRUPT__)
          • -
        • __HAL_CLEAR_FLAG(__HANDLE__, - - - - - __INTERRUPT__) by - __HAL_PCD_CLEAR_FLAG(__HANDLE__, - __INTERRUPT__) 
          • -
        • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  - - - - - by - __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)  -
          • -
        • __HAL_PCD_UNGATE_CLOCK(__HANDLE__) - - - - - by - __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
          • -
        • __HAL_PCD_GATE_CLOCK(__HANDLE__) - - - - - by - __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)
          • -
        -
      -
    • HAL - - - - ETH update
      • -
        -
      • Update HAL_ETH_GetReceivedFrame_IT() - function to return HAL_ERROR - if the received packet is not - complete
        • -
      • Use HAL_Delay() - instead of counting loop
        • -
      •  __HAL_ETH_MAC_CLEAR_FLAG() - macro is removed: the MACSR - register is read only
        • -
      • Add the - following macros used to Wake - up the device from STOP mode - by Ethernet event - - - - :
        • -
          -
        • __HAL_ETH_EXTI_ENABLE_IT()
          • -
        • __HAL_ETH_EXTI_DISABLE_IT()
          • -
        • __HAL_ETH_EXTI_GET_FLAG()
          • -
        • __HAL_ETH_EXTI_CLEAR_FLAG()
          • -
        • __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER()
          • -
        • __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER()
          • -
        • __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER()
          • -
        -
      -
    • HAL - - - - WWDG update
      • -
        -
      • Update macro - parameters to use underscore: - __XXX__
        • -
      • Use of CMSIS - constants instead of magic values
        • -
      • Use - MODIFY_REG macro in HAL_WWDG_Init()
        • -
      • Add - IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() - and HAL_WWDG_DeInit()
        • -
      -
    • HAL - - - - IWDG update
      • -
        -
      • Use WRITE_REG - instead of SET_BIT for all - IWDG macros
        • -
      • __HAL_IWDG_CLEAR_FLAG - - - - - removed: no IWDG flag cleared - by access to SR register
        • -
      • Use - MODIFY_REG macro in HAL_IWDG_Init()
        • -
      • Add - IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init()Add - - - - - the following macros used to - Wake
        • -
      -
    -

    V1.0.0 - - - - / 18-February-2014

    -

    Main Changes

    -
      -
    • First - - - - official release 
      • -
    -
    -

    For - - - - - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

    -
-

 

-
-
-

-
-
-

 

-
-
- \ No newline at end of file + +
+

Update History

+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and implementation enhancements.
    • +
  • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
    • +
  • HAL Generic update +
      +
    • Allow redefinition of macro UNUSED(x).
      • +
    • +
  • HAL RCC update +
      +
    • Correct the configuration macro of I2S clock source and the value of I2S external clock source.
      • +
    • Set the minimum value of PLLM.
      • +
    • Update the rest values for the macro __HAL_RCC_Axxx_FORCE_RESET() to avoid setting reserved bits.
      • +
    • +
  • HAL PWR update +
      +
    • Add a call to UNUSED() macro to avoid the generation of a warning related to the unused argument ‘Regulator’.
      • +
    • Add PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR mode to avoid systematic clear of event in HAL_PWR_EnterSLEEPMode() and HAL_PWR_EnterSTOPMode().
      • +
    • +
  • HAL Cortex update +
      +
    • Add the following new HAL/LL CORTEX APIs to clear PWR pending event: +
        +
      • LL_LPM_ClearEvent().
        • +
      • HAL_CORTEX_ClearEvent().
        • +
      • +
    • +
  • HAL EXTI update +
      +
    • Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine.
      • +
    • +
  • HAL/LL ADC update +
      +
    • Cast both LL_ADC_REG_ReadConversionData6() and LL_ADC_REG_ReadConversionData8() returned values from uint16_t to uint8_t to be consistent with prototypes.
      • +
    • Add a call to UNUSED() macro in LL_ADC_DMA_GetRegAddr() API to prevent compilation warning due to unused ‘Register’ parameter.
      • +
    • +
  • HAL DAC update +
      +
    • Fix incorrect word ‘surcharged’ in functions headers.
      • +
    • Updated DAC buffer calibration according to RM.
      • +
    • +
  • HAL CEC update +
      +
    • Better performance by removing multiple volatile reads or writes in interrupt handler.
      • +
    • +
  • HAL RTC update +
      +
    • Check if the RTC calendar has been previously initialized before entering initialization mode.
      • +
    • Remove macro __HAL_RTC_TAMPER_GET_IT() as it is redundant with macro __HAL_RTC_TAMPER_GET_FLAG() and create an alias into the stm32_hal_legacy.h file.
      • +
    • Correct misleading note about shadow registers.
      • +
    • +
  • HAL CRYP update +
      +
    • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before the DINR pointer increment.
      • +
    • +
  • HAL HASH update +
      +
    • HAL code quality enhancement for MISRA-C2012 Rule-2.2_c.
      • +
    • +
  • HAL TIM update +
      +
    • Align TIM_TIM2_ETH_PTP definition with the reference manual specification.
      • +
    • Improve driver robustness against wrong period values.
      • +
    • Improve driver robustness against wrong DMA related parameters.
      • +
    • Improve period configuration parameter check.
      • +
    • Remove Lock management from callback management functions.
      • +
    • Remove multiple volatile reads or writes in interrupt handler for better performance.
      • +
    • Improve HAL TIM driver’s operational behavior.
      • +
    • Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init().
      • +
    • +
  • HAL LPTIM update +
      +
    • Apply same naming rules to clear FLAG related functions.
      • +
    • Remove Lock management from callback management functions.
      • +
    • +
  • HAL CAN update +
      +
    • Removal of never reached code.
      • +
    • Improve protection against bad inputs.
      • +
    • +
  • HAL DSI update +
      +
    • Update to align DSI ULPS entry and exit sequences with reference manual.
      • +
    • +
  • HAL ETH update +
      +
    • Update Rx descriptor tail pointer management to avoid race condition.
      • +
    • +
  • HAL UART update +
      +
    • New API HAL_UARTEx_GetRxEventType() to retrieve the type of event that has led the RxEventCallback execution.
      • +
    • Removal of HAL_LOCK/HAL_UNLOCK() calls in HAL UART Tx and Rx APIs.
      • +
    • Removal of __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
      • +
    • Avoid ORE flag to be cleared by a transmit process in polling mode.
      • +
    • Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.
      • +
    • +
  • HAL USART update +
      +
    • Removal of __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
      • +
    • +
  • HAL I2C update +
      +
    • Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA.
      • +
    • Update I2C_MemoryTransmit_TXE_BTF process to disable TXE and BTF interrupts if nothing to do.
      • +
    • Clear TXE Flag at the end of transfer.
      • +
    • Move polling code of HAL memory interface through interrupt management to prevent timeout issue using HAL MEM interface through FreeRTOS.
      • +
    • Update I2C_IsErrorOccurred to return error if timeout is detected.
      • +
    • Clear the ADDRF flag only when direction is confirmed as changed, to prevent that the ADDRF flag is cleared too early when the restart is received.
      • +
    • Update HAL_I2C_Master_Transmit_IT to return HAL_BUSY instead of HAL_ERROR when timeout occur and I2C_FLAG_BUSY is SET.
      • +
    • Clear ACK bit once 3 bytes to read remain to be able to send the NACK once the transfer ends.
      • +
    • Duplicate the test condition after timeout detection to avoid false timeout detection.
      • +
    • Update HAL_I2C_IsDeviceReady() API to support 10_bit addressing mode: macro I2C_GENERATE_START is updated.
      • +
    • Update HAL I2C driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.
      • +
    • Update the HAL I2C driver to disactivate all interrupts after the end of transaction.
      • +
    • Update HAL_I2C_Init API to clear ADD10 bit in 7 bit addressing mode.
      • +
    • Solve Slave No stretch not functional by using HAL Slave interface.
      • +
    • Update HAL_FMPI2C_Mem_Write_IT API to initialize XferSize at 0.
      • +
    • Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice.
      • +
    • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF independently from I2C_FLAG_RXNE.
      • +
    • Clear ACK bit once 3 bytes to read remain to be able to send the NACK once the transfer ends.
      • +
    • Remove the unusable code in function HAL_I2C_IsDeviceReady.
      • +
    • Update HAL_I2C_Master_Abort_IT to support memory abort transfer.
      • +
    • Update LL_I2C_HandleTranfer function to prevent undefined behavior of volatile usage before updating the CR2 register.
      • +
    • Update I2C_WaitOnFlagUntilTimeout to handle error case.
      • +
    • Update the HAL I2C driver to reset PreviousState to I2C_STATE_NONE at the end of transfer.
      • +
    • +
  • HAL SMBUS update +
      +
    • Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master.
      • +
    • Add flush on TX register.
      • +
    • Change previous state from HAL_SMBUS_STATE_READY to HAL_SMBUS_STATE_NONE at the end of transfer.
      • +
    • Update HAL SMBUS driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.
      • +
    • +
  • HAL SAI update +
      +
    • Improve audio quality (avoid potential glitch).
      • +
    • Fix incorrect word ‘surcharged’.
      • +
    • +
  • HAL SPI update +
      +
    • Fix driver to don’t update state in case of error (HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT).
      • +
    • Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of one byte transaction.
      • +
    • Update IT API to enable interrupts after process unlock.
      • +
    • Add wait on flag TXE to be set at the end of transaction to be aligned with reference manual.
      • +
    • +
  • HAL SPDIFRX update +
      +
    • Prevent hard fault by checking DMA usage.
      • +
    • Tuning of default SPDIFRX timeout.
      • +
    • +
  • HAL USB OTG update +
      +
    • ll_usb.c fix added to USB_ClearInterrupts(), should write “1†to clear the interrupt status bits of OTG_FS_GINTSTS register.
      • +
    • ll_usb.c: remove useless software setting to setup the frame interval at 80%.
      • +
    • ll_usb.c, hal_hcd.c: adding support of hub split transactions.
      • +
    • ll_usb.c: improve delay management to set core mode.
      • +
    • ll_usb.c, hal_pcd.c: fix device connection in case battery charging used with HS instance linked to internal FS PHY.
      • +
    • ll_usb.c: increase timeout value to allow core reset to complete.
      • +
    • +
  • HAL IRDA update +
      +
    • Removal of __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
      • +
    • +
  • HAL SMARTCARD update +
      +
    • Removal of __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback().
      • +
    • +
  • HAL SDMMC update +
      +
    • Update HAL SD processes to manage STBITERR flag.
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix HAL ETH defects and implementation enhancements.
    • +
  • HAL updates +
      +
    • HAL ETH update +
        +
      • Remove useless assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)) from static function ETH_MACAddressConfig().
        • +
      • Replace hard coded Rx buffer size (1000U) by macro ETH_RX_BUF_SIZE.
        • +
      • Correct bit positions when getting MAC and DMA configurations and replace ‘UnicastSlowProtocolPacketDetect’ by ‘UnicastPausePacketDetect’ in the MAC default configuration structure.
        • +
      • Ensure a delay of 4 TX_CLK/RX_CLK cycles between two successive write operations to the same register.
        • +
      • Disable DMA transmission in both HAL_ETH_Stop_IT() and HAL_ETH_Stop() APIs.
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and implementation enhancements.
    • +
  • All source files: update disclaimer to add reference to the new license agreement.
    • +
  • The following changes done on the HAL drivers require an update of the application code based on older HAL versions +
      +
    • Rework of HAL Ethernet driver to resolve problems and improve performance (compatibility break).
      • +
    • A new HAL Ethernet driver has been redesigned with new APIs, to bypass limitations with previous HAL Ethernet driver version.
      • +
    • The new HAL Ethernet driver is the recommended version. It is located as usual in Drivers/STM32F4xx_HAL_Driver/Src and Drivers/STM32F4xx_HAL_Driver/Inc folders. +
        +
      • It can be enabled through switch HAL_ETH_MODULE_ENABLED in stm32f4xx_hal_conf.h
        • +
      • +
    • The legacy HAL Ethernet driver is also present in the release in Drivers/STM32F4xx_HAL_Driver/Src/Legacy and Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software compatibility reasons. +
        +
      • Its usage is not recommended as deprecated. It can however be enabled through switch HAL_ETH_LEGACY_MODULE_ENABLED in stm32f4xx_hal_conf.h
        • +
      • +
    • +
  • HAL update +
      +
    • HAL ETH update +
        +
      • Entire receive process reworked.
        • +
      • Resolve the problem of received data corruption.
        • +
      • Implement transmission in interrupt mode.
        • +
      • Handle one interrupt for multiple transmitted packets.
        • +
      • Implement APIs to handle PTP feature.
        • +
      • Implement APIs to handle Timestamp feature.
        • +
      • Add support of receive buffer unavailable.
        • +
      • Update HAL_ETH_IRQHandler() to handle receive buffer unavailable.
        • +
      • +
    • HAL SMBUS update +
        +
      • Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master. +
          +
        • Add flush on TX register.
          • +
        • +
      • +
    • HAL TIM update +
        +
      • __LL_TIM_CALC_PSC() macro update to round up the evaluate value when the fractional part of the division is greater than 0.5.
        • +
      • +
    • HAL LPTIM update +
        +
      • Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()
        • +
      • +
    • HAL UART update +
        +
      • Add const qualifier for read only pointers.
        • +
      • Improve header description of UART_WaitOnFlagUntilTimeout() function.
        • +
      • Add a check on the UART parity before enabling the parity error interruption.
        • +
      • Fix typo in UART_IT_TXE bit description.
        • +
      • +
    • HAL IRDA update +
        +
      • Improve header description of IRDA_WaitOnFlagUntilTimeout() function.
        • +
      • Add a check on the IRDA parity before enabling the parity error interrupt.
        • +
      • Add const qualifier for read only pointers.
        • +
      • +
    • HAL SMARTCARD update +
        +
      • Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function
        • +
      • Add const qualifier for read only pointers.
        • +
      • +
    • HAL NOR update +
        +
      • Apply adequate commands according to the command set field value
        • +
      • command set 1 for Micron JS28F512P33
        • +
      • command set 2 for Micron M29W128G and Cypress S29GL128P
        • +
      • Add new command operations: +
          +
        • NOR_CMD_READ_ARRAY
          • +
        • NOR_CMD_WORD_PROGRAM
          • +
        • NOR_CMD_BUFFERED_PROGRAM
          • +
        • NOR_CMD_CONFIRM
          • +
        • NOR_CMD_BLOCK_ERASE
          • +
        • NOR_CMD_BLOCK_UNLOCK
          • +
        • NOR_CMD_READ_STATUS_REG
          • +
        • NOR_CMD_CLEAR_STATUS_REG
          • +
        • +
      • Update some APIs in order to be compliant for memories with different command set, the updated APIs are: +
          +
        • HAL_NOR_Init()
          • +
        • HAL_NOR_Read_ID()
          • +
        • HAL_NOR_ReturnToReadMode()
          • +
        • HAL_NOR_Read()
          • +
        • HAL_NOR_Program()
          • +
        • HAL_NOR_ReadBuffer()
          • +
        • HAL_NOR_ProgramBuffer()
          • +
        • HAL_NOR_Erase_Block()
          • +
        • HAL_NOR_Erase_Chip()
          • +
        • HAL_NOR_GetStatus()
          • +
        • +
      • Align HAL_NOR_Init() API with core of the function when write operation is disabled to avoid HardFault.
        • +
      • +
    • HAL SDMMC update +
        +
      • Take into account the voltage range in the CMD1 command.
        • +
      • Add new LL function to have correct response for MMC driver.
        • +
      • Update the driver to have all fields correctly initialized.
        • +
      • Add an internal variable to manage the power class and call it before to update speed of bus width.
        • +
      • Add new API to get the value of the Extended CSD register and populate the ExtCSD field of the MMC handle.
        • +
      • In HAL_MMC_InitCard(), call to SDIO_PowerState_ON() moved after __HAL_MMC_ENABLE() to ensure MMC clock is enabled before the call to HAL_Delay() from within SDIO_PowerState_ON().
        • +
      • +
    • HAL DMA update +
        +
      • Manage the case of an invalid value of CallbackID passed to the HAL_DMA_RegisterCallback() API.
        • +
      • +
    • HAL LTDC update +
        +
      • Update HAL_LTDC_DeInit() to fix MCU Hang up during LCD turn OFF.
        • +
      • +
    • HAL I2C update +
        +
      • Update to fix issue detected due to low system frequency execution (HSI).
        • +
      • Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA
        • +
      • Update HAL I2C Master Receive IT process to safe manage data N= 2 and N= 3. +
          +
        • Disable RxNE interrupt if nothing to do.
          • +
        • +
      • +
    • HAL USART update +
        +
      • Improve header description of USART_WaitOnFlagUntilTimeout() function.
        • +
      • Add a check on the USART parity before enabling the parity error interrupt.
        • +
      • Add const qualifier for read only pointers.
        • +
      • +
    • HAL/LL ADC update +
        +
      • Update LL_ADC_IsActiveFlag_MST_EOCS() API to get the appropriate flag.
        • +
      • Better performance by removing multiple volatile reads or writes in interrupt handler.
        • +
      • +
    • HAL FMPI2C update +
        +
      • Update to handle errors in polling mode. +
          +
        • Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs.
          • +
        • +
      • +
    • HAL EXTI update +
        +
      • Update HAL_EXTI_GetConfigLine() API to fix wrong calculation of GPIOSel value.
        • +
      • +
    • HAL QSPI update +
        +
      • Update HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() APIs to check on QSPI BUSY flag status before executing the abort procedure.
        • +
      • +
    • HAL/LL RTC cleanup +
        +
      • Use bits definitions from CMSIS Device header file instead of hard-coded values.
        • +
      • Wrap comments to be 80-character long and correct typos.
        • +
      • Move constants RTC_IT_TAMP. from hal_rtc.h to hal_rtc_ex.h.
        • +
      • Gather all instructions related to exiting the “init†mode into new function RTC_ExitInitMode().
        • +
      • Add new macro assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger)) to check tamper filtering is disabled in case tamper events are triggered on signal edges.
        • +
      • Rework functions HAL_RTCEx_SetTamper() and HAL_RTCEx_SetTamper_IT() to: +
          +
        • Write in TAFCR register in one single access instead of two.
          • +
        • Avoid modifying user structure sTamper.
          • +
        • +
      • Remove functions LL_RTC_EnablePushPullMode() and LL_RTC_DisablePushPullMode() as related to non-supported features.
        • +
      • Remove any reference to non-supported features (e.g., LL_RTC_ISR_TAMP3F).
        • +
      • Remove useless conditional defines as corresponding features are supported by all part-numbers (e.g., #if defined(RTC_TAFCR_TAMPPRCH)).
        • +
      • +
    • HAL USB OTG update +
        +
      • Fix USB_FlushRxFifo() and USB_FlushTxFifo() APIs by adding check on AHB master IDLE state before flushing the USB FIFO
        • +
      • Fix to avoid resetting host channel direction during channel halt
        • +
      • Fix to report correct received amount of data with USB DMA enabled
        • +
      • Fix to avoid compiler optimization on count variable used for USB HAL timeout loop check
        • +
      • Add missing registered callbacks check for HAL_HCD_HC_NotifyURBChange_Callback()
        • +
      • Add new API HAL_PCD_SetTestMode() APIs to handle USB device high speed Test modes
        • +
      • Setting SNAK for EPs not required during device reset
        • +
      • Update USB IRQ handler to enable EP OUT disable
        • +
      • Add support of USB IN/OUT Iso incomplete
        • +
      • Fix USB BCD data contact timeout
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • HAL update +
      +
    • HAL EXTI update +
        +
      • Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.
        • +
      • +
    • HAL GPIO update +
        +
      • Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.
        • +
      • +
    • HAL DMA update +
        +
      • Update HAL_DMA_IRQHandler() API to set the DMA state before unlocking access to the DMA handle.
        • +
      • +
    • LL ADC update +
        +
      • Update LL_ADC_DeInit() API to clear missing SQR3 register.
        • +
      • +
    • HAL CAN update +
        +
      • Update HAL_CAN_Init() API to be aligned with reference manual and to avoid timeout error.
        • +
      • +
    • HAL/LL RTC_BKP update +
        +
      • Update __HAL_RTC_…(__HANDLE__, …) macros to access registers through (__HANDLE__)->Instance pointer and avoid “unused variable†warnings.
        • +
      • Correct month management in IS_LL_RTC_MONTH() macro.
        • +
      • +
    • HAL RNG update +
        +
      • Update timeout mechanism to avoid false timeout detection in case of preemption.
        • +
      • +
    • HAL QSPI update +
        +
      • ES0305 workaround disabled for STM32412xx devices.
        • +
      • +
    • HAL I2C update +
        +
      • Update HAL_I2C_Mem_Write_DMA() and HAL_I2C_Mem_Read_DMA() APIs to initialize Devaddress, Memaddress and EventCount parameters.
        • +
      • Update to prevent several calls of Start bit: +
          +
        • Update I2C_MemoryTransmit_TXE_BTF() API to increment EventCount.
          • +
        • +
      • Update to avoid I2C interrupt in endless loop: +
          +
        • Update HAL_I2C_Master_Transmit_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA() and HAL_I2C_Master_Receive_DMA() APIs to unlock the I2C peripheral before generating the start.
          • +
        • +
      • Update to use the right macro to clear I2C ADDR flag inside I2C_Slave_ADDR() API as it’s indicated in the reference manual.
        • +
      • Update I2C_IsAcknowledgeFailed() API to avoid I2C in busy state if NACK received after transmitting register address.
        • +
      • Update HAL_I2C_EV_IRQHandler() and I2C_MasterTransmit_BTF() APIs to correctly manage memory transfers: +
          +
        • Add check on memory mode before calling callbacks procedures.
          • +
        • +
      • +
    • LL USART update +
        +
      • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)
        • +
      • +
    • HAL SMBUS update +
        +
      • Updated HAL_SMBUS_ER_IRQHandler() API to return the correct error code “SMBUS_FLAG_PECERR†in case of packet error occurs.
        • +
      • +
    • HAL/LL SPI update +
        +
      • Updated to fix MISRA-C 2012 Rule-13.2.
        • +
      • Update LL_SPI_TransmitData8() API to avoid casting the result to 8 bits.
        • +
      • +
    • HAL UART update +
        +
      • Fix wrong comment related to RX pin configuration within the description section
        • +
      • Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback
        • +
      • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART) +
          +
        • Update CAN Initialization sequence to set “request initialization†bit before exit from sleep mode.
          • +
        • +
      • +
    • HAL USB update +
        +
      • HAL PCD: add fix transfer complete for IN Interrupt transaction in single buffer mode
        • +
      • Race condition in USB PCD control endpoint receive ISR.
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • HAL +
      +
    • HAL/LL USART update +
        +
      • Fix typo in USART_Receive_IT() and USART_TransmitReceive_IT() APIs to avoid possible compilation issues if the UART driver files are not included.
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
  • Added new HAL FMPSMBUS extended driver to support FMPSMBUS fast Mode Plus.
    • +
  • Removed “register†keyword to be compliant with new C++ rules: +
      +
    • The register storage class specifier was deprecated in C++11 and removed in C++17.
      • +
    • +
  • HAL +
      +
    • HAL update
      • +
    • General updates to fix known defects and enhancements implementation.
      • +
    • Added new defines for ARM compiler V6: +
        +
      • __weak
        • +
      • __packed
        • +
      • __NOINLINE
        • +
      • +
    • Updated HAL TimeBase TIM, RTC alarm and RTC WakeUp templates for more robustness +
        +
      • Updated Hal_Init_Tick() API to properly store the priority when using the non-default time base.
        • +
      • +
    • Updated PPP_MODULE_ENABLED for FMPSMBUS.
      • +
    • HAL/LL ADC update +
        +
      • Updated to add include of the LL ADC driver.
        • +
      • Updated the following APIs to set status HAL_ADC_STATE_ERROR_INTERNAL and error code HAL_ADC_ERROR_INTERNAL when error occurs: +
          +
        • HAL_ADC_Start()
          • +
        • HAL_ADC_Start_IT()
          • +
        • HAL_ADC_Start_DMA()
          • +
        • HAL_ADCEx_InjectedStart()
          • +
        • HAL_ADCEx_InjectedStart_IT()
          • +
        • HAL_ADCEx_MultiModeStart_DMA()
          • +
        • +
      • Updated HAL_ADC_Stop_DMA() API to check if DMA state is Busy before calling HAL_DMA_Abort() API to avoid DMA internal error.
        • +
      • Updated IS_ADC_CHANNEL to support temperature sensor for: +
          +
        • STM32F411xE
          • +
        • STM32F413xx
          • +
        • STM32F423xx
          • +
        • +
      • Fixed wrong defined values for: +
          +
        • LL_ADC_MULTI_REG_DMA_LIMIT_3
          • +
        • LL_ADC_MULTI_REG_DMA_UNLMT_3
          • +
        • +
      • Added __LL_ADC_CALC_VREFANALOG_VOLTAGE() macro to evaluate analog reference voltage.
        • +
      • Removed __LL_ADC_CALC_TEMPERATURE() macro for STM32F4x9 devices as the TS_CAL2 is not available.
        • +
      • +
    • HAL/LL DAC update +
        +
      • Added restruction on DAC Channel 2 defines and parameters.
        • +
      • HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID used instead of HAL_DAC_MSP_INIT_CB_ID and HAL_DAC_MSP_DEINIT_CB_ID.
        • +
      • Updated to support dual mode: +
          +
        • Added two new APIs: +
            +
          • HAL_DACEx_DualStart()
            • +
          • HAL_DACEx_DualStop()
            • +
          • +
        • +
      • Added position bit definition to be used instead of __DAC_MASK_SHIFT macro +
          +
        • __DAC_MASK_SHIFT macro has been removed.
          • +
        • +
      • Updated HAL_DAC_Start_DMA() API to return HAL_ERROR when error occurs.
        • +
      • Updated HAL_DAC_Stop_DMA() API to not return HAL_ERROR when DAC is already disabled.
        • +
      • +
    • HAL CEC update +
        +
      • Updated HAL_CEC_IRQHandler() API to avoid appending an extra byte to the end of a message.
        • +
      • +
    • HAL/LL GPIO update +
        +
      • Updated IS_GPIO_AF() to add missing values for STM32F401xC and STM32F401xE devices: +
          +
        • GPIO_AF3_TIM9
          • +
        • GPIO_AF3_TIM10
          • +
        • GPIO_AF3_TIM11
          • +
        • +
      • Updated LL/HAL GPIO_TogglePin() APIs to allow multi Pin’s toggling.
        • +
      • Updated HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.
        • +
      • +
    • HAL/LL RCC update +
        +
      • Updated HAL_RCC_OscConfig() API to add missing checks and to don’t return HAL_ERROR if request repeats the current PLL configuration.
        • +
      • Updated IS_RCC_PLLN_VALUE(VALUE) macro in case of STM32F411xE device in order to be aligned with reference manual.
        • +
      • +
    • HAL SD update +
        +
      • Update function SD_FindSCR() to resolve issue of FIFO blocking when reading.
        • +
      • Update read/write functions in DMA mode in order to force the DMA direction, updated functions: +
          +
        • HAL_SD_ReadBlocks_DMA()
          • +
        • HAL_SD_WriteBlocks_DMA()
          • +
        • +
      • Add the block size settings in the initialization functions and remove it from read/write transactions to avoid repeated and inefficient reconfiguration, updated functions: +
          +
        • HAL_SD_InitCard()
          • +
        • HAL_SD_GetCardStatus()
          • +
        • HAL_SD_ConfigWideBusOperation()
          • +
        • HAL_SD_ReadBlocks()
          • +
        • HAL_SD_WriteBlocks()
          • +
        • HAL_SD_ReadBlocks_IT()
          • +
        • HAL_SD_WriteBlocks_IT()
          • +
        • HAL_SD_ReadBlocks_DMA()
          • +
        • HAL_SD_WriteBlocks_DMA()
          • +
        • +
      • +
    • HAL MMC update +
        +
      • Add the block size settings in the initialization function and remove it from read/write transactions to avoid repeated and inefficient reconfiguration, updated functions: +
          +
        • HAL_MMC_InitCard()
          • +
        • HAL_MMC_ReadBlocks()
          • +
        • HAL_MMC_WriteBlocks()
          • +
        • HAL_MMC_ReadBlocks_IT()
          • +
        • HAL_MMC_WriteBlocks_IT()
          • +
        • HAL_MMC_ReadBlocks_DMA()
          • +
        • HAL_MMC_WriteBlocks_DMA()
          • +
        • +
      • Update read/write functions in DMA mode in order to force the DMA direction, updated functions: +
          +
        • HAL_MMC_ReadBlocks_DMA()
          • +
        • HAL_MMC_WriteBlocks_DMA()
          • +
        • +
      • Deploy new functions MMC_ReadExtCSD() and SDMMC_CmdSendEXTCSD () that read and check the sectors number of the device in order to resolve the issue of wrongly reading big memory size.
        • +
      • +
    • HAL NAND update +
        +
      • Update functions HAL_NAND_Read_SpareArea_16b() and HAL_NAND_Write_SpareArea_16b() to fix column address calculation issue.
        • +
      • +
    • LL SDMMC update +
        +
      • Update the definition of SDMMC_DATATIMEOUT constant in order to allow the user to redefine it in his proper application.
        • +
      • Remove ‘register’ storage class specifier from LL SDMMC driver.
        • +
      • Deploy new functions MMC_ReadExtCSD() and SDMMC_CmdSendEXTCSD () that read and check the sectors number of the device in order to resolve the issue of wrongly reading big memory size.
        • +
      • +
    • HAL SMBUS update +
        +
      • Support for Fast Mode Plus to be SMBUS rev 3 compliant.
        • +
      • Added HAL_FMPSMBUSEx_EnableFastModePlus() and HAL_FMPSMBUSEx_DisableFastModePlus() APIs to manage Fm+.
        • +
      • Updated SMBUS_MasterTransmit_BTF() , SMBUS_MasterTransmit_TXE() and SMBUS_MasterReceive_BTF() APIs to allow stop generation when CurrentXferOptions is different from SMBUS_FIRST_FRAME and SMBUS_NEXT_FRAME.
        • +
      • Updated SMBUS_ITError() API to correct the twice call of HAL_SMBUS_ErrorCallback.
        • +
      • +
    • HAL SPI update +
        +
      • Updated HAL_SPI_Init() API +
          +
        • To avoid setting the BaudRatePrescaler in case of Slave Motorola Mode.
          • +
        • Use the bit-mask for SPI configuration.
          • +
        • +
      • Updated Transmit/Receive processes in half-duplex mode +
          +
        • Disable the SPI instance before setting BDIOE bit.
          • +
        • +
      • Fixed wrong timeout management
        • +
      • Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled.
        • +
      • +
    • HAL SPDIFRX update +
        +
      • Remove ‘register’ storage class specifier from HAL SPDIFRX driver.
        • +
      • +
    • HAL I2S update +
        +
      • Updated I2SEx APIs to correctly support circular transfers +
          +
        • Updated I2SEx_TxRxDMACplt() API to manage DMA circular mode.
          • +
        • +
      • Updated HAL_I2SEx_TransmitReceive_DMA() API to set hdmatx (transfer callback and half) to NULL.
        • +
      • +
    • HAL SAI update +
        +
      • Updated to avoid the incorrect left/right synchronization. +
          +
        • Updated HAL_SAI_Transmit_DMA() API to follow the sequence described in the reference manual for slave transmitter mode.
          • +
        • +
      • Updated HAL_SAI_Init() API to correct the formula in case of SPDIF is wrong.
        • +
      • +
    • HAL CRYP update +
        +
      • Updated HAL_CRYP_SetConfig() and HAL_CRYP_GetConfig() APIs to set/get the continent of KeyIVConfigSkip correctly.
        • +
      • +
    • HAL EXTI update +
        +
      • __EXTI_LINE__ is now used instead of __LINE__ which is a standard C macro.
        • +
      • +
    • HAL DCMI +
        +
      • Support of HAL callback registration feature for DCMI extended driver.
        • +
      • +
    • HAL/LL TIM update +
        +
      • Updated HAL_TIMEx_OnePulseN_Start() and HAL_TIMEx_OnePulseN_Stop() APIs (pooling and IT mode) to take into consideration all OutputChannel parameters.
        • +
      • Corrected reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode.
        • +
      • Updated LL_TIM_GetCounterMode() API to return the correct counter mode.
        • +
      • +
    • HAL/LL SMARTCARD update +
        +
      • Fixed invalid initialization of SMARTCARD configuration by removing FIFO mode configuration as it is not member of SMARTCARD_InitTypeDef Structure.
        • +
      • Fixed typos in SMARTCARD State definition description
        • +
      • +
    • HAL/LL IRDA update +
        +
      • Fixed typos in IRDA State definition description
        • +
      • +
    • LL USART update +
        +
      • Remove useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro.
        • +
      • Update USART polling and interruption processes to fix issues related to accesses out of user specified buffer.
        • +
      • +
    • HAL USB update +
        +
      • Enhanced USB OTG host HAL with USB DMA is enabled: +
          +
        • fixed ping and data toggle issue,
          • +
        • reworked Channel error report management
          • +
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects.
    • +
  • HAL/LL I2C update +
      +
    • Update to fix hardfault issue with HAL_I2C_Mem_Write_DMA() API: +
        +
      • Abort the right ongoing DMA transfer when memory write access request operation failed: fix typo “hdmarx†replaced by “hdmatxâ€
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
  • HAL/LL I2C update +
      +
    • Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C memory IT processes +
        +
      • Add stop condition generation when NACK occurs.
        • +
      • +
    • Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer). +
        +
      • Add additional check on hi2c->hdmtx and hi2c->hdmarx before resetting DMA Tx/Rx complete callbacks
        • +
      • +
    • Update Sequential transfer APIs to adjust xfermode condition. +
        +
      • Replace hi2c->XferCount < MAX_NBYTE_SIZE by hi2c->XferCount <= MAX_NBYTE_SIZE which corresponds to a case without reload
        • +
      • +
    • +
  • HAL/LL USB update +
      +
    • Bug fix: USB_ReadPMA() and USB_WritePMA() by ensuring 16-bits access to USB PMA memory
      • +
    • Bug fix: correct USB RX count calculation
      • +
    • Fix USB Bulk transfer double buffer mode
      • +
    • Remove register keyword from USB defined macros as no more supported by C++ compiler
      • +
    • Minor rework on USBD_Start() and USBD_Stop() APIs: stopping device will be handled by HAL_PCD_DeInit() API.
      • +
    • Remove non used API for USB device mode.
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add new HAL FMPSMBUS and LL FMPI2C drivers
    • +
  • General updates to fix known defects and enhancements implementation
    • +
  • Update HAL CRYP driver to support block by block decryption without reinitializes the IV and KEY for each call.
    • +
  • Improve code quality by fixing MisraC-2012 violations
    • +
  • HAL/LL USB update +
      +
    • Add handling USB host babble error interrupt
      • +
    • Fix Enabling ULPI interface for platforms that integrates USB HS PHY
      • +
    • Fix Host data toggling for IN Iso transfers
      • +
    • Ensure to disable USB EP during endpoint deactivation
      • +
    • +
  • HAL CRYP update +
      +
    • Update HAL CRYP driver to support block by block decryption without initializing the IV and KEY at each call. +
        +
      • Add new CRYP Handler parameters: “KeyIVConfig†and “SizesSumâ€
        • +
      • Add new CRYP init parameter: "KeyIVConfigSkip
        • +
      • +
    • +
  • HAL I2S update +
      +
    • Update HAL_I2S_DMAStop() API to be more safe +
        +
      • Add a check on BSY, TXE and RXNE flags before disabling the I2S
        • +
      • +
    • Update HAL_I2S_DMAStop() API to fix multi-call transfer issue(to avoid re-initializing the I2S for the next transfer). +
        +
      • Add __HAL_I2SEXT_FLUSH_RX_DR() and __HAL_I2S_FLUSH_RX_DR() macros to flush the remaining data inside DR registers.
        • +
      • Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
  • HAL Generic update +
      +
    • HAL_SetTickFreq(): update to restore the previous tick frequency when HAL_InitTick() configuration failed.
      • +
    • +
  • HAL/LL GPIO update +
      +
    • Update GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s
      • +
    • +
  • HAL EXTI update +
      +
    • General update to enhance HAL EXTI driver robustness +
        +
      • Add additional assert check on EXTI config lines
        • +
      • Update to compute EXTI line mask before read/write access to EXTI registers
        • +
      • +
    • Update EXTI callbacks management to be compliant with reference manual: only one PR register for rising and falling interrupts. +
        +
      • Update parameters in EXTI_HandleTypeDef structure: merge HAL EXTI RisingCallback and FallingCallback in only one PendingCallback
        • +
      • Remove HAL_EXTI_RISING_CB_ID and HAL_EXTI_FALLING_CB_ID values from EXTI_CallbackIDTypeDef enumeration.
        • +
      • +
    • Update HAL_EXTI_IRQHandler() API to serve interrupts correctly. +
        +
      • Update to compute EXTI line mask before handle EXTI interrupt.
        • +
      • +
    • Update to support GPIO port interrupts: +
        +
      • Add new “GPIOSel†parameter in EXTI_ConfigTypeDef structure
        • +
      • +
    • +
  • HAL/LL RCC update +
      +
    • Update HAL_RCCEx_PeriphCLKConfig() API to support PLLI2S configuration for STM32F42xxx and STM32F43xxx devices
      • +
    • Update the HAL_RCC_ClockConfig() and HAL_RCC_DeInit() API to don’t overwrite the custom tick priority
      • +
    • Fix LL_RCC_DeInit() failure detected with gcc compiler and high optimization level is selected(-03)
      • +
    • Update HAL_RCC_OscConfig() API to don’t return HAL_ERROR if request repeats the current PLL configuration
      • +
    • +
  • HAL ADC update +
      +
    • Update LL_ADC_REG_Init() to fix wrong ADC CR1 register configuration +
        +
      • The ADC sequencer length is part of ADC SQR1 register not of ADC CR1 register
        • +
      • +
    • +
  • HAL CRYP update +
      +
    • Update HAL_CRYP_Encrypt() and HAL_CRYP_Decrypt() APIs to take into consideration the datatype fed to the DIN register (1-, 8-, 16-, or 32-bit data) when padding the last block of the payload, in case the size of this last block is less than 128 bits.
      • +
    • +
  • HAL RNG update +
      +
    • Update HAL_RNG_IRQHandler() API to fix error code management issue: error code is assigned “HAL_RNG_ERROR_CLOCK†in case of clock error and “HAL_RNG_ERROR_SEED†in case of seed error, not the opposite.
      • +
    • +
  • HAL DFSDM update +
      +
    • Update DFSDM_GetChannelFromInstance() API to remove unreachable check condition
      • +
    • +
  • HAL DMA update +
      +
    • Update HAL_DMA_Start_IT() API to omit the FIFO error
      • +
    • +
  • HAL FLASH update +
      +
    • Update FLASH_Program_DoubleWord() API to fix with EWARM high level optimization issue
      • +
    • +
  • HAL QSPI update +
      +
    • Remove Lock mechanism from HAL_QSPI_Init() and HAL_QSPI_DeInit() APIs
      • +
    • +
  • HAL HASH update +
      +
    • Null pointer on handler “hhash†is now checked before accessing structure member “hhash->Init.DataType†in the following API: +
        +
      • HAL_HASH_Init()
        • +
      • +
    • Following interrupt-based APIs have been added. Interrupt mode could allow the MCU to enter “Sleep†mode while a data block is being processed. Please refer to the “##### How to use this driver #####†section for details about their use. +
        +
      • HAL_HASH_SHA1_Accmlt_IT()
        • +
      • HAL_HASH_MD5_Accmlt_IT()
        • +
      • HAL_HASHEx_SHA224_Accmlt_IT()
        • +
      • HAL_HASHEx_SHA256_Accmlt_IT()
        • +
      • +
    • Following aliases have been added (just for clarity sake) as they shall be used at the end of the computation of a multi-buffers message and not at the start: +
        +
      • HAL_HASH_SHA1_Accmlt_End() to be used instead of HAL_HASH_SHA1_Start()
        • +
      • HAL_HASH_MD5_Accmlt_End() to be used instead of HAL_HASH_MD5_Start()
        • +
      • HAL_HASH_SHA1_Accmlt_End_IT() to be used instead of HAL_HASH_SHA1_Start_IT()
        • +
      • HAL_HASH_MD5_Accmlt_End_IT() to be used instead of HAL_HASH_MD5_Start_IT()
        • +
      • HAL_HASHEx_SHA224_Accmlt_End() to be used instead of HAL_HASHEx_SHA224_Start()
        • +
      • HAL_HASHEx_SHA256_Accmlt_End() to be used instead of HAL_HASHEx_SHA256_Start()
        • +
      • HAL_HASHEx_SHA224_Accmlt_End_IT() to be used instead of HAL_HASHEx_SHA224_Start_IT()
        • +
      • HAL_HASHEx_SHA256_Accmlt_End_IT() to be used instead of HAL_HASHEx_SHA256_Start_IT()
        • +
      • +
    • MISRAC-2012 rule R.5.1 (identifiers shall be distinct in the first 31 characters) constrained the naming of the above listed aliases (e.g. HAL_HASHEx_SHA256_Accmlt_End() could not be named HAL_HASHEx_SHA256_Accumulate_End(). Otherwise the name would have conflicted with HAL_HASHEx_SHA256_Accumulate_End_IT()). In order to have aligned names following APIs have been renamed: +
        +
      • HAL_HASH_MD5_Accumulate() renamed HAL_HASH_MD5_Accmlt()
        • +
      • HAL_HASH_SHA1_Accumulate() renamed HAL_HASH_SHA1_Accmlt()
        • +
      • HAL_HASHEx_SHA224_Accumulate() renamed HAL_HASHEx_SHA224_Accmlt()
        • +
      • HAL_HASHEx_SHA256_Accumulate() renamed HAL_HASHEx_SHA256_Accmlt()
        • +
      • +
    • HASH handler state is no more reset to HAL_HASH_STATE_READY once DMA has been started in the following APIs: +
        +
      • HAL_HASH_MD5_Start_DMA()
        • +
      • HAL_HMAC_MD5_Start_DMA()
        • +
      • HAL_HASH_SHA1_Start_DMA()
        • +
      • HAL_HMAC_SHA1_Start_DMA()
        • +
      • +
    • HASH phase state is now set to HAL_HASH_PHASE_READY once the digest has been read in the following APIs: +
        +
      • HASH_IT()
        • +
      • HMAC_Processing()
        • +
      • HASH_Start()
        • +
      • HASH_Finish()
        • +
      • +
    • Case of a large buffer scattered around in memory each piece of which is not necessarily a multiple of 4 bytes in length. +
        +
      • In section “##### How to use this driver #####â€, sub-section "*** Remarks on message length ***" added to provide recommendations to follow in such case.
        • +
      • No modification of the driver as the root-cause is at design-level.
        • +
      • +
    • +
  • HAL CAN update +
      +
    • HAL_CAN_GetRxMessage() update to get the correct value for the RTR (type of frame for the message that will be transmitted) field in the CAN_RxHeaderTypeDef structure.
      • +
    • +
  • HAL DCMI update +
      +
    • Add new HAL_DCMI_ConfigSyncUnmask() API to set embedded synchronization delimiters unmasks.
      • +
    • +
  • HAL RTC update +
      +
    • Following IRQ handlers’ implementation has been aligned with the STM32Cube firmware specification (in case of interrupt lines shared by multiple events, first check the IT enable bit is set then check the IT flag is set too): +
        +
      • HAL_RTC_AlarmIRQHandler()
        • +
      • HAL_RTCEx_WakeUpTimerIRQHandler()
        • +
      • HAL_RTCEx_TamperTimeStampIRQHandler()
        • +
      • +
    • +
  • HAL WWDG update +
      +
    • In “##### WWDG Specific features #####†descriptive comment section: +
        +
      • Maximal prescaler value has been corrected (8 instead of 128).
        • +
      • Maximal APB frequency has been corrected (42MHz instead of 56MHz) and possible timeout values updated.
        • +
      • +
    • +
  • HAL DMA2D update +
      +
    • Add the following API’s to Start DMA2D CLUT Loading. +
        +
      • HAL_DMA2D_CLUTStartLoad() Start DMA2D CLUT Loading.
        • +
      • HAL_DMA2D_CLUTStartLoad_IT() Start DMA2D CLUT Loading with interrupt enabled.
        • +
      • +
    • The following old wrong services will be kept in the HAL DCMI driver for legacy purpose and a specific Note is added: +
        +
      • HAL_DMA2D_CLUTLoad() can be replaced with HAL_DMA2D_CLUTStartLoad()
        • +
      • HAL_DMA2D_CLUTLoad_IT() can be replaced with HAL_DMA2D_CLUTStartLoad_IT()
        • +
      • HAL_DMA2D_ConfigCLUT() can be omitted as the config can be performed using the HAL_DMA2D_CLUTStartLoad() API.
        • +
      • +
    • +
  • HAL SDMMC update +
      +
    • Fix typo in “FileFormatGroup†parameter in the HAL_MMC_CardCSDTypeDef and HAL_SD_CardCSDTypeDef structures
      • +
    • Fix an improve handle state and error management
      • +
    • Rename the defined MMC card capacity type to be more meaningful: +
        +
      • Update MMC_HIGH_VOLTAGE_CARD to MMC LOW_CAPACITY_CARD
        • +
      • Update MMC_DUAL_VOLTAGE_CRAD to MMC_HIGH_CAPACITY_CARD
        • +
      • +
    • Fix management of peripheral flags depending on commands or data transfers +
        +
      • Add new defines “SDIO_STATIC_CMD_FLAGS†and “SDIO_STATIC_DATA_FLAGSâ€
        • +
      • Updates HAL SD and HAL MMC drivers to manage the new SDIO static flags.
        • +
      • +
    • Due to limitation SDIO hardware flow control indicated in Errata Sheet: +
        +
      • In 4-bits bus wide mode, do not use the HAL_SD_WriteBlocks_IT() or HAL_SD_WriteBlocks() APIs otherwise underrun will occur and it isn’t possible to activate the flow control.
        • +
      • Use DMA mode when using 4-bits bus wide mode or decrease the SDIO_CK frequency.
        • +
      • +
    • +
  • HAL UART update +
      +
    • Update UART polling processes to handle efficiently the Lock mechanism +
        +
      • Move the process unlock at the top of the HAL_UART_Receive() and HAL_UART_Transmit() API.
        • +
      • +
    • Fix baudrate calculation error for clock higher than 172Mhz +
        +
      • Add a forced cast on UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros.
        • +
      • Remove useless parenthesis from UART_DIVFRAQ_SAMPLING8(), UART_DIVFRAQ_SAMPLING16(), UART_BRR_SAMPLING8() and UART_BRR_SAMPLING16() macros to solve some MISRA warnings.
        • +
      • +
    • Update UART interruption handler to manage correctly the overrun interrupt +
        +
      • Add in the HAL_UART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • +
      • +
    • Fix baudrate calculation error UART9 and UART10 +
        +
      • In UART_SetConfig() API fix UART9 and UART10 clock source when computing baudrate values by adding a check on these instances and setting clock sourcePCLK2 instead of PCLK1.
        • +
      • +
    • Update UART_SetConfig() API +
        +
      • Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the UART_BRR_SAMPLING8() and UART_BRR_SAMPLING8() macros
        • +
      • +
    • +
  • HAL USART update +
      +
    • Fix baudrate calculation error for clock higher than 172Mhz +
        +
      • Add a forced cast on USART_DIV() macro.
        • +
      • Remove useless parenthesis from USART_DIVFRAQ() macro to solve some MISRA warnings.
        • +
      • +
    • Update USART interruption handler to manage correctly the overrun interrupt +
        +
      • Add in the HAL_USART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • +
      • +
    • Fix baudrate calculation error UART9 and UART10 +
        +
      • In USART_SetConfig() API fix UART9 and UART10 clock source when computing baudrate values by adding a check on these instances and setting clock sourcePCLK2 instead of PCLK1.
        • +
      • +
    • Update USART_SetConfig() API +
        +
      • Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the USART_BRR() macro
        • +
      • +
    • +
  • HAL IRDA update +
      +
    • Fix baudrate calculation error for clock higher than 172Mhz +
        +
      • Add a forced cast on IRDA_DIV() macro.
        • +
      • Remove useless parenthesis from IRDA_DIVFRAQ() macro to solve some MISRA warnings.
        • +
      • +
    • Update IRDA interruption handler to manage correctly the overrun interrupt +
        +
      • Add in the HAL_IRDA_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • +
      • +
    • Fix baudrate calculation error UART9 and UART10 +
        +
      • In IRDA_SetConfig() API fix UART9 and UART10 clock source when computing baudrate values by adding a check on these instances and setting clock sourcePCLK2 instead of PCLK1.
        • +
      • +
    • Update IRDA_SetConfig() API +
        +
      • Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the IRDA_BRR() macro
        • +
      • +
    • +
  • HAL SMARTCARD update +
      +
    • Fix baudrate calculation error for clock higher than 172Mhz +
        +
      • Add a forced cast on SMARTCARD_DIV() macro.
        • +
      • Remove useless parenthesis from SMARTCARD_DIVFRAQ() macro to solve some MISRA warnings.
        • +
      • +
    • Update SMARTCARD interruption handler to manage correctly the overrun interrupti +
        +
      • Add in the HAL_SMARTCARD_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • +
      • +
    • Update SMARTCARD_SetConfig() API +
        +
      • Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the SMARTCARD_BRR() macro
        • +
      • +
    • +
  • HAL TIM update +
      +
    • Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay +
        +
      • __HAL_TIM_ENABLE_OCxFAST() and __HAL_TIM_DISABLE_OCxFAST().
        • +
      • +
    • Update Encoder interface mode to keep TIM_CCER_CCxNP bits low +
        +
      • Add TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine encoder input polarity.
        • +
      • Add IS_TIM_ENCODERINPUT_POLARITY() macro to check the encoder input polarity.
        • +
      • Update HAL_TIM_Encoder_Init() API +
          +
        • Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.
          • +
        • +
      • +
    • Update TIM remapping input configuration in HAL_TIMEx_RemapConfig() API +
        +
      • Remove redundant check on LPTIM_OR_TIM5_ITR1_RMP bit and replace it by check on LPTIM_OR_TIM9_ITR1_RMP bit.
        • +
      • +
    • Update HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors and assert fails when using some TIM instances as input trigger. +
        +
      • Replace IS_TIM_SYNCHRO_INSTANCE() macro by IS_TIM_MASTER_INSTANCE() macro.
        • +
      • Add IS_TIM_SLAVE_INSTANCE() macro to check on TIM_SMCR_MSM bit.
        • +
      • +
    • Add lacking TIM input remapping definition +
        +
      • Add LL_TIM_TIM11_TI1_RMP_SPDIFRX and LL_TIM_TIM2_ITR1_RMP_ETH_PTP.
        • +
      • Add lacking definition for linked LPTIM_TIM input trigger remapping +
          +
        • Add following definitions : LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO, LL_TIM_TIM9_ITR1_RMP_LPTIM, LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO, LL_TIM_TIM5_ITR1_RMP_LPTIM, LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO and LL_TIM_TIM1_ITR2_RMP_LPTIM.
          • +
        • Add a new mechanism in LL_TIM_SetRemap() API to remap TIM1, TIM9, and TIM5 input triggers mapped on LPTIM register.
          • +
        • +
      • +
    • +
  • HAL LPTIM update +
      +
    • Add a polling mechanism to check on LPTIM_FLAG_XXOK flags in different API +
        +
      • Add LPTIM_WaitForFlag() API to wait for flag set.
        • +
      • Perform new checks on HAL_LPTIM_STATE_TIMEOUT.
        • +
      • +
    • Add lacking definitions of LPTIM input trigger remapping and its related API +
        +
      • LL_LPTIM_INPUT1_SRC_PAD_AF, LL_LPTIM_INPUT1_SRC_PAD_PA4, LL_LPTIM_INPUT1_SRC_PAD_PB9 and LL_LPTIM_INPUT1_SRC_TIM_DAC.
        • +
      • Add a new API LL_LPTIM_SetInput1Src() to access to the LPTIM_OR register and remap the LPTIM input trigger.
        • +
      • +
    • Perform a new check on indirect EXTI23 line associated to the LPTIM wake up timer +
        +
      • Condition the use of the LPTIM Wake-up Timer associated EXTI line configuration’s macros by EXTI_IMR_MR23 bit in different API : +
          +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE/DDISABLE_FALLING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT()
          • +
        • +
      • Update HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_LPTIM_Counter_Start_IT() and HAL_LPTIM_Counter_Stop_IT() API by adding Enable/Disable rising edge trigger on the LPTIM Wake-up Timer Exti line.
        • +
      • Add __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() in the end of the HAL_LPTIM_IRQHandler() API conditioned by EXTI_IMR_MR23 bit.
        • +
      • +
    • +
  • HAL I2C update +
      +
    • Update HAL_I2C_EV_IRQHandler() API to fix I2C send break issue +
        +
      • Add additional check on hi2c->hdmatx, hdmatx->XferCpltCallback, hi2c->hdmarx, hdmarx->XferCpltCallback in I2C_Master_SB() API to avoid enabling DMA request when IT mode is used.
        • +
      • +
    • Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C memory IT processes +
        +
      • Add stop condition generation when NACK occurs.
        • +
      • +
    • Update HAL_I2C_Init() API to force software reset before setting new I2C configuration
      • +
    • Update HAL I2C processes to report ErrorCode when wrong I2C start condition occurs +
        +
      • Add new ErrorCode define: HAL_I2C_WRONG_START
        • +
      • Set ErrorCode parameter in I2C handle to HAL_I2C_WRONG_START
        • +
      • +
    • Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer). +
        +
      • Add additional check on hi2c->hdmtx and hi2c->hdmarx before resetting DMA Tx/Rx complete callbacks
        • +
      • +
    • +
  • HAL FMPI2C update +
      +
    • Fix HAL FMPI2C slave interrupt handling issue with I2C sequential transfers. +
        +
      • Update FMPI2C_Slave_ISR_IT() and FMPI2C_Slave_ISR_DMA() APIs to check on STOP condition and handle it before clearing the ADDR flag
        • +
      • +
    • +
  • HAL NAND update +
      +
    • Update HAL_NAND_Write_Page_8b(), HAL_NAND_Write_Page_16b() and HAL_NAND_Write_SpareArea_16b() to manage correctly the time out condition.
      • +
    • +
  • HAL SAI update +
      +
    • Optimize SAI_DMATxCplt() and SAI_DMARxCplt() APIs to check on “Mode†parameter instead of CIRC bit in the CR register.
      • +
    • Remove unused SAI_FIFO_SIZE define
      • +
    • Update HAL_SAI_Receive_DMA() programming sequence to be inline with reference manual
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
  • HAL I2C update +
      +
    • Fix I2C send break issue in IT processes +
        +
      • Add additional check on hi2c->hdmatx and hi2c->hdmarx to avoid the DMA request enable when IT mode is used.
        • +
      • +
    • +
  • HAL SPI update +
      +
    • Update to implement Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode
      • +
    • +
  • LL LPTIM update +
      +
    • Fix compilation errors with LL_LPTIM_WriteReg() and LL_LPTIM_ReadReg() macros
      • +
    • +
  • HAL SDMMC update +
      +
    • Fix preprocessing compilation issue with SDIO STA STBITERR interrupt
      • +
    • +
  • HAL/LL USB update +
      +
    • Updated USB_WritePacket(), USB_ReadPacket() APIs to prevent compilation warning with GCC GNU v8.2.0
      • +
    • Rework USB_EPStartXfer() API to enable the USB endpoint before unmasking the TX FiFo empty interrupt in case DMA is not used
      • +
    • USB HAL_HCD_Init() and HAL_PCD_Init() APIs updated to avoid enabling USB DMA feature for OTG FS instance, USB DMA feature is available only on OTG HS Instance
      • +
    • Remove duplicated line in hal_hcd.c header file comment section
      • +
    • Rework USB HAL driver to use instance PCD_SPEED_xxx, HCD_SPEED_xx speeds instead of OTG register Core speed definition during the instance initialization
      • +
    • Software Quality improvement with a fix of CodeSonar warning on PCD_Port_IRQHandler() and HCD_Port_IRQHandler() interrupt handlers
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
  • General updates to fix CodeSonar compilation warnings
    • +
  • General updates to fix SW4STM32 compilation errors under Linux
    • +
  • General updates to fix the user manual .chm files
    • +
  • Add support of HAL callback registration feature
    • +
  • Add new HAL EXTI driver
    • +
  • Add new HAL SMBUS driver
    • +
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions +
      +
    • Rework of HAL CRYP driver (compatibility break) +
        +
      • HAL CRYP driver has been redesigned with new API’s, to bypass limitations on data Encryption/Decryption management present with previous HAL CRYP driver version.
        • +
      • The new HAL CRYP driver is the recommended version. It is located as usual in Drivers/STM32F4xx_HAL_Driver/Src and Drivers/STM32f4xx_HAL_Driver/Inc folders. It can be enabled through switch HAL_CRYP_MODULE_ENABLED in stm32f4xx_hal_conf.h
        • +
      • The legacy HAL CRYP driver is no longer supported.
        • +
      • +
    • Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure to allow the possibilities to enable or disable the TIM Auto Reload Preload.
      • +
    • +
  • HAL/LL Generic update +
      +
    • Add support of HAL callback registration feature +
        +
      • The feature disabled by default is available for the following HAL drivers: +
          +
        • ADC, CAN, CEC, CRYP, DAC, DCMI, DFSDM, DMA2D, DSI, ETH, HASH, HCD, I2C, FMPI2C, SMBUS, UART, USART, IRDA, SMARTCARD, LPTIM, LTDC, MMC, NAND, NOR, PCCARD, PCD, QSPI, RNG, RTC, SAI, SD, SDRAM, SRAM, SPDIFRX, SPI, I2S, TIM, and WWDG
          • +
        • +
      • The feature may be enabled individually per HAL PPP driver by setting the corresponding definition USE_HAL_PPP_REGISTER_CALLBACKS to 1U in stm32f4xx_hal_conf.h project configuration file (template file stm32f4xx_hal_conf_template.h available from Drivers/STM32F4xx_HAL_Driver/Inc)
        • +
      • Once enabled , the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback().
        • +
      • +
    • General updates to fix MISRA 2012 compilation errors +
        +
      • Replace HAL_GetUID() API by HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2()
        • +
      • HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() macros implementation update
        • +
      • “stdio.h†include updated with “stddef.hâ€
        • +
      • +
    • +
  • HAL GPIO update +
      +
    • Add missing define for SPI3 alternate function “GPIO_AF5_SPI3†for STM32F401VE devices
      • +
    • Remove “GPIO_AF9_TIM14†from defined alternate function list for STM32F401xx devices
      • +
    • HAL_GPIO_TogglePin() reentrancy robustness improvement
      • +
    • HAL_GPIO_DeInit() API update to avoid potential pending interrupt after call
      • +
    • Update GPIO_GET_INDEX() API for more compliance with STM32F412Vx/STM32F412Rx/STM32F412Cx devices
      • +
    • Update GPIO_BRR registers with Reference Manual regarding registers and bit definition values
      • +
    • +
  • HAL CRYP update +
      +
    • The CRYP_InitTypeDef is no more supported, changed by CRYP_ConfigTypedef to allow changing parameters using HAL_CRYP_setConfig() API without reinitialize the CRYP IP using the HAL_CRYP_Init() API
      • +
    • New parameters added in the CRYP_ConfigTypeDef structure: B0 and DataWidthUnit
      • +
    • Input data size parameter is added in the CRYP_HandleTypeDef structure
      • +
    • Add new APIs to manage the CRYP configuration: +
        +
      • HAL_CRYP_SetConfig()
        • +
      • HAL_CRYP_GetConfig()
        • +
      • +
    • Add new APIs to manage the Key derivation: +
        +
      • HAL_CRYPEx_EnableAutoKeyDerivation()
        • +
      • HAL_CRYPEx_DisableAutoKeyDerivation()
        • +
      • +
    • Add new APIs to encrypt and decrypt data: +
        +
      • HAL_CRYP_Encypt()
        • +
      • HAL_CRYP_Decypt()
        • +
      • HAL_CRYP_Encypt_IT()
        • +
      • HAL_CRYP_Decypt_IT()
        • +
      • HAL_CRYP_Encypt_DMA()
        • +
      • HAL_CRYP_Decypt_DMA()
        • +
      • +
    • Add new APIs to generate TAG: +
        +
      • HAL_CRYPEx_AES__GCM___GenerateAuthTAG()
        • +
      • HAL_CRYPEx_AES__CCM___Generago teAuthTAG()
        • +
      • +
    • +
  • HAL LPTIM update +
      +
    • Remove useless LPTIM Wakeup EXTI related macros from HAL_LPTIM_TimeOut_Start_IT() API
      • +
    • +
  • HAL I2C update +
      +
    • I2C API changes for MISRA-C 2012 compliance: +
        +
      • Rename HAL_I2C_Master_Sequential_Transmit_IT() to HAL_I2C_Master_Seq_Transmit_IT()
        • +
      • Rename HAL_I2C_Master_Sequentiel_Receive_IT() to HAL_I2C_Master_Seq_Receive_IT()
        • +
      • Rename HAL_I2C_Slave_Sequentiel_Transmit_IT() to HAL_I2C_Slave_Seq_Transmit_IT()
        • +
      • Rename HAL_I2C_Slave_Sequentiel_Receive_DMA() to HAL_I2C_Slave_Seq_Receive_DMA()
        • +
      • +
    • SMBUS defined flags are removed as not used by the HAL I2C driver +
        +
      • I2C_FLAG_SMBALERT
        • +
      • I2C_FLAG_TIMEOUT
        • +
      • I2C_FLAG_PECERR
        • +
      • I2C_FLAG_SMBHOST
        • +
      • I2C_FLAG_SMBDEFAULT
        • +
      • +
    • Add support of I2C repeated start feature in DMA Mode: +
        +
      • With the following new API’s +
          +
        • HAL_I2C_Master_Seq_Transmit_DMA()
          • +
        • HAL_I2C_Master_Seq_Receive_DMA()
          • +
        • HAL_I2C_Slave_Seq_Transmit_DMA()
          • +
        • HAL_I2C_Slave_Seq_Receive_DMA()
          • +
        • +
      • +
    • Add new I2C transfer options to easy manage the sequential transfers +
        +
      • I2C_FIRST_AND_NEXT_FRAME
        • +
      • I2C_LAST_FRAME_NO_STOP
        • +
      • I2C_OTHER_FRAME
        • +
      • I2C_OTHER_AND_LAST_FRAME
        • +
      • +
    • +
  • HAL FMPI2C update +
      +
    • I2C API changes for MISRA-C 2012 compliance: +
        +
      • Rename HAL_FMPI2C_Master_Sequential_Transmit_IT() to HAL_FMPI2C_Master_Seq_Transmit_IT()
        • +
      • Rename HAL_FMPI2C_Master_Sequentiel_Receive_IT() to HAL_FMPI2C_Master_Seq_Receive_IT()
        • +
      • Rename HAL_FMPI2C_Master_Sequentiel_Transmit_DMA() to HAL_FMPI2C_Master_Seq_Transmit_DMA()
        • +
      • Rename HAL_FMPI2C_Master_Sequentiel_Receive_DMA() to HAL_FMPI2C_Master_Seq_Receive_DMA()
        • +
      • +
    • Rename FMPI2C_CR1_DFN to FMPI2C_CR1_DNF for more compliance with Reference Manual regarding registers and bit definition naming
      • +
    • Add support of I2C repeated start feature in DMA Mode: +
        +
      • With the following new API’s +
          +
        • HAL_FMPI2C_Master_Seq_Transmit_DMA()
          • +
        • HAL_FMPI2C_Master_Seq_Receive_DMA()
          • +
        • HAL_FMPI2C_Slave_Seq_Transmit_DMA()
          • +
        • HAL_FMPI2C_Slave_Seq_Receive_DMA()
          • +
        • +
      • +
    • +
  • HAL FLASH update +
      +
    • Update the FLASH_OB_GetRDP() API to return the correct RDP level
      • +
    • +
  • HAL RCC update +
      +
    • Remove GPIOD CLK macros for STM32F412Cx devices (X = D)
      • +
    • Remove GPIOE CLK macros for STM32F412Rx\412Cx devices: (X = E)
      • +
    • Remove GPIOF/G CLK macros for STM32F412Vx\412Rx\412Cx devices (X= F or G) +
        +
      • __HAL_RCC_GPIOX_CLK_ENABLE()
        • +
      • __HAL_RCC_GPIO__X___CLK_DISABLE()
        • +
      • __HAL_RCC_GPIO__X___IS_CLK_ENABLED()
        • +
      • __HAL_RCC_GPIO__X___IS_CLK_DISABLED()
        • +
      • __HAL_RCC_GPIO__X___FORCE_RESET()
        • +
      • +
    • +
  • HAL RNG update +
      +
    • Update to manage RNG error code: +
        +
      • Add ErrorCode parameter in HAL RNG Handler structure
        • +
      • +
    • +
  • LL ADC update +
      +
    • Add __LL_ADC_CALC_TEMPERATURE() helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
      • +
    • Fix ADC channels configuration issues on STM32F413xx/423xx devices +
        +
      • To allow possibility to switch between VBAT and TEMPERATURE channels configurations
        • +
      • HAL_ADC_Start(), HAL_ADC_Start_IT() and HAL_ADC_Start_DMA() update to prevention from starting ADC2 or ADC3 once multimode is enabled
        • +
      • +
    • +
  • HAL DFSDM update +
      +
    • General updates to be compliant with DFSDM bits naming used in CMSIS files.
      • +
    • +
  • HAL CAN update +
      +
    • Update possible values list for FilterActivation parameter in CAN_FilterTypeDef structure +
        +
      • CAN_FILTER_ENABLE instead of ENABLE
        • +
      • CAN_FILTER_DISABLE instead of DISABLE
        • +
      • +
    • +
  • HAL CEC update +
      +
    • Update HAL CEC State management method: +
        +
      • Remove HAL_CEC_StateTypeDef structure parameters
        • +
      • Add new defines for CEC states
        • +
      • +
    • +
  • HAL DMA update +
      +
    • Add clean of callbacks in HAL_DMA_DeInit() API
      • +
    • +
  • HAL DMA2D update +
      +
    • Remove unused DMA2D_ColorTypeDef structure to be compliant with MISRAC 2012 Rule 2.3
      • +
    • General update to use dedicated defines for DMA2D_BACKGROUND_LAYER and DMA2D_FOREGROUND_LAYER instead of numerical values: 0/1.
      • +
    • +
  • HAL DSI update +
      +
    • Fix read multibyte issue: remove extra call to HAL_UNLOCK from DSI_ShortWrite() API.
      • +
    • +
  • HAL/LL RTC update +
      +
    • HAL/ LL drivers optimization +
        +
      • HAL driver: remove unused variables
        • +
      • LL driver: getter APIs optimization
        • +
      • +
    • +
  • HAL PWR update +
      +
    • Remove the following API’s as feature not supported by STM32F469xx/479xx devices +
        +
      • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
        • +
      • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
        • +
      • +
    • +
  • HAL SPI update +
      +
    • Update HAL_SPI_StateTypeDef structure to add new state: HAL_SPI_STATE_ABORT
      • +
    • +
  • HAL/LL TIM update +
      +
    • Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure +
        +
      • Refer to the TIM examples to identify the changes
        • +
      • +
    • Move the following TIM structures from stm32f4xx_hal_tim_ex.h into stm32f4xx_hal_tim.h +
        +
      • TIM_MasterConfigTypeDef
        • +
      • TIM_BreakDeadTimeConfigTypeDef
        • +
      • +
    • Add new TIM Callbacks API’s: +
        +
      • HAL_TIM_PeriodElapsedHalfCpltCallback()
        • +
      • HAL_TIM_IC_CaptureHalfCpltCallback()
        • +
      • HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
        • +
      • HAL_TIM_TriggerHalfCpltCallback()
        • +
      • +
    • TIM API changes for MISRA-C 2012 compliance: +
        +
      • Rename HAL_TIM_SlaveConfigSynchronization to HAL_TIM_SlaveConfigSynchro
        • +
      • Rename HAL_TIM_SlaveConfigSynchronization_IT to HAL_TIM_SlaveConfigSynchro_IT
        • +
      • Rename HAL_TIMEx_ConfigCommutationEvent to HAL_TIMEx_ConfigCommutEvent
        • +
      • Rename HAL_TIMEx_ConfigCommutationEvent_IT to HAL_TIMEx_ConfigCommutEvent_IT
        • +
      • Rename HAL_TIMEx_ConfigCommutationEvent_DMA to HAL_TIMEx_ConfigCommutEvent_DMA
        • +
      • Rename HAL_TIMEx_CommutationCallback to HAL_TIMEx_CommutCallback
        • +
      • Rename HAL_TIMEx_DMACommutationCplt to TIMEx_DMACommutationCplt
        • +
      • +
    • +
  • HAL/LL USB update +
      +
    • Rework USB interrupt handler and improve HS DMA support in Device mode
      • +
    • Fix BCD handling fr OTG instance in device mode
      • +
    • cleanup reference to low speed in device mode
      • +
    • allow writing TX FIFO in case of transfer length is equal to available space in the TX FIFO
      • +
    • Fix Toggle OUT interrupt channel in host mode
      • +
    • Update USB OTG max number of endpoints (6 FS and 9 HS instead of 5 and 8)
      • +
    • Update USB OTG IP to enable internal transceiver when starting USB device after committee BCD negotiation
      • +
    • +
  • LL IWDG update +
      +
    • Update LL inline macros to use IWDGx parameter instead of IWDG instance defined in CMSIS device
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
  • HAL update +
      +
    • Update UNUSED() macro implementation to avoid GCC warning +
        +
      • The warning is detected when the UNUSED() macro is called from C++ file
        • +
      • +
    • Update to make RAMFUNC define as generic type instead of HAL_StatusTypdef type.
      • +
    • +
  • HAL FLASH update +
      +
    • Update the prototypes of the following APIs after change on RAMFUNC defines +
        +
      • HAL_FLASHEx_StopFlashInterfaceClk()
        • +
      • HAL_FLASHEx_StartFlashInterfaceClk()
        • +
      • HAL_FLASHEx_EnableFlashSleepMode()
        • +
      • HAL_FLASHEx_DisableFlashSleepMode()
        • +
      • +
    • +
  • HAL SAI update +
      +
    • Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions +
      +
    • Rework of HAL CAN driver (compatibility break) +
        +
      • A new HAL CAN driver has been redesigned with new APIs, to bypass limitations on CAN Tx/Rx FIFO management present with previous HAL CAN driver version.
        • +
      • The new HAL CAN driver is the recommended version. It is located as usual in Drivers/STM32F4xx_HAL_Driver/Src and Drivers/STM32f4xx_HAL_Driver/Inc folders. It can be enabled through switch HAL_CAN_MODULE_ENABLED in stm32f4xx_hal_conf.h
        • +
      • The legacy HAL CAN driver is also present in the release in Drivers/STM32F4xx_HAL_Driver/Src/Legacy and Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software compatibility reasons. Its usage is not recommended as deprecated. It can however be enabled through switch HAL_CAN_LEGACY_MODULE_ENABLED in stm32f4xx_hal_conf.h
        • +
      • +
    • +
  • HAL update +
      +
    • Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms : +
        +
      • Add the following API’s : +
          +
        • HAL_GetTickPrio(): Returns a tick priority.
          • +
        • HAL_SetTickFreq(): Sets new tick frequency.
          • +
        • HAL_GetTickFreq(): Returns tick frequency.
          • +
        • +
      • Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and 1KHz (default).
        • +
      • +
    • +
  • HAL CAN update +
      +
    • Fields of CAN_InitTypeDef structure are reworked: +
        +
      • SJW to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to TransmitFifoPriority
        • +
      • +
    • HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API’s
      • +
    • HAL_CAN_Transmit() is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.
      • +
    • HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then HAL_CAN_AddTxMessage() for place Tx request.
      • +
    • HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage() to get Rx message.
      • +
    • HAL_CAN_Receive_IT() is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then HAL_CAN_GetRxMessage() in the receivecallback to get Rx message
      • +
    • HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()
      • +
    • HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback().
      • +
    • HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback().
      • +
    • More complete “How to use the new driver†is detailed in the driver header section itself.
      • +
    • +
  • HAL FMPI2C update +
      +
    • Add new option FMPI2C_LAST_FRAME_NO_STOP for the sequential transfer management +
        +
      • This option allows to manage a restart condition after several call of the same master sequential interface.
        • +
      • +
    • +
  • HAL RCC update +
      +
    • Add new HAL macros +
        +
      • __HAL_RCC_GET_RTC_SOURCE() allowing to get the RTC clock source
        • +
      • __HAL_RCC_GET_RTC_HSE_PRESCALER() allowing to get the HSE clock divider for RTC peripheral
        • +
      • +
    • Ensure reset of CIR and CSR registers when issuing HAL_RCC_DeInit()/LL_RCC_DeInit functions
      • +
    • Update HAL_RCC_OscConfig() to keep backup domain enabled when configuring respectively LSE and RTC clock source
      • +
    • Add new HAL interfaces allowing to control the activation or deactivation of PLLI2S and PLLSAI: +
        +
      • HAL_RCCEx_EnablePLLI2S()
        • +
      • HAL_RCCEx_DisablePLLI2S()
        • +
      • HAL_RCCEx_EnablePLLSAI()
        • +
      • HAL_RCCEx_DisablePLLSAI()
        • +
      • +
    • +
  • LL RCC update +
      +
    • Add new LL RCC macro +
        +
      • LL_RCC_PLL_SetMainSource() allowing to configure PLL main clock source
        • +
      • +
    • +
  • LL FMC / LL FSMC update +
      +
    • Add clear of the PTYP bit to select the PCARD mode in FMC_PCCARD_Init() / FSMC_PCCARD_Init()
      +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
  • Fix compilation warning with GCC compiler
    • +
  • Remove Date and version from header files
    • +
  • Update HAL drivers to refer to the new CMSIS bit position defines instead of usage the POSITION_VAL() macro
    • +
  • HAL Generic update +
      +
    • stm32f4xx_hal_def.h file changes: +
        +
      • Update __weak and __packed defined values for ARM compiler
        • +
      • Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler
        • +
      • +
    • stm32f4xx_ll_system.h file: add LL_SYSCFG_REMAP_SDRAM define
      • +
    • +
  • HAL ADC update +
      +
    • Fix wrong definition of ADC channel temperature sensor for STM32F413xx and STM32F423xx devices.
      • +
    • +
  • HAL DMA update +
      +
    • Update values for the following defines: DMA_FLAG_FEIF0_4 and DMA_FLAG_DMEIF0_4
      • +
    • +
  • HAL DSI update +
      +
    • Fix Extra warning with SW4STM32 compiler
      • +
    • Fix DSI display issue when using EWARM w/ high level optimization
      • +
    • Fix MISRAC errors
      • +
    • +
  • HAL FLASH update +
      +
    • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
      • +
    • +
  • HAL FMPI2C update +
      +
    • Update Interface APIs headers to remove confusing message about device address
      • +
    • Update FMPI2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags
      • +
    • Update FMPI2C_TransferConfig() to fix wrong bit management.
      • +
    • Update code comments to use DMA stream instead of DMA channel
      • +
    • +
  • HAL PWR update +
      +
    • HAL_PWR_EnableWakeUpPin() update description to add support of PWR_WAKEUP_PIN2 and PWR_WAKEUP_PIN3
      • +
    • +
  • HAL NOR update +
      +
    • Add the support of STM32F412Rx devices
      • +
    • +
  • HAL I2C update +
      +
    • Update Interface APIs headers to remove confusing message about device address
      • +
    • Update I2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs to fix bad Handling of NACK in I2C master receive process.
      • +
    • +
  • HAL RCC update +
      +
    • Update HAL_RCC_GetOscConfig() API to: +
        +
      • set PLLR in the RCC_OscInitStruct
        • +
      • check on null pointer
        • +
      • +
    • Update HAL_RCC_ClockConfig() API to: +
        +
      • check on null pointer
        • +
      • optimize code size by updating the handling method of the SWS bits
        • +
      • update to use __HAL_FLASH_GET_LATENCY() flash macro instead of using direct register access to LATENCY bits in FLASH ACR register.
        • +
      • +
    • Update HAL_RCC_DeInit() and LL_RCC_DeInit() APIs to +
        +
      • Be able to return HAL/LL status
        • +
      • Add checks for HSI, PLL and PLLI2S ready before modifying RCC CFGR registers
        • +
      • Clear all interrupt flags
        • +
      • Initialize systick interrupt period
        • +
      • +
    • Update HAL_RCC_GetSysClockFreq() to avoid risk of rounding error which may leads to a wrong returned value.
      • +
    • +
  • HAL RNG update +
      +
    • HAL_RNG_Init() remove Lock()/Unlock()
      • +
    • +
  • HAL MMC update +
      +
    • HAL_MMC_Erase() API: add missing () to fix compilation warning detected with SW4STM32 when extra feature is enabled.
      • +
    • +
  • HAL RTC update +
      +
    • HAL_RTC_Init() API: update to force the wait for synchro before setting TAFCR register when BYPSHAD bit in CR register is 0.
      • +
    • +
  • HAL SAI update +
      +
    • Update HAL_SAI_DMAStop() API to flush fifo after disabling SAI
      • +
    • +
  • HAL I2S update +
      +
    • Update I2S DMA fullduplex process to handle I2S Rx and Tx DMA Half transfer complete callback
      • +
    • +
  • HAL TIM update +
      +
    • Update HAL_TIMEx_OCN_xxxx() and HAL_TIMEx_PWMN_xxx() API description to remove support of TIM_CHANNEL_4
      • +
    • +
  • LL DMA update +
      +
    • Update to clear DMA flags using WRITE_REG() instead SET_REG() API to avoid read access to the IFCR register that is write only.
      • +
    • +
  • LL RTC update +
      +
    • Fix warning with static analyzer
      • +
    • +
  • LL USART update +
      +
    • Add assert macros to check USART BaudRate register
      • +
    • +
  • LL I2C update +
      +
    • Rename IS_I2C_CLOCK_SPEED() and IS_I2C_DUTY_CYCLE() respectively to IS_LL_I2C_CLOCK_SPEED() and IS_LL_I2C_DUTY_CYCLE() to avoid incompatible macros redefinition.
      • +
    • +
  • LL TIM update +
      +
    • Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in TIM CR1 register instead of setting it.
      • +
    • Update LL_TIM_DisableUpdateEvent() API to set UDIS bit in TIM CR1 register instead of clearing it.
      • +
    • +
  • LL USART update +
      +
    • Fix MISRA error w/ IS_LL_USART_BRR() macro
      • +
    • Fix wrong check when UART10 instance is used
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Update CHM UserManuals to support LL drivers
    • +
  • General updates to fix known defects and enhancements implementation
    • +
  • HAL CAN update +
      +
    • Add management of overrun error.
      • +
    • Allow possibility to receive messages from the 2 RX FIFOs in parallel via interrupt.
      • +
    • Fix message lost issue with specific sequence of transmit requests.
      • +
    • Handle transmission failure with error callback, when NART is enabled.
      • +
    • Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when timeout is reached
      • +
    • +
  • HAL PWR update +
      +
    • HAL_PWREx_EnterUnderDriveSTOPMode() API: remove check on UDRDY flag
      • +
    • +
  • LL ADC update +
      +
    • Fix wrong ADC group injected sequence configuration +
        +
      • LL_ADC_INJ_SetSequencerRanks() and LL_ADC_INJ_GetSequencerRanks() API’s update to take in consideration the ADC number of conversions
        • +
      • Update the defined values for ADC group injected seqencer ranks
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add Low Layer drivers allowing performance and footprint optimization +
      +
    • Low Layer drivers APIs provide register level programming: require deep knowledge of peripherals described in STM32F4xx Reference Manuals
      • +
    • Low Layer drivers are available for: ADC, Cortex, CRC, DAC, DMA, DMA2D, EXTI, GPIO, I2C, IWDG, LPTIM, PWR, RCC, RNG, RTC, SPI, TIM, USART, WWDG peripherals and additional Low Level Bus, System and Utilities APIs.
      • +
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f4xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f4xx_ll_ppp.h file must be included in user code.
      • +
    • +
  • General updates to fix known defects and enhancements implementation
    • +
  • Fix extra warnings with GCC compiler
    • +
  • HAL drivers clean up: remove double casting ‘uint32_t’ and ‘U’
    • +
  • Add new HAL MMC driver
    • +
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
    • +
  • HAL SD update +
      +
    • Overall rework of the driver for a more efficient implementation +
        +
      • Modify initialization API and structures
        • +
      • Modify Read / Write sequences: separate transfer process and SD Cards state management
        • +
      • Adding interrupt mode for Read / Write operations
        • +
      • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
        • +
      • +
    • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
      • +
    • +
  • HAL NAND update +
      +
    • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
      • +
    • Add new HAL_NAND_ConfigDevice API
      • +
    • +
  • HAL DFSDM update +
      +
    • Add support of Multichannel Delay feature +
        +
      • Add HAL_DFSDM_ConfigMultiChannelDelay API
        • +
      • The following APIs are moved to internal static functions: HAL_DFSDM_ClockIn_SourceSelection, HAL_DFSDM_ClockOut_SourceSelection, HAL_DFSDM_DataInX_SourceSelection (X=0,2,4,6), HAL_DFSDM_BitStreamClkDistribution_Config
        • +
      • +
    • +
  • HAL I2S update +
      +
    • Add specific callback API to manage I2S full duplex end of transfer process: +
        +
      • HAL_I2S_TxCpltCallback() and HAL_I2S_RxCpltCallback() API’s will be replaced with only HAL_I2SEx_TxRxCpltCallback() API.
        • +
      • +
    • +
  • HAL update +
      +
    • Modify default HAL_Delay implementation to guarantee minimum delay
      • +
    • +
  • HAL Cortex update +
      +
    • Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f4xx_hal_cortex.h to stm32f4xx_hal_cortex.c
      • +
    • Clear the whole MPU control register in HAL_MPU_Disable() API
      • +
    • +
  • HAL FLASH update +
      +
    • IS_FLASH_ADDRESS() macro update to support OTP range
      • +
    • FLASH_Program_DoubleWord(): Replace 64-bit accesses with 2 double-words operations
      • +
    • +
  • LL GPIO update +
      +
    • Update IS_GPIO_PIN() macro implementation to be more safe
      • +
    • +
  • LL RCC update +
      +
    • Update IS_RCC_PLLQ_VALUE() macro implementation: the minimum accepted value is 2 instead of 4
      • +
    • Rename RCC_LPTIM1CLKSOURCE_PCLK define to RCC_LPTIM1CLKSOURCE_PCLK1
      • +
    • Fix compilation issue w/ __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() and __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() macros for STM32F401xx devices
      • +
    • Add the following is clock enabled macros for STM32F401xx devices +
        +
      • __HAL_RCC_SDIO_IS_CLK_ENABLED()
        • +
      • __HAL_RCC_SPI4_IS_CLK_ENABLED()
        • +
      • __HAL_RCC_TIM10_IS_CLK_ENABLED()
        • +
      • +
    • Add the following is clock enabled macros for STM32F410xx devices +
        +
      • __HAL_RCC_CRC_IS_CLK_ENABLED()
        • +
      • __HAL_RCC_RNG_IS_CLK_ENABLED()
        • +
      • +
    • Update HAL_RCC_DeInit() to reset the RCC clock configuration to the default reset state.
      • +
    • Remove macros to configure BKPSRAM from STM32F401xx devices
      • +
    • Update to refer to AHBPrescTable[] and APBPrescTable[] tables defined in system_stm32f4xx.c file instead of APBAHBPrescTable[] table.
      • +
    • +
  • HAL FMPI2C update +
      +
    • Add FMPI2C_FIRST_AND_NEXT_FRAME define in Sequential Transfer Options
      • +
    • +
  • HAL ADC update +
      +
    • HAL_ADCEx_InjectedConfigChannel(): update the external trigger injected condition
      • +
    • +
  • HAL DMA update +
      +
    • HAL_DMA_Init(): update to check compatibility between FIFO threshold level and size of the memory burst
      • +
    • +
  • HAL QSPI update +
      +
    • QSPI_HandleTypeDef structure: Update transfer parameters on uint32_t instead of uint16_t
      • +
    • +
  • HAL UART/USART/IrDA/SMARTCARD update +
      +
    • DMA Receive process; the code has been updated to clear the USART OVR flag before enabling DMA receive request.
      • +
    • UART_SetConfig() update to manage correctly USART6 instance that is not available on STM32F410Tx devices
      • +
    • +
  • HAL CAN update +
      +
    • Remove Lock mechanism from HAL_CAN_Transmit_IT() and HAL_CAN_Receive_IT() processes
      • +
    • +
  • HAL TIM update +
      +
    • Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() macro to disable Master output without check on TIM channel state.
      • +
    • Update HAL_TIMEx_ConfigBreakDeadTime() to fix TIM BDTR register corruption.
      • +
    • +
  • HAL I2C update +
      +
    • Update HAL_I2C_Master_Transmit() and HAL_I2C_Slave_Transmit() to avoid sending extra bytes at the end of the transmit processes
      • +
    • Update HAL_I2C_Mem_Read() API to fix wrong check on misused parameter “Sizeâ€
      • +
    • Update I2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs to enhance Master sequential reception process.
      • +
    • +
  • HAL SPI update +
      +
    • Add transfer abort APIs and associated callbacks in interrupt mode +
        +
      • HAL_SPI_Abort()
        • +
      • HAL_SPI_Abort_IT()
        • +
      • HAL_SPI_AbortCpltCallback()
        • +
      • +
    • +
  • HAL I2S update +
      +
    • Add specific callback API to manage I2S full duplex end of transfer process: +
        +
      • HAL_I2S_TxCpltCallback() and HAL_I2S_RxCpltCallback() API’s will be replaced with only HAL_I2SEx_TxRxCpltCallback() API.
        • +
      • +
    • Update I2S Transmit/Receive polling process to manage Overrun and Underrun errors
      • +
    • Move the I2S clock input frequency calculation to HAL RCC driver.
      • +
    • Update the HAL I2SEx driver to keep only full duplex feature.
      • +
    • HAL_I2S_Init() API updated to +
        +
      • Fix wrong I2S clock calculation when PCM mode is used.
        • +
      • Return state HAL_I2S_ERROR_PRESCALER when the I2S clock is wrongly configured
        • +
      • +
    • +
  • HAL LTDC update +
      +
    • Optimize HAL_LTDC_IRQHandler() function by using direct register read
      • +
    • Rename the following API’s +
        +
      • HAL_LTDC_Relaod() by HAL_LTDC_Reload()
        • +
      • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
        • +
      • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
        • +
      • +
    • Add new defines for LTDC layers (LTDC_LAYER_1 / LTDC_LAYER_2)
      • +
    • Remove unused asserts
      • +
    • +
  • HAL USB PCD update +
      +
    • Flush all TX FIFOs on USB Reset
      • +
    • Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API’s
      • +
    • +
  • LL USB update +
      +
    • Enable DMA Burst mode for USB OTG HS
      • +
    • Fix SD card detection issue
      • +
    • +
  • LL SDMMC update +
      +
    • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F413xx and STM32F423xx devices
    • +
  • General updates to fix known defects and enhancements implementation
    • +
  • HAL CAN update +
      +
    • Update to add the support of 3 CAN management
      • +
    • +
  • HAL CRYP update +
      +
    • Update to add the support of AES features
      • +
    • +
  • HAL DFSDM update +
      +
    • Add definitions for new external trigger filters
      • +
    • Add definition for new Channels 4, 5, 6 and 7
      • +
    • Add functions and API for Filter state configuration and management
      • +
    • Add new functions: +
        +
      • HAL_DFSDM_BitstreamClock_Start()
        • +
      • HAL_DFSDM_BitstreamClock_Stop()
        • +
      • HAL_DFSDM_BitStreamClkDistribution_Config()
        • +
      • +
    • +
  • HAL DMA +
      +
    • Add the support of DMA Channels from 8 to 15
      • +
    • Update HAL_DMA_DeInit() function with the check on DMA stream instance
      • +
    • +
  • HAL DSI update +
      +
    • Update HAL_DSI_ConfigHostTimeouts() and HAL_DSI_Init() functions to avoid scratch in DSI_CCR register
      • +
    • +
  • HAL FLASH update +
      +
    • Enhance FLASH_WaitForLastOperation() function implementation
      • +
    • Update __HAL_FLASH_GET_FLAG() macro implementation
      • +
    • +
  • HAL GPIO update +
      +
    • Add specific alternate functions definitions
      • +
    • +
  • HAL I2C update +
      +
    • Update I2C_DMAError() function implementation to ignore DMA FIFO error
      • +
    • +
  • HAL I2S update +
      +
    • Enhance HAL_I2S_Init() implementation to test on PCM_SHORT and PCM_LONG standards
      • +
    • +
  • HAL IRDA update +
      +
    • Add new functions and call backs for Transfer Abort +
        +
      • HAL_IRDA_Abort()
        • +
      • HAL_IRDA_AbortTransmit()
        • +
      • HAL_IRDA_AbortReceive()
        • +
      • HAL_IRDA_Abort_IT()
        • +
      • HAL_IRDA_AbortTransmit_IT()
        • +
      • HAL_IRDA_AbortReceive_IT()
        • +
      • HAL_IRDA_AbortCpltCallback()
        • +
      • HAL_IRDA_AbortTransmitCpltCallback()
        • +
      • HAL_IRDA_AbortReceiveCpltCallback()
        • +
      • +
    • +
  • HAL PCD update +
      +
    • Update HAL_PCD_GetRxCount() function implementation
      • +
    • +
  • HAL RCC update +
      +
    • Update __HAL_RCC_HSE_CONFIG() macro implementation
      • +
    • Update __HAL_RCC_LSE_CONFIG() macro implementation
      • +
    • +
  • HAL SMARTCARD update +
      +
    • Add new functions and call backs for Transfer Abort +
        +
      • HAL_ SMARTCARD_Abort()
        • +
      • HAL_ SMARTCARD_AbortTransmit()
        • +
      • HAL_ SMARTCARD_AbortReceive()
        • +
      • HAL_ SMARTCARD_Abort_IT()
        • +
      • HAL_ SMARTCARD_AbortTransmit_IT()
        • +
      • HAL_ SMARTCARD_AbortReceive_IT()
        • +
      • HAL_ SMARTCARD_AbortCpltCallback()
        • +
      • HAL_ SMARTCARD_AbortTransmitCpltCallback()
        • +
      • HAL_ SMARTCARD_AbortReceiveCpltCallback()
        • +
      • +
    • +
  • HAL TIM update +
      +
    • Update HAL_TIMEx_RemapConfig() function to manage TIM internal trigger remap: LPTIM or TIM3_TRGO
      • +
    • +
  • HAL UART update +
      +
    • Add Transfer abort functions and callbacks
      • +
    • +
  • HAL USART update +
      +
    • Add Transfer abort functions and callbacks
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • HAL I2C update +
      +
    • Fix wrong behavior in consecutive transfers in case of single byte transmission (Master/Memory Receive interfaces)
      • +
    • Update HAL_I2C_Master_Transmit_DMA() / HAL_I2C_Master_Receive_DMA()/ HAL_I2C_Slave_Transmit_DMA() and HAL_I2C_Slave_Receive_DMA() to manage addressing phase through interruption instead of polling
      • +
    • Add a check on I2C handle state at start of all I2C API’s to ensure that I2C is ready
      • +
    • Update I2C API’s (Polling, IT and DMA interfaces) to manage I2C XferSize and XferCount handle parameters instead of API size parameter to help user to get information of counter in case of error.
      • +
    • Update Abort functionality to manage DMA use case
      • +
    • +
  • HAL FMPI2C update +
      +
    • Update to disable Own Address before setting the new Own Address configuration: +
        +
      • Update HAL_FMPI2C_Init() to disable FMPI2C_OARx_EN bit before any configuration in OARx registers
        • +
      • +
    • +
  • HAL CAN update +
      +
    • Update CAN receive processes to set CAN RxMsg FIFONumber parameter
      • +
    • +
  • HAL UART update +
      +
    • Update UART handle TxXferCount and RxXferCount parameters as volatile to avoid eventual issue with High Speed optimization
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • HAL GPIO update +
      +
    • HAL_GPIO_Init()/HAL_GPIO_DeInit() API’s: update GPIO_GET_INDEX() macro implementation to support all GPIO’s
      • +
    • +
  • HAL SPI update +
      +
    • Fix regression issue: restore HAL_SPI_DMAPause() and HAL_SPI_DMAResume() API’s
      • +
    • +
  • HAL RCC update +
      +
    • Fix FSMC macros compilation warnings with STM32F412Rx devices
      • +
    • +
  • HAL DMA update +
      +
    • HAL_DMA_PollFortransfer() API clean up
      • +
    • +
  • HAL PPP update(PPP refers to IRDA, UART, USART and SMARTCARD) +
      +
    • Update HAL_PPP_IRQHandler() to add a check on interrupt source before managing the error
      • +
    • +
  • HAL QSPI update +
      +
    • Implement workaround to fix the limitation pronounced in the Errata sheet 2.1.8 section: In some specific cases, DMA2 data corruption occurs when managing AHB and APB2 peripherals in a concurrent way
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F412cx, STM32F412rx, STM32F412vx and STM32F412zx devices
    • +
  • General updates to fix known defects and enhancements implementation
    • +
  • Add new HAL driver for DFSDM peripheral
    • +
  • Enhance HAL delay and time base implementation: +
      +
    • Add new drivers stm32f4xx_hal_timebase_rtc_alarm_template.c and stm32f4xx_hal_timebase_rtc_wakeup_template.c which override the native HAL time base functions (defined as weak) to either use the RTC as time base tick source. For more details about the usage of these drivers, please refer to HAL_TimeBase_RTC examples and FreeRTOS-based applications
      • +
    • +
  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.4 +
      +
    • HAL UART, USART, IRDA, SMARTCARD, SPI, I2C,FMPI2C, QSPI (referenced as PPP here below) drivers +
        +
      • Add PPP error management during DMA process. This requires the following updates on user application: +
          +
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
          • +
        • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
          • +
        • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
          • +
        • +
      • +
    • HAL I2C, FMPI2C (referenced as PPP here below) drivers: +
        +
      • Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using the PPP end of transfer interrupt in the DMA transfer process. This requires the following updates on user application: +
          +
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
          • +
        • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
          • +
        • +
      • +
    • HAL I2C driver: +
        +
      • I2C transfer processes IT update: NACK during addressing phase is managed through I2C Error interrupt instead of HAL state
        • +
      • +
    • HAL IWDG driver: rework overall driver for better implementation +
        +
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
        • +
      • +
    • HAL WWDG driver: rework overall driver for better implementation +
        +
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs
        • +
      • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter) function and API by removing the “counter†parameter
        • +
      • +
    • HAL QSPI driver: Enhance the DMA transmit process by using PPP TC interrupt instead of waiting on TC flag under DMA ISR. This requires the following updates on user application: +
        +
      • Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function
        • +
      • In stm32f4xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function
        • +
      • +
    • HAL CEC driver: Overall driver rework with compatibility break versus previous HAL version +
        +
      • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()
        • +
      • Remove HAL CEC receive interrupt process function HAL_CEC_Receive_IT() and enable the “receive†mode during the Init phase
        • +
      • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize()
        • +
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
        • +
      • Remove the ‘InitiatorAddress’ field from the CEC_InitTypeDef structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function
        • +
      • Add new parameter ‘RxFrameSize’ in HAL_CEC_RxCpltCallback() function
        • +
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
        • +
      • +
    • +
  • HAL RCC update +
      +
    • Update HAL_RCC_ClockConfig() function to adjust the SystemCoreClock
      • +
    • Rename macros and Literals: +
        +
      • RCC_PERIPHCLK_CK48 by RCC_PERIPHCLK_CLK48
        • +
      • IS_RCC_CK48CLKSOURCE by IS_RCC_CLK48CLKSOURCE
        • +
      • RCC_CK48CLKSOURCE_PLLSAIP by RCC_CLK48CLKSOURCE_PLLSAIP
        • +
      • RCC_SDIOCLKSOURCE_CK48 by RCC_SDIOCLKSOURCE_CLK48
        • +
      • RCC_CK48CLKSOURCE_PLLQ by RCC_CLK48CLKSOURCE_PLLQ
        • +
      • +
    • Update HAL_RCCEx_GetPeriphCLKConfig() and HAL_RCCEx_PeriphCLKConfig() functions to support TIM Prescaler for STM32F411xx devices
      • +
    • HAL_RCCEx_PeriphCLKConfig() API: update to fix the RTC clock configuration issue
      • +
    • +
  • HAL CEC update +
      +
    • Overall driver rework with break of compatibility with HAL V1.4.4 +
        +
      • Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()
        • +
      • Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the “Receive†mode enable within the Init phase
        • +
      • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function
        • +
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
        • +
      • Remove the ‘InitiatorAddress’ field from the CEC_InitTypeDef structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function
        • +
      • Add new parameter ‘RxFrameSize’ in HAL_CEC_RxCpltCallback() function
        • +
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
        • +
      • +
    • Update driver to implement the new CEC state machine: +
        +
      • Add new “rxState†field in CEC_HandleTypeDef structure to provide the CEC state information related to Rx Operations
        • +
      • Rename “state†field in CEC_HandleTypeDef structure to “gstateâ€: CEC state information related to global Handle management and Tx Operations
        • +
      • Update CEC process to manage the new CEC states.
        • +
      • Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)
        • +
      • +
    • +
  • HAL UART, USART, SMARTCARD and IRDA (referenced as PPP here below) update +
      +
    • Update Polling management: +
        +
      • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
        • +
      • +
    • Update DMA process: +
        +
      • Update the management of PPP peripheral errors during DMA process. This requires the following updates in user application: +
          +
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
          • +
        • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
          • +
        • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
          • +
        • +
      • +
    • +
  • HAL FMC update +
      +
    • Update FMC_NORSRAM_Init() to remove the Burst access mode configuration
      • +
    • Update FMC_SDRAM_Timing_Init() to fix initialization issue when configuring 2 SDRAM banks
      • +
    • +
  • HAL HCD update +
      +
    • Update HCD_Port_IRQHandler() to unmask disconnect IT only when the port is disabled
      • +
    • +
  • HAL I2C/FMPI2C update +
      +
    • Update Polling management: +
        +
      • The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
        • +
      • +
    • Add the management of Abort service: Abort DMA transfer through interrupt +
        +
      • In the case of Master Abort IT transfer usage: +
          +
        • Add new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process
          • +
        • A new abort state is defined in the HAL_I2C_StateTypeDef structure
          • +
        • +
      • +
    • Add the management of I2C peripheral errors, ACK failure and STOP condition detection during DMA process. This requires the following updates on user application: +
        +
      • Configure and enable the I2C IRQ in HAL_I2C_MspInit() function
        • +
      • In stm32f4xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function
        • +
      • Add and customize the Error Callback API: HAL_I2C_ErrorCallback()
        • +
      • Refer to the I2C_EEPROM or I2C_TwoBoards_ComDMA project examples usage of the API
        • +
      • +
    • NACK error during addressing phase is returned through interrupt instead of previously through I2C transfer API’s
      • +
    • I2C addressing phase is updated to be managed using interrupt instead of polling (Only for HAL I2C driver) +
        +
      • Add new static functions to manage I2C SB, ADDR and ADD10 flags
        • +
      • +
    • +
  • HAL SPI update +
      +
    • Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency +
        +
      • Polling mode: +
          +
        • Replace the use of SPI_WaitOnFlagUnitTimeout() function by “if†statement to check on RXNE/TXE flags while transferring data
          • +
        • +
      • Interrupt mode: +
          +
        • Minimize access on SPI registers
          • +
        • +
      • All modes: +
          +
        • Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled
          • +
        • Update timeout management to check on global processes
          • +
        • Update error code management in all processes
          • +
        • +
      • Update DMA process: +
          +
        • Add the management of SPI peripheral errors during DMA process. This requires the following updates in the user application:
          • +
        • Configure and enable the SPI IRQ in HAL_SPI_MspInit() function
          • +
        • In stm32f4xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function
          • +
        • Add and customize the Error Callback API: HAL_SPI_ErrorCallback()
          • +
        • Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA
          • +
        • +
      • Fix regression in polling mode: +
          +
        • Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()
          • +
        • Add to manage properly the overrun flag at the end of a HAL_SPI_TransmitReceive()
          • +
        • +
      • Fix regression in interrupt mode: +
          +
        • Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()
          • +
        • Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()
          • +
        • +
      • +
    • +
  • HAL DMA2D update +
      +
    • Update the HAL_DMA2D_DeInit() function to: +
        +
      • Abort transfer in case of ongoing DMA2D transfer
        • +
      • Reset DMA2D control registers
        • +
      • +
    • Update HAL_DMA2D_Abort() to disable DMA2D interrupts after stopping transfer
      • +
    • Optimize HAL_DMA2D_IRQHandler() by reading status registers only once
      • +
    • Update HAL_DMA2D_ProgramLineEvent() function to: +
        +
      • Return HAL error state in case of wrong line value
        • +
      • Enable line interrupt after setting the line watermark configuration
        • +
      • +
    • Add new HAL_DMA2D_CLUTLoad() and HAL_DMA2D_CLUTLoad_IT() functions to start DMA2D CLUT loading +
        +
      • HAL_DMA2D_CLUTLoading_Abort() function to abort the DMA2D CLUT loading
        • +
      • HAL_DMA2D_CLUTLoading_Suspend() function to suspend the DMA2D CLUT loading
        • +
      • HAL_DMA2D_CLUTLoading_Resume() function to resume the DMA2D CLUT loading
        • +
      • +
    • Add new DMA2D dead time management: +
        +
      • HAL_DMA2D_EnableDeadTime() function to enable DMA2D dead time feature
        • +
      • HAL_DMA2D_DisableDeadTime() function to disable DMA2D dead time feature
        • +
      • HAL_DMA2D_ConfigDeadTime() function to configure dead time
        • +
      • +
    • Update the name of DMA2D Input/Output color mode defines to be more clear for user (DMA2D_INPUT_XXX for input layers Colors, DMA2D_OUTPUT_XXX for output framebuffer Colors)
      • +
    • +
  • HAL LTDC update +
      +
    • Update HAL_LTDC_IRQHandler() to manage the case of reload interrupt
      • +
    • Add new callback API HAL_LTDC_ReloadEventCallback()
      • +
    • Add HAL_LTDC_Reload() to configure LTDC reload feature
      • +
    • Add new No Reload LTDC variant APIs +
        +
      • HAL_LTDC_ConfigLayer_NoReload() to configure the LTDC Layer according to the specified without reloading
        • +
      • HAL_LTDC_SetWindowSize_NoReload() to set the LTDC window size without reloading
        • +
      • HAL_LTDC_SetWindowPosition_NoReload() to set the LTDC window position without reloading
        • +
      • HAL_LTDC_SetPixelFormat_NoReload() to reconfigure the pixel format without reloading
        • +
      • HAL_LTDC_SetAlpha_NoReload() to reconfigure the layer alpha value without reloading
        • +
      • HAL_LTDC_SetAddress_NoReload() to reconfigure the frame buffer Address without reloading
        • +
      • HAL_LTDC_SetPitch_NoReload() to reconfigure the pitch for specific cases
        • +
      • HAL_LTDC_ConfigColorKeying_NoReload() to configure the color keying without reloading
        • +
      • HAL_LTDC_EnableColorKeying_NoReload() to enable the color keying without reloading
        • +
      • HAL_LTDC_DisableColorKeying_NoReload() to disable the color keying without reloading
        • +
      • HAL_LTDC_EnableCLUT_NoReload() to enable the color lookup table without reloading
        • +
      • HAL_LTDC_DisableCLUT_NoReload() to disable the color lookup table without reloading
        • +
      • Note: Variant functions with “_NoReload†post fix allows to set the LTDC configuration/settings without immediate reload. This is useful in case when the program requires to modify several LTDC settings (on one or both layers) then applying (reload) these settings in one shot by calling the function “HAL_LTDC_Reloadâ€
        • +
      • +
    • +
  • HAL RTC update +
      +
    • Add new timeout implementation based on cpu cycles for ALRAWF, ALRBWF and WUTWF flags
      • +
    • +
  • HAL SAI update +
      +
    • Update SAI state in case of TIMEOUT error within the HAL_SAI_Transmit() / HAL_SAI_Receive()
      • +
    • Update HAL_SAI_IRQHandler: +
        +
      • Add error management in case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()
        • +
      • Add error management in case of IT
        • +
      • +
    • Move SAI_BlockSynchroConfig() and SAI_GetInputClock() functions to stm32f4xx_hal_sai.c/.h files (extension files are kept empty for projects compatibility reason)
      • +
    • +
  • HAL DCMI update +
      +
    • Rename DCMI_DMAConvCplt to DCMI_DMAXferCplt
      • +
    • Update HAL_DCMI_Start_DMA() function to Enable the DCMI peripheral
      • +
    • Add new timeout implementation based on cpu cycles for DCMI stop
      • +
    • Add HAL_DCMI_Suspend() function to suspend DCMI capture
      • +
    • Add HAL_DCMI_Resume() function to resume capture after DCMI suspend
      • +
    • Update lock mechanism for DCMI process
      • +
    • Update HAL_DCMI_IRQHandler() function to: +
        +
      • Add error management in case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()
        • +
      • Optimize code by using direct register read
        • +
      • +
    • +
  • HAL DMA update +
      +
    • Add new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to register/unregister the different callbacks identified by the enum typedef HAL_DMA_CallbackIDTypeDef
      • +
    • Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context +
        +
      • The new registered Abort callback is called when DMA transfer abortion is completed
        • +
      • +
    • Add the check of compatibility between FIFO threshold level and size of the memory burst in the HAL_DMA_Init() API
      • +
    • Add new Error Codes: HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and HAL_DMA_ERROR_NOT_SUPPORTED
      • +
    • Remove all DMA states related to MEM0/MEM1 in HAL_DMA_StateTypeDef
      • +
    • +
  • HAL IWDG update +
      +
    • Overall rework of the driver for a more efficient implementation +
        +
      • Remove the following APIs: +
          +
        • HAL_IWDG_Start()
          • +
        • HAL_IWDG_MspInit()
          • +
        • HAL_IWDG_GetState()
          • +
        • +
      • +
    • Update implementation: +
        +
      • HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG counter
        • +
      • HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter
        • +
      • +
    • Refer to the following example to identify the changes: IWDG_Example
      • +
    • +
  • HAL LPTIM update +
      +
    • Update HAL_LPTIM_TimeOut_Start_IT() and HAL_LPTIM_Counter_Start_IT( ) APIs to configure WakeUp Timer EXTI interrupt to be able to wakeup MCU from low power mode by pressing the EXTI line.
      • +
    • Update HAL_LPTIM_TimeOut_Stop_IT() and HAL_LPTIM_Counter_Stop_IT( ) APIs to disable WakeUp Timer EXTI interrupt.
      • +
    • +
  • HAL NOR update +
      +
    • Update NOR_ADDR_SHIFT macro implementation
      • +
    • +
  • HAL PCD update +
      +
    • Update HAL_PCD_IRQHandler() to get HCLK frequency before setting TRDT value
      • +
    • +
  • HAL QSPI update +
      +
    • Update to manage QSPI error management during DMA process
      • +
    • Improve the DMA transmit process by using QSPI TC interrupt instead of waiting loop on TC flag under DMA ISR
      • +
    • These two improvements require the following updates on user application: +
        +
      • Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function
        • +
      • In stm32f4xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function
        • +
      • Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()
        • +
      • +
    • Add the management of non-blocking transfer abort service: HAL_QSPI_Abort_IT(). In this case the user must: +
        +
      • Add new callback HAL_QSPI_AbortCpltCallback() to inform user at the end of abort process
        • +
      • A new value of State in the HAL_QSPI_StateTypeDef provides the current state during the abort phase
        • +
      • +
    • Polling management update: +
        +
      • The Timeout value user must be estimated for the overall process duration: the Timeout measurement is cumulative.
        • +
      • +
    • Refer to the following examples, which describe the changes: +
        +
      • QSPI_ReadWrite_DMA
        • +
      • QSPI_MemoryMapped
        • +
      • QSPI_ExecuteInPlace
        • +
      • +
    • Add two new APIs for the QSPI fifo threshold: +
        +
      • HAL_QSPI_SetFifoThreshold(): configure the FIFO threshold of the QSPI
        • +
      • HAL_QSPI_GetFifoThreshold(): give the current FIFO threshold
        • +
      • +
    • Fix wrong data size management in HAL_QSPI_Receive_DMA()
      • +
    • +
  • HAL ADC update +
      +
    • Add new __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() macro for STM32F42x and STM32F43x devices to provide the possibility to convert VrefInt channel when both VrefInt and Vbat channels are selected.
      • +
    • +
  • HAL SPDIFRX update +
      +
    • Overall driver update for wait on flag management optimization
      • +
    • +
  • HAL WWDG update +
      +
    • Overall rework of the driver for more efficient implementation +
        +
      • Remove the following APIs: +
          +
        • HAL_WWDG_Start()
          • +
        • HAL_WWDG_Start_IT()
          • +
        • HAL_WWDG_MspDeInit()
          • +
        • HAL_WWDG_GetState()
          • +
        • +
      • Update implementation: +
          +
        • HAL_WWDG_Init() +
            +
          • A new parameter in the Init Structure: EWIMode
            • +
          • +
        • HAL_WWDG_MspInit()
          • +
        • HAL_WWDG_Refresh() +
            +
          • This function insures the reload of the counter
            • +
          • The “counter†parameter has been removed
            • +
          • +
        • HAL_WWDG_IRQHandler()
          • +
        • HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeUpCallback()
          • +
        • +
      • +
    • Refer to the following example to identify the changes: WWDG_Example
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • HAL Generic update +
      +
    • stm32f4xx_hal_conf_template.h +
        +
      • Optimize HSE Startup Timeout value from 5000ms to 100 ms
        • +
      • Add new define LSE_STARTUP_TIMEOUT
        • +
      • Add new define USE_SPI_CRC for code cleanup when the CRC calculation is disabled.
        • +
      • +
    • Update HAL drivers to support MISRA C 2004 rule 10.6
      • +
    • Add new template driver to configure timebase using TIMER : +
        +
      • stm32f4xx_hal_timebase_tim_template.c
        • +
      • +
    • +
  • HAL CAN update +
      +
    • Update HAL_CAN_Transmit() and HAL_CAN_Transmit_IT() functions to unlock process when all Mailboxes are busy
      • +
    • +
  • HAL DSI update +
      +
    • Update HAL_DSI_SetPHYTimings() functions to use the correct mask
      • +
    • +
  • HAL UART update +
      +
    • Several update on HAL UART driver to implement the new UART state machine: +
        +
      • Add new field in UART_HandleTypeDef structure: “rxStateâ€, UART state information related to Rx Operations
        • +
      • Rename “state†field in UART_HandleTypeDef structure by “gstateâ€: UART state information related to global Handle management and Tx Operations
        • +
      • Update UART process to manage the new UART states.
        • +
      • Update __HAL_UART_RESET_HANDLE_STATE() macro to handle the new UART state parameters (gState, rxState)
        • +
      • +
    • Update UART_BRR_SAMPLING16() and UART_BRR_SAMPLING8() Macros to fix wrong baudrate calculation.
      • +
    • +
  • HAL IRDA update +
      +
    • Several update on HAL IRDA driver to implement the new UART state machine: +
        +
      • Add new field in IRDA_HandleTypeDef structure: “rxStateâ€, IRDA state information related to Rx Operations
        • +
      • Rename “state†field in UART_HandleTypeDef structure by “gstateâ€: IRDA state information related to global Handle management and Tx Operations
        • +
      • Update IRDA process to manage the new UART states.
        • +
      • Update __HAL_IRDA_RESET_HANDLE_STATE() macro to handle the new IRDA state parameters (gState, rxState)
        • +
      • +
    • Removal of IRDA_TIMEOUT_VALUE define
      • +
    • Update IRDA_BRR() Macro to fix wrong baudrate calculation
      • +
    • +
  • HAL SMARTCARD update +
      +
    • Several update on HAL SMARTCARD driver to implement the new UART state machine: +
        +
      • Add new field in SMARTCARD_HandleTypeDef structure: “rxStateâ€, SMARTCARDstate information related to Rx Operations
        • +
      • Rename “state†field in UART_HandleTypeDef structure by “gstateâ€: SMARTCARDstate information related to global Handle management and Tx Operations
        • +
      • Update SMARTCARD process to manage the new UART states.
        • +
      • Update __HAL_SMARTCARD_RESET_HANDLE_STATE() macro to handle the new SMARTCARD state parameters (gState, rxState)
        • +
      • +
    • Update SMARTCARD_BRR() macro to fix wrong baudrate calculation
      • +
    • +
  • HAL RCC update +
      +
    • Add new default define value for HSI calibration “RCC_HSICALIBRATION_DEFAULTâ€
      • +
    • Optimize Internal oscillators and PLL startup timeout
      • +

    • Update to avoid the disable for HSE/LSE oscillators before setting the new RCC HSE/LSE configuration and add the following notes in HAL_RCC_OscConfig() API description:

      +
                         * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+                   *             supported by this API. User should request a transition to LSE Off
+                   *             first and then LSE On or LSE Bypass.
+                   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+                   *             supported by this API. User should request a transition to HSE Off
+                   *             first and then HSE On or HSE Bypass.
      • +
    • Optimize the HAL_RCC_ClockConfig() API implementation.
      • +
    • +
  • HAL DMA2D update +
      +
    • Update HAL_DMA2D_Abort() Function to end current DMA2D transfer properly
      • +
    • Update HAL_DMA2D_PollForTransfer() function to add poll for background CLUT loading (layer 0 and layer 1).
      • +
    • Update HAL_DMA2D_PollForTransfer() to set the corresponding ErrorCode in case of error occurrence
      • +
    • Update HAL_DMA2D_ConfigCLUT() function to fix wrong CLUT size and color mode settings
      • +
    • Removal of useless macro __HAL_DMA2D_DISABLE()
      • +
    • Update HAL_DMA2D_Suspend() to manage correctly the case where no transfer is on going
      • +
    • Update HAL_DMA2D_Resume() to manage correctly the case where no transfer is on going
      • +
    • Update HAL_DMA2D_Start_IT() to enable all required interrupts before enabling the transfer.
      • +
    • Add HAL_DMA2D_CLUTLoad_IT() Function to allow loading a CLUT with interruption model.
      • +

    • Update HAL_DMA2D_IRQHandler() to manage the following cases :

      +
        +
      • CLUT transfer complete
        • +
      • CLUT access error
        • +
      • Transfer watermark reached
        • +
      • +
    • Add new Callback APIs: +
        +
      • HAL_DMA2D_LineEventCallback() to signal a transfer watermark reached event
        • +
      • HAL_DMA2D_CLUTLoadingCpltCallback() to signal a CLUT loading complete event
        • +
      • +
    • Miscellaneous Improvement: +
        +
      • Add “HAL_DMA2D_ERROR_CAE†new define for CLUT Access error management.
        • +
      • Add “assert_param†used for parameters check is now done on the top of the exported functions : before locking the process using __HAL_LOCK
        • +
      • +
    • +
  • HAL I2C update +
      +
    • Add support of I2C repeated start feature: +
        +
      • With the following new API’s +
          +
        • HAL_I2C_Master_Sequential_Transmit_IT()
          • +
        • HAL_I2C_Master_Sequential_Receive_IT()
          • +
        • HAL_I2C_Master_Abort_IT()
          • +
        • HAL_I2C_Slave_Sequential_Transmit_IT()
          • +
        • HAL_I2C_Slave_Sequential_Receive_IT()
          • +
        • HAL_I2C_EnableListen_IT()
          • +
        • HAL_I2C_DisableListen_IT()
          • +
        • +
      • +
    • Add new user callbacks: +
        +
      • HAL_I2C_ListenCpltCallback()
        • +
      • HAL_I2C_AddrCallback()
        • +
      • +
    • Update to generate STOP condition when a acknowledge failure error is detected
      • +
    • Several update on HAL I2C driver to implement the new I2C state machine: +
        +
      • Add new API to get the I2C mode: HAL_I2C_GetMode()
        • +
      • Update I2C process to manage the new I2C states.
        • +
      • +
    • Fix wrong behaviour in single byte transmission
      • +
    • Update I2C_WaitOnFlagUntilTimeout() to manage the NACK feature.
      • +
    • Update I2C transmission process to support the case data size equal 0
      • +
    • +
  • HAL FMPI2C update +
      +
    • Add support of FMPI2C repeated start feature: +
        +
      • With the following new API’s +
          +
        • HAL_FMPI2C_Master_Sequential_Transmit_IT()
          • +
        • HAL_FMPI2C_Master_Sequential_Receive_IT()
          • +
        • HAL_FMPI2C_Master_Abort_IT()
          • +
        • HAL_FMPI2C_Slave_Sequential_Transmit_IT()
          • +
        • HAL_FMPI2C_Slave_Sequential_Receive_IT()
          • +
        • HAL_FMPI2C_EnableListen_IT()
          • +
        • HAL_FMPI2C_DisableListen_IT()
          • +
        • +
      • Add new user callbacks: +
          +
        • HAL_FMPI2C_ListenCpltCallback()
          • +
        • HAL_FMPI2C_AddrCallback()
          • +
        • +
      • Several update on HAL I2C driver to implement the new I2C state machine: +
          +
        • Add new API to get the FMPI2C mode: HAL_FMPI2C_GetMode()
          • +
        • Update FMPI2C process to manage the new FMPI2C states.
          • +
        • +
      • +
    • +
  • HAL SPI update +
      +
    • Major Update to improve performance in polling/interrupt mode to reach max frequency: +
        +
      • Polling mode : +
          +
        • Replace use of SPI_WaitOnFlagUnitTimeout() funnction by “if†statement to check on RXNE/TXE flags while transferring data.
          • +
        • Use API data pointer instead of SPI handle data pointer.
          • +
        • Use a Goto implementation instead of “if..else†statements.
          • +
        • +
      • Interrupt mode +
          +
        • Minimize access on SPI registers.
          • +
        • Split the SPI modes into dedicated static functions to minimize checking statements under HAL_IRQHandler(): +
            +
          • 1lines/2lines modes
            • +
          • 8 bit/ 16 bits data formats
            • +
          • CRC calculation enabled/disabled.
            • +
          • +
        • Remove waiting loop under ISR when closing the communication.
          • +
        • +
      • All modes: +
          +
        • Adding switch USE_SPI_CRC to minimize number of statements when CRC calculation is disabled.
          • +
        • Update Timeout management to check on global process.
          • +
        • Update Error code management in all processes.
          • +
        • +
      • +
    • Add note to the max frequencies reached in all modes.
      • +
    • Add note about Master Receive mode restrictions : +
        +
      • Master Receive mode restriction: +
        +(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI does not initiate a new transfer the following procedure has to be respected:
        +(##) HAL_SPI_DeInit()
        +(##) HAL_SPI_Init() +
        • +
      • +
    • +
  • HAL SAI update +
      +
    • Update for proper management of the external synchronization input selection +
        +
      • update of HAL_SAI_Init () function
        • +
      • update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups
        • +
      • +
    • Update SAI_SLOTACTIVE_X defines values
      • +
    • Update HAL_SAI_Init() function for proper companding mode management
      • +
    • Update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers
      • +
    • Update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size
      • +
    • Update HAL_SAI_EnableRxMuteMode() function for proper mute management
      • +
    • Update SAI_InitPCM() function to support 24bits configuration
      • +
    • +
  • HAL ETH update +
      +
    • Removal of ETH MAC debug register defines
      • +
    • +
  • HAL FLASH update +
      +
    • Update FLASH_MassErase() function to apply correctly voltage range parameter
      • +
    • +
  • HAL I2S update +
      +
    • Update I2S_DMATxCplt() and I2S_DMARxCplt() to manage properly FullDuplex mode without any risk of missing data.
      • +
    • +
  • LL FMC update +
      +
    • Update the FMC_NORSRAM_Init() function to use BurstAccessMode field properly
      • +
    • +
  • LL FSMC update +
      +
    • Update the FSMC_NORSRAM_Init() function to use BurstAccessMode field properly
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • HAL Generic update +
      +
    • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers by calling the following line: +
        +
      • UNUSED(hppp);
        • +
      • +
    • STM32Fxxx_User_Manual.chm files regenerated for HAL V1.4.3
      • +
    • +
  • HAL ETH update +
      +
    • Update HAL_ETH_Init() function to add timeout on the Software reset management
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    +
    • +
  • One change done on the HAL CRYP requires an update on the application code based on HAL V1.4.1 +
      +
    • Update HAL_CRYP_DESECB_Decrypt() API to invert pPlainData and pCypherData parameters
      +
      • +
    • +
  • HAL generic update +
      +
    • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers by calling the following line: +
        +
      • UNUSED(hppp);
        +
        • +
      • +
    • +
  • HAL CORTEX update +
      +
    • Remove duplication for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro
      +
      • +
    • +
  • HAL HASH update +
      +
    • Rename HAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef
      • +
    • Rename HAL_HASH_PhaseTypeDef to HAL_HASH_PhaseTypeDef
      • +
    • +
  • HAL RCC update +
      +
    • Add new macros __HAL_RCC_PPP_IS_CLK_ENABLED() to check on Clock enable/disable status
      • +
    • Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable for the SYSCFG
      • +
    • Update HAL_RCC_MCOConfig() API to use new defines for the GPIO Speed
      • +
    • Generic update to improve the PLL VCO min value(100MHz): PLLN, PLLI2S and PLLSAI min value is 50 instead of 192
      • +
    • +
  • HAL FLASH update +
      +
    • __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset ICRST bit in the ACR register after setting it.
      • +
    • Update to support until 15 FLASH wait state (FLASH_LATENCY_15) for STM32F446xx devices
      • +
    • +
  • HAL CRYP update +
      +
    • Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue
      • +
    • +
  • HAL I2S update +
      +
    • Update HAL_I2S_Init() API to call __HAL_RCC_I2S_CONFIG() macro when external I2S clock is selected
      • +
    • +
  • HAL LTDC update +
      +
    • Update HAL_LTDC_SetWindowPosition() API to configure Immediate reload register instead of vertical blanking reload register.
      • +
    • +
  • HAL TIM update +
      +
    • Update HAL_TIM_ConfigClockSource() API to check only the required parameters
      • +
    • +
  • HAL NAND update +
      +
    • Update HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() APIs to manage correctly the NAND Page access
      • +
    • +
  • HAL CAN update +
      +
    • Update to use “=†instead of “|=†to clear flags in the MSR, TSR, RF0R and RF1R registers
      • +
    • +
  • HAL HCD update +
      +
    • Fix typo in __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() macro implementation
      • +
    • +
  • HAL PCD update +
      +
    • Update HAL_PCD_IRQHandler() API to avoid issue when DMA mode enabled for Status Phase IN stage
      • +
    • +
  • LL FMC update +
      +
    • Update the FMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters
      • +
    • Update the FMC_NORSRAM_Init() API to add a check on the PageSize parameter for STM32F42/43xx devices
      • +
    • +
  • LL FSMC update +
      +
    • Update the FSMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • HAL DSI update +
      +
    • Update TCCR register assigned value in HAL_DSI_ConfigHostTimeouts() function
      • +
    • Update WPCR register assigned value in HAL_DSI_Init(), HAL_DSI_SetSlewRateAndDelayTuning(), HAL_DSI_SetSlewRateAndDelayTuning(), HAL_DSI_SetLowPowerRXFilter() / HAL_DSI_SetSDD(), HAL_DSI_SetLanePinsConfiguration(), HAL_DSI_SetPHYTimings(), HAL_DSI_ForceTXStopMode(), HAL_DSI_ForceRXLowPower(), HAL_DSI_ForceDataLanesInRX(), HAL_DSI_SetPullDown() and HAL_DSI_SetContentionDetectionOff() functions
      • +
    • Update DSI_HS_PM_ENABLE define value
      • +
    • Implement workaround for the hardware limitation: “The time to activate the clock between HS transmissions is not calculated correctlyâ€
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F469xx, STM32F479xx, STM32F410Cx, STM32F410Rx and STM32F410Tx devices
    • +
  • General updates to fix known defects and enhancements implementation
    • +
  • Add new HAL drivers for DSI and LPTIM peripherals
    • +
  • HAL ADC update +
      +
    • Rename ADC_CLOCKPRESCALER_PCLK_DIV2 define to ADC_CLOCK_SYNC_PCLK_DIV2
      • +
    • Rename ADC_CLOCKPRESCALER_PCLK_DIV4 define to ADC_CLOCK_SYNC_PCLK_DIV4
      • +
    • Rename ADC_CLOCKPRESCALER_PCLK_DIV6 define to ADC_CLOCK_SYNC_PCLK_DIV6
      • +
    • Rename ADC_CLOCKPRESCALER_PCLK_DIV8 define to ADC_CLOCK_SYNC_PCLK_DIV8
      • +
    • +
  • HAL CORTEX update +
      +
    • Add specific API for MPU management +
        +
      • add MPU_Region_InitTypeDef structure
        • +
      • add new function HAL_MPU_ConfigRegion()
        • +
      • +
    • +
  • HAL DMA update +
      +
    • Overall driver update for code optimization +
        +
      • add StreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef structure
        • +
      • add DMA_Base_Registers private structure
        • +
      • add static function DMA_CalcBaseAndBitshift()
        • +
      • update HAL_DMA_Init() function to use the new added static function
        • +
      • update HAL_DMA_DeInit() function to optimize clear flag operations
        • +
      • update HAL_DMA_Start_IT() function to optimize interrupts enable
        • +
      • update HAL_DMA_PollForTransfer() function to optimize check on flags
        • +
      • update HAL_DMA_IRQHandler() function to optimize interrupt flag management
        • +
      • +
    • +
  • HAL FLASH update +
      +
    • update HAL_FLASH_Program_IT() function by removing the pending flag clear
      • +
    • update HAL_FLASH_IRQHandler() function to improve erase operation procedure
      • +
    • update FLASH_WaitForLastOperation() function by checking on end of operation flag
      • +
    • +
  • HAL GPIO update +
      +
    • Rename GPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW
      • +
    • Rename GPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM
      • +
    • Rename GPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH
      • +
    • Rename GPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH
      • +
    • +
  • HAL I2S update +
      +
    • Move I2S_Clock_Source defines to extension file to properly add the support of STM32F410xx devices
      • +
    • +
  • HAL LTDC update +
      +
    • rename HAL_LTDC_LineEvenCallback() function to HAL_LTDC_LineEventCallback()
      • +
    • add new function HAL_LTDC_SetPitch()
      • +
    • add new functions HAL_LTDC_StructInitFromVideoConfig() and HAL_LTDC_StructInitFromAdaptedCommandConfig() applicable only to STM32F469xx and STM32F479xx devices
      • +
    • +
  • HAL PWR update +
      +
    • move __HAL_PWR_VOLTAGESCALING_CONFIG() macro to extension file
      • +
    • move PWR_WAKEUP_PIN2 define to extension file
      • +
    • add PWR_WAKEUP_PIN3 define, applicable only to STM32F10xx devices
      • +
    • add new functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() and HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), applicable only to STM32F469xx and STM32F479xx devices
      • +
    • +
  • HAL RTC update +
      +
    • Update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on the WUTWF flag
      • +
    • +
  • HAL TIM update +
      +
    • add new defines TIM_SYSTEMBREAKINPUT_HARDFAULT, TIM_SYSTEMBREAKINPUT_PVD and TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD, applicable only to STM32F410xx devices
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
  • One changes done on the HAL may require an update on the application code based on HAL V1.3.1 +
      +
    • HASH IT process: update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits
      • +
    • +
  • HAL RCC update +
      +
    • HAL_RCCEx_PeriphCLKConfig() updates: +
        +
      • Update the LSE check condition after backup domain reset: update to check LSE ready flag when LSE oscillator is already enabled instead of check on LSE oscillator only when LSE is used as RTC clock source
        • +
      • Use the right macro to check the PLLI2SQ parameters
        • +
      • +
    • +
  • HAL RTC update +
      +
    • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() macro: fix implementation issue
      • +
    • __HAL_RTC_ALARM_GET_IT(), __HAL_RTC_ALARM_CLEAR_FLAG(), __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(), __HAL_RTC_TIMESTAMP_CLEAR_FLAG() and __HAL_RTC_TAMPER_CLEAR_FLAG() macros implementation changed: remove unused cast
      • +
    • IS_RTC_TAMPER() macro: update to use literal instead of hardcoded value
      • +
    • Add new parameter SecondFraction in RTC_TimeTypeDef structure
      • +
    • HAL_RTC_GetTime() API update to support the new parameter SecondFraction
      • +
    • +
  • HAL ADC update +
      +
    • Add new literal: ADC_INJECTED_SOFTWARE_START to be used as possible value for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef structure to select the ADC software trigger mode.
      • +
    • +
  • HAL FLASH update +
      +
    • FLASH_OB_GetRDP() API update to return uint8_t instead of FlagStatus
      • +
    • __HAL_FLASH_GET_LATENCY() new macro add to get the flash latency
      • +
    • +
  • HAL SPI update +
      +
    • Fix the wrong definition of HAL_SPI_ERROR_FLAG literal
      • +
    • +
  • HAL I2S update +
      +
    • HAL_I2S_Transmit() API update to check on busy flag only for I2S slave mode
      • +
    • +
  • HAL CRC update +
      +
    • __HAL_CRC_SET_IDR() macro implementation change to use WRITE_REG() instead of MODIFY_REG()
      • +
    • +
  • HAL DMA2D update +
      +
    • HAL_DMA2D_ConfigLayer() API update to use “=†instead of “|=†to erase BGCOLR and FGCOLR registers before setting the new configuration
      • +
    • +
  • HAL HASH update +
      +
    • HAL_HASH_MODE_Start_IT() (MODE stands for MD5, SHA1, SHA224 and SHA36) updates: +
        +
      • Fix processing fail for small input buffers
        • +
      • Update to unlock the process and call return HAL_OK at the end of HASH processing to avoid incorrectly repeating software
        • +
      • Update to properly manage the HashITCounter
        • +
      • Update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits
        • +
      • +
    • __HAL_HASH_GET_FLAG() update to check the right register when the DINNE flag is selected
      • +
    • HAL_HASH_SHA1_Accumulate() updates: +
        +
      • Add a call to the new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size parameter.
        • +
      • Add the following note in API description +
          +
        • @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
          • +
        • +
      • +
    • +
  • HAL RTC update +
      +
    • Update to define hardware independent literals names: +
        +
      • Rename RTC_TAMPERPIN_PC13 by RTC_TAMPERPIN_DEFAULT
        • +
      • Rename RTC_TAMPERPIN_PA0 by RTC_TAMPERPIN_POS1
        • +
      • Rename RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1
        • +
      • Rename RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT
        • +
      • Rename RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1
        • +
      • Rename RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1
        • +
      • +
    • +
  • HAL ETH update +
      +
    • Remove duplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros
      • +
    • Remove illegal space ETH_MAC_READCONTROLLER_FLUSHING macro
      • +
    • Update ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and READING_STATUS)
      • +
    • +
  • HAL PCD update +
      +
    • HAL_PCD_IRQHandler API: fix the bad Configuration of Turnaround Time
      • +
    • +
  • HAL HCD update +
      +
    • Update to use local variable in USB Host channel re-activation
      • +
    • +
  • LL FMC update +
      +
    • FMC_SDRAM_SendCommand() API: remove the following line: return HAL_ERROR;
      • +
    • +
  • LL USB update +
      +
    • USB_FlushTxFifo API: update to flush all Tx FIFO
      • +
    • Update to use local variable in USB Host channel re-activation
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • HAL PWR update +
      +
    • Fix compilation issue with STM32F417xx product: update STM32F17xx by STM32F417xx
      • +
    • +
  • HAL SPI update +
      +
    • Remove unused variable to avoid warning with TrueSTUDIO
      • +
    • +
  • HAL I2C update +
      +
    • I2C Polling/IT/DMA processes: move the wait loop on busy flag at the top of the processes, to ensure that software not perform any write access to I2C_CR1 register before hardware clearing STOP bit and to avoid also the waiting loop on BUSY flag under I2C/DMA ISR.
      • +
    • Update busy flag Timeout value
      • +
    • I2C Master Receive Processes update to disable ACK before generate the STOP
      • +
    • +
  • HAL DAC update +
      +
    • Fix V1.3.0 regression issue with DAC software trigger configuration
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F446xx devices
    • +
  • General updates to fix known defects and enhancements implementation
    • +
  • Add new HAL drivers for CEC, QSPI, FMPI2C and SPDIFRX peripherals
    • +
  • Two changes done on the HAL requires an update on the application code based on HAL V1.2.0 +
      +
    • Overall SAI driver rework to have exhaustive support of the peripheral features: details are provided in HAL SAI update section below –> Compatibility with previous version is impacted
      • +
    • CRYP driver updated to support multi instance,so user must ensure that the new parameter Instance is initialized in his application(CRYPHandle.Instance = CRYP)
      • +
    • +
  • HAL Generic update +
      +
    • stm32f4xx_hal_def.h +
        +
      • Remove NULL definition and add include for stdio.h
        • +
      • +
    • stm32_hal_legacy.h +
        +
      • Update method to manage deference in alias implementation between all STM32 families
        • +
      • +
    • stm32f4xx_hal_ppp.c +
        +
      • HAL_PPP_Init(): update to force the HAL_PPP_STATE_RESET before calling the HAL_PPP_MspInit()
        • +
      • +
    • +
  • HAL RCC update +
      +
    • Add new function HAL_RCCEx_GetPeriphCLKFreq()
      • +
    • Move RCC_PLLInitTypeDef structure to extension file and add the new PLLR field specific to STM32F446xx devices
      • +
    • Move the following functions to extension file and add a __weak attribute in generic driver : this update is related to new system clock source (PLL/PLLR) added and only available for STM32F44xx devices +
        +
      • HAL_RCC_OscConfig()
        • +
      • HAL_RCC_GetSysClockFreq()
        • +
      • HAL_RCC_GetOscConfig()
        • +
      • +
    • Move the following macro to extension file as they have device dependent implementation +
        +
      • __HAL_RCC_PLL_CONFIG()
        • +
      • __HAL_RCC_PLLI2S_CONFIG()
        • +
      • __HAL_RCC_I2S_CONFIG()
        • +
      • +
    • Add new structure RCC_PLLI2SInitTypeDef containing new PLLI2S division factors used only w/ STM32F446xx devices
      • +
    • Add new structure RCC_PLLSAIInitTypeDef containing new PLLSAI division factors used only w/ STM32F446xx devices
      • +
    • Add new RCC_PeriphCLKInitTypeDef to support the peripheral source clock selection for (I2S, SAI, SDIO, FMPI2C, CEC, SPDIFRX and CLK48)
      • +
    • Update the HAL_RCCEx_PeriphCLKConfig() and HAL_RCCEx_GetPeriphCLKConfig() functions to support the new peripherals Clock source selection
      • +
    • Add __HAL_RCC_PLL_CONFIG() macro (the number of parameter and the implementation depend on the device part number)
      • +
    • Add __HAL_RCC_PLLI2S_CONFIG() macro(the number of parameter and the implementation depend on device part number)
      • +
    • Update __HAL_RCC_PLLSAI_CONFIG() macro to support new PLLSAI factors (PLLSAIM and PLLSAIP)
      • +
    • Add new macros for clock enable/Disable for the following peripherals (CEC, SPDIFRX, SAI2, QUADSPI)
      • +
    • Add the following new macros for clock source selection : +
        +
      • __HAL_RCC_SAI1_CONFIG() / __HAL_RCC_GET_SAI1_SOURCE()
        • +
      • __HAL_RCC_SAI2_CONFIG() / __HAL_RCC_GET_SAI2_SOURCE()
        • +
      • __HAL_RCC_I2S1_CONFIG() / __HAL_RCC_GET_I2S1_SOURCE()
        • +
      • __HAL_RCC_I2S2_CONFIG() / __HAL_RCC_GET_I2S2_SOURCE()
        • +
      • __HAL_RCC_CEC_CONFIG() / __HAL_RCC__GET_CEC_SOURCE()
        • +
      • __HAL_RCC_FMPI2C1_CONFIG() / __HAL_RCC_GET_FMPI2C1_SOURCE()
        • +
      • __HAL_RCC_SDIO_CONFIG() / __HAL_RCC_GET_SDIO_SOURCE()
        • +
      • __HAL_RCC_CLK48_CONFIG() / __HAL_RCC_GET_CLK48_SOURCE()
        • +
      • __HAL_RCC_SPDIFRXCLK_CONFIG() / __HAL_RCC_GET_SPDIFRX_SOURCE()
        • +
      • +
    • __HAL_RCC_PPP_CLK_ENABLE(): Implement workaround to cover RCC limitation regarding peripheral enable delay
      • +
    • HAL_RCC_OscConfig() fix issues: +
        +
      • Add a check on LSERDY flag when LSE_BYPASS is selected as new state for LSE oscillator.
        • +
      • +
    • Add new possible value RCC_PERIPHCLK_PLLI2S to be selected as PeriphClockSelection parameter in the RCC_PeriphCLKInitTypeDef structure to allow the possibility to output the PLLI2S on MCO without activating the I2S or the SAI.
      • +

    • __HAL_RCC_HSE_CONFIG() macro: add the comment below:
      +* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
      +* User should request a transition to HSE Off first and then HSE On or HSE Bypass.

      • +

    • __HAL_RCC_LSE_CONFIG() macro: add the comment below:
      +* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
      +* User should request a transition to LSE Off first and then LSE On or LSE Bypass.

      • +
    • Add the following new macros for PLL source and PLLM selection : +
        +
      • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
        • +
      • __HAL_RCC_PLL_PLLM_CONFIG()
        • +
      • +
    • Macros rename: +
        +
      • HAL_RCC_OTGHS_FORCE_RESET() by HAL_RCC_USB_OTG_HS_FORCE_RESET()
        • +
      • HAL_RCC_OTGHS_RELEASE_RESET() by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
        • +
      • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
        • +
      • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
        • +
      • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
        • +
      • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
        • +
      • +
    • Add __HAL_RCC_SYSCLK_CONFIG() new macro to configure the system clock source (SYSCLK)
      • +
    • __HAL_RCC_GET_SYSCLK_SOURCE() updates: +
        +
      • Add new RCC Literals: +
          +
        • RCC_SYSCLKSOURCE_STATUS_HSI
          • +
        • RCC_SYSCLKSOURCE_STATUS_HSE
          • +
        • RCC_SYSCLKSOURCE_STATUS_PLLCLK
          • +
        • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
          • +
        • +
      • Update macro description to refer to the literals above
        • +
      • +
    • +
  • HAL PWR update +
      +
    • Add new define PWR_WAKEUP_PIN2
      • +
    • Add new API to Control/Get VOS bits of CR register +
        +
      • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
        • +
      • HAL_PWREx_GetVoltageRange()
        • +
      • +
    • __HAL_PWR_ VOLTAGESCALING_CONFIG(): Implement workaround to cover VOS limitation delay when PLL is enabled after setting the VOS configuration
      • +
    • +
  • HAL GPIO update +
      +
    • Add the new Alternate functions literals related to remap for SPI, USART, I2C, SPDIFRX, CEC and QSPI
      • +
    • HAL_GPIO_DeInit(): Update to check if GPIO Pin x is already used in EXTI mode on another GPIO Port before De-Initialize the EXTI registers
      • +
    • +
  • HAL FLASH update +
      +
    • __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset ICRST bit in the ACR register after setting it.
      • +
    • __HAL_FLASH_DATA_CACHE_RESET() macro: update to reset DCRST bit in the ACR register after setting it.
      • +
    • +
  • HAL ADC update +
      +
    • Add new literal: ADC_SOFTWARE_START to be used as possible value for the ExternalTrigConv parameter in the ADC_InitTypeDef structure to select the ADC software trigger mode.
      • +
    • IS_ADC_CHANNEL() macro update to don’t assert stop the ADC_CHANNEL_TEMPSENSOR value
      • +
    • HAL_ADC_PollForConversion(): update to manage particular case when ADC configured in DMA mode and ADC sequencer with several ranks and polling for end of each conversion
      • +
    • HAL_ADC_Start()/HAL_ADC_Start_IT() /HAL_ADC_Start_DMA() update: +
        +
      • unlock the process before starting the ADC software conversion.
        • +
      • Optimize the ADC stabilization delays
        • +
      • +
    • __HAL_ADC_GET_IT_SOURCE() update macro implementation
      • +
    • Add more details in ‘How to use this driver’ section
      • +
    • +
  • HAL DAC update +
      +
    • Add new macro to check if the specified DAC interrupt source is enabled or disabled +
        +
      • __HAL_DAC_GET_IT_SOURCE()
        • +
      • +
    • HAL_DACEx_TriangleWaveGeneration() update to use DAC CR bit mask definition
      • +
    • HAL_DACEx_NoiseWaveGeneration() update to use DAC CR bit mask definition
      • +
    • +
  • HAL CAN update +
      +
    • CanTxMsgTypeDef structure: update to use uint8_t Data[8] instead of uint32_t Data[8]
      • +
    • CanRxMsgTypeDef structure: update to use uint8_t Data[8] instead of uint32_t Data[8]
      • +
    • +
  • HAL RTC update +
      +
    • Update to use CMSIS mask definition instead of hardcoded values (EXTI_IMR_IM17, EXTI_IMR_IM19..)
      • +
    • +
  • HAL LTDC update +
      +
    • LTDC_SetConfig() update to allow the drawing of partial bitmap in active layer.
      • +
    • +
  • HAL USART update +
      +
    • HAL_USART_Init() fix USART baud rate configuration issue: USART baud rate is twice Higher than expected
      • +
    • +
  • HAL SMARTCARD update +
      +
    • HAL_SMARTCARD_Transmit_IT() update to force the disable for the ERR interrupt to avoid the OVR interrupt
      • +
    • HAL_SMARTCARD_IRQHandler() update check condition for transmission end
      • +
    • Clean up: remove the following literals that aren’t used in smartcard mode +
        +
      • SMARTCARD_PARITY_NONE
        • +
      • SMARTCARD_WORDLENGTH_8B
        • +
      • SMARTCARD_STOPBITS_1
        • +
      • SMARTCADR_STOPBITS_2
        • +
      • +
    • +
  • HAL SPI update +
      +
    • HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TarnsmitReceive_DMA() update to unlock the process before enabling the SPI peripheral
      • +
    • HAL_SPI_Transmit_DMA() update to manage correctly the DMA RX stream in SPI Full duplex mode
      • +
    • Section SPI_Exported_Functions_Group2 update to remove duplication in *.chm UM
      • +
    • +
  • HAL CRYP update +
      +
    • Update to manage multi instance: +
        +
      • Add new parameter Instance in the CRYP_HandleTypeDef Handle structure.
        • +
      • Add new parameter in all HAL CRYP macros +
          +
        • example: __HAL_CRYP_ENABLE() updated by __HAL_CRYP_ENABLE(__HANDLE__)
          • +
        • +
      • +
    • +
  • HAL DCMI update +
      +
    • Add an extension driver stm32f4xx_hal_dcmi_ex.c/h to manage the support of new Black and White feature
      • +
    • Add __weak attribute for HAL_DCMI_Init() function and add a new implementation in the extension driver to manage the black and white configuration only available in the STM32F446xx devices.
      • +
    • Move DCMI_InitTypeDef structure to extension driver and add the following new fields related to black and white feature: ByteSelectMode, ByteSelectStart, LineSelectMode and LineSelectStart
      • +
    • +
  • HAL PCD update +
      +
    • Add the support of LPM feature +
        +
      • add PCD_LPM_StateTypeDef enum
        • +
      • update PCD_HandleTypeDef structure to support the LPM feature
        • +
      • add new functions HAL_PCDEx_ActivateLPM(), HAL_PCDEx_DeActivateLPM() and HAL_PCDEx_LPM_Callback() in the stm32f4xx_hal_pcd_ex.h/.c files
        • +
      • +
    • +
  • HAL TIM update +
      +
    • Add TIM_TIM11_SPDIFRX define
      • +
    • +
  • HAL SAI update +
      +
    • Add stm32f4xx_hal_sai_ex.h/.c files for the SAI_BlockSynchroConfig() and the SAI_GetInputClock() management
      • +
    • Add new defines HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_CNREADY, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ERROR_TIMEOUT in the SAI_Error_Code group
      • +
    • Add new defines SAI_SYNCEXT_DISABLE, SAI_SYNCEXT_IN_ENABLE, SAI_SYNCEXT_OUTBLOCKA_ENABLE, SAI_SYNCEXT_OUTBLOCKB_ENABLE for the SAI External synchronization
      • +
    • Add new defines SAI_I2S_STANDARD, SAI_I2S_MSBJUSTIFIED, SAI_I2S_LSBJUSTIFIED, SAI_PCM_LONG and SAI_PCM_SHORT for the SAI Supported protocol
      • +
    • Add new defines SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT and SAI_PROTOCOL_DATASIZE_32BIT for SAI protocol data size
      • +
    • Add SAI Callback prototype definition
      • +
    • Update SAI_InitTypeDef structure by adding new fields: SynchroExt, Mckdiv, MonoStereoMode, CompandingMode, TriState
      • +
    • Update SAI_HandleTypeDef structure: +
        +
      • remove uint16_t pTxBuffPtr, pRxBuffPtr, TxXferSize, RxXferSize, TxXferCount and RxXferCount and replace them respectively by uint8_t *pBuffPtr, uint16_t XferSize and uint16_t XferCount
        • +
      • add mutecallback field
        • +
      • add struct __SAI_HandleTypeDef *hsai field
        • +
      • +
    • Remove SAI_CLKSOURCE_PLLR and SAI_CLOCK_PLLSRC defines
      • +
    • Add SAI_CLKSOURCE_NA define
      • +
    • Add SAI_AUDIO_FREQUENCY_MCKDIV define
      • +
    • Add SAI_SPDIF_PROTOCOL define
      • +
    • Add SAI_SYNCHRONOUS_EXT define
      • +
    • Add new functions HAL_SAI_InitProtocol(), HAL_SAI_Abort(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_DisableRxMuteMode()
      • +
    • Update HAL_SAI_Transmit(), HAL_SAI_Receive(), HAL_SAI_Transmit_IT(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), HAL_SAI_Receive_DMA() functions to use uint8_t pData instead of uint16_t pData –> This update is mainly impacting the compatibility with previous driver version.
      • +
    • +
  • HAL I2S update +
      +
    • Split the following functions between Generic and Extended API based on full duplex management and add the attribute __weak in the Generic API +
        +
      • HAL_I2S_Init(), HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), HAL_I2S_DMAResume(), HAL_I2S_IRQHandle()
        • +
      • +
    • Move the following static functions from generic to extension driver +
        +
      • I2S_DMARxCplt() and I2S_DMATxCplt()
        • +
      • +
    • Remove static attribute from I2S_Transmit_IT() and I2S_Receive_IT() functions
      • +
    • Move I2SxEXT() macro to extension file
      • +
    • Add I2S_CLOCK_PLLR and I2S_CLOCK_PLLSRC defines for I2S clock source
      • +
    • Add new function I2S_GetInputClock()
      • +
    • +
  • HAL LL FMC update +
      +
    • Add WriteFifo and PageSize fields in the FMC_NORSRAM_InitTypeDef structure
      • +
    • Add FMC_PAGE_SIZE_NONE, FMC_PAGE_SIZE_128, FMC_PAGE_SIZE_256, FMC_PAGE_SIZE_1024, FMC_WRITE_FIFO_DISABLE, FMC_WRITE_FIFO_ENABLE defines
      • +
    • Update FMC_NORSRAM_Init(), FMC_NORSRAM_DeInit() and FMC_NORSRAM_Extended_Timing_Init() functions
      • +
    • +
  • HAL LL USB update +
      +
    • Update USB_OTG_CfgTypeDef structure to support LPM, lpm_enable field added
      • +
    • Update USB_HostInit() and USB_DevInit() functions to support the VBUS Sensing B activation
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Maintenance release to fix known defects and enhancements implementation
    • +
  • Macros and literals renaming to ensure compatibles across STM32 series, backward compatibility maintained thanks to new added file stm32_hal_legacy.h under /Inc/Legacy
    • +
  • Add *.chm UM for all drivers, a UM is provided for each superset RPN
    • +
  • Update drivers to be C++ compliant
    • +
  • Several update on source code formatting, for better UM generation (i.e. Doxygen tags updated)
    • +
  • Two changes done on the HAL requires an update on the application code based on HAL V1.1.0 +
      +
    • LSI_VALUE constant has been corrected in stm32f4xx_hal_conf.h file, its value changed from 40 KHz to 32 KHz
      • +
    • UART, USART, IRDA and SMARTCARD (referenced as PPP here below) drivers: in DMA transmit process, the code has been updated to avoid waiting on TC flag under DMA ISR, PPP TC interrupt is used instead. Below the update to be done on user application: +
        +
      • Configure and enable the USART IRQ in HAL_PPP_MspInit() function
        • +
      • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • +
      • +
    • +
  • HAL generic update +
      +
    • stm32f4xx_hal_def.h +
        +
      • Update NULL definition to fix C++ compilation issue
        • +
      • Add UNUSED() macro
        • +
      • Add a new define __NOINLINE to be used for the no inline code independent from tool chain
        • +
      • +
    • stm32f4xx_hal_conf_template.h +
        +
      • LSI_VALUE constant has been corrected, its value changed from 40 KHz to 32 KHz
        • +
      • +
    • Update all macros and literals naming to be uper case
      • +
    • ErrorCode parameter in PPP_HandleTypeDef structure updated to uint32_t instead of enum HAL_PPP_ErrorTypeDef
      • +
    • Remove the unused FLAG and IT assert macros
      • +
    • +
  • HAL ADC update +
      +
    • Fix temperature sensor channel configuration issue for STM32F427/437xx and STM32F429/439xx devices
      • +
    • +
  • HAL DAC update +
      +
    • HAL_DAC_ConfigChannel(): update the access to the DAC peripheral registers via the hdac handle instance
      • +
    • HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and DAC_FLAG_DMAUDR2
      • +
    • HAL_DACEx_NoiseWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration
      • +
    • HAL_DACEx_TriangleWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration
      • +
    • +
  • HAL CAN update +
      +
    • Unlock the CAN process when communication error occurred
      • +
    • +
  • HAL CORTEX update +
      +
    • Add new macro IS_NVIC_DEVICE_IRQ() to check on negative values of IRQn parameter
      • +
    • +

  • HAL CRYP update

    +
      +
    • HAL_CRYP_DESECB_Decrypt_DMA(): fix the inverted pPlainData and pCypherData parameters issue
      • +
    • CRYPEx_GCMCCM_SetInitVector(): remove the IVSize parameter as the key length 192bits and 256bits are not supported by this version
      • +
    • Add restriction for the CCM Encrypt/Decrypt API’s that only DataType equal to 8bits is supported
      • +
    • HAL_CRYPEx_AESGCM_Finish(): +
        +
      • Add restriction that the implementation is limited to 32bits inputs data length (Plain/Ciphertext, Header) compared with GCM stadards specifications (800-38D)
        • +
      • Update Size parameter on 32bits instead of 16bits
        • +
      • Fix issue with 16-bit Data Type: update to use intrinsic __ROR() instead of __REV16()
        • +
      • +
    • +

  • HAL DCMI update

    +
      +
    • HAL_DCMI_ConfigCROP(): Invert assert macros to check Y0 and Ysize parameters
      • +
    • +

  • HAL DMA update

    +
      +
    • HAL_DMA_Init(): Update to clear the DBM bit in the SxCR register before setting the new configuration
      • +
    • DMA_SetConfig(): add to clear the DBM bit in the SxCR register
      • +
    • +

  • HAL FLASH update

    +
      +
    • Add “HAL_†prefix in the defined values for the FLASH error code +
        +
      • Example: FLASH_ERROR_PGP renamed by HAL_FLASH_ERROR_PGP
        • +
      • +
    • Clear the Flash ErrorCode in the FLASH_WaitForLastOperation() function
      • +
    • Update FLASH_SetErrorCode() function to use “|=†operant to update the Flash ErrorCode parameter in the FLASH handle
      • +
    • IS_FLASH_ADDRESS(): Update the macro check using ‘<=’ condition instead of ‘<’
      • +
    • IS_OPTIONBYTE(): Update the macro check using ‘<=’ condition instead of ‘<’
      • +
    • Add “FLASH_†prefix in the defined values of FLASH Type Program parameter +
        +
      • Example: TYPEPROGRAM_BYTE renamed by FLASH_TYPEPROGRAM_BYTE
        • +
      • +
    • Add “FLASH_†prefix in the defined values of FLASH Type Erase parameter +
        +
      • Example: TYPEERASE_SECTORS renamed by FLASH_TYPEERASE_SECTORS
        • +
      • +
    • Add “FLASH_†prefix in the defined values of FLASH Voltage Range parameter +
        +
      • Example: VOLTAGE_RANGE_1 renamed by FLASH_VOLTAGE_RANGE_1
        • +
      • +
    • Add “OB_†prefix in the defined values of FLASH WRP State parameter +
        +
      • Example: WRPSTATE_ENABLE renamed by OB_WRPSTATE_ENABLE
        • +
      • +
    • Add “OB_†prefix in the defined values of the FLASH PCROP State parameter +
        +
      • PCROPSTATE_DISABLE updated by OB_PCROP_STATE_DISABLE
        • +
      • PCROPSTATE_ENABLE updated by OB_PCROP_STATE_ENABLE
        • +
      • +
    • Change “OBEX†prefix by “OPTIONBYTE†prefix in these defines: +
        +
      • OBEX_PCROP by OPTIONBYTE_PCROP
        • +
      • OBEX_BOOTCONFIG by OPTIONBYTE_BOOTCONFIG
        • +
      • +
    • +
  • HAL ETH update +
      +
    • Fix macros naming typo +
        +
      • Update __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() by __HAL_ETH_EXTI_SET_RISING_EDGE_TRIGGER()
        • +
      • Update __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() by __HAL_ETH_EXTI_SET_FALLING_EDGE_TRIGGER()
        • +
      • +
    • +
  • HAL PWR update +
      +
    • Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register +
        +
      • HAL_PWR_DisableSleepOnExit()
        • +
      • HAL_PWR_EnableSleepOnExit()
        • +
      • HAL_PWR_EnableSEVOnPend()
        • +
      • HAL_PWR_DisableSEVOnPend()
        • +
      • +
    • HAL_PWR_EnterSTOPMode() +
        +
      • Update to clear the CORTEX SLEEPDEEP bit of SCR register before entering in sleep mode
        • +
      • Update usage of __WFE() in low power entry function: if there is a pending event, calling __WFE() will not enter the CortexM4 core to sleep mode. The solution is to made the call below; the first __WFE() is always ignored and clears the event if one was already pending, the second is always applied
        +__SEV()
        +__WFE()
        +__WFE()
        • +
      • +
    • Add new PVD configuration modes +
        +
      • PWR_PVD_MODE_NORMAL
        • +
      • PWR_PVD_MODE_EVENT_RISING
        • +
      • PWR_PVD_MODE_EVENT_FALLING
        • +
      • PWR_PVD_MODE_EVENT_RISING_FALLING
        • +
      • +
    • Add new macros to manage PVD Trigger +
        +
      • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()
        • +
      • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(
        • +
      • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()
        • +
      • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
        • +
      • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
        • +
      • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
        • +
      • +
    • PVD macros: +
        +
      • Remove the __EXTILINE__ parameter
        • +
      • Update to use prefix "__HAL_PWR_PVD_" instead of prefix "__HAL_PVD"
        • +
      • +
    • Rename HAL_PWR_PVDConfig() by HAL_PWR_ConfigPVD()
      • +
    • Rename HAL_PWREx_ActivateOverDrive() by HAL_PWREx_EnableOverDrive()
      • +
    • Rename HAL_PWREx_DeactivateOverDrive() by HAL_PWREx_DisableOverDrive()
      • +
    • +
  • HAL GPIO update +
      +
    • HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call to the CMSIS assert macro to check GPIO instance: IS_GPIO_ALL_INSTANCE()
      • +
    • HAL_GPIO_WritePin(): update to write in BSRR register
      • +
    • Rename GPIO_GET_SOURCE() by GET_GPIO_INDEX() and move this later to file stm32f4xx_hal_gpio_ex.h
      • +
    • Add new define for alternate function GPIO_AF5_SPI3 for STM32F429xx/439xx and STM32F427xx/437xx devices
      • +
    • +
  • HAL HASH update +
      +
    • HAL_HASH_MD5_Start_IT(): fix input address management issue
      +
      • +
    • +
  • HAL RCC update +
      +
    • Rename the following Macros +
        +
      • __PPP_CLK_ENABLE() by __HAL_RCC_PPP_CLK_ENABLE()
        • +
      • __PPP_CLK_DISABLE() by __HAL_RCC_PPP_CLK_DISABLE()
        • +
      • __PPP_FORCE_RESET() by __HAL_RCC_PPP_FORCE_RESET()
        • +
      • __PPP_RELEASE_RESET() by __HAL_RCC_PPP_RELEASE_RESET()
        • +
      • __PPP_CLK_SLEEP_ENABLE() by __HAL_RCC_PPP_CLK_SLEEP_ENABLE()
        • +
      • __PPP_CLK_SLEEP_DISABLE() by __HAL_RCC_PPP_CLK_SLEEP_DISABLE()
        • +
      • +
    • IS_RCC_PLLSAIN_VALUE() macro: update the check condition
      • +
    • Add description of RCC known Limitations
      • +
    • Rename HAL_RCC_CCSCallback() by HAL_RCC_CSSCallback()
      • +
    • HAL_RCC_OscConfig() fix issues: +
        +
      • Remove the disable of HSE oscillator when HSE_BYPASS is used as system clock source or as PPL clock source
        • +
      • Add a check on HSERDY flag when HSE_BYPASS is selected as new state for HSE oscillator.
        • +
      • +
    • Rename __HAL_RCC_I2SCLK() by __HAL_RCC_I2S_Config()
      • +
    • +

  • HAL I2S update

    +
      +
    • HAL_I2S_Init(): add check on I2S instance using CMSIS macro IS_I2S_ALL_INSTANCE()
      • +
    • HAL_I2S_IRQHandler() update for compliance w/ C++
      • +
    • Add use of tmpreg variable in __HAL_I2S_CLEAR_OVRFLAG() and __HAL_I2S_CLEAR_UDRFLAG() macro for compliance with C++
      • +
    • HAL_I2S_GetError(): update to return uint32_t instead of HAL_I2S_ErrorTypeDef enumeration
      • +
    • +

  • HAL I2C update

    +
      +
    • Update to clear the POS bit in the CR1 register at the end of HAL_I2C_Master_Read_IT() and HAL_I2C_Mem_Read_IT() process
      • +
    • Rename HAL_I2CEx_DigitalFilter_Config() by HAL_I2CEx_ConfigDigitalFilter()
      • +
    • Rename HAL_I2CEx_AnalogFilter_Config() by HAL_I2CEx_ConfigAnalogFilter()
      • +
    • Add use of tmpreg variable in __HAL_I2C_CLEAR_ADDRFLAG() and __HAL_I2C_CLEAR_STOPFLAG() macro for compliance with C++
      • +
    • +
  • HAL IrDA update +
      +
    • DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, IrDA TC interrupt is used instead. Below the update to be done on user application: +
        +
      • Configure and enable the USART IRQ in HAL_IRDA_MspInit() function
        • +
      • In stm32f4xx_it.c file, UASRTx_IRQHandler() function: add a call to HAL_IRDA_IRQHandler() function
        • +
      • +
    • IT transmit process; the code has been updated to avoid waiting on TC flag under IRDA ISR, IrDA TC interrupt is used instead. No impact on user application
      • +
    • Rename Macros: add prefix "__HAL" +
        +
      • __IRDA_ENABLE() by __HAL_IRDA_ENABLE()
        • +
      • __IRDA_DISABLE() by __HAL_IRDA_DISABLE()
        • +
      • +
    • +
  • Add new user macros to manage the sample method feature +
      +
    • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE()
      • +
    • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE()
      • +
    • +
  • HAL_IRDA_Transmit_IT(): update to remove the enable of the parity error interrupt
    • +
  • Add use of tmpreg variable in __HAL_IRDA_CLEAR_PEFLAG() macro for compliance with C++
    • +
  • HAL_IRDA_Transmit_DMA() update to follow the right procedure “Transmission using DMA†in the reference manual +
      +
    • Add clear the TC flag in the SR register before enabling the DMA transmit request
      • +
    • +
  • HAL IWDG update +
      +
    • Rename the defined IWDG keys: +
        +
      • KR_KEY_RELOAD by IWDG_KEY_RELOAD
        • +
      • KR_KEY_ENABLE by IWDG_KEY_ENABLE
        • +
      • KR_KEY_EWA by IWDG_KEY_WRITE_ACCESS_ENABLE
        • +
      • KR_KEY_DWA by IWDG_KEY_WRITE_ACCESS_DISABLE
        • +
      • +
    • Add new macros __HAL_IWDG_RESET_HANDLE_STATE() and __HAL_IWDG_CLEAR_FLAG()
      • +
    • Update __HAL_IWDG_ENABLE_WRITE_ACCESS() and __HAL_IWDG_DISABLE_WRITE_ACCESS() as private macro
      • +
    • +

  • HAL SPI update

    +
      +
    • HAL_SPI_TransmitReceive_DMA() update to remove the DMA Tx Error Callback initialization when SPI RxOnly mode is selected
      • +
    • Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix “Unused variable†warning with TrueSTUDIO.
      • +
    • Rename Literals: remove “D†from “DISABLED†and “ENABLED†+
        +
      • SPI_TIMODE_DISABLED by SPI_TIMODE_DISABLE
        • +
      • SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE
        • +
      • SPI_CRCCALCULATION_DISABLED by SPI_CRCCALCULATION_DISABLE
        • +
      • SPI_CRCCALCULATION_ENABLED by SPI_CRCCALCULATION_ENABLE
        • +
      • +
    • Add use of tmpreg variable in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_FREFLAG() and __HAL_SPI_CLEAR_OVRFLAG() macros for compliance with C++
      +
      • +
    • +

  • HAL SDMMC update

    +
      +
    • IS_SDIO_ALL_INSTANCE() macro moved to CMSIS files
      • +
    • +
  • HAL LTDC update +
      +
    • HAL_LTDC_ConfigCLUT: optimize the function when pixel format is LTDC_PIXEL_FORMAT_AL44 +
        +
      • Update the size of color look up table to 16 instead of 256 when the pixel format is LTDC_PIXEL_FORMAT_AL44
        • +
      • +
    • +
  • HAL NAND update +
      +
    • Rename NAND Address structure to NAND_AddressTypeDef instead of NAND_AddressTypedef
      • +
    • Update the used algorithm of these functions +
        +
      • HAL_NAND_Read_Page()
        • +
      • HAL_NAND_Write_Page()
        • +
      • HAL_NAND_Read_SpareArea()
        • +
      • HAL_NAND_Write_SpareArea()
        • +
      • +
    • HAL_NAND_Write_Page(): move initialization of tickstart before while loop
      • +
    • HAL_NAND_Erase_Block(): add whait until NAND status is ready before exiting this function
      • +
    • +
  • HAL NOR update +
      +
    • Rename NOR Address structure to NOR_AddressTypeDef instead of NOR_AddressTypedef
      • +
    • NOR Status literals renamed +
        +
      • NOR_SUCCESS by HAL_NOR_STATUS_SUCCESS
        • +
      • NOR_ONGOING by HAL_NOR_STATUS_ONGOING
        • +
      • NOR_ERROR by HAL_NOR_STATUS_ERROR
        • +
      • NOR_TIMEOUT by HAL_NOR_STATUS_TIMEOUT
        • +
      • +
    • HAL_NOR_GetStatus() update to fix Timeout issue and exit from waiting loop when timeout occurred
      • +
    • +
  • HAL PCCARD update +
      +
    • Rename PCCARD Address structure to HAL_PCCARD_StatusTypeDef instead of CF_StatusTypedef
      • +
    • PCCARD Status literals renamed +
        +
      • CF_SUCCESS by HAL_PCCARD_STATUS_SUCCESS
        • +
      • CF_ONGOING by HAL_PCCARD_STATUS_ONGOING
        • +
      • CF_ERROR by HAL_PCCARD_STATUS_ERROR
        • +
      • CF_TIMEOUT by HAL_PCCARD_STATUS_TIMEOUT
        • +
      • +
    • Update “CF†by “PCCARD†in functions, literals and macros
      • +
    • +
  • HAL PCD update +
      +
    • Rename functions +
        +
      • HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup()
        • +
      • HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup()
        • +
      • +
    • Rename literals +
        +
      • USB_FS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
        • +
      • USB_FS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
        • +
      • USB_FS_EXTI_TRIGGER_BOTH_EDGE() by USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
        • +
      • USB_HS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
        • +
      • USB_HS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
        • +
      • USB_HS_EXTI_TRIGGER_BOTH_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
        • +
      • USB_HS_EXTI_LINE_WAKEUP by USB_OTG_HS_EXTI_LINE_WAKEUP
        • +
      • USB_FS_EXTI_LINE_WAKEUP by USB_OTG_FS_EXTI_LINE_WAKEUP
        • +
      • +
    • +
  • Rename USB EXTI macros (FS, HS referenced as SUBBLOCK here below) +
      +
    • __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()
      +
      • +
    • __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT()
      • +
    • __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG()
      • +
    • __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG()
      • +
    • __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE()
      • +
    • __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
      • +
    • __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
      • +
    • __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GENERATE_SWIT()
      +
      • +
    • +
  • HAL RNG update +
      +
    • Add new functions +
        +
      • HAL_RNG_GenerateRandomNumber(): to generate a 32-bits random number, return random value in argument and return HAL status.
        • +
      • HAL_RNG_GenerateRandomNumber_IT(): to start generation of the 32-bits random number, user should call the HAL_RNG_ReadLastRandomNumber() function under the HAL_RNG_ReadyCallback() to get the generated random value.
        • +
      • HAL_RNG_ReadLastRandomNumber(): to return the last random value stored in the RNG handle
        • +
      • +
    • HAL_RNG_GetRandomNumber(): return value update (obsolete), replaced by HAL_RNG_GenerateRandomNumber()
      • +
    • HAL_RNG_GetRandomNumber_IT(): wrong implementation (obsolete), replaced by HAL_RNG_GenerateRandomNumber_IT()
      • +
    • __HAL_RNG_CLEAR_FLAG() macro (obsolete), replaced by new __HAL_RNG_CLEAR_IT() macro
      • +
    • Add new define for RNG ready interrupt: RNG_IT_DRDY
      • +
    • +
  • HAL RTC update +
      +

    • HAL_RTC_GetTime() and HAL_RTC_GetDate(): add the comment below
      +* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
      +* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
      +* Reading RTC current time locks the values in calendar shadow registers until Current date is read.

      • +
    • Rename literals: add prefix "__HAL" +
        +
      • FORMAT_BIN by HAL_FORMAT_BIN
        • +
      • FORMAT_BCD by HAL_FORMAT_BCD
        • +
      • +
    • Rename macros (ALARM, WAKEUPTIMER and TIMESTAMP referenced as SUBBLOCK here below) +
        +
      • __HAL_RTC_EXTI_ENABLE_IT() by __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT()
        • +
      • __HAL_RTC_EXTI_DISABLE_IT() by __HAL_RTC__SUBBLOCK_EXTI_DISABLE_IT()
        • +
      • __HAL_RTC_EXTI_CLEAR_FLAG() by __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG()
        • +
      • __HAL_RTC_EXTI_GENERATE_SWIT() by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT()
        • +
      • +
    • Add new macros (ALARM, WAKEUPTIMER and TAMPER_TIMESTAMP referenced as SUBBLOCK here below) +
        +
      • __HAL_RTC_SUBBLOCK_GET_IT_SOURCE()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG()
        • +
      • +
    • +
  • HAL SAI update +
      +
    • Update SAI_STREOMODE by SAI_STEREOMODE
      • +
    • Update FIFO status Level defines in upper case
      • +
    • Rename literals: remove “D†from “DISABLED†and “ENABLED†+
        +
      • SAI_OUTPUTDRIVE_DISABLED by SAI_OUTPUTDRIVE_DISABLE
        • +
      • SAI_OUTPUTDRIVE_ENABLED by SAI_OUTPUTDRIVE_ENABLE
        • +
      • SAI_MASTERDIVIDER_ENABLED by SAI_MASTERDIVIDER_ENABLE
        • +
      • SAI_MASTERDIVIDER_DISABLED by SAI_MASTERDIVIDER_DISABLE
        • +
      • +
    • +
  • HAL SD update +
      +
    • Rename SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS
      • +
    • SD_PowerON() updated to add 1ms required power up waiting time before starting the SD initialization sequence
      • +
    • SD_DMA_RxCplt()/SD_DMA_TxCplt(): add a call to HAL_DMA_Abort()
      • +
    • HAL_SD_ReadBlocks() update to set the defined DATA_BLOCK_SIZE as SDIO DataBlockSize parameter
      • +
    • HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() update to call the HAL_DMA_Start_IT() function with DMA Datalength set to BlockSize/4 as the DMA is configured in word
      • +
    • +
  • HAL SMARTCARD update +
      +
    • DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, SMARTCARD TC interrupt is used instead. Below the update to be done on user application: +
        +
      • Configure and enable the USART IRQ in HAL_SAMRTCARD_MspInit() function
        • +
      • In stm32f4xx_it.c file, UASRTx_IRQHandler() function: add a call to HAL_SMARTCARD_IRQHandler() function
        • +
      • +
    • IT transmit process; the code has been updated to avoid waiting on TC flag under SMARTCARD ISR, SMARTCARD TC interrupt is used instead. No impact on user application
      • +
    • Rename macros: add prefix "__HAL" +
        +
      • __SMARTCARD_ENABLE() by __HAL_SMARTCARD_ENABLE()
        • +
      • __SMARTCARD_DISABLE() by __HAL_SMARTCARD_DISABLE()
        • +
      • __SMARTCARD_ENABLE_IT() by __HAL_SMARTCARD_ENABLE_IT()
        • +
      • __SMARTCARD_DISABLE_IT() by __HAL_SMARTCARD_DISABLE_IT()
        • +
      • __SMARTCARD_DMA_REQUEST_ENABLE() by __HAL_SMARTCARD_DMA_REQUEST_ENABLE()
        • +
      • __SMARTCARD_DMA_REQUEST_DISABLE() by __HAL_SMARTCARD_DMA_REQUEST_DISABLE()
        • +
      • +
    • Rename literals: remove “D†from “DISABLED†and “ENABLED†+
        +
      • SMARTCARD_NACK_ENABLED by SMARTCARD_NACK_ENABLE
        • +
      • SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE
        • +
      • +
    • Add new user macros to manage the sample method feature +
        +
      • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE()
        • +
      • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE()
        • +
      • +
    • Add use of tmpreg variable in __HAL_SMARTCARD_CLEAR_PEFLAG() macro for compliance with C++
      • +
    • HAL_SMARTCARD_Transmit_DMA() update to follow the right procedure “Transmission using DMA†in the reference manual +
        +
      • Add clear the TC flag in the SR register before enabling the DMA transmit request
        • +
      • +
    • +
  • HAL TIM update +
      +
    • Add TIM_CHANNEL_ALL as possible value for all Encoder Start/Stop APIs Description
      • +
    • HAL_TIM_OC_ConfigChannel() remove call to IS_TIM_FAST_STATE() assert macro
      • +
    • HAL_TIM_PWM_ConfigChannel() add a call to IS_TIM_FAST_STATE() assert macro to check the OCFastMode parameter
      • +
    • HAL_TIM_DMADelayPulseCplt() Update to set the TIM Channel before to call HAL_TIM_PWM_PulseFinishedCallback()
      • +
    • HAL_TIM_DMACaptureCplt() update to set the TIM Channel before to call HAL_TIM_IC_CaptureCallback()
      • +
    • TIM_ICx_ConfigChannel() update to fix Timer CCMR1 register corruption when setting ICFilter parameter
      • +
    • HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() update to abort the DMA transfer for the specific TIM channel
      • +
    • Add new function for TIM Slave configuration in IT mode: HAL_TIM_SlaveConfigSynchronization_IT()
      • +
    • HAL_TIMEx_ConfigBreakDeadTime() add an assert check on Break & DeadTime parameters values
      • +
    • HAL_TIMEx_OCN_Start_IT() add the enable of Break Interrupt for all output modes
      • +
    • Add new macros to ENABLE/DISABLE URS bit in TIM CR1 register: +
        +
      • __HAL_TIM_URS_ENABLE()
        • +
      • __HAL_TIM_URS_DISABLE()
        • +
      • +
    • Add new macro for TIM Edge modification: __HAL_TIM_SET_CAPTUREPOLARITY()
      • +
    • +
  • HAL UART update +
      +
    • Add IS_LIN_WORD_LENGTH() and IS_LIN_OVERSAMPLING() macros: to check respectively WordLength and OverSampling parameters in LIN mode
      • +
    • DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, UART TC interrupt is used instead. Below the update to be done on user application: +
        +
      • Configure and enable the USART IRQ in HAL_UART_MspInit() function
        • +
      • In stm32f4xx_it.c file, USARTx_IRQHandler() function: add a call to HAL_UART_IRQHandler() function
        • +
      • +
    • IT transmit process; the code has been updated to avoid waiting on TC flag under UART ISR, UART TC interrupt is used instead. No impact on user application
      • +
    • Rename macros: +
        +
      • __HAL_UART_ONEBIT_ENABLE() by __HAL_UART_ONE_BIT_SAMPLE_ENABLE()
        • +
      • __HAL_UART_ONEBIT_DISABLE() by __HAL_UART_ONE_BIT_SAMPLE_DISABLE()
        • +
      • +
    • Rename literals: +
        +
      • UART_WAKEUPMETHODE_IDLELINE by UART_WAKEUPMETHOD_IDLELINE
        • +
      • UART_WAKEUPMETHODE_ADDRESSMARK by UART_WAKEUPMETHOD_ADDRESSMARK
        • +
      • +
    • Add use of tmpreg variable in __HAL_UART_CLEAR_PEFLAG() macro for compliance with C++
      • +
    • HAL_UART_Transmit_DMA() update to follow the right procedure “Transmission using DMA†in the reference manual +
        +
      • Add clear the TC flag in the SR register before enabling the DMA transmit request
        • +
      • +
    • +
  • HAL USART update +
      +
    • DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, USART TC interrupt is used instead. Below the update to be done on user application: +
        +
      • Configure and enable the USART IRQ in HAL_USART_MspInit() function
        • +
      • In stm32f4xx_it.c file, USARTx_IRQHandler() function: add a call to HAL_USART_IRQHandler() function
        • +
      • +
    • IT transmit process; the code has been updated to avoid waiting on TC flag under USART ISR, USART TC interrupt is used instead. No impact on user application
      • +
    • HAL_USART_Init() update to enable the USART oversampling by 8 by default in order to reach max USART frequencies
      • +
    • USART_DMAReceiveCplt() update to set the new USART state after checking on the old state
      • +
    • HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() update to follow the right procedure “Transmission using DMA†in the reference manual +
        +
      • Add clear the TC flag in the SR register before enabling the DMA transmit request
        • +
      • +
    • Rename macros: +
        +
      • __USART_ENABLE() by __HAL_USART_ENABLE()
        • +
      • __USART_DISABLE() by __HAL_USART_DISABLE()
        • +
      • __USART_ENABLE_IT() by __HAL_USART_ENABLE_IT()
        • +
      • __USART_DISABLE_IT() by __HAL_USART_DISABLE_IT()
        • +
      • +
    • Rename literals: remove “D†from “DISABLED†and “ENABLED†+
        +
      • USART_CLOCK_DISABLED by USART_CLOCK_DISABLE
        • +
      • USART_CLOCK_ENABLED by USART_CLOCK_ENABLE
        • +
      • USARTNACK_ENABLED by USART_NACK_ENABLE
        • +
      • USARTNACK_DISABLED by USART_NACK_DISABLE
        • +
      • +
    • Add new user macros to manage the sample method feature +
        +
      • __HAL_USART_ONE_BIT_SAMPLE_ENABLE()
        • +
      • __HAL_USART_ONE_BIT_SAMPLE_DISABLE()
        • +
      • +
    • Add use of tmpreg variable in __HAL_USART_CLEAR_PEFLAG() macro for compliance with C++
      • +
    • +
  • HAL WWDG update +
      +
    • Add new parameter in __HAL_WWDG_ENABLE_IT() macro
      • +
    • Add new macros to manage WWDG IT & correction: +
        +
      • __HAL_WWDG_DISABLE()
        • +
      • __HAL_WWDG_DISABLE_IT()
        • +
      • __HAL_WWDG_GET_IT()
        • +
      • __HAL_WWDG_GET_IT_SOURCE()
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F411xE devices
    • +
  • HAL generic update +
      +
    • Enhance HAL delay and time base implementation +
        +
      • Systick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source)
        • +
      • Functions affecting time base configurations are declared as __Weak to make override possible in case of other implementations in user file, for more details please refer to HAL_TimeBase example
        • +
      • +
    • Fix flag clear procedure: use atomic write operation “=†instead of ready-modify-write operation “|=†or “&=â€
      • +
    • Fix on Timeout management, Timeout value set to 0 passed to API automatically exits the function after checking the flag without any wait
      • +
    • Common update for the following communication peripherals: SPI, UART, USART and IRDA +
        +
      • Add DMA circular mode support
        • +
      • Remove lock from recursive process
        • +
      • +
    • Add new macro __HAL_RESET_HANDLE_STATE to reset a given handle state
      • +
    • Add a new attribute for functions executed from internal SRAM and depending from Compiler implementation
      • +
    • When USE_RTOS == 1 (in stm32l0xx_hal_conf.h), the __HAL_LOCK() is not defined instead of being defined empty
      • +
    • Miscellaneous comments and formatting update
      • +
    • stm32f4xx_hal_conf_template.h +
        +
      • Add a new define for LSI default value LSI_VALUE
        • +
      • Add a new define for LSE default value LSE_VALUE
        • +
      • Add a new define for Tick interrupt priority TICK_INT_PRIORITY (needed for the enhanced time base implementation)
        • +
      • Important Note: aliases has been added for any API naming change, to keep compatibility with previous version
        • +
      • +
    • +
  • HAL GPIO update +
      +
    • Add a new macro __HAL_GPIO_EXTI_GENERATE_SWIT() to manage the generation of software interrupt on selected EXTI line
      • +
    • HAL_GPIO_Init(): use temporary variable when modifying the registers, to avoid unexpected transition in the GPIO pin configuration
      • +
    • Remove IS_GET_GPIO_PIN macro
      • +
    • Add a new function HAL_GPIO_LockPin()
      • +
    • Private Macro __HAL_GET_GPIO_SOURCE renamed into GET_GPIO_SOURCE
      • +
    • Add the support of STM32F411xx devices : add the new Alternate functions values related to new remap added for SPI, USART, I2C
      • +
    • Update the following HAL GPIO macros description: rename EXTI_Linex by GPIO_PIN_x +
        +
      • __HAL_GPIO_EXTI_CLEAR_IT()
        • +
      • __HAL_GPIO_EXTI_GET_IT()
        • +
      • __HAL_GPIO_EXTI_CLEAR_FLAG()
        • +
      • __HAL_GPIO_EXTI_GET_FLAG()
        • +
      • +
    • +

  • HAL DMA update

    +
      +
    • Fix in HAL_DMA_PollForTransfer() to: +
        +
      • set DMA error code in case of HAL_ERROR status
        • +
      • set HAL Unlock before DMA state update
        • +
      • +
    • +

  • HAL DMA2D update

    +
      +
    • Add configuration of source address in case of A8 or A4 M2M_PFC DMA2D mode
      • +
    • +
  • HAL FLASH update +
      +
    • Functions reorganization update, depending on the features supported by each STM32F4 device
      • +
    • Add new driver (stm32f4xx_hal_flash_ramfunc.h/.c) to manage function executed from RAM, these functions are available only for STM32F411xx Devices +
        +
      • FLASH_StopFlashInterfaceClk() : Stop the flash interface while System Run
        • +
      • FLASH_StartFlashInterfaceClk() : Stop the flash interface while System Run
        • +
      • FLASH_EnableFlashSleepMode() : Enable the flash sleep while System Run
        • +
      • FLASH_DisableFlashSleepMode() : Disable the flash sleep while System Run
        • +
      • +
    • +
  • HAL PWR update +
      +
    • HAL_PWR_PVDConfig(): add clear of the EXTI trigger before new configuration
      • +
    • Fix in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function
      • +
    • HAL_PWR_EnterSLEEPMode() +
        +
      • Remove disable and enable of SysTick Timer
        • +
      • Update usage of __WFE() in low power entry function: if there is a pending event, calling __WFE() will not enter the CortexM4 core to sleep mode. The solution is to made the call below; the first __WFE() is always ignored and clears the event if one was already pending, the second is always applied
        +__SEV()
        +__WFE()
        +__WFE()
        • +
      • +
    • Add new macro for software event generation __HAL_PVD_EXTI_GENERATE_SWIT()
      • +
    • Remove the following defines form Generic driver and add them under extension driver because they are only used within extension functions. +
        +
      • CR_FPDS_BB: used within HAL_PWREx_EnableFlashPowerDown() function
        • +
      • CSR_BRE_BB: used within HAL_PWREx_EnableBkUpReg() function
        • +
      • +
    • Add the support of STM32F411xx devices add the define STM32F411xE +
        +
      • For STM32F401xC, STM32F401xE and STM32F411xE devices add the following functions used to enable or disable the low voltage mode for regulators +
          +
        • HAL_PWREx_EnableMainRegulatorLowVoltage()
          • +
        • HAL_PWREx_DisableMainRegulatorLowVoltage()
          • +
        • HAL_PWREx_EnableLowRegulatorLowVoltage()
          • +
        • HAL_PWREx_DisableLowRegulatorLowVoltage()
          • +
        • +
      • For STM32F42xxx/43xxx devices, add a new function for Under Driver management as the macro already added for this mode is not sufficient: HAL_PWREx_EnterUnderDriveSTOPMode()
        • +
      • +
    • +
  • HAL RCC update +
      +
    • In HAL_RCC_ClockConfig() function: update the AHB clock divider before clock switch to new source
      • +
    • Allow to calibrate the HSI when it is used as system clock source
      • +
    • Rename the following macros +
        +
      • __OTGFS_FORCE_RESET () by __USB_OTG_FS_FORCE_RESET()
        • +
      • __OTGFS_RELEASE_RESET () by __USB_OTG_FS_RELEASE_RESET()
        • +
      • __OTGFS_CLK_SLEEP_ENABLE () by __USB_OTG_FS_CLK_SLEEP_ENABLE()
        • +
      • __OTGFS_CLK_SLEEP_DISABLE () by __USB_OTG_FS_CLK_SLEEP_DISABLE()
        • +
      • +
    • Add new field PLLI2SM in RCC_PLLI2SInitTypeDef structure, this division factor is added for PLLI2S VCO input clock only STM32F411xE devices => the FW compatibility is broken vs. STM32F401xx devices
      • +
    • Update HAL_RCCEx_PeriphCLKConfig() and HAL_RCCEx_GetPeriphCLKConfig() functions to support the new PLLI2SM
      • +
    • Add new function to manage the new LSE mode : HAL_RCCEx_SelectLSEMode()
      • +
    • Reorganize the macros depending from Part number used and make them more clear
      • +
    • +

  • HAL UART update

    +
      +
    • Add new macros to control CTS and RTS
      • +
    • Add specific macros to manage the flags cleared only by a software sequence +
        +
      • __HAL_UART_CLEAR_PEFLAG()
        • +
      • __HAL_UART_CLEAR_FEFLAG()
        • +
      • __HAL_UART_CLEAR_NEFLAG()
        • +
      • __HAL_UART_CLEAR_OREFLAG()
        • +
      • __HAL_UART_CLEAR_IDLEFLAG()
        • +
      • +
    • Add several enhancements without affecting the driver functionalities +
        +
      • Remove the check on RXNE set after reading the Data in the DR register
        • +
      • Update the transmit processes to use TXE instead of TC
        • +
      • Update HAL_UART_Transmit_IT() to enable UART_IT_TXE instead of UART_IT_TC
        • +
      • +
    • +

  • HAL USART update

    +
      +
    • Add specific macros to manage the flags cleared only by a software sequence +
        +
      • __HAL_USART_CLEAR_PEFLAG()
        • +
      • __HAL_USART_CLEAR_FEFLAG()
        • +
      • __HAL_USART_CLEAR_NEFLAG()
        • +
      • __HAL_USART_CLEAR_OREFLAG()
        • +
      • __HAL_USART_CLEAR_IDLEFLAG()
        • +
      • +
    • Update HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC
      • +
    • +

  • HAL IRDA update

    +
      +
    • Add specific macros to manage the flags cleared only by a software sequence __HAL_IRDA_CLEAR_PEFLAG() __HAL_ IRDA _CLEAR_FEFLAG() __HAL_ IRDA _CLEAR_NEFLAG() __HAL_ IRDA _CLEAR_OREFLAG() __HAL_ IRDA _CLEAR_IDLEFLAG()
      • +
    • Add several enhancements without affecting the driver functionalities +
        +
      • Remove the check on RXNE set after reading the Data in the DR register
        • +
      • Update HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC
        • +
      • +
    • Add the following APIs used within DMA process +
        +
      • HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
        • +
      • HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
        • +
      • HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
        • +
      • void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
        • +
      • void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
        • +
      • +
    • +

  • HAL SMARTCARD update

    +
      +
    • Add specific macros to manage the flags cleared only by a software sequence +
        +
      • __HAL_SMARTCARD_CLEAR_PEFLAG()
        • +
      • __HAL_SMARTCARD_CLEAR_FEFLAG()
        • +
      • __HAL_SMARTCARD_CLEAR_NEFLAG()
        • +
      • __HAL_SMARTCARD_CLEAR_OREFLAG()
        • +
      • __HAL_SMARTCARD_CLEAR_IDLEFLAG()
        • +
      • +
    • Add several enhancements without affecting the driver functionalities +
        +
      • Add a new state HAL_SMARTCARD_STATE_BUSY_TX_RX and all processes has been updated accordingly
        • +
      • Update HAL_SMARTCARD_Transmit_IT() to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC
        • +
      • +
    • +
  • HAL SPI update +
      +
    • Bugs fix +
        +
      • SPI interface is used in synchronous polling mode: at high clock rates like SPI prescaler 2 and 4, calling HAL_SPI_TransmitReceive() returns with error HAL_TIMEOUT
        • +
      • HAL_SPI_TransmitReceive_DMA() does not clean up the TX DMA, so any subsequent SPI calls return the DMA error
        • +
      • HAL_SPI_Transmit_DMA() is failing when data size is equal to 1 byte
        • +
      • +
    • Add the following APIs used within the DMA process +
        +
      • HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
        • +
      • HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
        • +
      • HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
        • +
      • void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
        • +
      • void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
        • +
      • void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
        • +
      • +
    • +
  • HAL RNG update +
      +
    • Add a conditional define to make this driver visible for all STM32F4xx devices except STM32F401xx and STM32F411xx Devices.
      • +
    • +
  • HAL CRC update +
      +
    • These macros are added to read/write the CRC IDR register: __HAL_CRC_SET_IDR() and __HAL_CRC_GET_IDR()
      • +
    • +
  • HAL DAC update +
      +
    • Enhance the DMA channel configuration when used with DAC
      • +
    • +
  • HAL TIM update +
      +
    • HAL_TIM_IRQHandler(): update to check the input capture channel 3 and 4 in CCMR2 instead of CCMR1
      • +
    • __HAL_TIM_PRESCALER() updated to use ‘=’ instead of ‘|=’
      • +
    • Add the following macro in TIM HAL driver +
        +
      • __HAL_TIM_GetCompare()
        • +
      • __HAL_TIM_GetCounter()
        • +
      • __HAL_TIM_GetAutoreload()
        • +
      • __HAL_TIM_GetClockDivision()
        • +
      • __HAL_TIM_GetICPrescaler()
        • +
      • +
    • +
  • HAL SDMMC update +
      +
    • Use of CMSIS constants instead of magic values
      • +
    • Miscellaneous update in functions internal coding
      • +
    • +
  • HAL NAND update +
      +
    • Fix issue of macros returning wrong address for NAND blocks
      • +
    • Fix issue for read/write NAND page/spare area
      • +
    • +
  • HAL NOR update +
      +
    • Add the NOR address bank macro used within the API
      • +
    • Update NOR API implementation to avoid the use of NOR address bank hard coded
      • +
    • +
  • HAL HCD update +
      +
    • HCD_StateTypeDef structure members renamed
      • +
    • These macro are renamed +
        +
      • __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
        • +
      • __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)
        • +
      • __HAL_IS_INVALID_INTERRUPT(__HANDLE__) by __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)
        • +
      • +
    • +
  • HAL PCD update +
      +
    • HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() renamed into HAL_PCDEx_SetTxFiFo() and HAL_PCDEx_SetRxFiFo() and moved to the extension files stm32f4xx_hal_pcd_ex.h/.c
      • +
    • PCD_StateTypeDef structure members renamed
      • +
    • Fix incorrect masking of TxFIFOEmpty
      • +
    • stm32f4xx_ll_usb.c: fix issue in HS mode
      • +
    • New macros added +
        +
      • __HAL_PCD_IS_PHY_SUSPENDED()
        • +
      • __HAL_USB_HS_EXTI_GENERATE_SWIT()
        • +
      • __HAL_USB_FS_EXTI_GENERATE_SWIT()
        • +
      • +
    • These macro are renamed +
        +
      • __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
        • +
      • __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)
        • +
      • __HAL_IS_INVALID_INTERRUPT(__HANDLE__) by __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)
        • +
      • __HAL_PCD_UNGATE_CLOCK(__HANDLE__) by __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
        • +
      • __HAL_PCD_GATE_CLOCK(__HANDLE___) by __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)
        • +
      • +
    • +
  • HAL ETH update +
      +
    • Update HAL_ETH_GetReceivedFrame_IT() function to return HAL_ERROR if the received packet is not complete
      • +
    • Use HAL_Delay() instead of counting loop
      • +
    • __HAL_ETH_MAC_CLEAR_FLAG() macro is removed: the MACSR register is read only
      • +
    • Add the following macros used to Wake up the device from STOP mode by Ethernet event : +
        +
      • __HAL_ETH_EXTI_ENABLE_IT()
        • +
      • __HAL_ETH_EXTI_DISABLE_IT()
        • +
      • __HAL_ETH_EXTI_GET_FLAG()
        • +
      • __HAL_ETH_EXTI_CLEAR_FLAG()
        • +
      • __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER()
        • +
      • __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER()
        • +
      • __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER()
        • +
      • +
    • +
  • HAL WWDG update +
      +
    • Update macro parameters to use underscore: __XXX__
      • +
    • Use of CMSIS constants instead of magic values
      • +
    • Use MODIFY_REG macro in HAL_WWDG_Init()
      • +
    • Add IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() and HAL_WWDG_DeInit()
      • +
    • +
  • HAL IWDG update +
      +
    • Use WRITE_REG instead of SET_BIT for all IWDG macros
      • +
    • __HAL_IWDG_CLEAR_FLAG removed: no IWDG flag cleared by access to SR register
      • +
    • Use MODIFY_REG macro in HAL_IWDG_Init()
      • +
    • Add IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init()Add the following macros used to Wake
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • First official release
    • +
+
+
+
+ +
+

For complete documentation on STM32F4xx, visit: [www.st.com/stm32f4]

+

This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.

+
+ + diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index fb7811dde4..de14a0e331 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.8.1 + * @brief STM32F4xx HAL Driver version number V1.8.2 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ @@ -368,7 +368,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) /** * @brief Return tick frequency. - * @retval tick period in Hz + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. */ HAL_TickFreqTypeDef HAL_GetTickFreq(void) { diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c index 128b23608a..9ad943d8d0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c @@ -266,7 +266,7 @@ * @{ */ /* Private function prototypes -----------------------------------------------*/ -static void ADC_Init(ADC_HandleTypeDef* hadc); +static void ADC_Init(ADC_HandleTypeDef *hadc); static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); static void ADC_DMAError(DMA_HandleTypeDef *hdma); static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); @@ -308,12 +308,12 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } @@ -331,12 +331,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); } - if(hadc->State == HAL_ADC_STATE_RESET) + if (hadc->State == HAL_ADC_STATE_RESET) { #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ @@ -402,12 +402,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } @@ -424,19 +424,19 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } - /* DeInit the low level hardware: RCC clock, NVIC */ - hadc->MspDeInitCallback(hadc); + /* DeInit the low level hardware: RCC clock, NVIC */ + hadc->MspDeInitCallback(hadc); #else - /* DeInit the low level hardware: RCC clock, NVIC */ - HAL_ADC_MspDeInit(hadc); + /* DeInit the low level hardware: RCC clock, NVIC */ + HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ @@ -659,7 +659,7 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -674,7 +674,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -713,7 +713,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; @@ -728,7 +728,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -736,14 +736,14 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -786,15 +786,15 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { #if defined(ADC2) && defined(ADC3) - if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ - || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) { #endif /* ADC2 || ADC3 */ /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -806,10 +806,10 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } } @@ -836,7 +836,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) * * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -849,7 +849,7 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, @@ -879,7 +879,7 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart = 0U; @@ -890,7 +890,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and polling for end of each conversion. */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && - HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -905,15 +905,15 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti tickstart = HAL_GetTick(); /* Check End of conversion flag */ - while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + while (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + if (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -939,10 +939,10 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); @@ -968,7 +968,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart = 0U; @@ -980,15 +980,15 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy tickstart = HAL_GetTick(); /* Check selected event flag */ - while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + while (!(__HAL_ADC_GET_FLAG(hadc, EventType))) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + if (!(__HAL_ADC_GET_FLAG(hadc, EventType))) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1003,7 +1003,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy } /* Analog watchdog (level out of window) event */ - if(EventType == ADC_AWD_EVENT) + if (EventType == ADC_AWD_EVENT) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); @@ -1034,7 +1034,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy * the configuration information for the specified ADC. * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; @@ -1049,7 +1049,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -1057,14 +1057,14 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -1110,15 +1110,15 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { #if defined(ADC2) && defined(ADC3) - if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ - || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) { #endif /* ADC2 || ADC3 */ /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -1130,10 +1130,10 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } } @@ -1159,7 +1159,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1172,9 +1172,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { - /* Disable ADC end of conversion interrupt for regular group */ + /* Disable ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); /* Set ADC state */ @@ -1196,7 +1196,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { uint32_t tmp1 = 0U, tmp2 = 0U; @@ -1211,7 +1211,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) tmp1 = tmp_sr & ADC_FLAG_EOC; tmp2 = tmp_cr1 & ADC_IT_EOC; /* Check End of conversion flag for regular channels */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) @@ -1226,10 +1226,10 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ @@ -1260,7 +1260,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) tmp1 = tmp_sr & ADC_FLAG_JEOC; tmp2 = tmp_cr1 & ADC_IT_JEOC; /* Check End of conversion flag for injected channels */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) @@ -1273,12 +1273,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* by external trigger, scan sequence on going or by automatic injected */ /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && - (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE)))) { /* Disable ADC end of single conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); @@ -1295,9 +1295,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Conversion complete callback */ /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->InjectedConvCpltCallback(hadc); + hadc->InjectedConvCpltCallback(hadc); #else - HAL_ADCEx_InjectedConvCpltCallback(hadc); + HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ @@ -1307,9 +1307,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) tmp1 = tmp_sr & ADC_FLAG_AWD; tmp2 = tmp_cr1 & ADC_IT_AWD; /* Check Analog watchdog flag */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); @@ -1329,7 +1329,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) tmp1 = tmp_sr & ADC_FLAG_OVR; tmp2 = tmp_cr1 & ADC_IT_OVR; /* Check Overrun flag */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Note: On STM32F4, ADC overrun can be set through other parameters */ /* refer to description of parameter "EOCSelection" for more */ @@ -1343,9 +1343,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); + hadc->ErrorCallback(hadc); #else - HAL_ADC_ErrorCallback(hadc); + HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the Overrun flag */ @@ -1361,7 +1361,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; @@ -1376,7 +1376,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Enable the ADC peripheral */ /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -1384,7 +1384,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } @@ -1392,13 +1392,13 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Check ADC DMA Mode */ /* - disable the DMA Mode if it is already enabled */ - if((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA) + if ((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA) { CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -1463,15 +1463,15 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { #if defined(ADC2) && defined(ADC3) - if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ - || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) { #endif /* ADC2 || ADC3 */ /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -1483,10 +1483,10 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } } @@ -1509,7 +1509,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; @@ -1524,7 +1524,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Disable the selected ADC DMA mode */ hadc->Instance->CR2 &= ~ADC_CR2_DMA; @@ -1565,7 +1565,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval Converted value */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) { /* Return the selected ADC converted value */ return hadc->Instance->DR; @@ -1577,7 +1577,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -1592,7 +1592,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -1607,7 +1607,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -1642,7 +1642,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * @verbatim =============================================================================== @@ -1658,15 +1658,15 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * @{ */ - /** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param sConfig ADC configuration structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +/** +* @brief Configures for the selected ADC regular channel its corresponding +* rank in the sequencer and its sample time. +* @param hadc pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @param sConfig ADC configuration structure. +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; @@ -1725,10 +1725,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); } - /* Pointer to the common control register to which is belonging hadc */ - /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ - /* control register) */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */ if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) @@ -1754,12 +1754,12 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Enable the Temperature sensor and VREFINT channel*/ tmpADC_Common->CCR |= ADC_CCR_TSVREFE; - if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } @@ -1789,7 +1789,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * that contains the configuration information of ADC analog watchdog. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) { #ifdef USE_FULL_ASSERT uint32_t tmp = 0U; @@ -1809,7 +1809,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* Process locked */ __HAL_LOCK(hadc); - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { /* Enable the ADC Analog watchdog interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); @@ -1871,7 +1871,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * the configuration information for the specified ADC. * @retval HAL state */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) { /* Return ADC state */ return hadc->State; @@ -1903,7 +1903,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) * the configuration information for the specified ADC. * @retval None */ -static void ADC_Init(ADC_HandleTypeDef* hadc) +static void ADC_Init(ADC_HandleTypeDef *hadc) { ADC_Common_TypeDef *tmpADC_Common; @@ -1934,7 +1934,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { /* Select external trigger to start conversion */ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); @@ -1955,7 +1955,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) hadc->Instance->CR2 &= ~(ADC_CR2_CONT); hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); - if(hadc->Init.DiscontinuousConvMode != DISABLE) + if (hadc->Init.DiscontinuousConvMode != DISABLE) { assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); @@ -1994,7 +1994,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) @@ -2008,10 +2008,10 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ @@ -2046,8 +2046,8 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - else - { + else + { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } @@ -2062,8 +2062,8 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) */ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Half conversion callback */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else @@ -2079,11 +2079,11 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) */ static void ADC_DMAError(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR_DMA; + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hadc->State = HAL_ADC_STATE_ERROR_DMA; /* Set ADC error code to DMA error */ hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - /* Error callback */ + /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c index cff0760cdc..7db1993715 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c @@ -143,7 +143,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; uint32_t tmp1 = 0U, tmp2 = 0U; @@ -156,7 +156,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -164,14 +164,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ @@ -205,11 +205,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -219,7 +219,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) + if ((hadc->Instance == ADC1) && tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -246,7 +246,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) * * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; uint32_t tmp1 = 0U, tmp2 = 0U; @@ -259,7 +259,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -267,14 +267,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ @@ -311,11 +311,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -325,7 +325,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) + if ((hadc->Instance == ADC1) && tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -357,7 +357,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; @@ -373,15 +373,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, @@ -411,7 +411,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart = 0U; @@ -419,17 +419,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u tickstart = HAL_GetTick(); /* Check End of conversion flag */ - while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + while (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + if (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) { - hadc->State= HAL_ADC_STATE_TIMEOUT; + hadc->State = HAL_ADC_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; @@ -450,12 +450,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && - (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE)))) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); @@ -482,7 +482,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u * @param hadc ADC handle * @retval None */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; @@ -498,15 +498,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); @@ -544,7 +544,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected * @retval None */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { __IO uint32_t tmp = 0U; @@ -556,7 +556,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Return the selected ADC converted value */ - switch(InjectedRank) + switch (InjectedRank) { case ADC_INJECTED_RANK_4: { @@ -579,7 +579,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa } break; default: - break; + break; } return tmp; } @@ -595,7 +595,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; @@ -610,7 +610,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); @@ -618,14 +618,14 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -697,7 +697,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -722,7 +722,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; @@ -743,7 +743,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Disable the selected ADC DMA mode for multimode */ tmpADC_Common->CCR &= ~ADC_CCR_DDS; @@ -775,7 +775,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval The converted data value. */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) { ADC_Common_TypeDef *tmpADC_Common; @@ -794,7 +794,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -811,7 +811,7 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) * @param sConfigInjected ADC configuration structure for injected channel. * @retval None */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) { #ifdef USE_FULL_ASSERT @@ -835,7 +835,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); #endif /* USE_FULL_ASSERT */ - if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); } @@ -868,17 +868,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Rank configuration */ /* Clear the old SQx bits for the selected rank */ - hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion); /* Set the SQx bits for the selected rank */ - hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion); /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ - if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { /* Select external trigger to start conversion */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); @@ -917,7 +917,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); } - switch(sConfigInjected->InjectedRank) + switch (sConfigInjected->InjectedRank) { case 1U: /* Set injected channel 1 offset */ @@ -944,7 +944,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ /* control register) */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); + tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* if ADC1 Channel_18 is selected enable VBAT Channel */ if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) @@ -975,7 +975,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I * the configuration information for multimode. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { ADC_Common_TypeDef *tmpADC_Common; @@ -1025,7 +1025,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) @@ -1039,10 +1039,10 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ @@ -1077,9 +1077,9 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) */ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ + HAL_ADC_ConvHalfCpltCallback(hadc); } /** @@ -1090,11 +1090,11 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) */ static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR_DMA; - /* Set ADC error code to DMA error */ - hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - HAL_ADC_ErrorCallback(hadc); + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hadc->State = HAL_ADC_STATE_ERROR_DMA; + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + HAL_ADC_ErrorCallback(hadc); } /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c index 4abdc60a9a..f99111633b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c @@ -33,7 +33,7 @@ (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() (++) Configure CAN pins (+++) Enable the clock for the CAN GPIOs - (+++) Configure CAN pins as alternate function open-drain + (+++) Configure CAN pins as alternate function (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) (+++) Configure the CAN interrupt priority using HAL_NVIC_SetPriority() @@ -226,8 +226,8 @@ #ifdef HAL_CAN_MODULE_ENABLED #ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" -#endif +#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -235,6 +235,7 @@ * @{ */ #define CAN_TIMEOUT_VALUE 10U +#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U /** * @} */ @@ -248,8 +249,8 @@ */ /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); @@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) #else /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Reset the CAN peripheral */ SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); @@ -555,7 +556,8 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)) +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)) { HAL_StatusTypeDef status = HAL_OK; @@ -813,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca */ /** @defgroup CAN_Exported_Functions_Group2 Configuration functions - * @brief Configuration functions. - * + * @brief Configuration functions. + * @verbatim ============================================================================== ##### Configuration functions ##### @@ -835,7 +837,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca * contains the filter configuration information. * @retval None */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; @@ -886,7 +888,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); -#endif +#endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); @@ -905,7 +907,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); -#endif +#endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); @@ -997,8 +999,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe */ /** @defgroup CAN_Exported_Functions_Group3 Control functions - * @brief Control functions - * + * @brief Control functions + * @verbatim ============================================================================== ##### Control functions ##### @@ -1170,7 +1172,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) { __IO uint32_t count = 0; - uint32_t timeout = 1000000U; HAL_CAN_StateTypeDef state = hcan->State; if ((state == HAL_CAN_STATE_READY) || @@ -1186,15 +1187,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) count++; /* Check if timeout is reached */ - if (count > timeout) + if (count > CAN_WAKEUP_TIMEOUT_COUNTER) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; return HAL_ERROR; } - } - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); /* Return function status */ return HAL_OK; @@ -1216,7 +1216,7 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) * - 0 : Sleep mode is not active. * - 1 : Sleep mode is active. */ -uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan) { uint32_t status = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1247,7 +1247,8 @@ uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox) { uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; @@ -1278,15 +1279,6 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType /* Select an empty transmit mailbox */ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; - /* Check transmit mailbox value */ - if (transmitmailbox > 2U) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; - - return HAL_ERROR; - } - /* Store the Tx mailbox */ *pTxMailbox = (uint32_t)1 << transmitmailbox; @@ -1404,7 +1396,7 @@ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMai * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { uint32_t freelevel = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1447,7 +1439,7 @@ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) * - 1 : Pending transmission request on at least one of the selected * Tx Mailbox. */ -uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) { uint32_t status = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1479,7 +1471,7 @@ uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxe * This parameter can be one value of @arg CAN_Tx_Mailboxes. * @retval Timestamp of message sent from Tx Mailbox. */ -uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox) { uint32_t timestamp = 0U; uint32_t transmitmailbox; @@ -1513,7 +1505,8 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { HAL_CAN_StateTypeDef state = hcan->State; @@ -1554,10 +1547,19 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, } else { - pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); - pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) + { + /* Truncate DLC to 8 if received field is over range */ + pHeader->DLC = 8U; + } + else + { + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + } pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; @@ -1603,7 +1605,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, * This parameter can be a value of @arg CAN_receive_FIFO_number. * @retval Number of messages available in Rx FIFO. */ -uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo) { uint32_t filllevel = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1633,8 +1635,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) */ /** @defgroup CAN_Exported_Functions_Group4 Interrupts management - * @brief Interrupts management - * + * @brief Interrupts management + * @verbatim ============================================================================== ##### Interrupts management ##### @@ -2099,8 +2101,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) */ /** @defgroup CAN_Exported_Functions_Group5 Callback functions - * @brief CAN Callback functions - * + * @brief CAN Callback functions + * @verbatim ============================================================================== ##### Callback functions ##### @@ -2349,8 +2351,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) */ /** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * + * @brief CAN Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2371,7 +2373,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan) { HAL_CAN_StateTypeDef state = hcan->State; @@ -2406,7 +2408,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) * the configuration information for the specified CAN. * @retval CAN Error Code */ -uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan) { /* Return CAN error code */ return hcan->ErrorCode; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c index 56e6e8489f..6a39d16ac6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c @@ -233,7 +233,8 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) /* Write to CEC Control Register */ hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \ - hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \ + hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \ + hcec->Init.BroadcastMsgNoErrorBitGen | \ hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \ hcec->Init.ListenMode; @@ -412,10 +413,10 @@ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) * @param hcec CEC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID - * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID + * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID + * @arg HAL_CEC_ERROR_CB_ID Error callback ID + * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ @@ -501,10 +502,10 @@ HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_Call * @param hcec uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID - * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID + * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID + * @arg HAL_CEC_ERROR_CB_ID Error callback ID + * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID * @retval status */ HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID) @@ -694,7 +695,7 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec) * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, - uint8_t *pData, uint32_t Size) + const uint8_t *pData, uint32_t Size) { /* if the peripheral isn't already busy and if there is no previous transmission already pending due to arbitration lost */ @@ -749,7 +750,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator * @param hcec CEC handle * @retval Frame size */ -uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) +uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec) { return hcec->RxXferSize; } @@ -775,13 +776,13 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) { /* save interrupts register for further error or interrupts handling purposes */ - uint32_t reg; - reg = hcec->Instance->ISR; + uint32_t itflag; + itflag = hcec->Instance->ISR; /* ----------------------------Arbitration Lost Management----------------------------------*/ /* CEC TX arbitration error interrupt occurred --------------------------------------*/ - if ((reg & CEC_FLAG_ARBLST) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST)) { hcec->ErrorCode = HAL_CEC_ERROR_ARBLST; __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); @@ -789,7 +790,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* ----------------------------Rx Management----------------------------------*/ /* CEC RX byte received interrupt ---------------------------------------------------*/ - if ((reg & CEC_FLAG_RXBR) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR)) { /* reception is starting */ hcec->RxState = HAL_CEC_STATE_BUSY_RX; @@ -801,7 +802,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) } /* CEC RX end received interrupt ---------------------------------------------------*/ - if ((reg & CEC_FLAG_RXEND) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND)) { /* clear IT */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); @@ -820,7 +821,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* ----------------------------Tx Management----------------------------------*/ /* CEC TX byte request interrupt ------------------------------------------------*/ - if ((reg & CEC_FLAG_TXBR) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR)) { --hcec->TxXferCount; if (hcec->TxXferCount == 0U) @@ -829,14 +830,14 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) __HAL_CEC_LAST_BYTE_TX_SET(hcec); } /* In all cases transmit the byte */ - hcec->Instance->TXDR = *hcec->pTxBuffPtr; + hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr; hcec->pTxBuffPtr++; /* clear Tx-Byte request flag */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); } /* CEC TX end interrupt ------------------------------------------------*/ - if ((reg & CEC_FLAG_TXEND) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND); @@ -854,21 +855,21 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) } /* ----------------------------Rx/Tx Error Management----------------------------------*/ - if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR | - CEC_ISR_TXACKE)) != 0U) + if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | + CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U) { - hcec->ErrorCode = reg; + hcec->ErrorCode = itflag; __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE | HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE); - if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) + if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) { hcec->Init.RxBuffer -= hcec->RxXferSize; hcec->RxXferSize = 0U; hcec->RxState = HAL_CEC_STATE_READY; } - else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) + else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) { /* Set the CEC state ready to be able to start again the process */ hcec->gState = HAL_CEC_STATE_READY; @@ -957,9 +958,10 @@ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) * the configuration information for the specified CEC module. * @retval HAL state */ -HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) +HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec) { - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = hcec->gState; temp2 = hcec->RxState; @@ -972,7 +974,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) * the configuration information for the specified CEC. * @retval CEC Error Code */ -uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) +uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec) { return hcec->ErrorCode; } @@ -993,4 +995,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) /** * @} */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c index 54d44b49ec..3de962f8f8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @@ -335,6 +335,16 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) } #endif /* __MPU_PRESENT */ +/** + * @brief Clear pending events. + * @retval None + */ +void HAL_CORTEX_ClearEvent(void) +{ + __SEV(); + __WFE(); +} + /** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c index 2e86b2b6a2..9bd354ab10 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c @@ -147,7 +147,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + __HAL_CRC_SET_IDR(hcrc, 0); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); @@ -303,7 +303,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t * @param hcrc CRC handle * @retval HAL state */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) { /* Return CRC handle state */ return hcrc->State; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c index 65ad59dfcd..bb41673b2d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c @@ -1011,7 +1011,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; - /* Statrt DES/TDES encryption process */ + /* Start DES/TDES encryption process */ status = CRYP_TDES_Process(hcryp, Timeout); break; @@ -2533,15 +2533,17 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); #else /* CRYP */ @@ -2780,7 +2782,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2822,7 +2825,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); /* Turn back to ALGOMODE of the configuration */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); @@ -2867,15 +2871,17 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); #else /* CRYP */ @@ -2961,7 +2967,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3005,7 +3012,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); /* Turn back to ALGOMODE of the configuration */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); @@ -3943,7 +3951,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ @@ -3980,7 +3989,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4218,7 +4228,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ @@ -4255,7 +4266,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4855,7 +4867,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); /* Select header phase */ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); @@ -5016,7 +5029,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ @@ -5062,7 +5076,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5107,7 +5122,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } @@ -5144,7 +5160,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } @@ -5178,7 +5195,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } @@ -5247,7 +5265,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5320,7 +5339,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) } /** - * @brief Sets the payload phase in iterrupt mode + * @brief Sets the payload phase in interrupt mode * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval state @@ -5545,16 +5564,16 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) - { - /* Call Input transfer complete callback */ + { + /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } + } } else /* Last block of payload < 128bit*/ { @@ -5966,7 +5985,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } } else @@ -6001,7 +6021,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Last block optionally pad the data with zeros*/ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) @@ -6051,7 +6072,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Wait until the complete message has been processed */ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; @@ -6071,7 +6093,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); #else /* AES */ @@ -6119,7 +6142,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -6158,13 +6182,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes /4U) % 4U)); loopcounter++) + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; @@ -6211,7 +6236,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -6329,10 +6355,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) loopcounter++; hcryp->CrypHeaderCount++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } @@ -6463,10 +6489,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) loopcounter++; hcryp->CrypHeaderCount++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c index f6883eea39..8953638e5d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c @@ -168,7 +168,7 @@ and a pointer to the user callback function. Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. @@ -183,9 +183,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DAC_Init + reset to the legacy weak (overridden) functions in the HAL_DAC_Init and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -200,7 +200,7 @@ When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** DAC HAL driver macros list *** ============================================= @@ -270,7 +270,7 @@ */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { - /* Check DAC handle */ + /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; @@ -331,7 +331,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) { - /* Check DAC handle */ + /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; @@ -434,6 +434,12 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -489,6 +495,12 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -519,11 +531,17 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment) { - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpreg = 0U; + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tmpreg; + + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -560,12 +578,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; - default: - break; } } #if defined(DAC_CHANNEL2_SUPPORT) @@ -594,17 +610,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Get DHR12L2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L2; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R2; break; - default: - break; } } #endif /* DAC_CHANNEL2_SUPPORT */ - - /* Enable the DMA Stream */ if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ @@ -653,6 +665,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -701,10 +719,13 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + uint32_t itsource = hdac->Instance->CR; + uint32_t itflag = hdac->Instance->SR; + + if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) { /* Check underrun flag of DAC channel 1 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; @@ -716,7 +737,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); /* Disable the selected DAC channel1 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -728,10 +749,10 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) } #if defined(DAC_CHANNEL2_SUPPORT) - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) + if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) { /* Check underrun flag of DAC channel 2 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; @@ -743,7 +764,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); /* Disable the selected DAC channel2 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -776,6 +797,12 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui { __IO uint32_t tmp = 0UL; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); @@ -893,10 +920,13 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval The selected DAC channel data output value. */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) { uint32_t result = 0; + /* Check the DAC peripheral handle */ + assert_param(hdac != NULL); + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -925,11 +955,19 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpreg1; uint32_t tmpreg2; + /* Check the DAC peripheral handle and channel configuration struct */ + if ((hdac == NULL) || (sConfig == NULL)) + { + return HAL_ERROR; + } + /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); @@ -944,7 +982,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL)); + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) + << (Channel & 0x10UL)); /* Configure for the selected DAC channel: buffer output, trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set BOFFx bit according to DAC_OutputBuffer value */ @@ -963,7 +1002,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf __HAL_UNLOCK(hdac); /* Return function status */ - return HAL_OK; + return status; } /** @@ -992,7 +1031,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * the configuration information for the specified DAC. * @retval HAL state */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac) { /* Return DAC handle state */ return hdac->State; @@ -1005,7 +1044,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) * the configuration information for the specified DAC. * @retval DAC Error Code */ -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac) { return hdac->ErrorCode; } @@ -1028,7 +1067,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief Register a User DAC Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback + * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -1052,6 +1093,12 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call { HAL_StatusTypeDef status = HAL_OK; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + if (pCallback == NULL) { /* Update the error code */ @@ -1059,9 +1106,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hdac); - if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) @@ -1132,14 +1176,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } /** * @brief Unregister a User DAC Callback - * DAC Callback is redirected to the weak (surcharged) predefined callback + * DAC Callback is redirected to the weak (overridden) predefined callback + * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1160,8 +1204,11 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hdac); + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } if (hdac->State == HAL_DAC_STATE_READY) { @@ -1247,8 +1294,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ @@ -1334,8 +1379,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) #endif /* DAC */ #endif /* HAL_DAC_MODULE_ENABLED */ - /** * @} */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c index 343dd98682..6e5ab5121d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c @@ -23,15 +23,6 @@ ##### How to use this driver ##### ============================================================================== [..] - - *** Dual mode IO operation *** - ============================== - [..] - (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : - Use HAL_DACEx_DualGetValue() to get digital data to be converted and use - HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in - Channel 1 and Channel 2. - *** Signal generation operation *** =================================== [..] @@ -61,6 +52,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -100,6 +92,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) { uint32_t tmp_swtrig = 0UL; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Process locked */ __HAL_LOCK(hdac); @@ -141,6 +139,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); @@ -180,6 +184,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); @@ -230,6 +240,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 */ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); @@ -275,6 +291,12 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Align uint32_t data; uint32_t tmp; + /* Check the DAC peripheral handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data1)); @@ -391,7 +413,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) +uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac) { uint32_t tmp = 0UL; @@ -492,4 +514,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) /** * @} */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c index 5279edf0a8..63126be305 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c @@ -324,7 +324,7 @@ DFSDM_Channel_HandleTypeDef* a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NUL * @{ */ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels); -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance); +static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance); static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); @@ -960,7 +960,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; @@ -1329,7 +1329,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; @@ -1596,7 +1596,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd * @param hdfsdm_channel DFSDM channel handle. * @retval Channel analog watchdog value. */ -int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { return (int16_t) hdfsdm_channel->Instance->CHWDATAR; } @@ -1655,7 +1655,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf * @param hdfsdm_channel DFSDM channel handle. * @retval DFSDM channel state. */ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { /* Return DFSDM channel handle state */ return hdfsdm_channel->State; @@ -2637,7 +2637,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd * @param Channel Corresponding channel of regular conversion. * @retval Regular conversion value */ -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; @@ -3051,7 +3051,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h * @param Channel Corresponding channel of injected conversion. * @retval Injected conversion value */ -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; @@ -3079,7 +3079,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef *awdParam) + const DFSDM_Filter_AwdParamTypeDef *awdParam) { HAL_StatusTypeDef status = HAL_OK; @@ -3236,7 +3236,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil * @retval Extreme detector maximum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; @@ -3264,7 +3264,7 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter * @retval Extreme detector minimum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; @@ -3291,7 +3291,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter * @retval Conversion time value * @note To get time in second, this value has to be divided by DFSDM clock frequency. */ -uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { uint32_t reg = 0U; uint32_t value = 0U; @@ -3676,7 +3676,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter state. */ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Return DFSDM filter handle state */ return hdfsdm_filter->State; @@ -3687,7 +3687,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter error code. */ -uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { return hdfsdm_filter->ErrorCode; } @@ -4183,7 +4183,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) * @param Instance DFSDM channel instance. * @retval Channel number. */ -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) +static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance) { uint32_t channel; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c index 4cfac40613..76f2b4673e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c @@ -118,7 +118,7 @@ and a pointer to the user callback function. (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -130,16 +130,16 @@ (+) MspDeInitCallback : DMA2D MspDeInit. (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak (overridden) functions: examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init + reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Exception as well for Transfer Completion and Transfer Error callbacks that are not defined - as weak (surcharged) functions. They must be defined by the user to be resorted to. + as weak (overridden) functions. They must be defined by the user to be resorted to. Callbacks can be registered/unregistered in READY state only. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered @@ -151,7 +151,7 @@ When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. [..] (@) You can refer to the DMA2D HAL driver header file for more useful macros @@ -422,7 +422,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) /** * @brief Register a User DMA2D Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hdma2d DMA2D handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -521,7 +521,7 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM /** * @brief Unregister a DMA2D Callback - * DMA2D Callback is redirected to the weak (surcharged) predefined callback + * DMA2D Callback is redirected to the weak (overridden) predefined callback * @param hdma2d DMA2D handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -562,11 +562,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_ break; case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */ break; case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */ break; default : @@ -582,11 +582,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_ switch (CallbackID) { case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */ break; case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */ break; default : diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c index bde68610e0..b193c24e69 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c @@ -1835,6 +1835,95 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify the initial status of the DSI Host */ + + /* Verify that the clock lane and the digital section of the D-PHY are enabled */ + if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that the D-PHY PLL and the reference bias are enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Verify that there are no ULPS exit or request on data lanes */ + if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no Transmission trigger */ + if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Verify that D-PHY PLL is locked */ + tickstart = HAL_GetTick(); + + while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + /* ULPS Request on Data Lanes */ hdsi->Instance->PUCR |= DSI_PUCR_URDL; @@ -1898,6 +1987,58 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify that all active lanes are in ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Exit ULPS on Data Lanes */ hdsi->Instance->PUCR |= DSI_PUCR_UEDL; @@ -1947,6 +2088,61 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /* De-assert the ULPM requests and the ULPM exit bits */ hdsi->Instance->PUCR = 0U; + /* Verify that D-PHY PLL is enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that D-PHY PLL is locked */ + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -1967,6 +2163,96 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify the initial status of the DSI Host */ + + /* Verify that the clock lane and the digital section of the D-PHY are enabled */ + if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that the D-PHY PLL and the reference bias are enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Verify that there are no ULPS exit or request on both data and clock lanes */ + if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no Transmission trigger */ + if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Verify that D-PHY PLL is locked */ + tickstart = HAL_GetTick(); + + while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ + DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + /* Clock lane configuration: no more HS request */ hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; @@ -1979,7 +2265,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /* Get tick */ tickstart = HAL_GetTick(); - /* Wait until all active lanes exit ULPM */ + /* Wait until all active lanes enter ULPM */ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U) @@ -2039,9 +2325,44 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify that all active lanes are in ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | \ + DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_UAN1 | \ + DSI_PSR_PSS1 | DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + /* Turn on the DSI PLL */ __HAL_DSI_PLL_ENABLE(hdsi); + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + /* Get tick */ tickstart = HAL_GetTick(); @@ -2114,6 +2435,62 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /* Restore clock lane configuration to HS */ hdsi->Instance->CLCR |= DSI_CLCR_DPCC; + /* Verify that D-PHY PLL is enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ + DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that D-PHY PLL is locked */ + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Process unlocked */ __HAL_UNLOCK(hdsi); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c index 634da3fd8d..ff0cfec156 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c @@ -501,7 +501,6 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call { /* Update the error code */ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - return HAL_ERROR; } @@ -579,7 +578,7 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call /** * @brief Unregister an ETH Callback - * ETH callabck is redirected to the weak predefined callback + * ETH callback is redirected to the weak predefined callback * @param heth eth handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -702,7 +701,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) { heth->gState = HAL_ETH_STATE_BUSY; - /* Set nombre of descriptors to build */ + /* Set number of descriptors to build */ heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; /* Build all descriptors */ @@ -772,7 +771,7 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \ ETH_MMCTIMR_TGFSCM); - /* Set nombre of descriptors to build */ + /* Set number of descriptors to build */ heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; /* Build all descriptors */ @@ -836,6 +835,7 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) { /* Set the ETH peripheral state to BUSY */ heth->gState = HAL_ETH_STATE_BUSY; + /* Disable the DMA transmission */ CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); @@ -903,6 +903,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) /* Disable the MAC reception */ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; @@ -1085,7 +1086,6 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) uint32_t bufflength; uint8_t rxdataready = 0U; - if (pAppBuff == NULL) { heth->ErrorCode |= HAL_ETH_ERROR_PARAM; @@ -1108,9 +1108,9 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET) { /* Get timestamp high */ - heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC6; + heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC7; /* Get timestamp low */ - heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC7; + heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC6; } if ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) { @@ -1193,6 +1193,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) */ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) { + uint32_t tailidx; uint32_t descidx; uint32_t desccount; ETH_DMADescTypeDef *dmarxdesc; @@ -1238,12 +1239,6 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) WRITE_REG(dmarxdesc->DESC1, ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH); } - /* Before transferring the ownership to DMA, make sure that the RX descriptors bits writing - is fully performed. - The __DMB() instruction is added to avoid any potential compiler optimization that - may lead to abnormal behavior. */ - __DMB(); - SET_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN); /* Increment current rx descriptor index */ @@ -1256,8 +1251,14 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (heth->RxDescList.RxBuildDescCnt != desccount) { + /* Set the tail pointer index */ + tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + + /* DMB instruction to avoid race condition */ + __DMB(); + /* Set the Tail pointer address */ - WRITE_REG(heth->Instance->DMARPDR, 0); + WRITE_REG(heth->Instance->DMARPDR, ((uint32_t)(heth->Init.RxDesc + (tailidx)))); heth->RxDescList.RxBuildDescIdx = descidx; heth->RxDescList.RxBuildDescCnt = desccount; @@ -1317,7 +1318,7 @@ __weak void HAL_ETH_RxAllocateCallback(uint8_t **buff) /** * @brief Rx Link callback. * @param pStart: pointer to packet start - * @param pStart: pointer to packet end + * @param pEnd: pointer to packet end * @param buff: pointer to received data * @param Length: received data length * @retval None @@ -1904,14 +1905,12 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) } } - /* ETH DMA Error */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_AIS)) { if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_AISE)) { heth->ErrorCode |= HAL_ETH_ERROR_DMA; - /* if fatal bus error occurred */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_FBES)) { @@ -2116,7 +2115,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA * @param RegValue: the value to write * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue) { uint32_t tmpreg1; @@ -2254,6 +2253,7 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp ETH_DMAOMR_FUGF) >> 6) > 0U) ? ENABLE : DISABLE; dmaconf->ReceiveThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RTC); dmaconf->SecondFrameOperate = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_OSF) >> 2) > 0U) ? ENABLE : DISABLE; + return HAL_OK; } @@ -2369,7 +2369,7 @@ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) * the configuration of the ETH MAC filters. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig) { uint32_t filterconfig; uint32_t tmpreg1; @@ -2447,7 +2447,8 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil * @param pMACAddr: Pointer to MAC address buffer data (6 bytes) * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr) +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, + const uint8_t *pMACAddr) { uint32_t macaddrlr; uint32_t macaddrhr; @@ -2546,7 +2547,7 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBit * that contains the Power Down configuration * @retval None. */ -void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig) +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig) { uint32_t powerdownconfig; @@ -2650,7 +2651,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi * the configuration information for ETHERNET module * @retval HAL state */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) +HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth) { return heth->gState; } @@ -2661,7 +2662,7 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) * the configuration information for ETHERNET module * @retval ETH Error Code */ -uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth) +uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth) { return heth->ErrorCode; } @@ -2672,7 +2673,7 @@ uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth) * the configuration information for ETHERNET module * @retval ETH DMA Error Code */ -uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth) +uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth) { return heth->DMAErrorCode; } @@ -2683,7 +2684,7 @@ uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth) * the configuration information for ETHERNET module * @retval ETH MAC Error Code */ -uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth) +uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth) { return heth->MACErrorCode; } @@ -2694,7 +2695,7 @@ uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth) * the configuration information for ETHERNET module * @retval ETH MAC WakeUp event source */ -uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth) +uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth) { return heth->MACWakeUpEvent; } @@ -2941,10 +2942,10 @@ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) { dmatxdesc = heth->Init.TxDesc + i; - WRITE_REG(dmatxdesc->DESC0, 0x0); - WRITE_REG(dmatxdesc->DESC1, 0x0); - WRITE_REG(dmatxdesc->DESC2, 0x0); - WRITE_REG(dmatxdesc->DESC3, 0x0); + WRITE_REG(dmatxdesc->DESC0, 0x0U); + WRITE_REG(dmatxdesc->DESC1, 0x0U); + WRITE_REG(dmatxdesc->DESC2, 0x0U); + WRITE_REG(dmatxdesc->DESC3, 0x0U); WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); @@ -2986,12 +2987,12 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) { dmarxdesc = heth->Init.RxDesc + i; - WRITE_REG(dmarxdesc->DESC0, 0x0); - WRITE_REG(dmarxdesc->DESC1, 0x0); - WRITE_REG(dmarxdesc->DESC2, 0x0); - WRITE_REG(dmarxdesc->DESC3, 0x0); - WRITE_REG(dmarxdesc->BackupAddr0, 0x0); - WRITE_REG(dmarxdesc->BackupAddr1, 0x0); + WRITE_REG(dmarxdesc->DESC0, 0x0U); + WRITE_REG(dmarxdesc->DESC1, 0x0U); + WRITE_REG(dmarxdesc->DESC2, 0x0U); + WRITE_REG(dmarxdesc->DESC3, 0x0U); + WRITE_REG(dmarxdesc->BackupAddr0, 0x0U); + WRITE_REG(dmarxdesc->BackupAddr1, 0x0U); /* Set Own bit of the Rx descriptor Status */ dmarxdesc->DESC0 = ETH_DMARXDESC_OWN; @@ -3015,11 +3016,11 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) } } - WRITE_REG(heth->RxDescList.RxDescIdx, 0); - WRITE_REG(heth->RxDescList.RxDescCnt, 0); - WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0); - WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0); - WRITE_REG(heth->RxDescList.ItMode, 0); + WRITE_REG(heth->RxDescList.RxDescIdx, 0U); + WRITE_REG(heth->RxDescList.RxDescCnt, 0U); + WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U); + WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U); + WRITE_REG(heth->RxDescList.ItMode, 0U); /* Set Receive Descriptor List Address */ WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc); @@ -3170,7 +3171,6 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; dmatxdesclist->CurTxDesc = descidx; - /* disable the interrupt */ __disable_irq(); @@ -3217,4 +3217,3 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) /** * @} */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c index 04b5215fdd..89166e2650 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c @@ -64,7 +64,7 @@ (++) Provide exiting handle as parameter. (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. - (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). (++) Provide exiting handle as parameter. (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). @@ -75,7 +75,7 @@ (#) Get interrupt pending bit using HAL_EXTI_GetPending(). - (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @@ -300,8 +300,8 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT { assert_param(IS_EXTI_GPIO_PIN(linepos)); - regval = (SYSCFG->EXTICR[linepos >> 2u] << 16u ); - pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 28u); + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; } } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c index d079dd07e7..a84b29d35e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c @@ -357,28 +357,28 @@ /* Private define for @ref PreviousState usage */ #define FMPI2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_FMPI2C_STATE_BUSY_TX | \ - (uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & \ - (uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY)))) + (uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ #define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) /*!< Default Value */ #define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_MASTER)) + (uint32_t)HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_MASTER)) + (uint32_t)HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_SLAVE)) + (uint32_t)HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_SLAVE)) + (uint32_t)HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_MEM)) + (uint32_t)HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ - (uint32_t)HAL_FMPI2C_MODE_MEM)) + (uint32_t)HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ @@ -401,7 +401,16 @@ * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup FMPI2C_Private_Macro + * @{ + */ +/* Macro to get remaining data to transfer on DMA side */ +#define FMPI2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -416,6 +425,7 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma); static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma); + /* Private functions to handle IT transfer */ static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); static void FMPI2C_ITMasterSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c); @@ -427,33 +437,37 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart); + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart); + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); /* Private functions for FMPI2C transfer IRQ handler */ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Mem_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources); + uint32_t ITSources); static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Mem_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources); + uint32_t ITSources); /* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t Tickstart); + uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); @@ -467,7 +481,7 @@ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c); /* Private function to handle start, restart or stop a transfer */ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); + uint32_t Request); /* Private function to Convert Specific options */ static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c); @@ -595,7 +609,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) /* Configure FMPI2Cx: Addressing Master mode */ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT) { - hfmpi2c->Instance->CR2 = (FMPI2C_CR2_ADD10); + SET_BIT(hfmpi2c->Instance->CR2, FMPI2C_CR2_ADD10); + } + else + { + /* Clear the FMPI2C ADD10 bit */ + CLEAR_BIT(hfmpi2c->Instance->CR2, FMPI2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hfmpi2c->Instance->CR2 |= (FMPI2C_CR2_AUTOEND | FMPI2C_CR2_NACK); @@ -606,7 +625,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) /* Configure FMPI2Cx: Dual mode and Own Address2 */ hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | \ - (hfmpi2c->Init.OwnAddress2Masks << 8)); + (hfmpi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/ /* Configure FMPI2Cx: Generalcall and NoStretch mode */ @@ -705,6 +724,8 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c) /** * @brief Register a User FMPI2C Callback * To be used instead of the weak predefined callback + * @note The HAL_FMPI2C_RegisterCallback() may be called before HAL_FMPI2C_Init() in HAL_FMPI2C_STATE_RESET + * to register callbacks for HAL_FMPI2C_MSPINIT_CB_ID and HAL_FMPI2C_MSPDEINIT_CB_ID. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param CallbackID ID of the callback to be registered @@ -724,7 +745,7 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c) * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, - pFMPI2C_CallbackTypeDef pCallback) + pFMPI2C_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -735,8 +756,6 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hfmpi2c); if (HAL_FMPI2C_STATE_READY == hfmpi2c->State) { @@ -825,14 +844,14 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpi2c); return status; } /** * @brief Unregister an FMPI2C Callback * FMPI2C callback is redirected to the weak predefined callback + * @note The HAL_FMPI2C_UnRegisterCallback() may be called before HAL_FMPI2C_Init() in HAL_FMPI2C_STATE_RESET + * to un-register callbacks for HAL_FMPI2C_MSPINIT_CB_ID and HAL_FMPI2C_MSPDEINIT_CB_ID. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param CallbackID ID of the callback to be unregistered @@ -855,9 +874,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, H { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hfmpi2c); - if (HAL_FMPI2C_STATE_READY == hfmpi2c->State) { switch (CallbackID) @@ -945,8 +961,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, H status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpi2c); return status; } @@ -969,8 +983,6 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hfmpi2c); if (HAL_FMPI2C_STATE_READY == hfmpi2c->State) { @@ -985,8 +997,6 @@ HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpi2c); return status; } @@ -1001,9 +1011,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hfmpi2c); - if (HAL_FMPI2C_STATE_READY == hfmpi2c->State) { hfmpi2c->AddrCallback = HAL_FMPI2C_AddrCallback; /* Legacy weak AddrCallback */ @@ -1017,8 +1024,6 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpi2c); return status; } @@ -1113,9 +1118,10 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout) + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t xfermode; if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { @@ -1139,19 +1145,40 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint hfmpi2c->XferCount = Size; hfmpi2c->XferISR = NULL; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_GENERATE_START_WRITE); + xfermode = FMPI2C_RELOAD_MODE; } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_WRITE); + xfermode = FMPI2C_AUTOEND_MODE; + } + + if (hfmpi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), xfermode, + FMPI2C_GENERATE_START_WRITE); + } + else + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, + FMPI2C_GENERATE_START_WRITE); } while (hfmpi2c->XferCount > 0U) @@ -1182,13 +1209,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } } @@ -1232,7 +1259,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout) + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1262,15 +1289,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + hfmpi2c->XferSize = 1U; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } while (hfmpi2c->XferCount > 0U) @@ -1302,13 +1329,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } } @@ -1350,9 +1377,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { @@ -1387,6 +1416,19 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 return HAL_ERROR; } + /* Preload TX data if no stretch enable */ + if (hfmpi2c->Init.NoStretchMode == FMPI2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferCount--; + } + /* Clear ADDR flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); @@ -1432,26 +1474,48 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 hfmpi2c->XferCount--; } - /* Wait until STOP flag is set */ - if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + /* Wait until AF flag is set */ + error = FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; + /* Check that FMPI2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ - if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + tmpXferCount = hfmpi2c->XferCount; + if ((hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) && (tmpXferCount == 0U)) { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ + /* Reset ErrorCode to NONE */ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; } else { + /* Disable Address Acknowledge */ + hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; return HAL_ERROR; } } + else + { + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); - /* Clear STOP flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + /* Clear AF flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Wait until STOP flag is set */ + if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + } /* Wait until BUSY flag is reset */ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) @@ -1488,7 +1552,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; @@ -1512,6 +1576,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ /* Prepare transfer parameters */ hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; + hfmpi2c->XferSize = hfmpi2c->XferCount; hfmpi2c->XferISR = NULL; /* Enable Address Acknowledge */ @@ -1554,6 +1619,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ hfmpi2c->pBuffPtr++; hfmpi2c->XferCount--; + hfmpi2c->XferSize--; } return HAL_ERROR; @@ -1566,6 +1632,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ hfmpi2c->pBuffPtr++; hfmpi2c->XferCount--; + hfmpi2c->XferSize--; } /* Wait until STOP flag is set */ @@ -1615,7 +1682,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) + uint16_t Size) { uint32_t xfermode; @@ -1652,7 +1719,26 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u /* Send Slave Address */ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE); + if (hfmpi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), xfermode, + FMPI2C_GENERATE_START_WRITE); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, + FMPI2C_GENERATE_START_WRITE); + } /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -1686,7 +1772,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) + uint16_t Size) { uint32_t xfermode; @@ -1712,7 +1798,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + hfmpi2c->XferSize = 1U; xfermode = FMPI2C_RELOAD_MODE; } else @@ -1775,6 +1861,20 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; + /* Preload TX data if no stretch enable */ + if (hfmpi2c->Init.NoStretchMode == FMPI2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -1857,10 +1957,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { @@ -1893,6 +1994,20 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, xfermode = FMPI2C_AUTOEND_MODE; } + if (hfmpi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + sizetoxfer = hfmpi2c->XferSize; + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + if (hfmpi2c->XferSize > 0U) { if (hfmpi2c->hdmatx != NULL) @@ -1908,8 +2023,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, - hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, + (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); } else { @@ -1930,7 +2045,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, { /* Send Slave Address */ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), + xfermode, FMPI2C_GENERATE_START_WRITE); /* Update XferCount value */ hfmpi2c->XferCount -= hfmpi2c->XferSize; @@ -1969,8 +2085,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2004,7 +2120,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -2031,7 +2147,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + hfmpi2c->XferSize = 1U; xfermode = FMPI2C_RELOAD_MODE; } else @@ -2117,7 +2233,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2125,11 +2241,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); } return HAL_OK; @@ -2173,67 +2289,99 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Slave_ISR_DMA; - if (hfmpi2c->hdmatx != NULL) + /* Preload TX data if no stretch enable */ + if (hfmpi2c->Init.NoStretchMode == FMPI2C_NOSTRETCH_ENABLE) { - /* Set the FMPI2C DMA transfer complete callback */ - hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError; + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; - /* Set the unused DMA callbacks to NULL */ - hfmpi2c->hdmatx->XferHalfCpltCallback = NULL; - hfmpi2c->hdmatx->XferAbortCallback = NULL; + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, - hfmpi2c->XferSize); + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; } - else + + if (hfmpi2c->XferCount != 0U) { - /* Update FMPI2C state */ - hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if (hfmpi2c->hdmatx != NULL) + { + /* Set the FMPI2C DMA transfer complete callback */ + hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt; - /* Update FMPI2C error code */ - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM; + /* Set the DMA error callback */ + hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Set the unused DMA callbacks to NULL */ + hfmpi2c->hdmatx->XferHalfCpltCallback = NULL; + hfmpi2c->hdmatx->XferAbortCallback = NULL; - return HAL_ERROR; - } + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, + (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize); + } + else + { + /* Update FMPI2C state */ + hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - if (dmaxferstatus == HAL_OK) - { - /* Enable Address Acknowledge */ - hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK; + /* Update FMPI2C error code */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - /* Note : The FMPI2C interrupts must be enabled after unlocking current process - to avoid the risk of FMPI2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + /* Note : The FMPI2C interrupts must be enabled after unlocking current process + to avoid the risk of FMPI2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + } + else + { + /* Update FMPI2C state */ + hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + + /* Update FMPI2C error code */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + return HAL_ERROR; + } } else { - /* Update FMPI2C state */ - hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - - /* Update FMPI2C error code */ - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA; + /* Enable Address Acknowledge */ + hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Note : The FMPI2C interrupts must be enabled after unlocking current process + to avoid the risk of FMPI2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); } return HAL_OK; @@ -2347,6 +2495,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui return HAL_BUSY; } } + /** * @brief Write an amount of data in blocking mode to a specific memory address * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains @@ -2361,7 +2510,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2445,13 +2594,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } @@ -2498,7 +2647,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2545,15 +2694,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + hfmpi2c->XferSize = 1U; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } do @@ -2583,15 +2732,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + hfmpi2c->XferSize = 1U; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t) hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } } while (hfmpi2c->XferCount > 0U); @@ -2635,11 +2784,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); @@ -2659,41 +2805,38 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; /* Prepare transfer parameters */ + hfmpi2c->XferSize = 0U; hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_IT; + hfmpi2c->Devaddress = DevAddress; - if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); + } /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; - } - - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2729,11 +2872,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); @@ -2753,9 +2893,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -2764,29 +2901,29 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_IT; + hfmpi2c->Devaddress = DevAddress; - if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); + /* Send Slave Address and Memory Address */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2795,11 +2932,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); return HAL_OK; } @@ -2808,6 +2945,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t return HAL_BUSY; } } + /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains @@ -2821,10 +2959,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2846,9 +2982,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -2857,28 +2990,36 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_DMA; + hfmpi2c->Devaddress = DevAddress; if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); + } if (hfmpi2c->hdmatx != NULL) { @@ -2913,12 +3054,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 if (dmaxferstatus == HAL_OK) { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP); - - /* Update XferCount value */ - hfmpi2c->XferCount -= hfmpi2c->XferSize; + /* Send Slave Address and Memory Address */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2926,11 +3063,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } else { @@ -2968,10 +3105,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2993,9 +3128,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -3004,25 +3136,35 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_DMA; + hfmpi2c->Devaddress = DevAddress; if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); } if (hfmpi2c->hdmarx != NULL) @@ -3058,11 +3200,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ if (dmaxferstatus == HAL_OK) { - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); - - /* Update XferCount value */ - hfmpi2c->XferCount -= hfmpi2c->XferSize; + /* Send Slave Address and Memory Address */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3070,11 +3209,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } else { @@ -3111,7 +3250,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; @@ -3203,22 +3342,6 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16 __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); } - /* Check if the maximum allowed number of trials has been reached */ - if (FMPI2C_Trials == Trials) - { - /* Generate Stop */ - hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); - } - /* Increment Trials */ FMPI2C_Trials++; } while (FMPI2C_Trials < Trials); @@ -3253,10 +3376,11 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3288,6 +3412,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 xfermode = hfmpi2c->XferOptions; } + if ((hfmpi2c->XferSize > 0U) && ((XferOptions == FMPI2C_FIRST_FRAME) || \ + (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + sizetoxfer = hfmpi2c->XferSize; + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3309,7 +3448,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 } /* Send Slave Address and set NBYTES to write */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)) + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3317,6 +3463,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); return HAL_OK; @@ -3340,11 +3490,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3376,6 +3527,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi xfermode = hfmpi2c->XferOptions; } + if ((hfmpi2c->XferSize > 0U) && ((XferOptions == FMPI2C_FIRST_FRAME) || \ + (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + sizetoxfer = hfmpi2c->XferSize; + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3411,8 +3577,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, - hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, + (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); } else { @@ -3432,7 +3598,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi if (dmaxferstatus == HAL_OK) { /* Send Slave Address and set NBYTES to write */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)) + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + } /* Update XferCount value */ hfmpi2c->XferCount -= hfmpi2c->XferSize; @@ -3471,8 +3644,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_WRITE); + if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)) + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3508,7 +3687,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = FMPI2C_GENERATE_START_READ; @@ -3595,7 +3774,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = FMPI2C_GENERATE_START_READ; @@ -3727,7 +3906,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3735,11 +3914,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); } return HAL_OK; @@ -3761,8 +3940,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3822,7 +4004,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c hfmpi2c->XferOptions = XferOptions; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -3857,8 +4040,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -3893,7 +4078,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; /* Set the FMPI2C DMA Abort callback : - will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort; /* Abort DMA RX */ @@ -3915,7 +4100,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 if (hfmpi2c->hdmatx != NULL) { /* Set the FMPI2C DMA Abort callback : - will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort; /* Abort DMA TX */ @@ -4000,7 +4185,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 return HAL_ERROR; } - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4010,15 +4196,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); + /* Enable DMA Request */ + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; - return HAL_OK; } else @@ -4038,8 +4224,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4099,7 +4288,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, hfmpi2c->XferOptions = XferOptions; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4134,8 +4324,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -4277,7 +4469,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c return HAL_ERROR; } - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4287,15 +4480,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); + /* Enable DMA Request */ + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; - return HAL_OK; } else @@ -4429,7 +4622,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint * the configuration information for the specified FMPI2C. * @retval None */ -void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) +void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) /* Derogation MISRAC2012-Rule-8.13 */ { /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hfmpi2c->Instance->ISR); @@ -4682,7 +4875,7 @@ __weak void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c) * the configuration information for the specified FMPI2C. * @retval HAL state */ -HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c) +HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(const FMPI2C_HandleTypeDef *hfmpi2c) { /* Return FMPI2C handle state */ return hfmpi2c->State; @@ -4694,7 +4887,7 @@ HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c) * the configuration information for FMPI2C module * @retval HAL mode */ -HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c) +HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(const FMPI2C_HandleTypeDef *hfmpi2c) { return hfmpi2c->Mode; } @@ -4705,7 +4898,7 @@ HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c) * the configuration information for the specified FMPI2C. * @retval FMPI2C Error Code */ -uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c) +uint32_t HAL_FMPI2C_GetError(const FMPI2C_HandleTypeDef *hfmpi2c) { return hfmpi2c->ErrorCode; } @@ -4731,7 +4924,7 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c) * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; @@ -4768,17 +4961,22 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm hfmpi2c->XferSize--; hfmpi2c->XferCount--; } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) == RESET) && \ + ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET))) { /* Write data to TXDR */ - hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + if (hfmpi2c->XferCount != 0U) + { + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; - /* Increment Buffer pointer */ - hfmpi2c->pBuffPtr++; + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; - hfmpi2c->XferSize--; - hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + hfmpi2c->XferCount--; + } } else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && \ (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) @@ -4789,7 +4987,15 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); } else @@ -4798,12 +5004,12 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) { FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, - hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); + hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); } else { FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, - FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); } } } @@ -4869,50 +5075,208 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm } /** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param ITFlags Interrupt flags to handle. * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Mem_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) { - uint32_t tmpoptions = hfmpi2c->XferOptions; + uint32_t direction = FMPI2C_GENERATE_START_WRITE; uint32_t tmpITFlags = ITFlags; - /* Process locked */ + /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Check if STOPF is set */ - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { - /* Call FMPI2C Slave complete process */ - FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags); + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~FMPI2C_FLAG_RXNE; - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + /* Read data from RXDR */ + *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferSize--; + hfmpi2c->XferCount--; + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) { - /* Check that FMPI2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hfmpi2c->XferCount == 0U) + if (hfmpi2c->Memaddress == 0xFFFFFFFFU) { - if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) - /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for - Warning[Pa134]: left and right operands are identical */ - { - /* Call FMPI2C Listen complete process */ - FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags); - } - else if ((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != FMPI2C_NO_OPTION_FRAME)) - { - /* Clear NACK Flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferSize--; + hfmpi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hfmpi2c->Instance->TXDR = hfmpi2c->Memaddress; + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U)) + { + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE); + } + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); + + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + direction = FMPI2C_GENERATE_START_READ; + } + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } + + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, direction); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + { + /* Call FMPI2C Master complete process */ + FMPI2C_ITMasterCplt(hfmpi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains + * the configuration information for the specified FMPI2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hfmpi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hfmpi2c); + + /* Check if STOPF is set */ + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + { + /* Call FMPI2C Slave complete process */ + FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags); + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + { + /* Check that FMPI2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hfmpi2c->XferCount == 0U) + { + if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call FMPI2C Listen complete process */ + FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags); + } + else if ((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != FMPI2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); @@ -5018,7 +5382,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; @@ -5057,7 +5421,15 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf /* Prepare the new XferSize to transfer */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } xfermode = FMPI2C_RELOAD_MODE; } else @@ -5149,6 +5521,170 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains + * the configuration information for the specified FMPI2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef FMPI2C_Mem_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = FMPI2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hfmpi2c); + + if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Set corresponding Error Code */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT); + + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hfmpi2c->Instance->TXDR = hfmpi2c->Memaddress; + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TCR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + + /* Enable only Error interrupt */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); + + if (hfmpi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hfmpi2c->XferCount -= hfmpi2c->XferSize; + + /* Enable DMA Request */ + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + } + else + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE); + } + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TC) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); + + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + direction = FMPI2C_GENERATE_START_READ; + } + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } + + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, direction); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hfmpi2c->XferCount -= hfmpi2c->XferSize; + + /* Enable DMA Request */ + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + } + else + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + } + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + { + /* Call FMPI2C Master complete process */ + FMPI2C_ITMasterCplt(hfmpi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + return HAL_OK; +} + /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains @@ -5158,7 +5694,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint32_t tmpoptions = hfmpi2c->XferOptions; uint32_t treatdmanack = 0U; @@ -5174,9 +5710,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm /* Call FMPI2C Slave complete process */ FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags); } - - if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Check that FMPI2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5190,7 +5725,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm { if (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_RXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U) { treatdmanack = 1U; } @@ -5202,7 +5737,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm { if (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_TXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx) == 0U) { treatdmanack = 1U; } @@ -5303,8 +5838,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart) + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); @@ -5358,8 +5893,8 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart) + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); @@ -5775,6 +6310,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hfmpi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hfmpi2c->XferOptions; HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State; /* Clear STOP Flag */ @@ -5791,6 +6327,11 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT); hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_RX; } + else if (tmpstate == HAL_FMPI2C_STATE_LISTEN) + { + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT); + hfmpi2c->PreviousState = FMPI2C_STATE_NONE; + } else { /* Do nothing */ @@ -5813,7 +6354,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) if (hfmpi2c->hdmatx != NULL) { - hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx); + hfmpi2c->XferCount = (uint16_t)FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx); } } else if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_RXDMAEN) != RESET) @@ -5823,7 +6364,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) if (hfmpi2c->hdmarx != NULL) { - hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx); + hfmpi2c->XferCount = (uint16_t)FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx); } } else @@ -5857,6 +6398,57 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; } + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_IT_NACKI) != RESET)) + { + /* Check that FMPI2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hfmpi2c->XferCount == 0U) + { + if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call FMPI2C Listen complete process */ + FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags); + } + else if ((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != FMPI2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); + + /* Last Byte is Transmitted */ + /* Call FMPI2C Slave Sequential complete process */ + FMPI2C_ITSlaveSeqCplt(hfmpi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + + if ((tmpoptions == FMPI2C_FIRST_FRAME) || (tmpoptions == FMPI2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode); + } + } + } + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; hfmpi2c->XferISR = NULL; @@ -5984,6 +6576,7 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) { HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ @@ -6011,20 +6604,38 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) /* Disable all interrupts */ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT); + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hfmpi2c->State != HAL_FMPI2C_STATE_ABORT) { /* Set HAL_FMPI2C_STATE_READY */ hfmpi2c->State = HAL_FMPI2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) + { + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) + { + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + } + } hfmpi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ tmppreviousstate = hfmpi2c->PreviousState; + if ((hfmpi2c->hdmatx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_TX) || \ - (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_TX))) + (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_TX))) { if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) { @@ -6054,7 +6665,7 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) } /* Abort DMA RX transfer if any */ else if ((hfmpi2c->hdmarx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_RX) || \ - (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_RX))) + (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_RX))) { if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN) { @@ -6197,6 +6808,7 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA FMPI2C slave transmit process complete callback. * @param hdma DMA handle @@ -6225,6 +6837,7 @@ static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA FMPI2C master receive process complete callback. * @param hdma DMA handle @@ -6253,7 +6866,15 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /* Set the XferSize to transfer */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + { + hfmpi2c->XferSize = 1U; + } + else + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + } } else { @@ -6275,6 +6896,7 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA FMPI2C slave receive process complete callback. * @param hdma DMA handle @@ -6286,7 +6908,7 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hfmpi2c->XferOptions; - if ((__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) && \ + if ((FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U) && \ (tmpoptions != FMPI2C_NO_OPTION_FRAME)) { /* Disable DMA Request */ @@ -6303,6 +6925,7 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA FMPI2C communication error callback. * @param hdma DMA handle @@ -6316,7 +6939,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) if (hfmpi2c->hdmatx != NULL) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx) == 0U) { treatdmaerror = 1U; } @@ -6324,7 +6947,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) if (hfmpi2c->hdmarx != NULL) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U) { treatdmaerror = 1U; } @@ -6341,6 +6964,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA FMPI2C communication abort callback * (To be called at end of DMA Abort procedure). @@ -6365,6 +6989,7 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) FMPI2C_TreatErrorCallback(hfmpi2c); } + /** * @brief This function handles FMPI2C Communication Timeout. It waits * until a flag is no longer in the specified status. @@ -6377,22 +7002,31 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t Tickstart) + uint32_t Timeout, uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status) { + /* Check if an error is detected */ + if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + return HAL_ERROR; + } } } } @@ -6408,7 +7042,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfm * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart) + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET) { @@ -6423,14 +7057,17 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -6446,7 +7083,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart) + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) { @@ -6459,14 +7096,17 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -6481,18 +7121,20 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart) + uint32_t Tickstart) { - while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -6500,40 +7142,51 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) { + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF; + /* Clear STOP Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); /* Clear Configuration Register 2 */ FMPI2C_RESET_CR2(hfmpi2c); - hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + status = HAL_ERROR; + } } } - return HAL_OK; + return status; } /** @@ -6549,15 +7202,14 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u HAL_StatusTypeDef status = HAL_OK; uint32_t itflag = hfmpi2c->Instance->ISR; uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_FMPI2C_ModeTypeDef tmp2; if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_AF)) { - /* In case of Soft End condition, generate the STOP condition */ - if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE) - { - /* Generate Stop */ - hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; - } + /* Clear NACKF Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ @@ -6566,11 +7218,35 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - error_code |= HAL_FMPI2C_ERROR_TIMEOUT; + tmp1 = (uint32_t)(hfmpi2c->Instance->CR2 & FMPI2C_CR2_STOP); + tmp2 = hfmpi2c->Mode; - status = HAL_ERROR; + /* In case of FMPI2C still busy, try to regenerate a STOP manually */ + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) != RESET) && \ + (tmp1 != FMPI2C_CR2_STOP) && \ + (tmp2 != HAL_FMPI2C_MODE_SLAVE)) + { + /* Generate Stop */ + hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > FMPI2C_TIMEOUT_STOPF) + { + error_code |= HAL_FMPI2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } } } } @@ -6582,9 +7258,6 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); } - /* Clear NACKF Flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); - error_code |= HAL_FMPI2C_ERROR_AF; status = HAL_ERROR; @@ -6666,7 +7339,7 @@ static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, u * @retval None */ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request) + uint32_t Request) { /* Check the parameters */ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance)); @@ -6675,14 +7348,14 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAdd /* Declaration of tmp to prevent undefined behavior of volatile usage */ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | \ - (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hfmpi2c->Instance->CR2, \ ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | \ (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | \ - FMPI2C_CR2_START | FMPI2C_CR2_STOP)), tmp); + FMPI2C_CR2_START | FMPI2C_CR2_STOP)), tmp); } /** @@ -6696,8 +7369,9 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR { uint32_t tmpisr = 0U; - if ((hfmpi2c->XferISR == FMPI2C_Master_ISR_DMA) || \ - (hfmpi2c->XferISR == FMPI2C_Slave_ISR_DMA)) + if ((hfmpi2c->XferISR != FMPI2C_Master_ISR_DMA) && \ + (hfmpi2c->XferISR != FMPI2C_Slave_ISR_DMA) && \ + (hfmpi2c->XferISR != FMPI2C_Mem_ISR_DMA)) { if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT) { @@ -6705,6 +7379,18 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } + if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI; + } + + if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI; + } + if (InterruptRequest == FMPI2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ @@ -6714,39 +7400,46 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR if (InterruptRequest == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= (FMPI2C_IT_STOPI | FMPI2C_IT_TCI); - } - - if (InterruptRequest == FMPI2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= FMPI2C_IT_TCI; + tmpisr |= FMPI2C_IT_STOPI; } } + else { if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT) { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ + /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI; } if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI; } + if (InterruptRequest == FMPI2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI; + } + if (InterruptRequest == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= FMPI2C_IT_STOPI; + tmpisr |= (FMPI2C_IT_STOPI | FMPI2C_IT_TCI); + } + + if (InterruptRequest == FMPI2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= FMPI2C_IT_TCI; } } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c index 700f25af05..4c913c6283 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c @@ -209,20 +209,28 @@ /** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions * @{ */ +/* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, - FlagStatus Status, uint32_t Timeout); + FlagStatus Status, uint32_t Timeout); -static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); -static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); +/* Private functions for FMPSMBUS transfer IRQ handler */ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); +static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); -static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/* Private functions to centralize the enable/disable of Interrupts */ +static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); +static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); -static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/* Private function to flush TXDR register */ +static void FMPSMBUS_Flush_TXDR(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/* Private function to handle start, restart or stop a transfer */ static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, - uint32_t Mode, uint32_t Request); + uint32_t Mode, uint32_t Request); + +/* Private function to Convert Specific options */ +static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus); /** * @} */ @@ -371,13 +379,13 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus) /*---------------------------- FMPSMBUSx OAR2 Configuration -----------------------*/ /* Configure FMPSMBUSx: Dual mode and Own Address2 */ hfmpsmbus->Instance->OAR2 = (hfmpsmbus->Init.DualAddressMode | hfmpsmbus->Init.OwnAddress2 | \ - (hfmpsmbus->Init.OwnAddress2Masks << 8U)); + (hfmpsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- FMPSMBUSx CR1 Configuration ------------------------*/ /* Configure FMPSMBUSx: Generalcall and NoStretch mode */ hfmpsmbus->Instance->CR1 = (hfmpsmbus->Init.GeneralCallMode | hfmpsmbus->Init.NoStretchMode | \ - hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | \ - hfmpsmbus->Init.AnalogFilter); + hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | \ + hfmpsmbus->Init.AnalogFilter); /* Enable Slave Byte Control only in case of Packet Error Check is enabled and FMPSMBUS Peripheral is set in Slave mode */ @@ -577,6 +585,9 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps /** * @brief Register a User FMPSMBUS Callback * To be used instead of the weak predefined callback + * @note The HAL_FMPSMBUS_RegisterCallback() may be called before HAL_FMPSMBUS_Init() in + * HAL_FMPSMBUS_STATE_RESET to register callbacks for HAL_FMPSMBUS_MSPINIT_CB_ID and + * HAL_FMPSMBUS_MSPDEINIT_CB_ID. * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains * the configuration information for the specified FMPSMBUS. * @param CallbackID ID of the callback to be registered @@ -593,8 +604,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, - pFMPSMBUS_CallbackTypeDef pCallback) + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, + pFMPSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -606,9 +617,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hfmpsmbus); - if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) { switch (CallbackID) @@ -684,14 +692,15 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpsmbus); return status; } /** * @brief Unregister an FMPSMBUS Callback * FMPSMBUS callback is redirected to the weak predefined callback + * @note The HAL_FMPSMBUS_UnRegisterCallback() may be called before HAL_FMPSMBUS_Init() in + * HAL_FMPSMBUS_STATE_RESET to un-register callbacks for HAL_FMPSMBUS_MSPINIT_CB_ID and + * HAL_FMPSMBUS_MSPDEINIT_CB_ID * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains * the configuration information for the specified FMPSMBUS. * @param CallbackID ID of the callback to be unregistered @@ -708,13 +717,10 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hfmpsmbus); - if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) { switch (CallbackID) @@ -790,8 +796,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsm status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpsmbus); return status; } @@ -804,7 +808,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsm * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - pFMPSMBUS_AddrCallbackTypeDef pCallback) + pFMPSMBUS_AddrCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -815,8 +819,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmp return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hfmpsmbus); if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) { @@ -831,8 +833,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmp status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpsmbus); return status; } @@ -847,9 +847,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hfmpsmbus); - if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) { hfmpsmbus->AddrCallback = HAL_FMPSMBUS_AddrCallback; /* Legacy weak AddrCallback */ @@ -863,8 +860,6 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hfmpsmbus); return status; } @@ -929,9 +924,10 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions) + uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; + uint32_t sizetoxfer; /* Check the parameters */ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -964,13 +960,37 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm hfmpsmbus->XferSize = Size; } + sizetoxfer = hfmpsmbus->XferSize; + if ((sizetoxfer > 0U) && ((XferOptions == FMPSMBUS_FIRST_FRAME) || + (XferOptions == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || + (XferOptions == FMPSMBUS_FIRST_FRAME_WITH_PEC) || + (XferOptions == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC))) + { + if (hfmpsmbus->pBuffPtr != NULL) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpsmbus->Instance->TXDR = *hfmpsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpsmbus->pBuffPtr++; + + hfmpsmbus->XferCount--; + hfmpsmbus->XferSize--; + } + else + { + return HAL_ERROR; + } + } + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) + if ((sizetoxfer < hfmpsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE)) { - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), - FMPSMBUS_GENERATE_START_WRITE); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer, + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_GENERATE_START_WRITE); } else { @@ -983,8 +1003,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) && \ (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -993,17 +1013,24 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus); /* Handle Transfer */ - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - hfmpsmbus->XferOptions, - FMPSMBUS_GENERATE_START_WRITE); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer, + hfmpsmbus->XferOptions, + FMPSMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) { - hfmpsmbus->XferSize--; - hfmpsmbus->XferCount--; + if (hfmpsmbus->XferSize > 0U) + { + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } } } @@ -1035,7 +1062,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) + uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -1076,8 +1103,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), - FMPSMBUS_GENERATE_START_READ); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_GENERATE_START_READ); } else { @@ -1091,7 +1118,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1101,8 +1128,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb /* Handle Transfer */ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - hfmpsmbus->XferOptions, - FMPSMBUS_GENERATE_START_READ); + hfmpsmbus->XferOptions, + FMPSMBUS_GENERATE_START_READ); } } @@ -1197,7 +1224,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1246,14 +1273,14 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) { FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -1295,7 +1322,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1340,7 +1367,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbu if (((FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) && (hfmpsmbus->XferSize == 2U)) || (hfmpsmbus->XferSize == 1U)) { FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); } else { @@ -1455,7 +1482,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; @@ -1604,7 +1631,7 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) /* FMPSMBUS in mode Transmitter ---------------------------------------------------*/ if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | - FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TXIS) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || @@ -1629,7 +1656,7 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) /* FMPSMBUS in mode Receiver ----------------------------------------------------*/ if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | - FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || @@ -1750,7 +1777,7 @@ __weak void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @retval None */ __weak void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, - uint16_t AddrMatchCode) + uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfmpsmbus); @@ -1819,7 +1846,7 @@ __weak void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) * the configuration information for the specified FMPSMBUS. * @retval HAL state */ -uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus) +uint32_t HAL_FMPSMBUS_GetState(const FMPSMBUS_HandleTypeDef *hfmpsmbus) { /* Return FMPSMBUS handle state */ return hfmpsmbus->State; @@ -1831,7 +1858,7 @@ uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus) * the configuration information for the specified FMPSMBUS. * @retval FMPSMBUS Error Code */ -uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus) +uint32_t HAL_FMPSMBUS_GetError(const FMPSMBUS_HandleTypeDef *hfmpsmbus) { return hfmpsmbus->ErrorCode; } @@ -1872,6 +1899,9 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, /* No need to generate STOP, it is automatically done */ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF; + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hfmpsmbus); @@ -1997,15 +2027,15 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, MAX_NBYTE_SIZE, - (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), - FMPSMBUS_NO_STARTSTOP); + (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), + FMPSMBUS_NO_STARTSTOP); hfmpsmbus->XferSize = MAX_NBYTE_SIZE; } else { hfmpsmbus->XferSize = hfmpsmbus->XferCount; FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) @@ -2162,6 +2192,9 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u /* Clear NACK Flag */ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF); + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hfmpsmbus); } @@ -2183,6 +2216,9 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u /* Set ErrorCode corresponding to a Non-Acknowledge */ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF; + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hfmpsmbus); @@ -2258,8 +2294,8 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u { /* Set Reload for next Bytes */ FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK; @@ -2272,15 +2308,15 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE) { FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE, - (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), - FMPSMBUS_NO_STARTSTOP); + (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), + FMPSMBUS_NO_STARTSTOP); hfmpsmbus->XferSize = MAX_NBYTE_SIZE; } else { hfmpsmbus->XferSize = hfmpsmbus->XferCount; FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) @@ -2584,7 +2620,13 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_PECERR); } - /* Store current volatile hfmpsmbus->State, misra rule */ + if (hfmpsmbus->ErrorCode != HAL_FMPSMBUS_ERROR_NONE) + { + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + } + + /* Store current volatile hfmpsmbus->ErrorCode, misra rule */ tmperror = hfmpsmbus->ErrorCode; /* Call the Error Callback in case of Error detected */ @@ -2625,7 +2667,7 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @retval HAL status */ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, - FlagStatus Status, uint32_t Timeout) + FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2654,6 +2696,27 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef return HAL_OK; } +/** + * @brief FMPSMBUS Tx data register flush process. + * @param hfmpsmbus FMPSMBUS handle. + * @retval None + */ +static void FMPSMBUS_Flush_TXDR(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXIS) != RESET) + { + hfmpsmbus->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXE) == RESET) + { + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXE); + } +} + /** * @brief Handle FMPSMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hfmpsmbus FMPSMBUS handle. @@ -2675,7 +2738,7 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef * @retval None */ static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, - uint32_t Mode, uint32_t Request) + uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c index f3aafe0a57..5fc5cc9d95 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c @@ -1657,7 +1657,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; uint32_t inputaddr; uint32_t buffersize; - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; if (hhash->State != HAL_HASH_STATE_SUSPENDED) { diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c index c7c5b70b90..7ab1222726 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c @@ -109,7 +109,9 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx; +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ /* Check the HCD handle allocation */ if (hhcd == NULL) @@ -120,7 +122,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); +#if defined (USB_OTG_FS) USBx = hhcd->Instance; +#endif /* defined (USB_OTG_FS) */ if (hhcd->State == HAL_HCD_STATE_RESET) { @@ -150,23 +154,37 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) hhcd->State = HAL_HCD_STATE_BUSY; +#if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ - if ((USBx->CID & (0x1U << 8)) == 0U) + if (USBx == USB_OTG_FS) { hhcd->Init.dma_enable = 0U; } +#endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_HCD_DISABLE(hhcd); /* Init the Core (common init.) */ - (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } - /* Force Host Mode*/ - (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + /* Force Host Mode */ + if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } /* Init Host */ - (void)USB_HostInit(hhcd->Instance, hhcd->Init); + if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } hhcd->State = HAL_HCD_STATE_READY; @@ -197,24 +215,22 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 0 to32K * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) { HAL_StatusTypeDef status; + uint32_t HostCoreSpeed; + uint32_t HCcharMps = mps; __HAL_LOCK(hhcd); hhcd->hc[ch_num].do_ping = 0U; hhcd->hc[ch_num].dev_addr = dev_address; - hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ep_type = ep_type; hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + (void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num); + if ((epnum & 0x80U) == 0x80U) { hhcd->hc[ch_num].ep_is_in = 1U; @@ -224,15 +240,27 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].ep_is_in = 0U; } + HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + if (ep_type == EP_TYPE_ISOC) + { + /* FS device plugged to HS HUB */ + if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + if (HCcharMps > ISO_SPLT_MPS) + { + /* ISO Max Packet Size for Split mode */ + HCcharMps = ISO_SPLT_MPS; + } + } + } + hhcd->hc[ch_num].speed = speed; + hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps; + + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, + dev_address, speed, ep_type, (uint16_t)HCcharMps); - status = USB_HC_Init(hhcd->Instance, - ch_num, - epnum, - dev_address, - speed, - ep_type, - mps); __HAL_UNLOCK(hhcd); return status; @@ -250,7 +278,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) HAL_StatusTypeDef status = HAL_OK; __HAL_LOCK(hhcd); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + (void)USB_HC_Halt(hhcd->Instance, ch_num); __HAL_UNLOCK(hhcd); return status; @@ -389,24 +417,41 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, switch (ep_type) { case EP_TYPE_CTRL: - if ((token == 1U) && (direction == 0U)) /*send data */ + if (token == 1U) /* send data */ { - if (length == 0U) + if (direction == 0U) { - /* For Status OUT stage, Length==0, Status Out PID = 1 */ - hhcd->hc[ch_num].toggle_out = 1U; - } + if (length == 0U) + { + /* For Status OUT stage, Length == 0U, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } - /* Set the Data Toggle bit as per the Flag */ - if (hhcd->hc[ch_num].toggle_out == 0U) - { - /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } else { - /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + if (hhcd->hc[ch_num].do_ssplit == 1U) + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } } } break; @@ -541,8 +586,11 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) (void)USB_FlushTxFifo(USBx, 0x10U); (void)USB_FlushRxFifo(USBx); - /* Restore FS Clock */ - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) @@ -571,16 +619,6 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); } - /* Handle Rx Queue Level Interrupts */ - if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) - { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - HCD_RXQLVL_IRQHandler(hhcd); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - /* Handle Host channel Interrupt */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { @@ -601,6 +639,16 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); } + + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } } } @@ -1084,7 +1132,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) * @param hhcd HCD handle * @retval HAL state */ -HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd) { return hhcd->State; } @@ -1103,7 +1151,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) * URB_ERROR/ * URB_STALL */ -HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) { return hhcd->hc[chnum].urb_state; } @@ -1116,7 +1164,7 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu * This parameter can be a value from 1 to 15 * @retval last transfer size in byte */ -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum) { return hhcd->hc[chnum].xfer_count; } @@ -1138,7 +1186,7 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) * HC_BBLERR/ * HC_DATATGLERR */ -HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) { return hhcd->hc[chnum].state; } @@ -1163,6 +1211,54 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) return (USB_GetHostSpeed(hhcd->Instance)); } +/** + * @brief Set host channel Hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param addr Hub address + * @param PortNbr Hub port number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr) +{ + uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + /* LS/FS device plugged to HS HUB */ + if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + hhcd->hc[ch_num].do_ssplit = 1U; + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U)) + { + hhcd->hc[ch_num].toggle_in = 1U; + } + } + + hhcd->hc[ch_num].hub_addr = addr; + hhcd->hc[ch_num].hub_port_nbr = PortNbr; + + return HAL_OK; +} + + +/** + * @brief Clear host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + hhcd->hc[ch_num].do_ssplit = 0U; + hhcd->hc[ch_num].do_csplit = 0U; + hhcd->hc[ch_num].hub_addr = 0U; + hhcd->hc[ch_num].hub_port_nbr = 0U; + + return HAL_OK; +} /** * @} */ @@ -1183,84 +1279,86 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) */ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t ch_num = (uint32_t)chnum; - uint32_t tmpreg; - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); - hhcd->hc[ch_num].state = HC_BBLERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); + hhcd->hc[chnum].state = HC_BBLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - hhcd->hc[ch_num].state = HC_STALL; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); - hhcd->hc[ch_num].state = HC_DATATGLERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) - { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } else { /* ... */ } - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) { - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) { + /* Clear any pending ACK IT */ + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + if (hhcd->Init.dma_enable != 0U) { - hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \ - (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); } - hhcd->hc[ch_num].state = HC_XFRC; - hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + hhcd->hc[chnum].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } - else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)) + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || + (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[ch_num].urb_state = URB_DONE; + USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[chnum].urb_state = URB_DONE; #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else @@ -1270,96 +1368,220 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->Init.dma_enable == 1U) { - if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U) + if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) { - hhcd->hc[ch_num].toggle_in ^= 1U; + hhcd->hc[chnum].toggle_in ^= 1U; } } else { - hhcd->hc[ch_num].toggle_in ^= 1U; + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 1U; + hhcd->hc[chnum].state = HC_ACK; + + (void)USB_HC_Halt(hhcd->Instance, chnum); } } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) { - if (hhcd->hc[ch_num].state == HC_XFRC) + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) { - hhcd->hc[ch_num].urb_state = URB_DONE; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; } - else if (hhcd->hc[ch_num].state == HC_STALL) + else if (hhcd->hc[chnum].state == HC_STALL) { - hhcd->hc[ch_num].urb_state = URB_STALL; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; } - else if ((hhcd->hc[ch_num].state == HC_XACTERR) || - (hhcd->hc[ch_num].state == HC_DATATGLERR)) + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + hhcd->hc[chnum].ep_ss_schedule = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; - /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } } } - else if (hhcd->hc[ch_num].state == HC_NAK) + else if (hhcd->hc[chnum].state == HC_NYET) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; - /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + if (hhcd->hc[chnum].do_csplit == 1U) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].NyetErrCnt++; + if (hhcd->hc[chnum].NyetErrCnt > 2U) + { + hhcd->hc[chnum].NyetErrCnt = 0U; + hhcd->hc[chnum].do_csplit = 0U; + + if (hhcd->hc[chnum].ErrCnt < 3U) + { + hhcd->hc[chnum].ep_ss_schedule = 1U; + } + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Set Complete split and re-activate the channel */ + USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } } - else if (hhcd->hc[ch_num].state == HC_BBLERR) + else if (hhcd->hc[chnum].state == HC_BBLERR) { - hhcd->hc[ch_num].ErrCnt++; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - /* ... */ + if (hhcd->hc[chnum].state == HC_HALTED) + { + return; + } } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].ErrCnt = 0U; + } + + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) { - if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) { - hhcd->hc[ch_num].ErrCnt = 0U; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt = 0U; - if (hhcd->Init.dma_enable == 0U) + if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U)) { - hhcd->hc[ch_num].state = HC_NAK; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); } } else { /* ... */ } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + __HAL_HCD_UNMASK_ACK_HC_INT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } else { @@ -1376,184 +1598,231 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t ch_num = (uint32_t)chnum; uint32_t tmpreg; uint32_t num_packets; - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_ping == 1U) + { + hhcd->hc[chnum].do_ping = 0U; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } - if (hhcd->hc[ch_num].do_ping == 1U) + if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U)) { - hhcd->hc[ch_num].do_ping = 0U; - hhcd->hc[ch_num].urb_state = URB_NOTREADY; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC) + { + hhcd->hc[chnum].do_csplit = 1U; + } + + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + + /* reset error_count */ + hhcd->hc[chnum].ErrCnt = 0U; } } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) { - hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt = 0U; /* transaction completed with NYET state, update do ping state */ - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) { - hhcd->hc[ch_num].do_ping = 1U; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].do_ping = 1U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); - hhcd->hc[ch_num].state = HC_XFRC; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + + if (hhcd->hc[chnum].do_csplit != 0U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) { - hhcd->hc[ch_num].state = HC_NYET; - hhcd->hc[ch_num].do_ping = 1U; - hhcd->hc[ch_num].ErrCnt = 0U; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].do_ping = 1U; + } + + hhcd->hc[chnum].ErrCnt = 0U; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - hhcd->hc[ch_num].state = HC_STALL; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].state = HC_NAK; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; - if (hhcd->hc[ch_num].do_ping == 0U) + if (hhcd->hc[chnum].do_ping == 0U) { - if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH) + if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) { - hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[chnum].do_ping = 1U; } } - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) { if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } else { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; } } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) { - hhcd->hc[ch_num].state = HC_DATATGLERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) { - if (hhcd->hc[ch_num].state == HC_XFRC) + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) { - hhcd->hc[ch_num].urb_state = URB_DONE; - if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || + (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) { if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[ch_num].toggle_out ^= 1U; + hhcd->hc[chnum].toggle_out ^= 1U; } - if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U)) + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) { - num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; + num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; if ((num_packets & 1U) != 0U) { - hhcd->hc[ch_num].toggle_out ^= 1U; + hhcd->hc[chnum].toggle_out ^= 1U; } } } } - else if (hhcd->hc[ch_num].state == HC_NAK) + else if (hhcd->hc[chnum].state == HC_ACK) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } } - else if (hhcd->hc[ch_num].state == HC_NYET) + else if (hhcd->hc[chnum].state == HC_NAK) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } } - else if (hhcd->hc[ch_num].state == HC_STALL) + else if (hhcd->hc[chnum].state == HC_NYET) { - hhcd->hc[ch_num].urb_state = URB_STALL; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; } - else if ((hhcd->hc[ch_num].state == HC_XACTERR) || - (hhcd->hc[ch_num].state == HC_DATATGLERR)) + else if (hhcd->hc[chnum].state == HC_STALL) { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + USBx_HC(chnum)->HCCHAR = tmpreg; } } else { - /* ... */ + return; } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); - #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { - /* ... */ + return; } } @@ -1564,17 +1833,17 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t pktsts; uint32_t pktcnt; uint32_t GrxstspReg; uint32_t xferSizePktCnt; uint32_t tmpreg; - uint32_t ch_num; + uint32_t chnum; GrxstspReg = hhcd->Instance->GRXSTSP; - ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; + chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; @@ -1582,33 +1851,33 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { case GRXSTS_PKTSTS_IN: /* Read the data into the host buffer. */ - if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) + if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) { - if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len) + if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) { (void)USB_ReadPacket(hhcd->Instance, - hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); + hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt); /* manage multiple Xfer */ - hhcd->hc[ch_num].xfer_buff += pktcnt; - hhcd->hc[ch_num].xfer_count += pktcnt; + hhcd->hc[chnum].xfer_buff += pktcnt; + hhcd->hc[chnum].xfer_count += pktcnt; /* get transfer size packet count */ - xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; + xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; - if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) { /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - hhcd->hc[ch_num].toggle_in ^= 1U; + USBx_HC(chnum)->HCCHAR = tmpreg; + hhcd->hc[chnum].toggle_in ^= 1U; } } else { - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].urb_state = URB_ERROR; } } break; @@ -1630,7 +1899,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) */ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0; __IO uint32_t hprt0_dup; @@ -1663,7 +1932,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) { - if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) { @@ -1678,7 +1947,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { if (hhcd->Init.speed == HCD_SPEED_FULL) { - USBx_HOST->HFIR = 60000U; + USBx_HOST->HFIR = HFIR_60_MHZ; } } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c index c2a8eb7543..f2884b69f6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -89,7 +89,7 @@ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() @@ -139,7 +139,7 @@ or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() @@ -193,7 +193,7 @@ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() @@ -313,7 +313,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @addtogroup I2C_Private_Define +/** @defgroup I2C_Private_Define I2C Private Define * @{ */ #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ @@ -334,6 +334,14 @@ */ /* Private macro -------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macros + * @{ + */ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -383,6 +391,9 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); /* Private function to Convert Specific options */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); + +/* Private function to flush DR register */ +static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c); /** * @} */ @@ -940,6 +951,20 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @brief I2C data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c) +{ + /* Write a dummy data in DR to clear TXE flag */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET) + { + hi2c->Instance->DR = 0x00U; + } +} + /** * @} */ @@ -1357,6 +1382,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) { + + if (hi2c->XferSize == 3U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; @@ -1662,10 +1694,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -1742,10 +1771,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -1952,10 +1978,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -2110,10 +2133,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -2811,6 +2831,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) { + if (hi2c->XferSize == 3U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; @@ -2871,10 +2896,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -2959,10 +2981,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3057,10 +3076,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3241,10 +3257,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3577,10 +3590,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3676,10 +3686,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3859,10 +3866,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3984,10 +3988,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -4712,7 +4713,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4728,7 +4729,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA UNUSED(DevAddress); /* Abort Master transfer during Receive or Transmit process */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER)) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) || + (CurrentMode == HAL_I2C_MODE_MEM))) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -5504,7 +5506,8 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) } else { - /* Do nothing */ + /* Clear TXE and BTF flags */ + I2C_Flush_DR(hi2c); } } @@ -5519,7 +5522,9 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { uint32_t tmp; + uint32_t CurrentXferOptions; + CurrentXferOptions = hi2c->XferOptions; tmp = hi2c->XferCount; if (tmp > 3U) { @@ -5575,7 +5580,14 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) else { hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterRxCpltCallback(hi2c); @@ -5723,7 +5735,14 @@ static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) else { hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterRxCpltCallback(hi2c); #else @@ -6170,7 +6189,7 @@ static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) { if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) { - hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx)); + hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx)); if (hi2c->XferCount != 0U) { @@ -6198,7 +6217,7 @@ static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) } else { - hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx)); + hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx)); if (hi2c->XferCount != 0U) { @@ -6367,6 +6386,9 @@ static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /* Clear TXE flag */ + I2C_Flush_DR(hi2c); + #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveTxCpltCallback(hi2c); #else @@ -7028,7 +7050,14 @@ static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) else { hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterRxCpltCallback(hi2c); @@ -7203,15 +7232,18 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7255,15 +7287,18 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7293,15 +7328,18 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7331,15 +7369,18 @@ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7367,15 +7408,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -7441,15 +7485,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c index 47b44ffdb1..0072dc19f2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c @@ -439,6 +439,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) /** * @brief Register a User IRDA Callback * To be used instead of the weak predefined callback + * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -466,8 +468,6 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hirda); if (hirda->gState == HAL_IRDA_STATE_READY) { @@ -552,15 +552,14 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } /** * @brief Unregister an IRDA callback * IRDA callback is redirected to the weak predefined callback + * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -580,9 +579,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hirda); - if (HAL_IRDA_STATE_READY == hirda->gState) { switch (CallbackID) @@ -666,9 +662,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ @@ -2030,7 +2023,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA. * @retval HAL state */ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda) { uint32_t temp1 = 0x00U, temp2 = 0x00U; temp1 = hirda->gState; @@ -2045,7 +2038,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA. * @retval IRDA Error Code */ -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda) { return hirda->ErrorCode; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c index 7b569513ce..05fa66da80 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c @@ -185,7 +185,7 @@ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag); /* Exported functions --------------------------------------------------------*/ @@ -1753,7 +1753,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Counter value. */ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1766,7 +1766,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Autoreload value. */ -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1779,7 +1779,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Compare value. */ -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -2077,9 +2077,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2150,9 +2147,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } @@ -2178,9 +2172,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2262,9 +2253,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -2292,7 +2280,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti * @param hlptim LPTIM handle * @retval HAL state */ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim) { /* Return LPTIM handle state */ return hlptim->State; @@ -2339,7 +2327,7 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) * @param flag The lptim flag * @retval HAL status */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag) { HAL_StatusTypeDef result = HAL_OK; uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c index fcc5fa1611..f5f814820d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c @@ -178,7 +178,13 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Define LTDC Private Define + * @{ + */ #define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -549,7 +555,7 @@ HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTD break; case HAL_LTDC_MSPINIT_CB_ID : - hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ break; case HAL_LTDC_MSPDEINIT_CB_ID : diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c index 2ee7795bf3..ab2ca72ec4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c @@ -74,16 +74,18 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc /* The following polarity is inverted: LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ +#if !defined(POLARITIES_INVERSION_UPDATED) /* Note 1 : Code in line w/ Current LTDC specification */ hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \ DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; - +#else /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ - /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; - hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; - hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ + hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; +#endif /* POLARITIES_INVERSION_UPDATED */ /* Retrieve vertical timing parameters from DSI */ hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; @@ -115,17 +117,18 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ +#if !defined(POLARITIES_INVERSION_UPDATED) /* Note 1 : Code in line w/ Current LTDC specification */ hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \ DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; - +#else /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ - /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; - hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; - hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ - + hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; +#endif /* POLARITIES_INVERSION_UPDATED */ return HAL_OK; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c index a0b89e621c..5cd4ab2dae 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c @@ -77,15 +77,15 @@ and a pointer to the user callback function. Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_NAND_Init + reset to the legacy weak (overridden) functions in the HAL_NAND_Init and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -100,7 +100,7 @@ When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -199,7 +199,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank); #else __FMC_NAND_ENABLE(hnand->Instance); -#endif +#endif /* (FMC_Bank2_3) || (FSMC_Bank2_3) */ /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -428,7 +428,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* Send Read ID command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; @@ -441,7 +441,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) #else /* FMC_PCR2_PWID is defined */ if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) -#endif +#endif /* FSMC_PCR2_PWID */ { data = *(__IO uint32_t *)deviceaddress; @@ -512,7 +512,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* Send NAND reset command */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; @@ -561,8 +561,8 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; @@ -597,7 +597,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -730,8 +730,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; @@ -766,7 +766,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -860,9 +860,9 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address /* Calculate PageSize */ #if defined(FSMC_PCR2_PWID) - if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) #else - if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) #endif /* FSMC_PCR2_PWID */ { hnand->Config.PageSize = hnand->Config.PageSize / 2U; @@ -913,8 +913,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; @@ -922,7 +922,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; - uint8_t *buff = pBuffer; + const uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -949,7 +949,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1077,8 +1077,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; @@ -1086,7 +1086,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; - uint16_t *buff = pBuffer; + const uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1113,7 +1113,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1181,9 +1181,9 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres /* Calculate PageSize */ #if defined(FSMC_PCR2_PWID) - if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) #else - if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) #endif /* FSMC_PCR2_PWID */ { hnand->Config.PageSize = hnand->Config.PageSize / 2U; @@ -1256,8 +1256,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumSpareAreaToRead) +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; uint32_t tickstart; @@ -1293,7 +1293,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1432,7 +1432,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; @@ -1469,7 +1469,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1608,8 +1608,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; @@ -1618,7 +1618,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; - uint8_t *buff = pBuffer; + const uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1645,7 +1645,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* Page address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1782,8 +1782,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; @@ -1792,7 +1792,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; - uint16_t *buff = pBuffer; + const uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1819,7 +1819,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* NAND raw address calculation */ nandaddress = ARRAY_ADDRESS(pAddress, hnand); @@ -1954,7 +1954,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A * @param pAddress pointer to NAND address structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress) { uint32_t deviceaddress; @@ -1983,7 +1983,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* Send Erase block command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; @@ -2021,7 +2021,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address */ -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { uint32_t status = NAND_VALID_ADDRESS; @@ -2052,7 +2052,7 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /** * @brief Register a User NAND Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hnand : NAND handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -2072,9 +2072,6 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hnand); - if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) @@ -2116,14 +2113,12 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnand); return status; } /** * @brief Unregister a User NAND Callback - * NAND Callback is redirected to the weak (surcharged) predefined callback + * NAND Callback is redirected to the weak predefined callback * @param hnand : NAND handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -2136,9 +2131,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hnand); - if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) @@ -2180,8 +2172,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnand); return status; } #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ @@ -2332,7 +2322,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, * the configuration information for NAND module. * @retval HAL state */ -HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) +HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand) { return hnand->State; } @@ -2343,7 +2333,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) * the configuration information for NAND module. * @retval NAND status */ -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) +uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand) { uint32_t data; uint32_t deviceaddress; @@ -2361,7 +2351,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) } #else deviceaddress = NAND_DEVICE; -#endif +#endif /* FMC_Bank2_3 */ /* Send Read status operation command */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c index 0a82044866..22366b4005 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c @@ -74,15 +74,15 @@ and a pointer to the user callback function. Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_NOR_Init + reset to the legacy weak (overridden) functions in the HAL_NOR_Init and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -97,7 +97,7 @@ When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -106,7 +106,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" -#if defined(FMC_Bank1) || defined(FSMC_Bank1) +#if defined(FMC_Bank1) || defined(FSMC_Bank1) /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -127,6 +127,11 @@ */ /* Constants to define address to set to write a command */ +#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA +#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA +#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA + #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA @@ -264,7 +269,8 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); /* Initialize NOR extended mode timing Interface */ - (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); + (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, + hnor->Init.NSBank, hnor->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); @@ -310,7 +316,16 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe else { /* Get the value of the command set */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), + NOR_CMD_DATA_CFI); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + } + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); status = HAL_NOR_ReturnToReadMode(hnor); @@ -472,9 +487,22 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I /* Send read ID command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_AUTO_SELECT); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_AUTO_SELECT); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -641,9 +669,22 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_READ_RESET); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_READ_RESET); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -722,9 +763,21 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /* Send program data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_PROGRAM); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -814,9 +867,22 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_READ_RESET); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_READ_RESET); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -909,10 +975,20 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + } + else + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + } /* Write Buffer Load Command */ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); @@ -1012,14 +1088,26 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Send block erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + } NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) @@ -1097,15 +1185,28 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) /* Send NOR chip erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), + NOR_CMD_DATA_CHIP_ERASE); + } } else { @@ -1176,8 +1277,15 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR } /* Send read CFI query command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), + NOR_CMD_DATA_CFI); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + } /* read the NOR CFI information */ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); @@ -1201,7 +1309,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) /** * @brief Register a User NOR Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hnor : NOR handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1221,9 +1329,6 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hnor); - state = hnor->State; if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { @@ -1247,14 +1352,12 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnor); return status; } /** * @brief Unregister a User NOR Callback - * NOR Callback is redirected to the weak (surcharged) predefined callback + * NOR Callback is redirected to the weak predefined callback * @param hnor : NOR handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1267,9 +1370,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hnor); - state = hnor->State; if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { @@ -1293,8 +1393,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hnor); return status; } #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ @@ -1411,7 +1509,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) * the configuration information for NOR module. * @retval NOR controller state */ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) +HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor) { return hnor->State; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c index 7e46592b31..fa50ea1863 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c @@ -122,7 +122,9 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx; +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ @@ -134,7 +136,9 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); +#if defined (USB_OTG_FS) USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) { @@ -171,11 +175,13 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; +#if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ - if ((USBx->CID & (0x1U << 8)) == 0U) + if (USBx == USB_OTG_FS) { hpcd->Init.dma_enable = 0U; } +#endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); @@ -187,8 +193,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) return HAL_ERROR; } - /* Force Device Mode*/ - (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); + /* Force Device Mode */ + if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) @@ -224,13 +234,17 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->USB_Address = 0U; hpcd->State = HAL_PCD_STATE_READY; -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) { (void)HAL_PCDEx_ActivateLPM(hpcd); } -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); return HAL_OK; @@ -318,7 +332,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function @@ -432,7 +446,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status @@ -1004,8 +1018,8 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; @@ -1033,8 +1047,8 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Disable USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -1306,7 +1320,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) { @@ -1332,7 +1348,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { @@ -1513,16 +1531,17 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) */ void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) USB_OTG_GlobalTypeDef *USBx; - USBx = hpcd->Instance; - if ((USBx->CID & (0x1U << 8)) == 0U) + if (USBx == USB_OTG_FS) { /* Clear EXTI pending Bit */ __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG(); } else +#endif /* defined (USB_OTG_FS) */ { /* Clear EXTI pending Bit */ __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG(); @@ -1733,8 +1752,8 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; @@ -1757,8 +1776,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Disable USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -1818,6 +1837,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; } + /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) { @@ -1851,7 +1871,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; ep->is_in = 0U; } - ep->num = ep_addr & EP_ADDR_MSK; + ep->num = ep_addr & EP_ADDR_MSK; __HAL_LOCK(hpcd); (void)USB_DeactivateEndpoint(hpcd->Instance, ep); @@ -1886,14 +1906,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); return HAL_OK; } @@ -1904,7 +1917,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u * @param ep_addr endpoint address * @retval Data Size */ -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) { return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; } @@ -1934,14 +1947,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); return HAL_OK; } @@ -2119,20 +2125,21 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval HAL state */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) { return hpcd->State; } +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Set the USB Device high speed test mode. * @param hpcd PCD handle * @param testmode USB Device high speed test mode * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; switch (testmode) @@ -2151,6 +2158,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) return HAL_OK; } +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ @@ -2233,9 +2241,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { USB_OTG_EPTypeDef *ep; - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; if (hpcd->Init.dma_enable == 1U) @@ -2344,9 +2352,9 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; if ((gSNPSiD > USB_OTG_CORE_ID_300A) && diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c index 292faf13bc..b66be6ac35 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c @@ -115,7 +115,9 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) return HAL_OK; } -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -148,8 +150,11 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) return HAL_OK; } -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \ + || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Handle BatteryCharging Process. * @param hpcd PCD handle @@ -178,9 +183,9 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN; HAL_Delay(50U); - USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; HAL_Delay(50U); if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U) @@ -196,9 +201,9 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) { /* start secondary detection to check connection to Charging Downstream Port or Dedicated Charging Port */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN; + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); HAL_Delay(50U); - USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; HAL_Delay(50U); if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET) @@ -285,7 +290,8 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) return HAL_OK; } -#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c index b9f7cc20cb..6b29888126 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c @@ -179,10 +179,12 @@ void HAL_PWR_DisableBkUpAccess(void) ================== [..] (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry) functions with (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and + no clear of pending event before. -@@- The Regulator parameter is not used for the STM32F4 family and is kept as parameter just to maintain compatibility with the @@ -204,10 +206,17 @@ void HAL_PWR_DisableBkUpAccess(void) the HAL_PWREx_DisableFlashPowerDown() function. (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry) function with: - (++) Main regulator ON. - (++) Low Power regulator ON. + (++) Regulator: + (+++) Main regulator ON. + (+++) Low Power regulator ON. + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + clear of pending events before. + (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + no clear of pending event before. (+) Exit: Any EXTI Line (Internal or External) configured in Interrupt/Event mode. @@ -372,12 +381,18 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) * just to maintain compatibility with the lower power families. * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and + * no clear of pending event before. * @retval None */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); @@ -393,9 +408,14 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) } else { + if(SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + /* Request Wait For Event */ - __SEV(); - __WFE(); __WFE(); } } @@ -415,8 +435,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @arg PWR_STOPENTRY_WFI : Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE : Enter Stop mode with WFE instruction and + * clear of pending events before. + * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + * no clear of pending event before. * @retval None */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) @@ -439,9 +462,13 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) } else { + if(STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } /* Request Wait For Event */ - __SEV(); - __WFE(); __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c index 74ffe1647c..508f0b6d85 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c @@ -162,7 +162,7 @@ and a pointer to the user callback function. Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. (+) FifoThresholdCallback : callback when the fifo threshold is reached. @@ -178,9 +178,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init + reset to the legacy weak (overridden) functions in the HAL_QSPI_Init and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -195,7 +195,7 @@ When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** Workarounds linked to Silicon Limitation *** ==================================================== @@ -2075,7 +2075,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) /** * @brief Register a User QSPI Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hqspi QSPI handle * @param CallbackId ID of the callback to be registered * This parameter can be one of the following values: @@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI /** * @brief Unregister a User QSPI Callback - * QSPI Callback is redirected to the weak (surcharged) predefined callback + * QSPI Callback is redirected to the weak predefined callback * @param hqspi QSPI handle * @param CallbackId ID of the callback to be unregistered * This parameter can be one of the following values: diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c index f187348743..8e494e630e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -479,7 +479,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -517,7 +517,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c index 114e09e058..0250aa722d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c @@ -843,6 +843,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } @@ -1253,6 +1257,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } @@ -1910,6 +1918,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } @@ -2140,6 +2152,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } @@ -2491,6 +2507,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } @@ -2745,6 +2765,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; } + default: + { + break; + } } return frequency; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c index bd50438df1..885ce69aa9 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c @@ -52,7 +52,7 @@ [..] Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -66,10 +66,10 @@ [..] By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak (overridden) functions: example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_RNG_Init() + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -86,7 +86,7 @@ [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -307,8 +307,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -362,8 +360,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -382,8 +378,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -437,8 +431,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -697,15 +689,16 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; /* RNG clock error interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } - else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; @@ -736,7 +729,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) } /* Check RNG data ready interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) { /* Generate random number once, so disable the IT */ __HAL_RNG_DISABLE_IT(hrng); @@ -768,7 +761,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval random value */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) { return (hrng->RandomNumber); } @@ -830,7 +823,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval HAL state */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) { return hrng->State; } @@ -840,7 +833,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code */ -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ return hrng->ErrorCode; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c index 2d2be66ddc..0365accf00 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -306,38 +306,50 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + if (status == HAL_OK) + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + /* Set RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + if (status == HAL_OK) + { + hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL; + hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; } if (status == HAL_OK) { - hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL; - hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); - hrtc->State = HAL_RTC_STATE_READY; } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - return status; } @@ -522,7 +534,7 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call /** * @brief Unregisters an RTC Callback - * RTC callabck is redirected to the weak predefined callback + * RTC callback is redirected to the weak predefined callback * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param CallbackID ID of the callback to be unregistered @@ -1293,7 +1305,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ do { - if (count-- == 0U) + count = count - 1U; + if (count == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1329,7 +1342,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ do { - if (count-- == 0U) + count = count - 1U; + if (count == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1529,21 +1543,24 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) { + /* Clear the EXTI's line Flag for RTC Alarm */ + __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); + /* Get the Alarm A interrupt source enable status */ if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U) { /* Get the pending status of the Alarm A Interrupt */ if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U) { + /* Clear the Alarm A interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + /* Alarm A callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->AlarmAEventCallback(hrtc); #else HAL_RTC_AlarmAEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Alarm A interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); } } @@ -1553,21 +1570,18 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) /* Get the pending status of the Alarm B Interrupt */ if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U) { + /* Clear the Alarm B interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + /* Alarm B callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->AlarmBEventCallback(hrtc); #else HAL_RTCEx_AlarmBEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Alarm B interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); } } - /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } @@ -1663,8 +1677,8 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { uint32_t tickstart = 0U; - /* Clear RSF flag */ - hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; + /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */ + hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK)); /* Get tick */ tickstart = HAL_GetTick(); @@ -1859,7 +1873,7 @@ HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) */ uint8_t RTC_ByteToBcd2(uint8_t number) { - uint8_t bcdhigh = 0U; + uint32_t bcdhigh = 0U; while (number >= 10U) { @@ -1877,9 +1891,9 @@ uint8_t RTC_ByteToBcd2(uint8_t number) */ uint8_t RTC_Bcd2ToByte(uint8_t number) { - uint8_t tmp = 0U; - tmp = ((uint8_t)(number & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (number & (uint8_t)0x0F)); + uint32_t tens = 0U; + tens = (((uint32_t)number & 0xF0U) >> 4U) * 10U; + return (uint8_t)(tens + ((uint32_t)number & 0x0FU)); } /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c index eb5708fa0d..f6aec5ea18 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -605,6 +605,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { + /* Clear the EXTI's Flag for RTC Timestamp and Tamper */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); + /* Get the Timestamp interrupt source enable status */ if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U) { @@ -618,7 +621,8 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_TimeStampEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the Timestamp interrupt pending bit */ + /* Clear the Timestamp interrupt pending bit after returning from callback + as RTC_TSTR and RTC_TSDR registers are cleared when TSF bit is reset */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); } } @@ -629,15 +633,15 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /* Get the pending status of the Tamper 1 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) { + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->Tamper1EventCallback(hrtc); #else HAL_RTCEx_Tamper1EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); } } @@ -648,22 +652,19 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /* Get the pending status of the Tamper 2 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) { + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->Tamper2EventCallback(hrtc); #else HAL_RTCEx_Tamper2EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); } } #endif /* RTC_TAMPER2_SUPPORT */ - /* Clear the EXTI's Flag for RTC Timestamp and Tamper */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } @@ -979,7 +980,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ do { - if (count-- == 0U) + count = count - 1U; + if (count == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1006,7 +1008,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ do { - if (count-- == 0U) + count = count - 1U; + if (count == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1130,23 +1133,23 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { + /* Clear the EXTI's line Flag for RTC WakeUpTimer */ + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); + /* Get the pending status of the Wakeup timer Interrupt */ if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) { + /* Clear the Wakeup timer interrupt pending bit */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + /* Wakeup timer callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->WakeUpTimerEventCallback(hrtc); #else HAL_RTCEx_WakeUpTimerEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Wakeup timer interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); } - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c index 19e3748285..e881d252ac 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c @@ -172,7 +172,7 @@ [..] Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. [..] @@ -187,10 +187,10 @@ [..] By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SAI_Init + reset to the legacy weak functions in the HAL_SAI_Init and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -207,7 +207,7 @@ [..] When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim */ @@ -260,7 +260,7 @@ typedef enum * @{ */ static void SAI_FillFifo(SAI_HandleTypeDef *hsai); -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode); +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, uint32_t mode); static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); @@ -1243,6 +1243,9 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + SAI_Disable(hsai); + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -1274,9 +1277,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) } } - /* Disable SAI peripheral */ - SAI_Disable(hsai); - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1302,6 +1302,9 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + SAI_Disable(hsai); + /* Check SAI DMA is enabled or not */ if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { @@ -1341,9 +1344,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) hsai->Instance->IMR = 0U; hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Disable SAI peripheral */ - SAI_Disable(hsai); - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1909,7 +1909,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) * the configuration information for SAI module. * @retval HAL state */ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai) { return hsai->State; } @@ -1920,7 +1920,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) * the configuration information for the specified SAI Block. * @retval SAI Error Code */ -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai) { return hsai->ErrorCode; } @@ -2138,7 +2138,7 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) * @param mode SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable */ -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, uint32_t mode) { uint32_t tmpIT = SAI_IT_OVRUDR; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c index 78a73f8089..2d5e8c4d67 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c @@ -95,7 +95,7 @@ * the configuration information for SAI module. * @retval SAI Clock Input */ -void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai) +void SAI_BlockSynchroConfig(const SAI_HandleTypeDef *hsai) { uint32_t tmpregisterGCR; @@ -158,7 +158,7 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai) * the configuration information for SAI module. * @retval SAI Clock Input */ -uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai) +uint32_t SAI_GetInputClock(const SAI_HandleTypeDef *hsai) { /* This variable used to store the SAI_CK_x (value in Hz) */ uint32_t saiclocksource = 0U; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c index 32e54ea152..ebafec7025 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c @@ -696,7 +696,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 } /* Get error state */ +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); @@ -911,7 +915,11 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint } /* Get error state */ +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); @@ -2921,13 +2929,17 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } } - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ { return HAL_SD_ERROR_DATA_TIMEOUT; } @@ -2949,7 +2961,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) *pData = SDIO_ReadFIFO(hsd->Instance); pData++; - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3141,13 +3153,17 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) break; } - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } +#if defined(SDIO_STA_STBITERR) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR))) +#else /* SDIO_STA_STBITERR not defined */ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) +#endif /* SDIO_STA_STBITERR */ { __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c index 31633a2b4e..eb31bdeef8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c @@ -82,15 +82,15 @@ and a pointer to the user callback function. Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : SDRAM MspInit. (+) MspDeInitCallback : SDRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init + reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -105,7 +105,7 @@ When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -132,9 +132,15 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma); static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma); static void SDRAM_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions @@ -785,7 +791,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) /** * @brief Register a User SDRAM Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -806,9 +812,6 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsdram); - state = hsdram->State; if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { @@ -851,14 +854,12 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsdram); return status; } /** * @brief Unregister a User SDRAM Callback - * SDRAM Callback is redirected to the weak (surcharged) predefined callback + * SDRAM Callback is redirected to the weak predefined callback * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -874,9 +875,6 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_ HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hsdram); - state = hsdram->State; if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { @@ -925,14 +923,12 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsdram); return status; } /** * @brief Register a User SDRAM Callback for DMA transfers - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsdram : SDRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1229,6 +1225,9 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) * @} */ +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ /** * @brief DMA SDRAM process complete callback. * @param hdma : DMA handle @@ -1295,6 +1294,9 @@ static void SDRAM_DMAError(DMA_HandleTypeDef *hdma) #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } +/** + * @} + */ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c index e721d80cd6..2295e7ecfd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c @@ -449,6 +449,9 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc) /** * @brief Register a User SMARTCARD Callback * To be used instead of the weak predefined callback + * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsc smartcard handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -474,8 +477,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, H return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsc); if (hsc->gState == HAL_SMARTCARD_STATE_READY) { @@ -554,15 +555,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, H status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsc); - return status; } /** * @brief Unregister an SMARTCARD callback * SMARTCARD callback is redirected to the weak predefined callback + * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsc smartcard handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -580,9 +581,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsc); - if (HAL_SMARTCARD_STATE_READY == hsc->gState) { switch (CallbackID) @@ -659,9 +657,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsc); - return status; } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -1780,7 +1775,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc * the configuration information for SMARTCARD module. * @retval HAL state */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc) { uint32_t temp1= 0x00U, temp2 = 0x00U; temp1 = hsc->gState; @@ -1795,7 +1790,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) * the configuration information for the specified SMARTCARD. * @retval SMARTCARD Error Code */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc) { return hsc->ErrorCode; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c index 25c72fda52..f8dbf31f6a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c @@ -181,7 +181,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @addtogroup SMBUS_Private_Define +/** @defgroup SMBUS_Private_Define SMBUS Private Define * @{ */ #define SMBUS_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ @@ -213,6 +213,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); static void SMBUS_ITError(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_Flush_DR(SMBUS_HandleTypeDef *hsmbus); /* Private functions for SMBUS transfer IRQ handler */ static HAL_StatusTypeDef SMBUS_MasterTransmit_TXE(SMBUS_HandleTypeDef *hsmbus); @@ -845,6 +846,17 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +/** + * @brief SMBUS data register flush process. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_Flush_DR(SMBUS_HandleTypeDef *hsmbus) +{ + /* Write a dummy data in DR to clear it */ + hsmbus->Instance->DR = 0x00U; +} + /** * @} */ @@ -1680,6 +1692,12 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) /* Clear AF flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Disable EVT, BUF and ERR interrupts */ + __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR); + + /* Flush data register */ + SMBUS_Flush_DR(hsmbus); } } @@ -2036,7 +2054,7 @@ static HAL_StatusTypeDef SMBUS_MasterTransmit_BTF(SMBUS_HandleTypeDef *hsmbus) /* Generate Stop */ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP); - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->PreviousState = SMBUS_STATE_NONE; hsmbus->State = HAL_SMBUS_STATE_READY; hsmbus->Mode = HAL_SMBUS_MODE_NONE; #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c index da7c302189..3b0ab1fa4d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c @@ -33,10 +33,12 @@ (##) SPDIFRX pins configuration: (+++) Enable the clock for the SPDIFRX GPIOs. (+++) Configure these SPDIFRX pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's). + (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and + HAL_SPDIFRX_ReceiveDataFlow_IT() API's). (+++) Configure the SPDIFRX interrupt priority. (+++) Enable the NVIC SPDIFRX IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's). + (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and + HAL_SPDIFRX_ReceiveControlFlow_DMA() API's). (+++) Declare a DMA handle structure for the reception of the Data Flow channel. (+++) Declare a DMA handle structure for the reception of the Control Flow channel. (+++) Enable the DMAx interface clock. @@ -46,8 +48,8 @@ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA CtrlRx/DataRx channel. - (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits - using HAL_SPDIFRX_Init() function. + (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, + stereo mode and masking of user bits using HAL_SPDIFRX_Init() function. -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process. @@ -90,7 +92,7 @@ ============================================= [..] Below the list of most used macros in SPDIFRX HAL driver. - (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State) + (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDLE State) (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State) (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State) (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts @@ -173,8 +175,13 @@ #if defined(STM32F446xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define SPDIFRX_TIMEOUT_VALUE 0xFFFFU - +/** @defgroup SPDIFRX_Private_Defines SPDIFRX Private Defines + * @{ + */ +#define SPDIFRX_TIMEOUT_VALUE 10U +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -888,7 +895,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, { if (count == 0U) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -973,7 +981,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi { if (count == 0U) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -1047,7 +1056,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ - if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != + HAL_OK) { /* Set SPDIFRX error */ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; @@ -1074,7 +1084,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, { if (count == 0U) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -1148,7 +1159,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ - if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != + HAL_OK) { /* Set SPDIFRX error */ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; @@ -1175,7 +1187,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd { if (count == 0U) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -1224,8 +1237,14 @@ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); /* Disable the SPDIFRX DMA channel */ - __HAL_DMA_DISABLE(hspdif->hdmaDrRx); - __HAL_DMA_DISABLE(hspdif->hdmaCsRx); + if (hspdif->hdmaDrRx != NULL) + { + __HAL_DMA_DISABLE(hspdif->hdmaDrRx); + } + if (hspdif->hdmaCsRx != NULL) + { + __HAL_DMA_DISABLE(hspdif->hdmaCsRx); + } /* Disable SPDIFRX peripheral */ __HAL_SPDIFRX_IDLE(hspdif); @@ -1578,8 +1597,8 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) * @param tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t tickstart) +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, + FlagStatus Status, uint32_t Timeout, uint32_t tickstart) { /* Wait until flag is set */ while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status) @@ -1589,7 +1608,8 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c index 62d5d65870..341b7ab591 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c @@ -856,6 +856,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -885,6 +886,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -914,9 +916,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error: - hspi->State = HAL_SPI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspi); return errorcode; @@ -939,6 +944,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -952,12 +963,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -1023,6 +1028,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1046,6 +1052,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1112,9 +1119,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1213,6 +1223,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { @@ -1246,6 +1265,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1258,6 +1278,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { @@ -1291,6 +1319,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1339,8 +1368,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD __HAL_SPI_CLEAR_OVRFLAG(hspi); } + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + else + { + hspi->State = HAL_SPI_STATE_READY; + } + error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1360,8 +1397,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); if ((pData == NULL) || (Size == 0U)) { @@ -1375,6 +1410,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1414,10 +1452,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { @@ -1425,8 +1459,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } -error : + /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1442,6 +1480,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { HAL_StatusTypeDef errorcode = HAL_OK; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1449,14 +1494,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); } - /* Process Locked */ - __HAL_LOCK(hspi); - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -1464,6 +1501,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1503,9 +1543,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current process unlock */ @@ -1517,9 +1554,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1541,9 +1581,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; @@ -1561,6 +1598,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p goto error; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1596,8 +1636,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p } #endif /* USE_SPI_CRC */ - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1606,9 +1644,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1695,7 +1736,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1735,6 +1775,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1749,12 +1795,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -1810,7 +1850,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1932,7 +1971,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1954,7 +1992,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -3595,6 +3632,13 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { + /* Wait until TXE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + /* Timeout in µs */ __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c index ef2eaf092e..178843732e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c @@ -83,15 +83,15 @@ and a pointer to the user callback function. Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init + reset to the legacy weak (overridden) functions in the HAL_SRAM_Init and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -106,7 +106,7 @@ When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -133,9 +133,15 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); static void SRAM_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ @@ -731,7 +737,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) /** * @brief Register a User SRAM Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -751,9 +757,6 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsram); - state = hsram->State; if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) { @@ -777,14 +780,12 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsram); return status; } /** * @brief Unregister a User SRAM Callback - * SRAM Callback is redirected to the weak (surcharged) predefined callback + * SRAM Callback is redirected to the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -799,9 +800,6 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - /* Process locked */ - __HAL_LOCK(hsram); - state = hsram->State; if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { @@ -847,14 +845,12 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsram); return status; } /** * @brief Register a User SRAM Callback for DMA transfers - * To be used instead of the weak (surcharged) predefined callback + * To be used to override the weak predefined callback * @param hsram : SRAM handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1018,7 +1014,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) * the configuration information for SRAM module. * @retval HAL state */ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) { return hsram->State; } @@ -1031,6 +1027,10 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) * @} */ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ + /** * @brief DMA SRAM process complete callback. * @param hdma : DMA handle @@ -1097,6 +1097,10 @@ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } +/** + * @} + */ + /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c index 1ca1781e9f..d5978cca3e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c @@ -204,9 +204,9 @@ all interrupt callbacks are set to the corresponding weak functions: /** @addtogroup TIM_Private_Functions * @{ */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); @@ -222,7 +222,7 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); + const TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ @@ -275,6 +275,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -522,7 +523,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; @@ -536,7 +537,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else if (htim->State == HAL_TIM_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -658,6 +659,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -1043,7 +1045,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1058,7 +1061,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1321,6 +1324,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -1706,7 +1710,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1721,7 +1726,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1983,6 +1988,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -2376,7 +2382,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -2632,6 +2638,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -3009,7 +3016,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; @@ -3035,6 +3042,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) { @@ -3544,7 +3552,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData1 == NULL) && (Length > 0U)) + if ((pData1 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3569,7 +3577,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData2 == NULL) && (Length > 0U)) + if ((pData2 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3598,7 +3606,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) { return HAL_ERROR; } @@ -3814,13 +3822,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + /* Capture compare 1 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3848,11 +3859,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 2 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) @@ -3878,11 +3889,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 3 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) @@ -3908,11 +3919,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 4 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) @@ -3938,11 +3949,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Update event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -3951,11 +3962,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else @@ -3964,11 +3975,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Trigger detection event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -3977,11 +3988,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM commutation event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else @@ -4028,7 +4039,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4106,7 +4117,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4206,7 +4217,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4468,7 +4479,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) { HAL_StatusTypeDef status; @@ -4520,7 +4532,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; @@ -5160,7 +5172,7 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -5289,7 +5301,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -5475,7 +5487,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5516,7 +5528,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5558,7 +5570,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; @@ -5832,8 +5844,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call { return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { @@ -6025,9 +6035,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } @@ -6070,9 +6077,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(htim); - if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) @@ -6304,9 +6308,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -6335,7 +6336,7 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @param htim TIM Base handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6345,7 +6346,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Output Compare handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6355,7 +6356,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6365,7 +6366,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) * @param htim TIM IC handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6375,7 +6376,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM OPM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6385,7 +6386,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Encoder Interface handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6395,7 +6396,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval Active channel */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) { return htim->Channel; } @@ -6413,7 +6414,7 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -6430,7 +6431,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, ui * @param htim TIM handle * @retval DMA burst state */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -6773,7 +6774,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) * @param Structure TIM Base configuration structure * @retval None */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; @@ -6813,6 +6814,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } } /** @@ -6821,17 +6829,18 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -6896,17 +6905,18 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -6935,7 +6945,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -6972,17 +6981,18 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7046,17 +7056,18 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7107,7 +7118,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -7247,9 +7258,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) @@ -7337,9 +7348,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; @@ -7376,9 +7387,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; @@ -7420,9 +7431,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; @@ -7468,9 +7479,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c index 092175f562..889f8fb9a7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c @@ -135,7 +135,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; @@ -151,6 +151,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -501,7 +502,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -834,7 +835,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -866,7 +867,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -881,7 +883,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1079,17 +1081,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1315,7 +1306,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1347,7 +1338,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1362,7 +1354,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1960,7 +1952,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig) + const TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; @@ -2021,7 +2013,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; @@ -2098,7 +2090,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { - /* Check parameters */ assert_param(IS_TIM_REMAP(htim->Instance, Remap)); @@ -2149,7 +2140,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2163,7 +2154,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2178,7 +2169,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2215,7 +2206,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) * @param htim TIM Hall Sensor handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -2230,7 +2221,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_3: TIM Channel 3 * @retval TIM Complementary channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -2329,15 +2320,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } else { /* nothing to do */ @@ -2406,13 +2388,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha { uint32_t tmp; - tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ } /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c index e7f0ace40a..e45f04c7af 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c @@ -6,7 +6,7 @@ * * This file override the native HAL time base functions (defined as weak) * to use the RTC ALARM for time base generation: - * + Intializes the RTC peripheral to increment the seconds registers each 1ms + * + Initializes the RTC peripheral to increment the seconds registers each 1ms * + The alarm is configured to assert an interrupt when the RTC reaches 1ms * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00 * + HSE (default), LSE or LSI can be selected as RTC clock source @@ -102,19 +102,19 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) HAL_StatusTypeDef status; #ifdef RTC_CLOCK_SOURCE_LSE - /* Configue LSE as RTC clock soucre */ + /* Configure LSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; #elif defined (RTC_CLOCK_SOURCE_LSI) - /* Configue LSI as RTC clock soucre */ + /* Configure LSI as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSIState = RCC_LSI_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; #elif defined (RTC_CLOCK_SOURCE_HSE) - /* Configue HSE as RTC clock soucre */ + /* Configure HSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c index a9cff87d24..897db4e612 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c @@ -6,7 +6,7 @@ * * This file overrides the native HAL time base functions (defined as weak) * to use the RTC WAKEUP for the time base generation: - * + Intializes the RTC peripheral and configures the wakeup timer to be + * + Initializes the RTC peripheral and configures the wakeup timer to be * incremented each 1ms * + The wakeup feature is configured to assert an interrupt each 1ms * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback @@ -109,19 +109,19 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) HAL_StatusTypeDef status; #ifdef RTC_CLOCK_SOURCE_LSE - /* Configue LSE as RTC clock soucre */ + /* Configure LSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; #elif defined (RTC_CLOCK_SOURCE_LSI) - /* Configue LSI as RTC clock soucre */ + /* Configure LSI as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSIState = RCC_LSI_ON; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; #elif defined (RTC_CLOCK_SOURCE_HSE) - /* Configue HSE as RTC clock soucre */ + /* Configure HSE as RTC clock source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c index 8e18d9744c..098acf9364 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c @@ -6,7 +6,7 @@ * * This file overrides the native HAL time base functions (defined as weak) * the TIM time base: - * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms + * + Initializes the TIM peripheral generate a Period elapsed Event each 1ms * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms * ****************************************************************************** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c index 36b7317a61..33a5f002c8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c @@ -420,6 +420,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -489,6 +490,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -569,6 +571,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -652,6 +655,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -694,6 +698,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Process Unlock */ __HAL_UNLOCK(huart); @@ -735,6 +740,8 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Register a User UART Callback * To be used instead of the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), + * HAL_MultiProcessor_Init() to register callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -763,8 +770,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_READY) { @@ -849,15 +854,15 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } /** * @brief Unregister an UART Callback * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() to un-register callbacks for HAL_UART_MSPINIT_CB_ID + * and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -877,9 +882,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - if (HAL_UART_STATE_READY == huart->gState) { switch (CallbackID) @@ -963,9 +965,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -1147,9 +1146,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; @@ -1171,13 +1167,12 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD pdata16bits = NULL; } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1195,6 +1190,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } @@ -1235,9 +1232,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1260,14 +1254,13 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - /* Check the remain data to be received */ while (huart->RxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { + huart->RxState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1322,9 +1315,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1332,9 +1322,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - /* Enable the UART Transmit data register empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); @@ -1367,9 +1354,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1404,9 +1388,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1433,9 +1414,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); - /* Process Unlocked */ - __HAL_UNLOCK(huart); - /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -1470,9 +1448,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1494,9 +1469,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { uint32_t dmarequest = 0x00U; - /* Process Locked */ - __HAL_LOCK(huart); - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) { @@ -1515,9 +1487,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -1529,8 +1498,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - /* Process Locked */ - __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_BUSY_TX) { @@ -1554,9 +1521,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -1636,11 +1600,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -1660,8 +1623,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* Initialize output number of received elements */ *RxLen = 0U; @@ -1678,6 +1639,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p /* If Set, and data has already been received, this means Idle Event is valid : End reception */ if (*RxLen > 0U) { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; huart->RxState = HAL_UART_STATE_READY; return HAL_OK; @@ -1760,10 +1722,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_IT(huart, pData, Size); @@ -1821,10 +1782,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_DMA(huart, pData, Size); @@ -1854,6 +1814,36 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ } } +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (returned value will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return(huart->RxEventType); +} + /** * @brief Abort ongoing transfers (blocking mode). * @param huart UART handle. @@ -2526,6 +2516,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); @@ -2556,6 +2551,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); @@ -2791,6 +2791,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RWU); huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -2818,6 +2819,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -2923,7 +2925,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) * the configuration information for the specified UART module. * @retval HAL state */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { uint32_t temp1 = 0x00U, temp2 = 0x00U; temp1 = huart->gState; @@ -2938,7 +2940,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval UART Error Code */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { return huart->ErrorCode; } @@ -3040,6 +3042,7 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) { @@ -3063,6 +3066,10 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } } + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3098,6 +3105,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3180,19 +3191,31 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; + } - /* Process Unlocked */ - __HAL_UNLOCK(huart); + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_OREFLAG(huart); - return HAL_TIMEOUT; + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } } } } @@ -3219,9 +3242,6 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - if (huart->Init.Parity != UART_PARITY_NONE) { /* Enable the UART Parity Error Interrupt */ @@ -3277,9 +3297,6 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); - /* Process Unlocked */ - __HAL_UNLOCK(huart); - if (huart->Init.Parity != UART_PARITY_NONE) { /* Enable the UART Parity Error Interrupt */ @@ -3619,6 +3636,9 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c index 945a646959..50c1b817dc 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c @@ -427,6 +427,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) /** * @brief Register a User USART Callback * To be used instead of the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -454,8 +456,6 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(husart); if (husart->State == HAL_USART_STATE_READY) { @@ -536,15 +536,14 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } /** * @brief Unregister an USART Callback * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -563,9 +562,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(husart); - if (husart->State == HAL_USART_STATE_READY) { switch (CallbackID) @@ -645,9 +641,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -2075,7 +2068,7 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) * the configuration information for the specified USART module. * @retval HAL state */ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) { return husart->State; } @@ -2086,11 +2079,14 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART Error Code */ -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) { return husart->ErrorCode; } +/** + * @} + */ /** * @} */ @@ -2819,10 +2815,6 @@ static void USART_SetConfig(USART_HandleTypeDef *husart) } } -/** - * @} - */ - /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c index 2d6e082864..cdb750fe6f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c @@ -22,9 +22,9 @@ #include "stm32f4xx_ll_bus.h" #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32F4xx_LL_Driver @@ -326,7 +326,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni #if defined(ADC_MULTIMODE_SUPPORT) assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); @@ -338,7 +338,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* On this STM32 series, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ - if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - common to several ADC */ @@ -350,16 +350,16 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* - Set ADC multimode DMA transfer */ /* - Set ADC multimode: delay between 2 sampling phases */ #if defined(ADC_MULTIMODE_SUPPORT) - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_ADCPRE + ADC_CCR_ADCPRE | ADC_CCR_MULTI | ADC_CCR_DMA | ADC_CCR_DDS | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | ADC_CommonInitStruct->Multimode | ADC_CommonInitStruct->MultiDMATransfer | ADC_CommonInitStruct->MultiTwoSamplingDelay @@ -368,13 +368,13 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni else { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_ADCPRE + ADC_CCR_ADCPRE | ADC_CCR_MULTI | ADC_CCR_DMA | ADC_CCR_DDS | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT ); } @@ -408,7 +408,7 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) #if defined(ADC_MULTIMODE_SUPPORT) /* Set fields of ADC multimode */ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; - ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; + ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; #endif /* ADC_MULTIMODE_SUPPORT */ } @@ -431,7 +431,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) assert_param(IS_ADC_ALL_INSTANCE(ADCx)); /* Disable ADC instance if not already disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 1UL) + if (LL_ADC_IsEnabled(ADCx) == 1UL) { /* Set ADC group regular trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ @@ -449,48 +449,48 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Check whether ADC state is compliant with expected state */ /* (hardware requirements of bits state to reset registers below) */ - if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL) + if (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL) { /* ========== Reset ADC registers ========== */ /* Reset register SR */ CLEAR_BIT(ADCx->SR, - ( LL_ADC_FLAG_STRT + (LL_ADC_FLAG_STRT | LL_ADC_FLAG_JSTRT | LL_ADC_FLAG_EOCS | LL_ADC_FLAG_OVR | LL_ADC_FLAG_JEOS - | LL_ADC_FLAG_AWD1 ) + | LL_ADC_FLAG_AWD1) ); /* Reset register CR1 */ CLEAR_BIT(ADCx->CR1, - ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN + (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE - | ADC_CR1_AWDCH ) + | ADC_CR1_AWDCH) ); /* Reset register CR2 */ CLEAR_BIT(ADCx->CR2, - ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL + (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DMA - | ADC_CR2_CONT | ADC_CR2_ADON ) + | ADC_CR2_CONT | ADC_CR2_ADON) ); /* Reset register SMPR1 */ CLEAR_BIT(ADCx->SMPR1, - ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 + (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) ); /* Reset register SMPR2 */ CLEAR_BIT(ADCx->SMPR2, - ( ADC_SMPR2_SMP9 + (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) @@ -512,28 +512,28 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset register SQR1 */ CLEAR_BIT(ADCx->SQR1, - ( ADC_SQR1_L + (ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) ); /* Reset register SQR2 */ CLEAR_BIT(ADCx->SQR2, - ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 + (ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) ); /* Reset register SQR3 */ CLEAR_BIT(ADCx->SQR3, - ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 + (ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) ); /* Reset register JSQR */ CLEAR_BIT(ADCx->JSQR, - ( ADC_JSQR_JL + (ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 - | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) + | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) ); /* Reset register DR */ @@ -595,24 +595,24 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC instance */ /* - Set ADC data resolution */ /* - Set ADC conversion data alignment */ MODIFY_REG(ADCx->CR1, - ADC_CR1_RES + ADC_CR1_RES | ADC_CR1_SCAN - , - ADC_InitStruct->Resolution + , + ADC_InitStruct->Resolution | ADC_InitStruct->SequencersScanMode ); MODIFY_REG(ADCx->CR2, - ADC_CR2_ALIGN - , - ADC_InitStruct->DataAlignment + ADC_CR2_ALIGN + , + ADC_InitStruct->DataAlignment ); } @@ -685,7 +685,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); } @@ -699,7 +699,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group regular */ @@ -712,33 +712,33 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* Note: On this STM32 series, ADC trigger edge is set when starting */ /* ADC conversion. */ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CR1, - ADC_CR1_DISCEN + ADC_CR1_DISCEN | ADC_CR1_DISCNUM - , - ADC_REG_InitStruct->SequencerDiscont + , + ADC_REG_InitStruct->SequencerDiscont ); } else { MODIFY_REG(ADCx->CR1, - ADC_CR1_DISCEN + ADC_CR1_DISCEN | ADC_CR1_DISCNUM - , - LL_ADC_REG_SEQ_DISCONT_DISABLE + , + LL_ADC_REG_SEQ_DISCONT_DISABLE ); } MODIFY_REG(ADCx->CR2, - ADC_CR2_EXTSEL + ADC_CR2_EXTSEL | ADC_CR2_EXTEN | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS - , - (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) + , + (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DMATransfer ); @@ -820,7 +820,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); } @@ -828,7 +828,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group injected */ @@ -840,32 +840,32 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* Note: On this STM32 series, ADC trigger edge is set when starting */ /* ADC conversion. */ /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CR1, - ADC_CR1_JDISCEN + ADC_CR1_JDISCEN | ADC_CR1_JAUTO - , - ADC_INJ_InitStruct->SequencerDiscont + , + ADC_INJ_InitStruct->SequencerDiscont | ADC_INJ_InitStruct->TrigAuto ); } else { MODIFY_REG(ADCx->CR1, - ADC_CR1_JDISCEN + ADC_CR1_JDISCEN | ADC_CR1_JAUTO - , - LL_ADC_REG_SEQ_DISCONT_DISABLE + , + LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_INJ_InitStruct->TrigAuto ); } MODIFY_REG(ADCx->CR2, - ADC_CR2_JEXTSEL + ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN - , - (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) + , + (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) ); /* Note: Hardware constraint (refer to description of this function): */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c index 113879301f..b64b4761ba 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c @@ -59,7 +59,7 @@ * - SUCCESS: CRC registers are de-initialized * - ERROR: CRC registers are not de-initialized */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c index 4514d9186f..77ce3587c7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c @@ -47,19 +47,16 @@ */ #if defined(DAC_CHANNEL2_SUPPORT) #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ - ( \ - ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ ) #else #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ - ( \ - ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ - ) + (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)) #endif /* DAC_CHANNEL2_SUPPORT */ #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ - ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ @@ -70,45 +67,45 @@ ) #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ - ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ ) #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ ) \ ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ ) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ - ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ - || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + (((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ ) /** @@ -135,7 +132,7 @@ * - SUCCESS: DAC registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) +ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx) { /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); @@ -170,14 +167,14 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: DAC registers are initialized * - ERROR: DAC registers are not initialized */ -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct) { ErrorStatus status = SUCCESS; @@ -277,4 +274,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c index 1bdf9dea7a..2431213940 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c @@ -61,7 +61,8 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ -#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) +#if defined(HAL_NOR_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\ + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -1449,7 +1450,7 @@ HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or * FMC_SDRAM_POWER_DOWN_MODE. */ -uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank) { uint32_t tmpreg; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c index 04966ea018..94718b7b24 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c @@ -46,22 +46,22 @@ */ #define IS_LL_FMPI2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_FMPI2C_MODE_I2C) || \ - ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_HOST) || \ - ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE) || \ - ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE_ARP)) + ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_HOST) || \ + ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE) || \ + ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE_ARP)) #define IS_LL_FMPI2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_FMPI2C_ANALOGFILTER_ENABLE) || \ - ((__VALUE__) == LL_FMPI2C_ANALOGFILTER_DISABLE)) + ((__VALUE__) == LL_FMPI2C_ANALOGFILTER_DISABLE)) #define IS_LL_FMPI2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) #define IS_LL_FMPI2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) #define IS_LL_FMPI2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_FMPI2C_ACK) || \ - ((__VALUE__) == LL_FMPI2C_NACK)) + ((__VALUE__) == LL_FMPI2C_NACK)) #define IS_LL_FMPI2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_FMPI2C_OWNADDRESS1_7BIT) || \ - ((__VALUE__) == LL_FMPI2C_OWNADDRESS1_10BIT)) + ((__VALUE__) == LL_FMPI2C_OWNADDRESS1_10BIT)) /** * @} */ @@ -84,7 +84,7 @@ * - SUCCESS: FMPI2C registers are de-initialized * - ERROR: FMPI2C registers are not de-initialized */ -ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx) +ErrorStatus LL_FMPI2C_DeInit(const FMPI2C_TypeDef *FMPI2Cx) { ErrorStatus status = SUCCESS; @@ -115,7 +115,7 @@ ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx) * - SUCCESS: FMPI2C registers are initialized * - ERROR: Not applicable */ -ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct) +ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, const LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct) { /* Check the FMPI2C Instance FMPI2Cx */ assert_param(IS_FMPI2C_ALL_INSTANCE(FMPI2Cx)); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c index 8172871fa6..ff79111818 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c @@ -59,7 +59,8 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ -#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \ + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FSMC_LL FSMC Low Layer * @brief FSMC driver modules diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c index 9336b5ca82..bb75125d06 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c @@ -92,7 +92,7 @@ * - SUCCESS: LPTIMx registers are de-initialized * - ERROR: invalid LPTIMx instance */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx) +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx) { ErrorStatus result = SUCCESS; @@ -137,7 +137,7 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) * - SUCCESS: LPTIMx instance has been initialized * - ERROR: LPTIMx instance hasn't been initialized */ -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { ErrorStatus result = SUCCESS; /* Check the parameters */ @@ -259,8 +259,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c index 333d63ca45..fc1ea50baa 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c @@ -59,7 +59,7 @@ * - SUCCESS: RNG registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) { ErrorStatus status = SUCCESS; @@ -77,7 +77,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) /* Enable RNG reset state */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); - /* Release RNG from reset state */ + /* Release RNG from reset state */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); #endif /* !RCC_AHB2_SUPPORT */ } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c index f3ee3ce016..4d106da398 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c index b272b62d95..49217db9fd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c @@ -137,14 +137,14 @@ /** @defgroup TIM_LL_Private_Functions TIM Private Functions * @{ */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); /** * @} */ @@ -165,7 +165,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: invalid TIMx instance */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) { ErrorStatus result = SUCCESS; @@ -301,7 +301,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) { uint32_t tmpcr1; @@ -380,7 +380,7 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) { ErrorStatus result = ERROR; @@ -435,7 +435,7 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) { ErrorStatus result = ERROR; @@ -489,7 +489,7 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -582,7 +582,7 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { uint32_t tmpcr2; uint32_t tmpccmr1; @@ -687,7 +687,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { uint32_t tmpbdtr = 0; @@ -711,7 +711,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); /* Set TIMx_BDTR */ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); @@ -738,7 +737,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -749,8 +748,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -778,8 +775,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -817,7 +816,7 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -828,8 +827,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -857,8 +854,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -896,7 +895,7 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -907,8 +906,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -936,8 +933,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -975,7 +974,7 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -986,8 +985,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1015,7 +1012,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the Output Idle state */ @@ -1037,7 +1033,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni return SUCCESS; } - /** * @brief Configure the TIMx input channel 1. * @param TIMx Timer Instance @@ -1046,7 +1041,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); @@ -1079,7 +1074,7 @@ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); @@ -1112,7 +1107,7 @@ static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); @@ -1145,7 +1140,7 @@ static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); @@ -1162,7 +1157,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c index 3cf68e363c..5b1ffa838e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c @@ -121,7 +121,7 @@ * - SUCCESS: USART registers are de-initialized * - ERROR: USART registers are not de-initialized */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) { ErrorStatus status = SUCCESS; @@ -245,7 +245,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * - SUCCESS: USART registers are initialized according to USART_InitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; @@ -409,7 +409,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c index 1df5fcf1b6..2570d422b8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -27,7 +27,7 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + (#) Fill parameters of Init structure in USB_CfgTypeDef structure. (#) Call USB_CoreInit() API to initialize the USB Core peripheral. @@ -258,9 +258,9 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy do { - HAL_Delay(1U); - ms++; - } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); } else if (mode == USB_DEVICE_MODE) { @@ -268,16 +268,16 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy do { - HAL_Delay(1U); - ms++; - } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); } else { return HAL_ERROR; } - if (ms == 50U) + if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) { return HAL_ERROR; } @@ -304,7 +304,9 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf USBx->DIEPTXF[i] = 0U; } -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) { @@ -341,14 +343,13 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; } -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; - /* Device mode configuration */ - USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - if (cfg.phy_itface == USB_OTG_ULPI_PHY) { if (cfg.speed == USBD_HS_SPEED) @@ -478,7 +479,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -492,7 +493,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -515,7 +516,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -529,7 +530,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -549,7 +550,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -565,7 +566,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t speed; @@ -594,7 +595,7 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -632,7 +633,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -671,7 +672,7 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -718,7 +719,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -785,8 +786,21 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & + (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); @@ -856,18 +870,34 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - if (ep->xfer_len == 0U) + if (epnum == 0U) { - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); } else { - pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); - ep->xfer_size = ep->maxpacket * pktcnt; + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + } } if (dma == 1U) @@ -896,106 +926,6 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef return HAL_OK; } -/** - * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - /* IN endpoint */ - if (ep->is_in == 1U) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0U) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - } - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - } - - if (dma == 1U) - { - if ((uint32_t)ep->dma_addr != 0U) - { - USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - } - else - { - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0U) - { - USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); - } - } - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len > 0U) - { - ep->xfer_len = ep->maxpacket; - } - - /* Store transfer size, for EP0 this is equal to endpoint max packet size */ - ep->xfer_size = ep->maxpacket; - - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); - - if (dma == 1U) - { - if ((uint32_t)ep->xfer_buff != 0U) - { - USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); - } - } - - /* EP enable */ - USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - - return HAL_OK; -} - /** * @brief USB_EPStoptXfer Stop transfer on an EP @@ -1003,7 +933,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { __IO uint32_t count = 0U; HAL_StatusTypeDef ret = HAL_OK; @@ -1067,7 +997,7 @@ HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * 1 : DMA feature used * @retval HAL status */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1098,7 +1028,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, * @param len Number of bytes to read * @retval pointer to destination buffer */ -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t *pDest = dest; @@ -1140,7 +1070,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -1171,7 +1101,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -1241,7 +1171,7 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to 255 * @retval HAL status */ -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1256,7 +1186,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t addres * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1273,7 +1203,7 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1288,9 +1218,9 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Global Interrupt status */ -uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { uint32_t tmpreg; @@ -1300,12 +1230,29 @@ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) return tmpreg; } +/** + * @brief USB_ReadChInterrupts: return USB channel interrupt status + * @param USBx Selected device + * @param chnum Channel number + * @retval USB Channel Interrupt status + */ +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_HC(chnum)->HCINT; + tmpreg &= USBx_HC(chnum)->HCINTMSK; + + return tmpreg; +} + /** * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Device OUT EP interrupt status */ -uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1319,9 +1266,9 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Device IN EP interrupt status */ -uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1339,7 +1286,7 @@ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ -uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1357,7 +1304,7 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ -uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1380,7 +1327,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) */ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) { - USBx->GINTSTS |= interrupt; + USBx->GINTSTS &= interrupt; } /** @@ -1391,7 +1338,7 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * 0 : Host * 1 : Device */ -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { return ((USBx->GINTSTS) & 0x1U); } @@ -1401,7 +1348,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1423,10 +1370,10 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) * @param psetup pointer to setup packet * @retval HAL status */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); if (gSNPSiD > USB_OTG_CORE_ID_300A) { @@ -1465,7 +1412,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -1479,7 +1426,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -1505,7 +1452,9 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) /* Disable HW VBUS sensing */ USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); #else @@ -1516,13 +1465,17 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \ + || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /* Disable Battery chargin detector */ USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); -#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ - if ((USBx->CID & (0x1U << 8)) != 0U) + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) { if (cfg.speed == USBH_FSLS_SPEED) { @@ -1555,7 +1508,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Clear all pending HC Interrupts */ for (i = 0U; i < cfg.Host_channels; i++) { - USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; USBx_HC(i)->HCINTMSK = 0U; } @@ -1563,9 +1516,9 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GINTMSK = 0U; /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFFU; - - if ((USBx->CID & (0x1U << 8)) != 0U) + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) { /* set Rx FIFO size */ USBx->GRXFSIZ = 0x200U; @@ -1573,6 +1526,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); } else +#endif /* defined (USB_OTG_HS) */ { /* set Rx FIFO size */ USBx->GRXFSIZ = 0x80U; @@ -1604,7 +1558,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1613,15 +1567,15 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) if (freq == HCFG_48_MHZ) { - USBx_HOST->HFIR = 48000U; + USBx_HOST->HFIR = HFIR_48_MHZ; } else if (freq == HCFG_6_MHZ) { - USBx_HOST->HFIR = 6000U; + USBx_HOST->HFIR = HFIR_6_MHZ; } else { - /* ... */ + return HAL_ERROR; } return HAL_OK; @@ -1634,7 +1588,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) * @note (1)The application must wait at least 10 ms * before clearing the reset bit. */ -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1661,7 +1615,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) * 1 : Activate VBUS * @retval HAL status */ -HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) { uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0 = 0U; @@ -1691,7 +1645,7 @@ HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) * @arg HCD_SPEED_FULL: Full speed mode * @arg HCD_SPEED_LOW: Low speed mode */ -uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0 = 0U; @@ -1705,7 +1659,7 @@ uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval current frame number */ -uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1747,7 +1701,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint32_t HostCoreSpeed; /* Clear old interrupt conditions for this host channel. */ - USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; /* Enable channel interrupts required for this transfer. */ switch (ep_type) @@ -1767,11 +1721,13 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, } else { - if ((USBx->CID & (0x1U << 8)) != 0U) +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) { USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM; } +#endif /* defined (USB_OTG_HS) */ } break; @@ -1808,6 +1764,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, break; } + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + /* Enable host channel Halt interrupt */ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; @@ -1842,7 +1801,8 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | - ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | + USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) { @@ -1870,53 +1830,118 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe uint8_t is_oddframe; uint16_t len_words; uint16_t num_packets; - uint16_t max_hc_pkt_count = 256U; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; - if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) { - /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ - if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK))) + /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ + if (dma == 1U) { - USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | - USB_OTG_HCINTMSK_ACKM | - USB_OTG_HCINTMSK_NAKM); - } + if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) + { - if ((dma == 0U) && (hc->do_ping == 1U)) + USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NAKM); + } + } + else { - (void)USB_DoPing(USBx, hc->ch_num); - return HAL_OK; + if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U)) + { + (void)USB_DoPing(USBx, hc->ch_num); + return HAL_OK; + } } - } +#endif /* defined (USB_OTG_HS) */ - /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0U) + if (hc->do_ssplit == 1U) { - num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + /* Set number of packet to 1 for Split transaction */ + num_packets = 1U; - if (num_packets > max_hc_pkt_count) + if (hc->ep_is_in != 0U) { - num_packets = max_hc_pkt_count; hc->XferSize = (uint32_t)num_packets * hc->max_packet; } - } - else - { - num_packets = 1U; - } + else + { + if (hc->ep_type == EP_TYPE_ISOC) + { + if (hc->xfer_len > ISO_SPLT_MPS) + { + /* Isochrone Max Packet Size for Split mode */ + hc->XferSize = hc->max_packet; + hc->xfer_len = hc->XferSize; - /* - * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of - * max_packet size. - */ - if (hc->ep_is_in != 0U) - { - hc->XferSize = (uint32_t)num_packets * hc->max_packet; + if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_MIDDLE; + } + else + { + hc->iso_splt_xactPos = HCSPLT_BEGIN; + } + } + else + { + hc->XferSize = hc->xfer_len; + + if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_FULL; + } + else + { + hc->iso_splt_xactPos = HCSPLT_END; + } + } + } + else + { + if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + } } else { - hc->XferSize = hc->xfer_len; + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } } /* Initialize the HCTSIZn register */ @@ -1934,6 +1959,65 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + if (hc->do_ssplit == 1U) + { + /* Set Hub start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) | + (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN; + + /* unmask ack & nyet for IN/OUT transactions */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NYET); + + if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + } + + if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && + (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + } + + /* Position management for iso out transaction on split mode */ + if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) + { + /* Set data payload position */ + switch (hc->iso_splt_xactPos) + { + case HCSPLT_BEGIN: + /* First data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1; + break; + + case HCSPLT_MIDDLE: + /* Middle data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos; + break; + + case HCSPLT_END: + /* End data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0; + break; + + case HCSPLT_FULL: + /* Entire data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS; + break; + + default: + break; + } + } + } + else + { + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + } + /* Set host channel enable */ tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; @@ -1955,7 +2039,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe return HAL_OK; } - if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) { switch (hc->ep_type) { @@ -2001,7 +2085,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe * @param USBx Selected device * @retval HAL state */ -uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2015,16 +2099,21 @@ uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t hcnum = (uint32_t)hc_num; __IO uint32_t count = 0U; uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; + + /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. + At the end of the next uframe/frame (in the worst case), the core generates a channel halted + and disables the channel automatically. */ - if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && - (ChannelEna == 0U)) + if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && + ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) { return HAL_OK; } @@ -2055,6 +2144,10 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } } else { @@ -2090,7 +2183,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t chnum = (uint32_t)ch_num; @@ -2166,8 +2259,8 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) } /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFFU; - USBx->GINTSTS = 0xFFFFFFFFU; + USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; (void)USB_EnableGlobalInt(USBx); @@ -2179,7 +2272,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2197,7 +2290,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2208,7 +2301,6 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) } #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - /** * @} */ diff --git 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system/Drivers/STM32F4xx_HAL_Driver/_htmresc/mini-st.css rename to system/Drivers/STM32F4xx_HAL_Driver/_htmresc/mini-st_2020.css index 3caf11c32e..db8b406aa4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/_htmresc/mini-st.css +++ b/system/Drivers/STM32F4xx_HAL_Driver/_htmresc/mini-st_2020.css @@ -1,39 +1,39 @@ @charset "UTF-8"; /* - Flavor name: Default (mini-default) - Author: Angelos Chalaris (chalarangelo@gmail.com) - Maintainers: Angelos Chalaris - mini.css version: v3.0.0-alpha.3 + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 */ /* Browsers resets and base typography. */ /* Core module CSS variable definitions */ :root { - --fore-color: #111; - --secondary-fore-color: #444; - --back-color: #f8f8f8; - --secondary-back-color: #f0f0f0; - --blockquote-color: #f57c00; - --pre-color: #1565c0; - --border-color: #aaa; - --secondary-border-color: #ddd; - --heading-ratio: 1.19; + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; --universal-margin: 0.5rem; - --universal-padding: 0.125rem; - --universal-border-radius: 0.125rem; - --a-link-color: #0277bd; - --a-visited-color: #01579b; } + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } html { - font-size: 14px; } + font-size: 13.5px; } a, b, del, em, i, ins, q, span, strong, u { font-size: 1em; } html, * { - font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; - line-height: 1.4; + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; -webkit-text-size-adjust: 100%; } * { @@ -42,7 +42,10 @@ html, * { body { margin: 0; color: var(--fore-color); - background: var(--back-color); } + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } details { display: block; } @@ -62,9 +65,9 @@ img { height: auto; } h1, h2, h3, h4, h5, h6 { - line-height: 1.2; + line-height: 1.25; margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - font-weight: 500; } + font-weight: 400; } h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { color: var(--secondary-fore-color); display: block; @@ -74,21 +77,15 @@ h1 { font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } h2 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); - background: var(--mark-back-color); - font-weight: 600; - padding: 0.1em 0.5em 0.2em 0.5em; - color: var(--mark-fore-color); } - + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } h3 { - font-size: calc(1rem * var(--heading-ratio)); - padding-left: calc(2 * var(--universal-margin)); - /* background: var(--border-color); */ - } + font-size: calc(1rem * var(--heading-ratio) ); } h4 { - font-size: 1rem;); - padding-left: calc(4 * var(--universal-margin)); } + font-size: calc(1rem * var(--heading-ratio)); } h5 { font-size: 1rem; } @@ -101,7 +98,7 @@ p { ol, ul { margin: var(--universal-margin); - padding-left: calc(6 * var(--universal-margin)); } + padding-left: calc(3 * var(--universal-margin)); } b, strong { font-weight: 700; } @@ -111,7 +108,7 @@ hr { border: 0; line-height: 1.25em; margin: var(--universal-margin); - height: 0.0625rem; + height: 0.0714285714rem; background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } blockquote { @@ -121,16 +118,16 @@ blockquote { color: var(--secondary-fore-color); margin: var(--universal-margin); padding: calc(3 * var(--universal-padding)); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.375rem solid var(--blockquote-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } blockquote:before { position: absolute; top: calc(0rem - var(--universal-padding)); left: 0; font-family: sans-serif; - font-size: 3rem; - font-weight: 700; + font-size: 2rem; + font-weight: 800; content: "\201c"; color: var(--blockquote-color); } blockquote[cite]:after { @@ -160,8 +157,8 @@ pre { background: var(--secondary-back-color); padding: calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.25rem solid var(--pre-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } sup, sub, code, kbd { @@ -204,7 +201,8 @@ a { box-sizing: border-box; display: flex; flex: 0 1 auto; - flex-flow: row wrap; } + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } .col-sm, [class^='col-sm-'], @@ -565,9 +563,9 @@ a { order: 999; } } /* Card component CSS variable definitions */ :root { - --card-back-color: #f8f8f8; - --card-fore-color: #111; - --card-border-color: #ddd; } + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } .card { display: flex; @@ -578,7 +576,7 @@ a { width: 100%; background: var(--card-back-color); color: var(--card-fore-color); - border: 0.0625rem solid var(--card-border-color); + border: 0.0714285714rem solid var(--card-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); overflow: hidden; } @@ -592,7 +590,7 @@ a { margin: 0; border: 0; border-radius: 0; - border-bottom: 0.0625rem solid var(--card-border-color); + border-bottom: 0.0714285714rem solid var(--card-border-color); padding: var(--universal-padding); width: 100%; } .card > .sectione.media { @@ -617,17 +615,18 @@ a { width: auto; } .card.warning { -/* --card-back-color: #ffca28; */ --card-back-color: #e5b8b7; - --card-border-color: #e8b825; } + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } .card.error { - --card-back-color: #b71c1c; - --card-fore-color: #f8f8f8; - --card-border-color: #a71a1a; } + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } .card > .sectione.dark { - --card-back-color: #e0e0e0; } + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } .card > .sectione.double-padded { padding: calc(1.5 * var(--universal-padding)); } @@ -637,12 +636,12 @@ a { */ /* Input_control module CSS variable definitions */ :root { - --form-back-color: #f0f0f0; - --form-fore-color: #111; - --form-border-color: #ddd; - --input-back-color: #f8f8f8; - --input-fore-color: #111; - --input-border-color: #ddd; + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; --input-focus-color: #0288d1; --input-invalid-color: #d32f2f; --button-back-color: #e2e2e2; @@ -655,13 +654,13 @@ a { form { background: var(--form-back-color); color: var(--form-fore-color); - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); padding: calc(2 * var(--universal-padding)) var(--universal-padding); } fieldset { - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 4); padding: var(--universal-padding); } @@ -671,7 +670,7 @@ legend { display: table; max-width: 100%; white-space: normal; - font-weight: 700; + font-weight: 500; padding: calc(var(--universal-padding) / 2); } label { @@ -716,7 +715,7 @@ input:not([type]), [type="text"], [type="email"], [type="number"], [type="search box-sizing: border-box; background: var(--input-back-color); color: var(--input-fore-color); - border: 0.0625rem solid var(--input-border-color); + border: 0.0714285714rem solid var(--input-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 2); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } @@ -763,8 +762,8 @@ option { [type="radio"]:checked:before { border-radius: 100%; content: ''; - top: calc(0.0625rem + var(--universal-padding) / 2); - left: calc(0.0625rem + var(--universal-padding) / 2); + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); background: var(--input-fore-color); width: 0.5rem; height: 0.5rem; } @@ -793,7 +792,7 @@ a[role="button"], label[role="button"], [role="button"] { display: inline-block; background: var(--button-back-color); color: var(--button-fore-color); - border: 0.0625rem solid var(--button-border-color); + border: 0.0714285714rem solid var(--button-border-color); border-radius: var(--universal-border-radius); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); @@ -814,7 +813,7 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d .button-group { display: flex; - border: 0.0625rem solid var(--button-group-border-color); + border: 0.0714285714rem solid var(--button-group-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { @@ -826,13 +825,13 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d border-radius: 0; box-shadow: none; } .button-group > :not(:first-child) { - border-left: 0.0625rem solid var(--button-group-border-color); } + border-left: 0.0714285714rem solid var(--button-group-border-color); } @media screen and (max-width: 499px) { .button-group { flex-direction: column; } .button-group > :not(:first-child) { border: 0; - border-top: 0.0625rem solid var(--button-group-border-color); } } + border-top: 0.0714285714rem solid var(--button-group-border-color); } } /* Custom elements for forms and input elements. @@ -874,29 +873,29 @@ button.large, [type="button"].large, [type="submit"].large, [type="reset"].large */ /* Navigation module CSS variable definitions */ :root { - --header-back-color: #f8f8f8; - --header-hover-back-color: #f0f0f0; - --header-fore-color: #444; - --header-border-color: #ddd; - --nav-back-color: #f8f8f8; - --nav-hover-back-color: #f0f0f0; - --nav-fore-color: #444; - --nav-border-color: #ddd; - --nav-link-color: #0277bd; - --footer-fore-color: #444; - --footer-back-color: #f8f8f8; - --footer-border-color: #ddd; - --footer-link-color: #0277bd; - --drawer-back-color: #f8f8f8; - --drawer-hover-back-color: #f0f0f0; - --drawer-border-color: #ddd; - --drawer-close-color: #444; } + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } header { - height: 3.1875rem; + height: 2.75rem; background: var(--header-back-color); color: var(--header-fore-color); - border-bottom: 0.0625rem solid var(--header-border-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); padding: calc(var(--universal-padding) / 4) 0; white-space: nowrap; overflow-x: auto; @@ -927,7 +926,7 @@ header { nav { background: var(--nav-back-color); color: var(--nav-fore-color); - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } nav * { @@ -946,10 +945,10 @@ nav { nav .sublink-1:before { position: absolute; left: calc(var(--universal-padding) - 1 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } nav .sublink-2 { position: relative; @@ -957,16 +956,16 @@ nav { nav .sublink-2:before { position: absolute; left: calc(var(--universal-padding) - 3 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } footer { background: var(--footer-back-color); color: var(--footer-fore-color); - border-top: 0.0625rem solid var(--footer-border-color); + border-top: 0.0714285714rem solid var(--footer-border-color); padding: calc(2 * var(--universal-padding)) var(--universal-padding); font-size: 0.875rem; } footer a, footer a:visited { @@ -1013,7 +1012,7 @@ footer.sticky { height: 100vh; overflow-y: auto; background: var(--drawer-back-color); - border: 0.0625rem solid var(--drawer-border-color); + border: 0.0714285714rem solid var(--drawer-border-color); border-radius: 0; margin: 0; z-index: 1110; @@ -1060,38 +1059,36 @@ footer.sticky { */ /* Table module CSS variable definitions. */ :root { - --table-border-color: #aaa; - --table-border-separator-color: #666; - --table-head-back-color: #e6e6e6; - --table-head-fore-color: #111; - --table-body-back-color: #f8f8f8; - --table-body-fore-color: #111; - --table-body-alt-back-color: #eee; } + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } table { border-collapse: separate; border-spacing: 0; - : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + margin: 0; display: flex; flex: 0 1 auto; flex-flow: row wrap; padding: var(--universal-padding); - padding-top: 0; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + padding-top: 0; } table caption { - font-size: 1.25 * rem; + font-size: 1rem; margin: calc(2 * var(--universal-margin)) 0; max-width: 100%; - flex: 0 0 100%; - text-align: left;} + flex: 0 0 100%; } table thead, table tbody { display: flex; flex-flow: row wrap; - border: 0.0625rem solid var(--table-border-color); } + border: 0.0714285714rem solid var(--table-border-color); } table thead { z-index: 999; border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; - border-bottom: 0.0625rem solid var(--table-border-separator-color); } + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } table tbody { border-top: 0; margin-top: calc(0 - var(--universal-margin)); @@ -1109,11 +1106,11 @@ table { table td { background: var(--table-body-back-color); color: var(--table-body-fore-color); - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table:not(.horizontal) { overflow: auto; - max-height: 850px; } + max-height: 100%; } table:not(.horizontal) thead, table:not(.horizontal) tbody { max-width: 100%; flex: 0 0 100%; } @@ -1134,32 +1131,33 @@ table.horizontal { border: 0; } table.horizontal thead, table.horizontal tbody { border: 0; + flex: .2 0 0; flex-flow: row nowrap; } table.horizontal tbody { overflow: auto; justify-content: space-between; - flex: 1 0 0; - margin-left: calc( 4 * var(--universal-margin)); + flex: .8 0 0; + margin-left: 0; padding-bottom: calc(var(--universal-padding) / 4); } table.horizontal tr { flex-direction: column; flex: 1 0 auto; } table.horizontal th, table.horizontal td { - width: 100%; + width: auto; border: 0; - border-bottom: 0.0625rem solid var(--table-border-color); } + border-bottom: 0.0714285714rem solid var(--table-border-color); } table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { border-top: 0; } table.horizontal th { text-align: right; - border-left: 0.0625rem solid var(--table-border-color); - border-right: 0.0625rem solid var(--table-border-separator-color); } + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } table.horizontal thead tr:first-child { padding-left: 0; } table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td { - border-right: 0.0625rem solid var(--table-border-color); } + border-right: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td:first-child { border-top-right-radius: 0.25rem; } table.horizontal tbody tr:last-child td:last-child { @@ -1191,12 +1189,12 @@ table.horizontal { display: table-row-group; } table tr, table.horizontal tr { display: block; - border: 0.0625rem solid var(--table-border-color); + border: 0.0714285714rem solid var(--table-border-color); border-radius: var(--universal-border-radius); - background: #fafafa; + background: #ffffff; padding: var(--universal-padding); margin: var(--universal-margin); - margin-bottom: calc(2 * var(--universal-margin)); } + margin-bottom: calc(1 * var(--universal-margin)); } table th, table td, table.horizontal th, table.horizontal td { width: auto; } table td, table.horizontal td { @@ -1211,9 +1209,6 @@ table.horizontal { border-top: 0; } table tbody tr:last-child td, table.horizontal tbody tr:last-child td { border-right: 0; } } -:root { - --table-body-alt-back-color: #eee; } - table tr:nth-of-type(2n) > td { background: var(--table-body-alt-back-color); } @@ -1234,8 +1229,8 @@ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focu */ /* Contextual module CSS variable definitions */ :root { - --mark-back-color: #0277bd; - --mark-fore-color: #fafafa; } + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } mark { background: var(--mark-back-color); @@ -1243,11 +1238,11 @@ mark { font-size: 0.95em; line-height: 1em; border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } mark.inline-block { display: inline-block; font-size: 1em; - line-height: 1.5; + line-height: 1.4; padding: calc(var(--universal-padding) / 2) var(--universal-padding); } :root { @@ -1314,8 +1309,8 @@ mark { :root { --modal-overlay-color: rgba(0, 0, 0, 0.45); - --modal-close-color: #444; - --modal-close-hover-color: #f0f0f0; } + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } [type="checkbox"].modal { height: 1px; @@ -1368,13 +1363,14 @@ mark { z-index: 1211; } :root { - --collapse-label-back-color: #e8e8e8; - --collapse-label-fore-color: #212121; - --collapse-label-hover-back-color: #f0f0f0; - --collapse-selected-label-back-color: #ececec; - --collapse-border-color: #ddd; - --collapse-content-back-color: #fafafa; - --collapse-selected-label-border-color: #0277bd; } + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } .collapse { width: calc(100% - 2 * var(--universal-margin)); @@ -1395,13 +1391,13 @@ mark { .collapse > label { flex-grow: 1; display: inline-block; - height: 1.5rem; + height: 1.25rem; cursor: pointer; - transition: background 0.3s; + transition: background 0.2s; color: var(--collapse-label-fore-color); background: var(--collapse-label-back-color); - border: 0.0625rem solid var(--collapse-border-color); - padding: calc(1.5 * var(--universal-padding)); } + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } .collapse > label:hover, .collapse > label:focus { background: var(--collapse-label-hover-back-color); } .collapse > label + div { @@ -1418,7 +1414,7 @@ mark { max-height: 1px; } .collapse > :checked + label { background: var(--collapse-selected-label-back-color); - border-bottom-color: var(--collapse-selected-label-border-color); } + border-color: var(--collapse-selected-label-border-color); } .collapse > :checked + label + div { box-sizing: border-box; position: relative; @@ -1427,13 +1423,13 @@ mark { overflow: auto; margin: 0; background: var(--collapse-content-back-color); - border: 0.0625rem solid var(--collapse-border-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); border-top: 0; padding: var(--universal-padding); clip: auto; -webkit-clip-path: inset(0%); clip-path: inset(0%); - max-height: 850px; } + max-height: 100%; } .collapse > label:not(:first-of-type) { border-top: 0; } .collapse > label:first-of-type { @@ -1450,11 +1446,8 @@ mark { /* Custom elements for contextual background elements, toasts and tooltips. */ -mark.secondary { - --mark-back-color: #d32f2f; } - mark.tertiary { - --mark-back-color: #308732; } + --mark-back-color: #3cb4e6; } mark.tag { padding: calc(var(--universal-padding)/2) var(--universal-padding); @@ -1463,9 +1456,9 @@ mark.tag { /* Definitions for progress elements and spinners. */ -/* Progess module CSS variable definitions */ +/* Progress module CSS variable definitions */ :root { - --progress-back-color: #ddd; + --progress-back-color: #3cb4e6; --progress-fore-color: #555; } progress { @@ -1558,45 +1551,53 @@ span[class^='icon-'] { filter: invert(100%); } span.icon-alert { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } span.icon-bookmark { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-calendar { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-credit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-edit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } span.icon-link { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } span.icon-help { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } span.icon-home { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-info { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } span.icon-lock { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } span.icon-mail { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-location { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' 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16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-search { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } span.icon-settings { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-share { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } span.icon-cart { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } span.icon-upload { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } span.icon-user { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } /* Definitions for utilities and helper classes. @@ -1604,7 +1605,7 @@ span.icon-user { /* Utility module CSS variable definitions */ :root { --generic-border-color: rgba(0, 0, 0, 0.3); - --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } .hidden { display: none !important; } @@ -1622,7 +1623,7 @@ span.icon-user { overflow: hidden !important; } .bordered { - border: 0.0625rem solid var(--generic-border-color) !important; } + border: 0.0714285714rem solid var(--generic-border-color) !important; } .rounded { border-radius: var(--universal-border-radius) !important; } @@ -1697,4 +1698,14 @@ span.icon-user { clip-path: inset(100%) !important; overflow: hidden !important; } } -/*# sourceMappingURL=mini-default.css.map */ +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git 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zw7ER9v~DyrC*R$do9aEw5r@B)YzHOLB^-c9Eu9D!sFmI8^VljVKE89{zY_8PTSF+J b^}%0^qYmp2WD(pA|JtZ4>nPPKybJpu3@X?! literal 0 HcmV?d00001 diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 5abbc1daf2..4476fdd94e 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -5,7 +5,7 @@ * STM32F1: 1.1.9 * STM32F2: 1.2.8 * STM32F3: 1.5.7 - * STM32F4: 1.8.0 + * STM32F4: 1.8.2 * STM32F7: 1.3.0 * STM32G0: 1.4.4 * STM32G4: 1.2.2 From f79dbe152717a557b9b8d812e3ac6d29e8ce1c04 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 29 Nov 2023 09:41:02 +0100 Subject: [PATCH 2/2] system(F4): update STM32F4xx CMSIS Drivers to v2.6.9 Included in STM32CubeF4 FW v1.28.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32F4xx/Include/stm32f401xc.h | 24 +- .../Device/ST/STM32F4xx/Include/stm32f401xe.h | 24 +- .../Device/ST/STM32F4xx/Include/stm32f405xx.h | 32 +- .../Device/ST/STM32F4xx/Include/stm32f407xx.h | 37 +- .../Device/ST/STM32F4xx/Include/stm32f410cx.h | 34 +- .../Device/ST/STM32F4xx/Include/stm32f410rx.h | 34 +- .../Device/ST/STM32F4xx/Include/stm32f410tx.h | 32 +- .../Device/ST/STM32F4xx/Include/stm32f411xe.h | 26 +- .../Device/ST/STM32F4xx/Include/stm32f412cx.h | 34 +- .../Device/ST/STM32F4xx/Include/stm32f412rx.h | 40 +- .../Device/ST/STM32F4xx/Include/stm32f412vx.h | 40 +- .../Device/ST/STM32F4xx/Include/stm32f412zx.h | 40 +- .../Device/ST/STM32F4xx/Include/stm32f413xx.h | 62 +- .../Device/ST/STM32F4xx/Include/stm32f415xx.h | 36 +- .../Device/ST/STM32F4xx/Include/stm32f417xx.h | 41 +- .../Device/ST/STM32F4xx/Include/stm32f423xx.h | 62 +- .../Device/ST/STM32F4xx/Include/stm32f427xx.h | 53 +- .../Device/ST/STM32F4xx/Include/stm32f429xx.h | 57 +- .../Device/ST/STM32F4xx/Include/stm32f437xx.h | 57 +- .../Device/ST/STM32F4xx/Include/stm32f439xx.h | 61 +- .../Device/ST/STM32F4xx/Include/stm32f446xx.h | 56 +- .../Device/ST/STM32F4xx/Include/stm32f469xx.h | 61 +- .../Device/ST/STM32F4xx/Include/stm32f479xx.h | 65 +- .../Device/ST/STM32F4xx/Include/stm32f4xx.h | 116 +- .../ST/STM32F4xx/Include/system_stm32f4xx.h | 18 +- .../ST/STM32F4xx/{License.md => LICENSE.md} | 0 .../CMSIS/Device/ST/STM32F4xx/README.md | 11 +- .../Device/ST/STM32F4xx/Release_Notes.html | 2818 +++++------------ .../Templates/gcc/startup_stm32f401xc.s | 9 +- .../Templates/gcc/startup_stm32f401xe.s | 9 +- .../Templates/gcc/startup_stm32f405xx.s | 9 +- .../Templates/gcc/startup_stm32f407xx.s | 9 +- .../Templates/gcc/startup_stm32f410cx.s | 9 +- .../Templates/gcc/startup_stm32f410rx.s | 9 +- .../Templates/gcc/startup_stm32f410tx.s | 9 +- .../Templates/gcc/startup_stm32f411xe.s | 9 +- .../Templates/gcc/startup_stm32f412cx.s | 9 +- .../Templates/gcc/startup_stm32f412rx.s | 9 +- .../Templates/gcc/startup_stm32f412vx.s | 9 +- .../Templates/gcc/startup_stm32f412zx.s | 9 +- .../Templates/gcc/startup_stm32f413xx.s | 9 +- .../Templates/gcc/startup_stm32f415xx.s | 9 +- .../Templates/gcc/startup_stm32f417xx.s | 9 +- .../Templates/gcc/startup_stm32f423xx.s | 9 +- .../Templates/gcc/startup_stm32f427xx.s | 9 +- .../Templates/gcc/startup_stm32f429xx.s | 9 +- .../Templates/gcc/startup_stm32f437xx.s | 10 +- .../Templates/gcc/startup_stm32f439xx.s | 9 +- .../Templates/gcc/startup_stm32f446xx.s | 9 +- .../Templates/gcc/startup_stm32f469xx.s | 9 +- .../Templates/gcc/startup_stm32f479xx.s | 9 +- .../Device/ST/STM32F4xx/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../{mini-st.css => mini-st_2020.css} | 363 ++- .../Device/ST/STM32F4xx/_htmresc/st_logo.png | Bin 18616 -> 0 bytes .../ST/STM32F4xx/_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 56 files changed, 1731 insertions(+), 2813 deletions(-) rename system/Drivers/CMSIS/Device/ST/STM32F4xx/{License.md => LICENSE.md} (100%) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/favicon.png rename system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/{mini-st.css => mini-st_2020.css} (77%) delete mode 100644 system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/st_logo.png create mode 100644 system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/st_logo_2020.png diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h index f37c761409..bf0ee64bbc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - peripherals registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention @@ -34,7 +34,7 @@ #define __STM32F401xC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS @@ -64,7 +64,7 @@ */ typedef enum { -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ @@ -73,7 +73,7 @@ typedef enum DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ + /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ @@ -129,7 +129,7 @@ typedef enum I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ - SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ } IRQn_Type; /** @@ -203,7 +203,7 @@ typedef struct __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; +} DBGMCU_TypeDef; /** @@ -822,9 +822,9 @@ typedef struct * @} */ - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ @@ -1400,7 +1400,7 @@ typedef struct /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) -#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ @@ -3915,7 +3915,7 @@ typedef struct #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) */ #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */ @@ -4291,7 +4291,7 @@ typedef struct #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk /******************** Bit definition for RCC_AHB2ENR register ***************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) */ #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h index fdb6a532cb..de30bcc23d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - peripherals registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention @@ -34,7 +34,7 @@ #define __STM32F401xE_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS @@ -64,7 +64,7 @@ */ typedef enum { -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ @@ -73,7 +73,7 @@ typedef enum DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ + /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ @@ -129,7 +129,7 @@ typedef enum I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ - SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ } IRQn_Type; /** @@ -203,7 +203,7 @@ typedef struct __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; +} DBGMCU_TypeDef; /** @@ -822,9 +822,9 @@ typedef struct * @} */ - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ @@ -1400,7 +1400,7 @@ typedef struct /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) -#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ @@ -3915,7 +3915,7 @@ typedef struct #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) */ #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */ @@ -4291,7 +4291,7 @@ typedef struct #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk /******************** Bit definition for RCC_AHB2ENR register ***************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) */ #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h index febecd7ca9..246c80051d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - peripherals registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention @@ -34,7 +34,7 @@ #define __STM32F405xx_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS @@ -64,7 +64,7 @@ */ typedef enum { -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ @@ -73,7 +73,7 @@ typedef enum DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ + /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ @@ -314,7 +314,7 @@ typedef struct __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; +} DBGMCU_TypeDef; /** @@ -1052,9 +1052,9 @@ typedef struct * @} */ - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ @@ -1066,7 +1066,7 @@ typedef struct /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) */ #define ADC_MULTIMODE_SUPPORT /*! - - - - - - - Release Notes for STM32F4xx CMSIS - - - - - -
-


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Release - Notes for STM32F4xx CMSIS

-

Copyright - 2017 STMicroelectronics

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-

Update History

- -

V2.6.8 / 11-February-2022

- -     -   Main - - - Changes
- - - -
    - -
  • All source files: update disclaimer to add reference to the new license agreement.
    • - -
  • Correct ETH bits definitions to be in line with naming used in the STM32F4 reference manual documents.
    • -
-

V2.6.7 / 16-July-2021

- -     -   Main - - - Changes
- - -
    -
  • Add missing definition - FLASH_CR_ERRIE to the CMSIS header file.
    • - -
  • Remove unsupported “GPIOF_BASE” - and “GPIOG_BASE” defines from STM32F412Vx - device.
    • - -
  • Add new atomic register access - macros in stm32f4xx.h file.
    • - -
  • Add LSI maximum startup time - datasheet value: LSI_STARTUP_TIME.
    • - -
  • Fix a typo in CMSIS STM32F4xx - version macro (__STM32F4xx_CMSIS_VERSION).
    -
    • -
-

V2.6.6 / 12-February-2021

-     -   Main - - - Changes
- - -
    -
  • system_stm32f4xx.c:
    • -
      -
    • Protect -Vector - - - table modification following SRAM or - FLASH preprocessor directive by a - generic preprocessor directive : - USER_VECT_TAB_ADDRESS
      • -
    • Update - - - SystemInit_ExtMemCtl() API to initialize - the tmpreg variable before each time out - loop condition.
      -
      • -
    -
  • Add License.md and - Readme.md files required for GitHub - publication
    • -
  • Improve GCC startup - files robustness.
    • -
  • Fix wrong value for - GPIO_MODER_MODE8_Msk and - GPIO_MODER_MODE2_Pos.
    • -
  • Update max number of - host channels in FS for STM32F446:
    • -
      -
    • Update - - - USB_OTG_FS_HOST_MAX_CHANNEL_NBR value - from 8 to 12.
      • -
    -
  • Add SMBDEN and SMBHEN - bit definition for STM32F410Tx device.
    -
    • -
-

V2.6.5 / 10-February-2020

-     -   Main - - - Changes
- - -
    -
  • All header files
    • -
      -
    • Update - - - to use new BSD License format
      -
      • -
    -
  • MDK-ARM startup files
    • -
      -
    • Update - - - to fix invalid config wizard annotations
      • -
    -
-

V2.6.4 / 06-December-2019

-     -   Main - - - Changes
- - -
    -
  • stm32f446xx.h file
    • -
      -
    • Update - - - to support HW flow control on UART4 and - UART5 instances
      • -
    -
  • stm32f412xx.h, stm32f413xx.h and stm32f423xx.h files
    • -
      -
    • Remove - - - unused IS_USB_ALL_INSTANCE() assert macro
      • -
    -
  • All header files
    • -
      -
    • Remove - - - unused IS_TIM_SYNCHRO_INSTANCE() assert - macro
      • -
    -
  • system_stm32f4xx.c file
    • -
      -
    • Update - - - SystemInit() API to don't reset RCC - registers to its reset values
      -
      • -
    -
-

V2.6.3 / 08-February-2019

-     -   Main - - - Changes
- - -
    -
  • CRYP:
    • -
      -
    • Update CMSIS - devices with correct CRYP data input - register name: DIN instead of DR
      • -
    • Add Bits - definition for CRYP CR ALGOMODE AES - GCM/CCM
      • -
    -
  • HASH:
    • -
      -
    • Update - HASH_DIGEST_TypeDef structure: resize - the HR register
      -
      • -
    • Remove MDMAT Bits - definition
      • -
    -
  • TIM:
    • -
      -
    • Add requires TIM - assert macros:
      • -
        -
      • IS_TIM_SYNCHRO_INSTANCE()
        • -
      • IS_TIM_CLOCKSOURCE_TIX_INSTANCE()
        • -
      • IS_TIM_CLOCKSOURCE_ITRX_INSTANCE()
        • -
      -
    -
  • RCC
    • -
      -
    • Add - - - RCC_CSR_BORRSTF bits definition
      • -
    -
  • GPIO
    -
    • -
      -
    • Fix - - - GPIO BRR bits definition
      • -
    • Adjust - - - the GPIO present on STM32F412 devices
      -
      • -
    -
  • SAI
    • -
      -
    • Fix - - - frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits - description
      -
      • -
    -
  • USB:
    • -
      -
    • Add - - - missing Bits Definitions in - USB_OTG_DOEPMSK register
      • -
    -
      -
        -
      • USB_OTG_DOEPMSK_AHBERRM
        • -
      • USB_OTG_DOEPMSK_OTEPSPRM
        • -
      • USB_OTG_DOEPMSK_BERRM
        • -
      • USB_OTG_DOEPMSK_NAKM
        • -
      • USB_OTG_DOEPMSK_NYETM
        • -
      -
    -
      -
    • Add - - - missing Bits Definitions in - USB_OTG_DIEPINT register
      • -
    -
      -
        -
      • USB_OTG_DIEPINT_INEPNM
        • -
      • USB_OTG_DIEPINT_AHBERR
        • -
      • USB_OTG_DOEPINT_OUTPKTERR
        • -
      •  USB_OTG_DOEPINT_NAK
        • -
      • USB_OTG_DOEPINT_STPKTRX
        • -
      -
    • Add - - - missing Bits Definitions in USB_OTG_DCFG - register
      • -
        -
      • USB_OTG_DCFG_XCVRDLY
        • -
      • USB_OTG_DCFG_ERRATIM
        • -
      -
    -
      -
    • Update - - - USB OTG max number of endpoints (6 FS - and 9 HS instead of 5 and 8)
      • -
    -
  • I2C/FMPI2C
    • -
      -
    • Align - - - Bit naming for FMPI2C_CR1 register: - FMPI2C_CR1_DFN--> FMPI2C_CR1_DNF
      • -
    • Add - - - IS_SMBUS_ALL_INSTANCE() - - - define
      • -
    -
  • DFSDM
    • -
      -
    • Align - - - Bit naming for DFSDM_FLTICR register: - DFSDM_FLTICR_CLRSCSDF--> - DFSDM_FLTICR_CLRSCDF
      • -
    -
  • PWR
    • -
      -
    • Remove PWR_CSR_WUPP - define: feature not available on - STM32F469xx/479xx devices
      • -
    -
-

V2.6.2 / 06-October-2017

-     -   Main - - - Changes
- - -
    -
      -
    • Remove Date and - Version from all header files
      • -
    • USB_OTG - - - register clean up: remove - duplicated bits definitions
      • -
    • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
      • -
        -
      • Remove - - - BKPSRAM_BASE define: feature not - available
        • -
      -
    • stm32f405xx.h, stm32f407xx.h files
      • -
        -
      • Rename - - - HASH_RNG_IRQn to RNG_IRQn: HASH - instance not available 
        • -
      -
    • stm32f410xx.h, stm32f412xx.h, stm32f413xx.h,  stm32f423xx.h files
      • -
        -
      • Add - - - missing wake-up pins defines
        • -
      -
    • stm32f412cx.h files
      • -
        -
      •  Add - support of USART3 instance
        • -
      -
    -
-

V2.6.1 / 14-February-2017

-     -   Main - - - Changes
- - -
    -
  • General updates in - header files to support LL drivers
    • -
      -
    • Align - - - Bit naming for RCC_CSR - register (ex: RCC_CSR_PADRSTF - --> RCC_CSR_PINRSTF)
      • -
    • Add - - - new defines for RCC features support:
      • -
        -
      • RCC - - - PLLI2S and RCC PLLSAI support
        • -
      • RCC - - - PLLR I2S clock source and RCC PLLR - system clock support
        • -
      • RCC - - - SAI1A PLL source and RCC SAI1B PLL - source support
        • -
      • RCC - - - AHB2 support
        -
        • -
      -
    • Add - - - RCC_DCKCFGR_PLLI2SDIVQ_X - and  RCC_DCKCFGR_PLLSAIDIVQ_X - bits definition
      • -
    • Add new defines for - RCC_PLLI2SCFGR_RST_VALUE, - RCC_PLLSAICFGR_RST_VALUE and - RCC_PLLCFGR_RST_VALUE
      • -
    • Add - - - new defines for RTC features support:
      • -
        -
      • RTC - - - Tamper 2 support
        • -
      • RTC - - - AF2 mapping support
        -
        • -
      -
    • Align - - - Bit naming for RTC_CR and RTC_TAFCR - registers (ex: RTC_CR_BCK --> RTC_CR_BKP)
      • -
    • Add - - - new define to manage RTC backup register - number: RTC_BKP_NUMBER
      • -
    • Rename - - - IS_UART_INSTANCE() macro to - IS_UART_HALFDUPLEX_INSTANCE()
      • -
    • Add new defines to check - LIN instance: IS_UART_LIN_INSTANCE
      • -
    • Remove - - - USART6 instance from STM32F410Tx header - file
      • -
    • Rename - IS_I2S_ALL_INSTANCE_EXT() macro to - IS_I2S_EXT_ALL_INSTANCEE()
      • -
    • Add - - - IS_I2S_APB1_INSTANCE() macro to check if - I2S instance mapping: API1 or APB2
      -
      • -
    • Remove - - - SPI_I2S_SUPPORT define for SPI I2S - features support: I2S feature is - available on all STM32F4xx devices
      • -
    • Add - - - SPI_I2S_FULLDUPLEX_SUPPORT define for - STM32F413xx/423xx devices
      • -
    • Align - - - SPI_I2SCFGR bit - naming: SPI_I2SCFGR_ASTRTEN bit is - missing for STM32F412xx devices
      • -
    • Add - - - new I2S_APB1_APB2_FEATURE - - - define - - - for STM32F4xx devices where I2S IP's are - splited between RCC APB1 and APB2 - interfaces
      -
      • -
    • Add new FLASH_SR_RDERR define in FLASH_SR register
      • -
    • Add FLASH_OTP_BASE and  FLASH_OTP_END defnes - to manage FLASH OPT area
      -
      • -
    • Add - - - bit definitions for ETH_MACDBGR - register
      • -
    • Add - - - new defines ADC1_COMMON_BASE and - ADC123_COMMON_BASE to replace ADC_BASE - define
      • -
    • Add - - - new defines ADC1_COMMON and - ADC123_COMMON to replace ADC define
      • -
    • Add - - - new ADC macros: IS_ADC_COMMON_INSTANCE() -and IS_ADC_MULTIMODE_MASTER_INSTANCE()
      -
      • -
    • Add - - - new defines for ADC multi mode features - support
      • -
    • Add - - - new ADC aliases ADC_CDR_RDATA_MST and - ADC_CDR_RDATA_SLV for compatibilities - with all STM32 Families
      • -
    • Update - - - TIM CNT and ARR register mask on 32-bits
      • -
    • Add new TIM_OR_TI1_RMP define in TIM_OR register
      • -
    • Add - - - new TIM macros to check TIM feature - instance support:
      • -
        -
      • IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
        • -
      • IS_TIM_CLOCK_DIVISION_INSTANCE()
        • -
      • IS_TIM_COMMUTATION_EVENT_INSTANCE()
        • -
      • IS_TIM_OCXREF_CLEAR_INSTANCE()
        • -
      • IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()
        • -
      • IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()
        • -
      • IS_TIM_REPETITION_COUNTER_INSTANCE()
        • -
      • IS_TIM_ENCODER_INTERFACE_INSTANCE()
        • -
      • IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()
        • -
      • IS_TIM_BREAK_INSTANCE()
        • -
      -
    • CAN_IER - - - register clean up: remove duplicated bit - definitions
      • -
    • USB_OTG - - - register: fix the wrong defined values - for USB_OTG_GAHBCFG bits
      • -
    -
-

V2.6.0 / 04-November-2016

-     -   Main - - - Changes
- - -
    -
  • Add support of STM32F413xx and STM32F423xx devices 
    • -
      -
    • Add - - - "stm32f413xx.h" and "stm32f423xx.h" - - - files
      • -
    -
      -
    • -

      Add - - - startup files  "startup_stm32f413xx.s" - - - and "startup_stm32f423xx.s" - - - for EWARM, MDK-ARM and SW4STM32 - toolchains

      -
      • -
    • Add - - - Linker files "stm32f413xx_flash.icf", - - - "stm32f413xx_sram.icf", - - - "stm32f423xx_flash.icf" - - - and "stm32f423xx_sram.icf" - - - used - - - within EWARM Workspaces
      • -
    -
  • All header files
    • -
      -
    • Use - - - _Pos and _Mask macro for all Bit - Definitions
      • -
    • Update - - - LPTIM_OR Bit Definition
      • -
    • Update - - - the defined frequencies by scale for USB - exported constants
      • -
    • Add - - - UID_BASE, FLASHSIZE_BASE and - PACKAGE_BASE defines
      • -
    • Add - - - new define DAC_CHANNEL2_SUPPORT to - manage DAC channel2 support
      • -
    • Use - - - new DAC1 naming
      • -
    • Rename - - - PWR_CSR_UDSWRDY define to PWR_CSR_UDRDY - in PWR_CSR register
      • -
    • Align - - - Bit naming for EXTI_IMR and EXTI_EMR - registers (ex: EXTI_IMR_MR0 --> - EXTI_IMR_IM0)
      -
      • -
    • Add - - - new EXTI_IMR_IM define in EXTI_IMR - register
      • -
    • Add - - - missing DMA registers definition
      • -
    • Add - - - macro to check SMBUS instance support
      -
      • -
    -
  • stm32f412cx.h, stm32f412zx.h, stm32f412vx.h, stm32f412rx.h files
    • -
      -
    • Add missing SYSCFG - register: CFGR2
      • -
    -
  • stm32f405xx.h, stm32f407xx.h, stm32f427xx.h, stm32f429xx.h files
    • -
      -
    • Remove - - - HASH_RNG_IRQn in IRQn_Type enumeration
      • -
    -
  • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
    • -
      -
    • Remove - - - I2C FLTR register as not supported
      -
      • -
    -
  • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
    • -
      -
    • Add - - - missing Bit Definition of ETH_MACDBGR - register
      • -
    -
  • system_stm32f4xx.c file
    • -
      -
    • Add - - - APBPrescTable declaration
      • -
    -
-

V2.5.1 / 28-June-2016

-     -   Main - - - Changes
- - -
    -
  • stm32f412rx.h, - stm32f412vx.h and - - - stm32f412zx.h files:
    • -
      -
    • -

      Add QSPI1_V2_1L - define to manage the QSPI DMA2 - limitation
      -

      -
      • -
    -
-

V2.5.0 / 22-April-2016

-     -   Main - - - Changes
- - -
    -
  • Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices
    • -
      -
    • -

      Add - "stm32f412Cx.h", "stm32f412Rx.h", "stm32f412Vx.h" and "stm32f412Zx.h" files

      -
      • -
    • -

      Add startup - files  "startup_stm32f412cx.s", "startup_stm32f412rx.s", "startup_stm32f412vx.s" and - - - "startup_stm32f412zx.s" - - - for EWARM, MDK-ARM and SW4STM32 - toolchains

      -
      • -
    • Add Linker files "stm32f412cx_flash.icf", "stm32f412cx_sram.icf", "stm32f412rx_flash.icf", "stm32f412rx_sram.icf", "stm32f412vx_flash.icf", "stm32f412vx_sram.icf", "stm32f412zx_flash.icf" and "stm32f412zx_sram.icf" used within EWARM - Workspaces
      • -
    -
  • Header files for all - STM32 devices
    • -
      -
    • Remove uint32_t cast - and keep only Misra Cast (U) to avoid - two types cast duplication
      • -
    • Correct some bits - definition to be in line with naming - used in the Reference Manual
      • -
        -
      • WWDG_CR_Tx changed - - - to WWDG_CR_T_x
        • -
      • WWDG_CFR_Wx changed - - - to WWDG_CFR_W_x
        • -
      • WWDG_CFR_WDGTBx changed - - - to WWDG_CFR_WDGTB_x
        • -
      -
    -
  • stm32f407xx.h, - stm32f417xx.h, stm32f427xx.h, - - - stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files
    • -
      -
    • Correct some bits - definition to be in line with naming - used in the Reference Manual
      • -
    -
      -
        -
      • DCMI_RISR_x changed - - - to DCMI_RIS_x
        • -
      • DCMI_RISR_OVF_RIS - - - changed to DCMI_RIS_OVR_RIS
        • -
      • DCMI_IER_OVF_IE - - - changed to DCMI_IER_OVR_IE
        • -
      -
    -
  • stm32f427xx.h, - stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files
    • -
      -
    • Correct some bits - definition to be in line with naming - used in the Reference Manual
      • -
        -
      • SAI_xFRCR_FSPO changed - - - to SAI_xFRCR_FSPOL
        • -
      -
    • Rename - IS_SAI_BLOCK_PERIPH to - IS_SAI_ALL_INSTANCE
      -
      • -
    -
  • stm32f410cx.h, - stm32f410rx.h, stm32f410tx.h files - - - and stm32f446xx.h
    • -
      -
    • Remove - FMPI2C_CR1_SWRST and FMPI2C_CR1_WUPEN - Bit definition for I2C_CR1 register
      • -
    -
  • stm32f407xx.h, - stm32f417xx.h, stm32f427xx.h, - stm32f437xx.h, stm32f439xx.h, - stm32f469xx.h, stm32f479xx.h files
    • -
      -
    • Add missing bits - definitions for DMA2D_CR, - DMA2D_FGPFCCR, DMA2D_BGPFCCR, - DMA2D_OPFCCR registers
      • -
    -
  • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
    • -
      -
    • Add missing RCC_DCKCFGR register - - - in RCC_TypeDef structure
      -
      • -
    • Add - missing Bit definition for RCC_DCKCFGR - register
      • -
    -
  • system_stm32f4xx.c
    -
    • -
      -
    • Update - SystemInit_ExtMemCtl() API to fix delay - optimization problem with GCC compiler: index variable is - declared as volatile 
      • -
    -
  • stm32f4xx.h
    • -
      -
    • Rename - __STM32F4xx_CMSIS_DEVICE_VERSION_xx - defines to - __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)
      • -
    -
- -

V2.4.3 / 29-January-2016

-     -   Main - - - Changes
-
- -
    -
  • -

    Header file for all STM32 devices -

    -
    • -
      -
    • Rename -ADC - - - overrun flags definitions : - ADC_CSR_DOVR1, ADC_CSR_DOVR2 and - ADC_CSR_DOVR3 are replaced respectively - by ADC_CSR_OVR1, ADC_CSR_OVR2 and - ADC_CSR_OVR3 to be aligned with - reference manuals
      • -
    • Add - - - missing bits definitions for DAC : - DAC_CR_DMAUDRIE1 and DAC_CR_DMAUDRIE2
      • -
    • Update - - - CMSIS driver to be compliant with MISRA - C 2004 rule 10.6
      • -
    • Remove - - - the double definition of - USB_OTG_HS_MAX_IN_ENDPOINTS and add a - new one for  - USB_OTG_HS_MAX_OUT_ENDPOINTS
      • -
    -
  • stm32f446xx.h, - - - stm32f469xx.h, stm32f479xx.h files 
    • -
      -
    • Change - - - the bit definition value of - QUADSPI_CR_FTHRES
      • -
    -
  • - stm32f446xx.h, stm32f469xx.h, - stm32f479xx.h, stm32f429xx.h, - stm32f439xx.h files
    • -
      -
    • Rename - - - the LTDC_GCR_DTEN to LTDC_GCR_DEN in - order to be aligned with the reference - manual
      • -
    • Rename - - - DCMI_MISR bit definitions to DCMI_MIS
      • -
    • Rename - - - DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
      • -
    • Add - - - missing bits definitions for DCMI_ESCR, - DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, - DCMI_DR registers
      • -
    -
  • - stm32f407xx.h, stm32f417xx.h, - stm32f427xx.h, stm32f437xx.h files
    • -
      -
    • Rename - - - DCMI_MISR bit definitions to DCMI_MIS
      • -
    • Rename - - - DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
      • -
    • Add - - - missing bits definitions for DCMI_ESCR, - DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, - DCMI_DR registers
      • -
    -
  • - stm32f410cx.h, stm32f410rx.h, - stm32f410tx.h files
    • -
      -
    • Update - - - the - - - LPTIM SNGSTRT defined value
      • -
    -
  • stm32f427xx.h, - stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f469xx.h, stm32f479xx.h - - - files
    • -
      -
    • Rename - - - the DMA2D_IFSR bit definitions to - DMA2D_IFCR
      • -
    -
  • stm32f427xx.h, - stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h - - - files 
    • -
      -
    • Correct - - - a wrong value of SAI_xCR2_CPL definition - bit 
      -
      • -
    -
-

V2.4.2 / 13-November-2015

-

Main Changes

-
    -
  • -

    system_stm32f4xx.c file -

    -
    • -
      -
    • update -SystemInit_ExtMemCtl() - - - function implementation to allow the - possibility of simultaneous use of - DATA_IN_ExtSRAM and DATA_IN_ExtSDRAM
      • -
    -
  • stm32f4xx.h - - - file
    • -
      -
    • add - - - symbols for STM32F411xC devices
      -
      • -
    -
  • stm32f405xx.h, - - - stm32f407xx.h, stm32f415xx.h, - stm32f417xx.h files
    • -
      -
    • add - - - FSMC_BCRx_CPSIZE bits definitions
      • -
    • remove - - - FSMC_BWTRx_CLKDIV and FSMC_BWTRx_DATLAT - bits definitions
      • -
    -
  • stm32f429xx.h, - - - stm32f427xx.h, stm32f437xx.h files
    • -
      -
    • add - - - FMC_BCRx_CPSIZE bits definitions
      • -
    • remove - - - FMC_BWTRx_CLKDIV and FMC_BWTRx_DATLAT - bits definitions
      • -
    -
  • stm32f446xx.h, - - - stm32f469xx.h and stm32f479xx.h
    • -
      -
    • update - - - USB_OTG_GlobalTypeDef registers - structure to remove ADP control - registers
      • -
    • add - - - USB_OTG_DOEPMSK_OTEPSPRM and - USB_OTG_DOEPINT_OTEPSPR bits definitions
      • -
    • Remove - - - ADP related bits definitions
      • -
    • add - - - IS_PCD_ALL_INSTANCE() and - IS_HCD_ALL_INSTANCE() macros
      -
      • -
    -
-

V2.4.1 / 09-October-2015

-

Main Changes

-
    -
  • "stm32f469xx.h", - - - "stm32f479xx.h" -
      -
    • Update bits definition for - DSI_WPCR and DSI_TCCR registers
      -
      • -
    -
    • -
-

V2.4.0 / 14-August-2015

-

Main Changes

-
    -
  • -

    Add - - - support of STM32F469xx - and STM32F479xx devices
    -

    -
    • -
      -
    • -

      Add - - - "stm32f469xx.h" and "stm32f479xx.h" - - - files

      -
      • -
    -
      -
    • -

      Add - - - startup files  "startup_stm32f469xx.s" - - - and "startup_stm32f479xx.s" - - - for EWARM, MDK-ARM and SW4STM32 - toolchains

      -
      • -
    • Add - - - Linker files "stm32f469xx_flash.icf", - - - "stm32f469xx_sram.icf", - - - "stm32f479xx_flash.icf" - - - and "stm32f479xx_sram.icf" - - - used - - - within EWARM Workspaces
      • -
    -
  • -

    Add - - - support of STM32F410xx - devices
    -

    -
    • -
      -
    • -

      Add - - - "stm32f410cx.h", "stm32f410tx.h" - and "stm32f410rx.h" - - - files

      -
      • -
    -
      -
    • -

      Add - - - startup files  "startup_stm32f410cx.s", - - - "startup_stm32f410rx.s" and "startup_stm32f410tx.s" - - - for EWARM, MDK-ARM and SW4STM32 - toolchains

      -
      • -
    • Add - - - Linker files "stm32f410cx_flash.icf", - - - "stm32f410cx_sram.icf", - - - "stm32f410rx_flash.icf", "stm32f410tx_sram.icf", - - - "stm32f410tx_flash.icf",  - and "stm32f410rx_sram.icf" - - - used - - - within EWARM Workspaces
      • -
    -
-

V2.3.2 / 26-June-2015

-

Main Changes

-
    -
  • "stm32f405xx.h", - - - "stm32f407xx.h", "stm32f415xx.h" and - "stm32f417xx.h" -
      -
    • Update FSMC_BTRx_DATAST - - - and FSMC_BWTRx_DATAST (where x can - be 1, 2, 3 and 4) mask on 8bits - instead of 4bits
      • -
    -
    • -
  • "stm32f427xx.h", - - - "stm32f437xx.h", "stm32f429xx.h" and - "stm32f439xx.h"
    -
      -
    • Update the defined mask value - for SAI_xSR_FLVL_2
      • -
    -
    • -
  • "stm32f415xx.h", - - - "stm32f417xx.h", "stm32f437xx.h" and - "stm32f439xx.h"
    • -
      -
    • HASH alignement with bits namming - used in documentation -
        -
          -
        • Rename HASH_IMR_DINIM to - HASH_IMR_DINIE
          • -
        -
          -
        • Rename HASH_IMR_DCIM to - HASH_IMR_DCIE
          • -
        -
          -
        • Rename HASH_STR_NBW to - HASH_STR_NBW
          • -
        -
      -
      • -
    -
  • system_stm32f4xx.c
    • -
      -
    • Remove __IO on constant table - declaration
      • -
    -
      -
    • Implement workaround to cover - RCC limitation regarding peripheral - enable delay
      • -
    -
      -
    • SystemInit_ExtMemCtl() - - - update GPIO configuration when external - SDRAM is used 
      • -
    -
- -

V2.3.1 / 03-April-2015

- Main Changes -
    -
  • -

    Header file for all STM32 devices

    -
      -
    • Update SRAM2, SRAM3 and - BKPSRAM Bit-Banding base address - defined values
      • -
    • Keep reference to - SRAM3 only for STM32F42xx and - STM32F43xx devices
      • -
    • Remove CCMDATARAM_BB_BASE: the - CCM Data RAM region is not accessible - via Bit-Banding
      -
      • -
    • Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of - 0x00001FFF
      -
      • -
    -
    • -
-

V2.3.0 / 02-March-2015

-

Main Changes

- -
    -
  • -

    Add - - - support of STM32F446xx - devices
    -

    -
    • -
      -
    • -

      Add - - - "stm32f446xx.h" file

      -
      • -
    -
      -
    • -

      Add - - - startup file "startup_stm32f446xx.s" - for EWARM, MDK-ARM and TrueSTUDIO - toolchains

      -
      • -
    • Add - - - Linker files "stm32f446xx_flash.icf" and - "stm32f446xx_sram.icf" used within EWARM - Workspaces
      • -
    -
  • -

    Header file for all STM32 devices

    -
      -
    • Add missing bits - definition in the EXTI IMR, EMR, RTSR, - FTSR, SWIER and PR registers
      • -
    • Update - RCC_AHB1RSTR_OTGHRST bit definition
      • -
    • Update PWR_CR_VOS - bits definition for STM32F40xx - - - and STM32F41xx - - - devices
      • -
    • -

      update SAI_xCR1_MCKDIV bit - definition
      -

      -
      • -
    -
    • -
-

V2.2.0 / 15-December-2014

-

Main Changes

- -
    -
  • -

    stm32f4xx.h

    -
      -
    • -

      Add new constant definition STM32F4 -
      -

      -
      • -
    -
    • -
  • -

    system_stm32f4xx.c
    -

    -
      -
    • -

      Fix SDRAM configuration in - SystemInit_ExtMemCtl(): change RowBitsNumber - from 11 to 12 (for MT48LC4M32B2 - available on STM324x9I_EVAL board)
      -

      -
      • -
    -
    • -
  • -

    Header file for all STM32 devices

    -
      -
    • -

      Add missing bits definition - for CAN, FMC and USB peripherals

      -
      • -
    • -

      GPIO_TypeDef: change the BSRR - register definition, the two 16-bits - definition BSRRH and BSRRL are - merged in a single 32-bits - definition BSRR

      -
      • -
    -
    • -
-

V2.1.0 / 19-June-2014

-

Main Changes

- - - -
    -
  • -

    Add - - - support of STM32F411xExx - devices
    -

    -
    • -
      -
    • -

      Add - - - "stm32f411xe.h" file

      -
      • -
    -
      -
    • -

      Add - - - startup file "startup_stm32f411xx.s" - for EWARM, MDK-ARM and TrueSTUDIO - toolchains

      -
      • -
    -
  • -

    All - - - header files

    -
    • -
      -
    • -

      Add - - - missing defines for GPIO LCKR Register

      -
      • -
    • -

      Add defines for - memories base and end addresses: - FLASH, SRAM, BKPSRAM and CCMRAM.

      -
      • -
    • -

      Add -the - - - following aliases for IRQ number and - handler definition to ensure - compatibility across the product lines - of STM32F4 Series;
      -

      -
      • -
        -
      • -

        example for STM32F405xx.h

        -
        • -
      -
    -
-
#define - - - FMC_IRQn              - - - FSMC_IRQn
- #define - - - FMC_IRQHandler     - FSMC_IRQHandler
-
    -
      -
        -
      • -

        and for STM32F427xx.h

        -
        • -
      -
    -
-
#define - - - FSMC_IRQn            - - - FMC_IRQn
- #define - - - FSMC_IRQHandler   FMC_IRQHandler
-
    -
  • "stm32f401xc.h" - - - and "stm32f401xe.h": update to be in line - with latest version of the Reference - - - manual
    • -
      -
    • Remove - - - RNG registers structures and the - corresponding bit definitions
      • -
    • Remove - - - any occurrence to RNG (clock enable, - clock reset,…)
      • -
    • Add - - - the following bit definition for PWR CR - register
      • -
        -
      • #define  PWR_CR_ADCDC1      - - - ((uint32_t)0x00002000)
        • -
      -
        -
      • #define  PWR_CR_LPLVDS       - - - ((uint32_t)0x00000400)     
        • -
      -
        -
      • #define  - - - PWR_CR_MRLVDS   -    ((uint32_t)0x00000800)     
        • -
      -
    -
  • "stm32f427xx.h", - - - "stm32f437xx.h", "stm32f429xx.h" and - "stm32f439xx.h"
    • -
      -
    • Add - - - a new legacy bit definition for PWR to - be in line with latest version of the - Reference manual
      • -
        -
      • #define  PWR_CR_LPUDS        PWR_CR_LPLVDS
        • -
      -
        -
      • #define  -PWR_CR_MRUDS      - - - PWR_CR_MRLVDS
        • -
      -
    -
  • -

    Update startup - files for EWARM toolchain to cope with - compiler enhancement of the V7.10 - version

    -
    • -
  • -

    system_stm32f4xx.c

    -
    • -
      -
    • Remove - - - dependency vs. the HAL, to allow using - this file without the need to have the - HAL drivers
      -
      • -
        -
      • Include - - - stm32f4xx.h - - - instead of stm32f4xx_hal.h
        • -
      • Add -definition - - - of HSE_VALUE and HSI_VALUE, if they - are not yet defined in the compilation - scope (these values are defined in - stm32f4xx_hal_conf).
        -
        • -
      -
    • -

      Use “__IO const” - instead of “__I”, to avoid any - compilation issue when __cplusplus - switch is defined

      -
      • -
    -
-

V2.0.0 / 18-February-2014

-

Main Changes

- - - -
    -
  • Update based on STM32Cube - specification
    -
    • -
  • This version and later has to be - used only with STM32CubeF4 based development
    • -
-

V1.3.0 / - 08-November-2013

-

Main Changes

-
    -
  • -

    Add -support - - - of STM32F401xExx - devices

    -
    • -
  • Update startup files "startup_stm32f401xx.s" for EWARM, MDK-ARM, TrueSTUDIO and - Ride toolchains: Add SPI4 interrupt - handler entry in the vector table
    • -
-

V1.2.1 / - 19-September-2013

-

Main Changes

-
    -
  • -

    system_stm32f4xx.c : Update FMC SDRAM - configuration (RBURST mode activation)
    -

    -
    • -
  • Update startup files "startup_stm32f427_437xx.s" and "startup_stm32f429_439xx.s"  for - TrueSTUDIO and Ride toolchains and - maintain the old name of startup files for - legacy purpose
    • -
-

V1.2.0 / - 11-September-2013

-

Main Changes

-
    -
  • -

    Add -support - - - of STM32F429/439xx - and STM32F401xCxx - devices

    -
    • -
  • Update - - - definition of STM32F427/437xx devices : - extension -of - - - the features to include system clock up to - 180MHz, dual bank Flash, reduced STOP Mode - current, SAI, PCROP, SDRAM and DMA2D
    • -
  • stm32f4xx.h
    -     -
      -
    • Add the - following device defines :
      • -
        -
      • "#define - STM32F40_41xxx" for all STM32405/415/407/417xx devices
        • -
      • "#define - STM32F427_437xx" for all STM32F427/437xx devices
        • -
      • "#define - STM32F429_439xx" for all STM32F429/439xx devices
        • -
      • "#define - STM32F401xx" for all STM32F401xx devices
        • -
      -
    • Maintain the - old device define for legacy purpose
      • -
    • Update IRQ - handler enumeration structure to - support all STM32F4xx Family devices. -  
      • -
    -
    • -
  • Add new startup files "startup_stm32f40_41xxx.s","startup_stm32f427_437xx.s", "startup_stm32f429_439xx.s" and "startup_stm32f401xx.s" for all toolchains and maintain - the old name for startup files for legacy - purpose
    • -
  • system_stm32f4xx.c -
      -
    • Update - the system configuration to - support all STM32F4xx Family devices. -  
      • -
    -
    • -
-

V1.1.0 / - 11-January-2013

-

Main Changes

-
    -
  • Official release for STM32F427x/437x - devices.
    • -
  • stm32f4xx.h
    -     -
      -
    • Update product - define: replace "#define STM32F4XX" by - "#define STM32F40XX" for STM32F40x/41x - devices
      • -
    •  Add new - product define: "#define STM32F427X" - for STM32F427x/437x devices.
      • -
    -
    • -
  • Add new startup files "startup_stm32f427x.s" for all - toolchains
    • -
  • rename startup files "startup_stm32f4xx.s" by "startup_stm32f40xx.s" for all - toolchains
    • -
  • system_stm32f4xx.c -
      -
    • Prefetch Buffer - enabled
      • -
    • Add reference - to STM32F427x/437x devices and - STM324x7I_EVAL board
      • -
    • SystemInit_ExtMemCtl() - - - function
      -       -
        -
      • Add - configuration of missing FSMC - address and data lines
        -
        • -
      -
        -
      • Change - memory type to SRAM instead of - PSRAM (PSRAM is available only on - STM324xG-EVAL RevA) and update - timing values
        • -
      -
      • -
    -
    • -
- -

V1.0.2 / 05-March-2012

-

Main Changes

-
    -
  • All source files: license - disclaimer text update and add link to the - License file on ST Internet.
    • -
-

V1.0.1 / 28-December-2011

-

Main Changes

-
    -
  • All source files: update - disclaimer to add reference to - the new license agreement
    • -
  • stm32f4xx.h
    • -
      -
    • Correct bit - - - definition: RCC_AHB2RSTR_HSAHRST changed - - - to RCC_AHB2RSTR_HASHRST
      • -
    -
-

V1.0.0 / 30-September-2011

-

Main Changes

-
    -
  • First official release for STM32F40x/41x - devices
    • -
  • Add startup file for TASKING - toolchain
    • -
  • system_stm32f4xx.c: - driver's comments update
    • -
-

V1.0.0RC2 / 26-September-2011

-

Main Changes

-
    -
  • Official version (V1.0.0) - Release Candidate2 for STM32F40x/41x - devices
    • -
  • stm32f4xx.h
    • -
      -
    • Add define for Cortex-M4 - revision __CM4_REV
      • -
    • Correct RCC_CFGR_PPRE2_DIV16 - bit (in RCC_CFGR register) value - to 0x0000E000
      • -
    • Correct some bits - definition to be in line with naming - used in the Reference Manual (RM0090)
      • -
        -
      • GPIO_OTYPER_IDR_x - changed to GPIO_IDR_IDR_x
        • -
      • GPIO_OTYPER_ODR_x - changed to GPIO_ODR_ODR_x
        • -
      • SYSCFG_PMC_MII_RMII - changed to SYSCFG_PMC_MII_RMII_SEL
        • -
      • RCC_APB2RSTR_SPI1 - changed to RCC_APB2RSTR_SPI1RST
        • -
      • DBGMCU_APB1_FZ_DBG_IWDEG_STOP - changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
        • -
      • PWR_CR_PMODE - changed to PWR_CR_VOS
        • -
      • PWR_CSR_REGRDY - changed to PWR_CSR_VOSRDY
        • -
      • Add new define - RCC_AHB1ENR_CCMDATARAMEN
        • -
      • Add new - defines SRAM2_BASE, CCMDATARAM_BASE - and BKPSRAM_BASE
        • -
      -
    • GPIO_TypeDef structure: in the - comment change AFR[2] address - mapping to 0x20-0x24 - instead of 0x24-0x28
      • -
    -
  • system_stm32f4xx.c
    • -
      -
    • SystemInit(): add code - to enable the FPU
      • -
    • SetSysClock(): change - PWR_CR_PMODE - by PWR_CR_VOS
      • -
    • SystemInit_ExtMemCtl(): - remove commented values
      • -
    -
  • startup (for all compilers)
    • -
      -
    • Delete code used to enable the - FPU (moved to system_stm32f4xx.c file)
      • -
    • File’s header updated
      • -
    -
-

V1.0.0RC1 / 25-August-2011

-

Main Changes

-
    -
  • Official version (V1.0.0) - Release Candidate1 for STM32F4xx devices
    • -
- -
    -
-
-
-

For - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

-

-
-

-
-
-

 

-
- \ No newline at end of file + + + + + + + Release Notes for STM32F4xx CMSIS + + + + + + +
+
+
+

Release Notes for

+

STM32F4xx CMSIS

+

Copyright © 2017 STMicroelectronics
+

+ +
+

Purpose

+

This driver provides the CMSIS device for the stm32f4xx products.

+
+
+

Update History

+
+ +
+

Main Changes

+
    +
  • Added new atomic register access macros in stm32f4xx.h file.
    • +
  • Update FLASH_SCALE2_LATENCY4_FREQ value to 120MHz instead of 12MHz.
    • +
  • Update the GCC startup file to be aligned to IAR/Keil IDE.
    • +
  • STM32F410/412/413/423: +
      +
    • Fix wrong defined value for wake-up pin 3 (PWR_CSR_EWUP3).
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • All source files: update disclaimer to add reference to the new license agreement.
    • +
  • Correct ETH bits definitions to be in line with naming used in the STM32F4 reference manual documents.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add missing definition FLASH_CR_ERRIE to the CMSIS header file.
    • +
  • Remove unsupported “GPIOF_BASE†and “GPIOG_BASE†defines from STM32F412Vx device.
    • +
  • Add new atomic register access macros in stm32f4xx.h file.
    • +
  • Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.
    • +
  • Fix a typo in CMSIS STM32F4xx version macro (__STM32F4xx_CMSIS_VERSION).
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • system_stm32f4xx.c: +
      +
    • Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS
      • +
    • Update SystemInit_ExtMemCtl() API to initialize the tmpreg variable before each time out loop condition.
      • +
    • +
  • Add License.md and Readme.md files required for GitHub publication
    • +
  • Improve GCC startup files robustness.
    • +
  • Fix wrong value for GPIO_MODER_MODE8_Msk and GPIO_MODER_MODE2_Pos.
    • +
  • Update max number of host channels in FS for STM32F446: +
      +
    • Update USB_OTG_FS_HOST_MAX_CHANNEL_NBR value from 8 to 12.
      • +
    • +
  • Add SMBDEN and SMBHEN bit definition for STM32F410Tx device.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • All header files +
      +
    • Update to use new BSD License format
      • +
    • +
  • MDK-ARM startup files +
      +
    • Update to fix invalid config wizard annotations
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • stm32f446xx.h file +
      +
    • Update to support HW flow control on UART4 and UART5 instances
      • +
    • +
  • stm32f412xx.h, stm32f413xx.h and stm32f423xx.h files +
      +
    • Remove unused IS_USB_ALL_INSTANCE() assert macro
      • +
    • +
  • All header files +
      +
    • Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro
      • +
    • +
  • system_stm32f4xx.c file +
      +
    • Update SystemInit() API to don’t reset RCC registers to its reset values
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • CRYP: +
      +
    • Update CMSIS devices with correct CRYP data input register name: DIN instead of DR
      • +
    • Add Bits definition for CRYP CR ALGOMODE AES GCM/CCM
      • +
    • +
  • HASH: +
      +
    • Update HASH_DIGEST_TypeDef structure: resize the HR register
      • +
    • Remove MDMAT Bits definition
      • +
    • +
  • TIM: +
      +
    • Add requires TIM assert macros:
      • +
    • IS_TIM_SYNCHRO_INSTANCE()
      • +
    • IS_TIM_CLOCKSOURCE_TIX_INSTANCE()
      • +
    • IS_TIM_CLOCKSOURCE_ITRX_INSTANCE()
      • +
    • +
  • RCC +
      +
    • Add RCC_CSR_BORRSTF bits definition
      • +
    • +
  • GPIO +
      +
    • Fix GPIO BRR bits definition
      • +
    • Adjust the GPIO present on STM32F412 devices
      • +
    • +
  • SAI +
      +
    • Fix frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits description
      • +
    • +
  • USB: +
      +
    • Add missing Bits Definitions in USB_OTG_DOEPMSK register
      • +
    • USB_OTG_DOEPMSK_AHBERRM
      • +
    • USB_OTG_DOEPMSK_OTEPSPRM
      • +
    • USB_OTG_DOEPMSK_BERRM
      • +
    • USB_OTG_DOEPMSK_NAKM
      • +
    • USB_OTG_DOEPMSK_NYETM
      • +
    • Add missing Bits Definitions in USB_OTG_DIEPINT register
      • +
    • USB_OTG_DIEPINT_INEPNM
      • +
    • USB_OTG_DIEPINT_AHBERR
      • +
    • USB_OTG_DOEPINT_OUTPKTERR
      • +
    • USB_OTG_DOEPINT_NAK
      • +
    • USB_OTG_DOEPINT_STPKTRX
      • +
    • Add missing Bits Definitions in USB_OTG_DCFG register
      • +
    • USB_OTG_DCFG_XCVRDLY
      • +
    • USB_OTG_DCFG_ERRATIM
      • +
    • Update USB OTG max number of endpoints (6 FS and 9 HS instead of 5 and 8)
      • +
    • +
  • I2C/FMPI2C +
      +
    • Align Bit naming for FMPI2C_CR1 register: FMPI2C_CR1_DFN–> FMPI2C_CR1_DNF
      • +
    • Add IS_SMBUS_ALL_INSTANCE() define
      • +
    • +
  • DFSDM +
      +
    • Align Bit naming for DFSDM_FLTICR register: DFSDM_FLTICR_CLRSCSDF–> DFSDM_FLTICR_CLRSCDF
      • +
    • +
  • PWR +
      +
    • Remove PWR_CSR_WUPP define: feature not available on STM32F469xx/479xx devices
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Remove Date and Version from all header files
    • +
  • USB_OTG register clean up: remove duplicated bits definitions
    • +
  • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files +
      +
    • Remove BKPSRAM_BASE define: feature not available
      • +
    • +
  • stm32f405xx.h, stm32f407xx.h files +
      +
    • Rename HASH_RNG_IRQn to RNG_IRQn: HASH instance not available
      • +
    • +
  • stm32f410xx.h, stm32f412xx.h, stm32f413xx.h, stm32f423xx.h files +
      +
    • Add missing wake-up pins defines
      • +
    • +
  • stm32f412cx.h files +
      +
    • Add support of USART3 instance
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates in header files to support LL drivers +
      +
    • Align Bit naming for RCC_CSR register (ex: RCC_CSR_PADRSTF –> RCC_CSR_PINRSTF)
      • +
    • Add new defines for RCC features support:
      • +
    • RCC PLLI2S and RCC PLLSAI support
      • +
    • RCC PLLR I2S clock source and RCC PLLR system clock support
      • +
    • RCC SAI1A PLL source and RCC SAI1B PLL source support
      • +
    • RCC AHB2 support
      • +
    • Add RCC_DCKCFGR_PLLI2SDIVQ_X and RCC_DCKCFGR_PLLSAIDIVQ_X bits definition
      • +
    • Add new defines for RCC_PLLI2SCFGR_RST_VALUE, RCC_PLLSAICFGR_RST_VALUE and RCC_PLLCFGR_RST_VALUE
      • +
    • Add new defines for RTC features support:
      • +
    • RTC Tamper 2 support
      • +
    • RTC AF2 mapping support
      • +
    • Align Bit naming for RTC_CR and RTC_TAFCR registers (ex: RTC_CR_BCK –> RTC_CR_BKP)
      • +
    • Add new define to manage RTC backup register number: RTC_BKP_NUMBER
      • +
    • Rename IS_UART_INSTANCE() macro to IS_UART_HALFDUPLEX_INSTANCE()
      • +
    • Add new defines to check LIN instance: IS_UART_LIN_INSTANCE
      • +
    • Remove USART6 instance from STM32F410Tx header file
      • +
    • Rename IS_I2S_ALL_INSTANCE_EXT() macro to IS_I2S_EXT_ALL_INSTANCEE()
      • +
    • Add IS_I2S_APB1_INSTANCE() macro to check if I2S instance mapping: API1 or APB2
      • +
    • Remove SPI_I2S_SUPPORT define for SPI I2S features support: I2S feature is available on all STM32F4xx devices
      • +
    • Add SPI_I2S_FULLDUPLEX_SUPPORT define for STM32F413xx/423xx devices
      • +
    • Align SPI_I2SCFGR bit naming: SPI_I2SCFGR_ASTRTEN bit is missing for STM32F412xx devices
      • +
    • Add new I2S_APB1_APB2_FEATURE define for STM32F4xx devices where I2S IP’s are splited between RCC APB1 and APB2 interfaces
      • +
    • Add new FLASH_SR_RDERR define in FLASH_SR register
      • +
    • Add FLASH_OTP_BASE and FLASH_OTP_END defnes to manage FLASH OPT area
      • +
    • Add bit definitions for ETH_MACDBGR register
      • +
    • Add new defines ADC1_COMMON_BASE and ADC123_COMMON_BASE to replace ADC_BASE define
      • +
    • Add new defines ADC1_COMMON and ADC123_COMMON to replace ADC define
      • +
    • Add new ADC macros: IS_ADC_COMMON_INSTANCE() and IS_ADC_MULTIMODE_MASTER_INSTANCE()
      • +
    • Add new defines for ADC multi mode features support
      • +
    • Add new ADC aliases ADC_CDR_RDATA_MST and ADC_CDR_RDATA_SLV for compatibilities with all STM32 Families
      • +
    • Update TIM CNT and ARR register mask on 32-bits
      • +
    • Add new TIM_OR_TI1_RMP define in TIM_OR register
      • +
    • Add new TIM macros to check TIM feature instance support:
      • +
    • IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
      • +
    • IS_TIM_CLOCK_DIVISION_INSTANCE()
      • +
    • IS_TIM_COMMUTATION_EVENT_INSTANCE()
      • +
    • IS_TIM_OCXREF_CLEAR_INSTANCE()
      • +
    • IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()
      • +
    • IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()
      • +
    • IS_TIM_REPETITION_COUNTER_INSTANCE()
      • +
    • IS_TIM_ENCODER_INTERFACE_INSTANCE()
      • +
    • IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()
      • +
    • IS_TIM_BREAK_INSTANCE()
      • +
    • +
  • CAN_IER register clean up: remove duplicated bit definitions
    • +
  • USB_OTG register: fix the wrong defined values for USB_OTG_GAHBCFG bits
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F413xx and STM32F423xx devices +
      +
    • Add “stm32f413xx.h†and “stm32f423xx.h†files
      • +
    • Add startup files “startup_stm32f413xx.s†and “startup_stm32f423xx.s†for EWARM, MDK-ARM and SW4STM32 toolchains
      • +
    • Add Linker files “stm32f413xx_flash.icfâ€, “stm32f413xx_sram.icfâ€, “stm32f423xx_flash.icf†and “stm32f423xx_sram.icf†used within EWARM Workspaces
      • +
    • +
  • All header files +
      +
    • Use _Pos and _Mask macro for all Bit Definitions
      • +
    • Update LPTIM_OR Bit Definition
      • +
    • Update the defined frequencies by scale for USB exported constants
      • +
    • Add UID_BASE, FLASHSIZE_BASE and PACKAGE_BASE defines
      • +
    • Add new define DAC_CHANNEL2_SUPPORT to manage DAC channel2 support
      • +
    • Use new DAC1 naming
      • +
    • Rename PWR_CSR_UDSWRDY define to PWR_CSR_UDRDY in PWR_CSR register
      • +
    • Align Bit naming for EXTI_IMR and EXTI_EMR registers (ex: EXTI_IMR_MR0 –> EXTI_IMR_IM0)
      • +
    • Add new EXTI_IMR_IM define in EXTI_IMR register
      • +
    • Add missing DMA registers definition
      • +
    • Add macro to check SMBUS instance support
      • +
    • +
  • stm32f412cx.h, stm32f412zx.h, stm32f412vx.h, stm32f412rx.h files +
      +
    • Add missing SYSCFG register: CFGR2
      • +
    • +
  • stm32f405xx.h, stm32f407xx.h, stm32f427xx.h, stm32f429xx.h files +
      +
    • Remove HASH_RNG_IRQn in IRQn_Type enumeration
      • +
    • +
  • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files +
      +
    • Remove I2C FLTR register as not supported
      • +
    • +
  • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files +
      +
    • Add missing Bit Definition of ETH_MACDBGR register
      • +
    • +
  • system_stm32f4xx.c file +
      +
    • Add APBPrescTable declaration
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • stm32f412rx.h, stm32f412vx.h and stm32f412zx.h files: +
      +
    • Add QSPI1_V2_1L define to manage the QSPI DMA2 limitation
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices +
      +
    • Add “stm32f412Cx.hâ€, “stm32f412Rx.hâ€, “stm32f412Vx.h†and “stm32f412Zx.h†files
      • +
    • Add startup files “startup_stm32f412cx.sâ€, “startup_stm32f412rx.sâ€, “startup_stm32f412vx.s†and “startup_stm32f412zx.s†for EWARM, MDK-ARM and SW4STM32 toolchains
      • +
    • Add Linker files “stm32f412cx_flash.icfâ€, “stm32f412cx_sram.icfâ€, “stm32f412rx_flash.icfâ€, “stm32f412rx_sram.icfâ€, “stm32f412vx_flash.icfâ€, “stm32f412vx_sram.icfâ€, “stm32f412zx_flash.icf†and “stm32f412zx_sram.icf†used within EWARM Workspaces
      • +
    • +
  • Header files for all STM32 devices +
      +
    • Remove uint32_t cast and keep only Misra Cast (U) to avoid two types cast duplication
      • +
    • Correct some bits definition to be in line with naming used in the Reference Manual
      • +
    • WWDG_CR_Tx changed to WWDG_CR_T_x
      • +
    • WWDG_CFR_Wx changed to WWDG_CFR_W_x
      • +
    • WWDG_CFR_WDGTBx changed to WWDG_CFR_WDGTB_x
      • +
    • +
  • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files +
      +
    • Correct some bits definition to be in line with naming used in the Reference Manual
      • +
    • DCMI_RISR_x changed to DCMI_RIS_x
      • +
    • DCMI_RISR_OVF_RIS changed to DCMI_RIS_OVR_RIS
      • +
    • DCMI_IER_OVF_IE changed to DCMI_IER_OVR_IE
      • +
    • +
  • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files +
      +
    • Correct some bits definition to be in line with naming used in the Reference Manual
      • +
    • SAI_xFRCR_FSPO changed to SAI_xFRCR_FSPOL
      • +
    • Rename IS_SAI_BLOCK_PERIPH to IS_SAI_ALL_INSTANCE
      • +
    • +
  • stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files and stm32f446xx.h +
      +
    • Remove FMPI2C_CR1_SWRST and FMPI2C_CR1_WUPEN Bit definition for I2C_CR1 register
      • +
    • +
  • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files +
      +
    • Add missing bits definitions for DMA2D_CR, DMA2D_FGPFCCR, DMA2D_BGPFCCR, DMA2D_OPFCCR registers
      • +
    • +
  • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files +
      +
    • Add missing RCC_DCKCFGR register in RCC_TypeDef structure
      • +
    • Add missing Bit definition for RCC_DCKCFGR register
      • +
    • +
  • system_stm32f4xx.c +
      +
    • Update SystemInit_ExtMemCtl() API to fix delay optimization problem with GCC compiler: index variable is declared as volatile
      • +
    • +
  • stm32f4xx.h +
      +
    • Rename __STM32F4xx_CMSIS_DEVICE_VERSION_xx defines to __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Header file for all STM32 devices +
      +
    • Rename ADC overrun flags definitions : ADC_CSR_DOVR1, ADC_CSR_DOVR2 and ADC_CSR_DOVR3 are replaced respectively by ADC_CSR_OVR1, ADC_CSR_OVR2 and ADC_CSR_OVR3 to be aligned with reference manuals
      • +
    • Add missing bits definitions for DAC : DAC_CR_DMAUDRIE1 and DAC_CR_DMAUDRIE2
      • +
    • Update CMSIS driver to be compliant with MISRA C 2004 rule 10.6
      • +
    • Remove the double definition of USB_OTG_HS_MAX_IN_ENDPOINTS and add a new one for USB_OTG_HS_MAX_OUT_ENDPOINTS
      • +
    • +
  • stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files +
      +
    • Change the bit definition value of QUADSPI_CR_FTHRES
      • +
    • +
  • stm32f446xx.h, stm32f469xx.h, stm32f479xx.h, stm32f429xx.h, stm32f439xx.h files +
      +
    • Rename the LTDC_GCR_DTEN to LTDC_GCR_DEN in order to be aligned with the reference manual
      • +
    • Rename DCMI_MISR bit definitions to DCMI_MIS
      • +
    • Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
      • +
    • Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
      • +
    • +
  • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h files +
      +
    • Rename DCMI_MISR bit definitions to DCMI_MIS
      • +
    • Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
      • +
    • Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
      • +
    • +
  • stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files +
      +
    • Update the LPTIM SNGSTRT defined value
      • +
    • +
  • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files +
      +
    • Rename the DMA2D_IFSR bit definitions to DMA2D_IFCR
      • +
    • +
  • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files +
      +
    • Correct a wrong value of SAI_xCR2_CPL definition bit
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • system_stm32f4xx.c file +
      +
    • update SystemInit_ExtMemCtl() function implementation to allow the possibility of simultaneous use of DATA_IN_ExtSRAM and DATA_IN_ExtSDRAM
      • +
    • +
  • stm32f4xx.h file +
      +
    • add symbols for STM32F411xC devices
      • +
    • +
  • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files +
      +
    • add FSMC_BCRx_CPSIZE bits definitions
      • +
    • remove FSMC_BWTRx_CLKDIV and FSMC_BWTRx_DATLAT bits definitions
      • +
    • +
  • stm32f429xx.h, stm32f427xx.h, stm32f437xx.h files +
      +
    • add FMC_BCRx_CPSIZE bits definitions
      • +
    • remove FMC_BWTRx_CLKDIV and FMC_BWTRx_DATLAT bits definitions
      • +
    • +
  • stm32f446xx.h, stm32f469xx.h and stm32f479xx.h +
      +
    • update USB_OTG_GlobalTypeDef registers structure to remove ADP control registers
      • +
    • add USB_OTG_DOEPMSK_OTEPSPRM and USB_OTG_DOEPINT_OTEPSPR bits definitions
      • +
    • Remove ADP related bits definitions
      • +
    • add IS_PCD_ALL_INSTANCE() and IS_HCD_ALL_INSTANCE() macros
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • “stm32f469xx.hâ€, “stm32f479xx.h†+
      +
    • Update bits definition for DSI_WPCR and DSI_TCCR registers
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F469xx and STM32F479xx devices +
      +
    • Add “stm32f469xx.h†and “stm32f479xx.h†files
      • +
    • Add startup files “startup_stm32f469xx.s†and “startup_stm32f479xx.s†for EWARM, MDK-ARM and SW4STM32 toolchains
      • +
    • Add Linker files “stm32f469xx_flash.icfâ€, “stm32f469xx_sram.icfâ€, “stm32f479xx_flash.icf†and “stm32f479xx_sram.icf†used within EWARM Workspaces
      • +
    • +
  • Add support of STM32F410xx devices +
      +
    • Add “stm32f410cx.hâ€, “stm32f410tx.h†and “stm32f410rx.h†files
      • +
    • Add startup files “startup_stm32f410cx.sâ€, “startup_stm32f410rx.s†and “startup_stm32f410tx.s†for EWARM, MDK-ARM and SW4STM32 toolchains
      • +
    • Add Linker files “stm32f410cx_flash.icfâ€, “stm32f410cx_sram.icfâ€, “stm32f410rx_flash.icfâ€, “stm32f410tx_sram.icfâ€, “stm32f410tx_flash.icfâ€, and “stm32f410rx_sram.icf†used within EWARM Workspaces
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • “stm32f405xx.hâ€, “stm32f407xx.hâ€, “stm32f415xx.h†and “stm32f417xx.h†+
      +
    • Update FSMC_BTRx_DATAST and FSMC_BWTRx_DATAST (where x can be 1, 2, 3 and 4) mask on 8bits instead of 4bits
      • +
    • +
  • “stm32f427xx.hâ€, “stm32f437xx.hâ€, “stm32f429xx.h†and “stm32f439xx.h†+
      +
    • Update the defined mask value for SAI_xSR_FLVL_2
      • +
    • +
  • “stm32f415xx.hâ€, “stm32f417xx.hâ€, “stm32f437xx.h†and “stm32f439xx.h†+
      +
    • HASH alignement with bits namming used in documentation
      • +
    • Rename HASH_IMR_DINIM to HASH_IMR_DINIE
      • +
    • Rename HASH_IMR_DCIM to HASH_IMR_DCIE
      • +
    • Rename HASH_STR_NBW to HASH_STR_NBW
      • +
    • +
  • system_stm32f4xx.c +
      +
    • Remove __IO on constant table declaration
      • +
    • Implement workaround to cover RCC limitation regarding peripheral enable delay
      • +
    • SystemInit_ExtMemCtl() update GPIO configuration when external SDRAM is used
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Header file for all STM32 devices +
      +
    • Update SRAM2, SRAM3 and BKPSRAM Bit-Banding base address defined values
      • +
    • Keep reference to SRAM3 only for STM32F42xx and STM32F43xx devices
      • +
    • Remove CCMDATARAM_BB_BASE: the CCM Data RAM region is not accessible via Bit-Banding
      • +
    • Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of 0x00001FFF
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F446xx devices +
      +
    • Add “stm32f446xx.h†file
      • +
    • Add startup file “startup_stm32f446xx.s†for EWARM, MDK-ARM and TrueSTUDIO toolchains
      • +
    • Add Linker files “stm32f446xx_flash.icf†and “stm32f446xx_sram.icf†used within EWARM Workspaces
      • +
    • +
  • Header file for all STM32 devices +
      +
    • Add missing bits definition in the EXTI IMR, EMR, RTSR, FTSR, SWIER and PR registers
      • +
    • Update RCC_AHB1RSTR_OTGHRST bit definition
      • +
    • Update PWR_CR_VOS bits definition for STM32F40xx and STM32F41xx devices
      • +
    • update SAI_xCR1_MCKDIV bit definition
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • stm32f4xx.h +
      +
    • Add new constant definition STM32F4
      • +
    • +
  • system_stm32f4xx.c +
      +
    • Fix SDRAM configuration in SystemInit_ExtMemCtl(): change RowBitsNumber from 11 to 12 (for MT48LC4M32B2 available on STM324x9I_EVAL board)
      • +
    • +
  • Header file for all STM32 devices +
      +
    • Add missing bits definition for CAN, FMC and USB peripherals
      • +
    • GPIO_TypeDef: change the BSRR register definition, the two 16-bits definition BSRRH and BSRRL are merged in a single 32-bits definition BSRR
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F411xExx devices +
      +
    • Add “stm32f411xe.h†file
      • +
    • Add startup file “startup_stm32f411xx.s†for EWARM, MDK-ARM and TrueSTUDIO toolchains
      • +
    • +
  • All header files +
      +
    • Add missing defines for GPIO LCKR Register
      • +
    • Add defines for memories base and end addresses: FLASH, SRAM, BKPSRAM and CCMRAM.
      • +
    • Add the following aliases for IRQ number and handler definition to ensure compatibility across the product lines of STM32F4 Series; +
        +

      • example for STM32F405xx.h

        +

        #define FMC_IRQn FSMC_IRQn #define FMC_IRQHandler FSMC_IRQHandler

        • +

      • and for STM32F427xx.h

        +

        #define FSMC_IRQn FMC_IRQn #define FSMC_IRQHandler FMC_IRQHandler

        • +
      • +
    • +
  • “stm32f401xc.h†and “stm32f401xe.hâ€: update to be in line with latest version of the Reference manual +
      +
    • Remove RNG registers structures and the corresponding bit definitions
      • +
    • Remove any occurrence to RNG (clock enable, clock reset,…)
      • +
    • Add the following bit definition for PWR CR registerAdd the following bit definition for PWR CR register +
        +
      • #define PWR_CR_ADCDC1 ((uint32_t)0x00002000)
        • +
      • #define PWR_CR_LPLVDS ((uint32_t)0x00000400)
        • +
      • #define PWR_CR_MRLVDS ((uint32_t)0x00000800)
        • +
      • +
    • +
  • “stm32f427xx.hâ€, “stm32f437xx.hâ€, “stm32f429xx.h†and “stm32f439xx.h†+
      +
    • Add a new legacy bit definition for PWR to be in line with latest version of the Reference manual +
        +
      • #define PWR_CR_LPUDS PWR_CR_LPLVDS
        • +
      • #define PWR_CR_MRUDS PWR_CR_MRLVDS
        • +
      • +
    • +
  • Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version
    • +
  • system_stm32f4xx.c +
      +
    • Remove dependency vs. the HAL, to allow using this file without the need to have the HAL drivers +
        +
      • Include stm32f4xx.h instead of stm32f4xx_hal.h
        • +
      • Add definition of HSE_VALUE and HSI_VALUE, if they are not yet defined in the compilation scope (these values are defined in stm32f4xx_hal_conf).
        • +
      • +
    • Use “__IO const†instead of “__Iâ€, to avoid any compilation issue when __cplusplus switch is defined
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Update based on STM32Cube specification
    • +
  • This version and later has to be used only with STM32CubeF4 based development
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F401xExx devices
    • +
  • Update startup files “startup_stm32f401xx.s†for EWARM, MDK-ARM, TrueSTUDIO and Ride toolchains: Add SPI4 interrupt handler entry in the vector table
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • system_stm32f4xx.c : Update FMC SDRAM configuration (RBURST mode activation)
    • +
  • Update startup files “startup_stm32f427_437xx.s†and “startup_stm32f429_439xx.s†for TrueSTUDIO and Ride toolchains and maintain the old name of startup files for legacy purpose
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add support of STM32F429/439xx and STM32F401xCxx devices
    • +
  • Update definition of STM32F427/437xx devices : extension of the features to include system clock up to 180MHz, dual bank Flash, reduced STOP Mode current, SAI, PCROP, SDRAM and DMA2D
    • +
  • stm32f4xx.h +
      +
    • Add the following device defines : +
        +
      • “#define STM32F40_41xxx†for all STM32405/415/407/417xx devices
        • +
      • “#define STM32F427_437xx†for all STM32F427/437xx devices
        • +
      • “#define STM32F429_439xx†for all STM32F429/439xx devices
        • +
      • “#define STM32F401xx†for all STM32F401xx devices
        • +
      • +
    • Maintain the old device define for legacy purpose
      • +
    • Update IRQ handler enumeration structure to support all STM32F4xx Family devices.
      • +
    • +
  • Add new startup files “startup_stm32f40_41xxx.sâ€,“startup_stm32f427_437xx.sâ€, “startup_stm32f429_439xx.s†and “startup_stm32f401xx.s†for all toolchains and maintain the old name for startup files for legacy purpose
    • +
  • system_stm32f4xx.c +
      +
    • Update the system configuration to support all STM32F4xx Family devices.
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Official release for STM32F427x/437x devices.
    • +
  • stm32f4xx.h +
      +
    • Update product define: replace “#define STM32F4XX†by “#define STM32F40XX†for STM32F40x/41x devices
      • +
    • Add new product define: “#define STM32F427X†for STM32F427x/437x devices.
      • +
    • +
  • Add new startup files “startup_stm32f427x.s†for all toolchains
    • +
  • rename startup files “startup_stm32f4xx.s†by “startup_stm32f40xx.s†for all toolchains
    • +
  • system_stm32f4xx.c +
      +
    • Prefetch Buffer enabled
      • +
    • Add reference to STM32F427x/437x devices and STM324x7I_EVAL board
      • +
    • SystemInit_ExtMemCtl() function +
        +
      • Add configuration of missing FSMC address and data lines
        • +
      • Change memory type to SRAM instead of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update timing values
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • All source files: update disclaimer to add reference to the new license agreement
    • +
  • stm32f4xx.h +
      +
    • Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • First official release for STM32F40x/41x devices
    • +
  • Add startup file for TASKING toolchain
    • +
  • system_stm32f4xx.c: driver’s comments update
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
    • +
  • stm32f4xx.h +
      +
    • Add define for Cortex-M4 revision __CM4_REV
      • +
    • Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
      • +
    • Correct some bits definition to be in line with naming used in the Reference Manual (RM0090) +
        +
      • GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
        • +
      • GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
        • +
      • SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
        • +
      • RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
        • +
      • DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
        • +
      • PWR_CR_PMODE changed to PWR_CR_VOS
        • +
      • PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
        • +
      • Add new define RCC_AHB1ENR_CCMDATARAMEN
        • +
      • Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
        • +
      • +
    • GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
      • +
    • +
  • system_stm32f4xx.c +
      +
    • SystemInit(): add code to enable the FPU
      • +
    • SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
      • +
    • SystemInit_ExtMemCtl(): remove commented values
      • +
    • +
  • startup (for all compilers) +
      +
    • Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
      • +
    • File’s header updated
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
    • +
+
+
+
+
+ + + diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s index 7368496c05..0e29dd6eaa 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -228,6 +228,9 @@ g_pfnVectors: .word 0 /* Reserved */ .word SPI4_IRQHandler /* SPI4 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s index 6272f36289..e0f69baf33 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -228,6 +228,9 @@ g_pfnVectors: .word 0 /* Reserved */ .word SPI4_IRQHandler /* SPI4 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s index e463fb3ffd..917d243a89 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors @@ -229,6 +229,9 @@ g_pfnVectors: .word FPU_IRQHandler /* FPU */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s index 714d3c4faa..24fa922d1c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -227,6 +227,9 @@ g_pfnVectors: .word FPU_IRQHandler /* FPU */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s index fdcab8fef2..42977bc99c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -241,6 +241,9 @@ g_pfnVectors: .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ .word LPTIM1_IRQHandler /* LP TIM1 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s index 0d86852a3a..2821128c40 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -241,6 +241,9 @@ g_pfnVectors: .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ .word LPTIM1_IRQHandler /* LP TIM1 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s index bb60d6b52c..861a1a934a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -241,6 +241,9 @@ g_pfnVectors: .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ .word LPTIM1_IRQHandler /* LP TIM1 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s index 1b86625e56..bae927c286 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -229,6 +229,9 @@ g_pfnVectors: .word SPI4_IRQHandler /* SPI4 */ .word SPI5_IRQHandler /* SPI5 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s index d20795efb6..9dcd71e697 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -240,6 +240,9 @@ g_pfnVectors: .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s index 1f34976a14..9f41f4f28e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -240,6 +240,9 @@ g_pfnVectors: .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s index 45cbf1797e..903447b378 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -240,6 +240,9 @@ g_pfnVectors: .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s index c11f39a943..117509d30d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -240,6 +240,9 @@ g_pfnVectors: .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s index eeac1ed141..3d2871a023 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -245,6 +245,9 @@ g_pfnVectors: .word DFSDM2_FLT2_IRQHandler /* DFSDM2 Filter2 */ .word DFSDM2_FLT3_IRQHandler /* DFSDM2 Filter3 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s index 871c499a85..f5201e08e3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -227,6 +227,9 @@ g_pfnVectors: .word FPU_IRQHandler /* FPU */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s index 2bbdc4e869..bbcc0326d3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -227,6 +227,9 @@ g_pfnVectors: .word FPU_IRQHandler /* FPU */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s index e15f80752b..e78d8bf368 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -245,6 +245,9 @@ g_pfnVectors: .word DFSDM2_FLT2_IRQHandler /* DFSDM2 Filter2 */ .word DFSDM2_FLT3_IRQHandler /* DFSDM2 Filter3 */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s index 4024d88346..e390ea5f08 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -235,6 +235,9 @@ g_pfnVectors: .word 0 /* Reserved */ .word 0 /* Reserved */ .word DMA2D_IRQHandler /* DMA2D */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s index 245231d818..56f5289cf6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -235,6 +235,9 @@ g_pfnVectors: .word LTDC_ER_IRQHandler /* LTDC_ER_IRQHandler */ .word DMA2D_IRQHandler /* DMA2D */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s index ac5dccd55f..d32ab6eb36 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit + /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +123,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -235,6 +236,9 @@ g_pfnVectors: .word 0 /* Reserved */ .word DMA2D_IRQHandler /* DMA2D */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s index 36ed7ac4af..09885e4708 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -237,6 +237,9 @@ Infinite_Loop: + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s index 41fb9f4557..eef0783487 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -242,6 +242,9 @@ g_pfnVectors: .word FMPI2C1_EV_IRQHandler /* FMPI2C 1 Event */ .word FMPI2C1_ER_IRQHandler /* FMPI2C 1 Error */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s index d5470fa41f..d6481b6658 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -238,6 +238,9 @@ Infinite_Loop: .word DSI_IRQHandler /* DSI */ + + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s index 9878def15f..02ab141d15 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s @@ -60,6 +60,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -91,8 +94,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -121,7 +122,6 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, 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z{r{JbyvQGZzbyvPS}zAifbhF49z~X|@9v|!=No>qsF|P~vf=g>7#%0yk<U?Ha8*Z4HW>#8w>z$A3 z>^uQlk;$a-6CQ(uc@RM)Cbss!xuPVl2@c1u-5tEUw}U8OfP_J+QYhfu$B<0Cj3xm7 c?*aZZ00ulYFs-m=@&Et;07*qoM6N<$f~=14i~s-t literal 0 HcmV?d00001 diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/mini-st.css b/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/mini-st_2020.css similarity index 77% rename from system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/mini-st.css rename to system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/mini-st_2020.css index eb41d56c4d..db8b406aa4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/mini-st.css +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/mini-st_2020.css @@ -1,39 +1,39 @@ @charset "UTF-8"; /* - Flavor name: Default (mini-default) - Author: Angelos Chalaris (chalarangelo@gmail.com) - Maintainers: Angelos Chalaris - mini.css version: v3.0.0-alpha.3 + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 */ /* Browsers resets and base typography. */ /* Core module CSS variable definitions */ :root { - --fore-color: #111; - --secondary-fore-color: #444; - --back-color: #f8f8f8; - --secondary-back-color: #f0f0f0; - --blockquote-color: #f57c00; - --pre-color: #1565c0; - --border-color: #aaa; - --secondary-border-color: #ddd; - --heading-ratio: 1.19; + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; --universal-margin: 0.5rem; - --universal-padding: 0.125rem; - --universal-border-radius: 0.125rem; - --a-link-color: #0277bd; - --a-visited-color: #01579b; } + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } html { - font-size: 14px; } + font-size: 13.5px; } a, b, del, em, i, ins, q, span, strong, u { font-size: 1em; } html, * { - font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; - line-height: 1.4; + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; -webkit-text-size-adjust: 100%; } * { @@ -42,7 +42,10 @@ html, * { body { margin: 0; color: var(--fore-color); - background: var(--back-color); } + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } details { display: block; } @@ -62,9 +65,9 @@ img { height: auto; } h1, h2, h3, h4, h5, h6 { - line-height: 1.2; + line-height: 1.25; margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - font-weight: 500; } + font-weight: 400; } h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { color: var(--secondary-fore-color); display: block; @@ -74,21 +77,15 @@ h1 { font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } h2 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); - background: var(--mark-back-color); - font-weight: 600; - padding: 0.1em 0.5em 0.2em 0.5em; - color: var(--mark-fore-color); } - + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } h3 { - font-size: calc(1rem * var(--heading-ratio)); - padding-left: calc(2 * var(--universal-margin)); - /* background: var(--border-color); */ - } + font-size: calc(1rem * var(--heading-ratio) ); } h4 { - font-size: 1rem;); - padding-left: calc(4 * var(--universal-margin)); } + font-size: calc(1rem * var(--heading-ratio)); } h5 { font-size: 1rem; } @@ -101,7 +98,7 @@ p { ol, ul { margin: var(--universal-margin); - padding-left: calc(6 * var(--universal-margin)); } + padding-left: calc(3 * var(--universal-margin)); } b, strong { font-weight: 700; } @@ -111,7 +108,7 @@ hr { border: 0; line-height: 1.25em; margin: var(--universal-margin); - height: 0.0625rem; + height: 0.0714285714rem; background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } blockquote { @@ -121,16 +118,16 @@ blockquote { color: var(--secondary-fore-color); margin: var(--universal-margin); padding: calc(3 * var(--universal-padding)); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.375rem solid var(--blockquote-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } blockquote:before { position: absolute; top: calc(0rem - var(--universal-padding)); left: 0; font-family: sans-serif; - font-size: 3rem; - font-weight: 700; + font-size: 2rem; + font-weight: 800; content: "\201c"; color: var(--blockquote-color); } blockquote[cite]:after { @@ -160,8 +157,8 @@ pre { background: var(--secondary-back-color); padding: calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.25rem solid var(--pre-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } sup, sub, code, kbd { @@ -204,7 +201,8 @@ a { box-sizing: border-box; display: flex; flex: 0 1 auto; - flex-flow: row wrap; } + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } .col-sm, [class^='col-sm-'], @@ -565,9 +563,9 @@ a { order: 999; } } /* Card component CSS variable definitions */ :root { - --card-back-color: #f8f8f8; - --card-fore-color: #111; - --card-border-color: #ddd; } + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } .card { display: flex; @@ -578,7 +576,7 @@ a { width: 100%; background: var(--card-back-color); color: var(--card-fore-color); - border: 0.0625rem solid var(--card-border-color); + border: 0.0714285714rem solid var(--card-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); overflow: hidden; } @@ -592,7 +590,7 @@ a { margin: 0; border: 0; border-radius: 0; - border-bottom: 0.0625rem solid var(--card-border-color); + border-bottom: 0.0714285714rem solid var(--card-border-color); padding: var(--universal-padding); width: 100%; } .card > .sectione.media { @@ -617,17 +615,18 @@ a { width: auto; } .card.warning { -/* --card-back-color: #ffca28; */ --card-back-color: #e5b8b7; - --card-border-color: #e8b825; } + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } .card.error { - --card-back-color: #b71c1c; - --card-fore-color: #f8f8f8; - --card-border-color: #a71a1a; } + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } .card > .sectione.dark { - --card-back-color: #e0e0e0; } + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } .card > .sectione.double-padded { padding: calc(1.5 * var(--universal-padding)); } @@ -637,12 +636,12 @@ a { */ /* Input_control module CSS variable definitions */ :root { - --form-back-color: #f0f0f0; - --form-fore-color: #111; - --form-border-color: #ddd; - --input-back-color: #f8f8f8; - --input-fore-color: #111; - --input-border-color: #ddd; + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; --input-focus-color: #0288d1; --input-invalid-color: #d32f2f; --button-back-color: #e2e2e2; @@ -655,13 +654,13 @@ a { form { background: var(--form-back-color); color: var(--form-fore-color); - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); padding: calc(2 * var(--universal-padding)) var(--universal-padding); } fieldset { - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 4); padding: var(--universal-padding); } @@ -671,7 +670,7 @@ legend { display: table; max-width: 100%; white-space: normal; - font-weight: 700; + font-weight: 500; padding: calc(var(--universal-padding) / 2); } label { @@ -716,7 +715,7 @@ input:not([type]), [type="text"], [type="email"], [type="number"], [type="search box-sizing: border-box; background: var(--input-back-color); color: var(--input-fore-color); - border: 0.0625rem solid var(--input-border-color); + border: 0.0714285714rem solid var(--input-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 2); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } @@ -763,8 +762,8 @@ option { [type="radio"]:checked:before { border-radius: 100%; content: ''; - top: calc(0.0625rem + var(--universal-padding) / 2); - left: calc(0.0625rem + var(--universal-padding) / 2); + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); background: var(--input-fore-color); width: 0.5rem; height: 0.5rem; } @@ -793,7 +792,7 @@ a[role="button"], label[role="button"], [role="button"] { display: inline-block; background: var(--button-back-color); color: var(--button-fore-color); - border: 0.0625rem solid var(--button-border-color); + border: 0.0714285714rem solid var(--button-border-color); border-radius: var(--universal-border-radius); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); @@ -814,7 +813,7 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d .button-group { display: flex; - border: 0.0625rem solid var(--button-group-border-color); + border: 0.0714285714rem solid var(--button-group-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { @@ -826,13 +825,13 @@ input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:d border-radius: 0; box-shadow: none; } .button-group > :not(:first-child) { - border-left: 0.0625rem solid var(--button-group-border-color); } + border-left: 0.0714285714rem solid var(--button-group-border-color); } @media screen and (max-width: 499px) { .button-group { flex-direction: column; } .button-group > :not(:first-child) { border: 0; - border-top: 0.0625rem solid var(--button-group-border-color); } } + border-top: 0.0714285714rem solid var(--button-group-border-color); } } /* Custom elements for forms and input elements. @@ -874,29 +873,29 @@ button.large, [type="button"].large, [type="submit"].large, [type="reset"].large */ /* Navigation module CSS variable definitions */ :root { - --header-back-color: #f8f8f8; - --header-hover-back-color: #f0f0f0; - --header-fore-color: #444; - --header-border-color: #ddd; - --nav-back-color: #f8f8f8; - --nav-hover-back-color: #f0f0f0; - --nav-fore-color: #444; - --nav-border-color: #ddd; - --nav-link-color: #0277bd; - --footer-fore-color: #444; - --footer-back-color: #f8f8f8; - --footer-border-color: #ddd; - --footer-link-color: #0277bd; - --drawer-back-color: #f8f8f8; - --drawer-hover-back-color: #f0f0f0; - --drawer-border-color: #ddd; - --drawer-close-color: #444; } + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } header { - height: 3.1875rem; + height: 2.75rem; background: var(--header-back-color); color: var(--header-fore-color); - border-bottom: 0.0625rem solid var(--header-border-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); padding: calc(var(--universal-padding) / 4) 0; white-space: nowrap; overflow-x: auto; @@ -927,7 +926,7 @@ header { nav { background: var(--nav-back-color); color: var(--nav-fore-color); - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } nav * { @@ -946,10 +945,10 @@ nav { nav .sublink-1:before { position: absolute; left: calc(var(--universal-padding) - 1 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } nav .sublink-2 { position: relative; @@ -957,16 +956,16 @@ nav { nav .sublink-2:before { position: absolute; left: calc(var(--universal-padding) - 3 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } footer { background: var(--footer-back-color); color: var(--footer-fore-color); - border-top: 0.0625rem solid var(--footer-border-color); + border-top: 0.0714285714rem solid var(--footer-border-color); padding: calc(2 * var(--universal-padding)) var(--universal-padding); font-size: 0.875rem; } footer a, footer a:visited { @@ -1013,7 +1012,7 @@ footer.sticky { height: 100vh; overflow-y: auto; background: var(--drawer-back-color); - border: 0.0625rem solid var(--drawer-border-color); + border: 0.0714285714rem solid var(--drawer-border-color); border-radius: 0; margin: 0; z-index: 1110; @@ -1060,38 +1059,36 @@ footer.sticky { */ /* Table module CSS variable definitions. */ :root { - --table-border-color: #aaa; - --table-border-separator-color: #666; - --table-head-back-color: #e6e6e6; - --table-head-fore-color: #111; - --table-body-back-color: #f8f8f8; - --table-body-fore-color: #111; - --table-body-alt-back-color: #eee; } + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } table { border-collapse: separate; border-spacing: 0; - : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + margin: 0; display: flex; flex: 0 1 auto; flex-flow: row wrap; padding: var(--universal-padding); - padding-top: 0; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + padding-top: 0; } table caption { - font-size: 1.25 * rem; + font-size: 1rem; margin: calc(2 * var(--universal-margin)) 0; max-width: 100%; - flex: 0 0 100%; - text-align: left;} + flex: 0 0 100%; } table thead, table tbody { display: flex; flex-flow: row wrap; - border: 0.0625rem solid var(--table-border-color); } + border: 0.0714285714rem solid var(--table-border-color); } table thead { z-index: 999; border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; - border-bottom: 0.0625rem solid var(--table-border-separator-color); } + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } table tbody { border-top: 0; margin-top: calc(0 - var(--universal-margin)); @@ -1109,11 +1106,11 @@ table { table td { background: var(--table-body-back-color); color: var(--table-body-fore-color); - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table:not(.horizontal) { overflow: auto; - max-height: 850px; } + max-height: 100%; } table:not(.horizontal) thead, table:not(.horizontal) tbody { max-width: 100%; flex: 0 0 100%; } @@ -1134,32 +1131,33 @@ table.horizontal { border: 0; } table.horizontal thead, table.horizontal tbody { border: 0; + flex: .2 0 0; flex-flow: row nowrap; } table.horizontal tbody { overflow: auto; justify-content: space-between; - flex: 1 0 0; - margin-left: calc( 4 * var(--universal-margin)); + flex: .8 0 0; + margin-left: 0; padding-bottom: calc(var(--universal-padding) / 4); } table.horizontal tr { flex-direction: column; flex: 1 0 auto; } table.horizontal th, table.horizontal td { - width: 100%; + width: auto; border: 0; - border-bottom: 0.0625rem solid var(--table-border-color); } + border-bottom: 0.0714285714rem solid var(--table-border-color); } table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { border-top: 0; } table.horizontal th { text-align: right; - border-left: 0.0625rem solid var(--table-border-color); - border-right: 0.0625rem solid var(--table-border-separator-color); } + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } table.horizontal thead tr:first-child { padding-left: 0; } table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td { - border-right: 0.0625rem solid var(--table-border-color); } + border-right: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td:first-child { border-top-right-radius: 0.25rem; } table.horizontal tbody tr:last-child td:last-child { @@ -1191,12 +1189,12 @@ table.horizontal { display: table-row-group; } table tr, table.horizontal tr { display: block; - border: 0.0625rem solid var(--table-border-color); + border: 0.0714285714rem solid var(--table-border-color); border-radius: var(--universal-border-radius); - background: #fafafa; + background: #ffffff; padding: var(--universal-padding); margin: var(--universal-margin); - margin-bottom: calc(2 * var(--universal-margin)); } + margin-bottom: calc(1 * var(--universal-margin)); } table th, table td, table.horizontal th, table.horizontal td { width: auto; } table td, table.horizontal td { @@ -1211,9 +1209,6 @@ table.horizontal { border-top: 0; } table tbody tr:last-child td, table.horizontal tbody tr:last-child td { border-right: 0; } } -:root { - --table-body-alt-back-color: #eee; } - table tr:nth-of-type(2n) > td { background: var(--table-body-alt-back-color); } @@ -1234,8 +1229,8 @@ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focu */ /* Contextual module CSS variable definitions */ :root { - --mark-back-color: #0277bd; - --mark-fore-color: #fafafa; } + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } mark { background: var(--mark-back-color); @@ -1243,11 +1238,11 @@ mark { font-size: 0.95em; line-height: 1em; border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } mark.inline-block { display: inline-block; font-size: 1em; - line-height: 1.5; + line-height: 1.4; padding: calc(var(--universal-padding) / 2) var(--universal-padding); } :root { @@ -1314,8 +1309,8 @@ mark { :root { --modal-overlay-color: rgba(0, 0, 0, 0.45); - --modal-close-color: #444; - --modal-close-hover-color: #f0f0f0; } + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } [type="checkbox"].modal { height: 1px; @@ -1368,13 +1363,14 @@ mark { z-index: 1211; } :root { - --collapse-label-back-color: #e8e8e8; - --collapse-label-fore-color: #212121; - --collapse-label-hover-back-color: #f0f0f0; - --collapse-selected-label-back-color: #ececec; - --collapse-border-color: #ddd; - --collapse-content-back-color: #fafafa; - --collapse-selected-label-border-color: #0277bd; } + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } .collapse { width: calc(100% - 2 * var(--universal-margin)); @@ -1395,13 +1391,13 @@ mark { .collapse > label { flex-grow: 1; display: inline-block; - height: 1.5rem; + height: 1.25rem; cursor: pointer; - transition: background 0.3s; + transition: background 0.2s; color: var(--collapse-label-fore-color); background: var(--collapse-label-back-color); - border: 0.0625rem solid var(--collapse-border-color); - padding: calc(1.5 * var(--universal-padding)); } + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } .collapse > label:hover, .collapse > label:focus { background: var(--collapse-label-hover-back-color); } .collapse > label + div { @@ -1418,7 +1414,7 @@ mark { max-height: 1px; } .collapse > :checked + label { background: var(--collapse-selected-label-back-color); - border-bottom-color: var(--collapse-selected-label-border-color); } + border-color: var(--collapse-selected-label-border-color); } .collapse > :checked + label + div { box-sizing: border-box; position: relative; @@ -1427,13 +1423,13 @@ mark { overflow: auto; margin: 0; background: var(--collapse-content-back-color); - border: 0.0625rem solid var(--collapse-border-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); border-top: 0; padding: var(--universal-padding); clip: auto; -webkit-clip-path: inset(0%); clip-path: inset(0%); - max-height: 850px; } + max-height: 100%; } .collapse > label:not(:first-of-type) { border-top: 0; } .collapse > label:first-of-type { @@ -1450,11 +1446,8 @@ mark { /* Custom elements for contextual background elements, toasts and tooltips. */ -mark.secondary { - --mark-back-color: #d32f2f; } - mark.tertiary { - --mark-back-color: #308732; } + --mark-back-color: #3cb4e6; } mark.tag { padding: calc(var(--universal-padding)/2) var(--universal-padding); @@ -1465,7 +1458,7 @@ mark.tag { */ /* Progress module CSS variable definitions */ :root { - --progress-back-color: #ddd; + --progress-back-color: #3cb4e6; --progress-fore-color: #555; } progress { @@ -1558,45 +1551,53 @@ span[class^='icon-'] { filter: invert(100%); } span.icon-alert { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } span.icon-bookmark { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-calendar { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-credit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-edit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } span.icon-link { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } span.icon-help { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } span.icon-home { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-info { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } span.icon-lock { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } span.icon-mail { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-location { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-phone { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-rss { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-search { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } span.icon-settings { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 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r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } span.icon-cart { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } span.icon-upload { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } span.icon-user { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } /* Definitions for utilities and helper classes. @@ -1604,7 +1605,7 @@ span.icon-user { /* Utility module CSS variable definitions */ :root { --generic-border-color: rgba(0, 0, 0, 0.3); - --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } .hidden { display: none !important; } @@ -1622,7 +1623,7 @@ span.icon-user { overflow: hidden !important; } .bordered { - border: 0.0625rem solid var(--generic-border-color) !important; } + border: 0.0714285714rem solid var(--generic-border-color) !important; } .rounded { border-radius: var(--universal-border-radius) !important; } @@ -1697,4 +1698,14 @@ span.icon-user { clip-path: inset(100%) !important; overflow: hidden !important; } } -/*# sourceMappingURL=mini-default.css.map */ +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/st_logo.png b/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/st_logo.png deleted file mode 100644 index 8b80057fd3a454a97de1c9d732b7fede82c83227..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 18616 zcmbTd^-~<*6D~X~?jgaQV8LAj0X_tm1Ydk1xVy{Z3GPmS;IP2r4oh%%cMl#Qcz~Pl zz5l>lZ`GVRHB&V|boY7A^z(F|Z=Y4=aIwg-006*MkpHOuZ?5<^0x;12-SsK9!v0Mt zmQpHG08kT${nrHb-!rC@ysj$%ki7ceKq56ESOEZeJ%x`_nqEey{^(v>eK${gL>pJ% zX8+KBAR_W-jhDrs{egi|sP<73DP`UFoa(>xj;8qknEx2bL~2@t%3k>}hnl@CWQrW@ zqfK>@e3$sL-m%ftg0YAkk!@=P!Ognuz(zhb|Tux{FeX<<7(5oLVU8=W*sUZ*$TqlSb6o1O0a zzeP#ZW!;?#>0N5v?0D|q?mzD8-<^@1V0FH{fY}2A9ooXbylcB6Y>PVo4nMxLi|AWA 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