Merge pull request #2353 from fpistm/STM32CubeWBA_update

chore(wba): update to latest STM32CubeWBA v1.3.1
stm32duino · Apr 30, 2024 · f31d070 · f31d070
2 parents 0588a96 + a887b4d
commit f31d070
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Showing 57 changed files with 953 additions and 390 deletions.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h
@@ -10295,6 +10295,10 @@ typedef struct
 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
                                                  ((INSTANCE) == TIM2_NS))
 
+/********* TIM Instances : supporting bitfield OCCS in SMCR register **********/
+#define IS_TIM_OCCS_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
+                                              ((INSTANCE) == TIM2_NS))
+
 /****************** TIM Instances : remapping capability **********************/
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
                                             ((INSTANCE) == TIM2_NS))

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h
@@ -14343,8 +14343,7 @@ typedef struct
                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
 
 /****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \
-                                                ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S))
 
 /****************** TIM Instances : supporting the break function *************/
 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
@@ -14530,6 +14529,11 @@ typedef struct
                                                  ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                  ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))
 
+/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
+#define IS_TIM_OCCS_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
+                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
+                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))
+
 /****************** TIM Instances : remapping capability **********************/
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
@@ -14563,9 +14567,9 @@ typedef struct
 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))
 
 /****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1_NS)  || ((__INSTANCE__) == TIM1_S) || \
-                                                ((__INSTANCE__) == TIM2_NS)  || ((__INSTANCE__) == TIM2_S) || \
-                                                ((__INSTANCE__) == TIM3_NS)  || ((__INSTANCE__) == TIM3_S))
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
+                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) || \
+                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))
 
 /****************************** TSC Instances *********************************/
 #define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S))
@@ -14791,8 +14795,7 @@ typedef struct
                                          ((INSTANCE) == TIM17_NS))
 
 /****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \
-                                               ((INSTANCE) == TIM3_NS))
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS)
 
 /****************** TIM Instances : supporting the break function *************/
 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
@@ -14974,9 +14977,16 @@ typedef struct
                                             ((INSTANCE) == TIM3_NS))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
-                                                 ((INSTANCE) == TIM2_NS)  || \
-                                                 ((INSTANCE) == TIM3_NS))
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)   || \
+                                                 ((INSTANCE) == TIM2_NS)   || \
+                                                 ((INSTANCE) == TIM3_NS)   || \
+                                                 ((INSTANCE) == TIM16_NS)  || \
+                                                 ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
+#define IS_TIM_OCCS_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
+                                              ((INSTANCE) == TIM2_NS)  || \
+                                              ((INSTANCE) == TIM3_NS))
 
 /****************** TIM Instances : remapping capability **********************/
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
@@ -15010,9 +15020,9 @@ typedef struct
 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       ((INSTANCE) == TIM1_NS)
 
 /****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1_NS)  || \
-                                                ((__INSTANCE__) == TIM2_NS)  || \
-                                                ((__INSTANCE__) == TIM3_NS))
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS))
 
 /****************************** TSC Instances *********************************/
 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS)

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h
@@ -15051,8 +15051,7 @@ typedef struct
                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
 
 /****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \
-                                                ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S))
 
 /****************** TIM Instances : supporting the break function *************/
 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
@@ -15238,6 +15237,11 @@ typedef struct
                                                  ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                  ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))
 
+/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
+#define IS_TIM_OCCS_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
+                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
+                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))
+
 /****************** TIM Instances : remapping capability **********************/
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
@@ -15271,9 +15275,9 @@ typedef struct
 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))
 
 /****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1_NS)  || ((__INSTANCE__) == TIM1_S) || \
-                                                ((__INSTANCE__) == TIM2_NS)  || ((__INSTANCE__) == TIM2_S) || \
-                                                ((__INSTANCE__) == TIM3_NS)  || ((__INSTANCE__) == TIM3_S))
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
+                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) || \
+                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))
 
 /****************************** TSC Instances *********************************/
 #define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S))
@@ -15499,8 +15503,7 @@ typedef struct
                                          ((INSTANCE) == TIM17_NS))
 
 /****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \
-                                               ((INSTANCE) == TIM3_NS))
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS)
 
 /****************** TIM Instances : supporting the break function *************/
 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
@@ -15682,9 +15685,16 @@ typedef struct
                                             ((INSTANCE) == TIM3_NS))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
-                                                 ((INSTANCE) == TIM2_NS)  || \
-                                                 ((INSTANCE) == TIM3_NS))
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)   || \
+                                                 ((INSTANCE) == TIM2_NS)   || \
+                                                 ((INSTANCE) == TIM3_NS)   || \
+                                                 ((INSTANCE) == TIM16_NS)  || \
+                                                 ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
+#define IS_TIM_OCCS_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
+                                              ((INSTANCE) == TIM2_NS)  || \
+                                              ((INSTANCE) == TIM3_NS))
 
 /****************** TIM Instances : remapping capability **********************/
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
@@ -15718,9 +15728,9 @@ typedef struct
 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       ((INSTANCE) == TIM1_NS)
 
 /****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1_NS)  || \
-                                                ((__INSTANCE__) == TIM2_NS)  || \
-                                                ((__INSTANCE__) == TIM3_NS))
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS))
 
 /****************************** TSC Instances *********************************/
 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS)

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h
@@ -15069,8 +15069,7 @@ typedef struct
                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
 
 /****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \
-                                                ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S))
 
 /****************** TIM Instances : supporting the break function *************/
 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
@@ -15256,6 +15255,11 @@ typedef struct
                                                  ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                  ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))
 
+/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
+#define IS_TIM_OCCS_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
+                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
+                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))
+
 /****************** TIM Instances : remapping capability **********************/
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
@@ -15289,9 +15293,9 @@ typedef struct
 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))
 
 /****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1_NS)  || ((__INSTANCE__) == TIM1_S) || \
-                                                ((__INSTANCE__) == TIM2_NS)  || ((__INSTANCE__) == TIM2_S) || \
-                                                ((__INSTANCE__) == TIM3_NS)  || ((__INSTANCE__) == TIM3_S))
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
+                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) || \
+                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))
 
 /****************************** TSC Instances *********************************/
 #define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S))
@@ -15517,8 +15521,7 @@ typedef struct
                                          ((INSTANCE) == TIM17_NS))
 
 /****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \
-                                               ((INSTANCE) == TIM3_NS))
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS)
 
 /****************** TIM Instances : supporting the break function *************/
 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
@@ -15700,9 +15703,16 @@ typedef struct
                                             ((INSTANCE) == TIM3_NS))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
-                                                 ((INSTANCE) == TIM2_NS)  || \
-                                                 ((INSTANCE) == TIM3_NS))
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)   || \
+                                                 ((INSTANCE) == TIM2_NS)   || \
+                                                 ((INSTANCE) == TIM3_NS)   || \
+                                                 ((INSTANCE) == TIM16_NS)  || \
+                                                 ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
+#define IS_TIM_OCCS_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
+                                              ((INSTANCE) == TIM2_NS)  || \
+                                              ((INSTANCE) == TIM3_NS))
 
 /****************** TIM Instances : remapping capability **********************/
 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
@@ -15736,9 +15746,9 @@ typedef struct
 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       ((INSTANCE) == TIM1_NS)
 
 /****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1_NS)  || \
-                                                ((__INSTANCE__) == TIM2_NS)  || \
-                                                ((__INSTANCE__) == TIM3_NS))
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS))
 
 /****************************** TSC Instances *********************************/
 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS)

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h
@@ -61,7 +61,7 @@
   /* #define STM32WBA52xx */   /*!< STM32WBA52xx Devices */
   /* #define STM32WBA54xx */   /*!< STM32WBA54xx Devices */
   /* #define STM32WBA55xx */   /*!< STM32WBA55xx Devices */
-#endif /* !STM32WBA55xx && !STM32WBA52xx ...*/
+#endif /* !STM32WBA50xx && !STM32WBA52xx ...*/
 
 /*  Tip: To avoid modifying this file each time you need to switch between these
         devices, you can define the device in your toolchain compiler preprocessor.
@@ -79,7 +79,7 @@
   * @brief CMSIS Device version number
   */
 #define __STM32WBA_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32WBA_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32WBA_CMSIS_VERSION_SUB1   (0x03U) /*!< [23:16] sub1 version */
 #define __STM32WBA_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32WBA_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32WBA_CMSIS_VERSION       ((__STM32WBA_CMSIS_VERSION_MAIN << 24U)\