From ab04e6f086d2a6e2b99568954faa8a0ce86896f4 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 29 Apr 2024 17:07:45 +0200 Subject: [PATCH 1/3] system(WBA) update STM32WBAxx HAL Drivers to v1.3.0 Included in STM32CubeWBA FW v1.3.1 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 51 +++++-- .../Inc/stm32wbaxx_hal.h | 13 +- .../Inc/stm32wbaxx_hal_cortex.h | 4 + .../Inc/stm32wbaxx_hal_flash.h | 2 +- .../Inc/stm32wbaxx_hal_i2c_ex.h | 6 +- .../Inc/stm32wbaxx_hal_lptim.h | 1 + .../Inc/stm32wbaxx_hal_pwr.h | 6 +- .../Inc/stm32wbaxx_hal_rcc.h | 128 ++++++++++++---- .../Inc/stm32wbaxx_hal_rcc_ex.h | 62 ++++++-- .../Inc/stm32wbaxx_hal_rng_ex.h | 38 ++--- .../Inc/stm32wbaxx_hal_rtc.h | 4 +- .../Inc/stm32wbaxx_hal_rtc_ex.h | 16 +- .../Inc/stm32wbaxx_hal_smbus_ex.h | 6 +- .../Inc/stm32wbaxx_hal_tim.h | 11 +- .../Inc/stm32wbaxx_hal_tim_ex.h | 4 +- .../Inc/stm32wbaxx_hal_tsc.h | 30 +++- .../Inc/stm32wbaxx_hal_uart_ex.h | 6 +- .../Inc/stm32wbaxx_hal_usart.h | 2 +- .../Inc/stm32wbaxx_hal_usart_ex.h | 2 +- .../Inc/stm32wbaxx_ll_adc.h | 24 +-- .../Inc/stm32wbaxx_ll_cortex.h | 4 + .../Inc/stm32wbaxx_ll_i2c.h | 6 +- .../Inc/stm32wbaxx_ll_lptim.h | 1 + .../Inc/stm32wbaxx_ll_lpuart.h | 23 ++- .../Inc/stm32wbaxx_ll_rtc.h | 10 +- .../Inc/stm32wbaxx_ll_tim.h | 27 +++- .../Inc/stm32wbaxx_ll_usart.h | 12 +- .../STM32WBAxx_HAL_Driver/Release_Notes.html | 134 +++++++++++++---- .../Src/stm32wbaxx_hal.c | 70 ++++----- .../Src/stm32wbaxx_hal_adc.c | 10 +- .../Src/stm32wbaxx_hal_cortex.c | 100 ++++++++++--- .../Src/stm32wbaxx_hal_flash_ex.c | 4 +- .../Src/stm32wbaxx_hal_i2c.c | 93 ++++++++---- .../Src/stm32wbaxx_hal_rcc_ex.c | 137 +++++++++++++++++- .../Src/stm32wbaxx_hal_rng_ex.c | 10 +- .../Src/stm32wbaxx_hal_rtc.c | 1 + .../Src/stm32wbaxx_hal_smbus.c | 7 +- .../Src/stm32wbaxx_hal_smbus_ex.c | 3 + .../Src/stm32wbaxx_hal_tim.c | 37 +++-- .../Src/stm32wbaxx_hal_tim_ex.c | 18 ++- .../Src/stm32wbaxx_hal_tsc.c | 7 + .../Src/stm32wbaxx_ll_adc.c | 16 +- .../Src/stm32wbaxx_ll_rtc.c | 8 +- .../Src/stm32wbaxx_ll_tim.c | 4 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 45 files changed, 829 insertions(+), 331 deletions(-) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index f8322d1b40..d10f6f6f89 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -548,6 +548,16 @@ extern "C" { #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ /** * @} @@ -1239,10 +1249,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) +#if defined(STM32H5) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 */ +#endif /* STM32H5 || STM32H7RS */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1254,10 +1264,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1595,7 +1605,7 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ -#define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ /** * @} @@ -1989,12 +1999,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ /** * @} @@ -2309,8 +2319,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2343,8 +2353,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2401,8 +2411,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2419,7 +2429,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -3644,8 +3654,12 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) + defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3747,8 +3761,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3894,7 +3910,7 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4217,6 +4233,9 @@ extern "C" { #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h index 6e351d0168..018bc66144 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h @@ -79,7 +79,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @brief STM32WBAxx HAL Driver version number */ #define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBAxx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32WBAxx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\ @@ -423,15 +423,6 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @} */ -/** @defgroup HAL_Private_Macros HAL Private Macros - * @{ - */ -#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ - ((FREQ) == HAL_TICK_FREQ_100HZ) || \ - ((FREQ) == HAL_TICK_FREQ_1KHZ)) -/** - * @} - */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions @@ -516,7 +507,6 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); * @} */ - /** @addtogroup HAL_Exported_Functions_Group6 * @{ */ @@ -533,6 +523,7 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri * @} */ + /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h index 38b2480f14..8d0f9ac345 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h @@ -282,11 +282,15 @@ void HAL_SYSTICK_Callback(void); void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit); void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit); #ifdef MPU_NS void HAL_MPU_Enable_NS(uint32_t MPU_Control); void HAL_MPU_Disable_NS(void); +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber); +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber); void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit); void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit); #endif /* MPU_NS */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h index 4bba62cdc0..e05609fcc6 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h @@ -1017,7 +1017,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) -#define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x7F1U) != 0U) && (((CFG) & 0x1U) != 0U) && (((CFG) & 0xFFFFF80EU) == 0U)) +#define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x1B4U) != 0U) && (((CFG) & 0x4U) != 0U) && (((CFG) & 0xFFFFFE4BU) == 0U)) #define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((WMSEC) & OB_WMSEC_AREA1) != 0U) #endif /* __ARM_FEATURE_CMSE */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h index cc84e89e04..4309ee25ac 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h @@ -100,9 +100,9 @@ typedef struct * @{ */ #if defined(I2C1) -#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ -#endif /* I2C1 */ -#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ +#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 */ +#endif /* I2C1, I2C2 */ +#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3, I2C4 */ #if defined(I2C_TRIG_GRP1) #define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U)) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_lptim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_lptim.h index 9186ab7096..5b538734e6 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_lptim.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_lptim.h @@ -220,6 +220,7 @@ typedef struct __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ __IO HAL_LPTIM_ChannelStateTypeDef ChannelState[2]; /*!< LPTIM channel operation state */ + #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h index 71785bda28..6dd5188a43 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h @@ -375,7 +375,7 @@ typedef struct * (*) Feature not available on all devices of the family * @retval The state of __FLAG__ (TRUE or FALSE). */ -#if defined(PWR_FLAG_REGPARDYV11) +#if defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) #if defined(PWR_FLAG_REGS) #define __HAL_PWR_GET_FLAG(__FLAG__)( \ ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY)== \ @@ -423,8 +423,6 @@ typedef struct PWR_SVMSR_PVDO) : \ ((__FLAG__) == PWR_FLAG_REGPARDYVDDRFPA) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA)== \ PWR_RADIOSCR_REGPARDYVDDRFPA) : \ - ((__FLAG__) == PWR_FLAG_REGPARDYV11) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYV11)== \ - PWR_RADIOSCR_REGPARDYV11) : \ ((__FLAG__) == PWR_WAKEUP_FLAG1) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == \ PWR_WUSR_WUF1) : \ ((__FLAG__) == PWR_WAKEUP_FLAG2) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == \ @@ -466,7 +464,7 @@ typedef struct ((__FLAG__) == PWR_WAKEUP_FLAG7) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == \ PWR_WUSR_WUF7) : \ (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) -#endif /* defined(PWR_FLAG_REGPARDYV11) */ +#endif /*defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) */ /** @brief Clear PWR flags. * @param __FLAG__ : Specifies the flag to clear. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h index 3b9bb50e29..8ccc312fc0 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h @@ -403,6 +403,34 @@ typedef struct * @} */ +#if defined(RCC_CCIPR2_ASSEL) +/** @defgroup RCC_Interrupt Interrupts + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 000: CIFR register + * - 001: ASSR register + * @{ + */ +/* Flags in the CIFR register */ +#define RCC_IT_LSI1RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSI1RDYF_Pos) /*!< LSI1 Ready Interrupt flag */ +#define RCC_IT_LSERDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSERDYF_Pos) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSIRDYF_Pos) /*!< HSI16 Ready Interrupt flag */ +#define RCC_IT_HSERDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSERDYF_Pos) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLL1RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_PLL1RDYF_Pos) /*!< PLL1 Ready Interrupt flag */ +#define RCC_IT_CSS ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSECSSF_Pos) /*!< HSE32 Clock Security System Interrupt flag */ +#if defined(RCC_LSI2_SUPPORT) +#define RCC_IT_LSI2RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSI2RDYF_Pos) /*!< LSI2 Ready Interrupt flag */ +#endif /* RCC_BDCR1_LSI2ON */ + +/* Flags in the ASSR register */ +#define RCC_IT_CAPTURE_ERROR ((ASSR_REG_INDEX << 5U) | RCC_ASSR_CAEF_Pos) /*!< Capture Error Interrupt flag */ +#define RCC_IT_COMPARER ((ASSR_REG_INDEX << 5U) | RCC_ASSR_COF_Pos) /*!< Comparer Interrupt flag */ +#define RCC_IT_CAPTURE_TRIGGER ((ASSR_REG_INDEX << 5U) | RCC_ASSR_CAF_Pos) /*!< Capture Trigger Interrupt flag */ +/** + * @} + */ +#else /** @defgroup RCC_Interrupt Interrupts * @{ */ @@ -418,6 +446,7 @@ typedef struct /** * @} */ + #endif /* RCC_CCIPR2_ASSEL */ /** @defgroup RCC_Flag Flags * Elements values convention: XXXYYYYYb @@ -2078,64 +2107,106 @@ typedef struct * the selected interrupts). * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt - * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) + * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) +#if defined(RCC_CCIPR2_ASSEL) + * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) + * @arg @ref RCC_IT_COMPARER Comparer Interrupt flag(*) + * @arg @ref RCC_IT_CAPTURE_TRIGGER Capture Trigger Interrupt flag(*) +#endif * (*) Feature not available on all devices of the family * @retval None */ +#if defined(RCC_CCIPR2_ASSEL) +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ + SET_BIT(RCC->CIER,1U << ((__INTERRUPT__) & RCC_FLAG_MASK)) : \ + SET_BIT(RCC->ASIER,1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) +#else #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) +#endif /* RCC_CCIPR2_ASSEL */ /** * @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable * the selected interrupts). * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt - * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) + * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) +#if defined(RCC_CCIPR2_ASSEL) + * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) + * @arg @ref RCC_IT_COMPARER Comparer Interrupt flag(*) + * @arg @ref RCC_IT_CAPTURE_TRIGGER Capture Trigger Interrupt flag(*) +#endif * (*) Feature not available on all devices of the family * @retval None */ +#if defined(RCC_CCIPR2_ASSEL) +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ + CLEAR_BIT(RCC->CIER,1U << ((__INTERRUPT__) & RCC_FLAG_MASK)) : \ + CLEAR_BIT(RCC->ASIER,1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) +#else #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) +#endif /* RCC_CCIPR2_ASSEL */ /** * @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] * bits to clear the selected interrupt pending bits. * @param __INTERRUPT__: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt - * @arg @ref RCC_IT_CSS High speed external clock security system interrupt - * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) + * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) +#if defined(RCC_CCIPR2_ASSEL) + * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) + * @arg @ref RCC_IT_COMPARER Comparer Interrupt flag(*) + * @arg @ref RCC_IT_CAPTURE_TRIGGER Capture Trigger Interrupt flag(*) +#endif * (*) Feature not available on all devices of the family * @retval None */ +#if defined(RCC_CCIPR2_ASSEL) +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ + WRITE_REG(RCC->CICR,1U << ((__INTERRUPT__) & RCC_FLAG_MASK)) : \ + CLEAR_BIT(RCC->ASSR,1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) +#else #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) +#endif /* RCC_CCIPR2_ASSEL */ /** @brief Check whether the RCC interrupt has occurred or not. * @param __INTERRUPT__: specifies the RCC interrupt source to check. * This parameter can be one of the following values: - * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt - * @arg @ref RCC_IT_CSS High speed external clock security system interrupt - * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) + * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) +#if defined(RCC_CCIPR2_ASSEL) + * @arg @ref RCC_IT_CAPTURE_ERROR Capture Error Interrupt flag(*) + * @arg @ref RCC_IT_COMPARER Comparer Interrupt flag(*) + * @arg @ref RCC_IT_CAPTURE_TRIGGER Capture Trigger Interrupt flag(*) +#endif * (*) Feature not available on all devices of the family * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ +#if defined(RCC_CCIPR2_ASSEL) +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ + ((RCC->CIFR & (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) : \ + ((RCC->ASSR & (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1U << ((__INTERRUPT__) & RCC_FLAG_MASK)))) +#else #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) +#endif /* RCC_CCIPR2_ASSEL */ /** @brief Set RMVF bit to clear the reset flags. * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, @@ -2191,6 +2262,11 @@ typedef struct #define CR_REG_INDEX (1U) #define BDCR1_REG_INDEX (2U) #define CSR_REG_INDEX (3U) +#if defined(RCC_CCIPR2_ASSEL) +/* Defines used for Interrupt Flags */ +#define CIFR_REG_INDEX (0U) +#define ASSR_REG_INDEX (1U) +#endif /* RCC_CCIPR2_ASSEL */ #define RCC_FLAG_MASK (0x1FU) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h index 20e5dd3ad5..1bcbe2ff07 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h @@ -129,11 +129,27 @@ typedef struct uint32_t RadioSlpTimClockSelection; /*!< Specifies Radio Sleep Timer clock source. This parameter can be a value of @ref RCC_RadioSleepTimer_Clock_Source */ } RCC_PeriphCLKInitTypeDef; + +#if defined(RCC_CCIPR2_ASSEL) +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ +uint32_t CapturePrescaler; /*!< Capture Prescaler. + This parameter can ba a value between 0 and 0x7F */ +uint32_t ClockPrescaler; /*!< Clock Prescaler. + This parameter can ba a value between 0 and 0x7F */ +uint32_t AutoReloadValue; /*!< Auto-reload value. + This parameter can be a value between 0 and 0xFFFFF*/ +uint32_t CompareValue; /*!< Compare value. + This parameter can be a value between 0 and 0xFFFFF*/ +} RCC_AudioSyncConfigTypeDef; +#endif /* RCC_CCIPR2_ASSEL */ /** * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants * @{ @@ -255,7 +271,7 @@ typedef struct */ #define RCC_TIMICCLKSOURCE_HSI 0x00000000U /*!< HSI selected for Timer16/17 and LPTimer2 */ #define RCC_TIMICCLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL /*!< HSI/256 selected for Timer16/17 and LPTimer2 */ -/* +/** * @} */ @@ -760,11 +776,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions * @{ */ -/** @addtogroup RCCEx_Exported_Functions_Group1 +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions * @{ */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); @@ -774,7 +790,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); * @} */ -/** @addtogroup RCCEx_Exported_Functions_Group2 +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions * @{ */ void HAL_RCCEx_EnableLSECSS(void); @@ -793,7 +809,7 @@ void HAL_RCCEx_LSI2GetConfig(RCC_LSIConfigTypeDef *pConfig); * @} */ -/** @addtogroup RCCEx_Exported_Functions_Group3 +/** @defgroup RCCEx_Exported_Functions_Group3 Radio Clock management functions * @{ */ void HAL_RCCEx_EnableRadioBBClock(void); @@ -805,10 +821,26 @@ uint32_t HAL_RCCEx_GetRadioBusClockReadiness(void); * @} */ +#if defined(RCC_CCIPR2_ASSEL) +/** @defgroup RCCEx_Exported_Functions_Group4 Audio Synchronization management functions + * @{ + */ +void HAL_RCCEx_EnableAudioSyncClock(void); +void HAL_RCCEx_DisableAudioSyncClock(void); +HAL_StatusTypeDef HAL_RCCEx_SetConfigAudioSync(const RCC_AudioSyncConfigTypeDef *pConf); +void HAL_RCCEx_GetConfigAudioSync(RCC_AudioSyncConfigTypeDef *pConf); +uint32_t HAL_RCCEx_GetAudioSyncCounterValue(void); +uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); /** * @} */ -/** @addtogroup RCCEx_Private_Constants +#endif /* RCC_CCIPR2_ASSEL */ + +/** + * @} + */ + +/** @defgroup RCCEx_Private_Constants Private Constants * @{ */ /* Define used for IS_RCC_* macros below */ @@ -848,7 +880,7 @@ uint32_t HAL_RCCEx_GetRadioBusClockReadiness(void); */ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCCEx_Private_Macros +/** @defgroup RCCEx_Private_Macros Private Macros * @{ */ #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ @@ -964,6 +996,16 @@ uint32_t HAL_RCCEx_GetRadioBusClockReadiness(void); ((__MODE__) == RCC_LSI2_MODE_ULP)) #endif /* RCC_BDCR1_LSI2ON */ +#if defined(RCC_CCIPR2_ASSEL) +#define IS_RCC_AUDIOSYNC_CAPTUREPRESCALER(__PRESCALER__) ((__PRESCALER__) <= (RCC_ASCR_CPS >> RCC_ASCR_CPS_Pos)) + +#define IS_RCC_AUDIOSYNC_CLOCKPRESCALER(__PRESCALER__) ((__PRESCALER__) <= (RCC_ASCR_PSC >> RCC_ASCR_PSC_Pos)) + +#define IS_RCC_AUDIOSYNC_AUTORELOAD(__VALUE__) ((__VALUE__) <= (RCC_ASARR_AR >> RCC_ASARR_AR_Pos)) + +#define IS_RCC_AUDIOSYNC_COMPARE(__VALUE__) ((__VALUE__) <= (RCC_ASCOR_CO >> RCC_ASCOR_CO_Pos)) +#endif /* RCC_CCIPR2_ASSEL */ + /** * @} */ @@ -976,10 +1018,6 @@ uint32_t HAL_RCCEx_GetRadioBusClockReadiness(void); * @} */ -/** -* @} -*/ - #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng_ex.h index 6cc6a399f0..def3c5e2fd 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,11 +55,11 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs - value of @ref RNG_Ex_Auto_Reset */ + value of @ref RNGEx_Auto_Reset */ uint32_t HealthTest; /*!< RNG health test control must be a value between 0x0FFCABFF and 0x00005200 */ } RNG_ConfigTypeDef; @@ -69,11 +69,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -112,7 +112,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -121,7 +121,7 @@ typedef struct /** * @} */ -/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration +/** @defgroup RNGEx_Auto_Reset Auto Reset configuration * @{ */ #define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ @@ -136,7 +136,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -145,7 +145,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -154,7 +154,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -163,7 +163,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -202,7 +202,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -211,11 +211,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -226,7 +226,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc.h index eea5b45652..6d974881ed 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc.h @@ -713,8 +713,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @retval None */ #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ - ((__FLAG__) == RTC_FLAG_ALRAF) ? (SET_BIT(RTC->SCR, RTC_SCR_CALRAF)):\ - ((__FLAG__) == RTC_FLAG_ALRBF) ? (SET_BIT(RTC->SCR, RTC_SCR_CALRBF)):\ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CALRAF)):\ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CALRBF)):\ (0U)) /* Dummy action because is an invalid parameter value */ /** diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h index dc6227d0b3..bf7e6fa2bb 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h @@ -637,7 +637,6 @@ typedef struct * @} */ - /** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition * @{ */ @@ -1027,7 +1026,7 @@ typedef struct * @arg @ref RTC_FLAG_WUTF * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CWUTF)) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG(RTC->SCR, RTC_SCR_CWUTF)) /** * @} @@ -1116,8 +1115,8 @@ typedef struct * @retval None */ #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ - ((__FLAG__) == RTC_FLAG_TSF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSF)):\ - ((__FLAG__) == RTC_FLAG_TSOVF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSOVF)):\ + ((__FLAG__) == RTC_FLAG_TSF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CTSF)):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF)):\ (0U)) /* Dummy action because is an invalid parameter value */ /** @@ -1437,9 +1436,9 @@ typedef struct */ #define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_SSRUMF)) != 0U) /** - * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @brief Check whether the specified RTC SSRU interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to check. * This parameter can be: * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval The state of __INTERRUPT__ (TRUE or FALSE) @@ -1457,14 +1456,14 @@ typedef struct #define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_SSRUF) == RTC_SR_SSRUF)) /** - * @brief Clear the RTC Wake Up timer's pending flags. + * @brief Clear the RTC SSRU's pending flags. * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC SSRU Flag to clear. * This parameter can be: * @arg @ref RTC_FLAG_SSRUF * @retval None */ -#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CSSRUF)) +#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF)) /** * @} */ @@ -1592,7 +1591,6 @@ void HAL_RTCEx_InternalTamper9EventCallback(RTC_HandleTypeDef *hrtc void HAL_RTCEx_InternalTamper11EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper12EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper13EventCallback(RTC_HandleTypeDef *hrtc); - /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h index bf8ff2b2cb..3447d277b6 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h @@ -92,9 +92,9 @@ typedef struct * @{ */ #if defined(I2C1) -#define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ -#endif /* I2C1 */ -#define SMBUS_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ +#define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 */ +#endif /* I2C1, I2C2 */ +#define SMBUS_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3, I2C4 */ #if defined(SMBUS_TRIG_GRP1) #define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U)) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h index c0dc4c5a62..bfe807ca31 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h @@ -831,14 +831,11 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ -#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ -#define TIM_CLOCKSOURCE_ITR9 TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */ -#define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */ /** * @} */ @@ -1065,8 +1062,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ -#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ -#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ /** @@ -2076,8 +2073,8 @@ mode. ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h index bb36840b37..2a13e15577 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h @@ -411,7 +411,7 @@ typedef struct #define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \ (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5)) -#if defined(TIM3) +#if defined(TIM3) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -475,7 +475,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #endif /* TIM3 */ -#if defined(TIM3) +#if defined(TIM3) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h index 5b79ba051a..256362df27 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h @@ -136,6 +136,9 @@ enum TSC_GROUP4_IDX, TSC_GROUP5_IDX, TSC_GROUP6_IDX, +#if defined(TSC_IOCCR_G7_IO1) + TSC_GROUP7_IDX, +#endif /* TSC_IOCCR_G7_IO1 */ TSC_NB_OF_GROUPS }; @@ -354,6 +357,11 @@ when the selected signal is detected on the SYNC input pin) */ #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) +#if defined(TSC_IOCCR_G7_IO1) +#define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) +#endif /* TSC_IOCCR_G7_IO1 */ + +#define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ @@ -382,6 +390,19 @@ when the selected signal is detected on the SYNC input pin) */ #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ +#if defined(TSC_IOCCR_G7_IO1) + +#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ +#define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ +#define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ +#define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ +#else + +#define TSC_GROUP7_IO1 (uint32_t)(0x00000040UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ +#define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */ +#define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ +#define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ +#endif /* TSC_IOCCR_G7_IO1 */ /** * @} */ @@ -661,7 +682,8 @@ when the selected signal is detected on the SYNC input pin) */ ((__VALUE__) == TSC_PG_PRESC_DIV128)) #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ - ((__CTPL__) > TSC_CTPL_2CYCLES)) || \ + (((__CTPL__) == TSC_CTPL_1CYCLE) || \ + ((__CTPL__) > TSC_CTPL_2CYCLES))) || \ (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ @@ -711,7 +733,11 @@ when the selected signal is detected on the SYNC input pin) */ (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ - (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2)) + (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ + (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ + (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ + (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ + (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4)) /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h index 22e3c41dcf..2768570d6b 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h @@ -66,7 +66,7 @@ typedef struct uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically. This parameter can be a value of @ref UARTEx_Autonomous_Trigger_selection - or @ref LPUARTEx_Autonomous_Trigger_selection.*/ + or @ref UARTEx_Low_Power_Autonomous_Trigger_selection.*/ uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity. This parameter can be a value of @ref UARTEx_Autonomous_Trigger_Polarity */ @@ -197,7 +197,7 @@ typedef struct * @} */ -/** @defgroup LPUARTEx_Autonomous_Trigger_selection LPUARTEx Autonomous trigger selection +/** @defgroup UARTEx_Low_Power_Autonomous_Trigger_selection UARTEx Low Power Autonomous trigger selection * @brief LPUART Autonomous Trigger selection * @{ */ @@ -304,7 +304,7 @@ HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ -#if defined (USART2) +#if defined(USART2) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h index 503a670531..51708c5850 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h @@ -142,7 +142,7 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart_ex.h index 3de2a21421..931a7afcfd 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart_ex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart_ex.h @@ -72,7 +72,7 @@ typedef struct * @{ */ #define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h index 01af3adc42..50878a41dd 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h @@ -705,14 +705,6 @@ typedef struct | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */ #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \ | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */ -#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \ - | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */ -#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \ - | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */ -#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \ - | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */ -#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \ - | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */ #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel @@ -969,18 +961,6 @@ typedef struct #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN13, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN14, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN15, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN16, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN17, converted by group regular only */ #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal @@ -1754,7 +1734,7 @@ typedef struct * On this STM32 series, refer to datasheet parameter "V30" (corresponding * to TS_CAL1). * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage - (see parameter above) is corresponding (unit: mV) + (see parameter above) is corresponding (unit: degree Celsius) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. @@ -1834,7 +1814,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t (void)(Register); /* Retrieve address of register DR */ - return (uint32_t) &(ADCx->DR); + return (uint32_t) & (ADCx->DR); } /** diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h index 7ba4a5f9c8..edb4f86e13 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h @@ -88,6 +88,10 @@ extern "C" { @endcond */ +/** + * @} + */ + /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type * @{ */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h index fec55e8434..2434996143 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h @@ -356,9 +356,9 @@ typedef struct * @{ */ #if defined(I2C1) -#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ -#endif /* I2C1 */ -#define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ +#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 */ +#endif /* I2C1, I2C2 */ +#define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3, I2C4 */ #if defined(I2C_TRIG_GRP1) #define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U)) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h index fbe0291005..61df87976d 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h @@ -1633,6 +1633,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL)); } + /** * @brief Clear the autoreload match flag (ARRMCF) * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h index e0985dafb6..bb1113b020 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h @@ -2538,6 +2538,21 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + /** * @} */ @@ -2674,8 +2689,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetTriggerPolarity(const USART_TypeDef *LPUAR * @arg @ref LL_LPUART_EXTI_LINE6_TRG * @arg @ref LL_LPUART_EXTI_LINE8_TRG * @arg @ref LL_LPUART_LPTIM1_OUT_TRG - * @arg @ref LL_LPUART_COMP1_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) - * @arg @ref LL_LPUART_COMP2_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_LPUART_COMP1_OUT_TRG (not available on all devices) + * @arg @ref LL_LPUART_COMP2_OUT_TRG (not available on all devices) * @arg @ref LL_LPUART_RTC_ALRA_TRG * @arg @ref LL_LPUART_RTC_WUT_TRG * @retval None @@ -2697,8 +2712,8 @@ __STATIC_INLINE void LL_LPUART_SetSelectedTrigger(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_EXTI_LINE6_TRG * @arg @ref LL_LPUART_EXTI_LINE8_TRG * @arg @ref LL_LPUART_LPTIM1_OUT_TRG - * @arg @ref LL_LPUART_COMP1_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) - * @arg @ref LL_LPUART_COMP2_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_LPUART_COMP1_OUT_TRG (not available on all devices) + * @arg @ref LL_LPUART_COMP2_OUT_TRG (not available on all devices) * @arg @ref LL_LPUART_RTC_ALRA_TRG * @arg @ref LL_LPUART_RTC_WUT_TRG */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h index 48fe01b278..8307da7fb2 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h @@ -348,8 +348,8 @@ typedef struct /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE * @{ */ -#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ -#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0U /*!< RTC_ALARM is push-pull output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0U /*!< RTC_ALARM is push-pull output */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ /** * @} */ @@ -1216,7 +1216,6 @@ __STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(const RTC_TypeDef *RTCx) return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BCDU)); } - #ifdef RTC_CR_POL /** * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) @@ -1450,13 +1449,12 @@ __STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(const RTC_TypeDef *RTCx) } #endif /* RTC_CR_TAMPALRM_PU */ - #if defined(RTC_CR_OUT2EN) /** * @brief Enable RTC_OUT2 output * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent) * and COE (@ref LL_RTC_CAL_SetOutputFreq) settings. - * @note RTC_OUT2 is not available ins VBAT mode. + * @note RTC_OUT2 is not available in VBAT mode. * @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2 * @param RTCx RTC Instance * @retval None @@ -1488,7 +1486,6 @@ __STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(const RTC_TypeDef *RTCx) return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U); } #endif /* RTC_CR_OUT2EN */ - /** * @} */ @@ -4322,7 +4319,6 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(const RTC_TypeDef *RTCx) return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U); } - /** * @brief Get internal tamper 5 detection flag. * @rmtoll TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP5 diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h index 033581374d..b54be94dd3 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h @@ -756,6 +756,15 @@ typedef struct */ #endif /* USE_FULL_LL_DRIVER */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 +#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 +/** +@endcond + */ + /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode * @{ */ @@ -771,8 +780,8 @@ typedef struct #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!Purpose

Update History

- +

Main Changes

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

@@ -49,8 +49,88 @@

Official Release
  • HAL/LL Drivers are available for all peripherals:
      -
    • HAL: ADC, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
      • -
    • LL: ADC, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
      • +
    • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
      • +
    • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
      • +
    • +
  • Update HAL/LL drivers to include latest corrections
    • +
+


+

+

HAL Drivers updates

+
    +
  • HAL CORTEX driver +
      +
    • Add functions to configure MPU region without enabling it
      • +
    • +
  • HAL I2C driver +
      +
    • Update HAL_I2C_Slave_Transmit to check if the received NACK is the correct one
      • +
    • Update SMBUS_ITErrorHandler to flash TXDR just in case of error
      • +
    • +
  • HAL RCC driver +
      +
    • Add note for Backup domain access to be enabled for RCC_PERIPHCLK_RADIOST use in HAL_RCCEx_PeriphCLKConfig()
      • +
    • +
  • HAL RTC driver +
      +
    • Update access to the SCR register now done via a one-shot write access
      • +
    • +
  • HAL TIM driver +
      +
    • Remove not supported TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_ITR9 and TIM_CLOCKSOURCE_ITR10 constants
      • +
    • Update HAL_TIM_ConfigOCrefClear() function to check if SMCR.OCCS bit-field is supported by the current instance before updating registers
      • +
    • +
  • HAL TSC driver +
      +
    • Modify assert to track the fordidden prescaler related to DT duration
      • +
    • +
+


+

+

LL Drivers updates

+
    +
  • LL LPUART driver +
      +
    • Add LL LPUART API allowing TX FIFO flush request
      • +
    • +
+


+

+

Supported Devices and boards

+
    +
  • STM32WBA52xx and STM32WBA55xx devices
    • +
  • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
    • +
+

Backward compatibility

+
    +
  • Not applicable
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

+

Contents

+

Official Release of HAL/LL Drivers for STM32WBAxx serie

+
    +
  • HAL/LL Drivers are available for all peripherals: +
      +
    • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
      • +
    • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
  • Update SysTick clock source management to handle HCLK, HCLK/8, LSI and LSE sources
      @@ -61,7 +141,7 @@

      Official Release


    -

    HAL Drivers updates

    +

    HAL Drivers updates

    • HAL CORTEX driver
        @@ -148,7 +228,7 @@

        HAL Drivers updates


      -

      LL Drivers updates

      +

      LL Drivers updates

      • LL GPIO driver
          @@ -173,24 +253,24 @@

          LL Drivers updates


        -

        Supported Devices and boards

        +

        Supported Devices and boards

        • STM32WBA52xx and STM32WBA55xx devices
        • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
        -

        Backward compatibility

        +

        Backward compatibility

        • Not applicable
        -

        Known Limitations

        +

        Known Limitations

        • None
        -

        Dependencies

        +

        Dependencies

        • None
        -

        Notes

        +

        Notes

        • None
        @@ -199,10 +279,10 @@

        Notes

        -

        Main Changes

        +

        Main Changes

        Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

        -

        Contents

        -

        Official Release of HAL/LL Drivers for STM32WBAxx serie

        +

        Contents

        +

        Official Release of HAL/LL Drivers for STM32WBAxx serie

        • HAL/LL Drivers are available for all peripherals:
            @@ -212,7 +292,7 @@

            Official Relea


          -

          HAL Drivers updates

          +

          HAL Drivers updates

          • HAL CORTEX driver
              @@ -273,7 +353,7 @@

              HAL Drivers updates


            -

            LL Drivers updates

            +

            LL Drivers updates

            • LL DMA driver
                @@ -295,24 +375,24 @@

                LL Drivers updates


              -

              Supported Devices and boards

              +

              Supported Devices and boards

              • STM32WBA52xx devices
              • NUCLEO-WBA52CG board
              -

              Backward compatibility

              +

              Backward compatibility

              • Not applicable
              -

              Known Limitations

              +

              Known Limitations

              • None
              -

              Dependencies

              +

              Dependencies

              • None
              -

              Notes

              +

              Notes

              • None
              @@ -321,9 +401,9 @@

              Notes

              -

              Main Changes

              +

              Main Changes

              First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

              -

              Contents

              +

              Contents

              First Official Release of HAL/LL Drivers for STM32WBAxx serie

              • HAL/LL Drivers are available for all peripherals: @@ -334,24 +414,24 @@

                First Offi


              -

              Supported Devices and boards

              +

              Supported Devices and boards

              • STM32WBA52xx devices
              • NUCLEO-WBA52CG board
              -

              Backward compatibility

              +

              Backward compatibility

              • Not applicable
              -

              Known Limitations

              +

              Known Limitations

              • None
              -

              Dependencies

              +

              Dependencies

              • None
              -

              Notes

              +

              Notes

              • None
              diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c index 7f4fb9582c..1d5b8c19c7 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c @@ -25,8 +25,8 @@ used by the PPP peripheral drivers and the user to start using the HAL. [..] The HAL contains two APIs' categories: - (+) Common HAL APIs - (+) Services HAL APIs + (+) Common HAL APIs (Version, Init, Tick) + (+) Services HAL APIs (DBGMCU, SYSCFG) @endverbatim ****************************************************************************** @@ -50,19 +50,20 @@ /* Private define ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + /* Exported variables --------------------------------------------------------*/ /** @defgroup HAL_Exported_Variables HAL Exported Variables * @{ */ __IO uint32_t uwTick; -uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ -/* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup HAL_Exported_Functions HAL Exported Functions @@ -77,11 +78,10 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initializes the Flash interface the NVIC allocation and initial clock - configuration. It initializes the systick also when timeout is needed - and the backup domain when enabled. - (+) De-Initializes common part of the HAL. - (+) Configure The time base source to have 1ms time base with a dedicated + (+) Initialize the Flash interface the NVIC allocation and initial time base + clock configuration. + (+) De-initialize common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated Tick interrupt priority. (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose @@ -148,8 +148,8 @@ HAL_StatusTypeDef HAL_Init(void) } /** - * @brief This function de-Initializes common part of the HAL and stops the systick. - * This function is optional. + * @brief De-initialize common part of the HAL and stop the source of time base. + * @note This function is optional. * @retval HAL status */ HAL_StatusTypeDef HAL_DeInit(void) @@ -184,29 +184,29 @@ HAL_StatusTypeDef HAL_DeInit(void) } /** - * @brief Initializes the MSP. + * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } /** - * @brief DeInitializes the MSP. + * @brief DeInitialize the MSP. * @retval None */ __weak void HAL_MspDeInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } /** - * @brief This function configures the source of the time base. + * @brief This function configures the source of the time base: * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after @@ -218,7 +218,7 @@ __weak void HAL_MspDeInit(void) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) @@ -285,7 +285,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @} */ -/** @defgroup HAL_Group2 HAL Control functions +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim @@ -300,9 +300,6 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) (+) Get the HAL API driver version (+) Get the device identifier (+) Get the device revision identifier - (+) Enable/Disable Debug module during SLEEP mode - (+) Enable/Disable Debug module during STOP mode - (+) Enable/Disable Debug module during STANDBY mode @endverbatim * @{ @@ -323,7 +320,7 @@ __weak void HAL_IncTick(void) } /** - * @brief Provides a tick value in millisecond. + * @brief Provide a tick value in millisecond. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value @@ -343,22 +340,29 @@ uint32_t HAL_GetTickPrio(void) } /** - * @brief Set new tick Freq. - * @retval Status + * @brief Set new tick frequency. + * @param Freq tick frequency + * @retval HAL status */ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; - assert_param(IS_TICKFREQ(Freq)); + HAL_TickFreqTypeDef prevTickFreq; if (uwTickFreq != Freq) { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); - - if (status == HAL_OK) + if (status != HAL_OK) { - uwTickFreq = Freq; + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; } } @@ -435,7 +439,7 @@ __weak void HAL_ResumeTick(void) } /** - * @brief Returns the HAL revision + * @brief Return the HAL revision. * @retval version : 0xXYZR (8bits for each decimal, R for RC) */ uint32_t HAL_GetHalVersion(void) @@ -444,16 +448,16 @@ uint32_t HAL_GetHalVersion(void) } /** - * @brief Returns the device revision identifier. + * @brief Return the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { - return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); + return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); } /** - * @brief Returns the device identifier. + * @brief Return the device identifier. * @retval Device identifier */ uint32_t HAL_GetDEVID(void) @@ -491,7 +495,6 @@ uint32_t HAL_GetUIDw2(void) * @} */ - /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions * @brief HAL Debug functions * @@ -747,6 +750,7 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri */ #endif /* HAL_MODULE_ENABLED */ + /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc.c index 233cc3ffc7..efe59189a7 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc.c @@ -825,17 +825,17 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Reset register SMPR */ hadc->Instance->SMPR &= ~ADC_SMPR_SMP1; - /* Reset registers AWDxTR */ - hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1); - hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2); - hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3); - /* Reset register CHSELR */ hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL); /* Reset register DR */ /* bits in access mode read only, no direct reset applicable */ + /* Reset registers AWDxTR */ + hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1); + hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2); + hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3); + /* Reset register PWRR */ /* Note: Bit of deep power down mode already updated previously */ hadc->Instance->PWRR &= ~(ADC_PWRR_AUTOFF); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c index d0b3a681e4..cfad3c53ee 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c @@ -505,6 +505,22 @@ void HAL_MPU_Enable(uint32_t MPU_Control) __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Enable the non-secure MPU. @@ -532,6 +548,21 @@ void HAL_MPU_Enable_NS(uint32_t MPU_Control) __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } + +/** + * @brief Enable the non-secure MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber) +{ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} #endif /* __ARM_FEATURE_CMSE */ /** @@ -554,6 +585,22 @@ void HAL_MPU_Disable(void) __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) void HAL_MPU_Disable_NS(void) { @@ -570,7 +617,24 @@ void HAL_MPU_Disable_NS(void) __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ } + +/** + * @brief Disable the non-secure MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} #endif /* __ARM_FEATURE_CMSE */ + /** * @brief Initialize and configure the Region and the memory to be protected. * @param MPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains @@ -600,6 +664,10 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, MPU_Region_InitTypeDef *MPU_RegionI /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_RegionInit->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_RegionInit->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_RegionInit->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_RegionInit->IsShareable)); + assert_param(IS_MPU_ATTRIBUTES_NUMBER(MPU_RegionInit->AttributesIndex)); /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ __DMB(); @@ -607,27 +675,17 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, MPU_Region_InitTypeDef *MPU_RegionI /* Set the Region number */ MPUx->RNR = MPU_RegionInit->Number; - if (MPU_RegionInit->Enable != MPU_REGION_DISABLE) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_RegionInit->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_RegionInit->AccessPermission)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_RegionInit->IsShareable)); - - MPUx->RBAR = (((uint32_t)MPU_RegionInit->BaseAddress & 0xFFFFFFE0U) | - ((uint32_t)MPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | - ((uint32_t)MPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | - ((uint32_t)MPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); - - MPUx->RLAR = (((uint32_t)MPU_RegionInit->LimitAddress & 0xFFFFFFE0U) | - ((uint32_t)MPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | - ((uint32_t)MPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); - } - else - { - MPUx->RBAR = 0U; - MPUx->RLAR = 0U; - } + /* Disable the Region */ + CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk); + + MPUx->RBAR = (((uint32_t)MPU_RegionInit->BaseAddress & 0xFFFFFFE0U) | + ((uint32_t)MPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | + ((uint32_t)MPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | + ((uint32_t)MPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); + + MPUx->RLAR = (((uint32_t)MPU_RegionInit->LimitAddress & 0xFFFFFFE0U) | + ((uint32_t)MPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | + ((uint32_t)MPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); } /** * @brief Initialize and configure the memory attributes. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c index b08994a33c..9f95483992 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c @@ -1336,7 +1336,7 @@ static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, /* Check the parameters */ assert_param(IS_OB_WMSEC_CONFIG(WMSecConfig)); - assert_param(IS_OB_WMSEC_AREA_EXCLUSIVE(WMSecConfig & 0x3U)); + assert_param(IS_OB_WMSEC_AREA_EXCLUSIVE(WMSecConfig & FLASH_BANK_1)); assert_param(IS_FLASH_PAGE(WMSecStartPage)); assert_param(IS_FLASH_PAGE(WMSecEndPage)); assert_param(IS_FLASH_PAGE(WMHDPEndPage)); @@ -1558,7 +1558,7 @@ static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, u /* Check the parameters */ assert_param(IS_OB_WMSEC_CONFIG(*WMSecConfig)); - assert_param(IS_FLASH_BANK_EXCLUSIVE((*WMSecConfig) & 0x3U)); + assert_param(IS_FLASH_BANK_EXCLUSIVE((*WMSecConfig) & FLASH_BANK_1)); /* Read SECWM registers */ if (((*WMSecConfig) & OB_WMSEC_AREA1) != 0U) diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c index 0befd7d3cb..1f67b9d949 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c @@ -90,7 +90,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -156,7 +156,7 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -214,7 +214,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -1363,6 +1363,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1389,14 +1391,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - /* Preload TX data if no stretch enable */ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { @@ -1410,6 +1404,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1421,6 +1427,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1433,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1456,31 +1470,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until AF flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } - return HAL_ERROR; + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { @@ -4819,7 +4850,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4828,7 +4859,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { /* Process Locked */ __HAL_LOCK(hi2c); diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c index d06b427902..53076faf4b 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c @@ -43,11 +43,11 @@ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions +/** @addtogroup RCCEx_Exported_Functions * @{ */ -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions +/** @addtogroup RCCEx_Exported_Functions_Group1 * @brief Extended Peripheral Control functions * @verbatim @@ -88,7 +88,9 @@ * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC ADC4 peripheral clock * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_RADIOST RADIO sleep timer clock (**) * @note (*) Peripherals are not available on all devices + * @note (**) This requires the Backup domain access to be enabled * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source: in this case the access to Backup domain is enabled. * @retval HAL status @@ -391,6 +393,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *Peri /* Configure the RADIO Sleep Timer clock source */ __HAL_RCC_RADIOSLPTIM_CONFIG(PeriphClkInit->RadioSlpTimClockSelection); + + /* Check configuration validity as under Backup domain access control */ + if (__HAL_RCC_GET_RADIOSLPTIM_SOURCE() != PeriphClkInit->RadioSlpTimClockSelection) + { + return HAL_ERROR; + } } return HAL_OK; @@ -517,6 +525,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC ADC4 peripheral clock * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_RADIOST RADIO sleep timer clock * @note (*) Peripherals are not available on all devices * @retval Frequency in Hz */ @@ -1124,7 +1133,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) * @} */ -/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions +/** @addtogroup RCCEx_Exported_Functions_Group2 * @brief Extended Clock management functions * @verbatim @@ -1190,7 +1199,7 @@ void HAL_RCCEx_DisableLSCO(void) /** * @brief Set HSE trimming value - * @param Trimming specifies the HSE trimmign value. + * @param Trimming specifies the HSE trimming value. * This parameter should be below 0x3F. * @retval None */ @@ -1204,7 +1213,7 @@ void HAL_RCCEx_HSESetTrimming(uint32_t Trimming) /** * @brief Get HSE trimming value - * @retval The programmed HSE trimmign value + * @retval The programmed HSE trimming value */ uint32_t HAL_RCCEx_HSEGetTrimming(void) { @@ -1231,7 +1240,7 @@ void HAL_RCCEx_LSESetTrimming(uint32_t Trimming) /** * @brief Get LSE trimming value - * @retval The programmed LSE trimmign value + * @retval The programmed LSE trimming value */ uint32_t HAL_RCCEx_LSEGetTrimming(void) { @@ -1281,7 +1290,7 @@ void HAL_RCCEx_LSI2GetConfig(RCC_LSIConfigTypeDef *pConfig) * @} */ -/** @defgroup RCCEx_Exported_Functions_Group3 Radio clock management functions +/** @addtogroup RCCEx_Exported_Functions_Group3 * @brief Radio clock management functions * @verbatim @@ -1347,6 +1356,120 @@ uint32_t HAL_RCCEx_GetRadioBusClockReadiness(void) * @} */ +#if defined(RCC_CCIPR2_ASSEL) +/** @addtogroup RCCEx_Exported_Functions_Group4 + * @brief Radio clock management functions + * +@verbatim + =============================================================================== + ##### Extended radio clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + audio-synchronization-related parameters. +@endverbatim + * @{ + */ + +/** + * @brief Enable the Audio Synchronization counter and kernel clock + * @retval None + */ +void HAL_RCCEx_EnableAudioSyncClock(void) +{ + SET_BIT(RCC->ASCR, RCC_ASCR_CEN); +} + +/** + * @brief Disable the Audio Synchronization counter and kernel clock + * @retval None + */ +void HAL_RCCEx_DisableAudioSyncClock(void) +{ + CLEAR_BIT(RCC->ASCR, RCC_ASCR_CEN); +} + +/** + * @brief Set Audio Synchronization Configuration + * @param pConf pointer to an RCC_AudioSyncConfigTypeDef structure that + * contains the configuration information for the Audio Synchronization + * @retval None + */ +HAL_StatusTypeDef HAL_RCCEx_SetConfigAudioSync(const RCC_AudioSyncConfigTypeDef *pConf) +{ + /* Check the parameters */ + assert_param(pConf != (void *)NULL); + assert_param(IS_RCC_AUDIOSYNC_CAPTUREPRESCALER(pConf->CapturePrescaler)); + assert_param(IS_RCC_AUDIOSYNC_CLOCKPRESCALER(pConf->ClockPrescaler)); + assert_param(IS_RCC_AUDIOSYNC_AUTORELOAD(pConf->AutoReloadValue)); + assert_param(IS_RCC_AUDIOSYNC_COMPARE(pConf->CompareValue)); + + /* Set ASCR register value */ + RCC->ASCR = (((pConf->CapturePrescaler) << RCC_ASCR_CPS_Pos) & \ + ((pConf->ClockPrescaler) << RCC_ASCR_PSC_Pos)); + + /* Set Auto Reload value */ + RCC->ASARR = ((pConf->AutoReloadValue) << RCC_ASARR_AR_Pos); + + /* Set Compare value */ + RCC->ASCOR = ((pConf->CompareValue) << RCC_ASCOR_CO_Pos); + + return HAL_OK; +} + +/** + * @brief Configure the pConf according to the internal + * RCC configuration registers. + * @param pConf pointer to an RCC_AudioSyncConfigTypeDef + * structure that will be configured. + * @retval None + */ +void HAL_RCCEx_GetConfigAudioSync(RCC_AudioSyncConfigTypeDef *pConf) +{ + uint32_t regvalue; + + /* Check the parameters */ + assert_param(pConf != (void *)NULL); + + /* Get Audio ASCR register */ + regvalue = RCC->ASCR; + + /* Get Capture prescaler value */ + pConf->CapturePrescaler = ((regvalue & RCC_ASCR_CPS) >> RCC_ASCR_CPS_Pos); + + /* Get Clock prescaler value */ + pConf->ClockPrescaler = ((regvalue & RCC_ASCR_PSC) >> RCC_ASCR_PSC_Pos); + + /* Get Auto Reload value */ + pConf->AutoReloadValue = ((RCC->ASARR & RCC_ASCAR_CA) >> RCC_ASCAR_CA_Pos); + + /* Get Compare value */ + pConf->CompareValue = ((RCC->ASCOR & RCC_ASCOR_CO) >> RCC_ASCOR_CO_Pos); +} + +/** + * @brief Get AudioSync Counter value + * @retval The Counter value + */ +uint32_t HAL_RCCEx_GetAudioSyncCounterValue(void) +{ + return ((RCC->ASCNTR & RCC_ASCNTR_CNT) >> RCC_ASCNTR_CNT_Pos); +} + +/** + * @brief Get AudioSync Capture value + * @retval The programmed Capture value + */ +uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void) +{ + return ((RCC->ASCAR & RCC_ASCAR_CA) >> RCC_ASCAR_CA_Pos); +} + +/** + * @} + */ +#endif /* RCC_CCIPR2_ASSEL */ + /** * @} */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng_ex.c index 3de5f9f590..0e66adbb0b 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -41,7 +41,7 @@ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -53,11 +53,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -269,7 +269,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc.c index b288722a44..ed2910d585 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc.c @@ -518,6 +518,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_SSRU_EVENT_CB_ID SSRU Event Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus.c index ccda2e6bfb..850034618e 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus.c @@ -2625,8 +2625,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); + if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) + { + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + } /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus_ex.c index 2e6a216014..23d81ea1c6 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus_ex.c @@ -6,6 +6,9 @@ * This file provides firmware functions to manage the following * functionalities of SMBUS Extended peripheral: * + Extended features functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + Autonomous Mode Functions * ****************************************************************************** * @attention diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim.c index de7fb7c7e7..0eda68d0e0 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim.c @@ -4630,7 +4630,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFERS. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ @@ -4776,7 +4776,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFERS. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status @@ -5086,7 +5086,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFERS. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ @@ -5231,7 +5231,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFERS. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status @@ -5578,15 +5578,28 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, case TIM_CLEARINPUTSOURCE_NONE: { /* Clear the OCREF clear selection bit and the the ETR Bits */ - CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + if (IS_TIM_OCCS_INSTANCE(htim->Instance)) + { + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + + /* Clear TIMx_AF2_OCRSEL (reset value) */ + CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL); + } + else + { + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + } break; } case TIM_CLEARINPUTSOURCE_COMP1: case TIM_CLEARINPUTSOURCE_COMP2: { - /* Clear the OCREF clear selection bit */ - CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + if (IS_TIM_OCCS_INSTANCE(htim->Instance)) + { + /* Clear the OCREF clear selection bit */ + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + } /* Set the clear input source */ MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); @@ -5613,8 +5626,14 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); - /* Set the OCREF clear selection bit */ - SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + if (IS_TIM_OCCS_INSTANCE(htim->Instance)) + { + /* Set the OCREF clear selection bit */ + SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + + /* Clear TIMx_AF2_OCRSEL (reset value) */ + CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL); + } break; } diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim_ex.c index 7145249607..8c67bc2199 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim_ex.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim_ex.c @@ -1902,7 +1902,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR7: Internal trigger 7 selected + * @arg TIM_TS_ITR8: Internal trigger 8 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: @@ -1919,6 +1920,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t __HAL_LOCK(htim); + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7) || + (InputTrigger == TIM_TS_ITR8)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; @@ -1956,7 +1960,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR7: Internal trigger 7 selected + * @arg TIM_TS_ITR8: Internal trigger 8 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: @@ -1973,6 +1978,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 __HAL_LOCK(htim); + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7) || + (InputTrigger == TIM_TS_ITR8)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; @@ -2011,7 +2019,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR7: Internal trigger 7 selected + * @arg TIM_TS_ITR8: Internal trigger 8 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: @@ -2028,6 +2037,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 __HAL_LOCK(htim); + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7) || + (InputTrigger == TIM_TS_ITR8)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tsc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tsc.c index d484dc17e7..f70c1ae4a7 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tsc.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tsc.c @@ -176,9 +176,16 @@ | PB14 (AF9) | TSC_G6_IO1 | | PB13 (AF9) | TSC_G6_IO2 | |--------------|-----------------| + |(*) PE3 (AF9) | TSC_G7_IO1 | + |(*) PE2 (AF9) | TSC_G7_IO2 | + |(*) PE1 (AF9) | TSC_G7_IO3 | + |(*) PE0 (AF9) | TSC_G7_IO4 | + |--------------|-----------------| | PB12 (AF9) | TSC_SYNC | +--------------------------------+ + (*) not usable for all devices. + */ /* Includes ------------------------------------------------------------------*/ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_adc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_adc.c index 3ae9761b20..28674a794c 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_adc.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_adc.c @@ -389,6 +389,14 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset register SMPR */ CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL); + /* Reset register CHSELR */ + CLEAR_BIT(ADCx->CHSELR, + (ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 + | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 + | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 + | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0) + ); + /* Reset register AWD1TR */ MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_LT1 | ADC_AWD1TR_HT1, ADC_AWD1TR_HT1); @@ -398,14 +406,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset register AWD3TR */ MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_LT3 | ADC_AWD3TR_HT3, ADC_AWD3TR_HT3); - /* Reset register CHSELR */ - CLEAR_BIT(ADCx->CHSELR, - (ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 - | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 - | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 - | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0) - ); - /* Reset register DR */ /* bits in access mode read only, no direct reset applicable */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rtc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rtc.c index 186bb215c9..ee73d0e847 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rtc.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rtc.c @@ -161,9 +161,9 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) #if defined (RTC_PRIVCFGR_PRIV) WRITE_REG(RTCx->PRIVCFGR, 0U); #endif /* RTC_PRIVCFGR_PRIV */ -#if defined (RTC_SECCFGR_SEC) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) WRITE_REG(RTCx->SECCFGR, 0U); -#endif /* RTC_SECCFGR_SEC */ +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Clear some bits of RTC_ICSR and exit Initialization mode */ CLEAR_BIT(RTCx->ICSR, RTC_ICSR_BCDU_Msk | RTC_ICSR_BIN_Msk | RTC_ICSR_INIT); @@ -179,9 +179,9 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) WRITE_REG(TAMP->CR1, 0U); WRITE_REG(TAMP->CR2, 0U); WRITE_REG(TAMP->CR3, 0U); -#if defined (TAMP_SECCFGR_TAMPSEC) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) WRITE_REG(TAMP->SECCFGR, 0U); -#endif /* TAMP_SECCFGR_TAMPSEC */ +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #if defined (TAMP_PRIVCFGR_TAMPPRIV) WRITE_REG(TAMP->PRIVCFGR, 0U); #endif /* TAMP_PRIVCFGR_TAMPPRIV */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c index c347ac2c95..801e1740ba 100644 --- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c @@ -66,8 +66,8 @@ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \ || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \ || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT)) diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index acc06cd3e9..83d50c2d5d 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -18,7 +18,7 @@ * STM32MP1: 1.6.0 * STM32U5: 1.5.0 * STM32WB: 1.14.2 - * STM32WBA: 1.2.0 + * STM32WBA: 1.3.0 * STM32WL: 1.3.0 Release notes of each STM32YYxx HAL Drivers available here: From db64f99c698c3c5ce1138ec70d33369c1819883c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 29 Apr 2024 17:07:46 +0200 Subject: [PATCH 2/3] system(WBA): update STM32WBAxx CMSIS Drivers to v1.3.0 Included in STM32CubeWBA FW v1.3.1 Signed-off-by: Frederic Pillon --- .../ST/STM32WBAxx/Include/stm32wba50xx.h | 4 ++ .../ST/STM32WBAxx/Include/stm32wba52xx.h | 36 +++++++----- .../ST/STM32WBAxx/Include/stm32wba54xx.h | 36 +++++++----- .../ST/STM32WBAxx/Include/stm32wba55xx.h | 36 +++++++----- .../Device/ST/STM32WBAxx/Include/stm32wbaxx.h | 4 +- .../Device/ST/STM32WBAxx/Release_Notes.html | 55 +++++++++++++++---- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 7 files changed, 119 insertions(+), 54 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h index eae81c6a0d..a7e35f80db 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h @@ -10295,6 +10295,10 @@ typedef struct #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ ((INSTANCE) == TIM2_NS)) +/********* TIM Instances : supporting bitfield OCCS in SMCR register **********/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ ((INSTANCE) == TIM2_NS)) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h index fb49c5ea64..b95d9163e3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h @@ -14343,8 +14343,7 @@ typedef struct ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) /****************** TIM Instances : supporting 32 bits counter ****************/ -#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ @@ -14530,6 +14529,11 @@ typedef struct ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ @@ -14563,9 +14567,9 @@ typedef struct #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ - ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ - ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) @@ -14791,8 +14795,7 @@ typedef struct ((INSTANCE) == TIM17_NS)) /****************** TIM Instances : supporting 32 bits counter ****************/ -#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \ - ((INSTANCE) == TIM3_NS)) +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ @@ -14974,9 +14977,16 @@ typedef struct ((INSTANCE) == TIM3_NS)) /****************** TIM Instances : supporting OCxREF clear *******************/ -#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ - ((INSTANCE) == TIM2_NS) || \ - ((INSTANCE) == TIM3_NS)) +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ @@ -15010,9 +15020,9 @@ typedef struct #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || \ - ((__INSTANCE__) == TIM2_NS) || \ - ((__INSTANCE__) == TIM3_NS)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h index 3ff8f14394..b286ceb489 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h @@ -15051,8 +15051,7 @@ typedef struct ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) /****************** TIM Instances : supporting 32 bits counter ****************/ -#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ @@ -15238,6 +15237,11 @@ typedef struct ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ @@ -15271,9 +15275,9 @@ typedef struct #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ - ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ - ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) @@ -15499,8 +15503,7 @@ typedef struct ((INSTANCE) == TIM17_NS)) /****************** TIM Instances : supporting 32 bits counter ****************/ -#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \ - ((INSTANCE) == TIM3_NS)) +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ @@ -15682,9 +15685,16 @@ typedef struct ((INSTANCE) == TIM3_NS)) /****************** TIM Instances : supporting OCxREF clear *******************/ -#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ - ((INSTANCE) == TIM2_NS) || \ - ((INSTANCE) == TIM3_NS)) +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ @@ -15718,9 +15728,9 @@ typedef struct #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || \ - ((__INSTANCE__) == TIM2_NS) || \ - ((__INSTANCE__) == TIM3_NS)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h index 680b40a9ff..6f9850c513 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h @@ -15069,8 +15069,7 @@ typedef struct ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) /****************** TIM Instances : supporting 32 bits counter ****************/ -#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ @@ -15256,6 +15255,11 @@ typedef struct ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ @@ -15289,9 +15293,9 @@ typedef struct #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ - ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ - ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) @@ -15517,8 +15521,7 @@ typedef struct ((INSTANCE) == TIM17_NS)) /****************** TIM Instances : supporting 32 bits counter ****************/ -#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \ - ((INSTANCE) == TIM3_NS)) +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ @@ -15700,9 +15703,16 @@ typedef struct ((INSTANCE) == TIM3_NS)) /****************** TIM Instances : supporting OCxREF clear *******************/ -#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ - ((INSTANCE) == TIM2_NS) || \ - ((INSTANCE) == TIM3_NS)) +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ @@ -15736,9 +15746,9 @@ typedef struct #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || \ - ((__INSTANCE__) == TIM2_NS) || \ - ((__INSTANCE__) == TIM3_NS)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) /****************************** TSC Instances *********************************/ #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h index c1fdad82ac..975b686f75 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h @@ -61,7 +61,7 @@ /* #define STM32WBA52xx */ /*!< STM32WBA52xx Devices */ /* #define STM32WBA54xx */ /*!< STM32WBA54xx Devices */ /* #define STM32WBA55xx */ /*!< STM32WBA55xx Devices */ -#endif /* !STM32WBA55xx && !STM32WBA52xx ...*/ +#endif /* !STM32WBA50xx && !STM32WBA52xx ...*/ /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. @@ -79,7 +79,7 @@ * @brief CMSIS Device version number */ #define __STM32WBA_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBA_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32WBA_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32WBA_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBA_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBA_CMSIS_VERSION ((__STM32WBA_CMSIS_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html index 572d83e938..461f337e15 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html @@ -44,7 +44,7 @@

              Purpose

              Update History

              - +

              Main Changes

              Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

              @@ -53,9 +53,9 @@

              Notes

              - +

              Main Changes

              -

              Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

              +

              Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

              Contents

              -

              Official Release of CMSIS devices drivers supporting STM32WBA52xx devices

              +

              Official Release of CMSIS devices drivers supporting STM32WBA52xx and STM32WBA55xx devices

              • Update CMSIS devices to include latest corrections
                  -
                • Align SAU region end address on Flash end address
                  • +
                • Add support of WKUP_S_IRQn and RCC_AUDIOSYNC_IRQn interrupts in CMSIS devices, startup_stm32wba5xxx.s and partition_stmwba5xxx.h files
                  • +
                • Update Licensing header in partition_stm325xxx.h files based on partition_ARMCM33.h
                  • +
                • Update declaration of g_pfnVectors size in gcc/startup_stm32wba5xxx.s files


              @@ -104,17 +106,20 @@

              Notes

              - +

              Main Changes

              -

              First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

              +

              Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

              Contents

              +

              Official Release of CMSIS devices drivers supporting STM32WBA52xx devices

                -
              • First official release of CMSIS devices drivers +
              • Update CMSIS devices to include latest corrections
                  -
                • Support of STM32WBA52xx devices
                  • +
                • Align SAU region end address on Flash end address
              +


              +

              Known Limitations

              • None
                • @@ -129,6 +134,32 @@

                Notes

              +
              + +
              +

              Main Changes

              +

              First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

              +

              Contents

              +
                +
              • First official release of CMSIS devices drivers +
                  +
                • Support of STM32WBA52xx devices
                  • +
                • +
              +

              Known Limitations

              +
                +
              • None
                • +
              +

              Dependencies

              +
                +
              • None
                • +
              +

              Notes

              +
                +
              • None
                • +
              +
              +