From 8d6acd40ea0ec7f07b9382c4d7160588d8020d88 Mon Sep 17 00:00:00 2001 From: Brandon Diaz Date: Wed, 26 Apr 2023 00:40:34 -0400 Subject: [PATCH 1/2] variant(F4): add generic STM32F412Zx support Signed-off-by: Brandon Diaz --- README.md | 1 + boards.txt | 32 +++ .../STM32F4xx/F412Z(E-G)(J-T)/generic_clock.c | 49 ++++- .../STM32F4xx/F412Z(E-G)(J-T)/ldscript.ld | 185 ++++++++++++++++++ 4 files changed, 265 insertions(+), 2 deletions(-) create mode 100644 variants/STM32F4xx/F412Z(E-G)(J-T)/ldscript.ld diff --git a/README.md b/README.md index d6fee8a9eb..0b8908117a 100644 --- a/README.md +++ b/README.md @@ -344,6 +344,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F411RC
STM32F411RE | Generic Board | *1.9.0* | | | :green_heart: | STM32F412CE
STM32F412CG | Generic Board | *1.9.0* | | | :green_heart: | STM32F412RE
STM32F412RG | Generic Board | *1.9.0* | | +| :yellow_heart: | STM32F412ZE
STM32F412ZG | Generic Board | **2.6.0** | | | :green_heart: | STM32F413CG
STM32F413CH | Generic Board | *1.9.0* | | | :green_heart: | STM32F413RG
STM32F413RH | Generic Board | *1.9.0* | | | :green_heart: | STM32F413ZG
STM32F413ZH | Generic Board | *2.0.0* | | diff --git a/boards.txt b/boards.txt index 38721006e0..da41e14081 100644 --- a/boards.txt +++ b/boards.txt @@ -4113,6 +4113,38 @@ GenF4.menu.pnum.GENERIC_F412RGYXP.build.board=GENERIC_F412RGYXP GenF4.menu.pnum.GENERIC_F412RGYXP.build.product_line=STM32F412Rx GenF4.menu.pnum.GENERIC_F412RGYXP.build.variant=STM32F4xx/F412R(E-G)(T-Y)x(P) +# Generic F412ZEJx +GenF4.menu.pnum.GENERIC_F412ZEJX=Generic F412ZEJx +GenF4.menu.pnum.GENERIC_F412ZEJX.upload.maximum_size=524288 +GenF4.menu.pnum.GENERIC_F412ZEJX.upload.maximum_data_size=262144 +GenF4.menu.pnum.GENERIC_F412ZEJX.build.board=GENERIC_F412ZEJX +GenF4.menu.pnum.GENERIC_F412ZEJX.build.product_line=STM32F412Zx +GenF4.menu.pnum.GENERIC_F412ZEJX.build.variant=STM32F4xx/F412Z(E-G)(J-T) + +# Generic F412ZGJx +GenF4.menu.pnum.GENERIC_F412ZGJX=Generic F412ZGJx +GenF4.menu.pnum.GENERIC_F412ZGJX.upload.maximum_size=1048576 +GenF4.menu.pnum.GENERIC_F412ZGJX.upload.maximum_data_size=262144 +GenF4.menu.pnum.GENERIC_F412ZGJX.build.board=GENERIC_F412ZGJX +GenF4.menu.pnum.GENERIC_F412ZGJX.build.product_line=STM32F412Zx +GenF4.menu.pnum.GENERIC_F412ZGJX.build.variant=STM32F4xx/F412Z(E-G)(J-T) + +# Generic F412ZETx +GenF4.menu.pnum.GENERIC_F412ZETX=Generic F412ZETx +GenF4.menu.pnum.GENERIC_F412ZETX.upload.maximum_size=524288 +GenF4.menu.pnum.GENERIC_F412ZETX.upload.maximum_data_size=262144 +GenF4.menu.pnum.GENERIC_F412ZETX.build.board=GENERIC_F412ZETX +GenF4.menu.pnum.GENERIC_F412ZETX.build.product_line=STM32F412Zx +GenF4.menu.pnum.GENERIC_F412ZETX.build.variant=STM32F4xx/F412Z(E-G)(J-T) + +# Generic F412ZGTx +GenF4.menu.pnum.GENERIC_F412ZGTX=Generic F412ZGTx +GenF4.menu.pnum.GENERIC_F412ZGTX.upload.maximum_size=1048576 +GenF4.menu.pnum.GENERIC_F412ZGTX.upload.maximum_data_size=262144 +GenF4.menu.pnum.GENERIC_F412ZGTX.build.board=GENERIC_F412ZGTX +GenF4.menu.pnum.GENERIC_F412ZGTX.build.product_line=STM32F412Zx +GenF4.menu.pnum.GENERIC_F412ZGTX.build.variant=STM32F4xx/F412Z(E-G)(J-T) + # Generic F413CGUx GenF4.menu.pnum.GENERIC_F413CGUX=Generic F413CGUx GenF4.menu.pnum.GENERIC_F413CGUX.upload.maximum_size=1048576 diff --git a/variants/STM32F4xx/F412Z(E-G)(J-T)/generic_clock.c b/variants/STM32F4xx/F412Z(E-G)(J-T)/generic_clock.c index 2180fca490..fc21569d7a 100644 --- a/variants/STM32F4xx/F412Z(E-G)(J-T)/generic_clock.c +++ b/variants/STM32F4xx/F412Z(E-G)(J-T)/generic_clock.c @@ -21,8 +21,53 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 96; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; + PeriphClkInitStruct.SdioClockSelection = RCC_SDIOCLKSOURCE_CLK48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32F4xx/F412Z(E-G)(J-T)/ldscript.ld b/variants/STM32F4xx/F412Z(E-G)(J-T)/ldscript.ld new file mode 100644 index 0000000000..545b6e13c4 --- /dev/null +++ b/variants/STM32F4xx/F412Z(E-G)(J-T)/ldscript.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32F412ZGTx Device from STM32F4 series +** 1024Kbytes FLASH +** 256Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} From 3f251f2dde841293978025f4787c2111cc67f6a6 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 15 May 2023 14:45:53 +0200 Subject: [PATCH 2/2] variant(F4): add Nucleo F412ZG support Signed-off-by: Frederic Pillon --- README.md | 1 + boards.txt | 14 + .../F412Z(E-G)(J-T)/variant_NUCLEO_F412ZG.cpp | 222 +++++++++++++++ .../F412Z(E-G)(J-T)/variant_NUCLEO_F412ZG.h | 257 ++++++++++++++++++ 4 files changed, 494 insertions(+) create mode 100644 variants/STM32F4xx/F412Z(E-G)(J-T)/variant_NUCLEO_F412ZG.cpp create mode 100644 variants/STM32F4xx/F412Z(E-G)(J-T)/variant_NUCLEO_F412ZG.h diff --git a/README.md b/README.md index 0b8908117a..052e8e8ff7 100644 --- a/README.md +++ b/README.md @@ -87,6 +87,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | | :green_heart: | STM32F207ZG | [Nucleo F207ZG](http://www.st.com/en/evaluation-tools/nucleo-f207zg.html) | *0.2.0* | | +| :yellow_heart: | STM32F412ZG | [Nucleo F412ZG](http://www.st.com/en/evaluation-tools/nucleo-f412zg.html) | **2.6.0** | | | :green_heart: | STM32F429ZI | [Nucleo F429ZI](http://www.st.com/en/evaluation-tools/nucleo-f429zi.html) | *0.1.0* | | | :green_heart: | STM32F722ZE | [Nucleo F722ZE](http://www.st.com/en/evaluation-tools/nucleo-f722ze.html) | *2.4.0* | | | :green_heart: | STM32F767ZI | [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) | *1.4.0* | | diff --git a/boards.txt b/boards.txt index da41e14081..ef45ddf37f 100644 --- a/boards.txt +++ b/boards.txt @@ -37,6 +37,20 @@ Nucleo_144.menu.pnum.NUCLEO_F207ZG.build.variant=STM32F2xx/F207Z(C-E-F-G)T_F217Z Nucleo_144.menu.pnum.NUCLEO_F207ZG.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS Nucleo_144.menu.pnum.NUCLEO_F207ZG.build.cmsis_lib_gcc=arm_cortexM3l_math +# NUCLEO_F412ZG board +Nucleo_144.menu.pnum.NUCLEO_F412ZG=Nucleo F412ZG +Nucleo_144.menu.pnum.NUCLEO_F412ZG.node=NODE_F412ZG +Nucleo_144.menu.pnum.NUCLEO_F412ZG.upload.maximum_size=1048576 +Nucleo_144.menu.pnum.NUCLEO_F412ZG.upload.maximum_data_size=262144 +Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.mcu=cortex-m4 +Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.fpu=-mfpu=fpv4-sp-d16 +Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.float-abi=-mfloat-abi=hard +Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.board=NUCLEO_F412ZG +Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.series=STM32F4xx +Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.product_line=STM32F412Zx +Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.variant=STM32F4xx/F412Z(E-G)(J-T) +Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.cmsis_lib_gcc=arm_cortexM4lf_math + # NUCLEO_F413ZH board Nucleo_144.menu.pnum.NUCLEO_F413ZH=Nucleo F413ZH Nucleo_144.menu.pnum.NUCLEO_F413ZH.node=NODE_F413ZH diff --git a/variants/STM32F4xx/F412Z(E-G)(J-T)/variant_NUCLEO_F412ZG.cpp b/variants/STM32F4xx/F412Z(E-G)(J-T)/variant_NUCLEO_F412ZG.cpp new file mode 100644 index 0000000000..ba691fc5f8 --- /dev/null +++ b/variants/STM32F4xx/F412Z(E-G)(J-T)/variant_NUCLEO_F412ZG.cpp @@ -0,0 +1,222 @@ +/* + ******************************************************************************* + * Copyright (c) 2023, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_NUCLEO_F412ZG) +#include "pins_arduino.h" + +// Digital PinName array +// This array allows to wrap Arduino pin number(Dx or x) +// to STM32 PinName (PX_n) +const PinName digitalPin[] = { + PG_9, //D0 + PG_14, //D1 + PF_15, //D2 + PE_13, //D3 + PF_14, //D4 + PE_11, //D5 + PE_9, //D6 + PF_13, //D7 + PF_12, //D8 + PD_15, //D9 + PD_14, //D10 + PA_7, //D11/A10 + PA_6, //D12/A11 + PA_5, //D13/A12 + PB_9, //D14 + PB_8, //D15 + PC_6, //D16 + PB_15, //D17 + PB_13, //D18 + PB_12, //D19 + PA_15, //D20 + PC_7, //D21 + PB_5, //D22 + PB_3, //D23 + PA_4, //D24/A13 + PB_4, //D25 + PB_6, //D26 + PB_2, //D27 + PD_13, //D28 + PD_12, //D29 + PD_11, //D30 + PE_2, //D31 + PA_0, //D32/A14 + PB_0, //D33/A15 - LED_GREEN + PE_0, //D34 + PB_11, //D35 + PB_10, //D36 + PE_15, //D37 + PE_14, //D38 + PE_12, //D39 + PE_10, //D40 + PE_7, //D41 + PE_8, //D42 + PC_8, //D43 + PC_9, //D44 + PC_10, //D45 + PC_11, //D46 + PC_12, //D47 + PD_2, //D48 + PG_2, //D49 + PG_3, //D50 + PD_7, //D51 + PD_6, //D52 + PD_5, //D53 + PD_4, //D54 + PD_3, //D55 + PE_2, //D56 + PE_4, //D57 + PE_5, //D58 + PE_6, //D59 + PE_3, //D60 + PF_8, //D61 + PF_7, //D62 + PF_9, //D63 + PG_1, //D64 + PG_0, //D65 + PD_1, //D66 + PD_0, //D67 + PF_0, //D68 + PF_1, //D69 + PF_2, //D70 + PB_7, //D71 - LED_BLUE + PB_14, //D72 - LED_RED + PC_13, //D73 - USER_BTN + PD_9, //D74 - Serial Rx + PD_8, //D75 - Serial Tx + PA_3, //D76/A0 + PC_0, //D77/A1 + PC_3, //D78/A2 + PC_1, //D79/A3 + PC_4, //D80/A4 + PC_5, //D81/A5 + PB_1, //D82/A6 + PC_2, //D83/A7 + PA_2, //D84/A8 + PF_6, //D85 + PA_1, //D86/A9 + PF_4, //D87 + PA_8, //D88 + PA_9, //D89 + PA_10, //D90 + PA_11, //D91 + PA_12, //D92 + PA_13, //D93 + PA_14, //D94 + PF_3, //D95/A20 + PF_5, //D96/A21 + PF_10, //D97/A22 + PC_14, //D98 + PC_15, //D99 + PD_10, //D100 + PE_1, //D101 + PF_11, //D102 + PG_4, //D103 + PG_5, //D104 + PG_6, //D105 + PG_7, //D106 + PG_8, //D107 + PG_10, //D108 + PG_11, //D109 + PG_12, //D110 + PG_13, //D111 + PG_15, //D112 + PH_0, //D113 + PH_1 //D114 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 76, //A0 + 77, //A1 + 78, //A2 + 79, //A3 + 80, //A4 + 81, //A5 + 82, //A6 + 83, //A7 + 84, //A8 + 86, //A9 + 11, //A10 + 12, //A11 + 13, //A12 + 24, //A13 + 32, //A14 + 33 //A15 +}; + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 384; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; + RCC_OscInitStruct.PLL.PLLQ = 8; + RCC_OscInitStruct.PLL.PLLR = 2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; + PeriphClkInitStruct.SdioClockSelection = RCC_SDIOCLKSOURCE_CLK48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif + +#endif /* ARDUINO_NUCLEO_F412ZG */ diff --git a/variants/STM32F4xx/F412Z(E-G)(J-T)/variant_NUCLEO_F412ZG.h b/variants/STM32F4xx/F412Z(E-G)(J-T)/variant_NUCLEO_F412ZG.h new file mode 100644 index 0000000000..0264ae395c --- /dev/null +++ b/variants/STM32F4xx/F412Z(E-G)(J-T)/variant_NUCLEO_F412ZG.h @@ -0,0 +1,257 @@ +/* + ******************************************************************************* + * Copyright (c) 2023, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ + +#define PG9 0 +#define PG14 1 +#define PF15 2 +#define PE13 3 +#define PF14 4 +#define PE11 5 +#define PE9 6 +#define PF13 7 +#define PF12 8 +#define PD15 9 +#define PD14 10 +#define PA7 PIN_A10 +#define PA6 PIN_A11 +#define PA5 PIN_A12 +#define PB9 14 +#define PB8 15 +#define PC6 16 +#define PB15 17 +#define PB13 18 +#define PB12 19 +#define PA15 20 +#define PC7 21 +#define PB5 22 +#define PB3 23 +#define PA4 PIN_A13 +#define PB4 25 +#define PB6 26 +#define PB2 27 +#define PD13 28 +#define PD12 29 +#define PD11 30 +#define PE2 31 +#define PA0 PIN_A14 +#define PB0 PIN_A15 // LED_GREEN +#define PE0 34 +#define PB11 35 +#define PB10 36 +#define PE15 37 +#define PE14 38 +#define PE12 39 +#define PE10 40 +#define PE7 41 +#define PE8 42 +#define PC8 43 +#define PC9 44 +#define PC10 45 +#define PC11 46 +#define PC12 47 +#define PD2 48 +#define PG2 49 +#define PG3 50 +#define PD7 51 +#define PD6 52 +#define PD5 53 +#define PD4 54 +#define PD3 55 +// 56 is PE2 (31) +#define PE4 57 +#define PE5 58 +#define PE6 59 +#define PE3 60 +#define PF8 61 +#define PF7 62 +#define PF9 63 +#define PG1 64 +#define PG0 65 +#define PD1 66 +#define PD0 67 +#define PF0 68 +#define PF1 69 +#define PF2 70 +#define PB7 71 // LED_BLUE +#define PB14 72 // LED_RED +#define PC13 73 // USER_BTN +#define PD9 74 // Serial Rx +#define PD8 75 // Serial Tx +#define PA3 PIN_A0 +#define PC0 PIN_A1 +#define PC3 PIN_A2 +#define PC1 PIN_A3 +#define PC4 PIN_A4 +#define PC5 PIN_A5 +#define PB1 PIN_A6 +#define PC2 PIN_A7 +#define PA2 PIN_A8 +// ST Morpho +#define PF6 85 +#define PA1 PIN_A9 +#define PF4 87 +#define PA8 88 +#define PA9 89 +#define PA10 90 +#define PA11 91 +#define PA12 92 +#define PA13 93 // SWD +#define PA14 94 // SWD +#define PF3 95 +#define PF5 96 +#define PF10 97 +#define PC14 98 +#define PC15 99 +#define PD10 100 +#define PE1 101 +#define PF11 102 +#define PG4 103 +#define PG5 104 +#define PG6 105 +#define PG7 106 +#define PG8 107 +#define PG10 108 +#define PG11 109 +#define PG12 110 +#define PG13 111 +#define PG15 112 +#define PH0 113 // MCO +#define PH1 114 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PE2_ALT1 (PE2 | ALT1) +#define PE4_ALT1 (PE4 | ALT1) +#define PE5_ALT1 (PE5 | ALT1) +#define PE6_ALT1 (PE6 | ALT1) +#define PE11_ALT1 (PE11 | ALT1) +#define PE12_ALT1 (PE12 | ALT1) +#define PE13_ALT1 (PE13 | ALT1) +#define PE14_ALT1 (PE14 | ALT1) + +#define NUM_DIGITAL_PINS 115 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#define LED_GREEN PB0 +#define LED_BLUE PB7 +#define LED_RED PB14 +#ifndef LED_BUILTIN + #define LED_BUILTIN LED_GREEN +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// Timer Definitions (optional) +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 3 +#endif + +// Default pin used for 'Serial' instance (ex: ST-Link) +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PD9 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PD8 +#endif + +/* Extra HAL modules */ +#if !defined(HAL_QSPI_MODULE_DISABLED) + #define HAL_QSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +// HSE default value is 25MHz in HAL +// HSE_BYPASS is 8MHz +#ifndef HSE_BYPASS_NOT_USED + #define HSE_VALUE 8000000 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif